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ath9k: Add btcoex profile management support for AR9462
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / xmit.c
1 /*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/dma-mapping.h>
18 #include "ath9k.h"
19 #include "ar9003_mac.h"
20
21 #define BITS_PER_BYTE 8
22 #define OFDM_PLCP_BITS 22
23 #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
24 #define L_STF 8
25 #define L_LTF 8
26 #define L_SIG 4
27 #define HT_SIG 8
28 #define HT_STF 4
29 #define HT_LTF(_ns) (4 * (_ns))
30 #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */
31 #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */
32 #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
33 #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
34
35
36 static u16 bits_per_symbol[][2] = {
37 /* 20MHz 40MHz */
38 { 26, 54 }, /* 0: BPSK */
39 { 52, 108 }, /* 1: QPSK 1/2 */
40 { 78, 162 }, /* 2: QPSK 3/4 */
41 { 104, 216 }, /* 3: 16-QAM 1/2 */
42 { 156, 324 }, /* 4: 16-QAM 3/4 */
43 { 208, 432 }, /* 5: 64-QAM 2/3 */
44 { 234, 486 }, /* 6: 64-QAM 3/4 */
45 { 260, 540 }, /* 7: 64-QAM 5/6 */
46 };
47
48 #define IS_HT_RATE(_rate) ((_rate) & 0x80)
49
50 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
51 struct ath_atx_tid *tid, struct sk_buff *skb);
52 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
53 int tx_flags, struct ath_txq *txq);
54 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
55 struct ath_txq *txq, struct list_head *bf_q,
56 struct ath_tx_status *ts, int txok, int sendbar);
57 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
58 struct list_head *head, bool internal);
59 static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
60 struct ath_tx_status *ts, int nframes, int nbad,
61 int txok);
62 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
63 int seqno);
64 static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc,
65 struct ath_txq *txq,
66 struct ath_atx_tid *tid,
67 struct sk_buff *skb);
68
69 enum {
70 MCS_HT20,
71 MCS_HT20_SGI,
72 MCS_HT40,
73 MCS_HT40_SGI,
74 };
75
76 static int ath_max_4ms_framelen[4][32] = {
77 [MCS_HT20] = {
78 3212, 6432, 9648, 12864, 19300, 25736, 28952, 32172,
79 6424, 12852, 19280, 25708, 38568, 51424, 57852, 64280,
80 9628, 19260, 28896, 38528, 57792, 65532, 65532, 65532,
81 12828, 25656, 38488, 51320, 65532, 65532, 65532, 65532,
82 },
83 [MCS_HT20_SGI] = {
84 3572, 7144, 10720, 14296, 21444, 28596, 32172, 35744,
85 7140, 14284, 21428, 28568, 42856, 57144, 64288, 65532,
86 10700, 21408, 32112, 42816, 64228, 65532, 65532, 65532,
87 14256, 28516, 42780, 57040, 65532, 65532, 65532, 65532,
88 },
89 [MCS_HT40] = {
90 6680, 13360, 20044, 26724, 40092, 53456, 60140, 65532,
91 13348, 26700, 40052, 53400, 65532, 65532, 65532, 65532,
92 20004, 40008, 60016, 65532, 65532, 65532, 65532, 65532,
93 26644, 53292, 65532, 65532, 65532, 65532, 65532, 65532,
94 },
95 [MCS_HT40_SGI] = {
96 7420, 14844, 22272, 29696, 44544, 59396, 65532, 65532,
97 14832, 29668, 44504, 59340, 65532, 65532, 65532, 65532,
98 22232, 44464, 65532, 65532, 65532, 65532, 65532, 65532,
99 29616, 59232, 65532, 65532, 65532, 65532, 65532, 65532,
100 }
101 };
102
103 /*********************/
104 /* Aggregation logic */
105 /*********************/
106
107 static void ath_tx_queue_tid(struct ath_txq *txq, struct ath_atx_tid *tid)
108 {
109 struct ath_atx_ac *ac = tid->ac;
110
111 if (tid->paused)
112 return;
113
114 if (tid->sched)
115 return;
116
117 tid->sched = true;
118 list_add_tail(&tid->list, &ac->tid_q);
119
120 if (ac->sched)
121 return;
122
123 ac->sched = true;
124 list_add_tail(&ac->list, &txq->axq_acq);
125 }
126
127 static void ath_tx_resume_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
128 {
129 struct ath_txq *txq = tid->ac->txq;
130
131 WARN_ON(!tid->paused);
132
133 spin_lock_bh(&txq->axq_lock);
134 tid->paused = false;
135
136 if (skb_queue_empty(&tid->buf_q))
137 goto unlock;
138
139 ath_tx_queue_tid(txq, tid);
140 ath_txq_schedule(sc, txq);
141 unlock:
142 spin_unlock_bh(&txq->axq_lock);
143 }
144
145 static struct ath_frame_info *get_frame_info(struct sk_buff *skb)
146 {
147 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
148 BUILD_BUG_ON(sizeof(struct ath_frame_info) >
149 sizeof(tx_info->rate_driver_data));
150 return (struct ath_frame_info *) &tx_info->rate_driver_data[0];
151 }
152
153 static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
154 {
155 struct ath_txq *txq = tid->ac->txq;
156 struct sk_buff *skb;
157 struct ath_buf *bf;
158 struct list_head bf_head;
159 struct ath_tx_status ts;
160 struct ath_frame_info *fi;
161
162 INIT_LIST_HEAD(&bf_head);
163
164 memset(&ts, 0, sizeof(ts));
165 spin_lock_bh(&txq->axq_lock);
166
167 while ((skb = __skb_dequeue(&tid->buf_q))) {
168 fi = get_frame_info(skb);
169 bf = fi->bf;
170
171 spin_unlock_bh(&txq->axq_lock);
172 if (bf && fi->retries) {
173 list_add_tail(&bf->list, &bf_head);
174 ath_tx_update_baw(sc, tid, bf->bf_state.seqno);
175 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 1);
176 } else {
177 ath_tx_send_normal(sc, txq, NULL, skb);
178 }
179 spin_lock_bh(&txq->axq_lock);
180 }
181
182 spin_unlock_bh(&txq->axq_lock);
183 }
184
185 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
186 int seqno)
187 {
188 int index, cindex;
189
190 index = ATH_BA_INDEX(tid->seq_start, seqno);
191 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
192
193 __clear_bit(cindex, tid->tx_buf);
194
195 while (tid->baw_head != tid->baw_tail && !test_bit(tid->baw_head, tid->tx_buf)) {
196 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
197 INCR(tid->baw_head, ATH_TID_MAX_BUFS);
198 }
199 }
200
201 static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
202 u16 seqno)
203 {
204 int index, cindex;
205
206 index = ATH_BA_INDEX(tid->seq_start, seqno);
207 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
208 __set_bit(cindex, tid->tx_buf);
209
210 if (index >= ((tid->baw_tail - tid->baw_head) &
211 (ATH_TID_MAX_BUFS - 1))) {
212 tid->baw_tail = cindex;
213 INCR(tid->baw_tail, ATH_TID_MAX_BUFS);
214 }
215 }
216
217 /*
218 * TODO: For frame(s) that are in the retry state, we will reuse the
219 * sequence number(s) without setting the retry bit. The
220 * alternative is to give up on these and BAR the receiver's window
221 * forward.
222 */
223 static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq,
224 struct ath_atx_tid *tid)
225
226 {
227 struct sk_buff *skb;
228 struct ath_buf *bf;
229 struct list_head bf_head;
230 struct ath_tx_status ts;
231 struct ath_frame_info *fi;
232
233 memset(&ts, 0, sizeof(ts));
234 INIT_LIST_HEAD(&bf_head);
235
236 while ((skb = __skb_dequeue(&tid->buf_q))) {
237 fi = get_frame_info(skb);
238 bf = fi->bf;
239
240 if (!bf) {
241 spin_unlock(&txq->axq_lock);
242 ath_tx_complete(sc, skb, ATH_TX_ERROR, txq);
243 spin_lock(&txq->axq_lock);
244 continue;
245 }
246
247 list_add_tail(&bf->list, &bf_head);
248
249 if (fi->retries)
250 ath_tx_update_baw(sc, tid, bf->bf_state.seqno);
251
252 spin_unlock(&txq->axq_lock);
253 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 0);
254 spin_lock(&txq->axq_lock);
255 }
256
257 tid->seq_next = tid->seq_start;
258 tid->baw_tail = tid->baw_head;
259 }
260
261 static void ath_tx_set_retry(struct ath_softc *sc, struct ath_txq *txq,
262 struct sk_buff *skb)
263 {
264 struct ath_frame_info *fi = get_frame_info(skb);
265 struct ath_buf *bf = fi->bf;
266 struct ieee80211_hdr *hdr;
267
268 TX_STAT_INC(txq->axq_qnum, a_retries);
269 if (fi->retries++ > 0)
270 return;
271
272 hdr = (struct ieee80211_hdr *)skb->data;
273 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY);
274 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
275 sizeof(*hdr), DMA_TO_DEVICE);
276 }
277
278 static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc)
279 {
280 struct ath_buf *bf = NULL;
281
282 spin_lock_bh(&sc->tx.txbuflock);
283
284 if (unlikely(list_empty(&sc->tx.txbuf))) {
285 spin_unlock_bh(&sc->tx.txbuflock);
286 return NULL;
287 }
288
289 bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list);
290 list_del(&bf->list);
291
292 spin_unlock_bh(&sc->tx.txbuflock);
293
294 return bf;
295 }
296
297 static void ath_tx_return_buffer(struct ath_softc *sc, struct ath_buf *bf)
298 {
299 spin_lock_bh(&sc->tx.txbuflock);
300 list_add_tail(&bf->list, &sc->tx.txbuf);
301 spin_unlock_bh(&sc->tx.txbuflock);
302 }
303
304 static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf)
305 {
306 struct ath_buf *tbf;
307
308 tbf = ath_tx_get_buffer(sc);
309 if (WARN_ON(!tbf))
310 return NULL;
311
312 ATH_TXBUF_RESET(tbf);
313
314 tbf->bf_mpdu = bf->bf_mpdu;
315 tbf->bf_buf_addr = bf->bf_buf_addr;
316 memcpy(tbf->bf_desc, bf->bf_desc, sc->sc_ah->caps.tx_desc_len);
317 tbf->bf_state = bf->bf_state;
318
319 return tbf;
320 }
321
322 static void ath_tx_count_frames(struct ath_softc *sc, struct ath_buf *bf,
323 struct ath_tx_status *ts, int txok,
324 int *nframes, int *nbad)
325 {
326 struct ath_frame_info *fi;
327 u16 seq_st = 0;
328 u32 ba[WME_BA_BMP_SIZE >> 5];
329 int ba_index;
330 int isaggr = 0;
331
332 *nbad = 0;
333 *nframes = 0;
334
335 isaggr = bf_isaggr(bf);
336 if (isaggr) {
337 seq_st = ts->ts_seqnum;
338 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
339 }
340
341 while (bf) {
342 fi = get_frame_info(bf->bf_mpdu);
343 ba_index = ATH_BA_INDEX(seq_st, bf->bf_state.seqno);
344
345 (*nframes)++;
346 if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index)))
347 (*nbad)++;
348
349 bf = bf->bf_next;
350 }
351 }
352
353
354 static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
355 struct ath_buf *bf, struct list_head *bf_q,
356 struct ath_tx_status *ts, int txok, bool retry)
357 {
358 struct ath_node *an = NULL;
359 struct sk_buff *skb;
360 struct ieee80211_sta *sta;
361 struct ieee80211_hw *hw = sc->hw;
362 struct ieee80211_hdr *hdr;
363 struct ieee80211_tx_info *tx_info;
364 struct ath_atx_tid *tid = NULL;
365 struct ath_buf *bf_next, *bf_last = bf->bf_lastbf;
366 struct list_head bf_head;
367 struct sk_buff_head bf_pending;
368 u16 seq_st = 0, acked_cnt = 0, txfail_cnt = 0;
369 u32 ba[WME_BA_BMP_SIZE >> 5];
370 int isaggr, txfail, txpending, sendbar = 0, needreset = 0, nbad = 0;
371 bool rc_update = true;
372 struct ieee80211_tx_rate rates[4];
373 struct ath_frame_info *fi;
374 int nframes;
375 u8 tidno;
376 bool flush = !!(ts->ts_status & ATH9K_TX_FLUSH);
377
378 skb = bf->bf_mpdu;
379 hdr = (struct ieee80211_hdr *)skb->data;
380
381 tx_info = IEEE80211_SKB_CB(skb);
382
383 memcpy(rates, tx_info->control.rates, sizeof(rates));
384
385 rcu_read_lock();
386
387 sta = ieee80211_find_sta_by_ifaddr(hw, hdr->addr1, hdr->addr2);
388 if (!sta) {
389 rcu_read_unlock();
390
391 INIT_LIST_HEAD(&bf_head);
392 while (bf) {
393 bf_next = bf->bf_next;
394
395 if (!bf->bf_stale || bf_next != NULL)
396 list_move_tail(&bf->list, &bf_head);
397
398 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts,
399 0, 0);
400
401 bf = bf_next;
402 }
403 return;
404 }
405
406 an = (struct ath_node *)sta->drv_priv;
407 tidno = ieee80211_get_qos_ctl(hdr)[0] & IEEE80211_QOS_CTL_TID_MASK;
408 tid = ATH_AN_2_TID(an, tidno);
409
410 /*
411 * The hardware occasionally sends a tx status for the wrong TID.
412 * In this case, the BA status cannot be considered valid and all
413 * subframes need to be retransmitted
414 */
415 if (tidno != ts->tid)
416 txok = false;
417
418 isaggr = bf_isaggr(bf);
419 memset(ba, 0, WME_BA_BMP_SIZE >> 3);
420
421 if (isaggr && txok) {
422 if (ts->ts_flags & ATH9K_TX_BA) {
423 seq_st = ts->ts_seqnum;
424 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
425 } else {
426 /*
427 * AR5416 can become deaf/mute when BA
428 * issue happens. Chip needs to be reset.
429 * But AP code may have sychronization issues
430 * when perform internal reset in this routine.
431 * Only enable reset in STA mode for now.
432 */
433 if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION)
434 needreset = 1;
435 }
436 }
437
438 __skb_queue_head_init(&bf_pending);
439
440 ath_tx_count_frames(sc, bf, ts, txok, &nframes, &nbad);
441 while (bf) {
442 u16 seqno = bf->bf_state.seqno;
443
444 txfail = txpending = sendbar = 0;
445 bf_next = bf->bf_next;
446
447 skb = bf->bf_mpdu;
448 tx_info = IEEE80211_SKB_CB(skb);
449 fi = get_frame_info(skb);
450
451 if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, seqno))) {
452 /* transmit completion, subframe is
453 * acked by block ack */
454 acked_cnt++;
455 } else if (!isaggr && txok) {
456 /* transmit completion */
457 acked_cnt++;
458 } else {
459 if ((tid->state & AGGR_CLEANUP) || !retry) {
460 /*
461 * cleanup in progress, just fail
462 * the un-acked sub-frames
463 */
464 txfail = 1;
465 } else if (flush) {
466 txpending = 1;
467 } else if (fi->retries < ATH_MAX_SW_RETRIES) {
468 if (txok || !an->sleeping)
469 ath_tx_set_retry(sc, txq, bf->bf_mpdu);
470
471 txpending = 1;
472 } else {
473 txfail = 1;
474 sendbar = 1;
475 txfail_cnt++;
476 }
477 }
478
479 /*
480 * Make sure the last desc is reclaimed if it
481 * not a holding desc.
482 */
483 INIT_LIST_HEAD(&bf_head);
484 if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) ||
485 bf_next != NULL || !bf_last->bf_stale)
486 list_move_tail(&bf->list, &bf_head);
487
488 if (!txpending || (tid->state & AGGR_CLEANUP)) {
489 /*
490 * complete the acked-ones/xretried ones; update
491 * block-ack window
492 */
493 spin_lock_bh(&txq->axq_lock);
494 ath_tx_update_baw(sc, tid, seqno);
495 spin_unlock_bh(&txq->axq_lock);
496
497 if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) {
498 memcpy(tx_info->control.rates, rates, sizeof(rates));
499 ath_tx_rc_status(sc, bf, ts, nframes, nbad, txok);
500 rc_update = false;
501 }
502
503 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts,
504 !txfail, sendbar);
505 } else {
506 /* retry the un-acked ones */
507 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)) {
508 if (bf->bf_next == NULL && bf_last->bf_stale) {
509 struct ath_buf *tbf;
510
511 tbf = ath_clone_txbuf(sc, bf_last);
512 /*
513 * Update tx baw and complete the
514 * frame with failed status if we
515 * run out of tx buf.
516 */
517 if (!tbf) {
518 spin_lock_bh(&txq->axq_lock);
519 ath_tx_update_baw(sc, tid, seqno);
520 spin_unlock_bh(&txq->axq_lock);
521
522 ath_tx_complete_buf(sc, bf, txq,
523 &bf_head,
524 ts, 0,
525 !flush);
526 break;
527 }
528
529 fi->bf = tbf;
530 }
531 }
532
533 /*
534 * Put this buffer to the temporary pending
535 * queue to retain ordering
536 */
537 __skb_queue_tail(&bf_pending, skb);
538 }
539
540 bf = bf_next;
541 }
542
543 /* prepend un-acked frames to the beginning of the pending frame queue */
544 if (!skb_queue_empty(&bf_pending)) {
545 if (an->sleeping)
546 ieee80211_sta_set_buffered(sta, tid->tidno, true);
547
548 spin_lock_bh(&txq->axq_lock);
549 skb_queue_splice(&bf_pending, &tid->buf_q);
550 if (!an->sleeping) {
551 ath_tx_queue_tid(txq, tid);
552
553 if (ts->ts_status & ATH9K_TXERR_FILT)
554 tid->ac->clear_ps_filter = true;
555 }
556 spin_unlock_bh(&txq->axq_lock);
557 }
558
559 if (tid->state & AGGR_CLEANUP) {
560 ath_tx_flush_tid(sc, tid);
561
562 if (tid->baw_head == tid->baw_tail) {
563 tid->state &= ~AGGR_ADDBA_COMPLETE;
564 tid->state &= ~AGGR_CLEANUP;
565 }
566 }
567
568 rcu_read_unlock();
569
570 if (needreset) {
571 RESET_STAT_INC(sc, RESET_TYPE_TX_ERROR);
572 ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
573 }
574 }
575
576 static bool ath_lookup_legacy(struct ath_buf *bf)
577 {
578 struct sk_buff *skb;
579 struct ieee80211_tx_info *tx_info;
580 struct ieee80211_tx_rate *rates;
581 int i;
582
583 skb = bf->bf_mpdu;
584 tx_info = IEEE80211_SKB_CB(skb);
585 rates = tx_info->control.rates;
586
587 for (i = 0; i < 4; i++) {
588 if (!rates[i].count || rates[i].idx < 0)
589 break;
590
591 if (!(rates[i].flags & IEEE80211_TX_RC_MCS))
592 return true;
593 }
594
595 return false;
596 }
597
598 static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf,
599 struct ath_atx_tid *tid)
600 {
601 struct sk_buff *skb;
602 struct ieee80211_tx_info *tx_info;
603 struct ieee80211_tx_rate *rates;
604 struct ath_mci_profile *mci = &sc->btcoex.mci;
605 u32 max_4ms_framelen, frmlen;
606 u16 aggr_limit, legacy = 0;
607 int i;
608
609 skb = bf->bf_mpdu;
610 tx_info = IEEE80211_SKB_CB(skb);
611 rates = tx_info->control.rates;
612
613 /*
614 * Find the lowest frame length among the rate series that will have a
615 * 4ms transmit duration.
616 * TODO - TXOP limit needs to be considered.
617 */
618 max_4ms_framelen = ATH_AMPDU_LIMIT_MAX;
619
620 for (i = 0; i < 4; i++) {
621 if (rates[i].count) {
622 int modeidx;
623 if (!(rates[i].flags & IEEE80211_TX_RC_MCS)) {
624 legacy = 1;
625 break;
626 }
627
628 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
629 modeidx = MCS_HT40;
630 else
631 modeidx = MCS_HT20;
632
633 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
634 modeidx++;
635
636 frmlen = ath_max_4ms_framelen[modeidx][rates[i].idx];
637 max_4ms_framelen = min(max_4ms_framelen, frmlen);
638 }
639 }
640
641 /*
642 * limit aggregate size by the minimum rate if rate selected is
643 * not a probe rate, if rate selected is a probe rate then
644 * avoid aggregation of this packet.
645 */
646 if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy)
647 return 0;
648
649 if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_MCI) && mci->aggr_limit)
650 aggr_limit = (max_4ms_framelen * mci->aggr_limit) >> 4;
651 else if (sc->sc_flags & SC_OP_BT_PRIORITY_DETECTED)
652 aggr_limit = min((max_4ms_framelen * 3) / 8,
653 (u32)ATH_AMPDU_LIMIT_MAX);
654 else
655 aggr_limit = min(max_4ms_framelen,
656 (u32)ATH_AMPDU_LIMIT_MAX);
657
658 /*
659 * h/w can accept aggregates up to 16 bit lengths (65535).
660 * The IE, however can hold up to 65536, which shows up here
661 * as zero. Ignore 65536 since we are constrained by hw.
662 */
663 if (tid->an->maxampdu)
664 aggr_limit = min(aggr_limit, tid->an->maxampdu);
665
666 return aggr_limit;
667 }
668
669 /*
670 * Returns the number of delimiters to be added to
671 * meet the minimum required mpdudensity.
672 */
673 static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid,
674 struct ath_buf *bf, u16 frmlen,
675 bool first_subfrm)
676 {
677 #define FIRST_DESC_NDELIMS 60
678 struct sk_buff *skb = bf->bf_mpdu;
679 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
680 u32 nsymbits, nsymbols;
681 u16 minlen;
682 u8 flags, rix;
683 int width, streams, half_gi, ndelim, mindelim;
684 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
685
686 /* Select standard number of delimiters based on frame length alone */
687 ndelim = ATH_AGGR_GET_NDELIM(frmlen);
688
689 /*
690 * If encryption enabled, hardware requires some more padding between
691 * subframes.
692 * TODO - this could be improved to be dependent on the rate.
693 * The hardware can keep up at lower rates, but not higher rates
694 */
695 if ((fi->keyix != ATH9K_TXKEYIX_INVALID) &&
696 !(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA))
697 ndelim += ATH_AGGR_ENCRYPTDELIM;
698
699 /*
700 * Add delimiter when using RTS/CTS with aggregation
701 * and non enterprise AR9003 card
702 */
703 if (first_subfrm && !AR_SREV_9580_10_OR_LATER(sc->sc_ah) &&
704 (sc->sc_ah->ent_mode & AR_ENT_OTP_MIN_PKT_SIZE_DISABLE))
705 ndelim = max(ndelim, FIRST_DESC_NDELIMS);
706
707 /*
708 * Convert desired mpdu density from microeconds to bytes based
709 * on highest rate in rate series (i.e. first rate) to determine
710 * required minimum length for subframe. Take into account
711 * whether high rate is 20 or 40Mhz and half or full GI.
712 *
713 * If there is no mpdu density restriction, no further calculation
714 * is needed.
715 */
716
717 if (tid->an->mpdudensity == 0)
718 return ndelim;
719
720 rix = tx_info->control.rates[0].idx;
721 flags = tx_info->control.rates[0].flags;
722 width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0;
723 half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0;
724
725 if (half_gi)
726 nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(tid->an->mpdudensity);
727 else
728 nsymbols = NUM_SYMBOLS_PER_USEC(tid->an->mpdudensity);
729
730 if (nsymbols == 0)
731 nsymbols = 1;
732
733 streams = HT_RC_2_STREAMS(rix);
734 nsymbits = bits_per_symbol[rix % 8][width] * streams;
735 minlen = (nsymbols * nsymbits) / BITS_PER_BYTE;
736
737 if (frmlen < minlen) {
738 mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ;
739 ndelim = max(mindelim, ndelim);
740 }
741
742 return ndelim;
743 }
744
745 static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc,
746 struct ath_txq *txq,
747 struct ath_atx_tid *tid,
748 struct list_head *bf_q,
749 int *aggr_len)
750 {
751 #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
752 struct ath_buf *bf, *bf_first = NULL, *bf_prev = NULL;
753 int rl = 0, nframes = 0, ndelim, prev_al = 0;
754 u16 aggr_limit = 0, al = 0, bpad = 0,
755 al_delta, h_baw = tid->baw_size / 2;
756 enum ATH_AGGR_STATUS status = ATH_AGGR_DONE;
757 struct ieee80211_tx_info *tx_info;
758 struct ath_frame_info *fi;
759 struct sk_buff *skb;
760 u16 seqno;
761
762 do {
763 skb = skb_peek(&tid->buf_q);
764 fi = get_frame_info(skb);
765 bf = fi->bf;
766 if (!fi->bf)
767 bf = ath_tx_setup_buffer(sc, txq, tid, skb);
768
769 if (!bf)
770 continue;
771
772 bf->bf_state.bf_type = BUF_AMPDU | BUF_AGGR;
773 seqno = bf->bf_state.seqno;
774 if (!bf_first)
775 bf_first = bf;
776
777 /* do not step over block-ack window */
778 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno)) {
779 status = ATH_AGGR_BAW_CLOSED;
780 break;
781 }
782
783 if (!rl) {
784 aggr_limit = ath_lookup_rate(sc, bf, tid);
785 rl = 1;
786 }
787
788 /* do not exceed aggregation limit */
789 al_delta = ATH_AGGR_DELIM_SZ + fi->framelen;
790
791 if (nframes &&
792 ((aggr_limit < (al + bpad + al_delta + prev_al)) ||
793 ath_lookup_legacy(bf))) {
794 status = ATH_AGGR_LIMITED;
795 break;
796 }
797
798 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
799 if (nframes && (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE))
800 break;
801
802 /* do not exceed subframe limit */
803 if (nframes >= min((int)h_baw, ATH_AMPDU_SUBFRAME_DEFAULT)) {
804 status = ATH_AGGR_LIMITED;
805 break;
806 }
807
808 /* add padding for previous frame to aggregation length */
809 al += bpad + al_delta;
810
811 /*
812 * Get the delimiters needed to meet the MPDU
813 * density for this node.
814 */
815 ndelim = ath_compute_num_delims(sc, tid, bf_first, fi->framelen,
816 !nframes);
817 bpad = PADBYTES(al_delta) + (ndelim << 2);
818
819 nframes++;
820 bf->bf_next = NULL;
821
822 /* link buffers of this frame to the aggregate */
823 if (!fi->retries)
824 ath_tx_addto_baw(sc, tid, seqno);
825 bf->bf_state.ndelim = ndelim;
826
827 __skb_unlink(skb, &tid->buf_q);
828 list_add_tail(&bf->list, bf_q);
829 if (bf_prev)
830 bf_prev->bf_next = bf;
831
832 bf_prev = bf;
833
834 } while (!skb_queue_empty(&tid->buf_q));
835
836 *aggr_len = al;
837
838 return status;
839 #undef PADBYTES
840 }
841
842 /*
843 * rix - rate index
844 * pktlen - total bytes (delims + data + fcs + pads + pad delims)
845 * width - 0 for 20 MHz, 1 for 40 MHz
846 * half_gi - to use 4us v/s 3.6 us for symbol time
847 */
848 static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, int pktlen,
849 int width, int half_gi, bool shortPreamble)
850 {
851 u32 nbits, nsymbits, duration, nsymbols;
852 int streams;
853
854 /* find number of symbols: PLCP + data */
855 streams = HT_RC_2_STREAMS(rix);
856 nbits = (pktlen << 3) + OFDM_PLCP_BITS;
857 nsymbits = bits_per_symbol[rix % 8][width] * streams;
858 nsymbols = (nbits + nsymbits - 1) / nsymbits;
859
860 if (!half_gi)
861 duration = SYMBOL_TIME(nsymbols);
862 else
863 duration = SYMBOL_TIME_HALFGI(nsymbols);
864
865 /* addup duration for legacy/ht training and signal fields */
866 duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
867
868 return duration;
869 }
870
871 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf,
872 struct ath_tx_info *info, int len)
873 {
874 struct ath_hw *ah = sc->sc_ah;
875 struct sk_buff *skb;
876 struct ieee80211_tx_info *tx_info;
877 struct ieee80211_tx_rate *rates;
878 const struct ieee80211_rate *rate;
879 struct ieee80211_hdr *hdr;
880 int i;
881 u8 rix = 0;
882
883 skb = bf->bf_mpdu;
884 tx_info = IEEE80211_SKB_CB(skb);
885 rates = tx_info->control.rates;
886 hdr = (struct ieee80211_hdr *)skb->data;
887
888 /* set dur_update_en for l-sig computation except for PS-Poll frames */
889 info->dur_update = !ieee80211_is_pspoll(hdr->frame_control);
890
891 /*
892 * We check if Short Preamble is needed for the CTS rate by
893 * checking the BSS's global flag.
894 * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used.
895 */
896 rate = ieee80211_get_rts_cts_rate(sc->hw, tx_info);
897 info->rtscts_rate = rate->hw_value;
898 if (sc->sc_flags & SC_OP_PREAMBLE_SHORT)
899 info->rtscts_rate |= rate->hw_value_short;
900
901 for (i = 0; i < 4; i++) {
902 bool is_40, is_sgi, is_sp;
903 int phy;
904
905 if (!rates[i].count || (rates[i].idx < 0))
906 continue;
907
908 rix = rates[i].idx;
909 info->rates[i].Tries = rates[i].count;
910
911 if (rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS) {
912 info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
913 info->flags |= ATH9K_TXDESC_RTSENA;
914 } else if (rates[i].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
915 info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
916 info->flags |= ATH9K_TXDESC_CTSENA;
917 }
918
919 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
920 info->rates[i].RateFlags |= ATH9K_RATESERIES_2040;
921 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
922 info->rates[i].RateFlags |= ATH9K_RATESERIES_HALFGI;
923
924 is_sgi = !!(rates[i].flags & IEEE80211_TX_RC_SHORT_GI);
925 is_40 = !!(rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH);
926 is_sp = !!(rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE);
927
928 if (rates[i].flags & IEEE80211_TX_RC_MCS) {
929 /* MCS rates */
930 info->rates[i].Rate = rix | 0x80;
931 info->rates[i].ChSel = ath_txchainmask_reduction(sc,
932 ah->txchainmask, info->rates[i].Rate);
933 info->rates[i].PktDuration = ath_pkt_duration(sc, rix, len,
934 is_40, is_sgi, is_sp);
935 if (rix < 8 && (tx_info->flags & IEEE80211_TX_CTL_STBC))
936 info->rates[i].RateFlags |= ATH9K_RATESERIES_STBC;
937 continue;
938 }
939
940 /* legacy rates */
941 if ((tx_info->band == IEEE80211_BAND_2GHZ) &&
942 !(rate->flags & IEEE80211_RATE_ERP_G))
943 phy = WLAN_RC_PHY_CCK;
944 else
945 phy = WLAN_RC_PHY_OFDM;
946
947 rate = &sc->sbands[tx_info->band].bitrates[rates[i].idx];
948 info->rates[i].Rate = rate->hw_value;
949 if (rate->hw_value_short) {
950 if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
951 info->rates[i].Rate |= rate->hw_value_short;
952 } else {
953 is_sp = false;
954 }
955
956 if (bf->bf_state.bfs_paprd)
957 info->rates[i].ChSel = ah->txchainmask;
958 else
959 info->rates[i].ChSel = ath_txchainmask_reduction(sc,
960 ah->txchainmask, info->rates[i].Rate);
961
962 info->rates[i].PktDuration = ath9k_hw_computetxtime(sc->sc_ah,
963 phy, rate->bitrate * 100, len, rix, is_sp);
964 }
965
966 /* For AR5416 - RTS cannot be followed by a frame larger than 8K */
967 if (bf_isaggr(bf) && (len > sc->sc_ah->caps.rts_aggr_limit))
968 info->flags &= ~ATH9K_TXDESC_RTSENA;
969
970 /* ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive. */
971 if (info->flags & ATH9K_TXDESC_RTSENA)
972 info->flags &= ~ATH9K_TXDESC_CTSENA;
973 }
974
975 static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb)
976 {
977 struct ieee80211_hdr *hdr;
978 enum ath9k_pkt_type htype;
979 __le16 fc;
980
981 hdr = (struct ieee80211_hdr *)skb->data;
982 fc = hdr->frame_control;
983
984 if (ieee80211_is_beacon(fc))
985 htype = ATH9K_PKT_TYPE_BEACON;
986 else if (ieee80211_is_probe_resp(fc))
987 htype = ATH9K_PKT_TYPE_PROBE_RESP;
988 else if (ieee80211_is_atim(fc))
989 htype = ATH9K_PKT_TYPE_ATIM;
990 else if (ieee80211_is_pspoll(fc))
991 htype = ATH9K_PKT_TYPE_PSPOLL;
992 else
993 htype = ATH9K_PKT_TYPE_NORMAL;
994
995 return htype;
996 }
997
998 static void ath_tx_fill_desc(struct ath_softc *sc, struct ath_buf *bf,
999 struct ath_txq *txq, int len)
1000 {
1001 struct ath_hw *ah = sc->sc_ah;
1002 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
1003 struct ath_buf *bf_first = bf;
1004 struct ath_tx_info info;
1005 bool aggr = !!(bf->bf_state.bf_type & BUF_AGGR);
1006
1007 memset(&info, 0, sizeof(info));
1008 info.is_first = true;
1009 info.is_last = true;
1010 info.txpower = MAX_RATE_POWER;
1011 info.qcu = txq->axq_qnum;
1012
1013 info.flags = ATH9K_TXDESC_INTREQ;
1014 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
1015 info.flags |= ATH9K_TXDESC_NOACK;
1016 if (tx_info->flags & IEEE80211_TX_CTL_LDPC)
1017 info.flags |= ATH9K_TXDESC_LDPC;
1018
1019 ath_buf_set_rate(sc, bf, &info, len);
1020
1021 if (tx_info->flags & IEEE80211_TX_CTL_CLEAR_PS_FILT)
1022 info.flags |= ATH9K_TXDESC_CLRDMASK;
1023
1024 if (bf->bf_state.bfs_paprd)
1025 info.flags |= (u32) bf->bf_state.bfs_paprd << ATH9K_TXDESC_PAPRD_S;
1026
1027
1028 while (bf) {
1029 struct sk_buff *skb = bf->bf_mpdu;
1030 struct ath_frame_info *fi = get_frame_info(skb);
1031
1032 info.type = get_hw_packet_type(skb);
1033 if (bf->bf_next)
1034 info.link = bf->bf_next->bf_daddr;
1035 else
1036 info.link = 0;
1037
1038 info.buf_addr[0] = bf->bf_buf_addr;
1039 info.buf_len[0] = skb->len;
1040 info.pkt_len = fi->framelen;
1041 info.keyix = fi->keyix;
1042 info.keytype = fi->keytype;
1043
1044 if (aggr) {
1045 if (bf == bf_first)
1046 info.aggr = AGGR_BUF_FIRST;
1047 else if (!bf->bf_next)
1048 info.aggr = AGGR_BUF_LAST;
1049 else
1050 info.aggr = AGGR_BUF_MIDDLE;
1051
1052 info.ndelim = bf->bf_state.ndelim;
1053 info.aggr_len = len;
1054 }
1055
1056 ath9k_hw_set_txdesc(ah, bf->bf_desc, &info);
1057 bf = bf->bf_next;
1058 }
1059 }
1060
1061 static void ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq,
1062 struct ath_atx_tid *tid)
1063 {
1064 struct ath_buf *bf;
1065 enum ATH_AGGR_STATUS status;
1066 struct ieee80211_tx_info *tx_info;
1067 struct list_head bf_q;
1068 int aggr_len;
1069
1070 do {
1071 if (skb_queue_empty(&tid->buf_q))
1072 return;
1073
1074 INIT_LIST_HEAD(&bf_q);
1075
1076 status = ath_tx_form_aggr(sc, txq, tid, &bf_q, &aggr_len);
1077
1078 /*
1079 * no frames picked up to be aggregated;
1080 * block-ack window is not open.
1081 */
1082 if (list_empty(&bf_q))
1083 break;
1084
1085 bf = list_first_entry(&bf_q, struct ath_buf, list);
1086 bf->bf_lastbf = list_entry(bf_q.prev, struct ath_buf, list);
1087 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
1088
1089 if (tid->ac->clear_ps_filter) {
1090 tid->ac->clear_ps_filter = false;
1091 tx_info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT;
1092 } else {
1093 tx_info->flags &= ~IEEE80211_TX_CTL_CLEAR_PS_FILT;
1094 }
1095
1096 /* if only one frame, send as non-aggregate */
1097 if (bf == bf->bf_lastbf) {
1098 aggr_len = get_frame_info(bf->bf_mpdu)->framelen;
1099 bf->bf_state.bf_type = BUF_AMPDU;
1100 } else {
1101 TX_STAT_INC(txq->axq_qnum, a_aggr);
1102 }
1103
1104 ath_tx_fill_desc(sc, bf, txq, aggr_len);
1105 ath_tx_txqaddbuf(sc, txq, &bf_q, false);
1106 } while (txq->axq_ampdu_depth < ATH_AGGR_MIN_QDEPTH &&
1107 status != ATH_AGGR_BAW_CLOSED);
1108 }
1109
1110 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
1111 u16 tid, u16 *ssn)
1112 {
1113 struct ath_atx_tid *txtid;
1114 struct ath_node *an;
1115
1116 an = (struct ath_node *)sta->drv_priv;
1117 txtid = ATH_AN_2_TID(an, tid);
1118
1119 if (txtid->state & (AGGR_CLEANUP | AGGR_ADDBA_COMPLETE))
1120 return -EAGAIN;
1121
1122 txtid->state |= AGGR_ADDBA_PROGRESS;
1123 txtid->paused = true;
1124 *ssn = txtid->seq_start = txtid->seq_next;
1125
1126 memset(txtid->tx_buf, 0, sizeof(txtid->tx_buf));
1127 txtid->baw_head = txtid->baw_tail = 0;
1128
1129 return 0;
1130 }
1131
1132 void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
1133 {
1134 struct ath_node *an = (struct ath_node *)sta->drv_priv;
1135 struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid);
1136 struct ath_txq *txq = txtid->ac->txq;
1137
1138 if (txtid->state & AGGR_CLEANUP)
1139 return;
1140
1141 if (!(txtid->state & AGGR_ADDBA_COMPLETE)) {
1142 txtid->state &= ~AGGR_ADDBA_PROGRESS;
1143 return;
1144 }
1145
1146 spin_lock_bh(&txq->axq_lock);
1147 txtid->paused = true;
1148
1149 /*
1150 * If frames are still being transmitted for this TID, they will be
1151 * cleaned up during tx completion. To prevent race conditions, this
1152 * TID can only be reused after all in-progress subframes have been
1153 * completed.
1154 */
1155 if (txtid->baw_head != txtid->baw_tail)
1156 txtid->state |= AGGR_CLEANUP;
1157 else
1158 txtid->state &= ~AGGR_ADDBA_COMPLETE;
1159 spin_unlock_bh(&txq->axq_lock);
1160
1161 ath_tx_flush_tid(sc, txtid);
1162 }
1163
1164 void ath_tx_aggr_sleep(struct ieee80211_sta *sta, struct ath_softc *sc,
1165 struct ath_node *an)
1166 {
1167 struct ath_atx_tid *tid;
1168 struct ath_atx_ac *ac;
1169 struct ath_txq *txq;
1170 bool buffered;
1171 int tidno;
1172
1173 for (tidno = 0, tid = &an->tid[tidno];
1174 tidno < WME_NUM_TID; tidno++, tid++) {
1175
1176 if (!tid->sched)
1177 continue;
1178
1179 ac = tid->ac;
1180 txq = ac->txq;
1181
1182 spin_lock_bh(&txq->axq_lock);
1183
1184 buffered = !skb_queue_empty(&tid->buf_q);
1185
1186 tid->sched = false;
1187 list_del(&tid->list);
1188
1189 if (ac->sched) {
1190 ac->sched = false;
1191 list_del(&ac->list);
1192 }
1193
1194 spin_unlock_bh(&txq->axq_lock);
1195
1196 ieee80211_sta_set_buffered(sta, tidno, buffered);
1197 }
1198 }
1199
1200 void ath_tx_aggr_wakeup(struct ath_softc *sc, struct ath_node *an)
1201 {
1202 struct ath_atx_tid *tid;
1203 struct ath_atx_ac *ac;
1204 struct ath_txq *txq;
1205 int tidno;
1206
1207 for (tidno = 0, tid = &an->tid[tidno];
1208 tidno < WME_NUM_TID; tidno++, tid++) {
1209
1210 ac = tid->ac;
1211 txq = ac->txq;
1212
1213 spin_lock_bh(&txq->axq_lock);
1214 ac->clear_ps_filter = true;
1215
1216 if (!skb_queue_empty(&tid->buf_q) && !tid->paused) {
1217 ath_tx_queue_tid(txq, tid);
1218 ath_txq_schedule(sc, txq);
1219 }
1220
1221 spin_unlock_bh(&txq->axq_lock);
1222 }
1223 }
1224
1225 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
1226 {
1227 struct ath_atx_tid *txtid;
1228 struct ath_node *an;
1229
1230 an = (struct ath_node *)sta->drv_priv;
1231
1232 if (sc->sc_flags & SC_OP_TXAGGR) {
1233 txtid = ATH_AN_2_TID(an, tid);
1234 txtid->baw_size =
1235 IEEE80211_MIN_AMPDU_BUF << sta->ht_cap.ampdu_factor;
1236 txtid->state |= AGGR_ADDBA_COMPLETE;
1237 txtid->state &= ~AGGR_ADDBA_PROGRESS;
1238 ath_tx_resume_tid(sc, txtid);
1239 }
1240 }
1241
1242 /********************/
1243 /* Queue Management */
1244 /********************/
1245
1246 static void ath_txq_drain_pending_buffers(struct ath_softc *sc,
1247 struct ath_txq *txq)
1248 {
1249 struct ath_atx_ac *ac, *ac_tmp;
1250 struct ath_atx_tid *tid, *tid_tmp;
1251
1252 list_for_each_entry_safe(ac, ac_tmp, &txq->axq_acq, list) {
1253 list_del(&ac->list);
1254 ac->sched = false;
1255 list_for_each_entry_safe(tid, tid_tmp, &ac->tid_q, list) {
1256 list_del(&tid->list);
1257 tid->sched = false;
1258 ath_tid_drain(sc, txq, tid);
1259 }
1260 }
1261 }
1262
1263 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
1264 {
1265 struct ath_hw *ah = sc->sc_ah;
1266 struct ath9k_tx_queue_info qi;
1267 static const int subtype_txq_to_hwq[] = {
1268 [WME_AC_BE] = ATH_TXQ_AC_BE,
1269 [WME_AC_BK] = ATH_TXQ_AC_BK,
1270 [WME_AC_VI] = ATH_TXQ_AC_VI,
1271 [WME_AC_VO] = ATH_TXQ_AC_VO,
1272 };
1273 int axq_qnum, i;
1274
1275 memset(&qi, 0, sizeof(qi));
1276 qi.tqi_subtype = subtype_txq_to_hwq[subtype];
1277 qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT;
1278 qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
1279 qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT;
1280 qi.tqi_physCompBuf = 0;
1281
1282 /*
1283 * Enable interrupts only for EOL and DESC conditions.
1284 * We mark tx descriptors to receive a DESC interrupt
1285 * when a tx queue gets deep; otherwise waiting for the
1286 * EOL to reap descriptors. Note that this is done to
1287 * reduce interrupt load and this only defers reaping
1288 * descriptors, never transmitting frames. Aside from
1289 * reducing interrupts this also permits more concurrency.
1290 * The only potential downside is if the tx queue backs
1291 * up in which case the top half of the kernel may backup
1292 * due to a lack of tx descriptors.
1293 *
1294 * The UAPSD queue is an exception, since we take a desc-
1295 * based intr on the EOSP frames.
1296 */
1297 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1298 qi.tqi_qflags = TXQ_FLAG_TXOKINT_ENABLE |
1299 TXQ_FLAG_TXERRINT_ENABLE;
1300 } else {
1301 if (qtype == ATH9K_TX_QUEUE_UAPSD)
1302 qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE;
1303 else
1304 qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE |
1305 TXQ_FLAG_TXDESCINT_ENABLE;
1306 }
1307 axq_qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi);
1308 if (axq_qnum == -1) {
1309 /*
1310 * NB: don't print a message, this happens
1311 * normally on parts with too few tx queues
1312 */
1313 return NULL;
1314 }
1315 if (!ATH_TXQ_SETUP(sc, axq_qnum)) {
1316 struct ath_txq *txq = &sc->tx.txq[axq_qnum];
1317
1318 txq->axq_qnum = axq_qnum;
1319 txq->mac80211_qnum = -1;
1320 txq->axq_link = NULL;
1321 INIT_LIST_HEAD(&txq->axq_q);
1322 INIT_LIST_HEAD(&txq->axq_acq);
1323 spin_lock_init(&txq->axq_lock);
1324 txq->axq_depth = 0;
1325 txq->axq_ampdu_depth = 0;
1326 txq->axq_tx_inprogress = false;
1327 sc->tx.txqsetup |= 1<<axq_qnum;
1328
1329 txq->txq_headidx = txq->txq_tailidx = 0;
1330 for (i = 0; i < ATH_TXFIFO_DEPTH; i++)
1331 INIT_LIST_HEAD(&txq->txq_fifo[i]);
1332 }
1333 return &sc->tx.txq[axq_qnum];
1334 }
1335
1336 int ath_txq_update(struct ath_softc *sc, int qnum,
1337 struct ath9k_tx_queue_info *qinfo)
1338 {
1339 struct ath_hw *ah = sc->sc_ah;
1340 int error = 0;
1341 struct ath9k_tx_queue_info qi;
1342
1343 if (qnum == sc->beacon.beaconq) {
1344 /*
1345 * XXX: for beacon queue, we just save the parameter.
1346 * It will be picked up by ath_beaconq_config when
1347 * it's necessary.
1348 */
1349 sc->beacon.beacon_qi = *qinfo;
1350 return 0;
1351 }
1352
1353 BUG_ON(sc->tx.txq[qnum].axq_qnum != qnum);
1354
1355 ath9k_hw_get_txq_props(ah, qnum, &qi);
1356 qi.tqi_aifs = qinfo->tqi_aifs;
1357 qi.tqi_cwmin = qinfo->tqi_cwmin;
1358 qi.tqi_cwmax = qinfo->tqi_cwmax;
1359 qi.tqi_burstTime = qinfo->tqi_burstTime;
1360 qi.tqi_readyTime = qinfo->tqi_readyTime;
1361
1362 if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) {
1363 ath_err(ath9k_hw_common(sc->sc_ah),
1364 "Unable to update hardware queue %u!\n", qnum);
1365 error = -EIO;
1366 } else {
1367 ath9k_hw_resettxqueue(ah, qnum);
1368 }
1369
1370 return error;
1371 }
1372
1373 int ath_cabq_update(struct ath_softc *sc)
1374 {
1375 struct ath9k_tx_queue_info qi;
1376 struct ath_beacon_config *cur_conf = &sc->cur_beacon_conf;
1377 int qnum = sc->beacon.cabq->axq_qnum;
1378
1379 ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi);
1380 /*
1381 * Ensure the readytime % is within the bounds.
1382 */
1383 if (sc->config.cabqReadytime < ATH9K_READY_TIME_LO_BOUND)
1384 sc->config.cabqReadytime = ATH9K_READY_TIME_LO_BOUND;
1385 else if (sc->config.cabqReadytime > ATH9K_READY_TIME_HI_BOUND)
1386 sc->config.cabqReadytime = ATH9K_READY_TIME_HI_BOUND;
1387
1388 qi.tqi_readyTime = (cur_conf->beacon_interval *
1389 sc->config.cabqReadytime) / 100;
1390 ath_txq_update(sc, qnum, &qi);
1391
1392 return 0;
1393 }
1394
1395 static bool bf_is_ampdu_not_probing(struct ath_buf *bf)
1396 {
1397 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(bf->bf_mpdu);
1398 return bf_isampdu(bf) && !(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE);
1399 }
1400
1401 static void ath_drain_txq_list(struct ath_softc *sc, struct ath_txq *txq,
1402 struct list_head *list, bool retry_tx)
1403 __releases(txq->axq_lock)
1404 __acquires(txq->axq_lock)
1405 {
1406 struct ath_buf *bf, *lastbf;
1407 struct list_head bf_head;
1408 struct ath_tx_status ts;
1409
1410 memset(&ts, 0, sizeof(ts));
1411 ts.ts_status = ATH9K_TX_FLUSH;
1412 INIT_LIST_HEAD(&bf_head);
1413
1414 while (!list_empty(list)) {
1415 bf = list_first_entry(list, struct ath_buf, list);
1416
1417 if (bf->bf_stale) {
1418 list_del(&bf->list);
1419
1420 ath_tx_return_buffer(sc, bf);
1421 continue;
1422 }
1423
1424 lastbf = bf->bf_lastbf;
1425 list_cut_position(&bf_head, list, &lastbf->list);
1426
1427 txq->axq_depth--;
1428 if (bf_is_ampdu_not_probing(bf))
1429 txq->axq_ampdu_depth--;
1430
1431 spin_unlock_bh(&txq->axq_lock);
1432 if (bf_isampdu(bf))
1433 ath_tx_complete_aggr(sc, txq, bf, &bf_head, &ts, 0,
1434 retry_tx);
1435 else
1436 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 0);
1437 spin_lock_bh(&txq->axq_lock);
1438 }
1439 }
1440
1441 /*
1442 * Drain a given TX queue (could be Beacon or Data)
1443 *
1444 * This assumes output has been stopped and
1445 * we do not need to block ath_tx_tasklet.
1446 */
1447 void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq, bool retry_tx)
1448 {
1449 spin_lock_bh(&txq->axq_lock);
1450 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1451 int idx = txq->txq_tailidx;
1452
1453 while (!list_empty(&txq->txq_fifo[idx])) {
1454 ath_drain_txq_list(sc, txq, &txq->txq_fifo[idx],
1455 retry_tx);
1456
1457 INCR(idx, ATH_TXFIFO_DEPTH);
1458 }
1459 txq->txq_tailidx = idx;
1460 }
1461
1462 txq->axq_link = NULL;
1463 txq->axq_tx_inprogress = false;
1464 ath_drain_txq_list(sc, txq, &txq->axq_q, retry_tx);
1465
1466 /* flush any pending frames if aggregation is enabled */
1467 if ((sc->sc_flags & SC_OP_TXAGGR) && !retry_tx)
1468 ath_txq_drain_pending_buffers(sc, txq);
1469
1470 spin_unlock_bh(&txq->axq_lock);
1471 }
1472
1473 bool ath_drain_all_txq(struct ath_softc *sc, bool retry_tx)
1474 {
1475 struct ath_hw *ah = sc->sc_ah;
1476 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1477 struct ath_txq *txq;
1478 int i;
1479 u32 npend = 0;
1480
1481 if (sc->sc_flags & SC_OP_INVALID)
1482 return true;
1483
1484 ath9k_hw_abort_tx_dma(ah);
1485
1486 /* Check if any queue remains active */
1487 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1488 if (!ATH_TXQ_SETUP(sc, i))
1489 continue;
1490
1491 if (ath9k_hw_numtxpending(ah, sc->tx.txq[i].axq_qnum))
1492 npend |= BIT(i);
1493 }
1494
1495 if (npend)
1496 ath_err(common, "Failed to stop TX DMA, queues=0x%03x!\n", npend);
1497
1498 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1499 if (!ATH_TXQ_SETUP(sc, i))
1500 continue;
1501
1502 /*
1503 * The caller will resume queues with ieee80211_wake_queues.
1504 * Mark the queue as not stopped to prevent ath_tx_complete
1505 * from waking the queue too early.
1506 */
1507 txq = &sc->tx.txq[i];
1508 txq->stopped = false;
1509 ath_draintxq(sc, txq, retry_tx);
1510 }
1511
1512 return !npend;
1513 }
1514
1515 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
1516 {
1517 ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum);
1518 sc->tx.txqsetup &= ~(1<<txq->axq_qnum);
1519 }
1520
1521 /* For each axq_acq entry, for each tid, try to schedule packets
1522 * for transmit until ampdu_depth has reached min Q depth.
1523 */
1524 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq)
1525 {
1526 struct ath_atx_ac *ac, *ac_tmp, *last_ac;
1527 struct ath_atx_tid *tid, *last_tid;
1528
1529 if (work_pending(&sc->hw_reset_work) || list_empty(&txq->axq_acq) ||
1530 txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH)
1531 return;
1532
1533 ac = list_first_entry(&txq->axq_acq, struct ath_atx_ac, list);
1534 last_ac = list_entry(txq->axq_acq.prev, struct ath_atx_ac, list);
1535
1536 list_for_each_entry_safe(ac, ac_tmp, &txq->axq_acq, list) {
1537 last_tid = list_entry(ac->tid_q.prev, struct ath_atx_tid, list);
1538 list_del(&ac->list);
1539 ac->sched = false;
1540
1541 while (!list_empty(&ac->tid_q)) {
1542 tid = list_first_entry(&ac->tid_q, struct ath_atx_tid,
1543 list);
1544 list_del(&tid->list);
1545 tid->sched = false;
1546
1547 if (tid->paused)
1548 continue;
1549
1550 ath_tx_sched_aggr(sc, txq, tid);
1551
1552 /*
1553 * add tid to round-robin queue if more frames
1554 * are pending for the tid
1555 */
1556 if (!skb_queue_empty(&tid->buf_q))
1557 ath_tx_queue_tid(txq, tid);
1558
1559 if (tid == last_tid ||
1560 txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH)
1561 break;
1562 }
1563
1564 if (!list_empty(&ac->tid_q)) {
1565 if (!ac->sched) {
1566 ac->sched = true;
1567 list_add_tail(&ac->list, &txq->axq_acq);
1568 }
1569 }
1570
1571 if (ac == last_ac ||
1572 txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH)
1573 return;
1574 }
1575 }
1576
1577 /***********/
1578 /* TX, DMA */
1579 /***********/
1580
1581 /*
1582 * Insert a chain of ath_buf (descriptors) on a txq and
1583 * assume the descriptors are already chained together by caller.
1584 */
1585 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
1586 struct list_head *head, bool internal)
1587 {
1588 struct ath_hw *ah = sc->sc_ah;
1589 struct ath_common *common = ath9k_hw_common(ah);
1590 struct ath_buf *bf, *bf_last;
1591 bool puttxbuf = false;
1592 bool edma;
1593
1594 /*
1595 * Insert the frame on the outbound list and
1596 * pass it on to the hardware.
1597 */
1598
1599 if (list_empty(head))
1600 return;
1601
1602 edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
1603 bf = list_first_entry(head, struct ath_buf, list);
1604 bf_last = list_entry(head->prev, struct ath_buf, list);
1605
1606 ath_dbg(common, ATH_DBG_QUEUE,
1607 "qnum: %d, txq depth: %d\n", txq->axq_qnum, txq->axq_depth);
1608
1609 if (edma && list_empty(&txq->txq_fifo[txq->txq_headidx])) {
1610 list_splice_tail_init(head, &txq->txq_fifo[txq->txq_headidx]);
1611 INCR(txq->txq_headidx, ATH_TXFIFO_DEPTH);
1612 puttxbuf = true;
1613 } else {
1614 list_splice_tail_init(head, &txq->axq_q);
1615
1616 if (txq->axq_link) {
1617 ath9k_hw_set_desc_link(ah, txq->axq_link, bf->bf_daddr);
1618 ath_dbg(common, ATH_DBG_XMIT,
1619 "link[%u] (%p)=%llx (%p)\n",
1620 txq->axq_qnum, txq->axq_link,
1621 ito64(bf->bf_daddr), bf->bf_desc);
1622 } else if (!edma)
1623 puttxbuf = true;
1624
1625 txq->axq_link = bf_last->bf_desc;
1626 }
1627
1628 if (puttxbuf) {
1629 TX_STAT_INC(txq->axq_qnum, puttxbuf);
1630 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
1631 ath_dbg(common, ATH_DBG_XMIT, "TXDP[%u] = %llx (%p)\n",
1632 txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc);
1633 }
1634
1635 if (!edma) {
1636 TX_STAT_INC(txq->axq_qnum, txstart);
1637 ath9k_hw_txstart(ah, txq->axq_qnum);
1638 }
1639
1640 if (!internal) {
1641 txq->axq_depth++;
1642 if (bf_is_ampdu_not_probing(bf))
1643 txq->axq_ampdu_depth++;
1644 }
1645 }
1646
1647 static void ath_tx_send_ampdu(struct ath_softc *sc, struct ath_atx_tid *tid,
1648 struct sk_buff *skb, struct ath_tx_control *txctl)
1649 {
1650 struct ath_frame_info *fi = get_frame_info(skb);
1651 struct list_head bf_head;
1652 struct ath_buf *bf;
1653
1654 /*
1655 * Do not queue to h/w when any of the following conditions is true:
1656 * - there are pending frames in software queue
1657 * - the TID is currently paused for ADDBA/BAR request
1658 * - seqno is not within block-ack window
1659 * - h/w queue depth exceeds low water mark
1660 */
1661 if (!skb_queue_empty(&tid->buf_q) || tid->paused ||
1662 !BAW_WITHIN(tid->seq_start, tid->baw_size, tid->seq_next) ||
1663 txctl->txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH) {
1664 /*
1665 * Add this frame to software queue for scheduling later
1666 * for aggregation.
1667 */
1668 TX_STAT_INC(txctl->txq->axq_qnum, a_queued_sw);
1669 __skb_queue_tail(&tid->buf_q, skb);
1670 if (!txctl->an || !txctl->an->sleeping)
1671 ath_tx_queue_tid(txctl->txq, tid);
1672 return;
1673 }
1674
1675 bf = ath_tx_setup_buffer(sc, txctl->txq, tid, skb);
1676 if (!bf)
1677 return;
1678
1679 bf->bf_state.bf_type = BUF_AMPDU;
1680 INIT_LIST_HEAD(&bf_head);
1681 list_add(&bf->list, &bf_head);
1682
1683 /* Add sub-frame to BAW */
1684 ath_tx_addto_baw(sc, tid, bf->bf_state.seqno);
1685
1686 /* Queue to h/w without aggregation */
1687 TX_STAT_INC(txctl->txq->axq_qnum, a_queued_hw);
1688 bf->bf_lastbf = bf;
1689 ath_tx_fill_desc(sc, bf, txctl->txq, fi->framelen);
1690 ath_tx_txqaddbuf(sc, txctl->txq, &bf_head, false);
1691 }
1692
1693 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
1694 struct ath_atx_tid *tid, struct sk_buff *skb)
1695 {
1696 struct ath_frame_info *fi = get_frame_info(skb);
1697 struct list_head bf_head;
1698 struct ath_buf *bf;
1699
1700 bf = fi->bf;
1701 if (!bf)
1702 bf = ath_tx_setup_buffer(sc, txq, tid, skb);
1703
1704 if (!bf)
1705 return;
1706
1707 INIT_LIST_HEAD(&bf_head);
1708 list_add_tail(&bf->list, &bf_head);
1709 bf->bf_state.bf_type = 0;
1710
1711 /* update starting sequence number for subsequent ADDBA request */
1712 if (tid)
1713 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
1714
1715 bf->bf_lastbf = bf;
1716 ath_tx_fill_desc(sc, bf, txq, fi->framelen);
1717 ath_tx_txqaddbuf(sc, txq, &bf_head, false);
1718 TX_STAT_INC(txq->axq_qnum, queued);
1719 }
1720
1721 static void setup_frame_info(struct ieee80211_hw *hw, struct sk_buff *skb,
1722 int framelen)
1723 {
1724 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1725 struct ieee80211_sta *sta = tx_info->control.sta;
1726 struct ieee80211_key_conf *hw_key = tx_info->control.hw_key;
1727 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1728 struct ath_frame_info *fi = get_frame_info(skb);
1729 struct ath_node *an = NULL;
1730 enum ath9k_key_type keytype;
1731
1732 keytype = ath9k_cmn_get_hw_crypto_keytype(skb);
1733
1734 if (sta)
1735 an = (struct ath_node *) sta->drv_priv;
1736
1737 memset(fi, 0, sizeof(*fi));
1738 if (hw_key)
1739 fi->keyix = hw_key->hw_key_idx;
1740 else if (an && ieee80211_is_data(hdr->frame_control) && an->ps_key > 0)
1741 fi->keyix = an->ps_key;
1742 else
1743 fi->keyix = ATH9K_TXKEYIX_INVALID;
1744 fi->keytype = keytype;
1745 fi->framelen = framelen;
1746 }
1747
1748 u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate)
1749 {
1750 struct ath_hw *ah = sc->sc_ah;
1751 struct ath9k_channel *curchan = ah->curchan;
1752 if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) &&
1753 (curchan->channelFlags & CHANNEL_5GHZ) &&
1754 (chainmask == 0x7) && (rate < 0x90))
1755 return 0x3;
1756 else
1757 return chainmask;
1758 }
1759
1760 /*
1761 * Assign a descriptor (and sequence number if necessary,
1762 * and map buffer for DMA. Frees skb on error
1763 */
1764 static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc,
1765 struct ath_txq *txq,
1766 struct ath_atx_tid *tid,
1767 struct sk_buff *skb)
1768 {
1769 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1770 struct ath_frame_info *fi = get_frame_info(skb);
1771 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1772 struct ath_buf *bf;
1773 u16 seqno;
1774
1775 bf = ath_tx_get_buffer(sc);
1776 if (!bf) {
1777 ath_dbg(common, ATH_DBG_XMIT, "TX buffers are full\n");
1778 goto error;
1779 }
1780
1781 ATH_TXBUF_RESET(bf);
1782
1783 if (tid) {
1784 seqno = tid->seq_next;
1785 hdr->seq_ctrl = cpu_to_le16(tid->seq_next << IEEE80211_SEQ_SEQ_SHIFT);
1786 INCR(tid->seq_next, IEEE80211_SEQ_MAX);
1787 bf->bf_state.seqno = seqno;
1788 }
1789
1790 bf->bf_mpdu = skb;
1791
1792 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
1793 skb->len, DMA_TO_DEVICE);
1794 if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) {
1795 bf->bf_mpdu = NULL;
1796 bf->bf_buf_addr = 0;
1797 ath_err(ath9k_hw_common(sc->sc_ah),
1798 "dma_mapping_error() on TX\n");
1799 ath_tx_return_buffer(sc, bf);
1800 goto error;
1801 }
1802
1803 fi->bf = bf;
1804
1805 return bf;
1806
1807 error:
1808 dev_kfree_skb_any(skb);
1809 return NULL;
1810 }
1811
1812 /* FIXME: tx power */
1813 static void ath_tx_start_dma(struct ath_softc *sc, struct sk_buff *skb,
1814 struct ath_tx_control *txctl)
1815 {
1816 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1817 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1818 struct ath_atx_tid *tid = NULL;
1819 struct ath_buf *bf;
1820 u8 tidno;
1821
1822 spin_lock_bh(&txctl->txq->axq_lock);
1823 if ((sc->sc_flags & SC_OP_TXAGGR) && txctl->an &&
1824 ieee80211_is_data_qos(hdr->frame_control)) {
1825 tidno = ieee80211_get_qos_ctl(hdr)[0] &
1826 IEEE80211_QOS_CTL_TID_MASK;
1827 tid = ATH_AN_2_TID(txctl->an, tidno);
1828
1829 WARN_ON(tid->ac->txq != txctl->txq);
1830 }
1831
1832 if ((tx_info->flags & IEEE80211_TX_CTL_AMPDU) && tid) {
1833 /*
1834 * Try aggregation if it's a unicast data frame
1835 * and the destination is HT capable.
1836 */
1837 ath_tx_send_ampdu(sc, tid, skb, txctl);
1838 } else {
1839 bf = ath_tx_setup_buffer(sc, txctl->txq, tid, skb);
1840 if (!bf)
1841 goto out;
1842
1843 bf->bf_state.bfs_paprd = txctl->paprd;
1844
1845 if (txctl->paprd)
1846 bf->bf_state.bfs_paprd_timestamp = jiffies;
1847
1848 ath_tx_send_normal(sc, txctl->txq, tid, skb);
1849 }
1850
1851 out:
1852 spin_unlock_bh(&txctl->txq->axq_lock);
1853 }
1854
1855 /* Upon failure caller should free skb */
1856 int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
1857 struct ath_tx_control *txctl)
1858 {
1859 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
1860 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1861 struct ieee80211_sta *sta = info->control.sta;
1862 struct ieee80211_vif *vif = info->control.vif;
1863 struct ath_softc *sc = hw->priv;
1864 struct ath_txq *txq = txctl->txq;
1865 int padpos, padsize;
1866 int frmlen = skb->len + FCS_LEN;
1867 int q;
1868
1869 /* NOTE: sta can be NULL according to net/mac80211.h */
1870 if (sta)
1871 txctl->an = (struct ath_node *)sta->drv_priv;
1872
1873 if (info->control.hw_key)
1874 frmlen += info->control.hw_key->icv_len;
1875
1876 /*
1877 * As a temporary workaround, assign seq# here; this will likely need
1878 * to be cleaned up to work better with Beacon transmission and virtual
1879 * BSSes.
1880 */
1881 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1882 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
1883 sc->tx.seq_no += 0x10;
1884 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
1885 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
1886 }
1887
1888 /* Add the padding after the header if this is not already done */
1889 padpos = ath9k_cmn_padpos(hdr->frame_control);
1890 padsize = padpos & 3;
1891 if (padsize && skb->len > padpos) {
1892 if (skb_headroom(skb) < padsize)
1893 return -ENOMEM;
1894
1895 skb_push(skb, padsize);
1896 memmove(skb->data, skb->data + padsize, padpos);
1897 hdr = (struct ieee80211_hdr *) skb->data;
1898 }
1899
1900 if ((vif && vif->type != NL80211_IFTYPE_AP &&
1901 vif->type != NL80211_IFTYPE_AP_VLAN) ||
1902 !ieee80211_is_data(hdr->frame_control))
1903 info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT;
1904
1905 setup_frame_info(hw, skb, frmlen);
1906
1907 /*
1908 * At this point, the vif, hw_key and sta pointers in the tx control
1909 * info are no longer valid (overwritten by the ath_frame_info data.
1910 */
1911
1912 q = skb_get_queue_mapping(skb);
1913 spin_lock_bh(&txq->axq_lock);
1914 if (txq == sc->tx.txq_map[q] &&
1915 ++txq->pending_frames > ATH_MAX_QDEPTH && !txq->stopped) {
1916 ieee80211_stop_queue(sc->hw, q);
1917 txq->stopped = 1;
1918 }
1919 spin_unlock_bh(&txq->axq_lock);
1920
1921 ath_tx_start_dma(sc, skb, txctl);
1922 return 0;
1923 }
1924
1925 /*****************/
1926 /* TX Completion */
1927 /*****************/
1928
1929 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
1930 int tx_flags, struct ath_txq *txq)
1931 {
1932 struct ieee80211_hw *hw = sc->hw;
1933 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1934 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1935 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data;
1936 int q, padpos, padsize;
1937
1938 ath_dbg(common, ATH_DBG_XMIT, "TX complete: skb: %p\n", skb);
1939
1940 if (tx_flags & ATH_TX_BAR)
1941 tx_info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
1942
1943 if (!(tx_flags & ATH_TX_ERROR))
1944 /* Frame was ACKed */
1945 tx_info->flags |= IEEE80211_TX_STAT_ACK;
1946
1947 padpos = ath9k_cmn_padpos(hdr->frame_control);
1948 padsize = padpos & 3;
1949 if (padsize && skb->len>padpos+padsize) {
1950 /*
1951 * Remove MAC header padding before giving the frame back to
1952 * mac80211.
1953 */
1954 memmove(skb->data + padsize, skb->data, padpos);
1955 skb_pull(skb, padsize);
1956 }
1957
1958 if (sc->ps_flags & PS_WAIT_FOR_TX_ACK) {
1959 sc->ps_flags &= ~PS_WAIT_FOR_TX_ACK;
1960 ath_dbg(common, ATH_DBG_PS,
1961 "Going back to sleep after having received TX status (0x%lx)\n",
1962 sc->ps_flags & (PS_WAIT_FOR_BEACON |
1963 PS_WAIT_FOR_CAB |
1964 PS_WAIT_FOR_PSPOLL_DATA |
1965 PS_WAIT_FOR_TX_ACK));
1966 }
1967
1968 q = skb_get_queue_mapping(skb);
1969 if (txq == sc->tx.txq_map[q]) {
1970 spin_lock_bh(&txq->axq_lock);
1971 if (WARN_ON(--txq->pending_frames < 0))
1972 txq->pending_frames = 0;
1973
1974 if (txq->stopped && txq->pending_frames < ATH_MAX_QDEPTH) {
1975 ieee80211_wake_queue(sc->hw, q);
1976 txq->stopped = 0;
1977 }
1978 spin_unlock_bh(&txq->axq_lock);
1979 }
1980
1981 ieee80211_tx_status(hw, skb);
1982 }
1983
1984 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
1985 struct ath_txq *txq, struct list_head *bf_q,
1986 struct ath_tx_status *ts, int txok, int sendbar)
1987 {
1988 struct sk_buff *skb = bf->bf_mpdu;
1989 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1990 unsigned long flags;
1991 int tx_flags = 0;
1992
1993 if (sendbar)
1994 tx_flags = ATH_TX_BAR;
1995
1996 if (!txok)
1997 tx_flags |= ATH_TX_ERROR;
1998
1999 if (ts->ts_status & ATH9K_TXERR_FILT)
2000 tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
2001
2002 dma_unmap_single(sc->dev, bf->bf_buf_addr, skb->len, DMA_TO_DEVICE);
2003 bf->bf_buf_addr = 0;
2004
2005 if (bf->bf_state.bfs_paprd) {
2006 if (time_after(jiffies,
2007 bf->bf_state.bfs_paprd_timestamp +
2008 msecs_to_jiffies(ATH_PAPRD_TIMEOUT)))
2009 dev_kfree_skb_any(skb);
2010 else
2011 complete(&sc->paprd_complete);
2012 } else {
2013 ath_debug_stat_tx(sc, bf, ts, txq, tx_flags);
2014 ath_tx_complete(sc, skb, tx_flags, txq);
2015 }
2016 /* At this point, skb (bf->bf_mpdu) is consumed...make sure we don't
2017 * accidentally reference it later.
2018 */
2019 bf->bf_mpdu = NULL;
2020
2021 /*
2022 * Return the list of ath_buf of this mpdu to free queue
2023 */
2024 spin_lock_irqsave(&sc->tx.txbuflock, flags);
2025 list_splice_tail_init(bf_q, &sc->tx.txbuf);
2026 spin_unlock_irqrestore(&sc->tx.txbuflock, flags);
2027 }
2028
2029 static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
2030 struct ath_tx_status *ts, int nframes, int nbad,
2031 int txok)
2032 {
2033 struct sk_buff *skb = bf->bf_mpdu;
2034 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
2035 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2036 struct ieee80211_hw *hw = sc->hw;
2037 struct ath_hw *ah = sc->sc_ah;
2038 u8 i, tx_rateindex;
2039
2040 if (txok)
2041 tx_info->status.ack_signal = ts->ts_rssi;
2042
2043 tx_rateindex = ts->ts_rateindex;
2044 WARN_ON(tx_rateindex >= hw->max_rates);
2045
2046 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
2047 tx_info->flags |= IEEE80211_TX_STAT_AMPDU;
2048
2049 BUG_ON(nbad > nframes);
2050 }
2051 tx_info->status.ampdu_len = nframes;
2052 tx_info->status.ampdu_ack_len = nframes - nbad;
2053
2054 if ((ts->ts_status & ATH9K_TXERR_FILT) == 0 &&
2055 (tx_info->flags & IEEE80211_TX_CTL_NO_ACK) == 0) {
2056 /*
2057 * If an underrun error is seen assume it as an excessive
2058 * retry only if max frame trigger level has been reached
2059 * (2 KB for single stream, and 4 KB for dual stream).
2060 * Adjust the long retry as if the frame was tried
2061 * hw->max_rate_tries times to affect how rate control updates
2062 * PER for the failed rate.
2063 * In case of congestion on the bus penalizing this type of
2064 * underruns should help hardware actually transmit new frames
2065 * successfully by eventually preferring slower rates.
2066 * This itself should also alleviate congestion on the bus.
2067 */
2068 if (unlikely(ts->ts_flags & (ATH9K_TX_DATA_UNDERRUN |
2069 ATH9K_TX_DELIM_UNDERRUN)) &&
2070 ieee80211_is_data(hdr->frame_control) &&
2071 ah->tx_trig_level >= sc->sc_ah->config.max_txtrig_level)
2072 tx_info->status.rates[tx_rateindex].count =
2073 hw->max_rate_tries;
2074 }
2075
2076 for (i = tx_rateindex + 1; i < hw->max_rates; i++) {
2077 tx_info->status.rates[i].count = 0;
2078 tx_info->status.rates[i].idx = -1;
2079 }
2080
2081 tx_info->status.rates[tx_rateindex].count = ts->ts_longretry + 1;
2082 }
2083
2084 static void ath_tx_process_buffer(struct ath_softc *sc, struct ath_txq *txq,
2085 struct ath_tx_status *ts, struct ath_buf *bf,
2086 struct list_head *bf_head)
2087 __releases(txq->axq_lock)
2088 __acquires(txq->axq_lock)
2089 {
2090 int txok;
2091
2092 txq->axq_depth--;
2093 txok = !(ts->ts_status & ATH9K_TXERR_MASK);
2094 txq->axq_tx_inprogress = false;
2095 if (bf_is_ampdu_not_probing(bf))
2096 txq->axq_ampdu_depth--;
2097
2098 spin_unlock_bh(&txq->axq_lock);
2099
2100 if (!bf_isampdu(bf)) {
2101 ath_tx_rc_status(sc, bf, ts, 1, txok ? 0 : 1, txok);
2102 ath_tx_complete_buf(sc, bf, txq, bf_head, ts, txok, 0);
2103 } else
2104 ath_tx_complete_aggr(sc, txq, bf, bf_head, ts, txok, true);
2105
2106 spin_lock_bh(&txq->axq_lock);
2107
2108 if (sc->sc_flags & SC_OP_TXAGGR)
2109 ath_txq_schedule(sc, txq);
2110 }
2111
2112 static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
2113 {
2114 struct ath_hw *ah = sc->sc_ah;
2115 struct ath_common *common = ath9k_hw_common(ah);
2116 struct ath_buf *bf, *lastbf, *bf_held = NULL;
2117 struct list_head bf_head;
2118 struct ath_desc *ds;
2119 struct ath_tx_status ts;
2120 int status;
2121
2122 ath_dbg(common, ATH_DBG_QUEUE, "tx queue %d (%x), link %p\n",
2123 txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum),
2124 txq->axq_link);
2125
2126 spin_lock_bh(&txq->axq_lock);
2127 for (;;) {
2128 if (work_pending(&sc->hw_reset_work))
2129 break;
2130
2131 if (list_empty(&txq->axq_q)) {
2132 txq->axq_link = NULL;
2133 if (sc->sc_flags & SC_OP_TXAGGR)
2134 ath_txq_schedule(sc, txq);
2135 break;
2136 }
2137 bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
2138
2139 /*
2140 * There is a race condition that a BH gets scheduled
2141 * after sw writes TxE and before hw re-load the last
2142 * descriptor to get the newly chained one.
2143 * Software must keep the last DONE descriptor as a
2144 * holding descriptor - software does so by marking
2145 * it with the STALE flag.
2146 */
2147 bf_held = NULL;
2148 if (bf->bf_stale) {
2149 bf_held = bf;
2150 if (list_is_last(&bf_held->list, &txq->axq_q))
2151 break;
2152
2153 bf = list_entry(bf_held->list.next, struct ath_buf,
2154 list);
2155 }
2156
2157 lastbf = bf->bf_lastbf;
2158 ds = lastbf->bf_desc;
2159
2160 memset(&ts, 0, sizeof(ts));
2161 status = ath9k_hw_txprocdesc(ah, ds, &ts);
2162 if (status == -EINPROGRESS)
2163 break;
2164
2165 TX_STAT_INC(txq->axq_qnum, txprocdesc);
2166
2167 /*
2168 * Remove ath_buf's of the same transmit unit from txq,
2169 * however leave the last descriptor back as the holding
2170 * descriptor for hw.
2171 */
2172 lastbf->bf_stale = true;
2173 INIT_LIST_HEAD(&bf_head);
2174 if (!list_is_singular(&lastbf->list))
2175 list_cut_position(&bf_head,
2176 &txq->axq_q, lastbf->list.prev);
2177
2178 if (bf_held) {
2179 list_del(&bf_held->list);
2180 ath_tx_return_buffer(sc, bf_held);
2181 }
2182
2183 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
2184 }
2185 spin_unlock_bh(&txq->axq_lock);
2186 }
2187
2188 static void ath_tx_complete_poll_work(struct work_struct *work)
2189 {
2190 struct ath_softc *sc = container_of(work, struct ath_softc,
2191 tx_complete_work.work);
2192 struct ath_txq *txq;
2193 int i;
2194 bool needreset = false;
2195 #ifdef CONFIG_ATH9K_DEBUGFS
2196 sc->tx_complete_poll_work_seen++;
2197 #endif
2198
2199 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
2200 if (ATH_TXQ_SETUP(sc, i)) {
2201 txq = &sc->tx.txq[i];
2202 spin_lock_bh(&txq->axq_lock);
2203 if (txq->axq_depth) {
2204 if (txq->axq_tx_inprogress) {
2205 needreset = true;
2206 spin_unlock_bh(&txq->axq_lock);
2207 break;
2208 } else {
2209 txq->axq_tx_inprogress = true;
2210 }
2211 }
2212 spin_unlock_bh(&txq->axq_lock);
2213 }
2214
2215 if (needreset) {
2216 ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_RESET,
2217 "tx hung, resetting the chip\n");
2218 RESET_STAT_INC(sc, RESET_TYPE_TX_HANG);
2219 ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
2220 }
2221
2222 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work,
2223 msecs_to_jiffies(ATH_TX_COMPLETE_POLL_INT));
2224 }
2225
2226
2227
2228 void ath_tx_tasklet(struct ath_softc *sc)
2229 {
2230 int i;
2231 u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1);
2232
2233 ath9k_hw_gettxintrtxqs(sc->sc_ah, &qcumask);
2234
2235 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2236 if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i)))
2237 ath_tx_processq(sc, &sc->tx.txq[i]);
2238 }
2239 }
2240
2241 void ath_tx_edma_tasklet(struct ath_softc *sc)
2242 {
2243 struct ath_tx_status ts;
2244 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2245 struct ath_hw *ah = sc->sc_ah;
2246 struct ath_txq *txq;
2247 struct ath_buf *bf, *lastbf;
2248 struct list_head bf_head;
2249 int status;
2250
2251 for (;;) {
2252 if (work_pending(&sc->hw_reset_work))
2253 break;
2254
2255 status = ath9k_hw_txprocdesc(ah, NULL, (void *)&ts);
2256 if (status == -EINPROGRESS)
2257 break;
2258 if (status == -EIO) {
2259 ath_dbg(common, ATH_DBG_XMIT,
2260 "Error processing tx status\n");
2261 break;
2262 }
2263
2264 /* Skip beacon completions */
2265 if (ts.qid == sc->beacon.beaconq)
2266 continue;
2267
2268 txq = &sc->tx.txq[ts.qid];
2269
2270 spin_lock_bh(&txq->axq_lock);
2271
2272 if (list_empty(&txq->txq_fifo[txq->txq_tailidx])) {
2273 spin_unlock_bh(&txq->axq_lock);
2274 return;
2275 }
2276
2277 bf = list_first_entry(&txq->txq_fifo[txq->txq_tailidx],
2278 struct ath_buf, list);
2279 lastbf = bf->bf_lastbf;
2280
2281 INIT_LIST_HEAD(&bf_head);
2282 list_cut_position(&bf_head, &txq->txq_fifo[txq->txq_tailidx],
2283 &lastbf->list);
2284
2285 if (list_empty(&txq->txq_fifo[txq->txq_tailidx])) {
2286 INCR(txq->txq_tailidx, ATH_TXFIFO_DEPTH);
2287
2288 if (!list_empty(&txq->axq_q)) {
2289 struct list_head bf_q;
2290
2291 INIT_LIST_HEAD(&bf_q);
2292 txq->axq_link = NULL;
2293 list_splice_tail_init(&txq->axq_q, &bf_q);
2294 ath_tx_txqaddbuf(sc, txq, &bf_q, true);
2295 }
2296 }
2297
2298 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
2299 spin_unlock_bh(&txq->axq_lock);
2300 }
2301 }
2302
2303 /*****************/
2304 /* Init, Cleanup */
2305 /*****************/
2306
2307 static int ath_txstatus_setup(struct ath_softc *sc, int size)
2308 {
2309 struct ath_descdma *dd = &sc->txsdma;
2310 u8 txs_len = sc->sc_ah->caps.txs_len;
2311
2312 dd->dd_desc_len = size * txs_len;
2313 dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
2314 &dd->dd_desc_paddr, GFP_KERNEL);
2315 if (!dd->dd_desc)
2316 return -ENOMEM;
2317
2318 return 0;
2319 }
2320
2321 static int ath_tx_edma_init(struct ath_softc *sc)
2322 {
2323 int err;
2324
2325 err = ath_txstatus_setup(sc, ATH_TXSTATUS_RING_SIZE);
2326 if (!err)
2327 ath9k_hw_setup_statusring(sc->sc_ah, sc->txsdma.dd_desc,
2328 sc->txsdma.dd_desc_paddr,
2329 ATH_TXSTATUS_RING_SIZE);
2330
2331 return err;
2332 }
2333
2334 static void ath_tx_edma_cleanup(struct ath_softc *sc)
2335 {
2336 struct ath_descdma *dd = &sc->txsdma;
2337
2338 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
2339 dd->dd_desc_paddr);
2340 }
2341
2342 int ath_tx_init(struct ath_softc *sc, int nbufs)
2343 {
2344 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2345 int error = 0;
2346
2347 spin_lock_init(&sc->tx.txbuflock);
2348
2349 error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf,
2350 "tx", nbufs, 1, 1);
2351 if (error != 0) {
2352 ath_err(common,
2353 "Failed to allocate tx descriptors: %d\n", error);
2354 goto err;
2355 }
2356
2357 error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf,
2358 "beacon", ATH_BCBUF, 1, 1);
2359 if (error != 0) {
2360 ath_err(common,
2361 "Failed to allocate beacon descriptors: %d\n", error);
2362 goto err;
2363 }
2364
2365 INIT_DELAYED_WORK(&sc->tx_complete_work, ath_tx_complete_poll_work);
2366
2367 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
2368 error = ath_tx_edma_init(sc);
2369 if (error)
2370 goto err;
2371 }
2372
2373 err:
2374 if (error != 0)
2375 ath_tx_cleanup(sc);
2376
2377 return error;
2378 }
2379
2380 void ath_tx_cleanup(struct ath_softc *sc)
2381 {
2382 if (sc->beacon.bdma.dd_desc_len != 0)
2383 ath_descdma_cleanup(sc, &sc->beacon.bdma, &sc->beacon.bbuf);
2384
2385 if (sc->tx.txdma.dd_desc_len != 0)
2386 ath_descdma_cleanup(sc, &sc->tx.txdma, &sc->tx.txbuf);
2387
2388 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
2389 ath_tx_edma_cleanup(sc);
2390 }
2391
2392 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an)
2393 {
2394 struct ath_atx_tid *tid;
2395 struct ath_atx_ac *ac;
2396 int tidno, acno;
2397
2398 for (tidno = 0, tid = &an->tid[tidno];
2399 tidno < WME_NUM_TID;
2400 tidno++, tid++) {
2401 tid->an = an;
2402 tid->tidno = tidno;
2403 tid->seq_start = tid->seq_next = 0;
2404 tid->baw_size = WME_MAX_BA;
2405 tid->baw_head = tid->baw_tail = 0;
2406 tid->sched = false;
2407 tid->paused = false;
2408 tid->state &= ~AGGR_CLEANUP;
2409 __skb_queue_head_init(&tid->buf_q);
2410 acno = TID_TO_WME_AC(tidno);
2411 tid->ac = &an->ac[acno];
2412 tid->state &= ~AGGR_ADDBA_COMPLETE;
2413 tid->state &= ~AGGR_ADDBA_PROGRESS;
2414 }
2415
2416 for (acno = 0, ac = &an->ac[acno];
2417 acno < WME_NUM_AC; acno++, ac++) {
2418 ac->sched = false;
2419 ac->txq = sc->tx.txq_map[acno];
2420 INIT_LIST_HEAD(&ac->tid_q);
2421 }
2422 }
2423
2424 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an)
2425 {
2426 struct ath_atx_ac *ac;
2427 struct ath_atx_tid *tid;
2428 struct ath_txq *txq;
2429 int tidno;
2430
2431 for (tidno = 0, tid = &an->tid[tidno];
2432 tidno < WME_NUM_TID; tidno++, tid++) {
2433
2434 ac = tid->ac;
2435 txq = ac->txq;
2436
2437 spin_lock_bh(&txq->axq_lock);
2438
2439 if (tid->sched) {
2440 list_del(&tid->list);
2441 tid->sched = false;
2442 }
2443
2444 if (ac->sched) {
2445 list_del(&ac->list);
2446 tid->ac->sched = false;
2447 }
2448
2449 ath_tid_drain(sc, txq, tid);
2450 tid->state &= ~AGGR_ADDBA_COMPLETE;
2451 tid->state &= ~AGGR_CLEANUP;
2452
2453 spin_unlock_bh(&txq->axq_lock);
2454 }
2455 }
Linux kernel - Deliverables
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