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Merge remote-tracking branch 'regulator/topic/da9063' into regulator-next
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / xmit.c
1 /*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/dma-mapping.h>
18 #include "ath9k.h"
19 #include "ar9003_mac.h"
20
21 #define BITS_PER_BYTE 8
22 #define OFDM_PLCP_BITS 22
23 #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
24 #define L_STF 8
25 #define L_LTF 8
26 #define L_SIG 4
27 #define HT_SIG 8
28 #define HT_STF 4
29 #define HT_LTF(_ns) (4 * (_ns))
30 #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */
31 #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */
32 #define TIME_SYMBOLS(t) ((t) >> 2)
33 #define TIME_SYMBOLS_HALFGI(t) (((t) * 5 - 4) / 18)
34 #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
35 #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
36
37
38 static u16 bits_per_symbol[][2] = {
39 /* 20MHz 40MHz */
40 { 26, 54 }, /* 0: BPSK */
41 { 52, 108 }, /* 1: QPSK 1/2 */
42 { 78, 162 }, /* 2: QPSK 3/4 */
43 { 104, 216 }, /* 3: 16-QAM 1/2 */
44 { 156, 324 }, /* 4: 16-QAM 3/4 */
45 { 208, 432 }, /* 5: 64-QAM 2/3 */
46 { 234, 486 }, /* 6: 64-QAM 3/4 */
47 { 260, 540 }, /* 7: 64-QAM 5/6 */
48 };
49
50 #define IS_HT_RATE(_rate) ((_rate) & 0x80)
51
52 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
53 struct ath_atx_tid *tid, struct sk_buff *skb);
54 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
55 int tx_flags, struct ath_txq *txq);
56 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
57 struct ath_txq *txq, struct list_head *bf_q,
58 struct ath_tx_status *ts, int txok);
59 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
60 struct list_head *head, bool internal);
61 static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
62 struct ath_tx_status *ts, int nframes, int nbad,
63 int txok);
64 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
65 int seqno);
66 static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc,
67 struct ath_txq *txq,
68 struct ath_atx_tid *tid,
69 struct sk_buff *skb);
70
71 enum {
72 MCS_HT20,
73 MCS_HT20_SGI,
74 MCS_HT40,
75 MCS_HT40_SGI,
76 };
77
78 /*********************/
79 /* Aggregation logic */
80 /*********************/
81
82 void ath_txq_lock(struct ath_softc *sc, struct ath_txq *txq)
83 __acquires(&txq->axq_lock)
84 {
85 spin_lock_bh(&txq->axq_lock);
86 }
87
88 void ath_txq_unlock(struct ath_softc *sc, struct ath_txq *txq)
89 __releases(&txq->axq_lock)
90 {
91 spin_unlock_bh(&txq->axq_lock);
92 }
93
94 void ath_txq_unlock_complete(struct ath_softc *sc, struct ath_txq *txq)
95 __releases(&txq->axq_lock)
96 {
97 struct sk_buff_head q;
98 struct sk_buff *skb;
99
100 __skb_queue_head_init(&q);
101 skb_queue_splice_init(&txq->complete_q, &q);
102 spin_unlock_bh(&txq->axq_lock);
103
104 while ((skb = __skb_dequeue(&q)))
105 ieee80211_tx_status(sc->hw, skb);
106 }
107
108 static void ath_tx_queue_tid(struct ath_txq *txq, struct ath_atx_tid *tid)
109 {
110 struct ath_atx_ac *ac = tid->ac;
111
112 if (tid->paused)
113 return;
114
115 if (tid->sched)
116 return;
117
118 tid->sched = true;
119 list_add_tail(&tid->list, &ac->tid_q);
120
121 if (ac->sched)
122 return;
123
124 ac->sched = true;
125 list_add_tail(&ac->list, &txq->axq_acq);
126 }
127
128 static struct ath_frame_info *get_frame_info(struct sk_buff *skb)
129 {
130 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
131 BUILD_BUG_ON(sizeof(struct ath_frame_info) >
132 sizeof(tx_info->rate_driver_data));
133 return (struct ath_frame_info *) &tx_info->rate_driver_data[0];
134 }
135
136 static void ath_send_bar(struct ath_atx_tid *tid, u16 seqno)
137 {
138 if (!tid->an->sta)
139 return;
140
141 ieee80211_send_bar(tid->an->vif, tid->an->sta->addr, tid->tidno,
142 seqno << IEEE80211_SEQ_SEQ_SHIFT);
143 }
144
145 static void ath_set_rates(struct ieee80211_vif *vif, struct ieee80211_sta *sta,
146 struct ath_buf *bf)
147 {
148 ieee80211_get_tx_rates(vif, sta, bf->bf_mpdu, bf->rates,
149 ARRAY_SIZE(bf->rates));
150 }
151
152 static void ath_txq_skb_done(struct ath_softc *sc, struct ath_txq *txq,
153 struct sk_buff *skb)
154 {
155 int q;
156
157 q = skb_get_queue_mapping(skb);
158 if (txq == sc->tx.uapsdq)
159 txq = sc->tx.txq_map[q];
160
161 if (txq != sc->tx.txq_map[q])
162 return;
163
164 if (WARN_ON(--txq->pending_frames < 0))
165 txq->pending_frames = 0;
166
167 if (txq->stopped &&
168 txq->pending_frames < sc->tx.txq_max_pending[q]) {
169 ieee80211_wake_queue(sc->hw, q);
170 txq->stopped = false;
171 }
172 }
173
174 static struct ath_atx_tid *
175 ath_get_skb_tid(struct ath_softc *sc, struct ath_node *an, struct sk_buff *skb)
176 {
177 struct ieee80211_hdr *hdr;
178 u8 tidno = 0;
179
180 hdr = (struct ieee80211_hdr *) skb->data;
181 if (ieee80211_is_data_qos(hdr->frame_control))
182 tidno = ieee80211_get_qos_ctl(hdr)[0];
183
184 tidno &= IEEE80211_QOS_CTL_TID_MASK;
185 return ATH_AN_2_TID(an, tidno);
186 }
187
188 static bool ath_tid_has_buffered(struct ath_atx_tid *tid)
189 {
190 return !skb_queue_empty(&tid->buf_q) || !skb_queue_empty(&tid->retry_q);
191 }
192
193 static struct sk_buff *ath_tid_dequeue(struct ath_atx_tid *tid)
194 {
195 struct sk_buff *skb;
196
197 skb = __skb_dequeue(&tid->retry_q);
198 if (!skb)
199 skb = __skb_dequeue(&tid->buf_q);
200
201 return skb;
202 }
203
204 /*
205 * ath_tx_tid_change_state:
206 * - clears a-mpdu flag of previous session
207 * - force sequence number allocation to fix next BlockAck Window
208 */
209 static void
210 ath_tx_tid_change_state(struct ath_softc *sc, struct ath_atx_tid *tid)
211 {
212 struct ath_txq *txq = tid->ac->txq;
213 struct ieee80211_tx_info *tx_info;
214 struct sk_buff *skb, *tskb;
215 struct ath_buf *bf;
216 struct ath_frame_info *fi;
217
218 skb_queue_walk_safe(&tid->buf_q, skb, tskb) {
219 fi = get_frame_info(skb);
220 bf = fi->bf;
221
222 tx_info = IEEE80211_SKB_CB(skb);
223 tx_info->flags &= ~IEEE80211_TX_CTL_AMPDU;
224
225 if (bf)
226 continue;
227
228 bf = ath_tx_setup_buffer(sc, txq, tid, skb);
229 if (!bf) {
230 __skb_unlink(skb, &tid->buf_q);
231 ath_txq_skb_done(sc, txq, skb);
232 ieee80211_free_txskb(sc->hw, skb);
233 continue;
234 }
235 }
236
237 }
238
239 static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
240 {
241 struct ath_txq *txq = tid->ac->txq;
242 struct sk_buff *skb;
243 struct ath_buf *bf;
244 struct list_head bf_head;
245 struct ath_tx_status ts;
246 struct ath_frame_info *fi;
247 bool sendbar = false;
248
249 INIT_LIST_HEAD(&bf_head);
250
251 memset(&ts, 0, sizeof(ts));
252
253 while ((skb = __skb_dequeue(&tid->retry_q))) {
254 fi = get_frame_info(skb);
255 bf = fi->bf;
256 if (!bf) {
257 ath_txq_skb_done(sc, txq, skb);
258 ieee80211_free_txskb(sc->hw, skb);
259 continue;
260 }
261
262 if (fi->baw_tracked) {
263 ath_tx_update_baw(sc, tid, bf->bf_state.seqno);
264 sendbar = true;
265 }
266
267 list_add_tail(&bf->list, &bf_head);
268 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0);
269 }
270
271 if (sendbar) {
272 ath_txq_unlock(sc, txq);
273 ath_send_bar(tid, tid->seq_start);
274 ath_txq_lock(sc, txq);
275 }
276 }
277
278 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
279 int seqno)
280 {
281 int index, cindex;
282
283 index = ATH_BA_INDEX(tid->seq_start, seqno);
284 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
285
286 __clear_bit(cindex, tid->tx_buf);
287
288 while (tid->baw_head != tid->baw_tail && !test_bit(tid->baw_head, tid->tx_buf)) {
289 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
290 INCR(tid->baw_head, ATH_TID_MAX_BUFS);
291 if (tid->bar_index >= 0)
292 tid->bar_index--;
293 }
294 }
295
296 static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
297 struct ath_buf *bf)
298 {
299 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
300 u16 seqno = bf->bf_state.seqno;
301 int index, cindex;
302
303 index = ATH_BA_INDEX(tid->seq_start, seqno);
304 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
305 __set_bit(cindex, tid->tx_buf);
306 fi->baw_tracked = 1;
307
308 if (index >= ((tid->baw_tail - tid->baw_head) &
309 (ATH_TID_MAX_BUFS - 1))) {
310 tid->baw_tail = cindex;
311 INCR(tid->baw_tail, ATH_TID_MAX_BUFS);
312 }
313 }
314
315 static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq,
316 struct ath_atx_tid *tid)
317
318 {
319 struct sk_buff *skb;
320 struct ath_buf *bf;
321 struct list_head bf_head;
322 struct ath_tx_status ts;
323 struct ath_frame_info *fi;
324
325 memset(&ts, 0, sizeof(ts));
326 INIT_LIST_HEAD(&bf_head);
327
328 while ((skb = ath_tid_dequeue(tid))) {
329 fi = get_frame_info(skb);
330 bf = fi->bf;
331
332 if (!bf) {
333 ath_tx_complete(sc, skb, ATH_TX_ERROR, txq);
334 continue;
335 }
336
337 list_add_tail(&bf->list, &bf_head);
338 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0);
339 }
340 }
341
342 static void ath_tx_set_retry(struct ath_softc *sc, struct ath_txq *txq,
343 struct sk_buff *skb, int count)
344 {
345 struct ath_frame_info *fi = get_frame_info(skb);
346 struct ath_buf *bf = fi->bf;
347 struct ieee80211_hdr *hdr;
348 int prev = fi->retries;
349
350 TX_STAT_INC(txq->axq_qnum, a_retries);
351 fi->retries += count;
352
353 if (prev > 0)
354 return;
355
356 hdr = (struct ieee80211_hdr *)skb->data;
357 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY);
358 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
359 sizeof(*hdr), DMA_TO_DEVICE);
360 }
361
362 static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc)
363 {
364 struct ath_buf *bf = NULL;
365
366 spin_lock_bh(&sc->tx.txbuflock);
367
368 if (unlikely(list_empty(&sc->tx.txbuf))) {
369 spin_unlock_bh(&sc->tx.txbuflock);
370 return NULL;
371 }
372
373 bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list);
374 list_del(&bf->list);
375
376 spin_unlock_bh(&sc->tx.txbuflock);
377
378 return bf;
379 }
380
381 static void ath_tx_return_buffer(struct ath_softc *sc, struct ath_buf *bf)
382 {
383 spin_lock_bh(&sc->tx.txbuflock);
384 list_add_tail(&bf->list, &sc->tx.txbuf);
385 spin_unlock_bh(&sc->tx.txbuflock);
386 }
387
388 static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf)
389 {
390 struct ath_buf *tbf;
391
392 tbf = ath_tx_get_buffer(sc);
393 if (WARN_ON(!tbf))
394 return NULL;
395
396 ATH_TXBUF_RESET(tbf);
397
398 tbf->bf_mpdu = bf->bf_mpdu;
399 tbf->bf_buf_addr = bf->bf_buf_addr;
400 memcpy(tbf->bf_desc, bf->bf_desc, sc->sc_ah->caps.tx_desc_len);
401 tbf->bf_state = bf->bf_state;
402 tbf->bf_state.stale = false;
403
404 return tbf;
405 }
406
407 static void ath_tx_count_frames(struct ath_softc *sc, struct ath_buf *bf,
408 struct ath_tx_status *ts, int txok,
409 int *nframes, int *nbad)
410 {
411 struct ath_frame_info *fi;
412 u16 seq_st = 0;
413 u32 ba[WME_BA_BMP_SIZE >> 5];
414 int ba_index;
415 int isaggr = 0;
416
417 *nbad = 0;
418 *nframes = 0;
419
420 isaggr = bf_isaggr(bf);
421 if (isaggr) {
422 seq_st = ts->ts_seqnum;
423 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
424 }
425
426 while (bf) {
427 fi = get_frame_info(bf->bf_mpdu);
428 ba_index = ATH_BA_INDEX(seq_st, bf->bf_state.seqno);
429
430 (*nframes)++;
431 if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index)))
432 (*nbad)++;
433
434 bf = bf->bf_next;
435 }
436 }
437
438
439 static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
440 struct ath_buf *bf, struct list_head *bf_q,
441 struct ath_tx_status *ts, int txok)
442 {
443 struct ath_node *an = NULL;
444 struct sk_buff *skb;
445 struct ieee80211_sta *sta;
446 struct ieee80211_hw *hw = sc->hw;
447 struct ieee80211_hdr *hdr;
448 struct ieee80211_tx_info *tx_info;
449 struct ath_atx_tid *tid = NULL;
450 struct ath_buf *bf_next, *bf_last = bf->bf_lastbf;
451 struct list_head bf_head;
452 struct sk_buff_head bf_pending;
453 u16 seq_st = 0, acked_cnt = 0, txfail_cnt = 0, seq_first;
454 u32 ba[WME_BA_BMP_SIZE >> 5];
455 int isaggr, txfail, txpending, sendbar = 0, needreset = 0, nbad = 0;
456 bool rc_update = true, isba;
457 struct ieee80211_tx_rate rates[4];
458 struct ath_frame_info *fi;
459 int nframes;
460 bool flush = !!(ts->ts_status & ATH9K_TX_FLUSH);
461 int i, retries;
462 int bar_index = -1;
463
464 skb = bf->bf_mpdu;
465 hdr = (struct ieee80211_hdr *)skb->data;
466
467 tx_info = IEEE80211_SKB_CB(skb);
468
469 memcpy(rates, bf->rates, sizeof(rates));
470
471 retries = ts->ts_longretry + 1;
472 for (i = 0; i < ts->ts_rateindex; i++)
473 retries += rates[i].count;
474
475 rcu_read_lock();
476
477 sta = ieee80211_find_sta_by_ifaddr(hw, hdr->addr1, hdr->addr2);
478 if (!sta) {
479 rcu_read_unlock();
480
481 INIT_LIST_HEAD(&bf_head);
482 while (bf) {
483 bf_next = bf->bf_next;
484
485 if (!bf->bf_state.stale || bf_next != NULL)
486 list_move_tail(&bf->list, &bf_head);
487
488 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts, 0);
489
490 bf = bf_next;
491 }
492 return;
493 }
494
495 an = (struct ath_node *)sta->drv_priv;
496 tid = ath_get_skb_tid(sc, an, skb);
497 seq_first = tid->seq_start;
498 isba = ts->ts_flags & ATH9K_TX_BA;
499
500 /*
501 * The hardware occasionally sends a tx status for the wrong TID.
502 * In this case, the BA status cannot be considered valid and all
503 * subframes need to be retransmitted
504 *
505 * Only BlockAcks have a TID and therefore normal Acks cannot be
506 * checked
507 */
508 if (isba && tid->tidno != ts->tid)
509 txok = false;
510
511 isaggr = bf_isaggr(bf);
512 memset(ba, 0, WME_BA_BMP_SIZE >> 3);
513
514 if (isaggr && txok) {
515 if (ts->ts_flags & ATH9K_TX_BA) {
516 seq_st = ts->ts_seqnum;
517 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
518 } else {
519 /*
520 * AR5416 can become deaf/mute when BA
521 * issue happens. Chip needs to be reset.
522 * But AP code may have sychronization issues
523 * when perform internal reset in this routine.
524 * Only enable reset in STA mode for now.
525 */
526 if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION)
527 needreset = 1;
528 }
529 }
530
531 __skb_queue_head_init(&bf_pending);
532
533 ath_tx_count_frames(sc, bf, ts, txok, &nframes, &nbad);
534 while (bf) {
535 u16 seqno = bf->bf_state.seqno;
536
537 txfail = txpending = sendbar = 0;
538 bf_next = bf->bf_next;
539
540 skb = bf->bf_mpdu;
541 tx_info = IEEE80211_SKB_CB(skb);
542 fi = get_frame_info(skb);
543
544 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno) ||
545 !tid->active) {
546 /*
547 * Outside of the current BlockAck window,
548 * maybe part of a previous session
549 */
550 txfail = 1;
551 } else if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, seqno))) {
552 /* transmit completion, subframe is
553 * acked by block ack */
554 acked_cnt++;
555 } else if (!isaggr && txok) {
556 /* transmit completion */
557 acked_cnt++;
558 } else if (flush) {
559 txpending = 1;
560 } else if (fi->retries < ATH_MAX_SW_RETRIES) {
561 if (txok || !an->sleeping)
562 ath_tx_set_retry(sc, txq, bf->bf_mpdu,
563 retries);
564
565 txpending = 1;
566 } else {
567 txfail = 1;
568 txfail_cnt++;
569 bar_index = max_t(int, bar_index,
570 ATH_BA_INDEX(seq_first, seqno));
571 }
572
573 /*
574 * Make sure the last desc is reclaimed if it
575 * not a holding desc.
576 */
577 INIT_LIST_HEAD(&bf_head);
578 if (bf_next != NULL || !bf_last->bf_state.stale)
579 list_move_tail(&bf->list, &bf_head);
580
581 if (!txpending) {
582 /*
583 * complete the acked-ones/xretried ones; update
584 * block-ack window
585 */
586 ath_tx_update_baw(sc, tid, seqno);
587
588 if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) {
589 memcpy(tx_info->control.rates, rates, sizeof(rates));
590 ath_tx_rc_status(sc, bf, ts, nframes, nbad, txok);
591 rc_update = false;
592 }
593
594 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts,
595 !txfail);
596 } else {
597 if (tx_info->flags & IEEE80211_TX_STATUS_EOSP) {
598 tx_info->flags &= ~IEEE80211_TX_STATUS_EOSP;
599 ieee80211_sta_eosp(sta);
600 }
601 /* retry the un-acked ones */
602 if (bf->bf_next == NULL && bf_last->bf_state.stale) {
603 struct ath_buf *tbf;
604
605 tbf = ath_clone_txbuf(sc, bf_last);
606 /*
607 * Update tx baw and complete the
608 * frame with failed status if we
609 * run out of tx buf.
610 */
611 if (!tbf) {
612 ath_tx_update_baw(sc, tid, seqno);
613
614 ath_tx_complete_buf(sc, bf, txq,
615 &bf_head, ts, 0);
616 bar_index = max_t(int, bar_index,
617 ATH_BA_INDEX(seq_first, seqno));
618 break;
619 }
620
621 fi->bf = tbf;
622 }
623
624 /*
625 * Put this buffer to the temporary pending
626 * queue to retain ordering
627 */
628 __skb_queue_tail(&bf_pending, skb);
629 }
630
631 bf = bf_next;
632 }
633
634 /* prepend un-acked frames to the beginning of the pending frame queue */
635 if (!skb_queue_empty(&bf_pending)) {
636 if (an->sleeping)
637 ieee80211_sta_set_buffered(sta, tid->tidno, true);
638
639 skb_queue_splice_tail(&bf_pending, &tid->retry_q);
640 if (!an->sleeping) {
641 ath_tx_queue_tid(txq, tid);
642
643 if (ts->ts_status & (ATH9K_TXERR_FILT | ATH9K_TXERR_XRETRY))
644 tid->ac->clear_ps_filter = true;
645 }
646 }
647
648 if (bar_index >= 0) {
649 u16 bar_seq = ATH_BA_INDEX2SEQ(seq_first, bar_index);
650
651 if (BAW_WITHIN(tid->seq_start, tid->baw_size, bar_seq))
652 tid->bar_index = ATH_BA_INDEX(tid->seq_start, bar_seq);
653
654 ath_txq_unlock(sc, txq);
655 ath_send_bar(tid, ATH_BA_INDEX2SEQ(seq_first, bar_index + 1));
656 ath_txq_lock(sc, txq);
657 }
658
659 rcu_read_unlock();
660
661 if (needreset)
662 ath9k_queue_reset(sc, RESET_TYPE_TX_ERROR);
663 }
664
665 static bool bf_is_ampdu_not_probing(struct ath_buf *bf)
666 {
667 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(bf->bf_mpdu);
668 return bf_isampdu(bf) && !(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE);
669 }
670
671 static void ath_tx_process_buffer(struct ath_softc *sc, struct ath_txq *txq,
672 struct ath_tx_status *ts, struct ath_buf *bf,
673 struct list_head *bf_head)
674 {
675 struct ieee80211_tx_info *info;
676 bool txok, flush;
677
678 txok = !(ts->ts_status & ATH9K_TXERR_MASK);
679 flush = !!(ts->ts_status & ATH9K_TX_FLUSH);
680 txq->axq_tx_inprogress = false;
681
682 txq->axq_depth--;
683 if (bf_is_ampdu_not_probing(bf))
684 txq->axq_ampdu_depth--;
685
686 if (!bf_isampdu(bf)) {
687 if (!flush) {
688 info = IEEE80211_SKB_CB(bf->bf_mpdu);
689 memcpy(info->control.rates, bf->rates,
690 sizeof(info->control.rates));
691 ath_tx_rc_status(sc, bf, ts, 1, txok ? 0 : 1, txok);
692 }
693 ath_tx_complete_buf(sc, bf, txq, bf_head, ts, txok);
694 } else
695 ath_tx_complete_aggr(sc, txq, bf, bf_head, ts, txok);
696
697 if (!flush)
698 ath_txq_schedule(sc, txq);
699 }
700
701 static bool ath_lookup_legacy(struct ath_buf *bf)
702 {
703 struct sk_buff *skb;
704 struct ieee80211_tx_info *tx_info;
705 struct ieee80211_tx_rate *rates;
706 int i;
707
708 skb = bf->bf_mpdu;
709 tx_info = IEEE80211_SKB_CB(skb);
710 rates = tx_info->control.rates;
711
712 for (i = 0; i < 4; i++) {
713 if (!rates[i].count || rates[i].idx < 0)
714 break;
715
716 if (!(rates[i].flags & IEEE80211_TX_RC_MCS))
717 return true;
718 }
719
720 return false;
721 }
722
723 static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf,
724 struct ath_atx_tid *tid)
725 {
726 struct sk_buff *skb;
727 struct ieee80211_tx_info *tx_info;
728 struct ieee80211_tx_rate *rates;
729 u32 max_4ms_framelen, frmlen;
730 u16 aggr_limit, bt_aggr_limit, legacy = 0;
731 int q = tid->ac->txq->mac80211_qnum;
732 int i;
733
734 skb = bf->bf_mpdu;
735 tx_info = IEEE80211_SKB_CB(skb);
736 rates = bf->rates;
737
738 /*
739 * Find the lowest frame length among the rate series that will have a
740 * 4ms (or TXOP limited) transmit duration.
741 */
742 max_4ms_framelen = ATH_AMPDU_LIMIT_MAX;
743
744 for (i = 0; i < 4; i++) {
745 int modeidx;
746
747 if (!rates[i].count)
748 continue;
749
750 if (!(rates[i].flags & IEEE80211_TX_RC_MCS)) {
751 legacy = 1;
752 break;
753 }
754
755 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
756 modeidx = MCS_HT40;
757 else
758 modeidx = MCS_HT20;
759
760 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
761 modeidx++;
762
763 frmlen = sc->tx.max_aggr_framelen[q][modeidx][rates[i].idx];
764 max_4ms_framelen = min(max_4ms_framelen, frmlen);
765 }
766
767 /*
768 * limit aggregate size by the minimum rate if rate selected is
769 * not a probe rate, if rate selected is a probe rate then
770 * avoid aggregation of this packet.
771 */
772 if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy)
773 return 0;
774
775 aggr_limit = min(max_4ms_framelen, (u32)ATH_AMPDU_LIMIT_MAX);
776
777 /*
778 * Override the default aggregation limit for BTCOEX.
779 */
780 bt_aggr_limit = ath9k_btcoex_aggr_limit(sc, max_4ms_framelen);
781 if (bt_aggr_limit)
782 aggr_limit = bt_aggr_limit;
783
784 /*
785 * h/w can accept aggregates up to 16 bit lengths (65535).
786 * The IE, however can hold up to 65536, which shows up here
787 * as zero. Ignore 65536 since we are constrained by hw.
788 */
789 if (tid->an->maxampdu)
790 aggr_limit = min(aggr_limit, tid->an->maxampdu);
791
792 return aggr_limit;
793 }
794
795 /*
796 * Returns the number of delimiters to be added to
797 * meet the minimum required mpdudensity.
798 */
799 static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid,
800 struct ath_buf *bf, u16 frmlen,
801 bool first_subfrm)
802 {
803 #define FIRST_DESC_NDELIMS 60
804 u32 nsymbits, nsymbols;
805 u16 minlen;
806 u8 flags, rix;
807 int width, streams, half_gi, ndelim, mindelim;
808 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
809
810 /* Select standard number of delimiters based on frame length alone */
811 ndelim = ATH_AGGR_GET_NDELIM(frmlen);
812
813 /*
814 * If encryption enabled, hardware requires some more padding between
815 * subframes.
816 * TODO - this could be improved to be dependent on the rate.
817 * The hardware can keep up at lower rates, but not higher rates
818 */
819 if ((fi->keyix != ATH9K_TXKEYIX_INVALID) &&
820 !(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA))
821 ndelim += ATH_AGGR_ENCRYPTDELIM;
822
823 /*
824 * Add delimiter when using RTS/CTS with aggregation
825 * and non enterprise AR9003 card
826 */
827 if (first_subfrm && !AR_SREV_9580_10_OR_LATER(sc->sc_ah) &&
828 (sc->sc_ah->ent_mode & AR_ENT_OTP_MIN_PKT_SIZE_DISABLE))
829 ndelim = max(ndelim, FIRST_DESC_NDELIMS);
830
831 /*
832 * Convert desired mpdu density from microeconds to bytes based
833 * on highest rate in rate series (i.e. first rate) to determine
834 * required minimum length for subframe. Take into account
835 * whether high rate is 20 or 40Mhz and half or full GI.
836 *
837 * If there is no mpdu density restriction, no further calculation
838 * is needed.
839 */
840
841 if (tid->an->mpdudensity == 0)
842 return ndelim;
843
844 rix = bf->rates[0].idx;
845 flags = bf->rates[0].flags;
846 width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0;
847 half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0;
848
849 if (half_gi)
850 nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(tid->an->mpdudensity);
851 else
852 nsymbols = NUM_SYMBOLS_PER_USEC(tid->an->mpdudensity);
853
854 if (nsymbols == 0)
855 nsymbols = 1;
856
857 streams = HT_RC_2_STREAMS(rix);
858 nsymbits = bits_per_symbol[rix % 8][width] * streams;
859 minlen = (nsymbols * nsymbits) / BITS_PER_BYTE;
860
861 if (frmlen < minlen) {
862 mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ;
863 ndelim = max(mindelim, ndelim);
864 }
865
866 return ndelim;
867 }
868
869 static struct ath_buf *
870 ath_tx_get_tid_subframe(struct ath_softc *sc, struct ath_txq *txq,
871 struct ath_atx_tid *tid, struct sk_buff_head **q)
872 {
873 struct ieee80211_tx_info *tx_info;
874 struct ath_frame_info *fi;
875 struct sk_buff *skb;
876 struct ath_buf *bf;
877 u16 seqno;
878
879 while (1) {
880 *q = &tid->retry_q;
881 if (skb_queue_empty(*q))
882 *q = &tid->buf_q;
883
884 skb = skb_peek(*q);
885 if (!skb)
886 break;
887
888 fi = get_frame_info(skb);
889 bf = fi->bf;
890 if (!fi->bf)
891 bf = ath_tx_setup_buffer(sc, txq, tid, skb);
892 else
893 bf->bf_state.stale = false;
894
895 if (!bf) {
896 __skb_unlink(skb, *q);
897 ath_txq_skb_done(sc, txq, skb);
898 ieee80211_free_txskb(sc->hw, skb);
899 continue;
900 }
901
902 bf->bf_next = NULL;
903 bf->bf_lastbf = bf;
904
905 tx_info = IEEE80211_SKB_CB(skb);
906 tx_info->flags &= ~IEEE80211_TX_CTL_CLEAR_PS_FILT;
907 if (!(tx_info->flags & IEEE80211_TX_CTL_AMPDU)) {
908 bf->bf_state.bf_type = 0;
909 return bf;
910 }
911
912 bf->bf_state.bf_type = BUF_AMPDU | BUF_AGGR;
913 seqno = bf->bf_state.seqno;
914
915 /* do not step over block-ack window */
916 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno))
917 break;
918
919 if (tid->bar_index > ATH_BA_INDEX(tid->seq_start, seqno)) {
920 struct ath_tx_status ts = {};
921 struct list_head bf_head;
922
923 INIT_LIST_HEAD(&bf_head);
924 list_add(&bf->list, &bf_head);
925 __skb_unlink(skb, *q);
926 ath_tx_update_baw(sc, tid, seqno);
927 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0);
928 continue;
929 }
930
931 return bf;
932 }
933
934 return NULL;
935 }
936
937 static bool
938 ath_tx_form_aggr(struct ath_softc *sc, struct ath_txq *txq,
939 struct ath_atx_tid *tid, struct list_head *bf_q,
940 struct ath_buf *bf_first, struct sk_buff_head *tid_q,
941 int *aggr_len)
942 {
943 #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
944 struct ath_buf *bf = bf_first, *bf_prev = NULL;
945 int nframes = 0, ndelim;
946 u16 aggr_limit = 0, al = 0, bpad = 0,
947 al_delta, h_baw = tid->baw_size / 2;
948 struct ieee80211_tx_info *tx_info;
949 struct ath_frame_info *fi;
950 struct sk_buff *skb;
951 bool closed = false;
952
953 bf = bf_first;
954 aggr_limit = ath_lookup_rate(sc, bf, tid);
955
956 do {
957 skb = bf->bf_mpdu;
958 fi = get_frame_info(skb);
959
960 /* do not exceed aggregation limit */
961 al_delta = ATH_AGGR_DELIM_SZ + fi->framelen;
962 if (nframes) {
963 if (aggr_limit < al + bpad + al_delta ||
964 ath_lookup_legacy(bf) || nframes >= h_baw)
965 break;
966
967 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
968 if ((tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE) ||
969 !(tx_info->flags & IEEE80211_TX_CTL_AMPDU))
970 break;
971 }
972
973 /* add padding for previous frame to aggregation length */
974 al += bpad + al_delta;
975
976 /*
977 * Get the delimiters needed to meet the MPDU
978 * density for this node.
979 */
980 ndelim = ath_compute_num_delims(sc, tid, bf_first, fi->framelen,
981 !nframes);
982 bpad = PADBYTES(al_delta) + (ndelim << 2);
983
984 nframes++;
985 bf->bf_next = NULL;
986
987 /* link buffers of this frame to the aggregate */
988 if (!fi->baw_tracked)
989 ath_tx_addto_baw(sc, tid, bf);
990 bf->bf_state.ndelim = ndelim;
991
992 __skb_unlink(skb, tid_q);
993 list_add_tail(&bf->list, bf_q);
994 if (bf_prev)
995 bf_prev->bf_next = bf;
996
997 bf_prev = bf;
998
999 bf = ath_tx_get_tid_subframe(sc, txq, tid, &tid_q);
1000 if (!bf) {
1001 closed = true;
1002 break;
1003 }
1004 } while (ath_tid_has_buffered(tid));
1005
1006 bf = bf_first;
1007 bf->bf_lastbf = bf_prev;
1008
1009 if (bf == bf_prev) {
1010 al = get_frame_info(bf->bf_mpdu)->framelen;
1011 bf->bf_state.bf_type = BUF_AMPDU;
1012 } else {
1013 TX_STAT_INC(txq->axq_qnum, a_aggr);
1014 }
1015
1016 *aggr_len = al;
1017
1018 return closed;
1019 #undef PADBYTES
1020 }
1021
1022 /*
1023 * rix - rate index
1024 * pktlen - total bytes (delims + data + fcs + pads + pad delims)
1025 * width - 0 for 20 MHz, 1 for 40 MHz
1026 * half_gi - to use 4us v/s 3.6 us for symbol time
1027 */
1028 static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, int pktlen,
1029 int width, int half_gi, bool shortPreamble)
1030 {
1031 u32 nbits, nsymbits, duration, nsymbols;
1032 int streams;
1033
1034 /* find number of symbols: PLCP + data */
1035 streams = HT_RC_2_STREAMS(rix);
1036 nbits = (pktlen << 3) + OFDM_PLCP_BITS;
1037 nsymbits = bits_per_symbol[rix % 8][width] * streams;
1038 nsymbols = (nbits + nsymbits - 1) / nsymbits;
1039
1040 if (!half_gi)
1041 duration = SYMBOL_TIME(nsymbols);
1042 else
1043 duration = SYMBOL_TIME_HALFGI(nsymbols);
1044
1045 /* addup duration for legacy/ht training and signal fields */
1046 duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
1047
1048 return duration;
1049 }
1050
1051 static int ath_max_framelen(int usec, int mcs, bool ht40, bool sgi)
1052 {
1053 int streams = HT_RC_2_STREAMS(mcs);
1054 int symbols, bits;
1055 int bytes = 0;
1056
1057 symbols = sgi ? TIME_SYMBOLS_HALFGI(usec) : TIME_SYMBOLS(usec);
1058 bits = symbols * bits_per_symbol[mcs % 8][ht40] * streams;
1059 bits -= OFDM_PLCP_BITS;
1060 bytes = bits / 8;
1061 bytes -= L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
1062 if (bytes > 65532)
1063 bytes = 65532;
1064
1065 return bytes;
1066 }
1067
1068 void ath_update_max_aggr_framelen(struct ath_softc *sc, int queue, int txop)
1069 {
1070 u16 *cur_ht20, *cur_ht20_sgi, *cur_ht40, *cur_ht40_sgi;
1071 int mcs;
1072
1073 /* 4ms is the default (and maximum) duration */
1074 if (!txop || txop > 4096)
1075 txop = 4096;
1076
1077 cur_ht20 = sc->tx.max_aggr_framelen[queue][MCS_HT20];
1078 cur_ht20_sgi = sc->tx.max_aggr_framelen[queue][MCS_HT20_SGI];
1079 cur_ht40 = sc->tx.max_aggr_framelen[queue][MCS_HT40];
1080 cur_ht40_sgi = sc->tx.max_aggr_framelen[queue][MCS_HT40_SGI];
1081 for (mcs = 0; mcs < 32; mcs++) {
1082 cur_ht20[mcs] = ath_max_framelen(txop, mcs, false, false);
1083 cur_ht20_sgi[mcs] = ath_max_framelen(txop, mcs, false, true);
1084 cur_ht40[mcs] = ath_max_framelen(txop, mcs, true, false);
1085 cur_ht40_sgi[mcs] = ath_max_framelen(txop, mcs, true, true);
1086 }
1087 }
1088
1089 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf,
1090 struct ath_tx_info *info, int len, bool rts)
1091 {
1092 struct ath_hw *ah = sc->sc_ah;
1093 struct sk_buff *skb;
1094 struct ieee80211_tx_info *tx_info;
1095 struct ieee80211_tx_rate *rates;
1096 const struct ieee80211_rate *rate;
1097 struct ieee80211_hdr *hdr;
1098 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
1099 u32 rts_thresh = sc->hw->wiphy->rts_threshold;
1100 int i;
1101 u8 rix = 0;
1102
1103 skb = bf->bf_mpdu;
1104 tx_info = IEEE80211_SKB_CB(skb);
1105 rates = bf->rates;
1106 hdr = (struct ieee80211_hdr *)skb->data;
1107
1108 /* set dur_update_en for l-sig computation except for PS-Poll frames */
1109 info->dur_update = !ieee80211_is_pspoll(hdr->frame_control);
1110 info->rtscts_rate = fi->rtscts_rate;
1111
1112 for (i = 0; i < ARRAY_SIZE(bf->rates); i++) {
1113 bool is_40, is_sgi, is_sp;
1114 int phy;
1115
1116 if (!rates[i].count || (rates[i].idx < 0))
1117 continue;
1118
1119 rix = rates[i].idx;
1120 info->rates[i].Tries = rates[i].count;
1121
1122 /*
1123 * Handle RTS threshold for unaggregated HT frames.
1124 */
1125 if (bf_isampdu(bf) && !bf_isaggr(bf) &&
1126 (rates[i].flags & IEEE80211_TX_RC_MCS) &&
1127 unlikely(rts_thresh != (u32) -1)) {
1128 if (!rts_thresh || (len > rts_thresh))
1129 rts = true;
1130 }
1131
1132 if (rts || rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS) {
1133 info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1134 info->flags |= ATH9K_TXDESC_RTSENA;
1135 } else if (rates[i].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
1136 info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1137 info->flags |= ATH9K_TXDESC_CTSENA;
1138 }
1139
1140 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
1141 info->rates[i].RateFlags |= ATH9K_RATESERIES_2040;
1142 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
1143 info->rates[i].RateFlags |= ATH9K_RATESERIES_HALFGI;
1144
1145 is_sgi = !!(rates[i].flags & IEEE80211_TX_RC_SHORT_GI);
1146 is_40 = !!(rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH);
1147 is_sp = !!(rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE);
1148
1149 if (rates[i].flags & IEEE80211_TX_RC_MCS) {
1150 /* MCS rates */
1151 info->rates[i].Rate = rix | 0x80;
1152 info->rates[i].ChSel = ath_txchainmask_reduction(sc,
1153 ah->txchainmask, info->rates[i].Rate);
1154 info->rates[i].PktDuration = ath_pkt_duration(sc, rix, len,
1155 is_40, is_sgi, is_sp);
1156 if (rix < 8 && (tx_info->flags & IEEE80211_TX_CTL_STBC))
1157 info->rates[i].RateFlags |= ATH9K_RATESERIES_STBC;
1158 continue;
1159 }
1160
1161 /* legacy rates */
1162 rate = &sc->sbands[tx_info->band].bitrates[rates[i].idx];
1163 if ((tx_info->band == IEEE80211_BAND_2GHZ) &&
1164 !(rate->flags & IEEE80211_RATE_ERP_G))
1165 phy = WLAN_RC_PHY_CCK;
1166 else
1167 phy = WLAN_RC_PHY_OFDM;
1168
1169 info->rates[i].Rate = rate->hw_value;
1170 if (rate->hw_value_short) {
1171 if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
1172 info->rates[i].Rate |= rate->hw_value_short;
1173 } else {
1174 is_sp = false;
1175 }
1176
1177 if (bf->bf_state.bfs_paprd)
1178 info->rates[i].ChSel = ah->txchainmask;
1179 else
1180 info->rates[i].ChSel = ath_txchainmask_reduction(sc,
1181 ah->txchainmask, info->rates[i].Rate);
1182
1183 info->rates[i].PktDuration = ath9k_hw_computetxtime(sc->sc_ah,
1184 phy, rate->bitrate * 100, len, rix, is_sp);
1185 }
1186
1187 /* For AR5416 - RTS cannot be followed by a frame larger than 8K */
1188 if (bf_isaggr(bf) && (len > sc->sc_ah->caps.rts_aggr_limit))
1189 info->flags &= ~ATH9K_TXDESC_RTSENA;
1190
1191 /* ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive. */
1192 if (info->flags & ATH9K_TXDESC_RTSENA)
1193 info->flags &= ~ATH9K_TXDESC_CTSENA;
1194 }
1195
1196 static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb)
1197 {
1198 struct ieee80211_hdr *hdr;
1199 enum ath9k_pkt_type htype;
1200 __le16 fc;
1201
1202 hdr = (struct ieee80211_hdr *)skb->data;
1203 fc = hdr->frame_control;
1204
1205 if (ieee80211_is_beacon(fc))
1206 htype = ATH9K_PKT_TYPE_BEACON;
1207 else if (ieee80211_is_probe_resp(fc))
1208 htype = ATH9K_PKT_TYPE_PROBE_RESP;
1209 else if (ieee80211_is_atim(fc))
1210 htype = ATH9K_PKT_TYPE_ATIM;
1211 else if (ieee80211_is_pspoll(fc))
1212 htype = ATH9K_PKT_TYPE_PSPOLL;
1213 else
1214 htype = ATH9K_PKT_TYPE_NORMAL;
1215
1216 return htype;
1217 }
1218
1219 static void ath_tx_fill_desc(struct ath_softc *sc, struct ath_buf *bf,
1220 struct ath_txq *txq, int len)
1221 {
1222 struct ath_hw *ah = sc->sc_ah;
1223 struct ath_buf *bf_first = NULL;
1224 struct ath_tx_info info;
1225 u32 rts_thresh = sc->hw->wiphy->rts_threshold;
1226 bool rts = false;
1227
1228 memset(&info, 0, sizeof(info));
1229 info.is_first = true;
1230 info.is_last = true;
1231 info.txpower = MAX_RATE_POWER;
1232 info.qcu = txq->axq_qnum;
1233
1234 while (bf) {
1235 struct sk_buff *skb = bf->bf_mpdu;
1236 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1237 struct ath_frame_info *fi = get_frame_info(skb);
1238 bool aggr = !!(bf->bf_state.bf_type & BUF_AGGR);
1239
1240 info.type = get_hw_packet_type(skb);
1241 if (bf->bf_next)
1242 info.link = bf->bf_next->bf_daddr;
1243 else
1244 info.link = 0;
1245
1246 if (!bf_first) {
1247 bf_first = bf;
1248
1249 info.flags = ATH9K_TXDESC_INTREQ;
1250 if ((tx_info->flags & IEEE80211_TX_CTL_CLEAR_PS_FILT) ||
1251 txq == sc->tx.uapsdq)
1252 info.flags |= ATH9K_TXDESC_CLRDMASK;
1253
1254 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
1255 info.flags |= ATH9K_TXDESC_NOACK;
1256 if (tx_info->flags & IEEE80211_TX_CTL_LDPC)
1257 info.flags |= ATH9K_TXDESC_LDPC;
1258
1259 if (bf->bf_state.bfs_paprd)
1260 info.flags |= (u32) bf->bf_state.bfs_paprd <<
1261 ATH9K_TXDESC_PAPRD_S;
1262
1263 /*
1264 * mac80211 doesn't handle RTS threshold for HT because
1265 * the decision has to be taken based on AMPDU length
1266 * and aggregation is done entirely inside ath9k.
1267 * Set the RTS/CTS flag for the first subframe based
1268 * on the threshold.
1269 */
1270 if (aggr && (bf == bf_first) &&
1271 unlikely(rts_thresh != (u32) -1)) {
1272 /*
1273 * "len" is the size of the entire AMPDU.
1274 */
1275 if (!rts_thresh || (len > rts_thresh))
1276 rts = true;
1277 }
1278 ath_buf_set_rate(sc, bf, &info, len, rts);
1279 }
1280
1281 info.buf_addr[0] = bf->bf_buf_addr;
1282 info.buf_len[0] = skb->len;
1283 info.pkt_len = fi->framelen;
1284 info.keyix = fi->keyix;
1285 info.keytype = fi->keytype;
1286
1287 if (aggr) {
1288 if (bf == bf_first)
1289 info.aggr = AGGR_BUF_FIRST;
1290 else if (bf == bf_first->bf_lastbf)
1291 info.aggr = AGGR_BUF_LAST;
1292 else
1293 info.aggr = AGGR_BUF_MIDDLE;
1294
1295 info.ndelim = bf->bf_state.ndelim;
1296 info.aggr_len = len;
1297 }
1298
1299 if (bf == bf_first->bf_lastbf)
1300 bf_first = NULL;
1301
1302 ath9k_hw_set_txdesc(ah, bf->bf_desc, &info);
1303 bf = bf->bf_next;
1304 }
1305 }
1306
1307 static void
1308 ath_tx_form_burst(struct ath_softc *sc, struct ath_txq *txq,
1309 struct ath_atx_tid *tid, struct list_head *bf_q,
1310 struct ath_buf *bf_first, struct sk_buff_head *tid_q)
1311 {
1312 struct ath_buf *bf = bf_first, *bf_prev = NULL;
1313 struct sk_buff *skb;
1314 int nframes = 0;
1315
1316 do {
1317 struct ieee80211_tx_info *tx_info;
1318 skb = bf->bf_mpdu;
1319
1320 nframes++;
1321 __skb_unlink(skb, tid_q);
1322 list_add_tail(&bf->list, bf_q);
1323 if (bf_prev)
1324 bf_prev->bf_next = bf;
1325 bf_prev = bf;
1326
1327 if (nframes >= 2)
1328 break;
1329
1330 bf = ath_tx_get_tid_subframe(sc, txq, tid, &tid_q);
1331 if (!bf)
1332 break;
1333
1334 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
1335 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU)
1336 break;
1337
1338 ath_set_rates(tid->an->vif, tid->an->sta, bf);
1339 } while (1);
1340 }
1341
1342 static bool ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq,
1343 struct ath_atx_tid *tid, bool *stop)
1344 {
1345 struct ath_buf *bf;
1346 struct ieee80211_tx_info *tx_info;
1347 struct sk_buff_head *tid_q;
1348 struct list_head bf_q;
1349 int aggr_len = 0;
1350 bool aggr, last = true;
1351
1352 if (!ath_tid_has_buffered(tid))
1353 return false;
1354
1355 INIT_LIST_HEAD(&bf_q);
1356
1357 bf = ath_tx_get_tid_subframe(sc, txq, tid, &tid_q);
1358 if (!bf)
1359 return false;
1360
1361 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
1362 aggr = !!(tx_info->flags & IEEE80211_TX_CTL_AMPDU);
1363 if ((aggr && txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH) ||
1364 (!aggr && txq->axq_depth >= ATH_NON_AGGR_MIN_QDEPTH)) {
1365 *stop = true;
1366 return false;
1367 }
1368
1369 ath_set_rates(tid->an->vif, tid->an->sta, bf);
1370 if (aggr)
1371 last = ath_tx_form_aggr(sc, txq, tid, &bf_q, bf,
1372 tid_q, &aggr_len);
1373 else
1374 ath_tx_form_burst(sc, txq, tid, &bf_q, bf, tid_q);
1375
1376 if (list_empty(&bf_q))
1377 return false;
1378
1379 if (tid->ac->clear_ps_filter || tid->an->no_ps_filter) {
1380 tid->ac->clear_ps_filter = false;
1381 tx_info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT;
1382 }
1383
1384 ath_tx_fill_desc(sc, bf, txq, aggr_len);
1385 ath_tx_txqaddbuf(sc, txq, &bf_q, false);
1386 return true;
1387 }
1388
1389 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
1390 u16 tid, u16 *ssn)
1391 {
1392 struct ath_atx_tid *txtid;
1393 struct ath_txq *txq;
1394 struct ath_node *an;
1395 u8 density;
1396
1397 an = (struct ath_node *)sta->drv_priv;
1398 txtid = ATH_AN_2_TID(an, tid);
1399 txq = txtid->ac->txq;
1400
1401 ath_txq_lock(sc, txq);
1402
1403 /* update ampdu factor/density, they may have changed. This may happen
1404 * in HT IBSS when a beacon with HT-info is received after the station
1405 * has already been added.
1406 */
1407 if (sta->ht_cap.ht_supported) {
1408 an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
1409 sta->ht_cap.ampdu_factor);
1410 density = ath9k_parse_mpdudensity(sta->ht_cap.ampdu_density);
1411 an->mpdudensity = density;
1412 }
1413
1414 /* force sequence number allocation for pending frames */
1415 ath_tx_tid_change_state(sc, txtid);
1416
1417 txtid->active = true;
1418 txtid->paused = true;
1419 *ssn = txtid->seq_start = txtid->seq_next;
1420 txtid->bar_index = -1;
1421
1422 memset(txtid->tx_buf, 0, sizeof(txtid->tx_buf));
1423 txtid->baw_head = txtid->baw_tail = 0;
1424
1425 ath_txq_unlock_complete(sc, txq);
1426
1427 return 0;
1428 }
1429
1430 void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
1431 {
1432 struct ath_node *an = (struct ath_node *)sta->drv_priv;
1433 struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid);
1434 struct ath_txq *txq = txtid->ac->txq;
1435
1436 ath_txq_lock(sc, txq);
1437 txtid->active = false;
1438 txtid->paused = false;
1439 ath_tx_flush_tid(sc, txtid);
1440 ath_tx_tid_change_state(sc, txtid);
1441 ath_txq_unlock_complete(sc, txq);
1442 }
1443
1444 void ath_tx_aggr_sleep(struct ieee80211_sta *sta, struct ath_softc *sc,
1445 struct ath_node *an)
1446 {
1447 struct ath_atx_tid *tid;
1448 struct ath_atx_ac *ac;
1449 struct ath_txq *txq;
1450 bool buffered;
1451 int tidno;
1452
1453 for (tidno = 0, tid = &an->tid[tidno];
1454 tidno < IEEE80211_NUM_TIDS; tidno++, tid++) {
1455
1456 if (!tid->sched)
1457 continue;
1458
1459 ac = tid->ac;
1460 txq = ac->txq;
1461
1462 ath_txq_lock(sc, txq);
1463
1464 buffered = ath_tid_has_buffered(tid);
1465
1466 tid->sched = false;
1467 list_del(&tid->list);
1468
1469 if (ac->sched) {
1470 ac->sched = false;
1471 list_del(&ac->list);
1472 }
1473
1474 ath_txq_unlock(sc, txq);
1475
1476 ieee80211_sta_set_buffered(sta, tidno, buffered);
1477 }
1478 }
1479
1480 void ath_tx_aggr_wakeup(struct ath_softc *sc, struct ath_node *an)
1481 {
1482 struct ath_atx_tid *tid;
1483 struct ath_atx_ac *ac;
1484 struct ath_txq *txq;
1485 int tidno;
1486
1487 for (tidno = 0, tid = &an->tid[tidno];
1488 tidno < IEEE80211_NUM_TIDS; tidno++, tid++) {
1489
1490 ac = tid->ac;
1491 txq = ac->txq;
1492
1493 ath_txq_lock(sc, txq);
1494 ac->clear_ps_filter = true;
1495
1496 if (!tid->paused && ath_tid_has_buffered(tid)) {
1497 ath_tx_queue_tid(txq, tid);
1498 ath_txq_schedule(sc, txq);
1499 }
1500
1501 ath_txq_unlock_complete(sc, txq);
1502 }
1503 }
1504
1505 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta,
1506 u16 tidno)
1507 {
1508 struct ath_atx_tid *tid;
1509 struct ath_node *an;
1510 struct ath_txq *txq;
1511
1512 an = (struct ath_node *)sta->drv_priv;
1513 tid = ATH_AN_2_TID(an, tidno);
1514 txq = tid->ac->txq;
1515
1516 ath_txq_lock(sc, txq);
1517
1518 tid->baw_size = IEEE80211_MIN_AMPDU_BUF << sta->ht_cap.ampdu_factor;
1519 tid->paused = false;
1520
1521 if (ath_tid_has_buffered(tid)) {
1522 ath_tx_queue_tid(txq, tid);
1523 ath_txq_schedule(sc, txq);
1524 }
1525
1526 ath_txq_unlock_complete(sc, txq);
1527 }
1528
1529 void ath9k_release_buffered_frames(struct ieee80211_hw *hw,
1530 struct ieee80211_sta *sta,
1531 u16 tids, int nframes,
1532 enum ieee80211_frame_release_type reason,
1533 bool more_data)
1534 {
1535 struct ath_softc *sc = hw->priv;
1536 struct ath_node *an = (struct ath_node *)sta->drv_priv;
1537 struct ath_txq *txq = sc->tx.uapsdq;
1538 struct ieee80211_tx_info *info;
1539 struct list_head bf_q;
1540 struct ath_buf *bf_tail = NULL, *bf;
1541 struct sk_buff_head *tid_q;
1542 int sent = 0;
1543 int i;
1544
1545 INIT_LIST_HEAD(&bf_q);
1546 for (i = 0; tids && nframes; i++, tids >>= 1) {
1547 struct ath_atx_tid *tid;
1548
1549 if (!(tids & 1))
1550 continue;
1551
1552 tid = ATH_AN_2_TID(an, i);
1553 if (tid->paused)
1554 continue;
1555
1556 ath_txq_lock(sc, tid->ac->txq);
1557 while (nframes > 0) {
1558 bf = ath_tx_get_tid_subframe(sc, sc->tx.uapsdq, tid, &tid_q);
1559 if (!bf)
1560 break;
1561
1562 __skb_unlink(bf->bf_mpdu, tid_q);
1563 list_add_tail(&bf->list, &bf_q);
1564 ath_set_rates(tid->an->vif, tid->an->sta, bf);
1565 if (bf_isampdu(bf)) {
1566 ath_tx_addto_baw(sc, tid, bf);
1567 bf->bf_state.bf_type &= ~BUF_AGGR;
1568 }
1569 if (bf_tail)
1570 bf_tail->bf_next = bf;
1571
1572 bf_tail = bf;
1573 nframes--;
1574 sent++;
1575 TX_STAT_INC(txq->axq_qnum, a_queued_hw);
1576
1577 if (an->sta && !ath_tid_has_buffered(tid))
1578 ieee80211_sta_set_buffered(an->sta, i, false);
1579 }
1580 ath_txq_unlock_complete(sc, tid->ac->txq);
1581 }
1582
1583 if (list_empty(&bf_q))
1584 return;
1585
1586 info = IEEE80211_SKB_CB(bf_tail->bf_mpdu);
1587 info->flags |= IEEE80211_TX_STATUS_EOSP;
1588
1589 bf = list_first_entry(&bf_q, struct ath_buf, list);
1590 ath_txq_lock(sc, txq);
1591 ath_tx_fill_desc(sc, bf, txq, 0);
1592 ath_tx_txqaddbuf(sc, txq, &bf_q, false);
1593 ath_txq_unlock(sc, txq);
1594 }
1595
1596 /********************/
1597 /* Queue Management */
1598 /********************/
1599
1600 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
1601 {
1602 struct ath_hw *ah = sc->sc_ah;
1603 struct ath9k_tx_queue_info qi;
1604 static const int subtype_txq_to_hwq[] = {
1605 [IEEE80211_AC_BE] = ATH_TXQ_AC_BE,
1606 [IEEE80211_AC_BK] = ATH_TXQ_AC_BK,
1607 [IEEE80211_AC_VI] = ATH_TXQ_AC_VI,
1608 [IEEE80211_AC_VO] = ATH_TXQ_AC_VO,
1609 };
1610 int axq_qnum, i;
1611
1612 memset(&qi, 0, sizeof(qi));
1613 qi.tqi_subtype = subtype_txq_to_hwq[subtype];
1614 qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT;
1615 qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
1616 qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT;
1617 qi.tqi_physCompBuf = 0;
1618
1619 /*
1620 * Enable interrupts only for EOL and DESC conditions.
1621 * We mark tx descriptors to receive a DESC interrupt
1622 * when a tx queue gets deep; otherwise waiting for the
1623 * EOL to reap descriptors. Note that this is done to
1624 * reduce interrupt load and this only defers reaping
1625 * descriptors, never transmitting frames. Aside from
1626 * reducing interrupts this also permits more concurrency.
1627 * The only potential downside is if the tx queue backs
1628 * up in which case the top half of the kernel may backup
1629 * due to a lack of tx descriptors.
1630 *
1631 * The UAPSD queue is an exception, since we take a desc-
1632 * based intr on the EOSP frames.
1633 */
1634 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1635 qi.tqi_qflags = TXQ_FLAG_TXINT_ENABLE;
1636 } else {
1637 if (qtype == ATH9K_TX_QUEUE_UAPSD)
1638 qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE;
1639 else
1640 qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE |
1641 TXQ_FLAG_TXDESCINT_ENABLE;
1642 }
1643 axq_qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi);
1644 if (axq_qnum == -1) {
1645 /*
1646 * NB: don't print a message, this happens
1647 * normally on parts with too few tx queues
1648 */
1649 return NULL;
1650 }
1651 if (!ATH_TXQ_SETUP(sc, axq_qnum)) {
1652 struct ath_txq *txq = &sc->tx.txq[axq_qnum];
1653
1654 txq->axq_qnum = axq_qnum;
1655 txq->mac80211_qnum = -1;
1656 txq->axq_link = NULL;
1657 __skb_queue_head_init(&txq->complete_q);
1658 INIT_LIST_HEAD(&txq->axq_q);
1659 INIT_LIST_HEAD(&txq->axq_acq);
1660 spin_lock_init(&txq->axq_lock);
1661 txq->axq_depth = 0;
1662 txq->axq_ampdu_depth = 0;
1663 txq->axq_tx_inprogress = false;
1664 sc->tx.txqsetup |= 1<<axq_qnum;
1665
1666 txq->txq_headidx = txq->txq_tailidx = 0;
1667 for (i = 0; i < ATH_TXFIFO_DEPTH; i++)
1668 INIT_LIST_HEAD(&txq->txq_fifo[i]);
1669 }
1670 return &sc->tx.txq[axq_qnum];
1671 }
1672
1673 int ath_txq_update(struct ath_softc *sc, int qnum,
1674 struct ath9k_tx_queue_info *qinfo)
1675 {
1676 struct ath_hw *ah = sc->sc_ah;
1677 int error = 0;
1678 struct ath9k_tx_queue_info qi;
1679
1680 BUG_ON(sc->tx.txq[qnum].axq_qnum != qnum);
1681
1682 ath9k_hw_get_txq_props(ah, qnum, &qi);
1683 qi.tqi_aifs = qinfo->tqi_aifs;
1684 qi.tqi_cwmin = qinfo->tqi_cwmin;
1685 qi.tqi_cwmax = qinfo->tqi_cwmax;
1686 qi.tqi_burstTime = qinfo->tqi_burstTime;
1687 qi.tqi_readyTime = qinfo->tqi_readyTime;
1688
1689 if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) {
1690 ath_err(ath9k_hw_common(sc->sc_ah),
1691 "Unable to update hardware queue %u!\n", qnum);
1692 error = -EIO;
1693 } else {
1694 ath9k_hw_resettxqueue(ah, qnum);
1695 }
1696
1697 return error;
1698 }
1699
1700 int ath_cabq_update(struct ath_softc *sc)
1701 {
1702 struct ath9k_tx_queue_info qi;
1703 struct ath_beacon_config *cur_conf = &sc->cur_beacon_conf;
1704 int qnum = sc->beacon.cabq->axq_qnum;
1705
1706 ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi);
1707 /*
1708 * Ensure the readytime % is within the bounds.
1709 */
1710 if (sc->config.cabqReadytime < ATH9K_READY_TIME_LO_BOUND)
1711 sc->config.cabqReadytime = ATH9K_READY_TIME_LO_BOUND;
1712 else if (sc->config.cabqReadytime > ATH9K_READY_TIME_HI_BOUND)
1713 sc->config.cabqReadytime = ATH9K_READY_TIME_HI_BOUND;
1714
1715 qi.tqi_readyTime = (cur_conf->beacon_interval *
1716 sc->config.cabqReadytime) / 100;
1717 ath_txq_update(sc, qnum, &qi);
1718
1719 return 0;
1720 }
1721
1722 static void ath_drain_txq_list(struct ath_softc *sc, struct ath_txq *txq,
1723 struct list_head *list)
1724 {
1725 struct ath_buf *bf, *lastbf;
1726 struct list_head bf_head;
1727 struct ath_tx_status ts;
1728
1729 memset(&ts, 0, sizeof(ts));
1730 ts.ts_status = ATH9K_TX_FLUSH;
1731 INIT_LIST_HEAD(&bf_head);
1732
1733 while (!list_empty(list)) {
1734 bf = list_first_entry(list, struct ath_buf, list);
1735
1736 if (bf->bf_state.stale) {
1737 list_del(&bf->list);
1738
1739 ath_tx_return_buffer(sc, bf);
1740 continue;
1741 }
1742
1743 lastbf = bf->bf_lastbf;
1744 list_cut_position(&bf_head, list, &lastbf->list);
1745 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
1746 }
1747 }
1748
1749 /*
1750 * Drain a given TX queue (could be Beacon or Data)
1751 *
1752 * This assumes output has been stopped and
1753 * we do not need to block ath_tx_tasklet.
1754 */
1755 void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq)
1756 {
1757 ath_txq_lock(sc, txq);
1758
1759 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1760 int idx = txq->txq_tailidx;
1761
1762 while (!list_empty(&txq->txq_fifo[idx])) {
1763 ath_drain_txq_list(sc, txq, &txq->txq_fifo[idx]);
1764
1765 INCR(idx, ATH_TXFIFO_DEPTH);
1766 }
1767 txq->txq_tailidx = idx;
1768 }
1769
1770 txq->axq_link = NULL;
1771 txq->axq_tx_inprogress = false;
1772 ath_drain_txq_list(sc, txq, &txq->axq_q);
1773
1774 ath_txq_unlock_complete(sc, txq);
1775 }
1776
1777 bool ath_drain_all_txq(struct ath_softc *sc)
1778 {
1779 struct ath_hw *ah = sc->sc_ah;
1780 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1781 struct ath_txq *txq;
1782 int i;
1783 u32 npend = 0;
1784
1785 if (test_bit(SC_OP_INVALID, &sc->sc_flags))
1786 return true;
1787
1788 ath9k_hw_abort_tx_dma(ah);
1789
1790 /* Check if any queue remains active */
1791 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1792 if (!ATH_TXQ_SETUP(sc, i))
1793 continue;
1794
1795 if (ath9k_hw_numtxpending(ah, sc->tx.txq[i].axq_qnum))
1796 npend |= BIT(i);
1797 }
1798
1799 if (npend)
1800 ath_err(common, "Failed to stop TX DMA, queues=0x%03x!\n", npend);
1801
1802 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1803 if (!ATH_TXQ_SETUP(sc, i))
1804 continue;
1805
1806 /*
1807 * The caller will resume queues with ieee80211_wake_queues.
1808 * Mark the queue as not stopped to prevent ath_tx_complete
1809 * from waking the queue too early.
1810 */
1811 txq = &sc->tx.txq[i];
1812 txq->stopped = false;
1813 ath_draintxq(sc, txq);
1814 }
1815
1816 return !npend;
1817 }
1818
1819 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
1820 {
1821 ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum);
1822 sc->tx.txqsetup &= ~(1<<txq->axq_qnum);
1823 }
1824
1825 /* For each axq_acq entry, for each tid, try to schedule packets
1826 * for transmit until ampdu_depth has reached min Q depth.
1827 */
1828 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq)
1829 {
1830 struct ath_atx_ac *ac, *last_ac;
1831 struct ath_atx_tid *tid, *last_tid;
1832 bool sent = false;
1833
1834 if (test_bit(SC_OP_HW_RESET, &sc->sc_flags) ||
1835 list_empty(&txq->axq_acq))
1836 return;
1837
1838 rcu_read_lock();
1839
1840 last_ac = list_entry(txq->axq_acq.prev, struct ath_atx_ac, list);
1841 while (!list_empty(&txq->axq_acq)) {
1842 bool stop = false;
1843
1844 ac = list_first_entry(&txq->axq_acq, struct ath_atx_ac, list);
1845 last_tid = list_entry(ac->tid_q.prev, struct ath_atx_tid, list);
1846 list_del(&ac->list);
1847 ac->sched = false;
1848
1849 while (!list_empty(&ac->tid_q)) {
1850
1851 tid = list_first_entry(&ac->tid_q, struct ath_atx_tid,
1852 list);
1853 list_del(&tid->list);
1854 tid->sched = false;
1855
1856 if (tid->paused)
1857 continue;
1858
1859 if (ath_tx_sched_aggr(sc, txq, tid, &stop))
1860 sent = true;
1861
1862 /*
1863 * add tid to round-robin queue if more frames
1864 * are pending for the tid
1865 */
1866 if (ath_tid_has_buffered(tid))
1867 ath_tx_queue_tid(txq, tid);
1868
1869 if (stop || tid == last_tid)
1870 break;
1871 }
1872
1873 if (!list_empty(&ac->tid_q) && !ac->sched) {
1874 ac->sched = true;
1875 list_add_tail(&ac->list, &txq->axq_acq);
1876 }
1877
1878 if (stop)
1879 break;
1880
1881 if (ac == last_ac) {
1882 if (!sent)
1883 break;
1884
1885 sent = false;
1886 last_ac = list_entry(txq->axq_acq.prev,
1887 struct ath_atx_ac, list);
1888 }
1889 }
1890
1891 rcu_read_unlock();
1892 }
1893
1894 /***********/
1895 /* TX, DMA */
1896 /***********/
1897
1898 /*
1899 * Insert a chain of ath_buf (descriptors) on a txq and
1900 * assume the descriptors are already chained together by caller.
1901 */
1902 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
1903 struct list_head *head, bool internal)
1904 {
1905 struct ath_hw *ah = sc->sc_ah;
1906 struct ath_common *common = ath9k_hw_common(ah);
1907 struct ath_buf *bf, *bf_last;
1908 bool puttxbuf = false;
1909 bool edma;
1910
1911 /*
1912 * Insert the frame on the outbound list and
1913 * pass it on to the hardware.
1914 */
1915
1916 if (list_empty(head))
1917 return;
1918
1919 edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
1920 bf = list_first_entry(head, struct ath_buf, list);
1921 bf_last = list_entry(head->prev, struct ath_buf, list);
1922
1923 ath_dbg(common, QUEUE, "qnum: %d, txq depth: %d\n",
1924 txq->axq_qnum, txq->axq_depth);
1925
1926 if (edma && list_empty(&txq->txq_fifo[txq->txq_headidx])) {
1927 list_splice_tail_init(head, &txq->txq_fifo[txq->txq_headidx]);
1928 INCR(txq->txq_headidx, ATH_TXFIFO_DEPTH);
1929 puttxbuf = true;
1930 } else {
1931 list_splice_tail_init(head, &txq->axq_q);
1932
1933 if (txq->axq_link) {
1934 ath9k_hw_set_desc_link(ah, txq->axq_link, bf->bf_daddr);
1935 ath_dbg(common, XMIT, "link[%u] (%p)=%llx (%p)\n",
1936 txq->axq_qnum, txq->axq_link,
1937 ito64(bf->bf_daddr), bf->bf_desc);
1938 } else if (!edma)
1939 puttxbuf = true;
1940
1941 txq->axq_link = bf_last->bf_desc;
1942 }
1943
1944 if (puttxbuf) {
1945 TX_STAT_INC(txq->axq_qnum, puttxbuf);
1946 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
1947 ath_dbg(common, XMIT, "TXDP[%u] = %llx (%p)\n",
1948 txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc);
1949 }
1950
1951 if (!edma) {
1952 TX_STAT_INC(txq->axq_qnum, txstart);
1953 ath9k_hw_txstart(ah, txq->axq_qnum);
1954 }
1955
1956 if (!internal) {
1957 while (bf) {
1958 txq->axq_depth++;
1959 if (bf_is_ampdu_not_probing(bf))
1960 txq->axq_ampdu_depth++;
1961
1962 bf_last = bf->bf_lastbf;
1963 bf = bf_last->bf_next;
1964 bf_last->bf_next = NULL;
1965 }
1966 }
1967 }
1968
1969 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
1970 struct ath_atx_tid *tid, struct sk_buff *skb)
1971 {
1972 struct ath_frame_info *fi = get_frame_info(skb);
1973 struct list_head bf_head;
1974 struct ath_buf *bf;
1975
1976 bf = fi->bf;
1977
1978 INIT_LIST_HEAD(&bf_head);
1979 list_add_tail(&bf->list, &bf_head);
1980 bf->bf_state.bf_type = 0;
1981
1982 bf->bf_next = NULL;
1983 bf->bf_lastbf = bf;
1984 ath_tx_fill_desc(sc, bf, txq, fi->framelen);
1985 ath_tx_txqaddbuf(sc, txq, &bf_head, false);
1986 TX_STAT_INC(txq->axq_qnum, queued);
1987 }
1988
1989 static void setup_frame_info(struct ieee80211_hw *hw,
1990 struct ieee80211_sta *sta,
1991 struct sk_buff *skb,
1992 int framelen)
1993 {
1994 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1995 struct ieee80211_key_conf *hw_key = tx_info->control.hw_key;
1996 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1997 const struct ieee80211_rate *rate;
1998 struct ath_frame_info *fi = get_frame_info(skb);
1999 struct ath_node *an = NULL;
2000 enum ath9k_key_type keytype;
2001 bool short_preamble = false;
2002
2003 /*
2004 * We check if Short Preamble is needed for the CTS rate by
2005 * checking the BSS's global flag.
2006 * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used.
2007 */
2008 if (tx_info->control.vif &&
2009 tx_info->control.vif->bss_conf.use_short_preamble)
2010 short_preamble = true;
2011
2012 rate = ieee80211_get_rts_cts_rate(hw, tx_info);
2013 keytype = ath9k_cmn_get_hw_crypto_keytype(skb);
2014
2015 if (sta)
2016 an = (struct ath_node *) sta->drv_priv;
2017
2018 memset(fi, 0, sizeof(*fi));
2019 if (hw_key)
2020 fi->keyix = hw_key->hw_key_idx;
2021 else if (an && ieee80211_is_data(hdr->frame_control) && an->ps_key > 0)
2022 fi->keyix = an->ps_key;
2023 else
2024 fi->keyix = ATH9K_TXKEYIX_INVALID;
2025 fi->keytype = keytype;
2026 fi->framelen = framelen;
2027 fi->rtscts_rate = rate->hw_value;
2028 if (short_preamble)
2029 fi->rtscts_rate |= rate->hw_value_short;
2030 }
2031
2032 u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate)
2033 {
2034 struct ath_hw *ah = sc->sc_ah;
2035 struct ath9k_channel *curchan = ah->curchan;
2036
2037 if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) &&
2038 (curchan->channelFlags & CHANNEL_5GHZ) &&
2039 (chainmask == 0x7) && (rate < 0x90))
2040 return 0x3;
2041 else if (AR_SREV_9462(ah) && ath9k_hw_btcoex_is_enabled(ah) &&
2042 IS_CCK_RATE(rate))
2043 return 0x2;
2044 else
2045 return chainmask;
2046 }
2047
2048 /*
2049 * Assign a descriptor (and sequence number if necessary,
2050 * and map buffer for DMA. Frees skb on error
2051 */
2052 static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc,
2053 struct ath_txq *txq,
2054 struct ath_atx_tid *tid,
2055 struct sk_buff *skb)
2056 {
2057 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2058 struct ath_frame_info *fi = get_frame_info(skb);
2059 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
2060 struct ath_buf *bf;
2061 int fragno;
2062 u16 seqno;
2063
2064 bf = ath_tx_get_buffer(sc);
2065 if (!bf) {
2066 ath_dbg(common, XMIT, "TX buffers are full\n");
2067 return NULL;
2068 }
2069
2070 ATH_TXBUF_RESET(bf);
2071
2072 if (tid) {
2073 fragno = le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG;
2074 seqno = tid->seq_next;
2075 hdr->seq_ctrl = cpu_to_le16(tid->seq_next << IEEE80211_SEQ_SEQ_SHIFT);
2076
2077 if (fragno)
2078 hdr->seq_ctrl |= cpu_to_le16(fragno);
2079
2080 if (!ieee80211_has_morefrags(hdr->frame_control))
2081 INCR(tid->seq_next, IEEE80211_SEQ_MAX);
2082
2083 bf->bf_state.seqno = seqno;
2084 }
2085
2086 bf->bf_mpdu = skb;
2087
2088 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
2089 skb->len, DMA_TO_DEVICE);
2090 if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) {
2091 bf->bf_mpdu = NULL;
2092 bf->bf_buf_addr = 0;
2093 ath_err(ath9k_hw_common(sc->sc_ah),
2094 "dma_mapping_error() on TX\n");
2095 ath_tx_return_buffer(sc, bf);
2096 return NULL;
2097 }
2098
2099 fi->bf = bf;
2100
2101 return bf;
2102 }
2103
2104 static int ath_tx_prepare(struct ieee80211_hw *hw, struct sk_buff *skb,
2105 struct ath_tx_control *txctl)
2106 {
2107 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2108 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2109 struct ieee80211_sta *sta = txctl->sta;
2110 struct ieee80211_vif *vif = info->control.vif;
2111 struct ath_vif *avp;
2112 struct ath_softc *sc = hw->priv;
2113 int frmlen = skb->len + FCS_LEN;
2114 int padpos, padsize;
2115
2116 /* NOTE: sta can be NULL according to net/mac80211.h */
2117 if (sta)
2118 txctl->an = (struct ath_node *)sta->drv_priv;
2119 else if (vif && ieee80211_is_data(hdr->frame_control)) {
2120 avp = (void *)vif->drv_priv;
2121 txctl->an = &avp->mcast_node;
2122 }
2123
2124 if (info->control.hw_key)
2125 frmlen += info->control.hw_key->icv_len;
2126
2127 /*
2128 * As a temporary workaround, assign seq# here; this will likely need
2129 * to be cleaned up to work better with Beacon transmission and virtual
2130 * BSSes.
2131 */
2132 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
2133 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
2134 sc->tx.seq_no += 0x10;
2135 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
2136 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
2137 }
2138
2139 if ((vif && vif->type != NL80211_IFTYPE_AP &&
2140 vif->type != NL80211_IFTYPE_AP_VLAN) ||
2141 !ieee80211_is_data(hdr->frame_control))
2142 info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT;
2143
2144 /* Add the padding after the header if this is not already done */
2145 padpos = ieee80211_hdrlen(hdr->frame_control);
2146 padsize = padpos & 3;
2147 if (padsize && skb->len > padpos) {
2148 if (skb_headroom(skb) < padsize)
2149 return -ENOMEM;
2150
2151 skb_push(skb, padsize);
2152 memmove(skb->data, skb->data + padsize, padpos);
2153 }
2154
2155 setup_frame_info(hw, sta, skb, frmlen);
2156 return 0;
2157 }
2158
2159
2160 /* Upon failure caller should free skb */
2161 int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
2162 struct ath_tx_control *txctl)
2163 {
2164 struct ieee80211_hdr *hdr;
2165 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2166 struct ieee80211_sta *sta = txctl->sta;
2167 struct ieee80211_vif *vif = info->control.vif;
2168 struct ath_softc *sc = hw->priv;
2169 struct ath_txq *txq = txctl->txq;
2170 struct ath_atx_tid *tid = NULL;
2171 struct ath_buf *bf;
2172 int q;
2173 int ret;
2174
2175 ret = ath_tx_prepare(hw, skb, txctl);
2176 if (ret)
2177 return ret;
2178
2179 hdr = (struct ieee80211_hdr *) skb->data;
2180 /*
2181 * At this point, the vif, hw_key and sta pointers in the tx control
2182 * info are no longer valid (overwritten by the ath_frame_info data.
2183 */
2184
2185 q = skb_get_queue_mapping(skb);
2186
2187 ath_txq_lock(sc, txq);
2188 if (txq == sc->tx.txq_map[q] &&
2189 ++txq->pending_frames > sc->tx.txq_max_pending[q] &&
2190 !txq->stopped) {
2191 ieee80211_stop_queue(sc->hw, q);
2192 txq->stopped = true;
2193 }
2194
2195 if (info->flags & IEEE80211_TX_CTL_PS_RESPONSE) {
2196 ath_txq_unlock(sc, txq);
2197 txq = sc->tx.uapsdq;
2198 ath_txq_lock(sc, txq);
2199 } else if (txctl->an &&
2200 ieee80211_is_data_present(hdr->frame_control)) {
2201 tid = ath_get_skb_tid(sc, txctl->an, skb);
2202
2203 WARN_ON(tid->ac->txq != txctl->txq);
2204
2205 if (info->flags & IEEE80211_TX_CTL_CLEAR_PS_FILT)
2206 tid->ac->clear_ps_filter = true;
2207
2208 /*
2209 * Add this frame to software queue for scheduling later
2210 * for aggregation.
2211 */
2212 TX_STAT_INC(txq->axq_qnum, a_queued_sw);
2213 __skb_queue_tail(&tid->buf_q, skb);
2214 if (!txctl->an->sleeping)
2215 ath_tx_queue_tid(txq, tid);
2216
2217 ath_txq_schedule(sc, txq);
2218 goto out;
2219 }
2220
2221 bf = ath_tx_setup_buffer(sc, txq, tid, skb);
2222 if (!bf) {
2223 ath_txq_skb_done(sc, txq, skb);
2224 if (txctl->paprd)
2225 dev_kfree_skb_any(skb);
2226 else
2227 ieee80211_free_txskb(sc->hw, skb);
2228 goto out;
2229 }
2230
2231 bf->bf_state.bfs_paprd = txctl->paprd;
2232
2233 if (txctl->paprd)
2234 bf->bf_state.bfs_paprd_timestamp = jiffies;
2235
2236 ath_set_rates(vif, sta, bf);
2237 ath_tx_send_normal(sc, txq, tid, skb);
2238
2239 out:
2240 ath_txq_unlock(sc, txq);
2241
2242 return 0;
2243 }
2244
2245 void ath_tx_cabq(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2246 struct sk_buff *skb)
2247 {
2248 struct ath_softc *sc = hw->priv;
2249 struct ath_tx_control txctl = {
2250 .txq = sc->beacon.cabq
2251 };
2252 struct ath_tx_info info = {};
2253 struct ieee80211_hdr *hdr;
2254 struct ath_buf *bf_tail = NULL;
2255 struct ath_buf *bf;
2256 LIST_HEAD(bf_q);
2257 int duration = 0;
2258 int max_duration;
2259
2260 max_duration =
2261 sc->cur_beacon_conf.beacon_interval * 1000 *
2262 sc->cur_beacon_conf.dtim_period / ATH_BCBUF;
2263
2264 do {
2265 struct ath_frame_info *fi = get_frame_info(skb);
2266
2267 if (ath_tx_prepare(hw, skb, &txctl))
2268 break;
2269
2270 bf = ath_tx_setup_buffer(sc, txctl.txq, NULL, skb);
2271 if (!bf)
2272 break;
2273
2274 bf->bf_lastbf = bf;
2275 ath_set_rates(vif, NULL, bf);
2276 ath_buf_set_rate(sc, bf, &info, fi->framelen, false);
2277 duration += info.rates[0].PktDuration;
2278 if (bf_tail)
2279 bf_tail->bf_next = bf;
2280
2281 list_add_tail(&bf->list, &bf_q);
2282 bf_tail = bf;
2283 skb = NULL;
2284
2285 if (duration > max_duration)
2286 break;
2287
2288 skb = ieee80211_get_buffered_bc(hw, vif);
2289 } while(skb);
2290
2291 if (skb)
2292 ieee80211_free_txskb(hw, skb);
2293
2294 if (list_empty(&bf_q))
2295 return;
2296
2297 bf = list_first_entry(&bf_q, struct ath_buf, list);
2298 hdr = (struct ieee80211_hdr *) bf->bf_mpdu->data;
2299
2300 if (hdr->frame_control & IEEE80211_FCTL_MOREDATA) {
2301 hdr->frame_control &= ~IEEE80211_FCTL_MOREDATA;
2302 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
2303 sizeof(*hdr), DMA_TO_DEVICE);
2304 }
2305
2306 ath_txq_lock(sc, txctl.txq);
2307 ath_tx_fill_desc(sc, bf, txctl.txq, 0);
2308 ath_tx_txqaddbuf(sc, txctl.txq, &bf_q, false);
2309 TX_STAT_INC(txctl.txq->axq_qnum, queued);
2310 ath_txq_unlock(sc, txctl.txq);
2311 }
2312
2313 /*****************/
2314 /* TX Completion */
2315 /*****************/
2316
2317 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
2318 int tx_flags, struct ath_txq *txq)
2319 {
2320 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2321 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2322 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data;
2323 int padpos, padsize;
2324 unsigned long flags;
2325
2326 ath_dbg(common, XMIT, "TX complete: skb: %p\n", skb);
2327
2328 if (sc->sc_ah->caldata)
2329 sc->sc_ah->caldata->paprd_packet_sent = true;
2330
2331 if (!(tx_flags & ATH_TX_ERROR))
2332 /* Frame was ACKed */
2333 tx_info->flags |= IEEE80211_TX_STAT_ACK;
2334
2335 padpos = ieee80211_hdrlen(hdr->frame_control);
2336 padsize = padpos & 3;
2337 if (padsize && skb->len>padpos+padsize) {
2338 /*
2339 * Remove MAC header padding before giving the frame back to
2340 * mac80211.
2341 */
2342 memmove(skb->data + padsize, skb->data, padpos);
2343 skb_pull(skb, padsize);
2344 }
2345
2346 spin_lock_irqsave(&sc->sc_pm_lock, flags);
2347 if ((sc->ps_flags & PS_WAIT_FOR_TX_ACK) && !txq->axq_depth) {
2348 sc->ps_flags &= ~PS_WAIT_FOR_TX_ACK;
2349 ath_dbg(common, PS,
2350 "Going back to sleep after having received TX status (0x%lx)\n",
2351 sc->ps_flags & (PS_WAIT_FOR_BEACON |
2352 PS_WAIT_FOR_CAB |
2353 PS_WAIT_FOR_PSPOLL_DATA |
2354 PS_WAIT_FOR_TX_ACK));
2355 }
2356 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
2357
2358 __skb_queue_tail(&txq->complete_q, skb);
2359 ath_txq_skb_done(sc, txq, skb);
2360 }
2361
2362 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
2363 struct ath_txq *txq, struct list_head *bf_q,
2364 struct ath_tx_status *ts, int txok)
2365 {
2366 struct sk_buff *skb = bf->bf_mpdu;
2367 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2368 unsigned long flags;
2369 int tx_flags = 0;
2370
2371 if (!txok)
2372 tx_flags |= ATH_TX_ERROR;
2373
2374 if (ts->ts_status & ATH9K_TXERR_FILT)
2375 tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
2376
2377 dma_unmap_single(sc->dev, bf->bf_buf_addr, skb->len, DMA_TO_DEVICE);
2378 bf->bf_buf_addr = 0;
2379
2380 if (bf->bf_state.bfs_paprd) {
2381 if (time_after(jiffies,
2382 bf->bf_state.bfs_paprd_timestamp +
2383 msecs_to_jiffies(ATH_PAPRD_TIMEOUT)))
2384 dev_kfree_skb_any(skb);
2385 else
2386 complete(&sc->paprd_complete);
2387 } else {
2388 ath_debug_stat_tx(sc, bf, ts, txq, tx_flags);
2389 ath_tx_complete(sc, skb, tx_flags, txq);
2390 }
2391 /* At this point, skb (bf->bf_mpdu) is consumed...make sure we don't
2392 * accidentally reference it later.
2393 */
2394 bf->bf_mpdu = NULL;
2395
2396 /*
2397 * Return the list of ath_buf of this mpdu to free queue
2398 */
2399 spin_lock_irqsave(&sc->tx.txbuflock, flags);
2400 list_splice_tail_init(bf_q, &sc->tx.txbuf);
2401 spin_unlock_irqrestore(&sc->tx.txbuflock, flags);
2402 }
2403
2404 static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
2405 struct ath_tx_status *ts, int nframes, int nbad,
2406 int txok)
2407 {
2408 struct sk_buff *skb = bf->bf_mpdu;
2409 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
2410 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2411 struct ieee80211_hw *hw = sc->hw;
2412 struct ath_hw *ah = sc->sc_ah;
2413 u8 i, tx_rateindex;
2414
2415 if (txok)
2416 tx_info->status.ack_signal = ts->ts_rssi;
2417
2418 tx_rateindex = ts->ts_rateindex;
2419 WARN_ON(tx_rateindex >= hw->max_rates);
2420
2421 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
2422 tx_info->flags |= IEEE80211_TX_STAT_AMPDU;
2423
2424 BUG_ON(nbad > nframes);
2425 }
2426 tx_info->status.ampdu_len = nframes;
2427 tx_info->status.ampdu_ack_len = nframes - nbad;
2428
2429 if ((ts->ts_status & ATH9K_TXERR_FILT) == 0 &&
2430 (tx_info->flags & IEEE80211_TX_CTL_NO_ACK) == 0) {
2431 /*
2432 * If an underrun error is seen assume it as an excessive
2433 * retry only if max frame trigger level has been reached
2434 * (2 KB for single stream, and 4 KB for dual stream).
2435 * Adjust the long retry as if the frame was tried
2436 * hw->max_rate_tries times to affect how rate control updates
2437 * PER for the failed rate.
2438 * In case of congestion on the bus penalizing this type of
2439 * underruns should help hardware actually transmit new frames
2440 * successfully by eventually preferring slower rates.
2441 * This itself should also alleviate congestion on the bus.
2442 */
2443 if (unlikely(ts->ts_flags & (ATH9K_TX_DATA_UNDERRUN |
2444 ATH9K_TX_DELIM_UNDERRUN)) &&
2445 ieee80211_is_data(hdr->frame_control) &&
2446 ah->tx_trig_level >= sc->sc_ah->config.max_txtrig_level)
2447 tx_info->status.rates[tx_rateindex].count =
2448 hw->max_rate_tries;
2449 }
2450
2451 for (i = tx_rateindex + 1; i < hw->max_rates; i++) {
2452 tx_info->status.rates[i].count = 0;
2453 tx_info->status.rates[i].idx = -1;
2454 }
2455
2456 tx_info->status.rates[tx_rateindex].count = ts->ts_longretry + 1;
2457 }
2458
2459 static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
2460 {
2461 struct ath_hw *ah = sc->sc_ah;
2462 struct ath_common *common = ath9k_hw_common(ah);
2463 struct ath_buf *bf, *lastbf, *bf_held = NULL;
2464 struct list_head bf_head;
2465 struct ath_desc *ds;
2466 struct ath_tx_status ts;
2467 int status;
2468
2469 ath_dbg(common, QUEUE, "tx queue %d (%x), link %p\n",
2470 txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum),
2471 txq->axq_link);
2472
2473 ath_txq_lock(sc, txq);
2474 for (;;) {
2475 if (test_bit(SC_OP_HW_RESET, &sc->sc_flags))
2476 break;
2477
2478 if (list_empty(&txq->axq_q)) {
2479 txq->axq_link = NULL;
2480 ath_txq_schedule(sc, txq);
2481 break;
2482 }
2483 bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
2484
2485 /*
2486 * There is a race condition that a BH gets scheduled
2487 * after sw writes TxE and before hw re-load the last
2488 * descriptor to get the newly chained one.
2489 * Software must keep the last DONE descriptor as a
2490 * holding descriptor - software does so by marking
2491 * it with the STALE flag.
2492 */
2493 bf_held = NULL;
2494 if (bf->bf_state.stale) {
2495 bf_held = bf;
2496 if (list_is_last(&bf_held->list, &txq->axq_q))
2497 break;
2498
2499 bf = list_entry(bf_held->list.next, struct ath_buf,
2500 list);
2501 }
2502
2503 lastbf = bf->bf_lastbf;
2504 ds = lastbf->bf_desc;
2505
2506 memset(&ts, 0, sizeof(ts));
2507 status = ath9k_hw_txprocdesc(ah, ds, &ts);
2508 if (status == -EINPROGRESS)
2509 break;
2510
2511 TX_STAT_INC(txq->axq_qnum, txprocdesc);
2512
2513 /*
2514 * Remove ath_buf's of the same transmit unit from txq,
2515 * however leave the last descriptor back as the holding
2516 * descriptor for hw.
2517 */
2518 lastbf->bf_state.stale = true;
2519 INIT_LIST_HEAD(&bf_head);
2520 if (!list_is_singular(&lastbf->list))
2521 list_cut_position(&bf_head,
2522 &txq->axq_q, lastbf->list.prev);
2523
2524 if (bf_held) {
2525 list_del(&bf_held->list);
2526 ath_tx_return_buffer(sc, bf_held);
2527 }
2528
2529 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
2530 }
2531 ath_txq_unlock_complete(sc, txq);
2532 }
2533
2534 void ath_tx_tasklet(struct ath_softc *sc)
2535 {
2536 struct ath_hw *ah = sc->sc_ah;
2537 u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1) & ah->intr_txqs;
2538 int i;
2539
2540 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2541 if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i)))
2542 ath_tx_processq(sc, &sc->tx.txq[i]);
2543 }
2544 }
2545
2546 void ath_tx_edma_tasklet(struct ath_softc *sc)
2547 {
2548 struct ath_tx_status ts;
2549 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2550 struct ath_hw *ah = sc->sc_ah;
2551 struct ath_txq *txq;
2552 struct ath_buf *bf, *lastbf;
2553 struct list_head bf_head;
2554 struct list_head *fifo_list;
2555 int status;
2556
2557 for (;;) {
2558 if (test_bit(SC_OP_HW_RESET, &sc->sc_flags))
2559 break;
2560
2561 status = ath9k_hw_txprocdesc(ah, NULL, (void *)&ts);
2562 if (status == -EINPROGRESS)
2563 break;
2564 if (status == -EIO) {
2565 ath_dbg(common, XMIT, "Error processing tx status\n");
2566 break;
2567 }
2568
2569 /* Process beacon completions separately */
2570 if (ts.qid == sc->beacon.beaconq) {
2571 sc->beacon.tx_processed = true;
2572 sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
2573
2574 ath9k_csa_is_finished(sc);
2575 continue;
2576 }
2577
2578 txq = &sc->tx.txq[ts.qid];
2579
2580 ath_txq_lock(sc, txq);
2581
2582 TX_STAT_INC(txq->axq_qnum, txprocdesc);
2583
2584 fifo_list = &txq->txq_fifo[txq->txq_tailidx];
2585 if (list_empty(fifo_list)) {
2586 ath_txq_unlock(sc, txq);
2587 return;
2588 }
2589
2590 bf = list_first_entry(fifo_list, struct ath_buf, list);
2591 if (bf->bf_state.stale) {
2592 list_del(&bf->list);
2593 ath_tx_return_buffer(sc, bf);
2594 bf = list_first_entry(fifo_list, struct ath_buf, list);
2595 }
2596
2597 lastbf = bf->bf_lastbf;
2598
2599 INIT_LIST_HEAD(&bf_head);
2600 if (list_is_last(&lastbf->list, fifo_list)) {
2601 list_splice_tail_init(fifo_list, &bf_head);
2602 INCR(txq->txq_tailidx, ATH_TXFIFO_DEPTH);
2603
2604 if (!list_empty(&txq->axq_q)) {
2605 struct list_head bf_q;
2606
2607 INIT_LIST_HEAD(&bf_q);
2608 txq->axq_link = NULL;
2609 list_splice_tail_init(&txq->axq_q, &bf_q);
2610 ath_tx_txqaddbuf(sc, txq, &bf_q, true);
2611 }
2612 } else {
2613 lastbf->bf_state.stale = true;
2614 if (bf != lastbf)
2615 list_cut_position(&bf_head, fifo_list,
2616 lastbf->list.prev);
2617 }
2618
2619 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
2620 ath_txq_unlock_complete(sc, txq);
2621 }
2622 }
2623
2624 /*****************/
2625 /* Init, Cleanup */
2626 /*****************/
2627
2628 static int ath_txstatus_setup(struct ath_softc *sc, int size)
2629 {
2630 struct ath_descdma *dd = &sc->txsdma;
2631 u8 txs_len = sc->sc_ah->caps.txs_len;
2632
2633 dd->dd_desc_len = size * txs_len;
2634 dd->dd_desc = dmam_alloc_coherent(sc->dev, dd->dd_desc_len,
2635 &dd->dd_desc_paddr, GFP_KERNEL);
2636 if (!dd->dd_desc)
2637 return -ENOMEM;
2638
2639 return 0;
2640 }
2641
2642 static int ath_tx_edma_init(struct ath_softc *sc)
2643 {
2644 int err;
2645
2646 err = ath_txstatus_setup(sc, ATH_TXSTATUS_RING_SIZE);
2647 if (!err)
2648 ath9k_hw_setup_statusring(sc->sc_ah, sc->txsdma.dd_desc,
2649 sc->txsdma.dd_desc_paddr,
2650 ATH_TXSTATUS_RING_SIZE);
2651
2652 return err;
2653 }
2654
2655 int ath_tx_init(struct ath_softc *sc, int nbufs)
2656 {
2657 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2658 int error = 0;
2659
2660 spin_lock_init(&sc->tx.txbuflock);
2661
2662 error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf,
2663 "tx", nbufs, 1, 1);
2664 if (error != 0) {
2665 ath_err(common,
2666 "Failed to allocate tx descriptors: %d\n", error);
2667 return error;
2668 }
2669
2670 error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf,
2671 "beacon", ATH_BCBUF, 1, 1);
2672 if (error != 0) {
2673 ath_err(common,
2674 "Failed to allocate beacon descriptors: %d\n", error);
2675 return error;
2676 }
2677
2678 INIT_DELAYED_WORK(&sc->tx_complete_work, ath_tx_complete_poll_work);
2679
2680 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
2681 error = ath_tx_edma_init(sc);
2682
2683 return error;
2684 }
2685
2686 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an)
2687 {
2688 struct ath_atx_tid *tid;
2689 struct ath_atx_ac *ac;
2690 int tidno, acno;
2691
2692 for (tidno = 0, tid = &an->tid[tidno];
2693 tidno < IEEE80211_NUM_TIDS;
2694 tidno++, tid++) {
2695 tid->an = an;
2696 tid->tidno = tidno;
2697 tid->seq_start = tid->seq_next = 0;
2698 tid->baw_size = WME_MAX_BA;
2699 tid->baw_head = tid->baw_tail = 0;
2700 tid->sched = false;
2701 tid->paused = false;
2702 tid->active = false;
2703 __skb_queue_head_init(&tid->buf_q);
2704 __skb_queue_head_init(&tid->retry_q);
2705 acno = TID_TO_WME_AC(tidno);
2706 tid->ac = &an->ac[acno];
2707 }
2708
2709 for (acno = 0, ac = &an->ac[acno];
2710 acno < IEEE80211_NUM_ACS; acno++, ac++) {
2711 ac->sched = false;
2712 ac->clear_ps_filter = true;
2713 ac->txq = sc->tx.txq_map[acno];
2714 INIT_LIST_HEAD(&ac->tid_q);
2715 }
2716 }
2717
2718 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an)
2719 {
2720 struct ath_atx_ac *ac;
2721 struct ath_atx_tid *tid;
2722 struct ath_txq *txq;
2723 int tidno;
2724
2725 for (tidno = 0, tid = &an->tid[tidno];
2726 tidno < IEEE80211_NUM_TIDS; tidno++, tid++) {
2727
2728 ac = tid->ac;
2729 txq = ac->txq;
2730
2731 ath_txq_lock(sc, txq);
2732
2733 if (tid->sched) {
2734 list_del(&tid->list);
2735 tid->sched = false;
2736 }
2737
2738 if (ac->sched) {
2739 list_del(&ac->list);
2740 tid->ac->sched = false;
2741 }
2742
2743 ath_tid_drain(sc, txq, tid);
2744 tid->active = false;
2745
2746 ath_txq_unlock(sc, txq);
2747 }
2748 }
Linux kernel - Deliverables
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