2 * Copyright (c) 2008-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/dma-mapping.h>
19 #include "ar9003_mac.h"
21 #define BITS_PER_BYTE 8
22 #define OFDM_PLCP_BITS 22
23 #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
29 #define HT_LTF(_ns) (4 * (_ns))
30 #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */
31 #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */
32 #define TIME_SYMBOLS(t) ((t) >> 2)
33 #define TIME_SYMBOLS_HALFGI(t) (((t) * 5 - 4) / 18)
34 #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
35 #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
38 static u16 bits_per_symbol
[][2] = {
40 { 26, 54 }, /* 0: BPSK */
41 { 52, 108 }, /* 1: QPSK 1/2 */
42 { 78, 162 }, /* 2: QPSK 3/4 */
43 { 104, 216 }, /* 3: 16-QAM 1/2 */
44 { 156, 324 }, /* 4: 16-QAM 3/4 */
45 { 208, 432 }, /* 5: 64-QAM 2/3 */
46 { 234, 486 }, /* 6: 64-QAM 3/4 */
47 { 260, 540 }, /* 7: 64-QAM 5/6 */
50 #define IS_HT_RATE(_rate) ((_rate) & 0x80)
52 static void ath_tx_send_normal(struct ath_softc
*sc
, struct ath_txq
*txq
,
53 struct ath_atx_tid
*tid
, struct sk_buff
*skb
);
54 static void ath_tx_complete(struct ath_softc
*sc
, struct sk_buff
*skb
,
55 int tx_flags
, struct ath_txq
*txq
);
56 static void ath_tx_complete_buf(struct ath_softc
*sc
, struct ath_buf
*bf
,
57 struct ath_txq
*txq
, struct list_head
*bf_q
,
58 struct ath_tx_status
*ts
, int txok
);
59 static void ath_tx_txqaddbuf(struct ath_softc
*sc
, struct ath_txq
*txq
,
60 struct list_head
*head
, bool internal
);
61 static void ath_tx_rc_status(struct ath_softc
*sc
, struct ath_buf
*bf
,
62 struct ath_tx_status
*ts
, int nframes
, int nbad
,
64 static void ath_tx_update_baw(struct ath_softc
*sc
, struct ath_atx_tid
*tid
,
66 static struct ath_buf
*ath_tx_setup_buffer(struct ath_softc
*sc
,
68 struct ath_atx_tid
*tid
,
78 /*********************/
79 /* Aggregation logic */
80 /*********************/
82 void ath_txq_lock(struct ath_softc
*sc
, struct ath_txq
*txq
)
83 __acquires(&txq
->axq_lock
)
85 spin_lock_bh(&txq
->axq_lock
);
88 void ath_txq_unlock(struct ath_softc
*sc
, struct ath_txq
*txq
)
89 __releases(&txq
->axq_lock
)
91 spin_unlock_bh(&txq
->axq_lock
);
94 void ath_txq_unlock_complete(struct ath_softc
*sc
, struct ath_txq
*txq
)
95 __releases(&txq
->axq_lock
)
97 struct sk_buff_head q
;
100 __skb_queue_head_init(&q
);
101 skb_queue_splice_init(&txq
->complete_q
, &q
);
102 spin_unlock_bh(&txq
->axq_lock
);
104 while ((skb
= __skb_dequeue(&q
)))
105 ieee80211_tx_status(sc
->hw
, skb
);
108 static void ath_tx_queue_tid(struct ath_txq
*txq
, struct ath_atx_tid
*tid
)
110 struct ath_atx_ac
*ac
= tid
->ac
;
119 list_add_tail(&tid
->list
, &ac
->tid_q
);
125 list_add_tail(&ac
->list
, &txq
->axq_acq
);
128 static struct ath_frame_info
*get_frame_info(struct sk_buff
*skb
)
130 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
131 BUILD_BUG_ON(sizeof(struct ath_frame_info
) >
132 sizeof(tx_info
->rate_driver_data
));
133 return (struct ath_frame_info
*) &tx_info
->rate_driver_data
[0];
136 static void ath_send_bar(struct ath_atx_tid
*tid
, u16 seqno
)
138 ieee80211_send_bar(tid
->an
->vif
, tid
->an
->sta
->addr
, tid
->tidno
,
139 seqno
<< IEEE80211_SEQ_SEQ_SHIFT
);
142 static void ath_set_rates(struct ieee80211_vif
*vif
, struct ieee80211_sta
*sta
,
145 ieee80211_get_tx_rates(vif
, sta
, bf
->bf_mpdu
, bf
->rates
,
146 ARRAY_SIZE(bf
->rates
));
149 static void ath_txq_skb_done(struct ath_softc
*sc
, struct ath_txq
*txq
,
154 q
= skb_get_queue_mapping(skb
);
155 if (txq
== sc
->tx
.uapsdq
)
156 txq
= sc
->tx
.txq_map
[q
];
158 if (txq
!= sc
->tx
.txq_map
[q
])
161 if (WARN_ON(--txq
->pending_frames
< 0))
162 txq
->pending_frames
= 0;
165 txq
->pending_frames
< sc
->tx
.txq_max_pending
[q
]) {
166 ieee80211_wake_queue(sc
->hw
, q
);
167 txq
->stopped
= false;
171 static void ath_tx_flush_tid(struct ath_softc
*sc
, struct ath_atx_tid
*tid
)
173 struct ath_txq
*txq
= tid
->ac
->txq
;
176 struct list_head bf_head
;
177 struct ath_tx_status ts
;
178 struct ath_frame_info
*fi
;
179 bool sendbar
= false;
181 INIT_LIST_HEAD(&bf_head
);
183 memset(&ts
, 0, sizeof(ts
));
185 while ((skb
= __skb_dequeue(&tid
->buf_q
))) {
186 fi
= get_frame_info(skb
);
190 bf
= ath_tx_setup_buffer(sc
, txq
, tid
, skb
);
192 ath_txq_skb_done(sc
, txq
, skb
);
193 ieee80211_free_txskb(sc
->hw
, skb
);
199 list_add_tail(&bf
->list
, &bf_head
);
200 ath_tx_update_baw(sc
, tid
, bf
->bf_state
.seqno
);
201 ath_tx_complete_buf(sc
, bf
, txq
, &bf_head
, &ts
, 0);
204 ath_set_rates(tid
->an
->vif
, tid
->an
->sta
, bf
);
205 ath_tx_send_normal(sc
, txq
, NULL
, skb
);
210 ath_txq_unlock(sc
, txq
);
211 ath_send_bar(tid
, tid
->seq_start
);
212 ath_txq_lock(sc
, txq
);
216 static void ath_tx_update_baw(struct ath_softc
*sc
, struct ath_atx_tid
*tid
,
221 index
= ATH_BA_INDEX(tid
->seq_start
, seqno
);
222 cindex
= (tid
->baw_head
+ index
) & (ATH_TID_MAX_BUFS
- 1);
224 __clear_bit(cindex
, tid
->tx_buf
);
226 while (tid
->baw_head
!= tid
->baw_tail
&& !test_bit(tid
->baw_head
, tid
->tx_buf
)) {
227 INCR(tid
->seq_start
, IEEE80211_SEQ_MAX
);
228 INCR(tid
->baw_head
, ATH_TID_MAX_BUFS
);
229 if (tid
->bar_index
>= 0)
234 static void ath_tx_addto_baw(struct ath_softc
*sc
, struct ath_atx_tid
*tid
,
239 index
= ATH_BA_INDEX(tid
->seq_start
, seqno
);
240 cindex
= (tid
->baw_head
+ index
) & (ATH_TID_MAX_BUFS
- 1);
241 __set_bit(cindex
, tid
->tx_buf
);
243 if (index
>= ((tid
->baw_tail
- tid
->baw_head
) &
244 (ATH_TID_MAX_BUFS
- 1))) {
245 tid
->baw_tail
= cindex
;
246 INCR(tid
->baw_tail
, ATH_TID_MAX_BUFS
);
251 * TODO: For frame(s) that are in the retry state, we will reuse the
252 * sequence number(s) without setting the retry bit. The
253 * alternative is to give up on these and BAR the receiver's window
256 static void ath_tid_drain(struct ath_softc
*sc
, struct ath_txq
*txq
,
257 struct ath_atx_tid
*tid
)
262 struct list_head bf_head
;
263 struct ath_tx_status ts
;
264 struct ath_frame_info
*fi
;
266 memset(&ts
, 0, sizeof(ts
));
267 INIT_LIST_HEAD(&bf_head
);
269 while ((skb
= __skb_dequeue(&tid
->buf_q
))) {
270 fi
= get_frame_info(skb
);
274 ath_tx_complete(sc
, skb
, ATH_TX_ERROR
, txq
);
278 list_add_tail(&bf
->list
, &bf_head
);
280 ath_tx_update_baw(sc
, tid
, bf
->bf_state
.seqno
);
281 ath_tx_complete_buf(sc
, bf
, txq
, &bf_head
, &ts
, 0);
284 tid
->seq_next
= tid
->seq_start
;
285 tid
->baw_tail
= tid
->baw_head
;
289 static void ath_tx_set_retry(struct ath_softc
*sc
, struct ath_txq
*txq
,
290 struct sk_buff
*skb
, int count
)
292 struct ath_frame_info
*fi
= get_frame_info(skb
);
293 struct ath_buf
*bf
= fi
->bf
;
294 struct ieee80211_hdr
*hdr
;
295 int prev
= fi
->retries
;
297 TX_STAT_INC(txq
->axq_qnum
, a_retries
);
298 fi
->retries
+= count
;
303 hdr
= (struct ieee80211_hdr
*)skb
->data
;
304 hdr
->frame_control
|= cpu_to_le16(IEEE80211_FCTL_RETRY
);
305 dma_sync_single_for_device(sc
->dev
, bf
->bf_buf_addr
,
306 sizeof(*hdr
), DMA_TO_DEVICE
);
309 static struct ath_buf
*ath_tx_get_buffer(struct ath_softc
*sc
)
311 struct ath_buf
*bf
= NULL
;
313 spin_lock_bh(&sc
->tx
.txbuflock
);
315 if (unlikely(list_empty(&sc
->tx
.txbuf
))) {
316 spin_unlock_bh(&sc
->tx
.txbuflock
);
320 bf
= list_first_entry(&sc
->tx
.txbuf
, struct ath_buf
, list
);
323 spin_unlock_bh(&sc
->tx
.txbuflock
);
328 static void ath_tx_return_buffer(struct ath_softc
*sc
, struct ath_buf
*bf
)
330 spin_lock_bh(&sc
->tx
.txbuflock
);
331 list_add_tail(&bf
->list
, &sc
->tx
.txbuf
);
332 spin_unlock_bh(&sc
->tx
.txbuflock
);
335 static struct ath_buf
* ath_clone_txbuf(struct ath_softc
*sc
, struct ath_buf
*bf
)
339 tbf
= ath_tx_get_buffer(sc
);
343 ATH_TXBUF_RESET(tbf
);
345 tbf
->bf_mpdu
= bf
->bf_mpdu
;
346 tbf
->bf_buf_addr
= bf
->bf_buf_addr
;
347 memcpy(tbf
->bf_desc
, bf
->bf_desc
, sc
->sc_ah
->caps
.tx_desc_len
);
348 tbf
->bf_state
= bf
->bf_state
;
353 static void ath_tx_count_frames(struct ath_softc
*sc
, struct ath_buf
*bf
,
354 struct ath_tx_status
*ts
, int txok
,
355 int *nframes
, int *nbad
)
357 struct ath_frame_info
*fi
;
359 u32 ba
[WME_BA_BMP_SIZE
>> 5];
366 isaggr
= bf_isaggr(bf
);
368 seq_st
= ts
->ts_seqnum
;
369 memcpy(ba
, &ts
->ba_low
, WME_BA_BMP_SIZE
>> 3);
373 fi
= get_frame_info(bf
->bf_mpdu
);
374 ba_index
= ATH_BA_INDEX(seq_st
, bf
->bf_state
.seqno
);
377 if (!txok
|| (isaggr
&& !ATH_BA_ISSET(ba
, ba_index
)))
385 static void ath_tx_complete_aggr(struct ath_softc
*sc
, struct ath_txq
*txq
,
386 struct ath_buf
*bf
, struct list_head
*bf_q
,
387 struct ath_tx_status
*ts
, int txok
)
389 struct ath_node
*an
= NULL
;
391 struct ieee80211_sta
*sta
;
392 struct ieee80211_hw
*hw
= sc
->hw
;
393 struct ieee80211_hdr
*hdr
;
394 struct ieee80211_tx_info
*tx_info
;
395 struct ath_atx_tid
*tid
= NULL
;
396 struct ath_buf
*bf_next
, *bf_last
= bf
->bf_lastbf
;
397 struct list_head bf_head
;
398 struct sk_buff_head bf_pending
;
399 u16 seq_st
= 0, acked_cnt
= 0, txfail_cnt
= 0, seq_first
;
400 u32 ba
[WME_BA_BMP_SIZE
>> 5];
401 int isaggr
, txfail
, txpending
, sendbar
= 0, needreset
= 0, nbad
= 0;
402 bool rc_update
= true, isba
;
403 struct ieee80211_tx_rate rates
[4];
404 struct ath_frame_info
*fi
;
407 bool flush
= !!(ts
->ts_status
& ATH9K_TX_FLUSH
);
412 hdr
= (struct ieee80211_hdr
*)skb
->data
;
414 tx_info
= IEEE80211_SKB_CB(skb
);
416 memcpy(rates
, bf
->rates
, sizeof(rates
));
418 retries
= ts
->ts_longretry
+ 1;
419 for (i
= 0; i
< ts
->ts_rateindex
; i
++)
420 retries
+= rates
[i
].count
;
424 sta
= ieee80211_find_sta_by_ifaddr(hw
, hdr
->addr1
, hdr
->addr2
);
428 INIT_LIST_HEAD(&bf_head
);
430 bf_next
= bf
->bf_next
;
432 if (!bf
->bf_stale
|| bf_next
!= NULL
)
433 list_move_tail(&bf
->list
, &bf_head
);
435 ath_tx_complete_buf(sc
, bf
, txq
, &bf_head
, ts
, 0);
442 an
= (struct ath_node
*)sta
->drv_priv
;
443 tidno
= ieee80211_get_qos_ctl(hdr
)[0] & IEEE80211_QOS_CTL_TID_MASK
;
444 tid
= ATH_AN_2_TID(an
, tidno
);
445 seq_first
= tid
->seq_start
;
446 isba
= ts
->ts_flags
& ATH9K_TX_BA
;
449 * The hardware occasionally sends a tx status for the wrong TID.
450 * In this case, the BA status cannot be considered valid and all
451 * subframes need to be retransmitted
453 * Only BlockAcks have a TID and therefore normal Acks cannot be
456 if (isba
&& tidno
!= ts
->tid
)
459 isaggr
= bf_isaggr(bf
);
460 memset(ba
, 0, WME_BA_BMP_SIZE
>> 3);
462 if (isaggr
&& txok
) {
463 if (ts
->ts_flags
& ATH9K_TX_BA
) {
464 seq_st
= ts
->ts_seqnum
;
465 memcpy(ba
, &ts
->ba_low
, WME_BA_BMP_SIZE
>> 3);
468 * AR5416 can become deaf/mute when BA
469 * issue happens. Chip needs to be reset.
470 * But AP code may have sychronization issues
471 * when perform internal reset in this routine.
472 * Only enable reset in STA mode for now.
474 if (sc
->sc_ah
->opmode
== NL80211_IFTYPE_STATION
)
479 __skb_queue_head_init(&bf_pending
);
481 ath_tx_count_frames(sc
, bf
, ts
, txok
, &nframes
, &nbad
);
483 u16 seqno
= bf
->bf_state
.seqno
;
485 txfail
= txpending
= sendbar
= 0;
486 bf_next
= bf
->bf_next
;
489 tx_info
= IEEE80211_SKB_CB(skb
);
490 fi
= get_frame_info(skb
);
492 if (!BAW_WITHIN(tid
->seq_start
, tid
->baw_size
, seqno
)) {
494 * Outside of the current BlockAck window,
495 * maybe part of a previous session
498 } else if (ATH_BA_ISSET(ba
, ATH_BA_INDEX(seq_st
, seqno
))) {
499 /* transmit completion, subframe is
500 * acked by block ack */
502 } else if (!isaggr
&& txok
) {
503 /* transmit completion */
507 } else if (fi
->retries
< ATH_MAX_SW_RETRIES
) {
508 if (txok
|| !an
->sleeping
)
509 ath_tx_set_retry(sc
, txq
, bf
->bf_mpdu
,
516 bar_index
= max_t(int, bar_index
,
517 ATH_BA_INDEX(seq_first
, seqno
));
521 * Make sure the last desc is reclaimed if it
522 * not a holding desc.
524 INIT_LIST_HEAD(&bf_head
);
525 if (bf_next
!= NULL
|| !bf_last
->bf_stale
)
526 list_move_tail(&bf
->list
, &bf_head
);
530 * complete the acked-ones/xretried ones; update
533 ath_tx_update_baw(sc
, tid
, seqno
);
535 if (rc_update
&& (acked_cnt
== 1 || txfail_cnt
== 1)) {
536 memcpy(tx_info
->control
.rates
, rates
, sizeof(rates
));
537 ath_tx_rc_status(sc
, bf
, ts
, nframes
, nbad
, txok
);
541 ath_tx_complete_buf(sc
, bf
, txq
, &bf_head
, ts
,
544 if (tx_info
->flags
& IEEE80211_TX_STATUS_EOSP
) {
545 tx_info
->flags
&= ~IEEE80211_TX_STATUS_EOSP
;
546 ieee80211_sta_eosp(sta
);
548 /* retry the un-acked ones */
549 if (bf
->bf_next
== NULL
&& bf_last
->bf_stale
) {
552 tbf
= ath_clone_txbuf(sc
, bf_last
);
554 * Update tx baw and complete the
555 * frame with failed status if we
559 ath_tx_update_baw(sc
, tid
, seqno
);
561 ath_tx_complete_buf(sc
, bf
, txq
,
563 bar_index
= max_t(int, bar_index
,
564 ATH_BA_INDEX(seq_first
, seqno
));
572 * Put this buffer to the temporary pending
573 * queue to retain ordering
575 __skb_queue_tail(&bf_pending
, skb
);
581 /* prepend un-acked frames to the beginning of the pending frame queue */
582 if (!skb_queue_empty(&bf_pending
)) {
584 ieee80211_sta_set_buffered(sta
, tid
->tidno
, true);
586 skb_queue_splice(&bf_pending
, &tid
->buf_q
);
588 ath_tx_queue_tid(txq
, tid
);
590 if (ts
->ts_status
& (ATH9K_TXERR_FILT
| ATH9K_TXERR_XRETRY
))
591 tid
->ac
->clear_ps_filter
= true;
595 if (bar_index
>= 0) {
596 u16 bar_seq
= ATH_BA_INDEX2SEQ(seq_first
, bar_index
);
598 if (BAW_WITHIN(tid
->seq_start
, tid
->baw_size
, bar_seq
))
599 tid
->bar_index
= ATH_BA_INDEX(tid
->seq_start
, bar_seq
);
601 ath_txq_unlock(sc
, txq
);
602 ath_send_bar(tid
, ATH_BA_INDEX2SEQ(seq_first
, bar_index
+ 1));
603 ath_txq_lock(sc
, txq
);
609 ath9k_queue_reset(sc
, RESET_TYPE_TX_ERROR
);
612 static bool bf_is_ampdu_not_probing(struct ath_buf
*bf
)
614 struct ieee80211_tx_info
*info
= IEEE80211_SKB_CB(bf
->bf_mpdu
);
615 return bf_isampdu(bf
) && !(info
->flags
& IEEE80211_TX_CTL_RATE_CTRL_PROBE
);
618 static void ath_tx_process_buffer(struct ath_softc
*sc
, struct ath_txq
*txq
,
619 struct ath_tx_status
*ts
, struct ath_buf
*bf
,
620 struct list_head
*bf_head
)
622 struct ieee80211_tx_info
*info
;
625 txok
= !(ts
->ts_status
& ATH9K_TXERR_MASK
);
626 flush
= !!(ts
->ts_status
& ATH9K_TX_FLUSH
);
627 txq
->axq_tx_inprogress
= false;
630 if (bf_is_ampdu_not_probing(bf
))
631 txq
->axq_ampdu_depth
--;
633 if (!bf_isampdu(bf
)) {
635 info
= IEEE80211_SKB_CB(bf
->bf_mpdu
);
636 memcpy(info
->control
.rates
, bf
->rates
,
637 sizeof(info
->control
.rates
));
638 ath_tx_rc_status(sc
, bf
, ts
, 1, txok
? 0 : 1, txok
);
640 ath_tx_complete_buf(sc
, bf
, txq
, bf_head
, ts
, txok
);
642 ath_tx_complete_aggr(sc
, txq
, bf
, bf_head
, ts
, txok
);
644 if ((sc
->sc_ah
->caps
.hw_caps
& ATH9K_HW_CAP_HT
) && !flush
)
645 ath_txq_schedule(sc
, txq
);
648 static bool ath_lookup_legacy(struct ath_buf
*bf
)
651 struct ieee80211_tx_info
*tx_info
;
652 struct ieee80211_tx_rate
*rates
;
656 tx_info
= IEEE80211_SKB_CB(skb
);
657 rates
= tx_info
->control
.rates
;
659 for (i
= 0; i
< 4; i
++) {
660 if (!rates
[i
].count
|| rates
[i
].idx
< 0)
663 if (!(rates
[i
].flags
& IEEE80211_TX_RC_MCS
))
670 static u32
ath_lookup_rate(struct ath_softc
*sc
, struct ath_buf
*bf
,
671 struct ath_atx_tid
*tid
)
674 struct ieee80211_tx_info
*tx_info
;
675 struct ieee80211_tx_rate
*rates
;
676 u32 max_4ms_framelen
, frmlen
;
677 u16 aggr_limit
, bt_aggr_limit
, legacy
= 0;
678 int q
= tid
->ac
->txq
->mac80211_qnum
;
682 tx_info
= IEEE80211_SKB_CB(skb
);
686 * Find the lowest frame length among the rate series that will have a
687 * 4ms (or TXOP limited) transmit duration.
689 max_4ms_framelen
= ATH_AMPDU_LIMIT_MAX
;
691 for (i
= 0; i
< 4; i
++) {
697 if (!(rates
[i
].flags
& IEEE80211_TX_RC_MCS
)) {
702 if (rates
[i
].flags
& IEEE80211_TX_RC_40_MHZ_WIDTH
)
707 if (rates
[i
].flags
& IEEE80211_TX_RC_SHORT_GI
)
710 frmlen
= sc
->tx
.max_aggr_framelen
[q
][modeidx
][rates
[i
].idx
];
711 max_4ms_framelen
= min(max_4ms_framelen
, frmlen
);
715 * limit aggregate size by the minimum rate if rate selected is
716 * not a probe rate, if rate selected is a probe rate then
717 * avoid aggregation of this packet.
719 if (tx_info
->flags
& IEEE80211_TX_CTL_RATE_CTRL_PROBE
|| legacy
)
722 aggr_limit
= min(max_4ms_framelen
, (u32
)ATH_AMPDU_LIMIT_MAX
);
725 * Override the default aggregation limit for BTCOEX.
727 bt_aggr_limit
= ath9k_btcoex_aggr_limit(sc
, max_4ms_framelen
);
729 aggr_limit
= bt_aggr_limit
;
732 * h/w can accept aggregates up to 16 bit lengths (65535).
733 * The IE, however can hold up to 65536, which shows up here
734 * as zero. Ignore 65536 since we are constrained by hw.
736 if (tid
->an
->maxampdu
)
737 aggr_limit
= min(aggr_limit
, tid
->an
->maxampdu
);
743 * Returns the number of delimiters to be added to
744 * meet the minimum required mpdudensity.
746 static int ath_compute_num_delims(struct ath_softc
*sc
, struct ath_atx_tid
*tid
,
747 struct ath_buf
*bf
, u16 frmlen
,
750 #define FIRST_DESC_NDELIMS 60
751 u32 nsymbits
, nsymbols
;
754 int width
, streams
, half_gi
, ndelim
, mindelim
;
755 struct ath_frame_info
*fi
= get_frame_info(bf
->bf_mpdu
);
757 /* Select standard number of delimiters based on frame length alone */
758 ndelim
= ATH_AGGR_GET_NDELIM(frmlen
);
761 * If encryption enabled, hardware requires some more padding between
763 * TODO - this could be improved to be dependent on the rate.
764 * The hardware can keep up at lower rates, but not higher rates
766 if ((fi
->keyix
!= ATH9K_TXKEYIX_INVALID
) &&
767 !(sc
->sc_ah
->caps
.hw_caps
& ATH9K_HW_CAP_EDMA
))
768 ndelim
+= ATH_AGGR_ENCRYPTDELIM
;
771 * Add delimiter when using RTS/CTS with aggregation
772 * and non enterprise AR9003 card
774 if (first_subfrm
&& !AR_SREV_9580_10_OR_LATER(sc
->sc_ah
) &&
775 (sc
->sc_ah
->ent_mode
& AR_ENT_OTP_MIN_PKT_SIZE_DISABLE
))
776 ndelim
= max(ndelim
, FIRST_DESC_NDELIMS
);
779 * Convert desired mpdu density from microeconds to bytes based
780 * on highest rate in rate series (i.e. first rate) to determine
781 * required minimum length for subframe. Take into account
782 * whether high rate is 20 or 40Mhz and half or full GI.
784 * If there is no mpdu density restriction, no further calculation
788 if (tid
->an
->mpdudensity
== 0)
791 rix
= bf
->rates
[0].idx
;
792 flags
= bf
->rates
[0].flags
;
793 width
= (flags
& IEEE80211_TX_RC_40_MHZ_WIDTH
) ? 1 : 0;
794 half_gi
= (flags
& IEEE80211_TX_RC_SHORT_GI
) ? 1 : 0;
797 nsymbols
= NUM_SYMBOLS_PER_USEC_HALFGI(tid
->an
->mpdudensity
);
799 nsymbols
= NUM_SYMBOLS_PER_USEC(tid
->an
->mpdudensity
);
804 streams
= HT_RC_2_STREAMS(rix
);
805 nsymbits
= bits_per_symbol
[rix
% 8][width
] * streams
;
806 minlen
= (nsymbols
* nsymbits
) / BITS_PER_BYTE
;
808 if (frmlen
< minlen
) {
809 mindelim
= (minlen
- frmlen
) / ATH_AGGR_DELIM_SZ
;
810 ndelim
= max(mindelim
, ndelim
);
816 static struct ath_buf
*
817 ath_tx_get_tid_subframe(struct ath_softc
*sc
, struct ath_txq
*txq
,
818 struct ath_atx_tid
*tid
)
820 struct ath_frame_info
*fi
;
826 skb
= skb_peek(&tid
->buf_q
);
830 fi
= get_frame_info(skb
);
833 bf
= ath_tx_setup_buffer(sc
, txq
, tid
, skb
);
836 __skb_unlink(skb
, &tid
->buf_q
);
837 ath_txq_skb_done(sc
, txq
, skb
);
838 ieee80211_free_txskb(sc
->hw
, skb
);
842 bf
->bf_state
.bf_type
= BUF_AMPDU
| BUF_AGGR
;
843 seqno
= bf
->bf_state
.seqno
;
845 /* do not step over block-ack window */
846 if (!BAW_WITHIN(tid
->seq_start
, tid
->baw_size
, seqno
))
849 if (tid
->bar_index
> ATH_BA_INDEX(tid
->seq_start
, seqno
)) {
850 struct ath_tx_status ts
= {};
851 struct list_head bf_head
;
853 INIT_LIST_HEAD(&bf_head
);
854 list_add(&bf
->list
, &bf_head
);
855 __skb_unlink(skb
, &tid
->buf_q
);
856 ath_tx_update_baw(sc
, tid
, seqno
);
857 ath_tx_complete_buf(sc
, bf
, txq
, &bf_head
, &ts
, 0);
869 static enum ATH_AGGR_STATUS
ath_tx_form_aggr(struct ath_softc
*sc
,
871 struct ath_atx_tid
*tid
,
872 struct list_head
*bf_q
,
875 #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
876 struct ath_buf
*bf
, *bf_first
= NULL
, *bf_prev
= NULL
;
877 int rl
= 0, nframes
= 0, ndelim
, prev_al
= 0;
878 u16 aggr_limit
= 0, al
= 0, bpad
= 0,
879 al_delta
, h_baw
= tid
->baw_size
/ 2;
880 enum ATH_AGGR_STATUS status
= ATH_AGGR_DONE
;
881 struct ieee80211_tx_info
*tx_info
;
882 struct ath_frame_info
*fi
;
886 bf
= ath_tx_get_tid_subframe(sc
, txq
, tid
);
888 status
= ATH_AGGR_BAW_CLOSED
;
893 fi
= get_frame_info(skb
);
899 ath_set_rates(tid
->an
->vif
, tid
->an
->sta
, bf
);
900 aggr_limit
= ath_lookup_rate(sc
, bf
, tid
);
904 /* do not exceed aggregation limit */
905 al_delta
= ATH_AGGR_DELIM_SZ
+ fi
->framelen
;
908 ((aggr_limit
< (al
+ bpad
+ al_delta
+ prev_al
)) ||
909 ath_lookup_legacy(bf
))) {
910 status
= ATH_AGGR_LIMITED
;
914 tx_info
= IEEE80211_SKB_CB(bf
->bf_mpdu
);
915 if (nframes
&& (tx_info
->flags
& IEEE80211_TX_CTL_RATE_CTRL_PROBE
))
918 /* do not exceed subframe limit */
919 if (nframes
>= min((int)h_baw
, ATH_AMPDU_SUBFRAME_DEFAULT
)) {
920 status
= ATH_AGGR_LIMITED
;
924 /* add padding for previous frame to aggregation length */
925 al
+= bpad
+ al_delta
;
928 * Get the delimiters needed to meet the MPDU
929 * density for this node.
931 ndelim
= ath_compute_num_delims(sc
, tid
, bf_first
, fi
->framelen
,
933 bpad
= PADBYTES(al_delta
) + (ndelim
<< 2);
938 /* link buffers of this frame to the aggregate */
940 ath_tx_addto_baw(sc
, tid
, bf
->bf_state
.seqno
);
941 bf
->bf_state
.ndelim
= ndelim
;
943 __skb_unlink(skb
, &tid
->buf_q
);
944 list_add_tail(&bf
->list
, bf_q
);
946 bf_prev
->bf_next
= bf
;
950 } while (!skb_queue_empty(&tid
->buf_q
));
960 * pktlen - total bytes (delims + data + fcs + pads + pad delims)
961 * width - 0 for 20 MHz, 1 for 40 MHz
962 * half_gi - to use 4us v/s 3.6 us for symbol time
964 static u32
ath_pkt_duration(struct ath_softc
*sc
, u8 rix
, int pktlen
,
965 int width
, int half_gi
, bool shortPreamble
)
967 u32 nbits
, nsymbits
, duration
, nsymbols
;
970 /* find number of symbols: PLCP + data */
971 streams
= HT_RC_2_STREAMS(rix
);
972 nbits
= (pktlen
<< 3) + OFDM_PLCP_BITS
;
973 nsymbits
= bits_per_symbol
[rix
% 8][width
] * streams
;
974 nsymbols
= (nbits
+ nsymbits
- 1) / nsymbits
;
977 duration
= SYMBOL_TIME(nsymbols
);
979 duration
= SYMBOL_TIME_HALFGI(nsymbols
);
981 /* addup duration for legacy/ht training and signal fields */
982 duration
+= L_STF
+ L_LTF
+ L_SIG
+ HT_SIG
+ HT_STF
+ HT_LTF(streams
);
987 static int ath_max_framelen(int usec
, int mcs
, bool ht40
, bool sgi
)
989 int streams
= HT_RC_2_STREAMS(mcs
);
993 symbols
= sgi
? TIME_SYMBOLS_HALFGI(usec
) : TIME_SYMBOLS(usec
);
994 bits
= symbols
* bits_per_symbol
[mcs
% 8][ht40
] * streams
;
995 bits
-= OFDM_PLCP_BITS
;
997 bytes
-= L_STF
+ L_LTF
+ L_SIG
+ HT_SIG
+ HT_STF
+ HT_LTF(streams
);
1004 void ath_update_max_aggr_framelen(struct ath_softc
*sc
, int queue
, int txop
)
1006 u16
*cur_ht20
, *cur_ht20_sgi
, *cur_ht40
, *cur_ht40_sgi
;
1009 /* 4ms is the default (and maximum) duration */
1010 if (!txop
|| txop
> 4096)
1013 cur_ht20
= sc
->tx
.max_aggr_framelen
[queue
][MCS_HT20
];
1014 cur_ht20_sgi
= sc
->tx
.max_aggr_framelen
[queue
][MCS_HT20_SGI
];
1015 cur_ht40
= sc
->tx
.max_aggr_framelen
[queue
][MCS_HT40
];
1016 cur_ht40_sgi
= sc
->tx
.max_aggr_framelen
[queue
][MCS_HT40_SGI
];
1017 for (mcs
= 0; mcs
< 32; mcs
++) {
1018 cur_ht20
[mcs
] = ath_max_framelen(txop
, mcs
, false, false);
1019 cur_ht20_sgi
[mcs
] = ath_max_framelen(txop
, mcs
, false, true);
1020 cur_ht40
[mcs
] = ath_max_framelen(txop
, mcs
, true, false);
1021 cur_ht40_sgi
[mcs
] = ath_max_framelen(txop
, mcs
, true, true);
1025 static void ath_buf_set_rate(struct ath_softc
*sc
, struct ath_buf
*bf
,
1026 struct ath_tx_info
*info
, int len
)
1028 struct ath_hw
*ah
= sc
->sc_ah
;
1029 struct sk_buff
*skb
;
1030 struct ieee80211_tx_info
*tx_info
;
1031 struct ieee80211_tx_rate
*rates
;
1032 const struct ieee80211_rate
*rate
;
1033 struct ieee80211_hdr
*hdr
;
1034 struct ath_frame_info
*fi
= get_frame_info(bf
->bf_mpdu
);
1039 tx_info
= IEEE80211_SKB_CB(skb
);
1041 hdr
= (struct ieee80211_hdr
*)skb
->data
;
1043 /* set dur_update_en for l-sig computation except for PS-Poll frames */
1044 info
->dur_update
= !ieee80211_is_pspoll(hdr
->frame_control
);
1045 info
->rtscts_rate
= fi
->rtscts_rate
;
1047 for (i
= 0; i
< ARRAY_SIZE(bf
->rates
); i
++) {
1048 bool is_40
, is_sgi
, is_sp
;
1051 if (!rates
[i
].count
|| (rates
[i
].idx
< 0))
1055 info
->rates
[i
].Tries
= rates
[i
].count
;
1057 if (rates
[i
].flags
& IEEE80211_TX_RC_USE_RTS_CTS
) {
1058 info
->rates
[i
].RateFlags
|= ATH9K_RATESERIES_RTS_CTS
;
1059 info
->flags
|= ATH9K_TXDESC_RTSENA
;
1060 } else if (rates
[i
].flags
& IEEE80211_TX_RC_USE_CTS_PROTECT
) {
1061 info
->rates
[i
].RateFlags
|= ATH9K_RATESERIES_RTS_CTS
;
1062 info
->flags
|= ATH9K_TXDESC_CTSENA
;
1065 if (rates
[i
].flags
& IEEE80211_TX_RC_40_MHZ_WIDTH
)
1066 info
->rates
[i
].RateFlags
|= ATH9K_RATESERIES_2040
;
1067 if (rates
[i
].flags
& IEEE80211_TX_RC_SHORT_GI
)
1068 info
->rates
[i
].RateFlags
|= ATH9K_RATESERIES_HALFGI
;
1070 is_sgi
= !!(rates
[i
].flags
& IEEE80211_TX_RC_SHORT_GI
);
1071 is_40
= !!(rates
[i
].flags
& IEEE80211_TX_RC_40_MHZ_WIDTH
);
1072 is_sp
= !!(rates
[i
].flags
& IEEE80211_TX_RC_USE_SHORT_PREAMBLE
);
1074 if (rates
[i
].flags
& IEEE80211_TX_RC_MCS
) {
1076 info
->rates
[i
].Rate
= rix
| 0x80;
1077 info
->rates
[i
].ChSel
= ath_txchainmask_reduction(sc
,
1078 ah
->txchainmask
, info
->rates
[i
].Rate
);
1079 info
->rates
[i
].PktDuration
= ath_pkt_duration(sc
, rix
, len
,
1080 is_40
, is_sgi
, is_sp
);
1081 if (rix
< 8 && (tx_info
->flags
& IEEE80211_TX_CTL_STBC
))
1082 info
->rates
[i
].RateFlags
|= ATH9K_RATESERIES_STBC
;
1087 rate
= &sc
->sbands
[tx_info
->band
].bitrates
[rates
[i
].idx
];
1088 if ((tx_info
->band
== IEEE80211_BAND_2GHZ
) &&
1089 !(rate
->flags
& IEEE80211_RATE_ERP_G
))
1090 phy
= WLAN_RC_PHY_CCK
;
1092 phy
= WLAN_RC_PHY_OFDM
;
1094 info
->rates
[i
].Rate
= rate
->hw_value
;
1095 if (rate
->hw_value_short
) {
1096 if (rates
[i
].flags
& IEEE80211_TX_RC_USE_SHORT_PREAMBLE
)
1097 info
->rates
[i
].Rate
|= rate
->hw_value_short
;
1102 if (bf
->bf_state
.bfs_paprd
)
1103 info
->rates
[i
].ChSel
= ah
->txchainmask
;
1105 info
->rates
[i
].ChSel
= ath_txchainmask_reduction(sc
,
1106 ah
->txchainmask
, info
->rates
[i
].Rate
);
1108 info
->rates
[i
].PktDuration
= ath9k_hw_computetxtime(sc
->sc_ah
,
1109 phy
, rate
->bitrate
* 100, len
, rix
, is_sp
);
1112 /* For AR5416 - RTS cannot be followed by a frame larger than 8K */
1113 if (bf_isaggr(bf
) && (len
> sc
->sc_ah
->caps
.rts_aggr_limit
))
1114 info
->flags
&= ~ATH9K_TXDESC_RTSENA
;
1116 /* ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive. */
1117 if (info
->flags
& ATH9K_TXDESC_RTSENA
)
1118 info
->flags
&= ~ATH9K_TXDESC_CTSENA
;
1121 static enum ath9k_pkt_type
get_hw_packet_type(struct sk_buff
*skb
)
1123 struct ieee80211_hdr
*hdr
;
1124 enum ath9k_pkt_type htype
;
1127 hdr
= (struct ieee80211_hdr
*)skb
->data
;
1128 fc
= hdr
->frame_control
;
1130 if (ieee80211_is_beacon(fc
))
1131 htype
= ATH9K_PKT_TYPE_BEACON
;
1132 else if (ieee80211_is_probe_resp(fc
))
1133 htype
= ATH9K_PKT_TYPE_PROBE_RESP
;
1134 else if (ieee80211_is_atim(fc
))
1135 htype
= ATH9K_PKT_TYPE_ATIM
;
1136 else if (ieee80211_is_pspoll(fc
))
1137 htype
= ATH9K_PKT_TYPE_PSPOLL
;
1139 htype
= ATH9K_PKT_TYPE_NORMAL
;
1144 static void ath_tx_fill_desc(struct ath_softc
*sc
, struct ath_buf
*bf
,
1145 struct ath_txq
*txq
, int len
)
1147 struct ath_hw
*ah
= sc
->sc_ah
;
1148 struct ath_buf
*bf_first
= NULL
;
1149 struct ath_tx_info info
;
1151 memset(&info
, 0, sizeof(info
));
1152 info
.is_first
= true;
1153 info
.is_last
= true;
1154 info
.txpower
= MAX_RATE_POWER
;
1155 info
.qcu
= txq
->axq_qnum
;
1158 struct sk_buff
*skb
= bf
->bf_mpdu
;
1159 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
1160 struct ath_frame_info
*fi
= get_frame_info(skb
);
1161 bool aggr
= !!(bf
->bf_state
.bf_type
& BUF_AGGR
);
1163 info
.type
= get_hw_packet_type(skb
);
1165 info
.link
= bf
->bf_next
->bf_daddr
;
1172 info
.flags
= ATH9K_TXDESC_INTREQ
;
1173 if ((tx_info
->flags
& IEEE80211_TX_CTL_CLEAR_PS_FILT
) ||
1174 txq
== sc
->tx
.uapsdq
)
1175 info
.flags
|= ATH9K_TXDESC_CLRDMASK
;
1177 if (tx_info
->flags
& IEEE80211_TX_CTL_NO_ACK
)
1178 info
.flags
|= ATH9K_TXDESC_NOACK
;
1179 if (tx_info
->flags
& IEEE80211_TX_CTL_LDPC
)
1180 info
.flags
|= ATH9K_TXDESC_LDPC
;
1182 if (bf
->bf_state
.bfs_paprd
)
1183 info
.flags
|= (u32
) bf
->bf_state
.bfs_paprd
<<
1184 ATH9K_TXDESC_PAPRD_S
;
1186 ath_buf_set_rate(sc
, bf
, &info
, len
);
1189 info
.buf_addr
[0] = bf
->bf_buf_addr
;
1190 info
.buf_len
[0] = skb
->len
;
1191 info
.pkt_len
= fi
->framelen
;
1192 info
.keyix
= fi
->keyix
;
1193 info
.keytype
= fi
->keytype
;
1197 info
.aggr
= AGGR_BUF_FIRST
;
1198 else if (bf
== bf_first
->bf_lastbf
)
1199 info
.aggr
= AGGR_BUF_LAST
;
1201 info
.aggr
= AGGR_BUF_MIDDLE
;
1203 info
.ndelim
= bf
->bf_state
.ndelim
;
1204 info
.aggr_len
= len
;
1207 if (bf
== bf_first
->bf_lastbf
)
1210 ath9k_hw_set_txdesc(ah
, bf
->bf_desc
, &info
);
1215 static void ath_tx_sched_aggr(struct ath_softc
*sc
, struct ath_txq
*txq
,
1216 struct ath_atx_tid
*tid
)
1219 enum ATH_AGGR_STATUS status
;
1220 struct ieee80211_tx_info
*tx_info
;
1221 struct list_head bf_q
;
1225 if (skb_queue_empty(&tid
->buf_q
))
1228 INIT_LIST_HEAD(&bf_q
);
1230 status
= ath_tx_form_aggr(sc
, txq
, tid
, &bf_q
, &aggr_len
);
1233 * no frames picked up to be aggregated;
1234 * block-ack window is not open.
1236 if (list_empty(&bf_q
))
1239 bf
= list_first_entry(&bf_q
, struct ath_buf
, list
);
1240 bf
->bf_lastbf
= list_entry(bf_q
.prev
, struct ath_buf
, list
);
1241 tx_info
= IEEE80211_SKB_CB(bf
->bf_mpdu
);
1243 if (tid
->ac
->clear_ps_filter
) {
1244 tid
->ac
->clear_ps_filter
= false;
1245 tx_info
->flags
|= IEEE80211_TX_CTL_CLEAR_PS_FILT
;
1247 tx_info
->flags
&= ~IEEE80211_TX_CTL_CLEAR_PS_FILT
;
1250 /* if only one frame, send as non-aggregate */
1251 if (bf
== bf
->bf_lastbf
) {
1252 aggr_len
= get_frame_info(bf
->bf_mpdu
)->framelen
;
1253 bf
->bf_state
.bf_type
= BUF_AMPDU
;
1255 TX_STAT_INC(txq
->axq_qnum
, a_aggr
);
1258 ath_tx_fill_desc(sc
, bf
, txq
, aggr_len
);
1259 ath_tx_txqaddbuf(sc
, txq
, &bf_q
, false);
1260 } while (txq
->axq_ampdu_depth
< ATH_AGGR_MIN_QDEPTH
&&
1261 status
!= ATH_AGGR_BAW_CLOSED
);
1264 int ath_tx_aggr_start(struct ath_softc
*sc
, struct ieee80211_sta
*sta
,
1267 struct ath_atx_tid
*txtid
;
1268 struct ath_node
*an
;
1271 an
= (struct ath_node
*)sta
->drv_priv
;
1272 txtid
= ATH_AN_2_TID(an
, tid
);
1274 /* update ampdu factor/density, they may have changed. This may happen
1275 * in HT IBSS when a beacon with HT-info is received after the station
1276 * has already been added.
1278 if (sta
->ht_cap
.ht_supported
) {
1279 an
->maxampdu
= 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR
+
1280 sta
->ht_cap
.ampdu_factor
);
1281 density
= ath9k_parse_mpdudensity(sta
->ht_cap
.ampdu_density
);
1282 an
->mpdudensity
= density
;
1285 txtid
->active
= true;
1286 txtid
->paused
= true;
1287 *ssn
= txtid
->seq_start
= txtid
->seq_next
;
1288 txtid
->bar_index
= -1;
1290 memset(txtid
->tx_buf
, 0, sizeof(txtid
->tx_buf
));
1291 txtid
->baw_head
= txtid
->baw_tail
= 0;
1296 void ath_tx_aggr_stop(struct ath_softc
*sc
, struct ieee80211_sta
*sta
, u16 tid
)
1298 struct ath_node
*an
= (struct ath_node
*)sta
->drv_priv
;
1299 struct ath_atx_tid
*txtid
= ATH_AN_2_TID(an
, tid
);
1300 struct ath_txq
*txq
= txtid
->ac
->txq
;
1302 ath_txq_lock(sc
, txq
);
1303 txtid
->active
= false;
1304 txtid
->paused
= true;
1305 ath_tx_flush_tid(sc
, txtid
);
1306 ath_txq_unlock_complete(sc
, txq
);
1309 void ath_tx_aggr_sleep(struct ieee80211_sta
*sta
, struct ath_softc
*sc
,
1310 struct ath_node
*an
)
1312 struct ath_atx_tid
*tid
;
1313 struct ath_atx_ac
*ac
;
1314 struct ath_txq
*txq
;
1318 for (tidno
= 0, tid
= &an
->tid
[tidno
];
1319 tidno
< IEEE80211_NUM_TIDS
; tidno
++, tid
++) {
1327 ath_txq_lock(sc
, txq
);
1329 buffered
= !skb_queue_empty(&tid
->buf_q
);
1332 list_del(&tid
->list
);
1336 list_del(&ac
->list
);
1339 ath_txq_unlock(sc
, txq
);
1341 ieee80211_sta_set_buffered(sta
, tidno
, buffered
);
1345 void ath_tx_aggr_wakeup(struct ath_softc
*sc
, struct ath_node
*an
)
1347 struct ath_atx_tid
*tid
;
1348 struct ath_atx_ac
*ac
;
1349 struct ath_txq
*txq
;
1352 for (tidno
= 0, tid
= &an
->tid
[tidno
];
1353 tidno
< IEEE80211_NUM_TIDS
; tidno
++, tid
++) {
1358 ath_txq_lock(sc
, txq
);
1359 ac
->clear_ps_filter
= true;
1361 if (!skb_queue_empty(&tid
->buf_q
) && !tid
->paused
) {
1362 ath_tx_queue_tid(txq
, tid
);
1363 ath_txq_schedule(sc
, txq
);
1366 ath_txq_unlock_complete(sc
, txq
);
1370 void ath_tx_aggr_resume(struct ath_softc
*sc
, struct ieee80211_sta
*sta
,
1373 struct ath_atx_tid
*tid
;
1374 struct ath_node
*an
;
1375 struct ath_txq
*txq
;
1377 an
= (struct ath_node
*)sta
->drv_priv
;
1378 tid
= ATH_AN_2_TID(an
, tidno
);
1381 ath_txq_lock(sc
, txq
);
1383 tid
->baw_size
= IEEE80211_MIN_AMPDU_BUF
<< sta
->ht_cap
.ampdu_factor
;
1384 tid
->paused
= false;
1386 if (!skb_queue_empty(&tid
->buf_q
)) {
1387 ath_tx_queue_tid(txq
, tid
);
1388 ath_txq_schedule(sc
, txq
);
1391 ath_txq_unlock_complete(sc
, txq
);
1394 void ath9k_release_buffered_frames(struct ieee80211_hw
*hw
,
1395 struct ieee80211_sta
*sta
,
1396 u16 tids
, int nframes
,
1397 enum ieee80211_frame_release_type reason
,
1400 struct ath_softc
*sc
= hw
->priv
;
1401 struct ath_node
*an
= (struct ath_node
*)sta
->drv_priv
;
1402 struct ath_txq
*txq
= sc
->tx
.uapsdq
;
1403 struct ieee80211_tx_info
*info
;
1404 struct list_head bf_q
;
1405 struct ath_buf
*bf_tail
= NULL
, *bf
;
1409 INIT_LIST_HEAD(&bf_q
);
1410 for (i
= 0; tids
&& nframes
; i
++, tids
>>= 1) {
1411 struct ath_atx_tid
*tid
;
1416 tid
= ATH_AN_2_TID(an
, i
);
1420 ath_txq_lock(sc
, tid
->ac
->txq
);
1421 while (!skb_queue_empty(&tid
->buf_q
) && nframes
> 0) {
1422 bf
= ath_tx_get_tid_subframe(sc
, sc
->tx
.uapsdq
, tid
);
1426 __skb_unlink(bf
->bf_mpdu
, &tid
->buf_q
);
1427 list_add_tail(&bf
->list
, &bf_q
);
1428 ath_set_rates(tid
->an
->vif
, tid
->an
->sta
, bf
);
1429 ath_tx_addto_baw(sc
, tid
, bf
->bf_state
.seqno
);
1430 bf
->bf_state
.bf_type
&= ~BUF_AGGR
;
1432 bf_tail
->bf_next
= bf
;
1437 TX_STAT_INC(txq
->axq_qnum
, a_queued_hw
);
1439 if (skb_queue_empty(&tid
->buf_q
))
1440 ieee80211_sta_set_buffered(an
->sta
, i
, false);
1442 ath_txq_unlock_complete(sc
, tid
->ac
->txq
);
1445 if (list_empty(&bf_q
))
1448 info
= IEEE80211_SKB_CB(bf_tail
->bf_mpdu
);
1449 info
->flags
|= IEEE80211_TX_STATUS_EOSP
;
1451 bf
= list_first_entry(&bf_q
, struct ath_buf
, list
);
1452 ath_txq_lock(sc
, txq
);
1453 ath_tx_fill_desc(sc
, bf
, txq
, 0);
1454 ath_tx_txqaddbuf(sc
, txq
, &bf_q
, false);
1455 ath_txq_unlock(sc
, txq
);
1458 /********************/
1459 /* Queue Management */
1460 /********************/
1462 struct ath_txq
*ath_txq_setup(struct ath_softc
*sc
, int qtype
, int subtype
)
1464 struct ath_hw
*ah
= sc
->sc_ah
;
1465 struct ath9k_tx_queue_info qi
;
1466 static const int subtype_txq_to_hwq
[] = {
1467 [IEEE80211_AC_BE
] = ATH_TXQ_AC_BE
,
1468 [IEEE80211_AC_BK
] = ATH_TXQ_AC_BK
,
1469 [IEEE80211_AC_VI
] = ATH_TXQ_AC_VI
,
1470 [IEEE80211_AC_VO
] = ATH_TXQ_AC_VO
,
1474 memset(&qi
, 0, sizeof(qi
));
1475 qi
.tqi_subtype
= subtype_txq_to_hwq
[subtype
];
1476 qi
.tqi_aifs
= ATH9K_TXQ_USEDEFAULT
;
1477 qi
.tqi_cwmin
= ATH9K_TXQ_USEDEFAULT
;
1478 qi
.tqi_cwmax
= ATH9K_TXQ_USEDEFAULT
;
1479 qi
.tqi_physCompBuf
= 0;
1482 * Enable interrupts only for EOL and DESC conditions.
1483 * We mark tx descriptors to receive a DESC interrupt
1484 * when a tx queue gets deep; otherwise waiting for the
1485 * EOL to reap descriptors. Note that this is done to
1486 * reduce interrupt load and this only defers reaping
1487 * descriptors, never transmitting frames. Aside from
1488 * reducing interrupts this also permits more concurrency.
1489 * The only potential downside is if the tx queue backs
1490 * up in which case the top half of the kernel may backup
1491 * due to a lack of tx descriptors.
1493 * The UAPSD queue is an exception, since we take a desc-
1494 * based intr on the EOSP frames.
1496 if (ah
->caps
.hw_caps
& ATH9K_HW_CAP_EDMA
) {
1497 qi
.tqi_qflags
= TXQ_FLAG_TXINT_ENABLE
;
1499 if (qtype
== ATH9K_TX_QUEUE_UAPSD
)
1500 qi
.tqi_qflags
= TXQ_FLAG_TXDESCINT_ENABLE
;
1502 qi
.tqi_qflags
= TXQ_FLAG_TXEOLINT_ENABLE
|
1503 TXQ_FLAG_TXDESCINT_ENABLE
;
1505 axq_qnum
= ath9k_hw_setuptxqueue(ah
, qtype
, &qi
);
1506 if (axq_qnum
== -1) {
1508 * NB: don't print a message, this happens
1509 * normally on parts with too few tx queues
1513 if (!ATH_TXQ_SETUP(sc
, axq_qnum
)) {
1514 struct ath_txq
*txq
= &sc
->tx
.txq
[axq_qnum
];
1516 txq
->axq_qnum
= axq_qnum
;
1517 txq
->mac80211_qnum
= -1;
1518 txq
->axq_link
= NULL
;
1519 __skb_queue_head_init(&txq
->complete_q
);
1520 INIT_LIST_HEAD(&txq
->axq_q
);
1521 INIT_LIST_HEAD(&txq
->axq_acq
);
1522 spin_lock_init(&txq
->axq_lock
);
1524 txq
->axq_ampdu_depth
= 0;
1525 txq
->axq_tx_inprogress
= false;
1526 sc
->tx
.txqsetup
|= 1<<axq_qnum
;
1528 txq
->txq_headidx
= txq
->txq_tailidx
= 0;
1529 for (i
= 0; i
< ATH_TXFIFO_DEPTH
; i
++)
1530 INIT_LIST_HEAD(&txq
->txq_fifo
[i
]);
1532 return &sc
->tx
.txq
[axq_qnum
];
1535 int ath_txq_update(struct ath_softc
*sc
, int qnum
,
1536 struct ath9k_tx_queue_info
*qinfo
)
1538 struct ath_hw
*ah
= sc
->sc_ah
;
1540 struct ath9k_tx_queue_info qi
;
1542 BUG_ON(sc
->tx
.txq
[qnum
].axq_qnum
!= qnum
);
1544 ath9k_hw_get_txq_props(ah
, qnum
, &qi
);
1545 qi
.tqi_aifs
= qinfo
->tqi_aifs
;
1546 qi
.tqi_cwmin
= qinfo
->tqi_cwmin
;
1547 qi
.tqi_cwmax
= qinfo
->tqi_cwmax
;
1548 qi
.tqi_burstTime
= qinfo
->tqi_burstTime
;
1549 qi
.tqi_readyTime
= qinfo
->tqi_readyTime
;
1551 if (!ath9k_hw_set_txq_props(ah
, qnum
, &qi
)) {
1552 ath_err(ath9k_hw_common(sc
->sc_ah
),
1553 "Unable to update hardware queue %u!\n", qnum
);
1556 ath9k_hw_resettxqueue(ah
, qnum
);
1562 int ath_cabq_update(struct ath_softc
*sc
)
1564 struct ath9k_tx_queue_info qi
;
1565 struct ath_beacon_config
*cur_conf
= &sc
->cur_beacon_conf
;
1566 int qnum
= sc
->beacon
.cabq
->axq_qnum
;
1568 ath9k_hw_get_txq_props(sc
->sc_ah
, qnum
, &qi
);
1570 * Ensure the readytime % is within the bounds.
1572 if (sc
->config
.cabqReadytime
< ATH9K_READY_TIME_LO_BOUND
)
1573 sc
->config
.cabqReadytime
= ATH9K_READY_TIME_LO_BOUND
;
1574 else if (sc
->config
.cabqReadytime
> ATH9K_READY_TIME_HI_BOUND
)
1575 sc
->config
.cabqReadytime
= ATH9K_READY_TIME_HI_BOUND
;
1577 qi
.tqi_readyTime
= (cur_conf
->beacon_interval
*
1578 sc
->config
.cabqReadytime
) / 100;
1579 ath_txq_update(sc
, qnum
, &qi
);
1584 static void ath_drain_txq_list(struct ath_softc
*sc
, struct ath_txq
*txq
,
1585 struct list_head
*list
)
1587 struct ath_buf
*bf
, *lastbf
;
1588 struct list_head bf_head
;
1589 struct ath_tx_status ts
;
1591 memset(&ts
, 0, sizeof(ts
));
1592 ts
.ts_status
= ATH9K_TX_FLUSH
;
1593 INIT_LIST_HEAD(&bf_head
);
1595 while (!list_empty(list
)) {
1596 bf
= list_first_entry(list
, struct ath_buf
, list
);
1599 list_del(&bf
->list
);
1601 ath_tx_return_buffer(sc
, bf
);
1605 lastbf
= bf
->bf_lastbf
;
1606 list_cut_position(&bf_head
, list
, &lastbf
->list
);
1607 ath_tx_process_buffer(sc
, txq
, &ts
, bf
, &bf_head
);
1612 * Drain a given TX queue (could be Beacon or Data)
1614 * This assumes output has been stopped and
1615 * we do not need to block ath_tx_tasklet.
1617 void ath_draintxq(struct ath_softc
*sc
, struct ath_txq
*txq
)
1619 ath_txq_lock(sc
, txq
);
1621 if (sc
->sc_ah
->caps
.hw_caps
& ATH9K_HW_CAP_EDMA
) {
1622 int idx
= txq
->txq_tailidx
;
1624 while (!list_empty(&txq
->txq_fifo
[idx
])) {
1625 ath_drain_txq_list(sc
, txq
, &txq
->txq_fifo
[idx
]);
1627 INCR(idx
, ATH_TXFIFO_DEPTH
);
1629 txq
->txq_tailidx
= idx
;
1632 txq
->axq_link
= NULL
;
1633 txq
->axq_tx_inprogress
= false;
1634 ath_drain_txq_list(sc
, txq
, &txq
->axq_q
);
1636 ath_txq_unlock_complete(sc
, txq
);
1639 bool ath_drain_all_txq(struct ath_softc
*sc
)
1641 struct ath_hw
*ah
= sc
->sc_ah
;
1642 struct ath_common
*common
= ath9k_hw_common(sc
->sc_ah
);
1643 struct ath_txq
*txq
;
1647 if (test_bit(SC_OP_INVALID
, &sc
->sc_flags
))
1650 ath9k_hw_abort_tx_dma(ah
);
1652 /* Check if any queue remains active */
1653 for (i
= 0; i
< ATH9K_NUM_TX_QUEUES
; i
++) {
1654 if (!ATH_TXQ_SETUP(sc
, i
))
1657 if (ath9k_hw_numtxpending(ah
, sc
->tx
.txq
[i
].axq_qnum
))
1662 ath_err(common
, "Failed to stop TX DMA, queues=0x%03x!\n", npend
);
1664 for (i
= 0; i
< ATH9K_NUM_TX_QUEUES
; i
++) {
1665 if (!ATH_TXQ_SETUP(sc
, i
))
1669 * The caller will resume queues with ieee80211_wake_queues.
1670 * Mark the queue as not stopped to prevent ath_tx_complete
1671 * from waking the queue too early.
1673 txq
= &sc
->tx
.txq
[i
];
1674 txq
->stopped
= false;
1675 ath_draintxq(sc
, txq
);
1681 void ath_tx_cleanupq(struct ath_softc
*sc
, struct ath_txq
*txq
)
1683 ath9k_hw_releasetxqueue(sc
->sc_ah
, txq
->axq_qnum
);
1684 sc
->tx
.txqsetup
&= ~(1<<txq
->axq_qnum
);
1687 /* For each axq_acq entry, for each tid, try to schedule packets
1688 * for transmit until ampdu_depth has reached min Q depth.
1690 void ath_txq_schedule(struct ath_softc
*sc
, struct ath_txq
*txq
)
1692 struct ath_atx_ac
*ac
, *ac_tmp
, *last_ac
;
1693 struct ath_atx_tid
*tid
, *last_tid
;
1695 if (test_bit(SC_OP_HW_RESET
, &sc
->sc_flags
) ||
1696 list_empty(&txq
->axq_acq
) ||
1697 txq
->axq_ampdu_depth
>= ATH_AGGR_MIN_QDEPTH
)
1702 ac
= list_first_entry(&txq
->axq_acq
, struct ath_atx_ac
, list
);
1703 last_ac
= list_entry(txq
->axq_acq
.prev
, struct ath_atx_ac
, list
);
1705 list_for_each_entry_safe(ac
, ac_tmp
, &txq
->axq_acq
, list
) {
1706 last_tid
= list_entry(ac
->tid_q
.prev
, struct ath_atx_tid
, list
);
1707 list_del(&ac
->list
);
1710 while (!list_empty(&ac
->tid_q
)) {
1711 tid
= list_first_entry(&ac
->tid_q
, struct ath_atx_tid
,
1713 list_del(&tid
->list
);
1719 ath_tx_sched_aggr(sc
, txq
, tid
);
1722 * add tid to round-robin queue if more frames
1723 * are pending for the tid
1725 if (!skb_queue_empty(&tid
->buf_q
))
1726 ath_tx_queue_tid(txq
, tid
);
1728 if (tid
== last_tid
||
1729 txq
->axq_ampdu_depth
>= ATH_AGGR_MIN_QDEPTH
)
1733 if (!list_empty(&ac
->tid_q
) && !ac
->sched
) {
1735 list_add_tail(&ac
->list
, &txq
->axq_acq
);
1738 if (ac
== last_ac
||
1739 txq
->axq_ampdu_depth
>= ATH_AGGR_MIN_QDEPTH
)
1751 * Insert a chain of ath_buf (descriptors) on a txq and
1752 * assume the descriptors are already chained together by caller.
1754 static void ath_tx_txqaddbuf(struct ath_softc
*sc
, struct ath_txq
*txq
,
1755 struct list_head
*head
, bool internal
)
1757 struct ath_hw
*ah
= sc
->sc_ah
;
1758 struct ath_common
*common
= ath9k_hw_common(ah
);
1759 struct ath_buf
*bf
, *bf_last
;
1760 bool puttxbuf
= false;
1764 * Insert the frame on the outbound list and
1765 * pass it on to the hardware.
1768 if (list_empty(head
))
1771 edma
= !!(ah
->caps
.hw_caps
& ATH9K_HW_CAP_EDMA
);
1772 bf
= list_first_entry(head
, struct ath_buf
, list
);
1773 bf_last
= list_entry(head
->prev
, struct ath_buf
, list
);
1775 ath_dbg(common
, QUEUE
, "qnum: %d, txq depth: %d\n",
1776 txq
->axq_qnum
, txq
->axq_depth
);
1778 if (edma
&& list_empty(&txq
->txq_fifo
[txq
->txq_headidx
])) {
1779 list_splice_tail_init(head
, &txq
->txq_fifo
[txq
->txq_headidx
]);
1780 INCR(txq
->txq_headidx
, ATH_TXFIFO_DEPTH
);
1783 list_splice_tail_init(head
, &txq
->axq_q
);
1785 if (txq
->axq_link
) {
1786 ath9k_hw_set_desc_link(ah
, txq
->axq_link
, bf
->bf_daddr
);
1787 ath_dbg(common
, XMIT
, "link[%u] (%p)=%llx (%p)\n",
1788 txq
->axq_qnum
, txq
->axq_link
,
1789 ito64(bf
->bf_daddr
), bf
->bf_desc
);
1793 txq
->axq_link
= bf_last
->bf_desc
;
1797 TX_STAT_INC(txq
->axq_qnum
, puttxbuf
);
1798 ath9k_hw_puttxbuf(ah
, txq
->axq_qnum
, bf
->bf_daddr
);
1799 ath_dbg(common
, XMIT
, "TXDP[%u] = %llx (%p)\n",
1800 txq
->axq_qnum
, ito64(bf
->bf_daddr
), bf
->bf_desc
);
1804 TX_STAT_INC(txq
->axq_qnum
, txstart
);
1805 ath9k_hw_txstart(ah
, txq
->axq_qnum
);
1811 if (bf_is_ampdu_not_probing(bf
))
1812 txq
->axq_ampdu_depth
++;
1814 bf
= bf
->bf_lastbf
->bf_next
;
1819 static void ath_tx_send_ampdu(struct ath_softc
*sc
, struct ath_txq
*txq
,
1820 struct ath_atx_tid
*tid
, struct sk_buff
*skb
,
1821 struct ath_tx_control
*txctl
)
1823 struct ath_frame_info
*fi
= get_frame_info(skb
);
1824 struct list_head bf_head
;
1828 * Do not queue to h/w when any of the following conditions is true:
1829 * - there are pending frames in software queue
1830 * - the TID is currently paused for ADDBA/BAR request
1831 * - seqno is not within block-ack window
1832 * - h/w queue depth exceeds low water mark
1834 if ((!skb_queue_empty(&tid
->buf_q
) || tid
->paused
||
1835 !BAW_WITHIN(tid
->seq_start
, tid
->baw_size
, tid
->seq_next
) ||
1836 txq
->axq_ampdu_depth
>= ATH_AGGR_MIN_QDEPTH
) &&
1837 txq
!= sc
->tx
.uapsdq
) {
1839 * Add this frame to software queue for scheduling later
1842 TX_STAT_INC(txq
->axq_qnum
, a_queued_sw
);
1843 __skb_queue_tail(&tid
->buf_q
, skb
);
1844 if (!txctl
->an
|| !txctl
->an
->sleeping
)
1845 ath_tx_queue_tid(txq
, tid
);
1849 bf
= ath_tx_setup_buffer(sc
, txq
, tid
, skb
);
1851 ath_txq_skb_done(sc
, txq
, skb
);
1852 ieee80211_free_txskb(sc
->hw
, skb
);
1856 ath_set_rates(tid
->an
->vif
, tid
->an
->sta
, bf
);
1857 bf
->bf_state
.bf_type
= BUF_AMPDU
;
1858 INIT_LIST_HEAD(&bf_head
);
1859 list_add(&bf
->list
, &bf_head
);
1861 /* Add sub-frame to BAW */
1862 ath_tx_addto_baw(sc
, tid
, bf
->bf_state
.seqno
);
1864 /* Queue to h/w without aggregation */
1865 TX_STAT_INC(txq
->axq_qnum
, a_queued_hw
);
1867 ath_tx_fill_desc(sc
, bf
, txq
, fi
->framelen
);
1868 ath_tx_txqaddbuf(sc
, txq
, &bf_head
, false);
1871 static void ath_tx_send_normal(struct ath_softc
*sc
, struct ath_txq
*txq
,
1872 struct ath_atx_tid
*tid
, struct sk_buff
*skb
)
1874 struct ath_frame_info
*fi
= get_frame_info(skb
);
1875 struct list_head bf_head
;
1880 INIT_LIST_HEAD(&bf_head
);
1881 list_add_tail(&bf
->list
, &bf_head
);
1882 bf
->bf_state
.bf_type
= 0;
1886 ath_tx_fill_desc(sc
, bf
, txq
, fi
->framelen
);
1887 ath_tx_txqaddbuf(sc
, txq
, &bf_head
, false);
1888 TX_STAT_INC(txq
->axq_qnum
, queued
);
1891 static void setup_frame_info(struct ieee80211_hw
*hw
,
1892 struct ieee80211_sta
*sta
,
1893 struct sk_buff
*skb
,
1896 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
1897 struct ieee80211_key_conf
*hw_key
= tx_info
->control
.hw_key
;
1898 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*)skb
->data
;
1899 const struct ieee80211_rate
*rate
;
1900 struct ath_frame_info
*fi
= get_frame_info(skb
);
1901 struct ath_node
*an
= NULL
;
1902 enum ath9k_key_type keytype
;
1903 bool short_preamble
= false;
1906 * We check if Short Preamble is needed for the CTS rate by
1907 * checking the BSS's global flag.
1908 * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used.
1910 if (tx_info
->control
.vif
&&
1911 tx_info
->control
.vif
->bss_conf
.use_short_preamble
)
1912 short_preamble
= true;
1914 rate
= ieee80211_get_rts_cts_rate(hw
, tx_info
);
1915 keytype
= ath9k_cmn_get_hw_crypto_keytype(skb
);
1918 an
= (struct ath_node
*) sta
->drv_priv
;
1920 memset(fi
, 0, sizeof(*fi
));
1922 fi
->keyix
= hw_key
->hw_key_idx
;
1923 else if (an
&& ieee80211_is_data(hdr
->frame_control
) && an
->ps_key
> 0)
1924 fi
->keyix
= an
->ps_key
;
1926 fi
->keyix
= ATH9K_TXKEYIX_INVALID
;
1927 fi
->keytype
= keytype
;
1928 fi
->framelen
= framelen
;
1929 fi
->rtscts_rate
= rate
->hw_value
;
1931 fi
->rtscts_rate
|= rate
->hw_value_short
;
1934 u8
ath_txchainmask_reduction(struct ath_softc
*sc
, u8 chainmask
, u32 rate
)
1936 struct ath_hw
*ah
= sc
->sc_ah
;
1937 struct ath9k_channel
*curchan
= ah
->curchan
;
1939 if ((ah
->caps
.hw_caps
& ATH9K_HW_CAP_APM
) &&
1940 (curchan
->channelFlags
& CHANNEL_5GHZ
) &&
1941 (chainmask
== 0x7) && (rate
< 0x90))
1943 else if (AR_SREV_9462(ah
) && ath9k_hw_btcoex_is_enabled(ah
) &&
1951 * Assign a descriptor (and sequence number if necessary,
1952 * and map buffer for DMA. Frees skb on error
1954 static struct ath_buf
*ath_tx_setup_buffer(struct ath_softc
*sc
,
1955 struct ath_txq
*txq
,
1956 struct ath_atx_tid
*tid
,
1957 struct sk_buff
*skb
)
1959 struct ath_common
*common
= ath9k_hw_common(sc
->sc_ah
);
1960 struct ath_frame_info
*fi
= get_frame_info(skb
);
1961 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*)skb
->data
;
1966 bf
= ath_tx_get_buffer(sc
);
1968 ath_dbg(common
, XMIT
, "TX buffers are full\n");
1972 ATH_TXBUF_RESET(bf
);
1975 fragno
= le16_to_cpu(hdr
->seq_ctrl
) & IEEE80211_SCTL_FRAG
;
1976 seqno
= tid
->seq_next
;
1977 hdr
->seq_ctrl
= cpu_to_le16(tid
->seq_next
<< IEEE80211_SEQ_SEQ_SHIFT
);
1980 hdr
->seq_ctrl
|= cpu_to_le16(fragno
);
1982 if (!ieee80211_has_morefrags(hdr
->frame_control
))
1983 INCR(tid
->seq_next
, IEEE80211_SEQ_MAX
);
1985 bf
->bf_state
.seqno
= seqno
;
1990 bf
->bf_buf_addr
= dma_map_single(sc
->dev
, skb
->data
,
1991 skb
->len
, DMA_TO_DEVICE
);
1992 if (unlikely(dma_mapping_error(sc
->dev
, bf
->bf_buf_addr
))) {
1994 bf
->bf_buf_addr
= 0;
1995 ath_err(ath9k_hw_common(sc
->sc_ah
),
1996 "dma_mapping_error() on TX\n");
1997 ath_tx_return_buffer(sc
, bf
);
2006 static int ath_tx_prepare(struct ieee80211_hw
*hw
, struct sk_buff
*skb
,
2007 struct ath_tx_control
*txctl
)
2009 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*) skb
->data
;
2010 struct ieee80211_tx_info
*info
= IEEE80211_SKB_CB(skb
);
2011 struct ieee80211_sta
*sta
= txctl
->sta
;
2012 struct ieee80211_vif
*vif
= info
->control
.vif
;
2013 struct ath_softc
*sc
= hw
->priv
;
2014 int frmlen
= skb
->len
+ FCS_LEN
;
2015 int padpos
, padsize
;
2017 /* NOTE: sta can be NULL according to net/mac80211.h */
2019 txctl
->an
= (struct ath_node
*)sta
->drv_priv
;
2021 if (info
->control
.hw_key
)
2022 frmlen
+= info
->control
.hw_key
->icv_len
;
2025 * As a temporary workaround, assign seq# here; this will likely need
2026 * to be cleaned up to work better with Beacon transmission and virtual
2029 if (info
->flags
& IEEE80211_TX_CTL_ASSIGN_SEQ
) {
2030 if (info
->flags
& IEEE80211_TX_CTL_FIRST_FRAGMENT
)
2031 sc
->tx
.seq_no
+= 0x10;
2032 hdr
->seq_ctrl
&= cpu_to_le16(IEEE80211_SCTL_FRAG
);
2033 hdr
->seq_ctrl
|= cpu_to_le16(sc
->tx
.seq_no
);
2036 if ((vif
&& vif
->type
!= NL80211_IFTYPE_AP
&&
2037 vif
->type
!= NL80211_IFTYPE_AP_VLAN
) ||
2038 !ieee80211_is_data(hdr
->frame_control
))
2039 info
->flags
|= IEEE80211_TX_CTL_CLEAR_PS_FILT
;
2041 /* Add the padding after the header if this is not already done */
2042 padpos
= ieee80211_hdrlen(hdr
->frame_control
);
2043 padsize
= padpos
& 3;
2044 if (padsize
&& skb
->len
> padpos
) {
2045 if (skb_headroom(skb
) < padsize
)
2048 skb_push(skb
, padsize
);
2049 memmove(skb
->data
, skb
->data
+ padsize
, padpos
);
2052 setup_frame_info(hw
, sta
, skb
, frmlen
);
2057 /* Upon failure caller should free skb */
2058 int ath_tx_start(struct ieee80211_hw
*hw
, struct sk_buff
*skb
,
2059 struct ath_tx_control
*txctl
)
2061 struct ieee80211_hdr
*hdr
;
2062 struct ieee80211_tx_info
*info
= IEEE80211_SKB_CB(skb
);
2063 struct ieee80211_sta
*sta
= txctl
->sta
;
2064 struct ieee80211_vif
*vif
= info
->control
.vif
;
2065 struct ath_softc
*sc
= hw
->priv
;
2066 struct ath_txq
*txq
= txctl
->txq
;
2067 struct ath_atx_tid
*tid
= NULL
;
2073 ret
= ath_tx_prepare(hw
, skb
, txctl
);
2077 hdr
= (struct ieee80211_hdr
*) skb
->data
;
2079 * At this point, the vif, hw_key and sta pointers in the tx control
2080 * info are no longer valid (overwritten by the ath_frame_info data.
2083 q
= skb_get_queue_mapping(skb
);
2085 ath_txq_lock(sc
, txq
);
2086 if (txq
== sc
->tx
.txq_map
[q
] &&
2087 ++txq
->pending_frames
> sc
->tx
.txq_max_pending
[q
] &&
2089 ieee80211_stop_queue(sc
->hw
, q
);
2090 txq
->stopped
= true;
2093 if (info
->flags
& IEEE80211_TX_CTL_PS_RESPONSE
) {
2094 ath_txq_unlock(sc
, txq
);
2095 txq
= sc
->tx
.uapsdq
;
2096 ath_txq_lock(sc
, txq
);
2099 if (txctl
->an
&& ieee80211_is_data_qos(hdr
->frame_control
)) {
2100 tidno
= ieee80211_get_qos_ctl(hdr
)[0] &
2101 IEEE80211_QOS_CTL_TID_MASK
;
2102 tid
= ATH_AN_2_TID(txctl
->an
, tidno
);
2104 WARN_ON(tid
->ac
->txq
!= txctl
->txq
);
2107 if ((info
->flags
& IEEE80211_TX_CTL_AMPDU
) && tid
) {
2109 * Try aggregation if it's a unicast data frame
2110 * and the destination is HT capable.
2112 ath_tx_send_ampdu(sc
, txq
, tid
, skb
, txctl
);
2116 bf
= ath_tx_setup_buffer(sc
, txq
, tid
, skb
);
2118 ath_txq_skb_done(sc
, txq
, skb
);
2120 dev_kfree_skb_any(skb
);
2122 ieee80211_free_txskb(sc
->hw
, skb
);
2126 bf
->bf_state
.bfs_paprd
= txctl
->paprd
;
2129 bf
->bf_state
.bfs_paprd_timestamp
= jiffies
;
2131 ath_set_rates(vif
, sta
, bf
);
2132 ath_tx_send_normal(sc
, txq
, tid
, skb
);
2135 ath_txq_unlock(sc
, txq
);
2140 void ath_tx_cabq(struct ieee80211_hw
*hw
, struct ieee80211_vif
*vif
,
2141 struct sk_buff
*skb
)
2143 struct ath_softc
*sc
= hw
->priv
;
2144 struct ath_tx_control txctl
= {
2145 .txq
= sc
->beacon
.cabq
2147 struct ath_tx_info info
= {};
2148 struct ieee80211_hdr
*hdr
;
2149 struct ath_buf
*bf_tail
= NULL
;
2156 sc
->cur_beacon_conf
.beacon_interval
* 1000 *
2157 sc
->cur_beacon_conf
.dtim_period
/ ATH_BCBUF
;
2160 struct ath_frame_info
*fi
= get_frame_info(skb
);
2162 if (ath_tx_prepare(hw
, skb
, &txctl
))
2165 bf
= ath_tx_setup_buffer(sc
, txctl
.txq
, NULL
, skb
);
2170 ath_set_rates(vif
, NULL
, bf
);
2171 ath_buf_set_rate(sc
, bf
, &info
, fi
->framelen
);
2172 duration
+= info
.rates
[0].PktDuration
;
2174 bf_tail
->bf_next
= bf
;
2176 list_add_tail(&bf
->list
, &bf_q
);
2180 if (duration
> max_duration
)
2183 skb
= ieee80211_get_buffered_bc(hw
, vif
);
2187 ieee80211_free_txskb(hw
, skb
);
2189 if (list_empty(&bf_q
))
2192 bf
= list_first_entry(&bf_q
, struct ath_buf
, list
);
2193 hdr
= (struct ieee80211_hdr
*) bf
->bf_mpdu
->data
;
2195 if (hdr
->frame_control
& IEEE80211_FCTL_MOREDATA
) {
2196 hdr
->frame_control
&= ~IEEE80211_FCTL_MOREDATA
;
2197 dma_sync_single_for_device(sc
->dev
, bf
->bf_buf_addr
,
2198 sizeof(*hdr
), DMA_TO_DEVICE
);
2201 ath_txq_lock(sc
, txctl
.txq
);
2202 ath_tx_fill_desc(sc
, bf
, txctl
.txq
, 0);
2203 ath_tx_txqaddbuf(sc
, txctl
.txq
, &bf_q
, false);
2204 TX_STAT_INC(txctl
.txq
->axq_qnum
, queued
);
2205 ath_txq_unlock(sc
, txctl
.txq
);
2212 static void ath_tx_complete(struct ath_softc
*sc
, struct sk_buff
*skb
,
2213 int tx_flags
, struct ath_txq
*txq
)
2215 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
2216 struct ath_common
*common
= ath9k_hw_common(sc
->sc_ah
);
2217 struct ieee80211_hdr
* hdr
= (struct ieee80211_hdr
*)skb
->data
;
2218 int padpos
, padsize
;
2219 unsigned long flags
;
2221 ath_dbg(common
, XMIT
, "TX complete: skb: %p\n", skb
);
2223 if (sc
->sc_ah
->caldata
)
2224 sc
->sc_ah
->caldata
->paprd_packet_sent
= true;
2226 if (!(tx_flags
& ATH_TX_ERROR
))
2227 /* Frame was ACKed */
2228 tx_info
->flags
|= IEEE80211_TX_STAT_ACK
;
2230 padpos
= ieee80211_hdrlen(hdr
->frame_control
);
2231 padsize
= padpos
& 3;
2232 if (padsize
&& skb
->len
>padpos
+padsize
) {
2234 * Remove MAC header padding before giving the frame back to
2237 memmove(skb
->data
+ padsize
, skb
->data
, padpos
);
2238 skb_pull(skb
, padsize
);
2241 spin_lock_irqsave(&sc
->sc_pm_lock
, flags
);
2242 if ((sc
->ps_flags
& PS_WAIT_FOR_TX_ACK
) && !txq
->axq_depth
) {
2243 sc
->ps_flags
&= ~PS_WAIT_FOR_TX_ACK
;
2245 "Going back to sleep after having received TX status (0x%lx)\n",
2246 sc
->ps_flags
& (PS_WAIT_FOR_BEACON
|
2248 PS_WAIT_FOR_PSPOLL_DATA
|
2249 PS_WAIT_FOR_TX_ACK
));
2251 spin_unlock_irqrestore(&sc
->sc_pm_lock
, flags
);
2253 __skb_queue_tail(&txq
->complete_q
, skb
);
2254 ath_txq_skb_done(sc
, txq
, skb
);
2257 static void ath_tx_complete_buf(struct ath_softc
*sc
, struct ath_buf
*bf
,
2258 struct ath_txq
*txq
, struct list_head
*bf_q
,
2259 struct ath_tx_status
*ts
, int txok
)
2261 struct sk_buff
*skb
= bf
->bf_mpdu
;
2262 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
2263 unsigned long flags
;
2267 tx_flags
|= ATH_TX_ERROR
;
2269 if (ts
->ts_status
& ATH9K_TXERR_FILT
)
2270 tx_info
->flags
|= IEEE80211_TX_STAT_TX_FILTERED
;
2272 dma_unmap_single(sc
->dev
, bf
->bf_buf_addr
, skb
->len
, DMA_TO_DEVICE
);
2273 bf
->bf_buf_addr
= 0;
2275 if (bf
->bf_state
.bfs_paprd
) {
2276 if (time_after(jiffies
,
2277 bf
->bf_state
.bfs_paprd_timestamp
+
2278 msecs_to_jiffies(ATH_PAPRD_TIMEOUT
)))
2279 dev_kfree_skb_any(skb
);
2281 complete(&sc
->paprd_complete
);
2283 ath_debug_stat_tx(sc
, bf
, ts
, txq
, tx_flags
);
2284 ath_tx_complete(sc
, skb
, tx_flags
, txq
);
2286 /* At this point, skb (bf->bf_mpdu) is consumed...make sure we don't
2287 * accidentally reference it later.
2292 * Return the list of ath_buf of this mpdu to free queue
2294 spin_lock_irqsave(&sc
->tx
.txbuflock
, flags
);
2295 list_splice_tail_init(bf_q
, &sc
->tx
.txbuf
);
2296 spin_unlock_irqrestore(&sc
->tx
.txbuflock
, flags
);
2299 static void ath_tx_rc_status(struct ath_softc
*sc
, struct ath_buf
*bf
,
2300 struct ath_tx_status
*ts
, int nframes
, int nbad
,
2303 struct sk_buff
*skb
= bf
->bf_mpdu
;
2304 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*)skb
->data
;
2305 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
2306 struct ieee80211_hw
*hw
= sc
->hw
;
2307 struct ath_hw
*ah
= sc
->sc_ah
;
2311 tx_info
->status
.ack_signal
= ts
->ts_rssi
;
2313 tx_rateindex
= ts
->ts_rateindex
;
2314 WARN_ON(tx_rateindex
>= hw
->max_rates
);
2316 if (tx_info
->flags
& IEEE80211_TX_CTL_AMPDU
) {
2317 tx_info
->flags
|= IEEE80211_TX_STAT_AMPDU
;
2319 BUG_ON(nbad
> nframes
);
2321 tx_info
->status
.ampdu_len
= nframes
;
2322 tx_info
->status
.ampdu_ack_len
= nframes
- nbad
;
2324 if ((ts
->ts_status
& ATH9K_TXERR_FILT
) == 0 &&
2325 (tx_info
->flags
& IEEE80211_TX_CTL_NO_ACK
) == 0) {
2327 * If an underrun error is seen assume it as an excessive
2328 * retry only if max frame trigger level has been reached
2329 * (2 KB for single stream, and 4 KB for dual stream).
2330 * Adjust the long retry as if the frame was tried
2331 * hw->max_rate_tries times to affect how rate control updates
2332 * PER for the failed rate.
2333 * In case of congestion on the bus penalizing this type of
2334 * underruns should help hardware actually transmit new frames
2335 * successfully by eventually preferring slower rates.
2336 * This itself should also alleviate congestion on the bus.
2338 if (unlikely(ts
->ts_flags
& (ATH9K_TX_DATA_UNDERRUN
|
2339 ATH9K_TX_DELIM_UNDERRUN
)) &&
2340 ieee80211_is_data(hdr
->frame_control
) &&
2341 ah
->tx_trig_level
>= sc
->sc_ah
->config
.max_txtrig_level
)
2342 tx_info
->status
.rates
[tx_rateindex
].count
=
2346 for (i
= tx_rateindex
+ 1; i
< hw
->max_rates
; i
++) {
2347 tx_info
->status
.rates
[i
].count
= 0;
2348 tx_info
->status
.rates
[i
].idx
= -1;
2351 tx_info
->status
.rates
[tx_rateindex
].count
= ts
->ts_longretry
+ 1;
2354 static void ath_tx_processq(struct ath_softc
*sc
, struct ath_txq
*txq
)
2356 struct ath_hw
*ah
= sc
->sc_ah
;
2357 struct ath_common
*common
= ath9k_hw_common(ah
);
2358 struct ath_buf
*bf
, *lastbf
, *bf_held
= NULL
;
2359 struct list_head bf_head
;
2360 struct ath_desc
*ds
;
2361 struct ath_tx_status ts
;
2364 ath_dbg(common
, QUEUE
, "tx queue %d (%x), link %p\n",
2365 txq
->axq_qnum
, ath9k_hw_gettxbuf(sc
->sc_ah
, txq
->axq_qnum
),
2368 ath_txq_lock(sc
, txq
);
2370 if (test_bit(SC_OP_HW_RESET
, &sc
->sc_flags
))
2373 if (list_empty(&txq
->axq_q
)) {
2374 txq
->axq_link
= NULL
;
2375 if (sc
->sc_ah
->caps
.hw_caps
& ATH9K_HW_CAP_HT
)
2376 ath_txq_schedule(sc
, txq
);
2379 bf
= list_first_entry(&txq
->axq_q
, struct ath_buf
, list
);
2382 * There is a race condition that a BH gets scheduled
2383 * after sw writes TxE and before hw re-load the last
2384 * descriptor to get the newly chained one.
2385 * Software must keep the last DONE descriptor as a
2386 * holding descriptor - software does so by marking
2387 * it with the STALE flag.
2392 if (list_is_last(&bf_held
->list
, &txq
->axq_q
))
2395 bf
= list_entry(bf_held
->list
.next
, struct ath_buf
,
2399 lastbf
= bf
->bf_lastbf
;
2400 ds
= lastbf
->bf_desc
;
2402 memset(&ts
, 0, sizeof(ts
));
2403 status
= ath9k_hw_txprocdesc(ah
, ds
, &ts
);
2404 if (status
== -EINPROGRESS
)
2407 TX_STAT_INC(txq
->axq_qnum
, txprocdesc
);
2410 * Remove ath_buf's of the same transmit unit from txq,
2411 * however leave the last descriptor back as the holding
2412 * descriptor for hw.
2414 lastbf
->bf_stale
= true;
2415 INIT_LIST_HEAD(&bf_head
);
2416 if (!list_is_singular(&lastbf
->list
))
2417 list_cut_position(&bf_head
,
2418 &txq
->axq_q
, lastbf
->list
.prev
);
2421 list_del(&bf_held
->list
);
2422 ath_tx_return_buffer(sc
, bf_held
);
2425 ath_tx_process_buffer(sc
, txq
, &ts
, bf
, &bf_head
);
2427 ath_txq_unlock_complete(sc
, txq
);
2430 void ath_tx_tasklet(struct ath_softc
*sc
)
2432 struct ath_hw
*ah
= sc
->sc_ah
;
2433 u32 qcumask
= ((1 << ATH9K_NUM_TX_QUEUES
) - 1) & ah
->intr_txqs
;
2436 for (i
= 0; i
< ATH9K_NUM_TX_QUEUES
; i
++) {
2437 if (ATH_TXQ_SETUP(sc
, i
) && (qcumask
& (1 << i
)))
2438 ath_tx_processq(sc
, &sc
->tx
.txq
[i
]);
2442 void ath_tx_edma_tasklet(struct ath_softc
*sc
)
2444 struct ath_tx_status ts
;
2445 struct ath_common
*common
= ath9k_hw_common(sc
->sc_ah
);
2446 struct ath_hw
*ah
= sc
->sc_ah
;
2447 struct ath_txq
*txq
;
2448 struct ath_buf
*bf
, *lastbf
;
2449 struct list_head bf_head
;
2450 struct list_head
*fifo_list
;
2454 if (test_bit(SC_OP_HW_RESET
, &sc
->sc_flags
))
2457 status
= ath9k_hw_txprocdesc(ah
, NULL
, (void *)&ts
);
2458 if (status
== -EINPROGRESS
)
2460 if (status
== -EIO
) {
2461 ath_dbg(common
, XMIT
, "Error processing tx status\n");
2465 /* Process beacon completions separately */
2466 if (ts
.qid
== sc
->beacon
.beaconq
) {
2467 sc
->beacon
.tx_processed
= true;
2468 sc
->beacon
.tx_last
= !(ts
.ts_status
& ATH9K_TXERR_MASK
);
2472 txq
= &sc
->tx
.txq
[ts
.qid
];
2474 ath_txq_lock(sc
, txq
);
2476 TX_STAT_INC(txq
->axq_qnum
, txprocdesc
);
2478 fifo_list
= &txq
->txq_fifo
[txq
->txq_tailidx
];
2479 if (list_empty(fifo_list
)) {
2480 ath_txq_unlock(sc
, txq
);
2484 bf
= list_first_entry(fifo_list
, struct ath_buf
, list
);
2486 list_del(&bf
->list
);
2487 ath_tx_return_buffer(sc
, bf
);
2488 bf
= list_first_entry(fifo_list
, struct ath_buf
, list
);
2491 lastbf
= bf
->bf_lastbf
;
2493 INIT_LIST_HEAD(&bf_head
);
2494 if (list_is_last(&lastbf
->list
, fifo_list
)) {
2495 list_splice_tail_init(fifo_list
, &bf_head
);
2496 INCR(txq
->txq_tailidx
, ATH_TXFIFO_DEPTH
);
2498 if (!list_empty(&txq
->axq_q
)) {
2499 struct list_head bf_q
;
2501 INIT_LIST_HEAD(&bf_q
);
2502 txq
->axq_link
= NULL
;
2503 list_splice_tail_init(&txq
->axq_q
, &bf_q
);
2504 ath_tx_txqaddbuf(sc
, txq
, &bf_q
, true);
2507 lastbf
->bf_stale
= true;
2509 list_cut_position(&bf_head
, fifo_list
,
2513 ath_tx_process_buffer(sc
, txq
, &ts
, bf
, &bf_head
);
2514 ath_txq_unlock_complete(sc
, txq
);
2522 static int ath_txstatus_setup(struct ath_softc
*sc
, int size
)
2524 struct ath_descdma
*dd
= &sc
->txsdma
;
2525 u8 txs_len
= sc
->sc_ah
->caps
.txs_len
;
2527 dd
->dd_desc_len
= size
* txs_len
;
2528 dd
->dd_desc
= dmam_alloc_coherent(sc
->dev
, dd
->dd_desc_len
,
2529 &dd
->dd_desc_paddr
, GFP_KERNEL
);
2536 static int ath_tx_edma_init(struct ath_softc
*sc
)
2540 err
= ath_txstatus_setup(sc
, ATH_TXSTATUS_RING_SIZE
);
2542 ath9k_hw_setup_statusring(sc
->sc_ah
, sc
->txsdma
.dd_desc
,
2543 sc
->txsdma
.dd_desc_paddr
,
2544 ATH_TXSTATUS_RING_SIZE
);
2549 int ath_tx_init(struct ath_softc
*sc
, int nbufs
)
2551 struct ath_common
*common
= ath9k_hw_common(sc
->sc_ah
);
2554 spin_lock_init(&sc
->tx
.txbuflock
);
2556 error
= ath_descdma_setup(sc
, &sc
->tx
.txdma
, &sc
->tx
.txbuf
,
2560 "Failed to allocate tx descriptors: %d\n", error
);
2564 error
= ath_descdma_setup(sc
, &sc
->beacon
.bdma
, &sc
->beacon
.bbuf
,
2565 "beacon", ATH_BCBUF
, 1, 1);
2568 "Failed to allocate beacon descriptors: %d\n", error
);
2572 INIT_DELAYED_WORK(&sc
->tx_complete_work
, ath_tx_complete_poll_work
);
2574 if (sc
->sc_ah
->caps
.hw_caps
& ATH9K_HW_CAP_EDMA
)
2575 error
= ath_tx_edma_init(sc
);
2580 void ath_tx_node_init(struct ath_softc
*sc
, struct ath_node
*an
)
2582 struct ath_atx_tid
*tid
;
2583 struct ath_atx_ac
*ac
;
2586 for (tidno
= 0, tid
= &an
->tid
[tidno
];
2587 tidno
< IEEE80211_NUM_TIDS
;
2591 tid
->seq_start
= tid
->seq_next
= 0;
2592 tid
->baw_size
= WME_MAX_BA
;
2593 tid
->baw_head
= tid
->baw_tail
= 0;
2595 tid
->paused
= false;
2596 tid
->active
= false;
2597 __skb_queue_head_init(&tid
->buf_q
);
2598 acno
= TID_TO_WME_AC(tidno
);
2599 tid
->ac
= &an
->ac
[acno
];
2602 for (acno
= 0, ac
= &an
->ac
[acno
];
2603 acno
< IEEE80211_NUM_ACS
; acno
++, ac
++) {
2605 ac
->txq
= sc
->tx
.txq_map
[acno
];
2606 INIT_LIST_HEAD(&ac
->tid_q
);
2610 void ath_tx_node_cleanup(struct ath_softc
*sc
, struct ath_node
*an
)
2612 struct ath_atx_ac
*ac
;
2613 struct ath_atx_tid
*tid
;
2614 struct ath_txq
*txq
;
2617 for (tidno
= 0, tid
= &an
->tid
[tidno
];
2618 tidno
< IEEE80211_NUM_TIDS
; tidno
++, tid
++) {
2623 ath_txq_lock(sc
, txq
);
2626 list_del(&tid
->list
);
2631 list_del(&ac
->list
);
2632 tid
->ac
->sched
= false;
2635 ath_tid_drain(sc
, txq
, tid
);
2636 tid
->active
= false;
2638 ath_txq_unlock(sc
, txq
);