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ath9k: Add more information to debugfs xmit file.
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / xmit.c
1 /*
2 * Copyright (c) 2008-2009 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include "ath9k.h"
18 #include "ar9003_mac.h"
19
20 #define BITS_PER_BYTE 8
21 #define OFDM_PLCP_BITS 22
22 #define HT_RC_2_MCS(_rc) ((_rc) & 0x1f)
23 #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
24 #define L_STF 8
25 #define L_LTF 8
26 #define L_SIG 4
27 #define HT_SIG 8
28 #define HT_STF 4
29 #define HT_LTF(_ns) (4 * (_ns))
30 #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */
31 #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */
32 #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
33 #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
34
35 #define OFDM_SIFS_TIME 16
36
37 static u16 bits_per_symbol[][2] = {
38 /* 20MHz 40MHz */
39 { 26, 54 }, /* 0: BPSK */
40 { 52, 108 }, /* 1: QPSK 1/2 */
41 { 78, 162 }, /* 2: QPSK 3/4 */
42 { 104, 216 }, /* 3: 16-QAM 1/2 */
43 { 156, 324 }, /* 4: 16-QAM 3/4 */
44 { 208, 432 }, /* 5: 64-QAM 2/3 */
45 { 234, 486 }, /* 6: 64-QAM 3/4 */
46 { 260, 540 }, /* 7: 64-QAM 5/6 */
47 };
48
49 #define IS_HT_RATE(_rate) ((_rate) & 0x80)
50
51 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
52 struct ath_atx_tid *tid,
53 struct list_head *bf_head);
54 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
55 struct ath_txq *txq, struct list_head *bf_q,
56 struct ath_tx_status *ts, int txok, int sendbar);
57 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
58 struct list_head *head);
59 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf, int len);
60 static void ath_tx_rc_status(struct ath_buf *bf, struct ath_tx_status *ts,
61 int nframes, int nbad, int txok, bool update_rc);
62 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
63 int seqno);
64
65 enum {
66 MCS_HT20,
67 MCS_HT20_SGI,
68 MCS_HT40,
69 MCS_HT40_SGI,
70 };
71
72 static int ath_max_4ms_framelen[4][32] = {
73 [MCS_HT20] = {
74 3212, 6432, 9648, 12864, 19300, 25736, 28952, 32172,
75 6424, 12852, 19280, 25708, 38568, 51424, 57852, 64280,
76 9628, 19260, 28896, 38528, 57792, 65532, 65532, 65532,
77 12828, 25656, 38488, 51320, 65532, 65532, 65532, 65532,
78 },
79 [MCS_HT20_SGI] = {
80 3572, 7144, 10720, 14296, 21444, 28596, 32172, 35744,
81 7140, 14284, 21428, 28568, 42856, 57144, 64288, 65532,
82 10700, 21408, 32112, 42816, 64228, 65532, 65532, 65532,
83 14256, 28516, 42780, 57040, 65532, 65532, 65532, 65532,
84 },
85 [MCS_HT40] = {
86 6680, 13360, 20044, 26724, 40092, 53456, 60140, 65532,
87 13348, 26700, 40052, 53400, 65532, 65532, 65532, 65532,
88 20004, 40008, 60016, 65532, 65532, 65532, 65532, 65532,
89 26644, 53292, 65532, 65532, 65532, 65532, 65532, 65532,
90 },
91 [MCS_HT40_SGI] = {
92 7420, 14844, 22272, 29696, 44544, 59396, 65532, 65532,
93 14832, 29668, 44504, 59340, 65532, 65532, 65532, 65532,
94 22232, 44464, 65532, 65532, 65532, 65532, 65532, 65532,
95 29616, 59232, 65532, 65532, 65532, 65532, 65532, 65532,
96 }
97 };
98
99 /*********************/
100 /* Aggregation logic */
101 /*********************/
102
103 static void ath_tx_queue_tid(struct ath_txq *txq, struct ath_atx_tid *tid)
104 {
105 struct ath_atx_ac *ac = tid->ac;
106
107 if (tid->paused)
108 return;
109
110 if (tid->sched)
111 return;
112
113 tid->sched = true;
114 list_add_tail(&tid->list, &ac->tid_q);
115
116 if (ac->sched)
117 return;
118
119 ac->sched = true;
120 list_add_tail(&ac->list, &txq->axq_acq);
121 }
122
123 static void ath_tx_resume_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
124 {
125 struct ath_txq *txq = tid->ac->txq;
126
127 WARN_ON(!tid->paused);
128
129 spin_lock_bh(&txq->axq_lock);
130 tid->paused = false;
131
132 if (list_empty(&tid->buf_q))
133 goto unlock;
134
135 ath_tx_queue_tid(txq, tid);
136 ath_txq_schedule(sc, txq);
137 unlock:
138 spin_unlock_bh(&txq->axq_lock);
139 }
140
141 static struct ath_frame_info *get_frame_info(struct sk_buff *skb)
142 {
143 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
144 BUILD_BUG_ON(sizeof(struct ath_frame_info) >
145 sizeof(tx_info->rate_driver_data));
146 return (struct ath_frame_info *) &tx_info->rate_driver_data[0];
147 }
148
149 static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
150 {
151 struct ath_txq *txq = tid->ac->txq;
152 struct ath_buf *bf;
153 struct list_head bf_head;
154 struct ath_tx_status ts;
155 struct ath_frame_info *fi;
156
157 INIT_LIST_HEAD(&bf_head);
158
159 memset(&ts, 0, sizeof(ts));
160 spin_lock_bh(&txq->axq_lock);
161
162 while (!list_empty(&tid->buf_q)) {
163 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
164 list_move_tail(&bf->list, &bf_head);
165
166 spin_unlock_bh(&txq->axq_lock);
167 fi = get_frame_info(bf->bf_mpdu);
168 if (fi->retries) {
169 ath_tx_update_baw(sc, tid, fi->seqno);
170 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 0);
171 } else {
172 ath_tx_send_normal(sc, txq, NULL, &bf_head);
173 }
174 spin_lock_bh(&txq->axq_lock);
175 }
176
177 spin_unlock_bh(&txq->axq_lock);
178 }
179
180 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
181 int seqno)
182 {
183 int index, cindex;
184
185 index = ATH_BA_INDEX(tid->seq_start, seqno);
186 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
187
188 __clear_bit(cindex, tid->tx_buf);
189
190 while (tid->baw_head != tid->baw_tail && !test_bit(tid->baw_head, tid->tx_buf)) {
191 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
192 INCR(tid->baw_head, ATH_TID_MAX_BUFS);
193 }
194 }
195
196 static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
197 u16 seqno)
198 {
199 int index, cindex;
200
201 index = ATH_BA_INDEX(tid->seq_start, seqno);
202 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
203 __set_bit(cindex, tid->tx_buf);
204
205 if (index >= ((tid->baw_tail - tid->baw_head) &
206 (ATH_TID_MAX_BUFS - 1))) {
207 tid->baw_tail = cindex;
208 INCR(tid->baw_tail, ATH_TID_MAX_BUFS);
209 }
210 }
211
212 /*
213 * TODO: For frame(s) that are in the retry state, we will reuse the
214 * sequence number(s) without setting the retry bit. The
215 * alternative is to give up on these and BAR the receiver's window
216 * forward.
217 */
218 static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq,
219 struct ath_atx_tid *tid)
220
221 {
222 struct ath_buf *bf;
223 struct list_head bf_head;
224 struct ath_tx_status ts;
225 struct ath_frame_info *fi;
226
227 memset(&ts, 0, sizeof(ts));
228 INIT_LIST_HEAD(&bf_head);
229
230 for (;;) {
231 if (list_empty(&tid->buf_q))
232 break;
233
234 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
235 list_move_tail(&bf->list, &bf_head);
236
237 fi = get_frame_info(bf->bf_mpdu);
238 if (fi->retries)
239 ath_tx_update_baw(sc, tid, fi->seqno);
240
241 spin_unlock(&txq->axq_lock);
242 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 0);
243 spin_lock(&txq->axq_lock);
244 }
245
246 tid->seq_next = tid->seq_start;
247 tid->baw_tail = tid->baw_head;
248 }
249
250 static void ath_tx_set_retry(struct ath_softc *sc, struct ath_txq *txq,
251 struct sk_buff *skb)
252 {
253 struct ath_frame_info *fi = get_frame_info(skb);
254 struct ieee80211_hdr *hdr;
255
256 TX_STAT_INC(txq->axq_qnum, a_retries);
257 if (fi->retries++ > 0)
258 return;
259
260 hdr = (struct ieee80211_hdr *)skb->data;
261 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY);
262 }
263
264 static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc)
265 {
266 struct ath_buf *bf = NULL;
267
268 spin_lock_bh(&sc->tx.txbuflock);
269
270 if (unlikely(list_empty(&sc->tx.txbuf))) {
271 spin_unlock_bh(&sc->tx.txbuflock);
272 return NULL;
273 }
274
275 bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list);
276 list_del(&bf->list);
277
278 spin_unlock_bh(&sc->tx.txbuflock);
279
280 return bf;
281 }
282
283 static void ath_tx_return_buffer(struct ath_softc *sc, struct ath_buf *bf)
284 {
285 spin_lock_bh(&sc->tx.txbuflock);
286 list_add_tail(&bf->list, &sc->tx.txbuf);
287 spin_unlock_bh(&sc->tx.txbuflock);
288 }
289
290 static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf)
291 {
292 struct ath_buf *tbf;
293
294 tbf = ath_tx_get_buffer(sc);
295 if (WARN_ON(!tbf))
296 return NULL;
297
298 ATH_TXBUF_RESET(tbf);
299
300 tbf->aphy = bf->aphy;
301 tbf->bf_mpdu = bf->bf_mpdu;
302 tbf->bf_buf_addr = bf->bf_buf_addr;
303 memcpy(tbf->bf_desc, bf->bf_desc, sc->sc_ah->caps.tx_desc_len);
304 tbf->bf_state = bf->bf_state;
305
306 return tbf;
307 }
308
309 static void ath_tx_count_frames(struct ath_softc *sc, struct ath_buf *bf,
310 struct ath_tx_status *ts, int txok,
311 int *nframes, int *nbad)
312 {
313 struct ath_frame_info *fi;
314 u16 seq_st = 0;
315 u32 ba[WME_BA_BMP_SIZE >> 5];
316 int ba_index;
317 int isaggr = 0;
318
319 *nbad = 0;
320 *nframes = 0;
321
322 isaggr = bf_isaggr(bf);
323 if (isaggr) {
324 seq_st = ts->ts_seqnum;
325 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
326 }
327
328 while (bf) {
329 fi = get_frame_info(bf->bf_mpdu);
330 ba_index = ATH_BA_INDEX(seq_st, fi->seqno);
331
332 (*nframes)++;
333 if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index)))
334 (*nbad)++;
335
336 bf = bf->bf_next;
337 }
338 }
339
340
341 static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
342 struct ath_buf *bf, struct list_head *bf_q,
343 struct ath_tx_status *ts, int txok, bool retry)
344 {
345 struct ath_node *an = NULL;
346 struct sk_buff *skb;
347 struct ieee80211_sta *sta;
348 struct ieee80211_hw *hw;
349 struct ieee80211_hdr *hdr;
350 struct ieee80211_tx_info *tx_info;
351 struct ath_atx_tid *tid = NULL;
352 struct ath_buf *bf_next, *bf_last = bf->bf_lastbf;
353 struct list_head bf_head, bf_pending;
354 u16 seq_st = 0, acked_cnt = 0, txfail_cnt = 0;
355 u32 ba[WME_BA_BMP_SIZE >> 5];
356 int isaggr, txfail, txpending, sendbar = 0, needreset = 0, nbad = 0;
357 bool rc_update = true;
358 struct ieee80211_tx_rate rates[4];
359 struct ath_frame_info *fi;
360 int nframes;
361 u8 tidno;
362
363 skb = bf->bf_mpdu;
364 hdr = (struct ieee80211_hdr *)skb->data;
365
366 tx_info = IEEE80211_SKB_CB(skb);
367 hw = bf->aphy->hw;
368
369 memcpy(rates, tx_info->control.rates, sizeof(rates));
370
371 rcu_read_lock();
372
373 sta = ieee80211_find_sta_by_ifaddr(hw, hdr->addr1, hdr->addr2);
374 if (!sta) {
375 rcu_read_unlock();
376
377 INIT_LIST_HEAD(&bf_head);
378 while (bf) {
379 bf_next = bf->bf_next;
380
381 bf->bf_state.bf_type |= BUF_XRETRY;
382 if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) ||
383 !bf->bf_stale || bf_next != NULL)
384 list_move_tail(&bf->list, &bf_head);
385
386 ath_tx_rc_status(bf, ts, 1, 1, 0, false);
387 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts,
388 0, 0);
389
390 bf = bf_next;
391 }
392 return;
393 }
394
395 an = (struct ath_node *)sta->drv_priv;
396 tidno = ieee80211_get_qos_ctl(hdr)[0] & IEEE80211_QOS_CTL_TID_MASK;
397 tid = ATH_AN_2_TID(an, tidno);
398
399 /*
400 * The hardware occasionally sends a tx status for the wrong TID.
401 * In this case, the BA status cannot be considered valid and all
402 * subframes need to be retransmitted
403 */
404 if (tidno != ts->tid)
405 txok = false;
406
407 isaggr = bf_isaggr(bf);
408 memset(ba, 0, WME_BA_BMP_SIZE >> 3);
409
410 if (isaggr && txok) {
411 if (ts->ts_flags & ATH9K_TX_BA) {
412 seq_st = ts->ts_seqnum;
413 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
414 } else {
415 /*
416 * AR5416 can become deaf/mute when BA
417 * issue happens. Chip needs to be reset.
418 * But AP code may have sychronization issues
419 * when perform internal reset in this routine.
420 * Only enable reset in STA mode for now.
421 */
422 if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION)
423 needreset = 1;
424 }
425 }
426
427 INIT_LIST_HEAD(&bf_pending);
428 INIT_LIST_HEAD(&bf_head);
429
430 ath_tx_count_frames(sc, bf, ts, txok, &nframes, &nbad);
431 while (bf) {
432 txfail = txpending = sendbar = 0;
433 bf_next = bf->bf_next;
434
435 skb = bf->bf_mpdu;
436 tx_info = IEEE80211_SKB_CB(skb);
437 fi = get_frame_info(skb);
438
439 if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, fi->seqno))) {
440 /* transmit completion, subframe is
441 * acked by block ack */
442 acked_cnt++;
443 } else if (!isaggr && txok) {
444 /* transmit completion */
445 acked_cnt++;
446 } else {
447 if (!(tid->state & AGGR_CLEANUP) && retry) {
448 if (fi->retries < ATH_MAX_SW_RETRIES) {
449 ath_tx_set_retry(sc, txq, bf->bf_mpdu);
450 txpending = 1;
451 } else {
452 bf->bf_state.bf_type |= BUF_XRETRY;
453 txfail = 1;
454 sendbar = 1;
455 txfail_cnt++;
456 }
457 } else {
458 /*
459 * cleanup in progress, just fail
460 * the un-acked sub-frames
461 */
462 txfail = 1;
463 }
464 }
465
466 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
467 bf_next == NULL) {
468 /*
469 * Make sure the last desc is reclaimed if it
470 * not a holding desc.
471 */
472 if (!bf_last->bf_stale)
473 list_move_tail(&bf->list, &bf_head);
474 else
475 INIT_LIST_HEAD(&bf_head);
476 } else {
477 BUG_ON(list_empty(bf_q));
478 list_move_tail(&bf->list, &bf_head);
479 }
480
481 if (!txpending || (tid->state & AGGR_CLEANUP)) {
482 /*
483 * complete the acked-ones/xretried ones; update
484 * block-ack window
485 */
486 spin_lock_bh(&txq->axq_lock);
487 ath_tx_update_baw(sc, tid, fi->seqno);
488 spin_unlock_bh(&txq->axq_lock);
489
490 if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) {
491 memcpy(tx_info->control.rates, rates, sizeof(rates));
492 ath_tx_rc_status(bf, ts, nframes, nbad, txok, true);
493 rc_update = false;
494 } else {
495 ath_tx_rc_status(bf, ts, nframes, nbad, txok, false);
496 }
497
498 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts,
499 !txfail, sendbar);
500 } else {
501 /* retry the un-acked ones */
502 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)) {
503 if (bf->bf_next == NULL && bf_last->bf_stale) {
504 struct ath_buf *tbf;
505
506 tbf = ath_clone_txbuf(sc, bf_last);
507 /*
508 * Update tx baw and complete the
509 * frame with failed status if we
510 * run out of tx buf.
511 */
512 if (!tbf) {
513 spin_lock_bh(&txq->axq_lock);
514 ath_tx_update_baw(sc, tid, fi->seqno);
515 spin_unlock_bh(&txq->axq_lock);
516
517 bf->bf_state.bf_type |=
518 BUF_XRETRY;
519 ath_tx_rc_status(bf, ts, nframes,
520 nbad, 0, false);
521 ath_tx_complete_buf(sc, bf, txq,
522 &bf_head,
523 ts, 0, 0);
524 break;
525 }
526
527 ath9k_hw_cleartxdesc(sc->sc_ah,
528 tbf->bf_desc);
529 list_add_tail(&tbf->list, &bf_head);
530 } else {
531 /*
532 * Clear descriptor status words for
533 * software retry
534 */
535 ath9k_hw_cleartxdesc(sc->sc_ah,
536 bf->bf_desc);
537 }
538 }
539
540 /*
541 * Put this buffer to the temporary pending
542 * queue to retain ordering
543 */
544 list_splice_tail_init(&bf_head, &bf_pending);
545 }
546
547 bf = bf_next;
548 }
549
550 /* prepend un-acked frames to the beginning of the pending frame queue */
551 if (!list_empty(&bf_pending)) {
552 spin_lock_bh(&txq->axq_lock);
553 list_splice(&bf_pending, &tid->buf_q);
554 ath_tx_queue_tid(txq, tid);
555 spin_unlock_bh(&txq->axq_lock);
556 }
557
558 if (tid->state & AGGR_CLEANUP) {
559 ath_tx_flush_tid(sc, tid);
560
561 if (tid->baw_head == tid->baw_tail) {
562 tid->state &= ~AGGR_ADDBA_COMPLETE;
563 tid->state &= ~AGGR_CLEANUP;
564 }
565 }
566
567 rcu_read_unlock();
568
569 if (needreset)
570 ath_reset(sc, false);
571 }
572
573 static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf,
574 struct ath_atx_tid *tid)
575 {
576 struct sk_buff *skb;
577 struct ieee80211_tx_info *tx_info;
578 struct ieee80211_tx_rate *rates;
579 u32 max_4ms_framelen, frmlen;
580 u16 aggr_limit, legacy = 0;
581 int i;
582
583 skb = bf->bf_mpdu;
584 tx_info = IEEE80211_SKB_CB(skb);
585 rates = tx_info->control.rates;
586
587 /*
588 * Find the lowest frame length among the rate series that will have a
589 * 4ms transmit duration.
590 * TODO - TXOP limit needs to be considered.
591 */
592 max_4ms_framelen = ATH_AMPDU_LIMIT_MAX;
593
594 for (i = 0; i < 4; i++) {
595 if (rates[i].count) {
596 int modeidx;
597 if (!(rates[i].flags & IEEE80211_TX_RC_MCS)) {
598 legacy = 1;
599 break;
600 }
601
602 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
603 modeidx = MCS_HT40;
604 else
605 modeidx = MCS_HT20;
606
607 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
608 modeidx++;
609
610 frmlen = ath_max_4ms_framelen[modeidx][rates[i].idx];
611 max_4ms_framelen = min(max_4ms_framelen, frmlen);
612 }
613 }
614
615 /*
616 * limit aggregate size by the minimum rate if rate selected is
617 * not a probe rate, if rate selected is a probe rate then
618 * avoid aggregation of this packet.
619 */
620 if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy)
621 return 0;
622
623 if (sc->sc_flags & SC_OP_BT_PRIORITY_DETECTED)
624 aggr_limit = min((max_4ms_framelen * 3) / 8,
625 (u32)ATH_AMPDU_LIMIT_MAX);
626 else
627 aggr_limit = min(max_4ms_framelen,
628 (u32)ATH_AMPDU_LIMIT_MAX);
629
630 /*
631 * h/w can accept aggregates upto 16 bit lengths (65535).
632 * The IE, however can hold upto 65536, which shows up here
633 * as zero. Ignore 65536 since we are constrained by hw.
634 */
635 if (tid->an->maxampdu)
636 aggr_limit = min(aggr_limit, tid->an->maxampdu);
637
638 return aggr_limit;
639 }
640
641 /*
642 * Returns the number of delimiters to be added to
643 * meet the minimum required mpdudensity.
644 */
645 static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid,
646 struct ath_buf *bf, u16 frmlen)
647 {
648 struct sk_buff *skb = bf->bf_mpdu;
649 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
650 u32 nsymbits, nsymbols;
651 u16 minlen;
652 u8 flags, rix;
653 int width, streams, half_gi, ndelim, mindelim;
654 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
655
656 /* Select standard number of delimiters based on frame length alone */
657 ndelim = ATH_AGGR_GET_NDELIM(frmlen);
658
659 /*
660 * If encryption enabled, hardware requires some more padding between
661 * subframes.
662 * TODO - this could be improved to be dependent on the rate.
663 * The hardware can keep up at lower rates, but not higher rates
664 */
665 if (fi->keyix != ATH9K_TXKEYIX_INVALID)
666 ndelim += ATH_AGGR_ENCRYPTDELIM;
667
668 /*
669 * Convert desired mpdu density from microeconds to bytes based
670 * on highest rate in rate series (i.e. first rate) to determine
671 * required minimum length for subframe. Take into account
672 * whether high rate is 20 or 40Mhz and half or full GI.
673 *
674 * If there is no mpdu density restriction, no further calculation
675 * is needed.
676 */
677
678 if (tid->an->mpdudensity == 0)
679 return ndelim;
680
681 rix = tx_info->control.rates[0].idx;
682 flags = tx_info->control.rates[0].flags;
683 width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0;
684 half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0;
685
686 if (half_gi)
687 nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(tid->an->mpdudensity);
688 else
689 nsymbols = NUM_SYMBOLS_PER_USEC(tid->an->mpdudensity);
690
691 if (nsymbols == 0)
692 nsymbols = 1;
693
694 streams = HT_RC_2_STREAMS(rix);
695 nsymbits = bits_per_symbol[rix % 8][width] * streams;
696 minlen = (nsymbols * nsymbits) / BITS_PER_BYTE;
697
698 if (frmlen < minlen) {
699 mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ;
700 ndelim = max(mindelim, ndelim);
701 }
702
703 return ndelim;
704 }
705
706 static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc,
707 struct ath_txq *txq,
708 struct ath_atx_tid *tid,
709 struct list_head *bf_q,
710 int *aggr_len)
711 {
712 #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
713 struct ath_buf *bf, *bf_first, *bf_prev = NULL;
714 int rl = 0, nframes = 0, ndelim, prev_al = 0;
715 u16 aggr_limit = 0, al = 0, bpad = 0,
716 al_delta, h_baw = tid->baw_size / 2;
717 enum ATH_AGGR_STATUS status = ATH_AGGR_DONE;
718 struct ieee80211_tx_info *tx_info;
719 struct ath_frame_info *fi;
720
721 bf_first = list_first_entry(&tid->buf_q, struct ath_buf, list);
722
723 do {
724 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
725 fi = get_frame_info(bf->bf_mpdu);
726
727 /* do not step over block-ack window */
728 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, fi->seqno)) {
729 status = ATH_AGGR_BAW_CLOSED;
730 break;
731 }
732
733 if (!rl) {
734 aggr_limit = ath_lookup_rate(sc, bf, tid);
735 rl = 1;
736 }
737
738 /* do not exceed aggregation limit */
739 al_delta = ATH_AGGR_DELIM_SZ + fi->framelen;
740
741 if (nframes &&
742 (aggr_limit < (al + bpad + al_delta + prev_al))) {
743 status = ATH_AGGR_LIMITED;
744 break;
745 }
746
747 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
748 if (nframes && ((tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE) ||
749 !(tx_info->control.rates[0].flags & IEEE80211_TX_RC_MCS)))
750 break;
751
752 /* do not exceed subframe limit */
753 if (nframes >= min((int)h_baw, ATH_AMPDU_SUBFRAME_DEFAULT)) {
754 status = ATH_AGGR_LIMITED;
755 break;
756 }
757 nframes++;
758
759 /* add padding for previous frame to aggregation length */
760 al += bpad + al_delta;
761
762 /*
763 * Get the delimiters needed to meet the MPDU
764 * density for this node.
765 */
766 ndelim = ath_compute_num_delims(sc, tid, bf_first, fi->framelen);
767 bpad = PADBYTES(al_delta) + (ndelim << 2);
768
769 bf->bf_next = NULL;
770 ath9k_hw_set_desc_link(sc->sc_ah, bf->bf_desc, 0);
771
772 /* link buffers of this frame to the aggregate */
773 if (!fi->retries)
774 ath_tx_addto_baw(sc, tid, fi->seqno);
775 ath9k_hw_set11n_aggr_middle(sc->sc_ah, bf->bf_desc, ndelim);
776 list_move_tail(&bf->list, bf_q);
777 if (bf_prev) {
778 bf_prev->bf_next = bf;
779 ath9k_hw_set_desc_link(sc->sc_ah, bf_prev->bf_desc,
780 bf->bf_daddr);
781 }
782 bf_prev = bf;
783
784 } while (!list_empty(&tid->buf_q));
785
786 *aggr_len = al;
787
788 return status;
789 #undef PADBYTES
790 }
791
792 static void ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq,
793 struct ath_atx_tid *tid)
794 {
795 struct ath_buf *bf;
796 enum ATH_AGGR_STATUS status;
797 struct ath_frame_info *fi;
798 struct list_head bf_q;
799 int aggr_len;
800
801 do {
802 if (list_empty(&tid->buf_q))
803 return;
804
805 INIT_LIST_HEAD(&bf_q);
806
807 status = ath_tx_form_aggr(sc, txq, tid, &bf_q, &aggr_len);
808
809 /*
810 * no frames picked up to be aggregated;
811 * block-ack window is not open.
812 */
813 if (list_empty(&bf_q))
814 break;
815
816 bf = list_first_entry(&bf_q, struct ath_buf, list);
817 bf->bf_lastbf = list_entry(bf_q.prev, struct ath_buf, list);
818
819 /* if only one frame, send as non-aggregate */
820 if (bf == bf->bf_lastbf) {
821 fi = get_frame_info(bf->bf_mpdu);
822
823 bf->bf_state.bf_type &= ~BUF_AGGR;
824 ath9k_hw_clr11n_aggr(sc->sc_ah, bf->bf_desc);
825 ath_buf_set_rate(sc, bf, fi->framelen);
826 ath_tx_txqaddbuf(sc, txq, &bf_q);
827 continue;
828 }
829
830 /* setup first desc of aggregate */
831 bf->bf_state.bf_type |= BUF_AGGR;
832 ath_buf_set_rate(sc, bf, aggr_len);
833 ath9k_hw_set11n_aggr_first(sc->sc_ah, bf->bf_desc, aggr_len);
834
835 /* anchor last desc of aggregate */
836 ath9k_hw_set11n_aggr_last(sc->sc_ah, bf->bf_lastbf->bf_desc);
837
838 ath_tx_txqaddbuf(sc, txq, &bf_q);
839 TX_STAT_INC(txq->axq_qnum, a_aggr);
840
841 } while (txq->axq_ampdu_depth < ATH_AGGR_MIN_QDEPTH &&
842 status != ATH_AGGR_BAW_CLOSED);
843 }
844
845 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
846 u16 tid, u16 *ssn)
847 {
848 struct ath_atx_tid *txtid;
849 struct ath_node *an;
850
851 an = (struct ath_node *)sta->drv_priv;
852 txtid = ATH_AN_2_TID(an, tid);
853
854 if (txtid->state & (AGGR_CLEANUP | AGGR_ADDBA_COMPLETE))
855 return -EAGAIN;
856
857 txtid->state |= AGGR_ADDBA_PROGRESS;
858 txtid->paused = true;
859 *ssn = txtid->seq_start = txtid->seq_next;
860
861 memset(txtid->tx_buf, 0, sizeof(txtid->tx_buf));
862 txtid->baw_head = txtid->baw_tail = 0;
863
864 return 0;
865 }
866
867 void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
868 {
869 struct ath_node *an = (struct ath_node *)sta->drv_priv;
870 struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid);
871 struct ath_txq *txq = txtid->ac->txq;
872
873 if (txtid->state & AGGR_CLEANUP)
874 return;
875
876 if (!(txtid->state & AGGR_ADDBA_COMPLETE)) {
877 txtid->state &= ~AGGR_ADDBA_PROGRESS;
878 return;
879 }
880
881 spin_lock_bh(&txq->axq_lock);
882 txtid->paused = true;
883
884 /*
885 * If frames are still being transmitted for this TID, they will be
886 * cleaned up during tx completion. To prevent race conditions, this
887 * TID can only be reused after all in-progress subframes have been
888 * completed.
889 */
890 if (txtid->baw_head != txtid->baw_tail)
891 txtid->state |= AGGR_CLEANUP;
892 else
893 txtid->state &= ~AGGR_ADDBA_COMPLETE;
894 spin_unlock_bh(&txq->axq_lock);
895
896 ath_tx_flush_tid(sc, txtid);
897 }
898
899 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
900 {
901 struct ath_atx_tid *txtid;
902 struct ath_node *an;
903
904 an = (struct ath_node *)sta->drv_priv;
905
906 if (sc->sc_flags & SC_OP_TXAGGR) {
907 txtid = ATH_AN_2_TID(an, tid);
908 txtid->baw_size =
909 IEEE80211_MIN_AMPDU_BUF << sta->ht_cap.ampdu_factor;
910 txtid->state |= AGGR_ADDBA_COMPLETE;
911 txtid->state &= ~AGGR_ADDBA_PROGRESS;
912 ath_tx_resume_tid(sc, txtid);
913 }
914 }
915
916 /********************/
917 /* Queue Management */
918 /********************/
919
920 static void ath_txq_drain_pending_buffers(struct ath_softc *sc,
921 struct ath_txq *txq)
922 {
923 struct ath_atx_ac *ac, *ac_tmp;
924 struct ath_atx_tid *tid, *tid_tmp;
925
926 list_for_each_entry_safe(ac, ac_tmp, &txq->axq_acq, list) {
927 list_del(&ac->list);
928 ac->sched = false;
929 list_for_each_entry_safe(tid, tid_tmp, &ac->tid_q, list) {
930 list_del(&tid->list);
931 tid->sched = false;
932 ath_tid_drain(sc, txq, tid);
933 }
934 }
935 }
936
937 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
938 {
939 struct ath_hw *ah = sc->sc_ah;
940 struct ath_common *common = ath9k_hw_common(ah);
941 struct ath9k_tx_queue_info qi;
942 static const int subtype_txq_to_hwq[] = {
943 [WME_AC_BE] = ATH_TXQ_AC_BE,
944 [WME_AC_BK] = ATH_TXQ_AC_BK,
945 [WME_AC_VI] = ATH_TXQ_AC_VI,
946 [WME_AC_VO] = ATH_TXQ_AC_VO,
947 };
948 int qnum, i;
949
950 memset(&qi, 0, sizeof(qi));
951 qi.tqi_subtype = subtype_txq_to_hwq[subtype];
952 qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT;
953 qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
954 qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT;
955 qi.tqi_physCompBuf = 0;
956
957 /*
958 * Enable interrupts only for EOL and DESC conditions.
959 * We mark tx descriptors to receive a DESC interrupt
960 * when a tx queue gets deep; otherwise waiting for the
961 * EOL to reap descriptors. Note that this is done to
962 * reduce interrupt load and this only defers reaping
963 * descriptors, never transmitting frames. Aside from
964 * reducing interrupts this also permits more concurrency.
965 * The only potential downside is if the tx queue backs
966 * up in which case the top half of the kernel may backup
967 * due to a lack of tx descriptors.
968 *
969 * The UAPSD queue is an exception, since we take a desc-
970 * based intr on the EOSP frames.
971 */
972 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
973 qi.tqi_qflags = TXQ_FLAG_TXOKINT_ENABLE |
974 TXQ_FLAG_TXERRINT_ENABLE;
975 } else {
976 if (qtype == ATH9K_TX_QUEUE_UAPSD)
977 qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE;
978 else
979 qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE |
980 TXQ_FLAG_TXDESCINT_ENABLE;
981 }
982 qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi);
983 if (qnum == -1) {
984 /*
985 * NB: don't print a message, this happens
986 * normally on parts with too few tx queues
987 */
988 return NULL;
989 }
990 if (qnum >= ARRAY_SIZE(sc->tx.txq)) {
991 ath_err(common, "qnum %u out of range, max %zu!\n",
992 qnum, ARRAY_SIZE(sc->tx.txq));
993 ath9k_hw_releasetxqueue(ah, qnum);
994 return NULL;
995 }
996 if (!ATH_TXQ_SETUP(sc, qnum)) {
997 struct ath_txq *txq = &sc->tx.txq[qnum];
998
999 txq->axq_qnum = qnum;
1000 txq->axq_link = NULL;
1001 INIT_LIST_HEAD(&txq->axq_q);
1002 INIT_LIST_HEAD(&txq->axq_acq);
1003 spin_lock_init(&txq->axq_lock);
1004 txq->axq_depth = 0;
1005 txq->axq_ampdu_depth = 0;
1006 txq->axq_tx_inprogress = false;
1007 sc->tx.txqsetup |= 1<<qnum;
1008
1009 txq->txq_headidx = txq->txq_tailidx = 0;
1010 for (i = 0; i < ATH_TXFIFO_DEPTH; i++)
1011 INIT_LIST_HEAD(&txq->txq_fifo[i]);
1012 INIT_LIST_HEAD(&txq->txq_fifo_pending);
1013 }
1014 return &sc->tx.txq[qnum];
1015 }
1016
1017 int ath_txq_update(struct ath_softc *sc, int qnum,
1018 struct ath9k_tx_queue_info *qinfo)
1019 {
1020 struct ath_hw *ah = sc->sc_ah;
1021 int error = 0;
1022 struct ath9k_tx_queue_info qi;
1023
1024 if (qnum == sc->beacon.beaconq) {
1025 /*
1026 * XXX: for beacon queue, we just save the parameter.
1027 * It will be picked up by ath_beaconq_config when
1028 * it's necessary.
1029 */
1030 sc->beacon.beacon_qi = *qinfo;
1031 return 0;
1032 }
1033
1034 BUG_ON(sc->tx.txq[qnum].axq_qnum != qnum);
1035
1036 ath9k_hw_get_txq_props(ah, qnum, &qi);
1037 qi.tqi_aifs = qinfo->tqi_aifs;
1038 qi.tqi_cwmin = qinfo->tqi_cwmin;
1039 qi.tqi_cwmax = qinfo->tqi_cwmax;
1040 qi.tqi_burstTime = qinfo->tqi_burstTime;
1041 qi.tqi_readyTime = qinfo->tqi_readyTime;
1042
1043 if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) {
1044 ath_err(ath9k_hw_common(sc->sc_ah),
1045 "Unable to update hardware queue %u!\n", qnum);
1046 error = -EIO;
1047 } else {
1048 ath9k_hw_resettxqueue(ah, qnum);
1049 }
1050
1051 return error;
1052 }
1053
1054 int ath_cabq_update(struct ath_softc *sc)
1055 {
1056 struct ath9k_tx_queue_info qi;
1057 int qnum = sc->beacon.cabq->axq_qnum;
1058
1059 ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi);
1060 /*
1061 * Ensure the readytime % is within the bounds.
1062 */
1063 if (sc->config.cabqReadytime < ATH9K_READY_TIME_LO_BOUND)
1064 sc->config.cabqReadytime = ATH9K_READY_TIME_LO_BOUND;
1065 else if (sc->config.cabqReadytime > ATH9K_READY_TIME_HI_BOUND)
1066 sc->config.cabqReadytime = ATH9K_READY_TIME_HI_BOUND;
1067
1068 qi.tqi_readyTime = (sc->beacon_interval *
1069 sc->config.cabqReadytime) / 100;
1070 ath_txq_update(sc, qnum, &qi);
1071
1072 return 0;
1073 }
1074
1075 static bool bf_is_ampdu_not_probing(struct ath_buf *bf)
1076 {
1077 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(bf->bf_mpdu);
1078 return bf_isampdu(bf) && !(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE);
1079 }
1080
1081 /*
1082 * Drain a given TX queue (could be Beacon or Data)
1083 *
1084 * This assumes output has been stopped and
1085 * we do not need to block ath_tx_tasklet.
1086 */
1087 void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq, bool retry_tx)
1088 {
1089 struct ath_buf *bf, *lastbf;
1090 struct list_head bf_head;
1091 struct ath_tx_status ts;
1092
1093 memset(&ts, 0, sizeof(ts));
1094 INIT_LIST_HEAD(&bf_head);
1095
1096 for (;;) {
1097 spin_lock_bh(&txq->axq_lock);
1098
1099 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1100 if (list_empty(&txq->txq_fifo[txq->txq_tailidx])) {
1101 txq->txq_headidx = txq->txq_tailidx = 0;
1102 spin_unlock_bh(&txq->axq_lock);
1103 break;
1104 } else {
1105 bf = list_first_entry(&txq->txq_fifo[txq->txq_tailidx],
1106 struct ath_buf, list);
1107 }
1108 } else {
1109 if (list_empty(&txq->axq_q)) {
1110 txq->axq_link = NULL;
1111 spin_unlock_bh(&txq->axq_lock);
1112 break;
1113 }
1114 bf = list_first_entry(&txq->axq_q, struct ath_buf,
1115 list);
1116
1117 if (bf->bf_stale) {
1118 list_del(&bf->list);
1119 spin_unlock_bh(&txq->axq_lock);
1120
1121 ath_tx_return_buffer(sc, bf);
1122 continue;
1123 }
1124 }
1125
1126 lastbf = bf->bf_lastbf;
1127
1128 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1129 list_cut_position(&bf_head,
1130 &txq->txq_fifo[txq->txq_tailidx],
1131 &lastbf->list);
1132 INCR(txq->txq_tailidx, ATH_TXFIFO_DEPTH);
1133 } else {
1134 /* remove ath_buf's of the same mpdu from txq */
1135 list_cut_position(&bf_head, &txq->axq_q, &lastbf->list);
1136 }
1137
1138 txq->axq_depth--;
1139 if (bf_is_ampdu_not_probing(bf))
1140 txq->axq_ampdu_depth--;
1141 spin_unlock_bh(&txq->axq_lock);
1142
1143 if (bf_isampdu(bf))
1144 ath_tx_complete_aggr(sc, txq, bf, &bf_head, &ts, 0,
1145 retry_tx);
1146 else
1147 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 0);
1148 }
1149
1150 spin_lock_bh(&txq->axq_lock);
1151 txq->axq_tx_inprogress = false;
1152 spin_unlock_bh(&txq->axq_lock);
1153
1154 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1155 spin_lock_bh(&txq->axq_lock);
1156 while (!list_empty(&txq->txq_fifo_pending)) {
1157 bf = list_first_entry(&txq->txq_fifo_pending,
1158 struct ath_buf, list);
1159 list_cut_position(&bf_head,
1160 &txq->txq_fifo_pending,
1161 &bf->bf_lastbf->list);
1162 spin_unlock_bh(&txq->axq_lock);
1163
1164 if (bf_isampdu(bf))
1165 ath_tx_complete_aggr(sc, txq, bf, &bf_head,
1166 &ts, 0, retry_tx);
1167 else
1168 ath_tx_complete_buf(sc, bf, txq, &bf_head,
1169 &ts, 0, 0);
1170 spin_lock_bh(&txq->axq_lock);
1171 }
1172 spin_unlock_bh(&txq->axq_lock);
1173 }
1174
1175 /* flush any pending frames if aggregation is enabled */
1176 if (sc->sc_flags & SC_OP_TXAGGR) {
1177 if (!retry_tx) {
1178 spin_lock_bh(&txq->axq_lock);
1179 ath_txq_drain_pending_buffers(sc, txq);
1180 spin_unlock_bh(&txq->axq_lock);
1181 }
1182 }
1183 }
1184
1185 bool ath_drain_all_txq(struct ath_softc *sc, bool retry_tx)
1186 {
1187 struct ath_hw *ah = sc->sc_ah;
1188 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1189 struct ath_txq *txq;
1190 int i, npend = 0;
1191
1192 if (sc->sc_flags & SC_OP_INVALID)
1193 return true;
1194
1195 /* Stop beacon queue */
1196 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
1197
1198 /* Stop data queues */
1199 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1200 if (ATH_TXQ_SETUP(sc, i)) {
1201 txq = &sc->tx.txq[i];
1202 ath9k_hw_stoptxdma(ah, txq->axq_qnum);
1203 npend += ath9k_hw_numtxpending(ah, txq->axq_qnum);
1204 }
1205 }
1206
1207 if (npend)
1208 ath_err(common, "Failed to stop TX DMA!\n");
1209
1210 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1211 if (ATH_TXQ_SETUP(sc, i))
1212 ath_draintxq(sc, &sc->tx.txq[i], retry_tx);
1213 }
1214
1215 return !npend;
1216 }
1217
1218 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
1219 {
1220 ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum);
1221 sc->tx.txqsetup &= ~(1<<txq->axq_qnum);
1222 }
1223
1224 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq)
1225 {
1226 struct ath_atx_ac *ac;
1227 struct ath_atx_tid *tid, *last;
1228
1229 if (list_empty(&txq->axq_acq) ||
1230 txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH)
1231 return;
1232
1233 ac = list_first_entry(&txq->axq_acq, struct ath_atx_ac, list);
1234 last = list_entry(ac->tid_q.prev, struct ath_atx_tid, list);
1235 list_del(&ac->list);
1236 ac->sched = false;
1237
1238 do {
1239 if (list_empty(&ac->tid_q))
1240 return;
1241
1242 tid = list_first_entry(&ac->tid_q, struct ath_atx_tid, list);
1243 list_del(&tid->list);
1244 tid->sched = false;
1245
1246 if (tid->paused)
1247 continue;
1248
1249 ath_tx_sched_aggr(sc, txq, tid);
1250
1251 /*
1252 * add tid to round-robin queue if more frames
1253 * are pending for the tid
1254 */
1255 if (!list_empty(&tid->buf_q))
1256 ath_tx_queue_tid(txq, tid);
1257
1258 if (tid == last || txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH)
1259 break;
1260 } while (!list_empty(&ac->tid_q));
1261
1262 if (!list_empty(&ac->tid_q)) {
1263 if (!ac->sched) {
1264 ac->sched = true;
1265 list_add_tail(&ac->list, &txq->axq_acq);
1266 }
1267 }
1268 }
1269
1270 /***********/
1271 /* TX, DMA */
1272 /***********/
1273
1274 /*
1275 * Insert a chain of ath_buf (descriptors) on a txq and
1276 * assume the descriptors are already chained together by caller.
1277 */
1278 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
1279 struct list_head *head)
1280 {
1281 struct ath_hw *ah = sc->sc_ah;
1282 struct ath_common *common = ath9k_hw_common(ah);
1283 struct ath_buf *bf;
1284
1285 /*
1286 * Insert the frame on the outbound list and
1287 * pass it on to the hardware.
1288 */
1289
1290 if (list_empty(head))
1291 return;
1292
1293 bf = list_first_entry(head, struct ath_buf, list);
1294
1295 ath_dbg(common, ATH_DBG_QUEUE,
1296 "qnum: %d, txq depth: %d\n", txq->axq_qnum, txq->axq_depth);
1297
1298 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1299 if (txq->axq_depth >= ATH_TXFIFO_DEPTH) {
1300 list_splice_tail_init(head, &txq->txq_fifo_pending);
1301 return;
1302 }
1303 if (!list_empty(&txq->txq_fifo[txq->txq_headidx]))
1304 ath_dbg(common, ATH_DBG_XMIT,
1305 "Initializing tx fifo %d which is non-empty\n",
1306 txq->txq_headidx);
1307 INIT_LIST_HEAD(&txq->txq_fifo[txq->txq_headidx]);
1308 list_splice_init(head, &txq->txq_fifo[txq->txq_headidx]);
1309 INCR(txq->txq_headidx, ATH_TXFIFO_DEPTH);
1310 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
1311 ath_dbg(common, ATH_DBG_XMIT, "TXDP[%u] = %llx (%p)\n",
1312 txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc);
1313 } else {
1314 list_splice_tail_init(head, &txq->axq_q);
1315
1316 if (txq->axq_link == NULL) {
1317 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
1318 ath_dbg(common, ATH_DBG_XMIT, "TXDP[%u] = %llx (%p)\n",
1319 txq->axq_qnum, ito64(bf->bf_daddr),
1320 bf->bf_desc);
1321 } else {
1322 *txq->axq_link = bf->bf_daddr;
1323 ath_dbg(common, ATH_DBG_XMIT,
1324 "link[%u] (%p)=%llx (%p)\n",
1325 txq->axq_qnum, txq->axq_link,
1326 ito64(bf->bf_daddr), bf->bf_desc);
1327 }
1328 ath9k_hw_get_desc_link(ah, bf->bf_lastbf->bf_desc,
1329 &txq->axq_link);
1330 ath9k_hw_txstart(ah, txq->axq_qnum);
1331 }
1332 txq->axq_depth++;
1333 if (bf_is_ampdu_not_probing(bf))
1334 txq->axq_ampdu_depth++;
1335 }
1336
1337 static void ath_tx_send_ampdu(struct ath_softc *sc, struct ath_atx_tid *tid,
1338 struct ath_buf *bf, struct ath_tx_control *txctl)
1339 {
1340 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
1341 struct list_head bf_head;
1342
1343 bf->bf_state.bf_type |= BUF_AMPDU;
1344 TX_STAT_INC(txctl->txq->axq_qnum, a_queued);
1345
1346 /*
1347 * Do not queue to h/w when any of the following conditions is true:
1348 * - there are pending frames in software queue
1349 * - the TID is currently paused for ADDBA/BAR request
1350 * - seqno is not within block-ack window
1351 * - h/w queue depth exceeds low water mark
1352 */
1353 if (!list_empty(&tid->buf_q) || tid->paused ||
1354 !BAW_WITHIN(tid->seq_start, tid->baw_size, fi->seqno) ||
1355 txctl->txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH) {
1356 /*
1357 * Add this frame to software queue for scheduling later
1358 * for aggregation.
1359 */
1360 list_add_tail(&bf->list, &tid->buf_q);
1361 ath_tx_queue_tid(txctl->txq, tid);
1362 return;
1363 }
1364
1365 INIT_LIST_HEAD(&bf_head);
1366 list_add(&bf->list, &bf_head);
1367
1368 /* Add sub-frame to BAW */
1369 if (!fi->retries)
1370 ath_tx_addto_baw(sc, tid, fi->seqno);
1371
1372 /* Queue to h/w without aggregation */
1373 bf->bf_lastbf = bf;
1374 ath_buf_set_rate(sc, bf, fi->framelen);
1375 ath_tx_txqaddbuf(sc, txctl->txq, &bf_head);
1376 }
1377
1378 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
1379 struct ath_atx_tid *tid,
1380 struct list_head *bf_head)
1381 {
1382 struct ath_frame_info *fi;
1383 struct ath_buf *bf;
1384
1385 bf = list_first_entry(bf_head, struct ath_buf, list);
1386 bf->bf_state.bf_type &= ~BUF_AMPDU;
1387
1388 /* update starting sequence number for subsequent ADDBA request */
1389 if (tid)
1390 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
1391
1392 bf->bf_lastbf = bf;
1393 fi = get_frame_info(bf->bf_mpdu);
1394 ath_buf_set_rate(sc, bf, fi->framelen);
1395 ath_tx_txqaddbuf(sc, txq, bf_head);
1396 TX_STAT_INC(txq->axq_qnum, queued);
1397 }
1398
1399 static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb)
1400 {
1401 struct ieee80211_hdr *hdr;
1402 enum ath9k_pkt_type htype;
1403 __le16 fc;
1404
1405 hdr = (struct ieee80211_hdr *)skb->data;
1406 fc = hdr->frame_control;
1407
1408 if (ieee80211_is_beacon(fc))
1409 htype = ATH9K_PKT_TYPE_BEACON;
1410 else if (ieee80211_is_probe_resp(fc))
1411 htype = ATH9K_PKT_TYPE_PROBE_RESP;
1412 else if (ieee80211_is_atim(fc))
1413 htype = ATH9K_PKT_TYPE_ATIM;
1414 else if (ieee80211_is_pspoll(fc))
1415 htype = ATH9K_PKT_TYPE_PSPOLL;
1416 else
1417 htype = ATH9K_PKT_TYPE_NORMAL;
1418
1419 return htype;
1420 }
1421
1422 static void setup_frame_info(struct ieee80211_hw *hw, struct sk_buff *skb,
1423 int framelen)
1424 {
1425 struct ath_wiphy *aphy = hw->priv;
1426 struct ath_softc *sc = aphy->sc;
1427 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1428 struct ieee80211_sta *sta = tx_info->control.sta;
1429 struct ieee80211_key_conf *hw_key = tx_info->control.hw_key;
1430 struct ieee80211_hdr *hdr;
1431 struct ath_frame_info *fi = get_frame_info(skb);
1432 struct ath_node *an;
1433 struct ath_atx_tid *tid;
1434 enum ath9k_key_type keytype;
1435 u16 seqno = 0;
1436 u8 tidno;
1437
1438 keytype = ath9k_cmn_get_hw_crypto_keytype(skb);
1439
1440 hdr = (struct ieee80211_hdr *)skb->data;
1441 if (sta && ieee80211_is_data_qos(hdr->frame_control) &&
1442 conf_is_ht(&hw->conf) && (sc->sc_flags & SC_OP_TXAGGR)) {
1443
1444 an = (struct ath_node *) sta->drv_priv;
1445 tidno = ieee80211_get_qos_ctl(hdr)[0] & IEEE80211_QOS_CTL_TID_MASK;
1446
1447 /*
1448 * Override seqno set by upper layer with the one
1449 * in tx aggregation state.
1450 */
1451 tid = ATH_AN_2_TID(an, tidno);
1452 seqno = tid->seq_next;
1453 hdr->seq_ctrl = cpu_to_le16(seqno << IEEE80211_SEQ_SEQ_SHIFT);
1454 INCR(tid->seq_next, IEEE80211_SEQ_MAX);
1455 }
1456
1457 memset(fi, 0, sizeof(*fi));
1458 if (hw_key)
1459 fi->keyix = hw_key->hw_key_idx;
1460 else
1461 fi->keyix = ATH9K_TXKEYIX_INVALID;
1462 fi->keytype = keytype;
1463 fi->framelen = framelen;
1464 fi->seqno = seqno;
1465 }
1466
1467 static int setup_tx_flags(struct sk_buff *skb)
1468 {
1469 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1470 int flags = 0;
1471
1472 flags |= ATH9K_TXDESC_CLRDMASK; /* needed for crypto errors */
1473 flags |= ATH9K_TXDESC_INTREQ;
1474
1475 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
1476 flags |= ATH9K_TXDESC_NOACK;
1477
1478 if (tx_info->flags & IEEE80211_TX_CTL_LDPC)
1479 flags |= ATH9K_TXDESC_LDPC;
1480
1481 return flags;
1482 }
1483
1484 /*
1485 * rix - rate index
1486 * pktlen - total bytes (delims + data + fcs + pads + pad delims)
1487 * width - 0 for 20 MHz, 1 for 40 MHz
1488 * half_gi - to use 4us v/s 3.6 us for symbol time
1489 */
1490 static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, int pktlen,
1491 int width, int half_gi, bool shortPreamble)
1492 {
1493 u32 nbits, nsymbits, duration, nsymbols;
1494 int streams;
1495
1496 /* find number of symbols: PLCP + data */
1497 streams = HT_RC_2_STREAMS(rix);
1498 nbits = (pktlen << 3) + OFDM_PLCP_BITS;
1499 nsymbits = bits_per_symbol[rix % 8][width] * streams;
1500 nsymbols = (nbits + nsymbits - 1) / nsymbits;
1501
1502 if (!half_gi)
1503 duration = SYMBOL_TIME(nsymbols);
1504 else
1505 duration = SYMBOL_TIME_HALFGI(nsymbols);
1506
1507 /* addup duration for legacy/ht training and signal fields */
1508 duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
1509
1510 return duration;
1511 }
1512
1513 u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate)
1514 {
1515 struct ath_hw *ah = sc->sc_ah;
1516 struct ath9k_channel *curchan = ah->curchan;
1517 if ((sc->sc_flags & SC_OP_ENABLE_APM) &&
1518 (curchan->channelFlags & CHANNEL_5GHZ) &&
1519 (chainmask == 0x7) && (rate < 0x90))
1520 return 0x3;
1521 else
1522 return chainmask;
1523 }
1524
1525 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf, int len)
1526 {
1527 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1528 struct ath9k_11n_rate_series series[4];
1529 struct sk_buff *skb;
1530 struct ieee80211_tx_info *tx_info;
1531 struct ieee80211_tx_rate *rates;
1532 const struct ieee80211_rate *rate;
1533 struct ieee80211_hdr *hdr;
1534 int i, flags = 0;
1535 u8 rix = 0, ctsrate = 0;
1536 bool is_pspoll;
1537
1538 memset(series, 0, sizeof(struct ath9k_11n_rate_series) * 4);
1539
1540 skb = bf->bf_mpdu;
1541 tx_info = IEEE80211_SKB_CB(skb);
1542 rates = tx_info->control.rates;
1543 hdr = (struct ieee80211_hdr *)skb->data;
1544 is_pspoll = ieee80211_is_pspoll(hdr->frame_control);
1545
1546 /*
1547 * We check if Short Preamble is needed for the CTS rate by
1548 * checking the BSS's global flag.
1549 * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used.
1550 */
1551 rate = ieee80211_get_rts_cts_rate(sc->hw, tx_info);
1552 ctsrate = rate->hw_value;
1553 if (sc->sc_flags & SC_OP_PREAMBLE_SHORT)
1554 ctsrate |= rate->hw_value_short;
1555
1556 for (i = 0; i < 4; i++) {
1557 bool is_40, is_sgi, is_sp;
1558 int phy;
1559
1560 if (!rates[i].count || (rates[i].idx < 0))
1561 continue;
1562
1563 rix = rates[i].idx;
1564 series[i].Tries = rates[i].count;
1565
1566 if ((sc->config.ath_aggr_prot && bf_isaggr(bf)) ||
1567 (rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS)) {
1568 series[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1569 flags |= ATH9K_TXDESC_RTSENA;
1570 } else if (rates[i].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
1571 series[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1572 flags |= ATH9K_TXDESC_CTSENA;
1573 }
1574
1575 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
1576 series[i].RateFlags |= ATH9K_RATESERIES_2040;
1577 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
1578 series[i].RateFlags |= ATH9K_RATESERIES_HALFGI;
1579
1580 is_sgi = !!(rates[i].flags & IEEE80211_TX_RC_SHORT_GI);
1581 is_40 = !!(rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH);
1582 is_sp = !!(rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE);
1583
1584 if (rates[i].flags & IEEE80211_TX_RC_MCS) {
1585 /* MCS rates */
1586 series[i].Rate = rix | 0x80;
1587 series[i].ChSel = ath_txchainmask_reduction(sc,
1588 common->tx_chainmask, series[i].Rate);
1589 series[i].PktDuration = ath_pkt_duration(sc, rix, len,
1590 is_40, is_sgi, is_sp);
1591 if (rix < 8 && (tx_info->flags & IEEE80211_TX_CTL_STBC))
1592 series[i].RateFlags |= ATH9K_RATESERIES_STBC;
1593 continue;
1594 }
1595
1596 /* legacy rates */
1597 if ((tx_info->band == IEEE80211_BAND_2GHZ) &&
1598 !(rate->flags & IEEE80211_RATE_ERP_G))
1599 phy = WLAN_RC_PHY_CCK;
1600 else
1601 phy = WLAN_RC_PHY_OFDM;
1602
1603 rate = &sc->sbands[tx_info->band].bitrates[rates[i].idx];
1604 series[i].Rate = rate->hw_value;
1605 if (rate->hw_value_short) {
1606 if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
1607 series[i].Rate |= rate->hw_value_short;
1608 } else {
1609 is_sp = false;
1610 }
1611
1612 if (bf->bf_state.bfs_paprd)
1613 series[i].ChSel = common->tx_chainmask;
1614 else
1615 series[i].ChSel = ath_txchainmask_reduction(sc,
1616 common->tx_chainmask, series[i].Rate);
1617
1618 series[i].PktDuration = ath9k_hw_computetxtime(sc->sc_ah,
1619 phy, rate->bitrate * 100, len, rix, is_sp);
1620 }
1621
1622 /* For AR5416 - RTS cannot be followed by a frame larger than 8K */
1623 if (bf_isaggr(bf) && (len > sc->sc_ah->caps.rts_aggr_limit))
1624 flags &= ~ATH9K_TXDESC_RTSENA;
1625
1626 /* ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive. */
1627 if (flags & ATH9K_TXDESC_RTSENA)
1628 flags &= ~ATH9K_TXDESC_CTSENA;
1629
1630 /* set dur_update_en for l-sig computation except for PS-Poll frames */
1631 ath9k_hw_set11n_ratescenario(sc->sc_ah, bf->bf_desc,
1632 bf->bf_lastbf->bf_desc,
1633 !is_pspoll, ctsrate,
1634 0, series, 4, flags);
1635
1636 if (sc->config.ath_aggr_prot && flags)
1637 ath9k_hw_set11n_burstduration(sc->sc_ah, bf->bf_desc, 8192);
1638 }
1639
1640 static struct ath_buf *ath_tx_setup_buffer(struct ieee80211_hw *hw,
1641 struct ath_txq *txq,
1642 struct sk_buff *skb)
1643 {
1644 struct ath_wiphy *aphy = hw->priv;
1645 struct ath_softc *sc = aphy->sc;
1646 struct ath_hw *ah = sc->sc_ah;
1647 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1648 struct ath_frame_info *fi = get_frame_info(skb);
1649 struct ath_buf *bf;
1650 struct ath_desc *ds;
1651 int frm_type;
1652
1653 bf = ath_tx_get_buffer(sc);
1654 if (!bf) {
1655 ath_dbg(common, ATH_DBG_XMIT, "TX buffers are full\n");
1656 return NULL;
1657 }
1658
1659 ATH_TXBUF_RESET(bf);
1660
1661 bf->aphy = aphy;
1662 bf->bf_flags = setup_tx_flags(skb);
1663 bf->bf_mpdu = skb;
1664
1665 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
1666 skb->len, DMA_TO_DEVICE);
1667 if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) {
1668 bf->bf_mpdu = NULL;
1669 bf->bf_buf_addr = 0;
1670 ath_err(ath9k_hw_common(sc->sc_ah),
1671 "dma_mapping_error() on TX\n");
1672 ath_tx_return_buffer(sc, bf);
1673 return NULL;
1674 }
1675
1676 frm_type = get_hw_packet_type(skb);
1677
1678 ds = bf->bf_desc;
1679 ath9k_hw_set_desc_link(ah, ds, 0);
1680
1681 ath9k_hw_set11n_txdesc(ah, ds, fi->framelen, frm_type, MAX_RATE_POWER,
1682 fi->keyix, fi->keytype, bf->bf_flags);
1683
1684 ath9k_hw_filltxdesc(ah, ds,
1685 skb->len, /* segment length */
1686 true, /* first segment */
1687 true, /* last segment */
1688 ds, /* first descriptor */
1689 bf->bf_buf_addr,
1690 txq->axq_qnum);
1691
1692
1693 return bf;
1694 }
1695
1696 /* FIXME: tx power */
1697 static void ath_tx_start_dma(struct ath_softc *sc, struct ath_buf *bf,
1698 struct ath_tx_control *txctl)
1699 {
1700 struct sk_buff *skb = bf->bf_mpdu;
1701 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1702 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1703 struct list_head bf_head;
1704 struct ath_atx_tid *tid = NULL;
1705 u8 tidno;
1706
1707 spin_lock_bh(&txctl->txq->axq_lock);
1708
1709 if (ieee80211_is_data_qos(hdr->frame_control) && txctl->an) {
1710 tidno = ieee80211_get_qos_ctl(hdr)[0] &
1711 IEEE80211_QOS_CTL_TID_MASK;
1712 tid = ATH_AN_2_TID(txctl->an, tidno);
1713
1714 WARN_ON(tid->ac->txq != txctl->txq);
1715 }
1716
1717 if ((tx_info->flags & IEEE80211_TX_CTL_AMPDU) && tid) {
1718 /*
1719 * Try aggregation if it's a unicast data frame
1720 * and the destination is HT capable.
1721 */
1722 ath_tx_send_ampdu(sc, tid, bf, txctl);
1723 } else {
1724 INIT_LIST_HEAD(&bf_head);
1725 list_add_tail(&bf->list, &bf_head);
1726
1727 bf->bf_state.bfs_ftype = txctl->frame_type;
1728 bf->bf_state.bfs_paprd = txctl->paprd;
1729
1730 if (bf->bf_state.bfs_paprd)
1731 ar9003_hw_set_paprd_txdesc(sc->sc_ah, bf->bf_desc,
1732 bf->bf_state.bfs_paprd);
1733
1734 ath_tx_send_normal(sc, txctl->txq, tid, &bf_head);
1735 }
1736
1737 spin_unlock_bh(&txctl->txq->axq_lock);
1738 }
1739
1740 /* Upon failure caller should free skb */
1741 int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
1742 struct ath_tx_control *txctl)
1743 {
1744 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
1745 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1746 struct ieee80211_sta *sta = info->control.sta;
1747 struct ath_wiphy *aphy = hw->priv;
1748 struct ath_softc *sc = aphy->sc;
1749 struct ath_txq *txq = txctl->txq;
1750 struct ath_buf *bf;
1751 int padpos, padsize;
1752 int frmlen = skb->len + FCS_LEN;
1753 int q;
1754
1755 /* NOTE: sta can be NULL according to net/mac80211.h */
1756 if (sta)
1757 txctl->an = (struct ath_node *)sta->drv_priv;
1758
1759 if (info->control.hw_key)
1760 frmlen += info->control.hw_key->icv_len;
1761
1762 /*
1763 * As a temporary workaround, assign seq# here; this will likely need
1764 * to be cleaned up to work better with Beacon transmission and virtual
1765 * BSSes.
1766 */
1767 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1768 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
1769 sc->tx.seq_no += 0x10;
1770 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
1771 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
1772 }
1773
1774 /* Add the padding after the header if this is not already done */
1775 padpos = ath9k_cmn_padpos(hdr->frame_control);
1776 padsize = padpos & 3;
1777 if (padsize && skb->len > padpos) {
1778 if (skb_headroom(skb) < padsize)
1779 return -ENOMEM;
1780
1781 skb_push(skb, padsize);
1782 memmove(skb->data, skb->data + padsize, padpos);
1783 }
1784
1785 setup_frame_info(hw, skb, frmlen);
1786
1787 /*
1788 * At this point, the vif, hw_key and sta pointers in the tx control
1789 * info are no longer valid (overwritten by the ath_frame_info data.
1790 */
1791
1792 bf = ath_tx_setup_buffer(hw, txctl->txq, skb);
1793 if (unlikely(!bf))
1794 return -ENOMEM;
1795
1796 q = skb_get_queue_mapping(skb);
1797 spin_lock_bh(&txq->axq_lock);
1798 if (txq == sc->tx.txq_map[q] &&
1799 ++txq->pending_frames > ATH_MAX_QDEPTH && !txq->stopped) {
1800 ath_mac80211_stop_queue(sc, q);
1801 txq->stopped = 1;
1802 }
1803 spin_unlock_bh(&txq->axq_lock);
1804
1805 ath_tx_start_dma(sc, bf, txctl);
1806
1807 return 0;
1808 }
1809
1810 /*****************/
1811 /* TX Completion */
1812 /*****************/
1813
1814 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
1815 struct ath_wiphy *aphy, int tx_flags, int ftype,
1816 struct ath_txq *txq)
1817 {
1818 struct ieee80211_hw *hw = sc->hw;
1819 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1820 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1821 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data;
1822 int q, padpos, padsize;
1823
1824 ath_dbg(common, ATH_DBG_XMIT, "TX complete: skb: %p\n", skb);
1825
1826 if (aphy)
1827 hw = aphy->hw;
1828
1829 if (tx_flags & ATH_TX_BAR)
1830 tx_info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
1831
1832 if (!(tx_flags & (ATH_TX_ERROR | ATH_TX_XRETRY))) {
1833 /* Frame was ACKed */
1834 tx_info->flags |= IEEE80211_TX_STAT_ACK;
1835 }
1836
1837 padpos = ath9k_cmn_padpos(hdr->frame_control);
1838 padsize = padpos & 3;
1839 if (padsize && skb->len>padpos+padsize) {
1840 /*
1841 * Remove MAC header padding before giving the frame back to
1842 * mac80211.
1843 */
1844 memmove(skb->data + padsize, skb->data, padpos);
1845 skb_pull(skb, padsize);
1846 }
1847
1848 if (sc->ps_flags & PS_WAIT_FOR_TX_ACK) {
1849 sc->ps_flags &= ~PS_WAIT_FOR_TX_ACK;
1850 ath_dbg(common, ATH_DBG_PS,
1851 "Going back to sleep after having received TX status (0x%lx)\n",
1852 sc->ps_flags & (PS_WAIT_FOR_BEACON |
1853 PS_WAIT_FOR_CAB |
1854 PS_WAIT_FOR_PSPOLL_DATA |
1855 PS_WAIT_FOR_TX_ACK));
1856 }
1857
1858 if (unlikely(ftype))
1859 ath9k_tx_status(hw, skb, ftype);
1860 else {
1861 q = skb_get_queue_mapping(skb);
1862 if (txq == sc->tx.txq_map[q]) {
1863 spin_lock_bh(&txq->axq_lock);
1864 if (WARN_ON(--txq->pending_frames < 0))
1865 txq->pending_frames = 0;
1866 spin_unlock_bh(&txq->axq_lock);
1867 }
1868
1869 ieee80211_tx_status(hw, skb);
1870 }
1871 }
1872
1873 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
1874 struct ath_txq *txq, struct list_head *bf_q,
1875 struct ath_tx_status *ts, int txok, int sendbar)
1876 {
1877 struct sk_buff *skb = bf->bf_mpdu;
1878 unsigned long flags;
1879 int tx_flags = 0;
1880
1881 if (sendbar)
1882 tx_flags = ATH_TX_BAR;
1883
1884 if (!txok) {
1885 tx_flags |= ATH_TX_ERROR;
1886
1887 if (bf_isxretried(bf))
1888 tx_flags |= ATH_TX_XRETRY;
1889 }
1890
1891 dma_unmap_single(sc->dev, bf->bf_buf_addr, skb->len, DMA_TO_DEVICE);
1892 bf->bf_buf_addr = 0;
1893
1894 if (bf->bf_state.bfs_paprd) {
1895 if (!sc->paprd_pending)
1896 dev_kfree_skb_any(skb);
1897 else
1898 complete(&sc->paprd_complete);
1899 } else {
1900 ath_debug_stat_tx(sc, bf, ts);
1901 ath_tx_complete(sc, skb, bf->aphy, tx_flags,
1902 bf->bf_state.bfs_ftype, txq);
1903 }
1904 /* At this point, skb (bf->bf_mpdu) is consumed...make sure we don't
1905 * accidentally reference it later.
1906 */
1907 bf->bf_mpdu = NULL;
1908
1909 /*
1910 * Return the list of ath_buf of this mpdu to free queue
1911 */
1912 spin_lock_irqsave(&sc->tx.txbuflock, flags);
1913 list_splice_tail_init(bf_q, &sc->tx.txbuf);
1914 spin_unlock_irqrestore(&sc->tx.txbuflock, flags);
1915 }
1916
1917 static void ath_tx_rc_status(struct ath_buf *bf, struct ath_tx_status *ts,
1918 int nframes, int nbad, int txok, bool update_rc)
1919 {
1920 struct sk_buff *skb = bf->bf_mpdu;
1921 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1922 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1923 struct ieee80211_hw *hw = bf->aphy->hw;
1924 struct ath_softc *sc = bf->aphy->sc;
1925 struct ath_hw *ah = sc->sc_ah;
1926 u8 i, tx_rateindex;
1927
1928 if (txok)
1929 tx_info->status.ack_signal = ts->ts_rssi;
1930
1931 tx_rateindex = ts->ts_rateindex;
1932 WARN_ON(tx_rateindex >= hw->max_rates);
1933
1934 if (ts->ts_status & ATH9K_TXERR_FILT)
1935 tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
1936 if ((tx_info->flags & IEEE80211_TX_CTL_AMPDU) && update_rc) {
1937 tx_info->flags |= IEEE80211_TX_STAT_AMPDU;
1938
1939 BUG_ON(nbad > nframes);
1940
1941 tx_info->status.ampdu_len = nframes;
1942 tx_info->status.ampdu_ack_len = nframes - nbad;
1943 }
1944
1945 if ((ts->ts_status & ATH9K_TXERR_FILT) == 0 &&
1946 (bf->bf_flags & ATH9K_TXDESC_NOACK) == 0 && update_rc) {
1947 /*
1948 * If an underrun error is seen assume it as an excessive
1949 * retry only if max frame trigger level has been reached
1950 * (2 KB for single stream, and 4 KB for dual stream).
1951 * Adjust the long retry as if the frame was tried
1952 * hw->max_rate_tries times to affect how rate control updates
1953 * PER for the failed rate.
1954 * In case of congestion on the bus penalizing this type of
1955 * underruns should help hardware actually transmit new frames
1956 * successfully by eventually preferring slower rates.
1957 * This itself should also alleviate congestion on the bus.
1958 */
1959 if (ieee80211_is_data(hdr->frame_control) &&
1960 (ts->ts_flags & (ATH9K_TX_DATA_UNDERRUN |
1961 ATH9K_TX_DELIM_UNDERRUN)) &&
1962 ah->tx_trig_level >= sc->sc_ah->caps.tx_triglevel_max)
1963 tx_info->status.rates[tx_rateindex].count =
1964 hw->max_rate_tries;
1965 }
1966
1967 for (i = tx_rateindex + 1; i < hw->max_rates; i++) {
1968 tx_info->status.rates[i].count = 0;
1969 tx_info->status.rates[i].idx = -1;
1970 }
1971
1972 tx_info->status.rates[tx_rateindex].count = ts->ts_longretry + 1;
1973 }
1974
1975 static void ath_wake_mac80211_queue(struct ath_softc *sc, int qnum)
1976 {
1977 struct ath_txq *txq;
1978
1979 txq = sc->tx.txq_map[qnum];
1980 spin_lock_bh(&txq->axq_lock);
1981 if (txq->stopped && txq->pending_frames < ATH_MAX_QDEPTH) {
1982 if (ath_mac80211_start_queue(sc, qnum))
1983 txq->stopped = 0;
1984 }
1985 spin_unlock_bh(&txq->axq_lock);
1986 }
1987
1988 static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
1989 {
1990 struct ath_hw *ah = sc->sc_ah;
1991 struct ath_common *common = ath9k_hw_common(ah);
1992 struct ath_buf *bf, *lastbf, *bf_held = NULL;
1993 struct list_head bf_head;
1994 struct ath_desc *ds;
1995 struct ath_tx_status ts;
1996 int txok;
1997 int status;
1998 int qnum;
1999
2000 ath_dbg(common, ATH_DBG_QUEUE, "tx queue %d (%x), link %p\n",
2001 txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum),
2002 txq->axq_link);
2003
2004 for (;;) {
2005 spin_lock_bh(&txq->axq_lock);
2006 if (list_empty(&txq->axq_q)) {
2007 txq->axq_link = NULL;
2008 spin_unlock_bh(&txq->axq_lock);
2009 break;
2010 }
2011 bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
2012
2013 /*
2014 * There is a race condition that a BH gets scheduled
2015 * after sw writes TxE and before hw re-load the last
2016 * descriptor to get the newly chained one.
2017 * Software must keep the last DONE descriptor as a
2018 * holding descriptor - software does so by marking
2019 * it with the STALE flag.
2020 */
2021 bf_held = NULL;
2022 if (bf->bf_stale) {
2023 bf_held = bf;
2024 if (list_is_last(&bf_held->list, &txq->axq_q)) {
2025 spin_unlock_bh(&txq->axq_lock);
2026 break;
2027 } else {
2028 bf = list_entry(bf_held->list.next,
2029 struct ath_buf, list);
2030 }
2031 }
2032
2033 lastbf = bf->bf_lastbf;
2034 ds = lastbf->bf_desc;
2035
2036 memset(&ts, 0, sizeof(ts));
2037 status = ath9k_hw_txprocdesc(ah, ds, &ts);
2038 if (status == -EINPROGRESS) {
2039 spin_unlock_bh(&txq->axq_lock);
2040 break;
2041 }
2042 TX_STAT_INC(txq->axq_qnum, txprocdesc);
2043
2044 /*
2045 * Remove ath_buf's of the same transmit unit from txq,
2046 * however leave the last descriptor back as the holding
2047 * descriptor for hw.
2048 */
2049 lastbf->bf_stale = true;
2050 INIT_LIST_HEAD(&bf_head);
2051 if (!list_is_singular(&lastbf->list))
2052 list_cut_position(&bf_head,
2053 &txq->axq_q, lastbf->list.prev);
2054
2055 txq->axq_depth--;
2056 txok = !(ts.ts_status & ATH9K_TXERR_MASK);
2057 txq->axq_tx_inprogress = false;
2058 if (bf_held)
2059 list_del(&bf_held->list);
2060
2061 if (bf_is_ampdu_not_probing(bf))
2062 txq->axq_ampdu_depth--;
2063 spin_unlock_bh(&txq->axq_lock);
2064
2065 if (bf_held)
2066 ath_tx_return_buffer(sc, bf_held);
2067
2068 if (!bf_isampdu(bf)) {
2069 /*
2070 * This frame is sent out as a single frame.
2071 * Use hardware retry status for this frame.
2072 */
2073 if (ts.ts_status & ATH9K_TXERR_XRETRY)
2074 bf->bf_state.bf_type |= BUF_XRETRY;
2075 ath_tx_rc_status(bf, &ts, 1, txok ? 0 : 1, txok, true);
2076 }
2077
2078 qnum = skb_get_queue_mapping(bf->bf_mpdu);
2079
2080 if (bf_isampdu(bf))
2081 ath_tx_complete_aggr(sc, txq, bf, &bf_head, &ts, txok,
2082 true);
2083 else
2084 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, txok, 0);
2085
2086 if (txq == sc->tx.txq_map[qnum])
2087 ath_wake_mac80211_queue(sc, qnum);
2088
2089 spin_lock_bh(&txq->axq_lock);
2090 if (sc->sc_flags & SC_OP_TXAGGR)
2091 ath_txq_schedule(sc, txq);
2092 spin_unlock_bh(&txq->axq_lock);
2093 }
2094 }
2095
2096 static void ath_tx_complete_poll_work(struct work_struct *work)
2097 {
2098 struct ath_softc *sc = container_of(work, struct ath_softc,
2099 tx_complete_work.work);
2100 struct ath_txq *txq;
2101 int i;
2102 bool needreset = false;
2103
2104 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
2105 if (ATH_TXQ_SETUP(sc, i)) {
2106 txq = &sc->tx.txq[i];
2107 spin_lock_bh(&txq->axq_lock);
2108 if (txq->axq_depth) {
2109 if (txq->axq_tx_inprogress) {
2110 needreset = true;
2111 spin_unlock_bh(&txq->axq_lock);
2112 break;
2113 } else {
2114 txq->axq_tx_inprogress = true;
2115 }
2116 }
2117 spin_unlock_bh(&txq->axq_lock);
2118 }
2119
2120 if (needreset) {
2121 ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_RESET,
2122 "tx hung, resetting the chip\n");
2123 ath9k_ps_wakeup(sc);
2124 ath_reset(sc, true);
2125 ath9k_ps_restore(sc);
2126 }
2127
2128 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work,
2129 msecs_to_jiffies(ATH_TX_COMPLETE_POLL_INT));
2130 }
2131
2132
2133
2134 void ath_tx_tasklet(struct ath_softc *sc)
2135 {
2136 int i;
2137 u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1);
2138
2139 ath9k_hw_gettxintrtxqs(sc->sc_ah, &qcumask);
2140
2141 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2142 if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i)))
2143 ath_tx_processq(sc, &sc->tx.txq[i]);
2144 }
2145 }
2146
2147 void ath_tx_edma_tasklet(struct ath_softc *sc)
2148 {
2149 struct ath_tx_status txs;
2150 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2151 struct ath_hw *ah = sc->sc_ah;
2152 struct ath_txq *txq;
2153 struct ath_buf *bf, *lastbf;
2154 struct list_head bf_head;
2155 int status;
2156 int txok;
2157 int qnum;
2158
2159 for (;;) {
2160 status = ath9k_hw_txprocdesc(ah, NULL, (void *)&txs);
2161 if (status == -EINPROGRESS)
2162 break;
2163 if (status == -EIO) {
2164 ath_dbg(common, ATH_DBG_XMIT,
2165 "Error processing tx status\n");
2166 break;
2167 }
2168
2169 /* Skip beacon completions */
2170 if (txs.qid == sc->beacon.beaconq)
2171 continue;
2172
2173 txq = &sc->tx.txq[txs.qid];
2174
2175 spin_lock_bh(&txq->axq_lock);
2176 if (list_empty(&txq->txq_fifo[txq->txq_tailidx])) {
2177 spin_unlock_bh(&txq->axq_lock);
2178 return;
2179 }
2180
2181 bf = list_first_entry(&txq->txq_fifo[txq->txq_tailidx],
2182 struct ath_buf, list);
2183 lastbf = bf->bf_lastbf;
2184
2185 INIT_LIST_HEAD(&bf_head);
2186 list_cut_position(&bf_head, &txq->txq_fifo[txq->txq_tailidx],
2187 &lastbf->list);
2188 INCR(txq->txq_tailidx, ATH_TXFIFO_DEPTH);
2189 txq->axq_depth--;
2190 txq->axq_tx_inprogress = false;
2191 if (bf_is_ampdu_not_probing(bf))
2192 txq->axq_ampdu_depth--;
2193 spin_unlock_bh(&txq->axq_lock);
2194
2195 txok = !(txs.ts_status & ATH9K_TXERR_MASK);
2196
2197 if (!bf_isampdu(bf)) {
2198 if (txs.ts_status & ATH9K_TXERR_XRETRY)
2199 bf->bf_state.bf_type |= BUF_XRETRY;
2200 ath_tx_rc_status(bf, &txs, 1, txok ? 0 : 1, txok, true);
2201 }
2202
2203 qnum = skb_get_queue_mapping(bf->bf_mpdu);
2204
2205 if (bf_isampdu(bf))
2206 ath_tx_complete_aggr(sc, txq, bf, &bf_head, &txs,
2207 txok, true);
2208 else
2209 ath_tx_complete_buf(sc, bf, txq, &bf_head,
2210 &txs, txok, 0);
2211
2212 if (txq == sc->tx.txq_map[qnum])
2213 ath_wake_mac80211_queue(sc, qnum);
2214
2215 spin_lock_bh(&txq->axq_lock);
2216 if (!list_empty(&txq->txq_fifo_pending)) {
2217 INIT_LIST_HEAD(&bf_head);
2218 bf = list_first_entry(&txq->txq_fifo_pending,
2219 struct ath_buf, list);
2220 list_cut_position(&bf_head, &txq->txq_fifo_pending,
2221 &bf->bf_lastbf->list);
2222 ath_tx_txqaddbuf(sc, txq, &bf_head);
2223 } else if (sc->sc_flags & SC_OP_TXAGGR)
2224 ath_txq_schedule(sc, txq);
2225 spin_unlock_bh(&txq->axq_lock);
2226 }
2227 }
2228
2229 /*****************/
2230 /* Init, Cleanup */
2231 /*****************/
2232
2233 static int ath_txstatus_setup(struct ath_softc *sc, int size)
2234 {
2235 struct ath_descdma *dd = &sc->txsdma;
2236 u8 txs_len = sc->sc_ah->caps.txs_len;
2237
2238 dd->dd_desc_len = size * txs_len;
2239 dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
2240 &dd->dd_desc_paddr, GFP_KERNEL);
2241 if (!dd->dd_desc)
2242 return -ENOMEM;
2243
2244 return 0;
2245 }
2246
2247 static int ath_tx_edma_init(struct ath_softc *sc)
2248 {
2249 int err;
2250
2251 err = ath_txstatus_setup(sc, ATH_TXSTATUS_RING_SIZE);
2252 if (!err)
2253 ath9k_hw_setup_statusring(sc->sc_ah, sc->txsdma.dd_desc,
2254 sc->txsdma.dd_desc_paddr,
2255 ATH_TXSTATUS_RING_SIZE);
2256
2257 return err;
2258 }
2259
2260 static void ath_tx_edma_cleanup(struct ath_softc *sc)
2261 {
2262 struct ath_descdma *dd = &sc->txsdma;
2263
2264 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
2265 dd->dd_desc_paddr);
2266 }
2267
2268 int ath_tx_init(struct ath_softc *sc, int nbufs)
2269 {
2270 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2271 int error = 0;
2272
2273 spin_lock_init(&sc->tx.txbuflock);
2274
2275 error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf,
2276 "tx", nbufs, 1, 1);
2277 if (error != 0) {
2278 ath_err(common,
2279 "Failed to allocate tx descriptors: %d\n", error);
2280 goto err;
2281 }
2282
2283 error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf,
2284 "beacon", ATH_BCBUF, 1, 1);
2285 if (error != 0) {
2286 ath_err(common,
2287 "Failed to allocate beacon descriptors: %d\n", error);
2288 goto err;
2289 }
2290
2291 INIT_DELAYED_WORK(&sc->tx_complete_work, ath_tx_complete_poll_work);
2292
2293 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
2294 error = ath_tx_edma_init(sc);
2295 if (error)
2296 goto err;
2297 }
2298
2299 err:
2300 if (error != 0)
2301 ath_tx_cleanup(sc);
2302
2303 return error;
2304 }
2305
2306 void ath_tx_cleanup(struct ath_softc *sc)
2307 {
2308 if (sc->beacon.bdma.dd_desc_len != 0)
2309 ath_descdma_cleanup(sc, &sc->beacon.bdma, &sc->beacon.bbuf);
2310
2311 if (sc->tx.txdma.dd_desc_len != 0)
2312 ath_descdma_cleanup(sc, &sc->tx.txdma, &sc->tx.txbuf);
2313
2314 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
2315 ath_tx_edma_cleanup(sc);
2316 }
2317
2318 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an)
2319 {
2320 struct ath_atx_tid *tid;
2321 struct ath_atx_ac *ac;
2322 int tidno, acno;
2323
2324 for (tidno = 0, tid = &an->tid[tidno];
2325 tidno < WME_NUM_TID;
2326 tidno++, tid++) {
2327 tid->an = an;
2328 tid->tidno = tidno;
2329 tid->seq_start = tid->seq_next = 0;
2330 tid->baw_size = WME_MAX_BA;
2331 tid->baw_head = tid->baw_tail = 0;
2332 tid->sched = false;
2333 tid->paused = false;
2334 tid->state &= ~AGGR_CLEANUP;
2335 INIT_LIST_HEAD(&tid->buf_q);
2336 acno = TID_TO_WME_AC(tidno);
2337 tid->ac = &an->ac[acno];
2338 tid->state &= ~AGGR_ADDBA_COMPLETE;
2339 tid->state &= ~AGGR_ADDBA_PROGRESS;
2340 }
2341
2342 for (acno = 0, ac = &an->ac[acno];
2343 acno < WME_NUM_AC; acno++, ac++) {
2344 ac->sched = false;
2345 ac->txq = sc->tx.txq_map[acno];
2346 INIT_LIST_HEAD(&ac->tid_q);
2347 }
2348 }
2349
2350 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an)
2351 {
2352 struct ath_atx_ac *ac;
2353 struct ath_atx_tid *tid;
2354 struct ath_txq *txq;
2355 int tidno;
2356
2357 for (tidno = 0, tid = &an->tid[tidno];
2358 tidno < WME_NUM_TID; tidno++, tid++) {
2359
2360 ac = tid->ac;
2361 txq = ac->txq;
2362
2363 spin_lock_bh(&txq->axq_lock);
2364
2365 if (tid->sched) {
2366 list_del(&tid->list);
2367 tid->sched = false;
2368 }
2369
2370 if (ac->sched) {
2371 list_del(&ac->list);
2372 tid->ac->sched = false;
2373 }
2374
2375 ath_tid_drain(sc, txq, tid);
2376 tid->state &= ~AGGR_ADDBA_COMPLETE;
2377 tid->state &= ~AGGR_CLEANUP;
2378
2379 spin_unlock_bh(&txq->axq_lock);
2380 }
2381 }
Linux kernel - Deliverables
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