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ath9k: fix aggregation stop/flush handling
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / xmit.c
1 /*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/dma-mapping.h>
18 #include "ath9k.h"
19 #include "ar9003_mac.h"
20
21 #define BITS_PER_BYTE 8
22 #define OFDM_PLCP_BITS 22
23 #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
24 #define L_STF 8
25 #define L_LTF 8
26 #define L_SIG 4
27 #define HT_SIG 8
28 #define HT_STF 4
29 #define HT_LTF(_ns) (4 * (_ns))
30 #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */
31 #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */
32 #define TIME_SYMBOLS(t) ((t) >> 2)
33 #define TIME_SYMBOLS_HALFGI(t) (((t) * 5 - 4) / 18)
34 #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
35 #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
36
37
38 static u16 bits_per_symbol[][2] = {
39 /* 20MHz 40MHz */
40 { 26, 54 }, /* 0: BPSK */
41 { 52, 108 }, /* 1: QPSK 1/2 */
42 { 78, 162 }, /* 2: QPSK 3/4 */
43 { 104, 216 }, /* 3: 16-QAM 1/2 */
44 { 156, 324 }, /* 4: 16-QAM 3/4 */
45 { 208, 432 }, /* 5: 64-QAM 2/3 */
46 { 234, 486 }, /* 6: 64-QAM 3/4 */
47 { 260, 540 }, /* 7: 64-QAM 5/6 */
48 };
49
50 #define IS_HT_RATE(_rate) ((_rate) & 0x80)
51
52 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
53 struct ath_atx_tid *tid, struct sk_buff *skb);
54 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
55 int tx_flags, struct ath_txq *txq);
56 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
57 struct ath_txq *txq, struct list_head *bf_q,
58 struct ath_tx_status *ts, int txok);
59 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
60 struct list_head *head, bool internal);
61 static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
62 struct ath_tx_status *ts, int nframes, int nbad,
63 int txok);
64 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
65 int seqno);
66 static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc,
67 struct ath_txq *txq,
68 struct ath_atx_tid *tid,
69 struct sk_buff *skb);
70
71 enum {
72 MCS_HT20,
73 MCS_HT20_SGI,
74 MCS_HT40,
75 MCS_HT40_SGI,
76 };
77
78 /*********************/
79 /* Aggregation logic */
80 /*********************/
81
82 void ath_txq_lock(struct ath_softc *sc, struct ath_txq *txq)
83 __acquires(&txq->axq_lock)
84 {
85 spin_lock_bh(&txq->axq_lock);
86 }
87
88 void ath_txq_unlock(struct ath_softc *sc, struct ath_txq *txq)
89 __releases(&txq->axq_lock)
90 {
91 spin_unlock_bh(&txq->axq_lock);
92 }
93
94 void ath_txq_unlock_complete(struct ath_softc *sc, struct ath_txq *txq)
95 __releases(&txq->axq_lock)
96 {
97 struct sk_buff_head q;
98 struct sk_buff *skb;
99
100 __skb_queue_head_init(&q);
101 skb_queue_splice_init(&txq->complete_q, &q);
102 spin_unlock_bh(&txq->axq_lock);
103
104 while ((skb = __skb_dequeue(&q)))
105 ieee80211_tx_status(sc->hw, skb);
106 }
107
108 static void ath_tx_queue_tid(struct ath_txq *txq, struct ath_atx_tid *tid)
109 {
110 struct ath_atx_ac *ac = tid->ac;
111
112 if (tid->paused)
113 return;
114
115 if (tid->sched)
116 return;
117
118 tid->sched = true;
119 list_add_tail(&tid->list, &ac->tid_q);
120
121 if (ac->sched)
122 return;
123
124 ac->sched = true;
125 list_add_tail(&ac->list, &txq->axq_acq);
126 }
127
128 static void ath_tx_resume_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
129 {
130 struct ath_txq *txq = tid->ac->txq;
131
132 WARN_ON(!tid->paused);
133
134 ath_txq_lock(sc, txq);
135 tid->paused = false;
136
137 if (skb_queue_empty(&tid->buf_q))
138 goto unlock;
139
140 ath_tx_queue_tid(txq, tid);
141 ath_txq_schedule(sc, txq);
142 unlock:
143 ath_txq_unlock_complete(sc, txq);
144 }
145
146 static struct ath_frame_info *get_frame_info(struct sk_buff *skb)
147 {
148 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
149 BUILD_BUG_ON(sizeof(struct ath_frame_info) >
150 sizeof(tx_info->rate_driver_data));
151 return (struct ath_frame_info *) &tx_info->rate_driver_data[0];
152 }
153
154 static void ath_send_bar(struct ath_atx_tid *tid, u16 seqno)
155 {
156 ieee80211_send_bar(tid->an->vif, tid->an->sta->addr, tid->tidno,
157 seqno << IEEE80211_SEQ_SEQ_SHIFT);
158 }
159
160 static void ath_set_rates(struct ieee80211_vif *vif, struct ieee80211_sta *sta,
161 struct ath_buf *bf)
162 {
163 ieee80211_get_tx_rates(vif, sta, bf->bf_mpdu, bf->rates,
164 ARRAY_SIZE(bf->rates));
165 }
166
167 static void ath_tx_clear_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
168 {
169 tid->state &= ~AGGR_ADDBA_COMPLETE;
170 tid->state &= ~AGGR_CLEANUP;
171 if (!tid->stop_cb)
172 return;
173
174 ieee80211_start_tx_ba_cb_irqsafe(tid->an->vif, tid->an->sta->addr,
175 tid->tidno);
176 tid->stop_cb = false;
177 }
178
179 static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid,
180 bool flush_packets)
181 {
182 struct ath_txq *txq = tid->ac->txq;
183 struct sk_buff *skb;
184 struct ath_buf *bf;
185 struct list_head bf_head;
186 struct ath_tx_status ts;
187 struct ath_frame_info *fi;
188 bool sendbar = false;
189
190 INIT_LIST_HEAD(&bf_head);
191
192 memset(&ts, 0, sizeof(ts));
193
194 while ((skb = __skb_dequeue(&tid->buf_q))) {
195 fi = get_frame_info(skb);
196 bf = fi->bf;
197 if (!bf && !flush_packets)
198 bf = ath_tx_setup_buffer(sc, txq, tid, skb);
199
200 if (!bf) {
201 ieee80211_free_txskb(sc->hw, skb);
202 continue;
203 }
204
205 if (fi->retries || flush_packets) {
206 list_add_tail(&bf->list, &bf_head);
207 ath_tx_update_baw(sc, tid, bf->bf_state.seqno);
208 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0);
209 sendbar = true;
210 } else {
211 ath_set_rates(tid->an->vif, tid->an->sta, bf);
212 ath_tx_send_normal(sc, txq, NULL, skb);
213 }
214 }
215
216 if (tid->baw_head == tid->baw_tail)
217 ath_tx_clear_tid(sc, tid);
218
219 if (sendbar && !flush_packets) {
220 ath_txq_unlock(sc, txq);
221 ath_send_bar(tid, tid->seq_start);
222 ath_txq_lock(sc, txq);
223 }
224 }
225
226 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
227 int seqno)
228 {
229 int index, cindex;
230
231 index = ATH_BA_INDEX(tid->seq_start, seqno);
232 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
233
234 __clear_bit(cindex, tid->tx_buf);
235
236 while (tid->baw_head != tid->baw_tail && !test_bit(tid->baw_head, tid->tx_buf)) {
237 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
238 INCR(tid->baw_head, ATH_TID_MAX_BUFS);
239 if (tid->bar_index >= 0)
240 tid->bar_index--;
241 }
242 }
243
244 static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
245 u16 seqno)
246 {
247 int index, cindex;
248
249 index = ATH_BA_INDEX(tid->seq_start, seqno);
250 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
251 __set_bit(cindex, tid->tx_buf);
252
253 if (index >= ((tid->baw_tail - tid->baw_head) &
254 (ATH_TID_MAX_BUFS - 1))) {
255 tid->baw_tail = cindex;
256 INCR(tid->baw_tail, ATH_TID_MAX_BUFS);
257 }
258 }
259
260 /*
261 * TODO: For frame(s) that are in the retry state, we will reuse the
262 * sequence number(s) without setting the retry bit. The
263 * alternative is to give up on these and BAR the receiver's window
264 * forward.
265 */
266 static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq,
267 struct ath_atx_tid *tid)
268
269 {
270 struct sk_buff *skb;
271 struct ath_buf *bf;
272 struct list_head bf_head;
273 struct ath_tx_status ts;
274 struct ath_frame_info *fi;
275
276 memset(&ts, 0, sizeof(ts));
277 INIT_LIST_HEAD(&bf_head);
278
279 while ((skb = __skb_dequeue(&tid->buf_q))) {
280 fi = get_frame_info(skb);
281 bf = fi->bf;
282
283 if (!bf) {
284 ath_tx_complete(sc, skb, ATH_TX_ERROR, txq);
285 continue;
286 }
287
288 list_add_tail(&bf->list, &bf_head);
289
290 if (fi->retries)
291 ath_tx_update_baw(sc, tid, bf->bf_state.seqno);
292
293 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0);
294 }
295
296 tid->seq_next = tid->seq_start;
297 tid->baw_tail = tid->baw_head;
298 tid->bar_index = -1;
299 }
300
301 static void ath_tx_set_retry(struct ath_softc *sc, struct ath_txq *txq,
302 struct sk_buff *skb, int count)
303 {
304 struct ath_frame_info *fi = get_frame_info(skb);
305 struct ath_buf *bf = fi->bf;
306 struct ieee80211_hdr *hdr;
307 int prev = fi->retries;
308
309 TX_STAT_INC(txq->axq_qnum, a_retries);
310 fi->retries += count;
311
312 if (prev > 0)
313 return;
314
315 hdr = (struct ieee80211_hdr *)skb->data;
316 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY);
317 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
318 sizeof(*hdr), DMA_TO_DEVICE);
319 }
320
321 static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc)
322 {
323 struct ath_buf *bf = NULL;
324
325 spin_lock_bh(&sc->tx.txbuflock);
326
327 if (unlikely(list_empty(&sc->tx.txbuf))) {
328 spin_unlock_bh(&sc->tx.txbuflock);
329 return NULL;
330 }
331
332 bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list);
333 list_del(&bf->list);
334
335 spin_unlock_bh(&sc->tx.txbuflock);
336
337 return bf;
338 }
339
340 static void ath_tx_return_buffer(struct ath_softc *sc, struct ath_buf *bf)
341 {
342 spin_lock_bh(&sc->tx.txbuflock);
343 list_add_tail(&bf->list, &sc->tx.txbuf);
344 spin_unlock_bh(&sc->tx.txbuflock);
345 }
346
347 static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf)
348 {
349 struct ath_buf *tbf;
350
351 tbf = ath_tx_get_buffer(sc);
352 if (WARN_ON(!tbf))
353 return NULL;
354
355 ATH_TXBUF_RESET(tbf);
356
357 tbf->bf_mpdu = bf->bf_mpdu;
358 tbf->bf_buf_addr = bf->bf_buf_addr;
359 memcpy(tbf->bf_desc, bf->bf_desc, sc->sc_ah->caps.tx_desc_len);
360 tbf->bf_state = bf->bf_state;
361
362 return tbf;
363 }
364
365 static void ath_tx_count_frames(struct ath_softc *sc, struct ath_buf *bf,
366 struct ath_tx_status *ts, int txok,
367 int *nframes, int *nbad)
368 {
369 struct ath_frame_info *fi;
370 u16 seq_st = 0;
371 u32 ba[WME_BA_BMP_SIZE >> 5];
372 int ba_index;
373 int isaggr = 0;
374
375 *nbad = 0;
376 *nframes = 0;
377
378 isaggr = bf_isaggr(bf);
379 if (isaggr) {
380 seq_st = ts->ts_seqnum;
381 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
382 }
383
384 while (bf) {
385 fi = get_frame_info(bf->bf_mpdu);
386 ba_index = ATH_BA_INDEX(seq_st, bf->bf_state.seqno);
387
388 (*nframes)++;
389 if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index)))
390 (*nbad)++;
391
392 bf = bf->bf_next;
393 }
394 }
395
396
397 static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
398 struct ath_buf *bf, struct list_head *bf_q,
399 struct ath_tx_status *ts, int txok)
400 {
401 struct ath_node *an = NULL;
402 struct sk_buff *skb;
403 struct ieee80211_sta *sta;
404 struct ieee80211_hw *hw = sc->hw;
405 struct ieee80211_hdr *hdr;
406 struct ieee80211_tx_info *tx_info;
407 struct ath_atx_tid *tid = NULL;
408 struct ath_buf *bf_next, *bf_last = bf->bf_lastbf;
409 struct list_head bf_head;
410 struct sk_buff_head bf_pending;
411 u16 seq_st = 0, acked_cnt = 0, txfail_cnt = 0, seq_first;
412 u32 ba[WME_BA_BMP_SIZE >> 5];
413 int isaggr, txfail, txpending, sendbar = 0, needreset = 0, nbad = 0;
414 bool rc_update = true, isba;
415 struct ieee80211_tx_rate rates[4];
416 struct ath_frame_info *fi;
417 int nframes;
418 u8 tidno;
419 bool flush = !!(ts->ts_status & ATH9K_TX_FLUSH);
420 int i, retries;
421 int bar_index = -1;
422
423 skb = bf->bf_mpdu;
424 hdr = (struct ieee80211_hdr *)skb->data;
425
426 tx_info = IEEE80211_SKB_CB(skb);
427
428 memcpy(rates, bf->rates, sizeof(rates));
429
430 retries = ts->ts_longretry + 1;
431 for (i = 0; i < ts->ts_rateindex; i++)
432 retries += rates[i].count;
433
434 rcu_read_lock();
435
436 sta = ieee80211_find_sta_by_ifaddr(hw, hdr->addr1, hdr->addr2);
437 if (!sta) {
438 rcu_read_unlock();
439
440 INIT_LIST_HEAD(&bf_head);
441 while (bf) {
442 bf_next = bf->bf_next;
443
444 if (!bf->bf_stale || bf_next != NULL)
445 list_move_tail(&bf->list, &bf_head);
446
447 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts, 0);
448
449 bf = bf_next;
450 }
451 return;
452 }
453
454 an = (struct ath_node *)sta->drv_priv;
455 tidno = ieee80211_get_qos_ctl(hdr)[0] & IEEE80211_QOS_CTL_TID_MASK;
456 tid = ATH_AN_2_TID(an, tidno);
457 seq_first = tid->seq_start;
458 isba = ts->ts_flags & ATH9K_TX_BA;
459
460 /*
461 * The hardware occasionally sends a tx status for the wrong TID.
462 * In this case, the BA status cannot be considered valid and all
463 * subframes need to be retransmitted
464 *
465 * Only BlockAcks have a TID and therefore normal Acks cannot be
466 * checked
467 */
468 if (isba && tidno != ts->tid)
469 txok = false;
470
471 isaggr = bf_isaggr(bf);
472 memset(ba, 0, WME_BA_BMP_SIZE >> 3);
473
474 if (isaggr && txok) {
475 if (ts->ts_flags & ATH9K_TX_BA) {
476 seq_st = ts->ts_seqnum;
477 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
478 } else {
479 /*
480 * AR5416 can become deaf/mute when BA
481 * issue happens. Chip needs to be reset.
482 * But AP code may have sychronization issues
483 * when perform internal reset in this routine.
484 * Only enable reset in STA mode for now.
485 */
486 if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION)
487 needreset = 1;
488 }
489 }
490
491 __skb_queue_head_init(&bf_pending);
492
493 ath_tx_count_frames(sc, bf, ts, txok, &nframes, &nbad);
494 while (bf) {
495 u16 seqno = bf->bf_state.seqno;
496
497 txfail = txpending = sendbar = 0;
498 bf_next = bf->bf_next;
499
500 skb = bf->bf_mpdu;
501 tx_info = IEEE80211_SKB_CB(skb);
502 fi = get_frame_info(skb);
503
504 if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, seqno))) {
505 /* transmit completion, subframe is
506 * acked by block ack */
507 acked_cnt++;
508 } else if (!isaggr && txok) {
509 /* transmit completion */
510 acked_cnt++;
511 } else if (tid->state & AGGR_CLEANUP) {
512 /*
513 * cleanup in progress, just fail
514 * the un-acked sub-frames
515 */
516 txfail = 1;
517 } else if (flush) {
518 txpending = 1;
519 } else if (fi->retries < ATH_MAX_SW_RETRIES) {
520 if (txok || !an->sleeping)
521 ath_tx_set_retry(sc, txq, bf->bf_mpdu,
522 retries);
523
524 txpending = 1;
525 } else {
526 txfail = 1;
527 txfail_cnt++;
528 bar_index = max_t(int, bar_index,
529 ATH_BA_INDEX(seq_first, seqno));
530 }
531
532 /*
533 * Make sure the last desc is reclaimed if it
534 * not a holding desc.
535 */
536 INIT_LIST_HEAD(&bf_head);
537 if (bf_next != NULL || !bf_last->bf_stale)
538 list_move_tail(&bf->list, &bf_head);
539
540 if (!txpending || (tid->state & AGGR_CLEANUP)) {
541 /*
542 * complete the acked-ones/xretried ones; update
543 * block-ack window
544 */
545 ath_tx_update_baw(sc, tid, seqno);
546
547 if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) {
548 memcpy(tx_info->control.rates, rates, sizeof(rates));
549 ath_tx_rc_status(sc, bf, ts, nframes, nbad, txok);
550 rc_update = false;
551 }
552
553 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts,
554 !txfail);
555 } else {
556 /* retry the un-acked ones */
557 if (bf->bf_next == NULL && bf_last->bf_stale) {
558 struct ath_buf *tbf;
559
560 tbf = ath_clone_txbuf(sc, bf_last);
561 /*
562 * Update tx baw and complete the
563 * frame with failed status if we
564 * run out of tx buf.
565 */
566 if (!tbf) {
567 ath_tx_update_baw(sc, tid, seqno);
568
569 ath_tx_complete_buf(sc, bf, txq,
570 &bf_head, ts, 0);
571 bar_index = max_t(int, bar_index,
572 ATH_BA_INDEX(seq_first, seqno));
573 break;
574 }
575
576 fi->bf = tbf;
577 }
578
579 /*
580 * Put this buffer to the temporary pending
581 * queue to retain ordering
582 */
583 __skb_queue_tail(&bf_pending, skb);
584 }
585
586 bf = bf_next;
587 }
588
589 /* prepend un-acked frames to the beginning of the pending frame queue */
590 if (!skb_queue_empty(&bf_pending)) {
591 if (an->sleeping)
592 ieee80211_sta_set_buffered(sta, tid->tidno, true);
593
594 skb_queue_splice(&bf_pending, &tid->buf_q);
595 if (!an->sleeping) {
596 ath_tx_queue_tid(txq, tid);
597
598 if (ts->ts_status & (ATH9K_TXERR_FILT | ATH9K_TXERR_XRETRY))
599 tid->ac->clear_ps_filter = true;
600 }
601 }
602
603 if (bar_index >= 0) {
604 u16 bar_seq = ATH_BA_INDEX2SEQ(seq_first, bar_index);
605
606 if (BAW_WITHIN(tid->seq_start, tid->baw_size, bar_seq))
607 tid->bar_index = ATH_BA_INDEX(tid->seq_start, bar_seq);
608
609 ath_txq_unlock(sc, txq);
610 ath_send_bar(tid, ATH_BA_INDEX2SEQ(seq_first, bar_index + 1));
611 ath_txq_lock(sc, txq);
612 }
613
614 if (tid->state & AGGR_CLEANUP)
615 ath_tx_flush_tid(sc, tid, false);
616
617 rcu_read_unlock();
618
619 if (needreset)
620 ath9k_queue_reset(sc, RESET_TYPE_TX_ERROR);
621 }
622
623 static bool bf_is_ampdu_not_probing(struct ath_buf *bf)
624 {
625 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(bf->bf_mpdu);
626 return bf_isampdu(bf) && !(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE);
627 }
628
629 static void ath_tx_process_buffer(struct ath_softc *sc, struct ath_txq *txq,
630 struct ath_tx_status *ts, struct ath_buf *bf,
631 struct list_head *bf_head)
632 {
633 bool txok, flush;
634
635 txok = !(ts->ts_status & ATH9K_TXERR_MASK);
636 flush = !!(ts->ts_status & ATH9K_TX_FLUSH);
637 txq->axq_tx_inprogress = false;
638
639 txq->axq_depth--;
640 if (bf_is_ampdu_not_probing(bf))
641 txq->axq_ampdu_depth--;
642
643 if (!bf_isampdu(bf)) {
644 if (!flush)
645 ath_tx_rc_status(sc, bf, ts, 1, txok ? 0 : 1, txok);
646 ath_tx_complete_buf(sc, bf, txq, bf_head, ts, txok);
647 } else
648 ath_tx_complete_aggr(sc, txq, bf, bf_head, ts, txok);
649
650 if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) && !flush)
651 ath_txq_schedule(sc, txq);
652 }
653
654 static bool ath_lookup_legacy(struct ath_buf *bf)
655 {
656 struct sk_buff *skb;
657 struct ieee80211_tx_info *tx_info;
658 struct ieee80211_tx_rate *rates;
659 int i;
660
661 skb = bf->bf_mpdu;
662 tx_info = IEEE80211_SKB_CB(skb);
663 rates = tx_info->control.rates;
664
665 for (i = 0; i < 4; i++) {
666 if (!rates[i].count || rates[i].idx < 0)
667 break;
668
669 if (!(rates[i].flags & IEEE80211_TX_RC_MCS))
670 return true;
671 }
672
673 return false;
674 }
675
676 static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf,
677 struct ath_atx_tid *tid)
678 {
679 struct sk_buff *skb;
680 struct ieee80211_tx_info *tx_info;
681 struct ieee80211_tx_rate *rates;
682 u32 max_4ms_framelen, frmlen;
683 u16 aggr_limit, bt_aggr_limit, legacy = 0;
684 int q = tid->ac->txq->mac80211_qnum;
685 int i;
686
687 skb = bf->bf_mpdu;
688 tx_info = IEEE80211_SKB_CB(skb);
689 rates = tx_info->control.rates;
690
691 /*
692 * Find the lowest frame length among the rate series that will have a
693 * 4ms (or TXOP limited) transmit duration.
694 */
695 max_4ms_framelen = ATH_AMPDU_LIMIT_MAX;
696
697 for (i = 0; i < 4; i++) {
698 int modeidx;
699
700 if (!rates[i].count)
701 continue;
702
703 if (!(rates[i].flags & IEEE80211_TX_RC_MCS)) {
704 legacy = 1;
705 break;
706 }
707
708 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
709 modeidx = MCS_HT40;
710 else
711 modeidx = MCS_HT20;
712
713 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
714 modeidx++;
715
716 frmlen = sc->tx.max_aggr_framelen[q][modeidx][rates[i].idx];
717 max_4ms_framelen = min(max_4ms_framelen, frmlen);
718 }
719
720 /*
721 * limit aggregate size by the minimum rate if rate selected is
722 * not a probe rate, if rate selected is a probe rate then
723 * avoid aggregation of this packet.
724 */
725 if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy)
726 return 0;
727
728 aggr_limit = min(max_4ms_framelen, (u32)ATH_AMPDU_LIMIT_MAX);
729
730 /*
731 * Override the default aggregation limit for BTCOEX.
732 */
733 bt_aggr_limit = ath9k_btcoex_aggr_limit(sc, max_4ms_framelen);
734 if (bt_aggr_limit)
735 aggr_limit = bt_aggr_limit;
736
737 /*
738 * h/w can accept aggregates up to 16 bit lengths (65535).
739 * The IE, however can hold up to 65536, which shows up here
740 * as zero. Ignore 65536 since we are constrained by hw.
741 */
742 if (tid->an->maxampdu)
743 aggr_limit = min(aggr_limit, tid->an->maxampdu);
744
745 return aggr_limit;
746 }
747
748 /*
749 * Returns the number of delimiters to be added to
750 * meet the minimum required mpdudensity.
751 */
752 static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid,
753 struct ath_buf *bf, u16 frmlen,
754 bool first_subfrm)
755 {
756 #define FIRST_DESC_NDELIMS 60
757 u32 nsymbits, nsymbols;
758 u16 minlen;
759 u8 flags, rix;
760 int width, streams, half_gi, ndelim, mindelim;
761 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
762
763 /* Select standard number of delimiters based on frame length alone */
764 ndelim = ATH_AGGR_GET_NDELIM(frmlen);
765
766 /*
767 * If encryption enabled, hardware requires some more padding between
768 * subframes.
769 * TODO - this could be improved to be dependent on the rate.
770 * The hardware can keep up at lower rates, but not higher rates
771 */
772 if ((fi->keyix != ATH9K_TXKEYIX_INVALID) &&
773 !(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA))
774 ndelim += ATH_AGGR_ENCRYPTDELIM;
775
776 /*
777 * Add delimiter when using RTS/CTS with aggregation
778 * and non enterprise AR9003 card
779 */
780 if (first_subfrm && !AR_SREV_9580_10_OR_LATER(sc->sc_ah) &&
781 (sc->sc_ah->ent_mode & AR_ENT_OTP_MIN_PKT_SIZE_DISABLE))
782 ndelim = max(ndelim, FIRST_DESC_NDELIMS);
783
784 /*
785 * Convert desired mpdu density from microeconds to bytes based
786 * on highest rate in rate series (i.e. first rate) to determine
787 * required minimum length for subframe. Take into account
788 * whether high rate is 20 or 40Mhz and half or full GI.
789 *
790 * If there is no mpdu density restriction, no further calculation
791 * is needed.
792 */
793
794 if (tid->an->mpdudensity == 0)
795 return ndelim;
796
797 rix = bf->rates[0].idx;
798 flags = bf->rates[0].flags;
799 width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0;
800 half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0;
801
802 if (half_gi)
803 nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(tid->an->mpdudensity);
804 else
805 nsymbols = NUM_SYMBOLS_PER_USEC(tid->an->mpdudensity);
806
807 if (nsymbols == 0)
808 nsymbols = 1;
809
810 streams = HT_RC_2_STREAMS(rix);
811 nsymbits = bits_per_symbol[rix % 8][width] * streams;
812 minlen = (nsymbols * nsymbits) / BITS_PER_BYTE;
813
814 if (frmlen < minlen) {
815 mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ;
816 ndelim = max(mindelim, ndelim);
817 }
818
819 return ndelim;
820 }
821
822 static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc,
823 struct ath_txq *txq,
824 struct ath_atx_tid *tid,
825 struct list_head *bf_q,
826 int *aggr_len)
827 {
828 #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
829 struct ath_buf *bf, *bf_first = NULL, *bf_prev = NULL;
830 int rl = 0, nframes = 0, ndelim, prev_al = 0;
831 u16 aggr_limit = 0, al = 0, bpad = 0,
832 al_delta, h_baw = tid->baw_size / 2;
833 enum ATH_AGGR_STATUS status = ATH_AGGR_DONE;
834 struct ieee80211_tx_info *tx_info;
835 struct ath_frame_info *fi;
836 struct sk_buff *skb;
837 u16 seqno;
838
839 do {
840 skb = skb_peek(&tid->buf_q);
841 fi = get_frame_info(skb);
842 bf = fi->bf;
843 if (!fi->bf)
844 bf = ath_tx_setup_buffer(sc, txq, tid, skb);
845
846 if (!bf) {
847 __skb_unlink(skb, &tid->buf_q);
848 ieee80211_free_txskb(sc->hw, skb);
849 continue;
850 }
851
852 bf->bf_state.bf_type = BUF_AMPDU | BUF_AGGR;
853 seqno = bf->bf_state.seqno;
854
855 /* do not step over block-ack window */
856 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno)) {
857 status = ATH_AGGR_BAW_CLOSED;
858 break;
859 }
860
861 if (tid->bar_index > ATH_BA_INDEX(tid->seq_start, seqno)) {
862 struct ath_tx_status ts = {};
863 struct list_head bf_head;
864
865 INIT_LIST_HEAD(&bf_head);
866 list_add(&bf->list, &bf_head);
867 __skb_unlink(skb, &tid->buf_q);
868 ath_tx_update_baw(sc, tid, seqno);
869 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0);
870 continue;
871 }
872
873 if (!bf_first)
874 bf_first = bf;
875
876 if (!rl) {
877 ath_set_rates(tid->an->vif, tid->an->sta, bf);
878 aggr_limit = ath_lookup_rate(sc, bf, tid);
879 rl = 1;
880 }
881
882 /* do not exceed aggregation limit */
883 al_delta = ATH_AGGR_DELIM_SZ + fi->framelen;
884
885 if (nframes &&
886 ((aggr_limit < (al + bpad + al_delta + prev_al)) ||
887 ath_lookup_legacy(bf))) {
888 status = ATH_AGGR_LIMITED;
889 break;
890 }
891
892 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
893 if (nframes && (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE))
894 break;
895
896 /* do not exceed subframe limit */
897 if (nframes >= min((int)h_baw, ATH_AMPDU_SUBFRAME_DEFAULT)) {
898 status = ATH_AGGR_LIMITED;
899 break;
900 }
901
902 /* add padding for previous frame to aggregation length */
903 al += bpad + al_delta;
904
905 /*
906 * Get the delimiters needed to meet the MPDU
907 * density for this node.
908 */
909 ndelim = ath_compute_num_delims(sc, tid, bf_first, fi->framelen,
910 !nframes);
911 bpad = PADBYTES(al_delta) + (ndelim << 2);
912
913 nframes++;
914 bf->bf_next = NULL;
915
916 /* link buffers of this frame to the aggregate */
917 if (!fi->retries)
918 ath_tx_addto_baw(sc, tid, seqno);
919 bf->bf_state.ndelim = ndelim;
920
921 __skb_unlink(skb, &tid->buf_q);
922 list_add_tail(&bf->list, bf_q);
923 if (bf_prev)
924 bf_prev->bf_next = bf;
925
926 bf_prev = bf;
927
928 } while (!skb_queue_empty(&tid->buf_q));
929
930 *aggr_len = al;
931
932 return status;
933 #undef PADBYTES
934 }
935
936 /*
937 * rix - rate index
938 * pktlen - total bytes (delims + data + fcs + pads + pad delims)
939 * width - 0 for 20 MHz, 1 for 40 MHz
940 * half_gi - to use 4us v/s 3.6 us for symbol time
941 */
942 static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, int pktlen,
943 int width, int half_gi, bool shortPreamble)
944 {
945 u32 nbits, nsymbits, duration, nsymbols;
946 int streams;
947
948 /* find number of symbols: PLCP + data */
949 streams = HT_RC_2_STREAMS(rix);
950 nbits = (pktlen << 3) + OFDM_PLCP_BITS;
951 nsymbits = bits_per_symbol[rix % 8][width] * streams;
952 nsymbols = (nbits + nsymbits - 1) / nsymbits;
953
954 if (!half_gi)
955 duration = SYMBOL_TIME(nsymbols);
956 else
957 duration = SYMBOL_TIME_HALFGI(nsymbols);
958
959 /* addup duration for legacy/ht training and signal fields */
960 duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
961
962 return duration;
963 }
964
965 static int ath_max_framelen(int usec, int mcs, bool ht40, bool sgi)
966 {
967 int streams = HT_RC_2_STREAMS(mcs);
968 int symbols, bits;
969 int bytes = 0;
970
971 symbols = sgi ? TIME_SYMBOLS_HALFGI(usec) : TIME_SYMBOLS(usec);
972 bits = symbols * bits_per_symbol[mcs % 8][ht40] * streams;
973 bits -= OFDM_PLCP_BITS;
974 bytes = bits / 8;
975 bytes -= L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
976 if (bytes > 65532)
977 bytes = 65532;
978
979 return bytes;
980 }
981
982 void ath_update_max_aggr_framelen(struct ath_softc *sc, int queue, int txop)
983 {
984 u16 *cur_ht20, *cur_ht20_sgi, *cur_ht40, *cur_ht40_sgi;
985 int mcs;
986
987 /* 4ms is the default (and maximum) duration */
988 if (!txop || txop > 4096)
989 txop = 4096;
990
991 cur_ht20 = sc->tx.max_aggr_framelen[queue][MCS_HT20];
992 cur_ht20_sgi = sc->tx.max_aggr_framelen[queue][MCS_HT20_SGI];
993 cur_ht40 = sc->tx.max_aggr_framelen[queue][MCS_HT40];
994 cur_ht40_sgi = sc->tx.max_aggr_framelen[queue][MCS_HT40_SGI];
995 for (mcs = 0; mcs < 32; mcs++) {
996 cur_ht20[mcs] = ath_max_framelen(txop, mcs, false, false);
997 cur_ht20_sgi[mcs] = ath_max_framelen(txop, mcs, false, true);
998 cur_ht40[mcs] = ath_max_framelen(txop, mcs, true, false);
999 cur_ht40_sgi[mcs] = ath_max_framelen(txop, mcs, true, true);
1000 }
1001 }
1002
1003 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf,
1004 struct ath_tx_info *info, int len)
1005 {
1006 struct ath_hw *ah = sc->sc_ah;
1007 struct sk_buff *skb;
1008 struct ieee80211_tx_info *tx_info;
1009 struct ieee80211_tx_rate *rates;
1010 const struct ieee80211_rate *rate;
1011 struct ieee80211_hdr *hdr;
1012 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
1013 int i;
1014 u8 rix = 0;
1015
1016 skb = bf->bf_mpdu;
1017 tx_info = IEEE80211_SKB_CB(skb);
1018 rates = bf->rates;
1019 hdr = (struct ieee80211_hdr *)skb->data;
1020
1021 /* set dur_update_en for l-sig computation except for PS-Poll frames */
1022 info->dur_update = !ieee80211_is_pspoll(hdr->frame_control);
1023 info->rtscts_rate = fi->rtscts_rate;
1024
1025 for (i = 0; i < ARRAY_SIZE(bf->rates); i++) {
1026 bool is_40, is_sgi, is_sp;
1027 int phy;
1028
1029 if (!rates[i].count || (rates[i].idx < 0))
1030 continue;
1031
1032 rix = rates[i].idx;
1033 info->rates[i].Tries = rates[i].count;
1034
1035 if (rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS) {
1036 info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1037 info->flags |= ATH9K_TXDESC_RTSENA;
1038 } else if (rates[i].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
1039 info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1040 info->flags |= ATH9K_TXDESC_CTSENA;
1041 }
1042
1043 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
1044 info->rates[i].RateFlags |= ATH9K_RATESERIES_2040;
1045 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
1046 info->rates[i].RateFlags |= ATH9K_RATESERIES_HALFGI;
1047
1048 is_sgi = !!(rates[i].flags & IEEE80211_TX_RC_SHORT_GI);
1049 is_40 = !!(rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH);
1050 is_sp = !!(rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE);
1051
1052 if (rates[i].flags & IEEE80211_TX_RC_MCS) {
1053 /* MCS rates */
1054 info->rates[i].Rate = rix | 0x80;
1055 info->rates[i].ChSel = ath_txchainmask_reduction(sc,
1056 ah->txchainmask, info->rates[i].Rate);
1057 info->rates[i].PktDuration = ath_pkt_duration(sc, rix, len,
1058 is_40, is_sgi, is_sp);
1059 if (rix < 8 && (tx_info->flags & IEEE80211_TX_CTL_STBC))
1060 info->rates[i].RateFlags |= ATH9K_RATESERIES_STBC;
1061 continue;
1062 }
1063
1064 /* legacy rates */
1065 rate = &sc->sbands[tx_info->band].bitrates[rates[i].idx];
1066 if ((tx_info->band == IEEE80211_BAND_2GHZ) &&
1067 !(rate->flags & IEEE80211_RATE_ERP_G))
1068 phy = WLAN_RC_PHY_CCK;
1069 else
1070 phy = WLAN_RC_PHY_OFDM;
1071
1072 info->rates[i].Rate = rate->hw_value;
1073 if (rate->hw_value_short) {
1074 if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
1075 info->rates[i].Rate |= rate->hw_value_short;
1076 } else {
1077 is_sp = false;
1078 }
1079
1080 if (bf->bf_state.bfs_paprd)
1081 info->rates[i].ChSel = ah->txchainmask;
1082 else
1083 info->rates[i].ChSel = ath_txchainmask_reduction(sc,
1084 ah->txchainmask, info->rates[i].Rate);
1085
1086 info->rates[i].PktDuration = ath9k_hw_computetxtime(sc->sc_ah,
1087 phy, rate->bitrate * 100, len, rix, is_sp);
1088 }
1089
1090 /* For AR5416 - RTS cannot be followed by a frame larger than 8K */
1091 if (bf_isaggr(bf) && (len > sc->sc_ah->caps.rts_aggr_limit))
1092 info->flags &= ~ATH9K_TXDESC_RTSENA;
1093
1094 /* ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive. */
1095 if (info->flags & ATH9K_TXDESC_RTSENA)
1096 info->flags &= ~ATH9K_TXDESC_CTSENA;
1097 }
1098
1099 static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb)
1100 {
1101 struct ieee80211_hdr *hdr;
1102 enum ath9k_pkt_type htype;
1103 __le16 fc;
1104
1105 hdr = (struct ieee80211_hdr *)skb->data;
1106 fc = hdr->frame_control;
1107
1108 if (ieee80211_is_beacon(fc))
1109 htype = ATH9K_PKT_TYPE_BEACON;
1110 else if (ieee80211_is_probe_resp(fc))
1111 htype = ATH9K_PKT_TYPE_PROBE_RESP;
1112 else if (ieee80211_is_atim(fc))
1113 htype = ATH9K_PKT_TYPE_ATIM;
1114 else if (ieee80211_is_pspoll(fc))
1115 htype = ATH9K_PKT_TYPE_PSPOLL;
1116 else
1117 htype = ATH9K_PKT_TYPE_NORMAL;
1118
1119 return htype;
1120 }
1121
1122 static void ath_tx_fill_desc(struct ath_softc *sc, struct ath_buf *bf,
1123 struct ath_txq *txq, int len)
1124 {
1125 struct ath_hw *ah = sc->sc_ah;
1126 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
1127 struct ath_buf *bf_first = bf;
1128 struct ath_tx_info info;
1129 bool aggr = !!(bf->bf_state.bf_type & BUF_AGGR);
1130
1131 memset(&info, 0, sizeof(info));
1132 info.is_first = true;
1133 info.is_last = true;
1134 info.txpower = MAX_RATE_POWER;
1135 info.qcu = txq->axq_qnum;
1136
1137 info.flags = ATH9K_TXDESC_INTREQ;
1138 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
1139 info.flags |= ATH9K_TXDESC_NOACK;
1140 if (tx_info->flags & IEEE80211_TX_CTL_LDPC)
1141 info.flags |= ATH9K_TXDESC_LDPC;
1142
1143 ath_buf_set_rate(sc, bf, &info, len);
1144
1145 if (tx_info->flags & IEEE80211_TX_CTL_CLEAR_PS_FILT)
1146 info.flags |= ATH9K_TXDESC_CLRDMASK;
1147
1148 if (bf->bf_state.bfs_paprd)
1149 info.flags |= (u32) bf->bf_state.bfs_paprd << ATH9K_TXDESC_PAPRD_S;
1150
1151
1152 while (bf) {
1153 struct sk_buff *skb = bf->bf_mpdu;
1154 struct ath_frame_info *fi = get_frame_info(skb);
1155
1156 info.type = get_hw_packet_type(skb);
1157 if (bf->bf_next)
1158 info.link = bf->bf_next->bf_daddr;
1159 else
1160 info.link = 0;
1161
1162 info.buf_addr[0] = bf->bf_buf_addr;
1163 info.buf_len[0] = skb->len;
1164 info.pkt_len = fi->framelen;
1165 info.keyix = fi->keyix;
1166 info.keytype = fi->keytype;
1167
1168 if (aggr) {
1169 if (bf == bf_first)
1170 info.aggr = AGGR_BUF_FIRST;
1171 else if (!bf->bf_next)
1172 info.aggr = AGGR_BUF_LAST;
1173 else
1174 info.aggr = AGGR_BUF_MIDDLE;
1175
1176 info.ndelim = bf->bf_state.ndelim;
1177 info.aggr_len = len;
1178 }
1179
1180 ath9k_hw_set_txdesc(ah, bf->bf_desc, &info);
1181 bf = bf->bf_next;
1182 }
1183 }
1184
1185 static void ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq,
1186 struct ath_atx_tid *tid)
1187 {
1188 struct ath_buf *bf;
1189 enum ATH_AGGR_STATUS status;
1190 struct ieee80211_tx_info *tx_info;
1191 struct list_head bf_q;
1192 int aggr_len;
1193
1194 do {
1195 if (skb_queue_empty(&tid->buf_q))
1196 return;
1197
1198 INIT_LIST_HEAD(&bf_q);
1199
1200 status = ath_tx_form_aggr(sc, txq, tid, &bf_q, &aggr_len);
1201
1202 /*
1203 * no frames picked up to be aggregated;
1204 * block-ack window is not open.
1205 */
1206 if (list_empty(&bf_q))
1207 break;
1208
1209 bf = list_first_entry(&bf_q, struct ath_buf, list);
1210 bf->bf_lastbf = list_entry(bf_q.prev, struct ath_buf, list);
1211 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
1212
1213 if (tid->ac->clear_ps_filter) {
1214 tid->ac->clear_ps_filter = false;
1215 tx_info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT;
1216 } else {
1217 tx_info->flags &= ~IEEE80211_TX_CTL_CLEAR_PS_FILT;
1218 }
1219
1220 /* if only one frame, send as non-aggregate */
1221 if (bf == bf->bf_lastbf) {
1222 aggr_len = get_frame_info(bf->bf_mpdu)->framelen;
1223 bf->bf_state.bf_type = BUF_AMPDU;
1224 } else {
1225 TX_STAT_INC(txq->axq_qnum, a_aggr);
1226 }
1227
1228 ath_tx_fill_desc(sc, bf, txq, aggr_len);
1229 ath_tx_txqaddbuf(sc, txq, &bf_q, false);
1230 } while (txq->axq_ampdu_depth < ATH_AGGR_MIN_QDEPTH &&
1231 status != ATH_AGGR_BAW_CLOSED);
1232 }
1233
1234 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
1235 u16 tid, u16 *ssn)
1236 {
1237 struct ath_atx_tid *txtid;
1238 struct ath_node *an;
1239 u8 density;
1240
1241 an = (struct ath_node *)sta->drv_priv;
1242 txtid = ATH_AN_2_TID(an, tid);
1243
1244 if (txtid->state & (AGGR_CLEANUP | AGGR_ADDBA_COMPLETE))
1245 return -EAGAIN;
1246
1247 /* update ampdu factor/density, they may have changed. This may happen
1248 * in HT IBSS when a beacon with HT-info is received after the station
1249 * has already been added.
1250 */
1251 if (sta->ht_cap.ht_supported) {
1252 an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
1253 sta->ht_cap.ampdu_factor);
1254 density = ath9k_parse_mpdudensity(sta->ht_cap.ampdu_density);
1255 an->mpdudensity = density;
1256 }
1257
1258 txtid->state |= AGGR_ADDBA_PROGRESS;
1259 txtid->paused = true;
1260 *ssn = txtid->seq_start = txtid->seq_next;
1261 txtid->bar_index = -1;
1262
1263 memset(txtid->tx_buf, 0, sizeof(txtid->tx_buf));
1264 txtid->baw_head = txtid->baw_tail = 0;
1265
1266 return 0;
1267 }
1268
1269 bool ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid,
1270 bool flush)
1271 {
1272 struct ath_node *an = (struct ath_node *)sta->drv_priv;
1273 struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid);
1274 struct ath_txq *txq = txtid->ac->txq;
1275 bool ret = !flush;
1276
1277 if (flush)
1278 txtid->stop_cb = false;
1279
1280 if (txtid->state & AGGR_CLEANUP)
1281 return false;
1282
1283 if (!(txtid->state & AGGR_ADDBA_COMPLETE)) {
1284 txtid->state &= ~AGGR_ADDBA_PROGRESS;
1285 return ret;
1286 }
1287
1288 ath_txq_lock(sc, txq);
1289 txtid->paused = true;
1290
1291 /*
1292 * If frames are still being transmitted for this TID, they will be
1293 * cleaned up during tx completion. To prevent race conditions, this
1294 * TID can only be reused after all in-progress subframes have been
1295 * completed.
1296 */
1297 if (txtid->baw_head != txtid->baw_tail) {
1298 txtid->state |= AGGR_CLEANUP;
1299 ret = false;
1300 txtid->stop_cb = !flush;
1301 } else {
1302 txtid->state &= ~AGGR_ADDBA_COMPLETE;
1303 }
1304
1305 ath_tx_flush_tid(sc, txtid, flush);
1306 ath_txq_unlock_complete(sc, txq);
1307 return ret;
1308 }
1309
1310 void ath_tx_aggr_sleep(struct ieee80211_sta *sta, struct ath_softc *sc,
1311 struct ath_node *an)
1312 {
1313 struct ath_atx_tid *tid;
1314 struct ath_atx_ac *ac;
1315 struct ath_txq *txq;
1316 bool buffered;
1317 int tidno;
1318
1319 for (tidno = 0, tid = &an->tid[tidno];
1320 tidno < IEEE80211_NUM_TIDS; tidno++, tid++) {
1321
1322 if (!tid->sched)
1323 continue;
1324
1325 ac = tid->ac;
1326 txq = ac->txq;
1327
1328 ath_txq_lock(sc, txq);
1329
1330 buffered = !skb_queue_empty(&tid->buf_q);
1331
1332 tid->sched = false;
1333 list_del(&tid->list);
1334
1335 if (ac->sched) {
1336 ac->sched = false;
1337 list_del(&ac->list);
1338 }
1339
1340 ath_txq_unlock(sc, txq);
1341
1342 ieee80211_sta_set_buffered(sta, tidno, buffered);
1343 }
1344 }
1345
1346 void ath_tx_aggr_wakeup(struct ath_softc *sc, struct ath_node *an)
1347 {
1348 struct ath_atx_tid *tid;
1349 struct ath_atx_ac *ac;
1350 struct ath_txq *txq;
1351 int tidno;
1352
1353 for (tidno = 0, tid = &an->tid[tidno];
1354 tidno < IEEE80211_NUM_TIDS; tidno++, tid++) {
1355
1356 ac = tid->ac;
1357 txq = ac->txq;
1358
1359 ath_txq_lock(sc, txq);
1360 ac->clear_ps_filter = true;
1361
1362 if (!skb_queue_empty(&tid->buf_q) && !tid->paused) {
1363 ath_tx_queue_tid(txq, tid);
1364 ath_txq_schedule(sc, txq);
1365 }
1366
1367 ath_txq_unlock_complete(sc, txq);
1368 }
1369 }
1370
1371 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
1372 {
1373 struct ath_atx_tid *txtid;
1374 struct ath_node *an;
1375
1376 an = (struct ath_node *)sta->drv_priv;
1377
1378 txtid = ATH_AN_2_TID(an, tid);
1379 txtid->baw_size = IEEE80211_MIN_AMPDU_BUF << sta->ht_cap.ampdu_factor;
1380 txtid->state |= AGGR_ADDBA_COMPLETE;
1381 txtid->state &= ~AGGR_ADDBA_PROGRESS;
1382 ath_tx_resume_tid(sc, txtid);
1383 }
1384
1385 /********************/
1386 /* Queue Management */
1387 /********************/
1388
1389 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
1390 {
1391 struct ath_hw *ah = sc->sc_ah;
1392 struct ath9k_tx_queue_info qi;
1393 static const int subtype_txq_to_hwq[] = {
1394 [IEEE80211_AC_BE] = ATH_TXQ_AC_BE,
1395 [IEEE80211_AC_BK] = ATH_TXQ_AC_BK,
1396 [IEEE80211_AC_VI] = ATH_TXQ_AC_VI,
1397 [IEEE80211_AC_VO] = ATH_TXQ_AC_VO,
1398 };
1399 int axq_qnum, i;
1400
1401 memset(&qi, 0, sizeof(qi));
1402 qi.tqi_subtype = subtype_txq_to_hwq[subtype];
1403 qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT;
1404 qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
1405 qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT;
1406 qi.tqi_physCompBuf = 0;
1407
1408 /*
1409 * Enable interrupts only for EOL and DESC conditions.
1410 * We mark tx descriptors to receive a DESC interrupt
1411 * when a tx queue gets deep; otherwise waiting for the
1412 * EOL to reap descriptors. Note that this is done to
1413 * reduce interrupt load and this only defers reaping
1414 * descriptors, never transmitting frames. Aside from
1415 * reducing interrupts this also permits more concurrency.
1416 * The only potential downside is if the tx queue backs
1417 * up in which case the top half of the kernel may backup
1418 * due to a lack of tx descriptors.
1419 *
1420 * The UAPSD queue is an exception, since we take a desc-
1421 * based intr on the EOSP frames.
1422 */
1423 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1424 qi.tqi_qflags = TXQ_FLAG_TXINT_ENABLE;
1425 } else {
1426 if (qtype == ATH9K_TX_QUEUE_UAPSD)
1427 qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE;
1428 else
1429 qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE |
1430 TXQ_FLAG_TXDESCINT_ENABLE;
1431 }
1432 axq_qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi);
1433 if (axq_qnum == -1) {
1434 /*
1435 * NB: don't print a message, this happens
1436 * normally on parts with too few tx queues
1437 */
1438 return NULL;
1439 }
1440 if (!ATH_TXQ_SETUP(sc, axq_qnum)) {
1441 struct ath_txq *txq = &sc->tx.txq[axq_qnum];
1442
1443 txq->axq_qnum = axq_qnum;
1444 txq->mac80211_qnum = -1;
1445 txq->axq_link = NULL;
1446 __skb_queue_head_init(&txq->complete_q);
1447 INIT_LIST_HEAD(&txq->axq_q);
1448 INIT_LIST_HEAD(&txq->axq_acq);
1449 spin_lock_init(&txq->axq_lock);
1450 txq->axq_depth = 0;
1451 txq->axq_ampdu_depth = 0;
1452 txq->axq_tx_inprogress = false;
1453 sc->tx.txqsetup |= 1<<axq_qnum;
1454
1455 txq->txq_headidx = txq->txq_tailidx = 0;
1456 for (i = 0; i < ATH_TXFIFO_DEPTH; i++)
1457 INIT_LIST_HEAD(&txq->txq_fifo[i]);
1458 }
1459 return &sc->tx.txq[axq_qnum];
1460 }
1461
1462 int ath_txq_update(struct ath_softc *sc, int qnum,
1463 struct ath9k_tx_queue_info *qinfo)
1464 {
1465 struct ath_hw *ah = sc->sc_ah;
1466 int error = 0;
1467 struct ath9k_tx_queue_info qi;
1468
1469 BUG_ON(sc->tx.txq[qnum].axq_qnum != qnum);
1470
1471 ath9k_hw_get_txq_props(ah, qnum, &qi);
1472 qi.tqi_aifs = qinfo->tqi_aifs;
1473 qi.tqi_cwmin = qinfo->tqi_cwmin;
1474 qi.tqi_cwmax = qinfo->tqi_cwmax;
1475 qi.tqi_burstTime = qinfo->tqi_burstTime;
1476 qi.tqi_readyTime = qinfo->tqi_readyTime;
1477
1478 if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) {
1479 ath_err(ath9k_hw_common(sc->sc_ah),
1480 "Unable to update hardware queue %u!\n", qnum);
1481 error = -EIO;
1482 } else {
1483 ath9k_hw_resettxqueue(ah, qnum);
1484 }
1485
1486 return error;
1487 }
1488
1489 int ath_cabq_update(struct ath_softc *sc)
1490 {
1491 struct ath9k_tx_queue_info qi;
1492 struct ath_beacon_config *cur_conf = &sc->cur_beacon_conf;
1493 int qnum = sc->beacon.cabq->axq_qnum;
1494
1495 ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi);
1496 /*
1497 * Ensure the readytime % is within the bounds.
1498 */
1499 if (sc->config.cabqReadytime < ATH9K_READY_TIME_LO_BOUND)
1500 sc->config.cabqReadytime = ATH9K_READY_TIME_LO_BOUND;
1501 else if (sc->config.cabqReadytime > ATH9K_READY_TIME_HI_BOUND)
1502 sc->config.cabqReadytime = ATH9K_READY_TIME_HI_BOUND;
1503
1504 qi.tqi_readyTime = (cur_conf->beacon_interval *
1505 sc->config.cabqReadytime) / 100;
1506 ath_txq_update(sc, qnum, &qi);
1507
1508 return 0;
1509 }
1510
1511 static void ath_drain_txq_list(struct ath_softc *sc, struct ath_txq *txq,
1512 struct list_head *list)
1513 {
1514 struct ath_buf *bf, *lastbf;
1515 struct list_head bf_head;
1516 struct ath_tx_status ts;
1517
1518 memset(&ts, 0, sizeof(ts));
1519 ts.ts_status = ATH9K_TX_FLUSH;
1520 INIT_LIST_HEAD(&bf_head);
1521
1522 while (!list_empty(list)) {
1523 bf = list_first_entry(list, struct ath_buf, list);
1524
1525 if (bf->bf_stale) {
1526 list_del(&bf->list);
1527
1528 ath_tx_return_buffer(sc, bf);
1529 continue;
1530 }
1531
1532 lastbf = bf->bf_lastbf;
1533 list_cut_position(&bf_head, list, &lastbf->list);
1534 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
1535 }
1536 }
1537
1538 /*
1539 * Drain a given TX queue (could be Beacon or Data)
1540 *
1541 * This assumes output has been stopped and
1542 * we do not need to block ath_tx_tasklet.
1543 */
1544 void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq)
1545 {
1546 ath_txq_lock(sc, txq);
1547
1548 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1549 int idx = txq->txq_tailidx;
1550
1551 while (!list_empty(&txq->txq_fifo[idx])) {
1552 ath_drain_txq_list(sc, txq, &txq->txq_fifo[idx]);
1553
1554 INCR(idx, ATH_TXFIFO_DEPTH);
1555 }
1556 txq->txq_tailidx = idx;
1557 }
1558
1559 txq->axq_link = NULL;
1560 txq->axq_tx_inprogress = false;
1561 ath_drain_txq_list(sc, txq, &txq->axq_q);
1562
1563 ath_txq_unlock_complete(sc, txq);
1564 }
1565
1566 bool ath_drain_all_txq(struct ath_softc *sc)
1567 {
1568 struct ath_hw *ah = sc->sc_ah;
1569 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1570 struct ath_txq *txq;
1571 int i;
1572 u32 npend = 0;
1573
1574 if (test_bit(SC_OP_INVALID, &sc->sc_flags))
1575 return true;
1576
1577 ath9k_hw_abort_tx_dma(ah);
1578
1579 /* Check if any queue remains active */
1580 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1581 if (!ATH_TXQ_SETUP(sc, i))
1582 continue;
1583
1584 if (ath9k_hw_numtxpending(ah, sc->tx.txq[i].axq_qnum))
1585 npend |= BIT(i);
1586 }
1587
1588 if (npend)
1589 ath_err(common, "Failed to stop TX DMA, queues=0x%03x!\n", npend);
1590
1591 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1592 if (!ATH_TXQ_SETUP(sc, i))
1593 continue;
1594
1595 /*
1596 * The caller will resume queues with ieee80211_wake_queues.
1597 * Mark the queue as not stopped to prevent ath_tx_complete
1598 * from waking the queue too early.
1599 */
1600 txq = &sc->tx.txq[i];
1601 txq->stopped = false;
1602 ath_draintxq(sc, txq);
1603 }
1604
1605 return !npend;
1606 }
1607
1608 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
1609 {
1610 ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum);
1611 sc->tx.txqsetup &= ~(1<<txq->axq_qnum);
1612 }
1613
1614 /* For each axq_acq entry, for each tid, try to schedule packets
1615 * for transmit until ampdu_depth has reached min Q depth.
1616 */
1617 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq)
1618 {
1619 struct ath_atx_ac *ac, *ac_tmp, *last_ac;
1620 struct ath_atx_tid *tid, *last_tid;
1621
1622 if (test_bit(SC_OP_HW_RESET, &sc->sc_flags) ||
1623 list_empty(&txq->axq_acq) ||
1624 txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH)
1625 return;
1626
1627 ac = list_first_entry(&txq->axq_acq, struct ath_atx_ac, list);
1628 last_ac = list_entry(txq->axq_acq.prev, struct ath_atx_ac, list);
1629
1630 list_for_each_entry_safe(ac, ac_tmp, &txq->axq_acq, list) {
1631 last_tid = list_entry(ac->tid_q.prev, struct ath_atx_tid, list);
1632 list_del(&ac->list);
1633 ac->sched = false;
1634
1635 while (!list_empty(&ac->tid_q)) {
1636 tid = list_first_entry(&ac->tid_q, struct ath_atx_tid,
1637 list);
1638 list_del(&tid->list);
1639 tid->sched = false;
1640
1641 if (tid->paused)
1642 continue;
1643
1644 ath_tx_sched_aggr(sc, txq, tid);
1645
1646 /*
1647 * add tid to round-robin queue if more frames
1648 * are pending for the tid
1649 */
1650 if (!skb_queue_empty(&tid->buf_q))
1651 ath_tx_queue_tid(txq, tid);
1652
1653 if (tid == last_tid ||
1654 txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH)
1655 break;
1656 }
1657
1658 if (!list_empty(&ac->tid_q) && !ac->sched) {
1659 ac->sched = true;
1660 list_add_tail(&ac->list, &txq->axq_acq);
1661 }
1662
1663 if (ac == last_ac ||
1664 txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH)
1665 return;
1666 }
1667 }
1668
1669 /***********/
1670 /* TX, DMA */
1671 /***********/
1672
1673 /*
1674 * Insert a chain of ath_buf (descriptors) on a txq and
1675 * assume the descriptors are already chained together by caller.
1676 */
1677 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
1678 struct list_head *head, bool internal)
1679 {
1680 struct ath_hw *ah = sc->sc_ah;
1681 struct ath_common *common = ath9k_hw_common(ah);
1682 struct ath_buf *bf, *bf_last;
1683 bool puttxbuf = false;
1684 bool edma;
1685
1686 /*
1687 * Insert the frame on the outbound list and
1688 * pass it on to the hardware.
1689 */
1690
1691 if (list_empty(head))
1692 return;
1693
1694 edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
1695 bf = list_first_entry(head, struct ath_buf, list);
1696 bf_last = list_entry(head->prev, struct ath_buf, list);
1697
1698 ath_dbg(common, QUEUE, "qnum: %d, txq depth: %d\n",
1699 txq->axq_qnum, txq->axq_depth);
1700
1701 if (edma && list_empty(&txq->txq_fifo[txq->txq_headidx])) {
1702 list_splice_tail_init(head, &txq->txq_fifo[txq->txq_headidx]);
1703 INCR(txq->txq_headidx, ATH_TXFIFO_DEPTH);
1704 puttxbuf = true;
1705 } else {
1706 list_splice_tail_init(head, &txq->axq_q);
1707
1708 if (txq->axq_link) {
1709 ath9k_hw_set_desc_link(ah, txq->axq_link, bf->bf_daddr);
1710 ath_dbg(common, XMIT, "link[%u] (%p)=%llx (%p)\n",
1711 txq->axq_qnum, txq->axq_link,
1712 ito64(bf->bf_daddr), bf->bf_desc);
1713 } else if (!edma)
1714 puttxbuf = true;
1715
1716 txq->axq_link = bf_last->bf_desc;
1717 }
1718
1719 if (puttxbuf) {
1720 TX_STAT_INC(txq->axq_qnum, puttxbuf);
1721 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
1722 ath_dbg(common, XMIT, "TXDP[%u] = %llx (%p)\n",
1723 txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc);
1724 }
1725
1726 if (!edma) {
1727 TX_STAT_INC(txq->axq_qnum, txstart);
1728 ath9k_hw_txstart(ah, txq->axq_qnum);
1729 }
1730
1731 if (!internal) {
1732 txq->axq_depth++;
1733 if (bf_is_ampdu_not_probing(bf))
1734 txq->axq_ampdu_depth++;
1735 }
1736 }
1737
1738 static void ath_tx_send_ampdu(struct ath_softc *sc, struct ath_atx_tid *tid,
1739 struct sk_buff *skb, struct ath_tx_control *txctl)
1740 {
1741 struct ath_frame_info *fi = get_frame_info(skb);
1742 struct list_head bf_head;
1743 struct ath_buf *bf;
1744
1745 /*
1746 * Do not queue to h/w when any of the following conditions is true:
1747 * - there are pending frames in software queue
1748 * - the TID is currently paused for ADDBA/BAR request
1749 * - seqno is not within block-ack window
1750 * - h/w queue depth exceeds low water mark
1751 */
1752 if (!skb_queue_empty(&tid->buf_q) || tid->paused ||
1753 !BAW_WITHIN(tid->seq_start, tid->baw_size, tid->seq_next) ||
1754 txctl->txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH) {
1755 /*
1756 * Add this frame to software queue for scheduling later
1757 * for aggregation.
1758 */
1759 TX_STAT_INC(txctl->txq->axq_qnum, a_queued_sw);
1760 __skb_queue_tail(&tid->buf_q, skb);
1761 if (!txctl->an || !txctl->an->sleeping)
1762 ath_tx_queue_tid(txctl->txq, tid);
1763 return;
1764 }
1765
1766 bf = ath_tx_setup_buffer(sc, txctl->txq, tid, skb);
1767 if (!bf) {
1768 ieee80211_free_txskb(sc->hw, skb);
1769 return;
1770 }
1771
1772 ath_set_rates(tid->an->vif, tid->an->sta, bf);
1773 bf->bf_state.bf_type = BUF_AMPDU;
1774 INIT_LIST_HEAD(&bf_head);
1775 list_add(&bf->list, &bf_head);
1776
1777 /* Add sub-frame to BAW */
1778 ath_tx_addto_baw(sc, tid, bf->bf_state.seqno);
1779
1780 /* Queue to h/w without aggregation */
1781 TX_STAT_INC(txctl->txq->axq_qnum, a_queued_hw);
1782 bf->bf_lastbf = bf;
1783 ath_tx_fill_desc(sc, bf, txctl->txq, fi->framelen);
1784 ath_tx_txqaddbuf(sc, txctl->txq, &bf_head, false);
1785 }
1786
1787 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
1788 struct ath_atx_tid *tid, struct sk_buff *skb)
1789 {
1790 struct ath_frame_info *fi = get_frame_info(skb);
1791 struct list_head bf_head;
1792 struct ath_buf *bf;
1793
1794 bf = fi->bf;
1795
1796 INIT_LIST_HEAD(&bf_head);
1797 list_add_tail(&bf->list, &bf_head);
1798 bf->bf_state.bf_type = 0;
1799
1800 bf->bf_next = NULL;
1801 bf->bf_lastbf = bf;
1802 ath_tx_fill_desc(sc, bf, txq, fi->framelen);
1803 ath_tx_txqaddbuf(sc, txq, &bf_head, false);
1804 TX_STAT_INC(txq->axq_qnum, queued);
1805 }
1806
1807 static void setup_frame_info(struct ieee80211_hw *hw,
1808 struct ieee80211_sta *sta,
1809 struct sk_buff *skb,
1810 int framelen)
1811 {
1812 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1813 struct ieee80211_key_conf *hw_key = tx_info->control.hw_key;
1814 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1815 const struct ieee80211_rate *rate;
1816 struct ath_frame_info *fi = get_frame_info(skb);
1817 struct ath_node *an = NULL;
1818 enum ath9k_key_type keytype;
1819 bool short_preamble = false;
1820
1821 /*
1822 * We check if Short Preamble is needed for the CTS rate by
1823 * checking the BSS's global flag.
1824 * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used.
1825 */
1826 if (tx_info->control.vif &&
1827 tx_info->control.vif->bss_conf.use_short_preamble)
1828 short_preamble = true;
1829
1830 rate = ieee80211_get_rts_cts_rate(hw, tx_info);
1831 keytype = ath9k_cmn_get_hw_crypto_keytype(skb);
1832
1833 if (sta)
1834 an = (struct ath_node *) sta->drv_priv;
1835
1836 memset(fi, 0, sizeof(*fi));
1837 if (hw_key)
1838 fi->keyix = hw_key->hw_key_idx;
1839 else if (an && ieee80211_is_data(hdr->frame_control) && an->ps_key > 0)
1840 fi->keyix = an->ps_key;
1841 else
1842 fi->keyix = ATH9K_TXKEYIX_INVALID;
1843 fi->keytype = keytype;
1844 fi->framelen = framelen;
1845 fi->rtscts_rate = rate->hw_value;
1846 if (short_preamble)
1847 fi->rtscts_rate |= rate->hw_value_short;
1848 }
1849
1850 u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate)
1851 {
1852 struct ath_hw *ah = sc->sc_ah;
1853 struct ath9k_channel *curchan = ah->curchan;
1854
1855 if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) &&
1856 (curchan->channelFlags & CHANNEL_5GHZ) &&
1857 (chainmask == 0x7) && (rate < 0x90))
1858 return 0x3;
1859 else if (AR_SREV_9462(ah) && ath9k_hw_btcoex_is_enabled(ah) &&
1860 IS_CCK_RATE(rate))
1861 return 0x2;
1862 else
1863 return chainmask;
1864 }
1865
1866 /*
1867 * Assign a descriptor (and sequence number if necessary,
1868 * and map buffer for DMA. Frees skb on error
1869 */
1870 static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc,
1871 struct ath_txq *txq,
1872 struct ath_atx_tid *tid,
1873 struct sk_buff *skb)
1874 {
1875 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1876 struct ath_frame_info *fi = get_frame_info(skb);
1877 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1878 struct ath_buf *bf;
1879 int fragno;
1880 u16 seqno;
1881
1882 bf = ath_tx_get_buffer(sc);
1883 if (!bf) {
1884 ath_dbg(common, XMIT, "TX buffers are full\n");
1885 return NULL;
1886 }
1887
1888 ATH_TXBUF_RESET(bf);
1889
1890 if (tid) {
1891 fragno = le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG;
1892 seqno = tid->seq_next;
1893 hdr->seq_ctrl = cpu_to_le16(tid->seq_next << IEEE80211_SEQ_SEQ_SHIFT);
1894
1895 if (fragno)
1896 hdr->seq_ctrl |= cpu_to_le16(fragno);
1897
1898 if (!ieee80211_has_morefrags(hdr->frame_control))
1899 INCR(tid->seq_next, IEEE80211_SEQ_MAX);
1900
1901 bf->bf_state.seqno = seqno;
1902 }
1903
1904 bf->bf_mpdu = skb;
1905
1906 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
1907 skb->len, DMA_TO_DEVICE);
1908 if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) {
1909 bf->bf_mpdu = NULL;
1910 bf->bf_buf_addr = 0;
1911 ath_err(ath9k_hw_common(sc->sc_ah),
1912 "dma_mapping_error() on TX\n");
1913 ath_tx_return_buffer(sc, bf);
1914 return NULL;
1915 }
1916
1917 fi->bf = bf;
1918
1919 return bf;
1920 }
1921
1922 /* Upon failure caller should free skb */
1923 int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
1924 struct ath_tx_control *txctl)
1925 {
1926 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
1927 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1928 struct ieee80211_sta *sta = txctl->sta;
1929 struct ieee80211_vif *vif = info->control.vif;
1930 struct ath_softc *sc = hw->priv;
1931 struct ath_txq *txq = txctl->txq;
1932 struct ath_atx_tid *tid = NULL;
1933 struct ath_buf *bf;
1934 int padpos, padsize;
1935 int frmlen = skb->len + FCS_LEN;
1936 u8 tidno;
1937 int q;
1938
1939 /* NOTE: sta can be NULL according to net/mac80211.h */
1940 if (sta)
1941 txctl->an = (struct ath_node *)sta->drv_priv;
1942
1943 if (info->control.hw_key)
1944 frmlen += info->control.hw_key->icv_len;
1945
1946 /*
1947 * As a temporary workaround, assign seq# here; this will likely need
1948 * to be cleaned up to work better with Beacon transmission and virtual
1949 * BSSes.
1950 */
1951 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1952 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
1953 sc->tx.seq_no += 0x10;
1954 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
1955 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
1956 }
1957
1958 /* Add the padding after the header if this is not already done */
1959 padpos = ieee80211_hdrlen(hdr->frame_control);
1960 padsize = padpos & 3;
1961 if (padsize && skb->len > padpos) {
1962 if (skb_headroom(skb) < padsize)
1963 return -ENOMEM;
1964
1965 skb_push(skb, padsize);
1966 memmove(skb->data, skb->data + padsize, padpos);
1967 hdr = (struct ieee80211_hdr *) skb->data;
1968 }
1969
1970 if ((vif && vif->type != NL80211_IFTYPE_AP &&
1971 vif->type != NL80211_IFTYPE_AP_VLAN) ||
1972 !ieee80211_is_data(hdr->frame_control))
1973 info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT;
1974
1975 setup_frame_info(hw, sta, skb, frmlen);
1976
1977 /*
1978 * At this point, the vif, hw_key and sta pointers in the tx control
1979 * info are no longer valid (overwritten by the ath_frame_info data.
1980 */
1981
1982 q = skb_get_queue_mapping(skb);
1983
1984 ath_txq_lock(sc, txq);
1985 if (txq == sc->tx.txq_map[q] &&
1986 ++txq->pending_frames > sc->tx.txq_max_pending[q] &&
1987 !txq->stopped) {
1988 ieee80211_stop_queue(sc->hw, q);
1989 txq->stopped = true;
1990 }
1991
1992 if (txctl->an && ieee80211_is_data_qos(hdr->frame_control)) {
1993 tidno = ieee80211_get_qos_ctl(hdr)[0] &
1994 IEEE80211_QOS_CTL_TID_MASK;
1995 tid = ATH_AN_2_TID(txctl->an, tidno);
1996
1997 WARN_ON(tid->ac->txq != txctl->txq);
1998 }
1999
2000 if ((info->flags & IEEE80211_TX_CTL_AMPDU) && tid) {
2001 /*
2002 * Try aggregation if it's a unicast data frame
2003 * and the destination is HT capable.
2004 */
2005 ath_tx_send_ampdu(sc, tid, skb, txctl);
2006 goto out;
2007 }
2008
2009 bf = ath_tx_setup_buffer(sc, txctl->txq, tid, skb);
2010 if (!bf) {
2011 if (txctl->paprd)
2012 dev_kfree_skb_any(skb);
2013 else
2014 ieee80211_free_txskb(sc->hw, skb);
2015 goto out;
2016 }
2017
2018 bf->bf_state.bfs_paprd = txctl->paprd;
2019
2020 if (txctl->paprd)
2021 bf->bf_state.bfs_paprd_timestamp = jiffies;
2022
2023 ath_set_rates(vif, sta, bf);
2024 ath_tx_send_normal(sc, txctl->txq, tid, skb);
2025
2026 out:
2027 ath_txq_unlock(sc, txq);
2028
2029 return 0;
2030 }
2031
2032 /*****************/
2033 /* TX Completion */
2034 /*****************/
2035
2036 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
2037 int tx_flags, struct ath_txq *txq)
2038 {
2039 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2040 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2041 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data;
2042 int q, padpos, padsize;
2043 unsigned long flags;
2044
2045 ath_dbg(common, XMIT, "TX complete: skb: %p\n", skb);
2046
2047 if (sc->sc_ah->caldata)
2048 sc->sc_ah->caldata->paprd_packet_sent = true;
2049
2050 if (!(tx_flags & ATH_TX_ERROR))
2051 /* Frame was ACKed */
2052 tx_info->flags |= IEEE80211_TX_STAT_ACK;
2053
2054 padpos = ieee80211_hdrlen(hdr->frame_control);
2055 padsize = padpos & 3;
2056 if (padsize && skb->len>padpos+padsize) {
2057 /*
2058 * Remove MAC header padding before giving the frame back to
2059 * mac80211.
2060 */
2061 memmove(skb->data + padsize, skb->data, padpos);
2062 skb_pull(skb, padsize);
2063 }
2064
2065 spin_lock_irqsave(&sc->sc_pm_lock, flags);
2066 if ((sc->ps_flags & PS_WAIT_FOR_TX_ACK) && !txq->axq_depth) {
2067 sc->ps_flags &= ~PS_WAIT_FOR_TX_ACK;
2068 ath_dbg(common, PS,
2069 "Going back to sleep after having received TX status (0x%lx)\n",
2070 sc->ps_flags & (PS_WAIT_FOR_BEACON |
2071 PS_WAIT_FOR_CAB |
2072 PS_WAIT_FOR_PSPOLL_DATA |
2073 PS_WAIT_FOR_TX_ACK));
2074 }
2075 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
2076
2077 q = skb_get_queue_mapping(skb);
2078 if (txq == sc->tx.txq_map[q]) {
2079 if (WARN_ON(--txq->pending_frames < 0))
2080 txq->pending_frames = 0;
2081
2082 if (txq->stopped &&
2083 txq->pending_frames < sc->tx.txq_max_pending[q]) {
2084 ieee80211_wake_queue(sc->hw, q);
2085 txq->stopped = false;
2086 }
2087 }
2088
2089 __skb_queue_tail(&txq->complete_q, skb);
2090 }
2091
2092 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
2093 struct ath_txq *txq, struct list_head *bf_q,
2094 struct ath_tx_status *ts, int txok)
2095 {
2096 struct sk_buff *skb = bf->bf_mpdu;
2097 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2098 unsigned long flags;
2099 int tx_flags = 0;
2100
2101 if (!txok)
2102 tx_flags |= ATH_TX_ERROR;
2103
2104 if (ts->ts_status & ATH9K_TXERR_FILT)
2105 tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
2106
2107 dma_unmap_single(sc->dev, bf->bf_buf_addr, skb->len, DMA_TO_DEVICE);
2108 bf->bf_buf_addr = 0;
2109
2110 if (bf->bf_state.bfs_paprd) {
2111 if (time_after(jiffies,
2112 bf->bf_state.bfs_paprd_timestamp +
2113 msecs_to_jiffies(ATH_PAPRD_TIMEOUT)))
2114 dev_kfree_skb_any(skb);
2115 else
2116 complete(&sc->paprd_complete);
2117 } else {
2118 ath_debug_stat_tx(sc, bf, ts, txq, tx_flags);
2119 ath_tx_complete(sc, skb, tx_flags, txq);
2120 }
2121 /* At this point, skb (bf->bf_mpdu) is consumed...make sure we don't
2122 * accidentally reference it later.
2123 */
2124 bf->bf_mpdu = NULL;
2125
2126 /*
2127 * Return the list of ath_buf of this mpdu to free queue
2128 */
2129 spin_lock_irqsave(&sc->tx.txbuflock, flags);
2130 list_splice_tail_init(bf_q, &sc->tx.txbuf);
2131 spin_unlock_irqrestore(&sc->tx.txbuflock, flags);
2132 }
2133
2134 static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
2135 struct ath_tx_status *ts, int nframes, int nbad,
2136 int txok)
2137 {
2138 struct sk_buff *skb = bf->bf_mpdu;
2139 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
2140 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2141 struct ieee80211_hw *hw = sc->hw;
2142 struct ath_hw *ah = sc->sc_ah;
2143 u8 i, tx_rateindex;
2144
2145 if (txok)
2146 tx_info->status.ack_signal = ts->ts_rssi;
2147
2148 tx_rateindex = ts->ts_rateindex;
2149 WARN_ON(tx_rateindex >= hw->max_rates);
2150
2151 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
2152 tx_info->flags |= IEEE80211_TX_STAT_AMPDU;
2153
2154 BUG_ON(nbad > nframes);
2155 }
2156 tx_info->status.ampdu_len = nframes;
2157 tx_info->status.ampdu_ack_len = nframes - nbad;
2158
2159 if ((ts->ts_status & ATH9K_TXERR_FILT) == 0 &&
2160 (tx_info->flags & IEEE80211_TX_CTL_NO_ACK) == 0) {
2161 /*
2162 * If an underrun error is seen assume it as an excessive
2163 * retry only if max frame trigger level has been reached
2164 * (2 KB for single stream, and 4 KB for dual stream).
2165 * Adjust the long retry as if the frame was tried
2166 * hw->max_rate_tries times to affect how rate control updates
2167 * PER for the failed rate.
2168 * In case of congestion on the bus penalizing this type of
2169 * underruns should help hardware actually transmit new frames
2170 * successfully by eventually preferring slower rates.
2171 * This itself should also alleviate congestion on the bus.
2172 */
2173 if (unlikely(ts->ts_flags & (ATH9K_TX_DATA_UNDERRUN |
2174 ATH9K_TX_DELIM_UNDERRUN)) &&
2175 ieee80211_is_data(hdr->frame_control) &&
2176 ah->tx_trig_level >= sc->sc_ah->config.max_txtrig_level)
2177 tx_info->status.rates[tx_rateindex].count =
2178 hw->max_rate_tries;
2179 }
2180
2181 for (i = tx_rateindex + 1; i < hw->max_rates; i++) {
2182 tx_info->status.rates[i].count = 0;
2183 tx_info->status.rates[i].idx = -1;
2184 }
2185
2186 tx_info->status.rates[tx_rateindex].count = ts->ts_longretry + 1;
2187 }
2188
2189 static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
2190 {
2191 struct ath_hw *ah = sc->sc_ah;
2192 struct ath_common *common = ath9k_hw_common(ah);
2193 struct ath_buf *bf, *lastbf, *bf_held = NULL;
2194 struct list_head bf_head;
2195 struct ath_desc *ds;
2196 struct ath_tx_status ts;
2197 int status;
2198
2199 ath_dbg(common, QUEUE, "tx queue %d (%x), link %p\n",
2200 txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum),
2201 txq->axq_link);
2202
2203 ath_txq_lock(sc, txq);
2204 for (;;) {
2205 if (test_bit(SC_OP_HW_RESET, &sc->sc_flags))
2206 break;
2207
2208 if (list_empty(&txq->axq_q)) {
2209 txq->axq_link = NULL;
2210 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
2211 ath_txq_schedule(sc, txq);
2212 break;
2213 }
2214 bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
2215
2216 /*
2217 * There is a race condition that a BH gets scheduled
2218 * after sw writes TxE and before hw re-load the last
2219 * descriptor to get the newly chained one.
2220 * Software must keep the last DONE descriptor as a
2221 * holding descriptor - software does so by marking
2222 * it with the STALE flag.
2223 */
2224 bf_held = NULL;
2225 if (bf->bf_stale) {
2226 bf_held = bf;
2227 if (list_is_last(&bf_held->list, &txq->axq_q))
2228 break;
2229
2230 bf = list_entry(bf_held->list.next, struct ath_buf,
2231 list);
2232 }
2233
2234 lastbf = bf->bf_lastbf;
2235 ds = lastbf->bf_desc;
2236
2237 memset(&ts, 0, sizeof(ts));
2238 status = ath9k_hw_txprocdesc(ah, ds, &ts);
2239 if (status == -EINPROGRESS)
2240 break;
2241
2242 TX_STAT_INC(txq->axq_qnum, txprocdesc);
2243
2244 /*
2245 * Remove ath_buf's of the same transmit unit from txq,
2246 * however leave the last descriptor back as the holding
2247 * descriptor for hw.
2248 */
2249 lastbf->bf_stale = true;
2250 INIT_LIST_HEAD(&bf_head);
2251 if (!list_is_singular(&lastbf->list))
2252 list_cut_position(&bf_head,
2253 &txq->axq_q, lastbf->list.prev);
2254
2255 if (bf_held) {
2256 list_del(&bf_held->list);
2257 ath_tx_return_buffer(sc, bf_held);
2258 }
2259
2260 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
2261 }
2262 ath_txq_unlock_complete(sc, txq);
2263 }
2264
2265 void ath_tx_tasklet(struct ath_softc *sc)
2266 {
2267 struct ath_hw *ah = sc->sc_ah;
2268 u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1) & ah->intr_txqs;
2269 int i;
2270
2271 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2272 if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i)))
2273 ath_tx_processq(sc, &sc->tx.txq[i]);
2274 }
2275 }
2276
2277 void ath_tx_edma_tasklet(struct ath_softc *sc)
2278 {
2279 struct ath_tx_status ts;
2280 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2281 struct ath_hw *ah = sc->sc_ah;
2282 struct ath_txq *txq;
2283 struct ath_buf *bf, *lastbf;
2284 struct list_head bf_head;
2285 struct list_head *fifo_list;
2286 int status;
2287
2288 for (;;) {
2289 if (test_bit(SC_OP_HW_RESET, &sc->sc_flags))
2290 break;
2291
2292 status = ath9k_hw_txprocdesc(ah, NULL, (void *)&ts);
2293 if (status == -EINPROGRESS)
2294 break;
2295 if (status == -EIO) {
2296 ath_dbg(common, XMIT, "Error processing tx status\n");
2297 break;
2298 }
2299
2300 /* Process beacon completions separately */
2301 if (ts.qid == sc->beacon.beaconq) {
2302 sc->beacon.tx_processed = true;
2303 sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
2304 continue;
2305 }
2306
2307 txq = &sc->tx.txq[ts.qid];
2308
2309 ath_txq_lock(sc, txq);
2310
2311 TX_STAT_INC(txq->axq_qnum, txprocdesc);
2312
2313 fifo_list = &txq->txq_fifo[txq->txq_tailidx];
2314 if (list_empty(fifo_list)) {
2315 ath_txq_unlock(sc, txq);
2316 return;
2317 }
2318
2319 bf = list_first_entry(fifo_list, struct ath_buf, list);
2320 if (bf->bf_stale) {
2321 list_del(&bf->list);
2322 ath_tx_return_buffer(sc, bf);
2323 bf = list_first_entry(fifo_list, struct ath_buf, list);
2324 }
2325
2326 lastbf = bf->bf_lastbf;
2327
2328 INIT_LIST_HEAD(&bf_head);
2329 if (list_is_last(&lastbf->list, fifo_list)) {
2330 list_splice_tail_init(fifo_list, &bf_head);
2331 INCR(txq->txq_tailidx, ATH_TXFIFO_DEPTH);
2332
2333 if (!list_empty(&txq->axq_q)) {
2334 struct list_head bf_q;
2335
2336 INIT_LIST_HEAD(&bf_q);
2337 txq->axq_link = NULL;
2338 list_splice_tail_init(&txq->axq_q, &bf_q);
2339 ath_tx_txqaddbuf(sc, txq, &bf_q, true);
2340 }
2341 } else {
2342 lastbf->bf_stale = true;
2343 if (bf != lastbf)
2344 list_cut_position(&bf_head, fifo_list,
2345 lastbf->list.prev);
2346 }
2347
2348 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
2349 ath_txq_unlock_complete(sc, txq);
2350 }
2351 }
2352
2353 /*****************/
2354 /* Init, Cleanup */
2355 /*****************/
2356
2357 static int ath_txstatus_setup(struct ath_softc *sc, int size)
2358 {
2359 struct ath_descdma *dd = &sc->txsdma;
2360 u8 txs_len = sc->sc_ah->caps.txs_len;
2361
2362 dd->dd_desc_len = size * txs_len;
2363 dd->dd_desc = dmam_alloc_coherent(sc->dev, dd->dd_desc_len,
2364 &dd->dd_desc_paddr, GFP_KERNEL);
2365 if (!dd->dd_desc)
2366 return -ENOMEM;
2367
2368 return 0;
2369 }
2370
2371 static int ath_tx_edma_init(struct ath_softc *sc)
2372 {
2373 int err;
2374
2375 err = ath_txstatus_setup(sc, ATH_TXSTATUS_RING_SIZE);
2376 if (!err)
2377 ath9k_hw_setup_statusring(sc->sc_ah, sc->txsdma.dd_desc,
2378 sc->txsdma.dd_desc_paddr,
2379 ATH_TXSTATUS_RING_SIZE);
2380
2381 return err;
2382 }
2383
2384 int ath_tx_init(struct ath_softc *sc, int nbufs)
2385 {
2386 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2387 int error = 0;
2388
2389 spin_lock_init(&sc->tx.txbuflock);
2390
2391 error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf,
2392 "tx", nbufs, 1, 1);
2393 if (error != 0) {
2394 ath_err(common,
2395 "Failed to allocate tx descriptors: %d\n", error);
2396 return error;
2397 }
2398
2399 error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf,
2400 "beacon", ATH_BCBUF, 1, 1);
2401 if (error != 0) {
2402 ath_err(common,
2403 "Failed to allocate beacon descriptors: %d\n", error);
2404 return error;
2405 }
2406
2407 INIT_DELAYED_WORK(&sc->tx_complete_work, ath_tx_complete_poll_work);
2408
2409 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
2410 error = ath_tx_edma_init(sc);
2411
2412 return error;
2413 }
2414
2415 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an)
2416 {
2417 struct ath_atx_tid *tid;
2418 struct ath_atx_ac *ac;
2419 int tidno, acno;
2420
2421 for (tidno = 0, tid = &an->tid[tidno];
2422 tidno < IEEE80211_NUM_TIDS;
2423 tidno++, tid++) {
2424 tid->an = an;
2425 tid->tidno = tidno;
2426 tid->seq_start = tid->seq_next = 0;
2427 tid->baw_size = WME_MAX_BA;
2428 tid->baw_head = tid->baw_tail = 0;
2429 tid->sched = false;
2430 tid->paused = false;
2431 tid->state &= ~AGGR_CLEANUP;
2432 __skb_queue_head_init(&tid->buf_q);
2433 acno = TID_TO_WME_AC(tidno);
2434 tid->ac = &an->ac[acno];
2435 tid->state &= ~AGGR_ADDBA_COMPLETE;
2436 tid->state &= ~AGGR_ADDBA_PROGRESS;
2437 tid->stop_cb = false;
2438 }
2439
2440 for (acno = 0, ac = &an->ac[acno];
2441 acno < IEEE80211_NUM_ACS; acno++, ac++) {
2442 ac->sched = false;
2443 ac->txq = sc->tx.txq_map[acno];
2444 INIT_LIST_HEAD(&ac->tid_q);
2445 }
2446 }
2447
2448 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an)
2449 {
2450 struct ath_atx_ac *ac;
2451 struct ath_atx_tid *tid;
2452 struct ath_txq *txq;
2453 int tidno;
2454
2455 for (tidno = 0, tid = &an->tid[tidno];
2456 tidno < IEEE80211_NUM_TIDS; tidno++, tid++) {
2457
2458 ac = tid->ac;
2459 txq = ac->txq;
2460
2461 ath_txq_lock(sc, txq);
2462
2463 if (tid->sched) {
2464 list_del(&tid->list);
2465 tid->sched = false;
2466 }
2467
2468 if (ac->sched) {
2469 list_del(&ac->list);
2470 tid->ac->sched = false;
2471 }
2472
2473 ath_tid_drain(sc, txq, tid);
2474 ath_tx_clear_tid(sc, tid);
2475
2476 ath_txq_unlock(sc, txq);
2477 }
2478 }
Linux kernel - Deliverables
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