2 * Copyright (c) 2008-2009 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 #include "ar9003_mac.h"
20 #define BITS_PER_BYTE 8
21 #define OFDM_PLCP_BITS 22
22 #define HT_RC_2_MCS(_rc) ((_rc) & 0x1f)
23 #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
29 #define HT_LTF(_ns) (4 * (_ns))
30 #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */
31 #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */
32 #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
33 #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
35 #define OFDM_SIFS_TIME 16
37 static u16 bits_per_symbol
[][2] = {
39 { 26, 54 }, /* 0: BPSK */
40 { 52, 108 }, /* 1: QPSK 1/2 */
41 { 78, 162 }, /* 2: QPSK 3/4 */
42 { 104, 216 }, /* 3: 16-QAM 1/2 */
43 { 156, 324 }, /* 4: 16-QAM 3/4 */
44 { 208, 432 }, /* 5: 64-QAM 2/3 */
45 { 234, 486 }, /* 6: 64-QAM 3/4 */
46 { 260, 540 }, /* 7: 64-QAM 5/6 */
49 #define IS_HT_RATE(_rate) ((_rate) & 0x80)
51 static void ath_tx_send_ht_normal(struct ath_softc
*sc
, struct ath_txq
*txq
,
52 struct ath_atx_tid
*tid
,
53 struct list_head
*bf_head
);
54 static void ath_tx_complete_buf(struct ath_softc
*sc
, struct ath_buf
*bf
,
55 struct ath_txq
*txq
, struct list_head
*bf_q
,
56 struct ath_tx_status
*ts
, int txok
, int sendbar
);
57 static void ath_tx_txqaddbuf(struct ath_softc
*sc
, struct ath_txq
*txq
,
58 struct list_head
*head
);
59 static void ath_buf_set_rate(struct ath_softc
*sc
, struct ath_buf
*bf
);
60 static int ath_tx_num_badfrms(struct ath_softc
*sc
, struct ath_buf
*bf
,
61 struct ath_tx_status
*ts
, int txok
);
62 static void ath_tx_rc_status(struct ath_buf
*bf
, struct ath_tx_status
*ts
,
63 int nbad
, int txok
, bool update_rc
);
72 static int ath_max_4ms_framelen
[4][32] = {
74 3212, 6432, 9648, 12864, 19300, 25736, 28952, 32172,
75 6424, 12852, 19280, 25708, 38568, 51424, 57852, 64280,
76 9628, 19260, 28896, 38528, 57792, 65532, 65532, 65532,
77 12828, 25656, 38488, 51320, 65532, 65532, 65532, 65532,
80 3572, 7144, 10720, 14296, 21444, 28596, 32172, 35744,
81 7140, 14284, 21428, 28568, 42856, 57144, 64288, 65532,
82 10700, 21408, 32112, 42816, 64228, 65532, 65532, 65532,
83 14256, 28516, 42780, 57040, 65532, 65532, 65532, 65532,
86 6680, 13360, 20044, 26724, 40092, 53456, 60140, 65532,
87 13348, 26700, 40052, 53400, 65532, 65532, 65532, 65532,
88 20004, 40008, 60016, 65532, 65532, 65532, 65532, 65532,
89 26644, 53292, 65532, 65532, 65532, 65532, 65532, 65532,
92 7420, 14844, 22272, 29696, 44544, 59396, 65532, 65532,
93 14832, 29668, 44504, 59340, 65532, 65532, 65532, 65532,
94 22232, 44464, 65532, 65532, 65532, 65532, 65532, 65532,
95 29616, 59232, 65532, 65532, 65532, 65532, 65532, 65532,
99 /*********************/
100 /* Aggregation logic */
101 /*********************/
103 static void ath_tx_queue_tid(struct ath_txq
*txq
, struct ath_atx_tid
*tid
)
105 struct ath_atx_ac
*ac
= tid
->ac
;
114 list_add_tail(&tid
->list
, &ac
->tid_q
);
120 list_add_tail(&ac
->list
, &txq
->axq_acq
);
123 static void ath_tx_pause_tid(struct ath_softc
*sc
, struct ath_atx_tid
*tid
)
125 struct ath_txq
*txq
= &sc
->tx
.txq
[tid
->ac
->qnum
];
127 spin_lock_bh(&txq
->axq_lock
);
129 spin_unlock_bh(&txq
->axq_lock
);
132 static void ath_tx_resume_tid(struct ath_softc
*sc
, struct ath_atx_tid
*tid
)
134 struct ath_txq
*txq
= &sc
->tx
.txq
[tid
->ac
->qnum
];
136 BUG_ON(tid
->paused
<= 0);
137 spin_lock_bh(&txq
->axq_lock
);
144 if (list_empty(&tid
->buf_q
))
147 ath_tx_queue_tid(txq
, tid
);
148 ath_txq_schedule(sc
, txq
);
150 spin_unlock_bh(&txq
->axq_lock
);
153 static void ath_tx_flush_tid(struct ath_softc
*sc
, struct ath_atx_tid
*tid
)
155 struct ath_txq
*txq
= &sc
->tx
.txq
[tid
->ac
->qnum
];
157 struct list_head bf_head
;
158 INIT_LIST_HEAD(&bf_head
);
160 BUG_ON(tid
->paused
<= 0);
161 spin_lock_bh(&txq
->axq_lock
);
165 if (tid
->paused
> 0) {
166 spin_unlock_bh(&txq
->axq_lock
);
170 while (!list_empty(&tid
->buf_q
)) {
171 bf
= list_first_entry(&tid
->buf_q
, struct ath_buf
, list
);
172 BUG_ON(bf_isretried(bf
));
173 list_move_tail(&bf
->list
, &bf_head
);
174 ath_tx_send_ht_normal(sc
, txq
, tid
, &bf_head
);
177 spin_unlock_bh(&txq
->axq_lock
);
180 static void ath_tx_update_baw(struct ath_softc
*sc
, struct ath_atx_tid
*tid
,
185 index
= ATH_BA_INDEX(tid
->seq_start
, seqno
);
186 cindex
= (tid
->baw_head
+ index
) & (ATH_TID_MAX_BUFS
- 1);
188 tid
->tx_buf
[cindex
] = NULL
;
190 while (tid
->baw_head
!= tid
->baw_tail
&& !tid
->tx_buf
[tid
->baw_head
]) {
191 INCR(tid
->seq_start
, IEEE80211_SEQ_MAX
);
192 INCR(tid
->baw_head
, ATH_TID_MAX_BUFS
);
196 static void ath_tx_addto_baw(struct ath_softc
*sc
, struct ath_atx_tid
*tid
,
201 if (bf_isretried(bf
))
204 index
= ATH_BA_INDEX(tid
->seq_start
, bf
->bf_seqno
);
205 cindex
= (tid
->baw_head
+ index
) & (ATH_TID_MAX_BUFS
- 1);
207 BUG_ON(tid
->tx_buf
[cindex
] != NULL
);
208 tid
->tx_buf
[cindex
] = bf
;
210 if (index
>= ((tid
->baw_tail
- tid
->baw_head
) &
211 (ATH_TID_MAX_BUFS
- 1))) {
212 tid
->baw_tail
= cindex
;
213 INCR(tid
->baw_tail
, ATH_TID_MAX_BUFS
);
218 * TODO: For frame(s) that are in the retry state, we will reuse the
219 * sequence number(s) without setting the retry bit. The
220 * alternative is to give up on these and BAR the receiver's window
223 static void ath_tid_drain(struct ath_softc
*sc
, struct ath_txq
*txq
,
224 struct ath_atx_tid
*tid
)
228 struct list_head bf_head
;
229 struct ath_tx_status ts
;
231 memset(&ts
, 0, sizeof(ts
));
232 INIT_LIST_HEAD(&bf_head
);
235 if (list_empty(&tid
->buf_q
))
238 bf
= list_first_entry(&tid
->buf_q
, struct ath_buf
, list
);
239 list_move_tail(&bf
->list
, &bf_head
);
241 if (bf_isretried(bf
))
242 ath_tx_update_baw(sc
, tid
, bf
->bf_seqno
);
244 spin_unlock(&txq
->axq_lock
);
245 ath_tx_complete_buf(sc
, bf
, txq
, &bf_head
, &ts
, 0, 0);
246 spin_lock(&txq
->axq_lock
);
249 tid
->seq_next
= tid
->seq_start
;
250 tid
->baw_tail
= tid
->baw_head
;
253 static void ath_tx_set_retry(struct ath_softc
*sc
, struct ath_txq
*txq
,
257 struct ieee80211_hdr
*hdr
;
259 bf
->bf_state
.bf_type
|= BUF_RETRY
;
261 TX_STAT_INC(txq
->axq_qnum
, a_retries
);
264 hdr
= (struct ieee80211_hdr
*)skb
->data
;
265 hdr
->frame_control
|= cpu_to_le16(IEEE80211_FCTL_RETRY
);
268 static struct ath_buf
*ath_tx_get_buffer(struct ath_softc
*sc
)
270 struct ath_buf
*bf
= NULL
;
272 spin_lock_bh(&sc
->tx
.txbuflock
);
274 if (unlikely(list_empty(&sc
->tx
.txbuf
))) {
275 spin_unlock_bh(&sc
->tx
.txbuflock
);
279 bf
= list_first_entry(&sc
->tx
.txbuf
, struct ath_buf
, list
);
282 spin_unlock_bh(&sc
->tx
.txbuflock
);
287 static void ath_tx_return_buffer(struct ath_softc
*sc
, struct ath_buf
*bf
)
289 spin_lock_bh(&sc
->tx
.txbuflock
);
290 list_add_tail(&bf
->list
, &sc
->tx
.txbuf
);
291 spin_unlock_bh(&sc
->tx
.txbuflock
);
294 static struct ath_buf
* ath_clone_txbuf(struct ath_softc
*sc
, struct ath_buf
*bf
)
298 tbf
= ath_tx_get_buffer(sc
);
302 ATH_TXBUF_RESET(tbf
);
304 tbf
->aphy
= bf
->aphy
;
305 tbf
->bf_mpdu
= bf
->bf_mpdu
;
306 tbf
->bf_buf_addr
= bf
->bf_buf_addr
;
307 memcpy(tbf
->bf_desc
, bf
->bf_desc
, sc
->sc_ah
->caps
.tx_desc_len
);
308 tbf
->bf_state
= bf
->bf_state
;
309 tbf
->bf_dmacontext
= bf
->bf_dmacontext
;
314 static void ath_tx_complete_aggr(struct ath_softc
*sc
, struct ath_txq
*txq
,
315 struct ath_buf
*bf
, struct list_head
*bf_q
,
316 struct ath_tx_status
*ts
, int txok
)
318 struct ath_node
*an
= NULL
;
320 struct ieee80211_sta
*sta
;
321 struct ieee80211_hw
*hw
;
322 struct ieee80211_hdr
*hdr
;
323 struct ieee80211_tx_info
*tx_info
;
324 struct ath_atx_tid
*tid
= NULL
;
325 struct ath_buf
*bf_next
, *bf_last
= bf
->bf_lastbf
;
326 struct list_head bf_head
, bf_pending
;
327 u16 seq_st
= 0, acked_cnt
= 0, txfail_cnt
= 0;
328 u32 ba
[WME_BA_BMP_SIZE
>> 5];
329 int isaggr
, txfail
, txpending
, sendbar
= 0, needreset
= 0, nbad
= 0;
330 bool rc_update
= true;
331 struct ieee80211_tx_rate rates
[4];
334 hdr
= (struct ieee80211_hdr
*)skb
->data
;
336 tx_info
= IEEE80211_SKB_CB(skb
);
339 memcpy(rates
, tx_info
->control
.rates
, sizeof(rates
));
343 /* XXX: use ieee80211_find_sta! */
344 sta
= ieee80211_find_sta_by_hw(hw
, hdr
->addr1
);
350 an
= (struct ath_node
*)sta
->drv_priv
;
351 tid
= ATH_AN_2_TID(an
, bf
->bf_tidno
);
353 isaggr
= bf_isaggr(bf
);
354 memset(ba
, 0, WME_BA_BMP_SIZE
>> 3);
356 if (isaggr
&& txok
) {
357 if (ts
->ts_flags
& ATH9K_TX_BA
) {
358 seq_st
= ts
->ts_seqnum
;
359 memcpy(ba
, &ts
->ba_low
, WME_BA_BMP_SIZE
>> 3);
362 * AR5416 can become deaf/mute when BA
363 * issue happens. Chip needs to be reset.
364 * But AP code may have sychronization issues
365 * when perform internal reset in this routine.
366 * Only enable reset in STA mode for now.
368 if (sc
->sc_ah
->opmode
== NL80211_IFTYPE_STATION
)
373 INIT_LIST_HEAD(&bf_pending
);
374 INIT_LIST_HEAD(&bf_head
);
376 nbad
= ath_tx_num_badfrms(sc
, bf
, ts
, txok
);
378 txfail
= txpending
= 0;
379 bf_next
= bf
->bf_next
;
382 tx_info
= IEEE80211_SKB_CB(skb
);
384 if (ATH_BA_ISSET(ba
, ATH_BA_INDEX(seq_st
, bf
->bf_seqno
))) {
385 /* transmit completion, subframe is
386 * acked by block ack */
388 } else if (!isaggr
&& txok
) {
389 /* transmit completion */
392 if (!(tid
->state
& AGGR_CLEANUP
) &&
393 !bf_last
->bf_tx_aborted
) {
394 if (bf
->bf_retries
< ATH_MAX_SW_RETRIES
) {
395 ath_tx_set_retry(sc
, txq
, bf
);
398 bf
->bf_state
.bf_type
|= BUF_XRETRY
;
405 * cleanup in progress, just fail
406 * the un-acked sub-frames
412 if (!(sc
->sc_ah
->caps
.hw_caps
& ATH9K_HW_CAP_EDMA
) &&
415 * Make sure the last desc is reclaimed if it
416 * not a holding desc.
418 if (!bf_last
->bf_stale
)
419 list_move_tail(&bf
->list
, &bf_head
);
421 INIT_LIST_HEAD(&bf_head
);
423 BUG_ON(list_empty(bf_q
));
424 list_move_tail(&bf
->list
, &bf_head
);
429 * complete the acked-ones/xretried ones; update
432 spin_lock_bh(&txq
->axq_lock
);
433 ath_tx_update_baw(sc
, tid
, bf
->bf_seqno
);
434 spin_unlock_bh(&txq
->axq_lock
);
436 if (rc_update
&& (acked_cnt
== 1 || txfail_cnt
== 1)) {
437 memcpy(tx_info
->control
.rates
, rates
, sizeof(rates
));
438 ath_tx_rc_status(bf
, ts
, nbad
, txok
, true);
441 ath_tx_rc_status(bf
, ts
, nbad
, txok
, false);
444 ath_tx_complete_buf(sc
, bf
, txq
, &bf_head
, ts
,
447 /* retry the un-acked ones */
448 if (!(sc
->sc_ah
->caps
.hw_caps
& ATH9K_HW_CAP_EDMA
)) {
449 if (bf
->bf_next
== NULL
&& bf_last
->bf_stale
) {
452 tbf
= ath_clone_txbuf(sc
, bf_last
);
454 * Update tx baw and complete the
455 * frame with failed status if we
459 spin_lock_bh(&txq
->axq_lock
);
460 ath_tx_update_baw(sc
, tid
,
462 spin_unlock_bh(&txq
->axq_lock
);
464 bf
->bf_state
.bf_type
|=
466 ath_tx_rc_status(bf
, ts
, nbad
,
468 ath_tx_complete_buf(sc
, bf
, txq
,
474 ath9k_hw_cleartxdesc(sc
->sc_ah
,
476 list_add_tail(&tbf
->list
, &bf_head
);
479 * Clear descriptor status words for
482 ath9k_hw_cleartxdesc(sc
->sc_ah
,
488 * Put this buffer to the temporary pending
489 * queue to retain ordering
491 list_splice_tail_init(&bf_head
, &bf_pending
);
497 if (tid
->state
& AGGR_CLEANUP
) {
498 if (tid
->baw_head
== tid
->baw_tail
) {
499 tid
->state
&= ~AGGR_ADDBA_COMPLETE
;
500 tid
->state
&= ~AGGR_CLEANUP
;
502 /* send buffered frames as singles */
503 ath_tx_flush_tid(sc
, tid
);
509 /* prepend un-acked frames to the beginning of the pending frame queue */
510 if (!list_empty(&bf_pending
)) {
511 spin_lock_bh(&txq
->axq_lock
);
512 list_splice(&bf_pending
, &tid
->buf_q
);
513 ath_tx_queue_tid(txq
, tid
);
514 spin_unlock_bh(&txq
->axq_lock
);
520 ath_reset(sc
, false);
523 static u32
ath_lookup_rate(struct ath_softc
*sc
, struct ath_buf
*bf
,
524 struct ath_atx_tid
*tid
)
527 struct ieee80211_tx_info
*tx_info
;
528 struct ieee80211_tx_rate
*rates
;
529 u32 max_4ms_framelen
, frmlen
;
530 u16 aggr_limit
, legacy
= 0;
534 tx_info
= IEEE80211_SKB_CB(skb
);
535 rates
= tx_info
->control
.rates
;
538 * Find the lowest frame length among the rate series that will have a
539 * 4ms transmit duration.
540 * TODO - TXOP limit needs to be considered.
542 max_4ms_framelen
= ATH_AMPDU_LIMIT_MAX
;
544 for (i
= 0; i
< 4; i
++) {
545 if (rates
[i
].count
) {
547 if (!(rates
[i
].flags
& IEEE80211_TX_RC_MCS
)) {
552 if (rates
[i
].flags
& IEEE80211_TX_RC_40_MHZ_WIDTH
)
557 if (rates
[i
].flags
& IEEE80211_TX_RC_SHORT_GI
)
560 frmlen
= ath_max_4ms_framelen
[modeidx
][rates
[i
].idx
];
561 max_4ms_framelen
= min(max_4ms_framelen
, frmlen
);
566 * limit aggregate size by the minimum rate if rate selected is
567 * not a probe rate, if rate selected is a probe rate then
568 * avoid aggregation of this packet.
570 if (tx_info
->flags
& IEEE80211_TX_CTL_RATE_CTRL_PROBE
|| legacy
)
573 if (sc
->sc_flags
& SC_OP_BT_PRIORITY_DETECTED
)
574 aggr_limit
= min((max_4ms_framelen
* 3) / 8,
575 (u32
)ATH_AMPDU_LIMIT_MAX
);
577 aggr_limit
= min(max_4ms_framelen
,
578 (u32
)ATH_AMPDU_LIMIT_MAX
);
581 * h/w can accept aggregates upto 16 bit lengths (65535).
582 * The IE, however can hold upto 65536, which shows up here
583 * as zero. Ignore 65536 since we are constrained by hw.
585 if (tid
->an
->maxampdu
)
586 aggr_limit
= min(aggr_limit
, tid
->an
->maxampdu
);
592 * Returns the number of delimiters to be added to
593 * meet the minimum required mpdudensity.
595 static int ath_compute_num_delims(struct ath_softc
*sc
, struct ath_atx_tid
*tid
,
596 struct ath_buf
*bf
, u16 frmlen
)
598 struct sk_buff
*skb
= bf
->bf_mpdu
;
599 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
600 u32 nsymbits
, nsymbols
;
603 int width
, streams
, half_gi
, ndelim
, mindelim
;
605 /* Select standard number of delimiters based on frame length alone */
606 ndelim
= ATH_AGGR_GET_NDELIM(frmlen
);
609 * If encryption enabled, hardware requires some more padding between
611 * TODO - this could be improved to be dependent on the rate.
612 * The hardware can keep up at lower rates, but not higher rates
614 if (bf
->bf_keytype
!= ATH9K_KEY_TYPE_CLEAR
)
615 ndelim
+= ATH_AGGR_ENCRYPTDELIM
;
618 * Convert desired mpdu density from microeconds to bytes based
619 * on highest rate in rate series (i.e. first rate) to determine
620 * required minimum length for subframe. Take into account
621 * whether high rate is 20 or 40Mhz and half or full GI.
623 * If there is no mpdu density restriction, no further calculation
627 if (tid
->an
->mpdudensity
== 0)
630 rix
= tx_info
->control
.rates
[0].idx
;
631 flags
= tx_info
->control
.rates
[0].flags
;
632 width
= (flags
& IEEE80211_TX_RC_40_MHZ_WIDTH
) ? 1 : 0;
633 half_gi
= (flags
& IEEE80211_TX_RC_SHORT_GI
) ? 1 : 0;
636 nsymbols
= NUM_SYMBOLS_PER_USEC_HALFGI(tid
->an
->mpdudensity
);
638 nsymbols
= NUM_SYMBOLS_PER_USEC(tid
->an
->mpdudensity
);
643 streams
= HT_RC_2_STREAMS(rix
);
644 nsymbits
= bits_per_symbol
[rix
% 8][width
] * streams
;
645 minlen
= (nsymbols
* nsymbits
) / BITS_PER_BYTE
;
647 if (frmlen
< minlen
) {
648 mindelim
= (minlen
- frmlen
) / ATH_AGGR_DELIM_SZ
;
649 ndelim
= max(mindelim
, ndelim
);
655 static enum ATH_AGGR_STATUS
ath_tx_form_aggr(struct ath_softc
*sc
,
657 struct ath_atx_tid
*tid
,
658 struct list_head
*bf_q
)
660 #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
661 struct ath_buf
*bf
, *bf_first
, *bf_prev
= NULL
;
662 int rl
= 0, nframes
= 0, ndelim
, prev_al
= 0;
663 u16 aggr_limit
= 0, al
= 0, bpad
= 0,
664 al_delta
, h_baw
= tid
->baw_size
/ 2;
665 enum ATH_AGGR_STATUS status
= ATH_AGGR_DONE
;
667 bf_first
= list_first_entry(&tid
->buf_q
, struct ath_buf
, list
);
670 bf
= list_first_entry(&tid
->buf_q
, struct ath_buf
, list
);
672 /* do not step over block-ack window */
673 if (!BAW_WITHIN(tid
->seq_start
, tid
->baw_size
, bf
->bf_seqno
)) {
674 status
= ATH_AGGR_BAW_CLOSED
;
679 aggr_limit
= ath_lookup_rate(sc
, bf
, tid
);
683 /* do not exceed aggregation limit */
684 al_delta
= ATH_AGGR_DELIM_SZ
+ bf
->bf_frmlen
;
687 (aggr_limit
< (al
+ bpad
+ al_delta
+ prev_al
))) {
688 status
= ATH_AGGR_LIMITED
;
692 /* do not exceed subframe limit */
693 if (nframes
>= min((int)h_baw
, ATH_AMPDU_SUBFRAME_DEFAULT
)) {
694 status
= ATH_AGGR_LIMITED
;
699 /* add padding for previous frame to aggregation length */
700 al
+= bpad
+ al_delta
;
703 * Get the delimiters needed to meet the MPDU
704 * density for this node.
706 ndelim
= ath_compute_num_delims(sc
, tid
, bf_first
, bf
->bf_frmlen
);
707 bpad
= PADBYTES(al_delta
) + (ndelim
<< 2);
710 ath9k_hw_set_desc_link(sc
->sc_ah
, bf
->bf_desc
, 0);
712 /* link buffers of this frame to the aggregate */
713 ath_tx_addto_baw(sc
, tid
, bf
);
714 ath9k_hw_set11n_aggr_middle(sc
->sc_ah
, bf
->bf_desc
, ndelim
);
715 list_move_tail(&bf
->list
, bf_q
);
717 bf_prev
->bf_next
= bf
;
718 ath9k_hw_set_desc_link(sc
->sc_ah
, bf_prev
->bf_desc
,
723 } while (!list_empty(&tid
->buf_q
));
725 bf_first
->bf_al
= al
;
726 bf_first
->bf_nframes
= nframes
;
732 static void ath_tx_sched_aggr(struct ath_softc
*sc
, struct ath_txq
*txq
,
733 struct ath_atx_tid
*tid
)
736 enum ATH_AGGR_STATUS status
;
737 struct list_head bf_q
;
740 if (list_empty(&tid
->buf_q
))
743 INIT_LIST_HEAD(&bf_q
);
745 status
= ath_tx_form_aggr(sc
, txq
, tid
, &bf_q
);
748 * no frames picked up to be aggregated;
749 * block-ack window is not open.
751 if (list_empty(&bf_q
))
754 bf
= list_first_entry(&bf_q
, struct ath_buf
, list
);
755 bf
->bf_lastbf
= list_entry(bf_q
.prev
, struct ath_buf
, list
);
757 /* if only one frame, send as non-aggregate */
758 if (bf
->bf_nframes
== 1) {
759 bf
->bf_state
.bf_type
&= ~BUF_AGGR
;
760 ath9k_hw_clr11n_aggr(sc
->sc_ah
, bf
->bf_desc
);
761 ath_buf_set_rate(sc
, bf
);
762 ath_tx_txqaddbuf(sc
, txq
, &bf_q
);
766 /* setup first desc of aggregate */
767 bf
->bf_state
.bf_type
|= BUF_AGGR
;
768 ath_buf_set_rate(sc
, bf
);
769 ath9k_hw_set11n_aggr_first(sc
->sc_ah
, bf
->bf_desc
, bf
->bf_al
);
771 /* anchor last desc of aggregate */
772 ath9k_hw_set11n_aggr_last(sc
->sc_ah
, bf
->bf_lastbf
->bf_desc
);
774 ath_tx_txqaddbuf(sc
, txq
, &bf_q
);
775 TX_STAT_INC(txq
->axq_qnum
, a_aggr
);
777 } while (txq
->axq_depth
< ATH_AGGR_MIN_QDEPTH
&&
778 status
!= ATH_AGGR_BAW_CLOSED
);
781 void ath_tx_aggr_start(struct ath_softc
*sc
, struct ieee80211_sta
*sta
,
784 struct ath_atx_tid
*txtid
;
787 an
= (struct ath_node
*)sta
->drv_priv
;
788 txtid
= ATH_AN_2_TID(an
, tid
);
789 txtid
->state
|= AGGR_ADDBA_PROGRESS
;
790 ath_tx_pause_tid(sc
, txtid
);
791 *ssn
= txtid
->seq_start
;
794 void ath_tx_aggr_stop(struct ath_softc
*sc
, struct ieee80211_sta
*sta
, u16 tid
)
796 struct ath_node
*an
= (struct ath_node
*)sta
->drv_priv
;
797 struct ath_atx_tid
*txtid
= ATH_AN_2_TID(an
, tid
);
798 struct ath_txq
*txq
= &sc
->tx
.txq
[txtid
->ac
->qnum
];
799 struct ath_tx_status ts
;
801 struct list_head bf_head
;
803 memset(&ts
, 0, sizeof(ts
));
804 INIT_LIST_HEAD(&bf_head
);
806 if (txtid
->state
& AGGR_CLEANUP
)
809 if (!(txtid
->state
& AGGR_ADDBA_COMPLETE
)) {
810 txtid
->state
&= ~AGGR_ADDBA_PROGRESS
;
814 ath_tx_pause_tid(sc
, txtid
);
816 /* drop all software retried frames and mark this TID */
817 spin_lock_bh(&txq
->axq_lock
);
818 while (!list_empty(&txtid
->buf_q
)) {
819 bf
= list_first_entry(&txtid
->buf_q
, struct ath_buf
, list
);
820 if (!bf_isretried(bf
)) {
822 * NB: it's based on the assumption that
823 * software retried frame will always stay
824 * at the head of software queue.
828 list_move_tail(&bf
->list
, &bf_head
);
829 ath_tx_update_baw(sc
, txtid
, bf
->bf_seqno
);
830 ath_tx_complete_buf(sc
, bf
, txq
, &bf_head
, &ts
, 0, 0);
832 spin_unlock_bh(&txq
->axq_lock
);
834 if (txtid
->baw_head
!= txtid
->baw_tail
) {
835 txtid
->state
|= AGGR_CLEANUP
;
837 txtid
->state
&= ~AGGR_ADDBA_COMPLETE
;
838 ath_tx_flush_tid(sc
, txtid
);
842 void ath_tx_aggr_resume(struct ath_softc
*sc
, struct ieee80211_sta
*sta
, u16 tid
)
844 struct ath_atx_tid
*txtid
;
847 an
= (struct ath_node
*)sta
->drv_priv
;
849 if (sc
->sc_flags
& SC_OP_TXAGGR
) {
850 txtid
= ATH_AN_2_TID(an
, tid
);
852 IEEE80211_MIN_AMPDU_BUF
<< sta
->ht_cap
.ampdu_factor
;
853 txtid
->state
|= AGGR_ADDBA_COMPLETE
;
854 txtid
->state
&= ~AGGR_ADDBA_PROGRESS
;
855 ath_tx_resume_tid(sc
, txtid
);
859 bool ath_tx_aggr_check(struct ath_softc
*sc
, struct ath_node
*an
, u8 tidno
)
861 struct ath_atx_tid
*txtid
;
863 if (!(sc
->sc_flags
& SC_OP_TXAGGR
))
866 txtid
= ATH_AN_2_TID(an
, tidno
);
868 if (!(txtid
->state
& (AGGR_ADDBA_COMPLETE
| AGGR_ADDBA_PROGRESS
)))
873 /********************/
874 /* Queue Management */
875 /********************/
877 static void ath_txq_drain_pending_buffers(struct ath_softc
*sc
,
880 struct ath_atx_ac
*ac
, *ac_tmp
;
881 struct ath_atx_tid
*tid
, *tid_tmp
;
883 list_for_each_entry_safe(ac
, ac_tmp
, &txq
->axq_acq
, list
) {
886 list_for_each_entry_safe(tid
, tid_tmp
, &ac
->tid_q
, list
) {
887 list_del(&tid
->list
);
889 ath_tid_drain(sc
, txq
, tid
);
894 struct ath_txq
*ath_txq_setup(struct ath_softc
*sc
, int qtype
, int subtype
)
896 struct ath_hw
*ah
= sc
->sc_ah
;
897 struct ath_common
*common
= ath9k_hw_common(ah
);
898 struct ath9k_tx_queue_info qi
;
901 memset(&qi
, 0, sizeof(qi
));
902 qi
.tqi_subtype
= subtype
;
903 qi
.tqi_aifs
= ATH9K_TXQ_USEDEFAULT
;
904 qi
.tqi_cwmin
= ATH9K_TXQ_USEDEFAULT
;
905 qi
.tqi_cwmax
= ATH9K_TXQ_USEDEFAULT
;
906 qi
.tqi_physCompBuf
= 0;
909 * Enable interrupts only for EOL and DESC conditions.
910 * We mark tx descriptors to receive a DESC interrupt
911 * when a tx queue gets deep; otherwise waiting for the
912 * EOL to reap descriptors. Note that this is done to
913 * reduce interrupt load and this only defers reaping
914 * descriptors, never transmitting frames. Aside from
915 * reducing interrupts this also permits more concurrency.
916 * The only potential downside is if the tx queue backs
917 * up in which case the top half of the kernel may backup
918 * due to a lack of tx descriptors.
920 * The UAPSD queue is an exception, since we take a desc-
921 * based intr on the EOSP frames.
923 if (ah
->caps
.hw_caps
& ATH9K_HW_CAP_EDMA
) {
924 qi
.tqi_qflags
= TXQ_FLAG_TXOKINT_ENABLE
|
925 TXQ_FLAG_TXERRINT_ENABLE
;
927 if (qtype
== ATH9K_TX_QUEUE_UAPSD
)
928 qi
.tqi_qflags
= TXQ_FLAG_TXDESCINT_ENABLE
;
930 qi
.tqi_qflags
= TXQ_FLAG_TXEOLINT_ENABLE
|
931 TXQ_FLAG_TXDESCINT_ENABLE
;
933 qnum
= ath9k_hw_setuptxqueue(ah
, qtype
, &qi
);
936 * NB: don't print a message, this happens
937 * normally on parts with too few tx queues
941 if (qnum
>= ARRAY_SIZE(sc
->tx
.txq
)) {
942 ath_print(common
, ATH_DBG_FATAL
,
943 "qnum %u out of range, max %u!\n",
944 qnum
, (unsigned int)ARRAY_SIZE(sc
->tx
.txq
));
945 ath9k_hw_releasetxqueue(ah
, qnum
);
948 if (!ATH_TXQ_SETUP(sc
, qnum
)) {
949 struct ath_txq
*txq
= &sc
->tx
.txq
[qnum
];
951 txq
->axq_class
= subtype
;
952 txq
->axq_qnum
= qnum
;
953 txq
->axq_link
= NULL
;
954 INIT_LIST_HEAD(&txq
->axq_q
);
955 INIT_LIST_HEAD(&txq
->axq_acq
);
956 spin_lock_init(&txq
->axq_lock
);
958 txq
->axq_tx_inprogress
= false;
959 sc
->tx
.txqsetup
|= 1<<qnum
;
961 txq
->txq_headidx
= txq
->txq_tailidx
= 0;
962 for (i
= 0; i
< ATH_TXFIFO_DEPTH
; i
++)
963 INIT_LIST_HEAD(&txq
->txq_fifo
[i
]);
964 INIT_LIST_HEAD(&txq
->txq_fifo_pending
);
966 return &sc
->tx
.txq
[qnum
];
969 int ath_txq_update(struct ath_softc
*sc
, int qnum
,
970 struct ath9k_tx_queue_info
*qinfo
)
972 struct ath_hw
*ah
= sc
->sc_ah
;
974 struct ath9k_tx_queue_info qi
;
976 if (qnum
== sc
->beacon
.beaconq
) {
978 * XXX: for beacon queue, we just save the parameter.
979 * It will be picked up by ath_beaconq_config when
982 sc
->beacon
.beacon_qi
= *qinfo
;
986 BUG_ON(sc
->tx
.txq
[qnum
].axq_qnum
!= qnum
);
988 ath9k_hw_get_txq_props(ah
, qnum
, &qi
);
989 qi
.tqi_aifs
= qinfo
->tqi_aifs
;
990 qi
.tqi_cwmin
= qinfo
->tqi_cwmin
;
991 qi
.tqi_cwmax
= qinfo
->tqi_cwmax
;
992 qi
.tqi_burstTime
= qinfo
->tqi_burstTime
;
993 qi
.tqi_readyTime
= qinfo
->tqi_readyTime
;
995 if (!ath9k_hw_set_txq_props(ah
, qnum
, &qi
)) {
996 ath_print(ath9k_hw_common(sc
->sc_ah
), ATH_DBG_FATAL
,
997 "Unable to update hardware queue %u!\n", qnum
);
1000 ath9k_hw_resettxqueue(ah
, qnum
);
1006 int ath_cabq_update(struct ath_softc
*sc
)
1008 struct ath9k_tx_queue_info qi
;
1009 int qnum
= sc
->beacon
.cabq
->axq_qnum
;
1011 ath9k_hw_get_txq_props(sc
->sc_ah
, qnum
, &qi
);
1013 * Ensure the readytime % is within the bounds.
1015 if (sc
->config
.cabqReadytime
< ATH9K_READY_TIME_LO_BOUND
)
1016 sc
->config
.cabqReadytime
= ATH9K_READY_TIME_LO_BOUND
;
1017 else if (sc
->config
.cabqReadytime
> ATH9K_READY_TIME_HI_BOUND
)
1018 sc
->config
.cabqReadytime
= ATH9K_READY_TIME_HI_BOUND
;
1020 qi
.tqi_readyTime
= (sc
->beacon_interval
*
1021 sc
->config
.cabqReadytime
) / 100;
1022 ath_txq_update(sc
, qnum
, &qi
);
1028 * Drain a given TX queue (could be Beacon or Data)
1030 * This assumes output has been stopped and
1031 * we do not need to block ath_tx_tasklet.
1033 void ath_draintxq(struct ath_softc
*sc
, struct ath_txq
*txq
, bool retry_tx
)
1035 struct ath_buf
*bf
, *lastbf
;
1036 struct list_head bf_head
;
1037 struct ath_tx_status ts
;
1039 memset(&ts
, 0, sizeof(ts
));
1040 INIT_LIST_HEAD(&bf_head
);
1043 spin_lock_bh(&txq
->axq_lock
);
1045 if (sc
->sc_ah
->caps
.hw_caps
& ATH9K_HW_CAP_EDMA
) {
1046 if (list_empty(&txq
->txq_fifo
[txq
->txq_tailidx
])) {
1047 txq
->txq_headidx
= txq
->txq_tailidx
= 0;
1048 spin_unlock_bh(&txq
->axq_lock
);
1051 bf
= list_first_entry(&txq
->txq_fifo
[txq
->txq_tailidx
],
1052 struct ath_buf
, list
);
1055 if (list_empty(&txq
->axq_q
)) {
1056 txq
->axq_link
= NULL
;
1057 spin_unlock_bh(&txq
->axq_lock
);
1060 bf
= list_first_entry(&txq
->axq_q
, struct ath_buf
,
1064 list_del(&bf
->list
);
1065 spin_unlock_bh(&txq
->axq_lock
);
1067 ath_tx_return_buffer(sc
, bf
);
1072 lastbf
= bf
->bf_lastbf
;
1074 lastbf
->bf_tx_aborted
= true;
1076 if (sc
->sc_ah
->caps
.hw_caps
& ATH9K_HW_CAP_EDMA
) {
1077 list_cut_position(&bf_head
,
1078 &txq
->txq_fifo
[txq
->txq_tailidx
],
1080 INCR(txq
->txq_tailidx
, ATH_TXFIFO_DEPTH
);
1082 /* remove ath_buf's of the same mpdu from txq */
1083 list_cut_position(&bf_head
, &txq
->axq_q
, &lastbf
->list
);
1088 spin_unlock_bh(&txq
->axq_lock
);
1091 ath_tx_complete_aggr(sc
, txq
, bf
, &bf_head
, &ts
, 0);
1093 ath_tx_complete_buf(sc
, bf
, txq
, &bf_head
, &ts
, 0, 0);
1096 spin_lock_bh(&txq
->axq_lock
);
1097 txq
->axq_tx_inprogress
= false;
1098 spin_unlock_bh(&txq
->axq_lock
);
1100 /* flush any pending frames if aggregation is enabled */
1101 if (sc
->sc_flags
& SC_OP_TXAGGR
) {
1103 spin_lock_bh(&txq
->axq_lock
);
1104 ath_txq_drain_pending_buffers(sc
, txq
);
1105 spin_unlock_bh(&txq
->axq_lock
);
1109 if (sc
->sc_ah
->caps
.hw_caps
& ATH9K_HW_CAP_EDMA
) {
1110 spin_lock_bh(&txq
->axq_lock
);
1111 while (!list_empty(&txq
->txq_fifo_pending
)) {
1112 bf
= list_first_entry(&txq
->txq_fifo_pending
,
1113 struct ath_buf
, list
);
1114 list_cut_position(&bf_head
,
1115 &txq
->txq_fifo_pending
,
1116 &bf
->bf_lastbf
->list
);
1117 spin_unlock_bh(&txq
->axq_lock
);
1120 ath_tx_complete_aggr(sc
, txq
, bf
, &bf_head
,
1123 ath_tx_complete_buf(sc
, bf
, txq
, &bf_head
,
1125 spin_lock_bh(&txq
->axq_lock
);
1127 spin_unlock_bh(&txq
->axq_lock
);
1131 void ath_drain_all_txq(struct ath_softc
*sc
, bool retry_tx
)
1133 struct ath_hw
*ah
= sc
->sc_ah
;
1134 struct ath_common
*common
= ath9k_hw_common(sc
->sc_ah
);
1135 struct ath_txq
*txq
;
1138 if (sc
->sc_flags
& SC_OP_INVALID
)
1141 /* Stop beacon queue */
1142 ath9k_hw_stoptxdma(sc
->sc_ah
, sc
->beacon
.beaconq
);
1144 /* Stop data queues */
1145 for (i
= 0; i
< ATH9K_NUM_TX_QUEUES
; i
++) {
1146 if (ATH_TXQ_SETUP(sc
, i
)) {
1147 txq
= &sc
->tx
.txq
[i
];
1148 ath9k_hw_stoptxdma(ah
, txq
->axq_qnum
);
1149 npend
+= ath9k_hw_numtxpending(ah
, txq
->axq_qnum
);
1156 ath_print(common
, ATH_DBG_FATAL
,
1157 "Failed to stop TX DMA. Resetting hardware!\n");
1159 spin_lock_bh(&sc
->sc_resetlock
);
1160 r
= ath9k_hw_reset(ah
, sc
->sc_ah
->curchan
, false);
1162 ath_print(common
, ATH_DBG_FATAL
,
1163 "Unable to reset hardware; reset status %d\n",
1165 spin_unlock_bh(&sc
->sc_resetlock
);
1168 for (i
= 0; i
< ATH9K_NUM_TX_QUEUES
; i
++) {
1169 if (ATH_TXQ_SETUP(sc
, i
))
1170 ath_draintxq(sc
, &sc
->tx
.txq
[i
], retry_tx
);
1174 void ath_tx_cleanupq(struct ath_softc
*sc
, struct ath_txq
*txq
)
1176 ath9k_hw_releasetxqueue(sc
->sc_ah
, txq
->axq_qnum
);
1177 sc
->tx
.txqsetup
&= ~(1<<txq
->axq_qnum
);
1180 void ath_txq_schedule(struct ath_softc
*sc
, struct ath_txq
*txq
)
1182 struct ath_atx_ac
*ac
;
1183 struct ath_atx_tid
*tid
;
1185 if (list_empty(&txq
->axq_acq
))
1188 ac
= list_first_entry(&txq
->axq_acq
, struct ath_atx_ac
, list
);
1189 list_del(&ac
->list
);
1193 if (list_empty(&ac
->tid_q
))
1196 tid
= list_first_entry(&ac
->tid_q
, struct ath_atx_tid
, list
);
1197 list_del(&tid
->list
);
1203 ath_tx_sched_aggr(sc
, txq
, tid
);
1206 * add tid to round-robin queue if more frames
1207 * are pending for the tid
1209 if (!list_empty(&tid
->buf_q
))
1210 ath_tx_queue_tid(txq
, tid
);
1213 } while (!list_empty(&ac
->tid_q
));
1215 if (!list_empty(&ac
->tid_q
)) {
1218 list_add_tail(&ac
->list
, &txq
->axq_acq
);
1223 int ath_tx_setup(struct ath_softc
*sc
, int haltype
)
1225 struct ath_txq
*txq
;
1227 if (haltype
>= ARRAY_SIZE(sc
->tx
.hwq_map
)) {
1228 ath_print(ath9k_hw_common(sc
->sc_ah
), ATH_DBG_FATAL
,
1229 "HAL AC %u out of range, max %zu!\n",
1230 haltype
, ARRAY_SIZE(sc
->tx
.hwq_map
));
1233 txq
= ath_txq_setup(sc
, ATH9K_TX_QUEUE_DATA
, haltype
);
1235 sc
->tx
.hwq_map
[haltype
] = txq
->axq_qnum
;
1246 * Insert a chain of ath_buf (descriptors) on a txq and
1247 * assume the descriptors are already chained together by caller.
1249 static void ath_tx_txqaddbuf(struct ath_softc
*sc
, struct ath_txq
*txq
,
1250 struct list_head
*head
)
1252 struct ath_hw
*ah
= sc
->sc_ah
;
1253 struct ath_common
*common
= ath9k_hw_common(ah
);
1257 * Insert the frame on the outbound list and
1258 * pass it on to the hardware.
1261 if (list_empty(head
))
1264 bf
= list_first_entry(head
, struct ath_buf
, list
);
1266 ath_print(common
, ATH_DBG_QUEUE
,
1267 "qnum: %d, txq depth: %d\n", txq
->axq_qnum
, txq
->axq_depth
);
1269 if (sc
->sc_ah
->caps
.hw_caps
& ATH9K_HW_CAP_EDMA
) {
1270 if (txq
->axq_depth
>= ATH_TXFIFO_DEPTH
) {
1271 list_splice_tail_init(head
, &txq
->txq_fifo_pending
);
1274 if (!list_empty(&txq
->txq_fifo
[txq
->txq_headidx
]))
1275 ath_print(common
, ATH_DBG_XMIT
,
1276 "Initializing tx fifo %d which "
1279 INIT_LIST_HEAD(&txq
->txq_fifo
[txq
->txq_headidx
]);
1280 list_splice_init(head
, &txq
->txq_fifo
[txq
->txq_headidx
]);
1281 INCR(txq
->txq_headidx
, ATH_TXFIFO_DEPTH
);
1282 ath9k_hw_puttxbuf(ah
, txq
->axq_qnum
, bf
->bf_daddr
);
1283 ath_print(common
, ATH_DBG_XMIT
,
1284 "TXDP[%u] = %llx (%p)\n",
1285 txq
->axq_qnum
, ito64(bf
->bf_daddr
), bf
->bf_desc
);
1287 list_splice_tail_init(head
, &txq
->axq_q
);
1289 if (txq
->axq_link
== NULL
) {
1290 ath9k_hw_puttxbuf(ah
, txq
->axq_qnum
, bf
->bf_daddr
);
1291 ath_print(common
, ATH_DBG_XMIT
,
1292 "TXDP[%u] = %llx (%p)\n",
1293 txq
->axq_qnum
, ito64(bf
->bf_daddr
),
1296 *txq
->axq_link
= bf
->bf_daddr
;
1297 ath_print(common
, ATH_DBG_XMIT
,
1298 "link[%u] (%p)=%llx (%p)\n",
1299 txq
->axq_qnum
, txq
->axq_link
,
1300 ito64(bf
->bf_daddr
), bf
->bf_desc
);
1302 ath9k_hw_get_desc_link(ah
, bf
->bf_lastbf
->bf_desc
,
1304 ath9k_hw_txstart(ah
, txq
->axq_qnum
);
1309 static void ath_tx_send_ampdu(struct ath_softc
*sc
, struct ath_atx_tid
*tid
,
1310 struct list_head
*bf_head
,
1311 struct ath_tx_control
*txctl
)
1315 bf
= list_first_entry(bf_head
, struct ath_buf
, list
);
1316 bf
->bf_state
.bf_type
|= BUF_AMPDU
;
1317 TX_STAT_INC(txctl
->txq
->axq_qnum
, a_queued
);
1320 * Do not queue to h/w when any of the following conditions is true:
1321 * - there are pending frames in software queue
1322 * - the TID is currently paused for ADDBA/BAR request
1323 * - seqno is not within block-ack window
1324 * - h/w queue depth exceeds low water mark
1326 if (!list_empty(&tid
->buf_q
) || tid
->paused
||
1327 !BAW_WITHIN(tid
->seq_start
, tid
->baw_size
, bf
->bf_seqno
) ||
1328 txctl
->txq
->axq_depth
>= ATH_AGGR_MIN_QDEPTH
) {
1330 * Add this frame to software queue for scheduling later
1333 list_move_tail(&bf
->list
, &tid
->buf_q
);
1334 ath_tx_queue_tid(txctl
->txq
, tid
);
1338 /* Add sub-frame to BAW */
1339 ath_tx_addto_baw(sc
, tid
, bf
);
1341 /* Queue to h/w without aggregation */
1344 ath_buf_set_rate(sc
, bf
);
1345 ath_tx_txqaddbuf(sc
, txctl
->txq
, bf_head
);
1348 static void ath_tx_send_ht_normal(struct ath_softc
*sc
, struct ath_txq
*txq
,
1349 struct ath_atx_tid
*tid
,
1350 struct list_head
*bf_head
)
1354 bf
= list_first_entry(bf_head
, struct ath_buf
, list
);
1355 bf
->bf_state
.bf_type
&= ~BUF_AMPDU
;
1357 /* update starting sequence number for subsequent ADDBA request */
1358 INCR(tid
->seq_start
, IEEE80211_SEQ_MAX
);
1362 ath_buf_set_rate(sc
, bf
);
1363 ath_tx_txqaddbuf(sc
, txq
, bf_head
);
1364 TX_STAT_INC(txq
->axq_qnum
, queued
);
1367 static void ath_tx_send_normal(struct ath_softc
*sc
, struct ath_txq
*txq
,
1368 struct list_head
*bf_head
)
1372 bf
= list_first_entry(bf_head
, struct ath_buf
, list
);
1376 ath_buf_set_rate(sc
, bf
);
1377 ath_tx_txqaddbuf(sc
, txq
, bf_head
);
1378 TX_STAT_INC(txq
->axq_qnum
, queued
);
1381 static enum ath9k_pkt_type
get_hw_packet_type(struct sk_buff
*skb
)
1383 struct ieee80211_hdr
*hdr
;
1384 enum ath9k_pkt_type htype
;
1387 hdr
= (struct ieee80211_hdr
*)skb
->data
;
1388 fc
= hdr
->frame_control
;
1390 if (ieee80211_is_beacon(fc
))
1391 htype
= ATH9K_PKT_TYPE_BEACON
;
1392 else if (ieee80211_is_probe_resp(fc
))
1393 htype
= ATH9K_PKT_TYPE_PROBE_RESP
;
1394 else if (ieee80211_is_atim(fc
))
1395 htype
= ATH9K_PKT_TYPE_ATIM
;
1396 else if (ieee80211_is_pspoll(fc
))
1397 htype
= ATH9K_PKT_TYPE_PSPOLL
;
1399 htype
= ATH9K_PKT_TYPE_NORMAL
;
1404 static int get_hw_crypto_keytype(struct sk_buff
*skb
)
1406 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
1408 if (tx_info
->control
.hw_key
) {
1409 if (tx_info
->control
.hw_key
->alg
== ALG_WEP
)
1410 return ATH9K_KEY_TYPE_WEP
;
1411 else if (tx_info
->control
.hw_key
->alg
== ALG_TKIP
)
1412 return ATH9K_KEY_TYPE_TKIP
;
1413 else if (tx_info
->control
.hw_key
->alg
== ALG_CCMP
)
1414 return ATH9K_KEY_TYPE_AES
;
1417 return ATH9K_KEY_TYPE_CLEAR
;
1420 static void assign_aggr_tid_seqno(struct sk_buff
*skb
,
1423 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
1424 struct ieee80211_hdr
*hdr
;
1425 struct ath_node
*an
;
1426 struct ath_atx_tid
*tid
;
1430 if (!tx_info
->control
.sta
)
1433 an
= (struct ath_node
*)tx_info
->control
.sta
->drv_priv
;
1434 hdr
= (struct ieee80211_hdr
*)skb
->data
;
1435 fc
= hdr
->frame_control
;
1437 if (ieee80211_is_data_qos(fc
)) {
1438 qc
= ieee80211_get_qos_ctl(hdr
);
1439 bf
->bf_tidno
= qc
[0] & 0xf;
1443 * For HT capable stations, we save tidno for later use.
1444 * We also override seqno set by upper layer with the one
1445 * in tx aggregation state.
1447 tid
= ATH_AN_2_TID(an
, bf
->bf_tidno
);
1448 hdr
->seq_ctrl
= cpu_to_le16(tid
->seq_next
<< IEEE80211_SEQ_SEQ_SHIFT
);
1449 bf
->bf_seqno
= tid
->seq_next
;
1450 INCR(tid
->seq_next
, IEEE80211_SEQ_MAX
);
1453 static int setup_tx_flags(struct sk_buff
*skb
, bool use_ldpc
)
1455 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
1458 flags
|= ATH9K_TXDESC_CLRDMASK
; /* needed for crypto errors */
1459 flags
|= ATH9K_TXDESC_INTREQ
;
1461 if (tx_info
->flags
& IEEE80211_TX_CTL_NO_ACK
)
1462 flags
|= ATH9K_TXDESC_NOACK
;
1465 flags
|= ATH9K_TXDESC_LDPC
;
1472 * pktlen - total bytes (delims + data + fcs + pads + pad delims)
1473 * width - 0 for 20 MHz, 1 for 40 MHz
1474 * half_gi - to use 4us v/s 3.6 us for symbol time
1476 static u32
ath_pkt_duration(struct ath_softc
*sc
, u8 rix
, struct ath_buf
*bf
,
1477 int width
, int half_gi
, bool shortPreamble
)
1479 u32 nbits
, nsymbits
, duration
, nsymbols
;
1480 int streams
, pktlen
;
1482 pktlen
= bf_isaggr(bf
) ? bf
->bf_al
: bf
->bf_frmlen
;
1484 /* find number of symbols: PLCP + data */
1485 streams
= HT_RC_2_STREAMS(rix
);
1486 nbits
= (pktlen
<< 3) + OFDM_PLCP_BITS
;
1487 nsymbits
= bits_per_symbol
[rix
% 8][width
] * streams
;
1488 nsymbols
= (nbits
+ nsymbits
- 1) / nsymbits
;
1491 duration
= SYMBOL_TIME(nsymbols
);
1493 duration
= SYMBOL_TIME_HALFGI(nsymbols
);
1495 /* addup duration for legacy/ht training and signal fields */
1496 duration
+= L_STF
+ L_LTF
+ L_SIG
+ HT_SIG
+ HT_STF
+ HT_LTF(streams
);
1501 static void ath_buf_set_rate(struct ath_softc
*sc
, struct ath_buf
*bf
)
1503 struct ath_common
*common
= ath9k_hw_common(sc
->sc_ah
);
1504 struct ath9k_11n_rate_series series
[4];
1505 struct sk_buff
*skb
;
1506 struct ieee80211_tx_info
*tx_info
;
1507 struct ieee80211_tx_rate
*rates
;
1508 const struct ieee80211_rate
*rate
;
1509 struct ieee80211_hdr
*hdr
;
1511 u8 rix
= 0, ctsrate
= 0;
1514 memset(series
, 0, sizeof(struct ath9k_11n_rate_series
) * 4);
1517 tx_info
= IEEE80211_SKB_CB(skb
);
1518 rates
= tx_info
->control
.rates
;
1519 hdr
= (struct ieee80211_hdr
*)skb
->data
;
1520 is_pspoll
= ieee80211_is_pspoll(hdr
->frame_control
);
1523 * We check if Short Preamble is needed for the CTS rate by
1524 * checking the BSS's global flag.
1525 * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used.
1527 rate
= ieee80211_get_rts_cts_rate(sc
->hw
, tx_info
);
1528 ctsrate
= rate
->hw_value
;
1529 if (sc
->sc_flags
& SC_OP_PREAMBLE_SHORT
)
1530 ctsrate
|= rate
->hw_value_short
;
1532 for (i
= 0; i
< 4; i
++) {
1533 bool is_40
, is_sgi
, is_sp
;
1536 if (!rates
[i
].count
|| (rates
[i
].idx
< 0))
1540 series
[i
].Tries
= rates
[i
].count
;
1541 series
[i
].ChSel
= common
->tx_chainmask
;
1543 if ((sc
->config
.ath_aggr_prot
&& bf_isaggr(bf
)) ||
1544 (rates
[i
].flags
& IEEE80211_TX_RC_USE_RTS_CTS
)) {
1545 series
[i
].RateFlags
|= ATH9K_RATESERIES_RTS_CTS
;
1546 flags
|= ATH9K_TXDESC_RTSENA
;
1547 } else if (rates
[i
].flags
& IEEE80211_TX_RC_USE_CTS_PROTECT
) {
1548 series
[i
].RateFlags
|= ATH9K_RATESERIES_RTS_CTS
;
1549 flags
|= ATH9K_TXDESC_CTSENA
;
1552 if (rates
[i
].flags
& IEEE80211_TX_RC_40_MHZ_WIDTH
)
1553 series
[i
].RateFlags
|= ATH9K_RATESERIES_2040
;
1554 if (rates
[i
].flags
& IEEE80211_TX_RC_SHORT_GI
)
1555 series
[i
].RateFlags
|= ATH9K_RATESERIES_HALFGI
;
1557 is_sgi
= !!(rates
[i
].flags
& IEEE80211_TX_RC_SHORT_GI
);
1558 is_40
= !!(rates
[i
].flags
& IEEE80211_TX_RC_40_MHZ_WIDTH
);
1559 is_sp
= !!(rates
[i
].flags
& IEEE80211_TX_RC_USE_SHORT_PREAMBLE
);
1561 if (rates
[i
].flags
& IEEE80211_TX_RC_MCS
) {
1563 series
[i
].Rate
= rix
| 0x80;
1564 series
[i
].PktDuration
= ath_pkt_duration(sc
, rix
, bf
,
1565 is_40
, is_sgi
, is_sp
);
1566 if (rix
< 8 && (tx_info
->flags
& IEEE80211_TX_CTL_STBC
))
1567 series
[i
].RateFlags
|= ATH9K_RATESERIES_STBC
;
1572 if ((tx_info
->band
== IEEE80211_BAND_2GHZ
) &&
1573 !(rate
->flags
& IEEE80211_RATE_ERP_G
))
1574 phy
= WLAN_RC_PHY_CCK
;
1576 phy
= WLAN_RC_PHY_OFDM
;
1578 rate
= &sc
->sbands
[tx_info
->band
].bitrates
[rates
[i
].idx
];
1579 series
[i
].Rate
= rate
->hw_value
;
1580 if (rate
->hw_value_short
) {
1581 if (rates
[i
].flags
& IEEE80211_TX_RC_USE_SHORT_PREAMBLE
)
1582 series
[i
].Rate
|= rate
->hw_value_short
;
1587 series
[i
].PktDuration
= ath9k_hw_computetxtime(sc
->sc_ah
,
1588 phy
, rate
->bitrate
* 100, bf
->bf_frmlen
, rix
, is_sp
);
1591 /* For AR5416 - RTS cannot be followed by a frame larger than 8K */
1592 if (bf_isaggr(bf
) && (bf
->bf_al
> sc
->sc_ah
->caps
.rts_aggr_limit
))
1593 flags
&= ~ATH9K_TXDESC_RTSENA
;
1595 /* ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive. */
1596 if (flags
& ATH9K_TXDESC_RTSENA
)
1597 flags
&= ~ATH9K_TXDESC_CTSENA
;
1599 /* set dur_update_en for l-sig computation except for PS-Poll frames */
1600 ath9k_hw_set11n_ratescenario(sc
->sc_ah
, bf
->bf_desc
,
1601 bf
->bf_lastbf
->bf_desc
,
1602 !is_pspoll
, ctsrate
,
1603 0, series
, 4, flags
);
1605 if (sc
->config
.ath_aggr_prot
&& flags
)
1606 ath9k_hw_set11n_burstduration(sc
->sc_ah
, bf
->bf_desc
, 8192);
1609 static int ath_tx_setup_buffer(struct ieee80211_hw
*hw
, struct ath_buf
*bf
,
1610 struct sk_buff
*skb
,
1611 struct ath_tx_control
*txctl
)
1613 struct ath_wiphy
*aphy
= hw
->priv
;
1614 struct ath_softc
*sc
= aphy
->sc
;
1615 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
1616 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*)skb
->data
;
1619 int padpos
, padsize
;
1620 bool use_ldpc
= false;
1622 tx_info
->pad
[0] = 0;
1623 switch (txctl
->frame_type
) {
1624 case ATH9K_IFT_NOT_INTERNAL
:
1626 case ATH9K_IFT_PAUSE
:
1627 tx_info
->pad
[0] |= ATH_TX_INFO_FRAME_TYPE_PAUSE
;
1629 case ATH9K_IFT_UNPAUSE
:
1630 tx_info
->pad
[0] |= ATH_TX_INFO_FRAME_TYPE_INTERNAL
;
1633 hdrlen
= ieee80211_get_hdrlen_from_skb(skb
);
1634 fc
= hdr
->frame_control
;
1636 ATH_TXBUF_RESET(bf
);
1639 bf
->bf_frmlen
= skb
->len
+ FCS_LEN
;
1640 /* Remove the padding size from bf_frmlen, if any */
1641 padpos
= ath9k_cmn_padpos(hdr
->frame_control
);
1642 padsize
= padpos
& 3;
1643 if (padsize
&& skb
->len
>padpos
+padsize
) {
1644 bf
->bf_frmlen
-= padsize
;
1647 if (!txctl
->paprd
&& conf_is_ht(&hw
->conf
)) {
1648 bf
->bf_state
.bf_type
|= BUF_HT
;
1649 if (tx_info
->flags
& IEEE80211_TX_CTL_LDPC
)
1653 bf
->bf_state
.bfs_paprd
= txctl
->paprd
;
1655 bf
->bf_state
.bfs_paprd_timestamp
= jiffies
;
1656 bf
->bf_flags
= setup_tx_flags(skb
, use_ldpc
);
1658 bf
->bf_keytype
= get_hw_crypto_keytype(skb
);
1659 if (bf
->bf_keytype
!= ATH9K_KEY_TYPE_CLEAR
) {
1660 bf
->bf_frmlen
+= tx_info
->control
.hw_key
->icv_len
;
1661 bf
->bf_keyix
= tx_info
->control
.hw_key
->hw_key_idx
;
1663 bf
->bf_keyix
= ATH9K_TXKEYIX_INVALID
;
1666 if (ieee80211_is_data_qos(fc
) && bf_isht(bf
) &&
1667 (sc
->sc_flags
& SC_OP_TXAGGR
))
1668 assign_aggr_tid_seqno(skb
, bf
);
1672 bf
->bf_dmacontext
= dma_map_single(sc
->dev
, skb
->data
,
1673 skb
->len
, DMA_TO_DEVICE
);
1674 if (unlikely(dma_mapping_error(sc
->dev
, bf
->bf_dmacontext
))) {
1676 ath_print(ath9k_hw_common(sc
->sc_ah
), ATH_DBG_FATAL
,
1677 "dma_mapping_error() on TX\n");
1681 bf
->bf_buf_addr
= bf
->bf_dmacontext
;
1683 /* tag if this is a nullfunc frame to enable PS when AP acks it */
1684 if (ieee80211_is_nullfunc(fc
) && ieee80211_has_pm(fc
)) {
1685 bf
->bf_isnullfunc
= true;
1686 sc
->ps_flags
&= ~PS_NULLFUNC_COMPLETED
;
1688 bf
->bf_isnullfunc
= false;
1690 bf
->bf_tx_aborted
= false;
1695 /* FIXME: tx power */
1696 static void ath_tx_start_dma(struct ath_softc
*sc
, struct ath_buf
*bf
,
1697 struct ath_tx_control
*txctl
)
1699 struct sk_buff
*skb
= bf
->bf_mpdu
;
1700 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
1701 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*)skb
->data
;
1702 struct ath_node
*an
= NULL
;
1703 struct list_head bf_head
;
1704 struct ath_desc
*ds
;
1705 struct ath_atx_tid
*tid
;
1706 struct ath_hw
*ah
= sc
->sc_ah
;
1710 frm_type
= get_hw_packet_type(skb
);
1711 fc
= hdr
->frame_control
;
1713 INIT_LIST_HEAD(&bf_head
);
1714 list_add_tail(&bf
->list
, &bf_head
);
1717 ath9k_hw_set_desc_link(ah
, ds
, 0);
1719 ath9k_hw_set11n_txdesc(ah
, ds
, bf
->bf_frmlen
, frm_type
, MAX_RATE_POWER
,
1720 bf
->bf_keyix
, bf
->bf_keytype
, bf
->bf_flags
);
1722 ath9k_hw_filltxdesc(ah
, ds
,
1723 skb
->len
, /* segment length */
1724 true, /* first segment */
1725 true, /* last segment */
1726 ds
, /* first descriptor */
1728 txctl
->txq
->axq_qnum
);
1730 if (bf
->bf_state
.bfs_paprd
)
1731 ar9003_hw_set_paprd_txdesc(ah
, ds
, bf
->bf_state
.bfs_paprd
);
1733 spin_lock_bh(&txctl
->txq
->axq_lock
);
1735 if (bf_isht(bf
) && (sc
->sc_flags
& SC_OP_TXAGGR
) &&
1736 tx_info
->control
.sta
) {
1737 an
= (struct ath_node
*)tx_info
->control
.sta
->drv_priv
;
1738 tid
= ATH_AN_2_TID(an
, bf
->bf_tidno
);
1740 if (!ieee80211_is_data_qos(fc
)) {
1741 ath_tx_send_normal(sc
, txctl
->txq
, &bf_head
);
1745 if (tx_info
->flags
& IEEE80211_TX_CTL_AMPDU
) {
1747 * Try aggregation if it's a unicast data frame
1748 * and the destination is HT capable.
1750 ath_tx_send_ampdu(sc
, tid
, &bf_head
, txctl
);
1753 * Send this frame as regular when ADDBA
1754 * exchange is neither complete nor pending.
1756 ath_tx_send_ht_normal(sc
, txctl
->txq
,
1760 ath_tx_send_normal(sc
, txctl
->txq
, &bf_head
);
1764 spin_unlock_bh(&txctl
->txq
->axq_lock
);
1767 /* Upon failure caller should free skb */
1768 int ath_tx_start(struct ieee80211_hw
*hw
, struct sk_buff
*skb
,
1769 struct ath_tx_control
*txctl
)
1771 struct ath_wiphy
*aphy
= hw
->priv
;
1772 struct ath_softc
*sc
= aphy
->sc
;
1773 struct ath_common
*common
= ath9k_hw_common(sc
->sc_ah
);
1774 struct ath_txq
*txq
= txctl
->txq
;
1778 bf
= ath_tx_get_buffer(sc
);
1780 ath_print(common
, ATH_DBG_XMIT
, "TX buffers are full\n");
1784 r
= ath_tx_setup_buffer(hw
, bf
, skb
, txctl
);
1786 ath_print(common
, ATH_DBG_FATAL
, "TX mem alloc failure\n");
1788 /* upon ath_tx_processq() this TX queue will be resumed, we
1789 * guarantee this will happen by knowing beforehand that
1790 * we will at least have to run TX completionon one buffer
1792 spin_lock_bh(&txq
->axq_lock
);
1793 if (!txq
->stopped
&& txq
->axq_depth
> 1) {
1794 ath_mac80211_stop_queue(sc
, skb_get_queue_mapping(skb
));
1797 spin_unlock_bh(&txq
->axq_lock
);
1799 ath_tx_return_buffer(sc
, bf
);
1804 q
= skb_get_queue_mapping(skb
);
1808 spin_lock_bh(&txq
->axq_lock
);
1809 if (++sc
->tx
.pending_frames
[q
] > ATH_MAX_QDEPTH
&& !txq
->stopped
) {
1810 ath_mac80211_stop_queue(sc
, skb_get_queue_mapping(skb
));
1813 spin_unlock_bh(&txq
->axq_lock
);
1815 ath_tx_start_dma(sc
, bf
, txctl
);
1820 void ath_tx_cabq(struct ieee80211_hw
*hw
, struct sk_buff
*skb
)
1822 struct ath_wiphy
*aphy
= hw
->priv
;
1823 struct ath_softc
*sc
= aphy
->sc
;
1824 struct ath_common
*common
= ath9k_hw_common(sc
->sc_ah
);
1825 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*) skb
->data
;
1826 int padpos
, padsize
;
1827 struct ieee80211_tx_info
*info
= IEEE80211_SKB_CB(skb
);
1828 struct ath_tx_control txctl
;
1830 memset(&txctl
, 0, sizeof(struct ath_tx_control
));
1833 * As a temporary workaround, assign seq# here; this will likely need
1834 * to be cleaned up to work better with Beacon transmission and virtual
1837 if (info
->flags
& IEEE80211_TX_CTL_ASSIGN_SEQ
) {
1838 if (info
->flags
& IEEE80211_TX_CTL_FIRST_FRAGMENT
)
1839 sc
->tx
.seq_no
+= 0x10;
1840 hdr
->seq_ctrl
&= cpu_to_le16(IEEE80211_SCTL_FRAG
);
1841 hdr
->seq_ctrl
|= cpu_to_le16(sc
->tx
.seq_no
);
1844 /* Add the padding after the header if this is not already done */
1845 padpos
= ath9k_cmn_padpos(hdr
->frame_control
);
1846 padsize
= padpos
& 3;
1847 if (padsize
&& skb
->len
>padpos
) {
1848 if (skb_headroom(skb
) < padsize
) {
1849 ath_print(common
, ATH_DBG_XMIT
,
1850 "TX CABQ padding failed\n");
1851 dev_kfree_skb_any(skb
);
1854 skb_push(skb
, padsize
);
1855 memmove(skb
->data
, skb
->data
+ padsize
, padpos
);
1858 txctl
.txq
= sc
->beacon
.cabq
;
1860 ath_print(common
, ATH_DBG_XMIT
,
1861 "transmitting CABQ packet, skb: %p\n", skb
);
1863 if (ath_tx_start(hw
, skb
, &txctl
) != 0) {
1864 ath_print(common
, ATH_DBG_XMIT
, "CABQ TX failed\n");
1870 dev_kfree_skb_any(skb
);
1877 static void ath_tx_complete(struct ath_softc
*sc
, struct sk_buff
*skb
,
1878 struct ath_wiphy
*aphy
, int tx_flags
)
1880 struct ieee80211_hw
*hw
= sc
->hw
;
1881 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
1882 struct ath_common
*common
= ath9k_hw_common(sc
->sc_ah
);
1883 struct ieee80211_hdr
* hdr
= (struct ieee80211_hdr
*)skb
->data
;
1884 int q
, padpos
, padsize
;
1886 ath_print(common
, ATH_DBG_XMIT
, "TX complete: skb: %p\n", skb
);
1891 if (tx_flags
& ATH_TX_BAR
)
1892 tx_info
->flags
|= IEEE80211_TX_STAT_AMPDU_NO_BACK
;
1894 if (!(tx_flags
& (ATH_TX_ERROR
| ATH_TX_XRETRY
))) {
1895 /* Frame was ACKed */
1896 tx_info
->flags
|= IEEE80211_TX_STAT_ACK
;
1899 padpos
= ath9k_cmn_padpos(hdr
->frame_control
);
1900 padsize
= padpos
& 3;
1901 if (padsize
&& skb
->len
>padpos
+padsize
) {
1903 * Remove MAC header padding before giving the frame back to
1906 memmove(skb
->data
+ padsize
, skb
->data
, padpos
);
1907 skb_pull(skb
, padsize
);
1910 if (sc
->ps_flags
& PS_WAIT_FOR_TX_ACK
) {
1911 sc
->ps_flags
&= ~PS_WAIT_FOR_TX_ACK
;
1912 ath_print(common
, ATH_DBG_PS
,
1913 "Going back to sleep after having "
1914 "received TX status (0x%lx)\n",
1915 sc
->ps_flags
& (PS_WAIT_FOR_BEACON
|
1917 PS_WAIT_FOR_PSPOLL_DATA
|
1918 PS_WAIT_FOR_TX_ACK
));
1921 if (unlikely(tx_info
->pad
[0] & ATH_TX_INFO_FRAME_TYPE_INTERNAL
))
1922 ath9k_tx_status(hw
, skb
);
1924 q
= skb_get_queue_mapping(skb
);
1928 if (--sc
->tx
.pending_frames
[q
] < 0)
1929 sc
->tx
.pending_frames
[q
] = 0;
1931 ieee80211_tx_status(hw
, skb
);
1935 static void ath_tx_complete_buf(struct ath_softc
*sc
, struct ath_buf
*bf
,
1936 struct ath_txq
*txq
, struct list_head
*bf_q
,
1937 struct ath_tx_status
*ts
, int txok
, int sendbar
)
1939 struct sk_buff
*skb
= bf
->bf_mpdu
;
1940 unsigned long flags
;
1944 tx_flags
= ATH_TX_BAR
;
1947 tx_flags
|= ATH_TX_ERROR
;
1949 if (bf_isxretried(bf
))
1950 tx_flags
|= ATH_TX_XRETRY
;
1953 dma_unmap_single(sc
->dev
, bf
->bf_dmacontext
, skb
->len
, DMA_TO_DEVICE
);
1955 if (bf
->bf_state
.bfs_paprd
) {
1956 if (time_after(jiffies
,
1957 bf
->bf_state
.bfs_paprd_timestamp
+
1958 msecs_to_jiffies(ATH_PAPRD_TIMEOUT
)))
1959 dev_kfree_skb_any(skb
);
1961 complete(&sc
->paprd_complete
);
1963 ath_tx_complete(sc
, skb
, bf
->aphy
, tx_flags
);
1964 ath_debug_stat_tx(sc
, txq
, bf
, ts
);
1968 * Return the list of ath_buf of this mpdu to free queue
1970 spin_lock_irqsave(&sc
->tx
.txbuflock
, flags
);
1971 list_splice_tail_init(bf_q
, &sc
->tx
.txbuf
);
1972 spin_unlock_irqrestore(&sc
->tx
.txbuflock
, flags
);
1975 static int ath_tx_num_badfrms(struct ath_softc
*sc
, struct ath_buf
*bf
,
1976 struct ath_tx_status
*ts
, int txok
)
1979 u32 ba
[WME_BA_BMP_SIZE
>> 5];
1984 if (bf
->bf_lastbf
->bf_tx_aborted
)
1987 isaggr
= bf_isaggr(bf
);
1989 seq_st
= ts
->ts_seqnum
;
1990 memcpy(ba
, &ts
->ba_low
, WME_BA_BMP_SIZE
>> 3);
1994 ba_index
= ATH_BA_INDEX(seq_st
, bf
->bf_seqno
);
1995 if (!txok
|| (isaggr
&& !ATH_BA_ISSET(ba
, ba_index
)))
2004 static void ath_tx_rc_status(struct ath_buf
*bf
, struct ath_tx_status
*ts
,
2005 int nbad
, int txok
, bool update_rc
)
2007 struct sk_buff
*skb
= bf
->bf_mpdu
;
2008 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*)skb
->data
;
2009 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
2010 struct ieee80211_hw
*hw
= bf
->aphy
->hw
;
2014 tx_info
->status
.ack_signal
= ts
->ts_rssi
;
2016 tx_rateindex
= ts
->ts_rateindex
;
2017 WARN_ON(tx_rateindex
>= hw
->max_rates
);
2019 if (ts
->ts_status
& ATH9K_TXERR_FILT
)
2020 tx_info
->flags
|= IEEE80211_TX_STAT_TX_FILTERED
;
2021 if ((tx_info
->flags
& IEEE80211_TX_CTL_AMPDU
) && update_rc
)
2022 tx_info
->flags
|= IEEE80211_TX_STAT_AMPDU
;
2024 if ((ts
->ts_status
& ATH9K_TXERR_FILT
) == 0 &&
2025 (bf
->bf_flags
& ATH9K_TXDESC_NOACK
) == 0 && update_rc
) {
2026 if (ieee80211_is_data(hdr
->frame_control
)) {
2028 (ATH9K_TX_DATA_UNDERRUN
| ATH9K_TX_DELIM_UNDERRUN
))
2029 tx_info
->pad
[0] |= ATH_TX_INFO_UNDERRUN
;
2030 if ((ts
->ts_status
& ATH9K_TXERR_XRETRY
) ||
2031 (ts
->ts_status
& ATH9K_TXERR_FIFO
))
2032 tx_info
->pad
[0] |= ATH_TX_INFO_XRETRY
;
2033 tx_info
->status
.ampdu_len
= bf
->bf_nframes
;
2034 tx_info
->status
.ampdu_ack_len
= bf
->bf_nframes
- nbad
;
2038 for (i
= tx_rateindex
+ 1; i
< hw
->max_rates
; i
++) {
2039 tx_info
->status
.rates
[i
].count
= 0;
2040 tx_info
->status
.rates
[i
].idx
= -1;
2043 tx_info
->status
.rates
[tx_rateindex
].count
= ts
->ts_longretry
+ 1;
2046 static void ath_wake_mac80211_queue(struct ath_softc
*sc
, struct ath_txq
*txq
)
2050 qnum
= ath_get_mac80211_qnum(txq
->axq_class
, sc
);
2054 spin_lock_bh(&txq
->axq_lock
);
2055 if (txq
->stopped
&& sc
->tx
.pending_frames
[qnum
] < ATH_MAX_QDEPTH
) {
2056 ath_mac80211_start_queue(sc
, qnum
);
2059 spin_unlock_bh(&txq
->axq_lock
);
2062 static void ath_tx_processq(struct ath_softc
*sc
, struct ath_txq
*txq
)
2064 struct ath_hw
*ah
= sc
->sc_ah
;
2065 struct ath_common
*common
= ath9k_hw_common(ah
);
2066 struct ath_buf
*bf
, *lastbf
, *bf_held
= NULL
;
2067 struct list_head bf_head
;
2068 struct ath_desc
*ds
;
2069 struct ath_tx_status ts
;
2073 ath_print(common
, ATH_DBG_QUEUE
, "tx queue %d (%x), link %p\n",
2074 txq
->axq_qnum
, ath9k_hw_gettxbuf(sc
->sc_ah
, txq
->axq_qnum
),
2078 spin_lock_bh(&txq
->axq_lock
);
2079 if (list_empty(&txq
->axq_q
)) {
2080 txq
->axq_link
= NULL
;
2081 spin_unlock_bh(&txq
->axq_lock
);
2084 bf
= list_first_entry(&txq
->axq_q
, struct ath_buf
, list
);
2087 * There is a race condition that a BH gets scheduled
2088 * after sw writes TxE and before hw re-load the last
2089 * descriptor to get the newly chained one.
2090 * Software must keep the last DONE descriptor as a
2091 * holding descriptor - software does so by marking
2092 * it with the STALE flag.
2097 if (list_is_last(&bf_held
->list
, &txq
->axq_q
)) {
2098 spin_unlock_bh(&txq
->axq_lock
);
2101 bf
= list_entry(bf_held
->list
.next
,
2102 struct ath_buf
, list
);
2106 lastbf
= bf
->bf_lastbf
;
2107 ds
= lastbf
->bf_desc
;
2109 memset(&ts
, 0, sizeof(ts
));
2110 status
= ath9k_hw_txprocdesc(ah
, ds
, &ts
);
2111 if (status
== -EINPROGRESS
) {
2112 spin_unlock_bh(&txq
->axq_lock
);
2117 * We now know the nullfunc frame has been ACKed so we
2120 if (bf
->bf_isnullfunc
&&
2121 (ts
.ts_status
& ATH9K_TX_ACKED
)) {
2122 if ((sc
->ps_flags
& PS_ENABLED
))
2123 ath9k_enable_ps(sc
);
2125 sc
->ps_flags
|= PS_NULLFUNC_COMPLETED
;
2129 * Remove ath_buf's of the same transmit unit from txq,
2130 * however leave the last descriptor back as the holding
2131 * descriptor for hw.
2133 lastbf
->bf_stale
= true;
2134 INIT_LIST_HEAD(&bf_head
);
2135 if (!list_is_singular(&lastbf
->list
))
2136 list_cut_position(&bf_head
,
2137 &txq
->axq_q
, lastbf
->list
.prev
);
2140 txok
= !(ts
.ts_status
& ATH9K_TXERR_MASK
);
2141 txq
->axq_tx_inprogress
= false;
2143 list_del(&bf_held
->list
);
2144 spin_unlock_bh(&txq
->axq_lock
);
2147 ath_tx_return_buffer(sc
, bf_held
);
2149 if (!bf_isampdu(bf
)) {
2151 * This frame is sent out as a single frame.
2152 * Use hardware retry status for this frame.
2154 if (ts
.ts_status
& ATH9K_TXERR_XRETRY
)
2155 bf
->bf_state
.bf_type
|= BUF_XRETRY
;
2156 ath_tx_rc_status(bf
, &ts
, 0, txok
, true);
2160 ath_tx_complete_aggr(sc
, txq
, bf
, &bf_head
, &ts
, txok
);
2162 ath_tx_complete_buf(sc
, bf
, txq
, &bf_head
, &ts
, txok
, 0);
2164 ath_wake_mac80211_queue(sc
, txq
);
2166 spin_lock_bh(&txq
->axq_lock
);
2167 if (sc
->sc_flags
& SC_OP_TXAGGR
)
2168 ath_txq_schedule(sc
, txq
);
2169 spin_unlock_bh(&txq
->axq_lock
);
2173 static void ath_tx_complete_poll_work(struct work_struct
*work
)
2175 struct ath_softc
*sc
= container_of(work
, struct ath_softc
,
2176 tx_complete_work
.work
);
2177 struct ath_txq
*txq
;
2179 bool needreset
= false;
2181 for (i
= 0; i
< ATH9K_NUM_TX_QUEUES
; i
++)
2182 if (ATH_TXQ_SETUP(sc
, i
)) {
2183 txq
= &sc
->tx
.txq
[i
];
2184 spin_lock_bh(&txq
->axq_lock
);
2185 if (txq
->axq_depth
) {
2186 if (txq
->axq_tx_inprogress
) {
2188 spin_unlock_bh(&txq
->axq_lock
);
2191 txq
->axq_tx_inprogress
= true;
2194 spin_unlock_bh(&txq
->axq_lock
);
2198 ath_print(ath9k_hw_common(sc
->sc_ah
), ATH_DBG_RESET
,
2199 "tx hung, resetting the chip\n");
2200 ath9k_ps_wakeup(sc
);
2201 ath_reset(sc
, false);
2202 ath9k_ps_restore(sc
);
2205 ieee80211_queue_delayed_work(sc
->hw
, &sc
->tx_complete_work
,
2206 msecs_to_jiffies(ATH_TX_COMPLETE_POLL_INT
));
2211 void ath_tx_tasklet(struct ath_softc
*sc
)
2214 u32 qcumask
= ((1 << ATH9K_NUM_TX_QUEUES
) - 1);
2216 ath9k_hw_gettxintrtxqs(sc
->sc_ah
, &qcumask
);
2218 for (i
= 0; i
< ATH9K_NUM_TX_QUEUES
; i
++) {
2219 if (ATH_TXQ_SETUP(sc
, i
) && (qcumask
& (1 << i
)))
2220 ath_tx_processq(sc
, &sc
->tx
.txq
[i
]);
2224 void ath_tx_edma_tasklet(struct ath_softc
*sc
)
2226 struct ath_tx_status txs
;
2227 struct ath_common
*common
= ath9k_hw_common(sc
->sc_ah
);
2228 struct ath_hw
*ah
= sc
->sc_ah
;
2229 struct ath_txq
*txq
;
2230 struct ath_buf
*bf
, *lastbf
;
2231 struct list_head bf_head
;
2236 status
= ath9k_hw_txprocdesc(ah
, NULL
, (void *)&txs
);
2237 if (status
== -EINPROGRESS
)
2239 if (status
== -EIO
) {
2240 ath_print(common
, ATH_DBG_XMIT
,
2241 "Error processing tx status\n");
2245 /* Skip beacon completions */
2246 if (txs
.qid
== sc
->beacon
.beaconq
)
2249 txq
= &sc
->tx
.txq
[txs
.qid
];
2251 spin_lock_bh(&txq
->axq_lock
);
2252 if (list_empty(&txq
->txq_fifo
[txq
->txq_tailidx
])) {
2253 spin_unlock_bh(&txq
->axq_lock
);
2257 bf
= list_first_entry(&txq
->txq_fifo
[txq
->txq_tailidx
],
2258 struct ath_buf
, list
);
2259 lastbf
= bf
->bf_lastbf
;
2261 INIT_LIST_HEAD(&bf_head
);
2262 list_cut_position(&bf_head
, &txq
->txq_fifo
[txq
->txq_tailidx
],
2264 INCR(txq
->txq_tailidx
, ATH_TXFIFO_DEPTH
);
2266 txq
->axq_tx_inprogress
= false;
2267 spin_unlock_bh(&txq
->axq_lock
);
2269 txok
= !(txs
.ts_status
& ATH9K_TXERR_MASK
);
2272 * Make sure null func frame is acked before configuring
2275 if (bf
->bf_isnullfunc
&& txok
) {
2276 if ((sc
->ps_flags
& PS_ENABLED
))
2277 ath9k_enable_ps(sc
);
2279 sc
->ps_flags
|= PS_NULLFUNC_COMPLETED
;
2282 if (!bf_isampdu(bf
)) {
2283 if (txs
.ts_status
& ATH9K_TXERR_XRETRY
)
2284 bf
->bf_state
.bf_type
|= BUF_XRETRY
;
2285 ath_tx_rc_status(bf
, &txs
, 0, txok
, true);
2289 ath_tx_complete_aggr(sc
, txq
, bf
, &bf_head
, &txs
, txok
);
2291 ath_tx_complete_buf(sc
, bf
, txq
, &bf_head
,
2294 ath_wake_mac80211_queue(sc
, txq
);
2296 spin_lock_bh(&txq
->axq_lock
);
2297 if (!list_empty(&txq
->txq_fifo_pending
)) {
2298 INIT_LIST_HEAD(&bf_head
);
2299 bf
= list_first_entry(&txq
->txq_fifo_pending
,
2300 struct ath_buf
, list
);
2301 list_cut_position(&bf_head
, &txq
->txq_fifo_pending
,
2302 &bf
->bf_lastbf
->list
);
2303 ath_tx_txqaddbuf(sc
, txq
, &bf_head
);
2304 } else if (sc
->sc_flags
& SC_OP_TXAGGR
)
2305 ath_txq_schedule(sc
, txq
);
2306 spin_unlock_bh(&txq
->axq_lock
);
2314 static int ath_txstatus_setup(struct ath_softc
*sc
, int size
)
2316 struct ath_descdma
*dd
= &sc
->txsdma
;
2317 u8 txs_len
= sc
->sc_ah
->caps
.txs_len
;
2319 dd
->dd_desc_len
= size
* txs_len
;
2320 dd
->dd_desc
= dma_alloc_coherent(sc
->dev
, dd
->dd_desc_len
,
2321 &dd
->dd_desc_paddr
, GFP_KERNEL
);
2328 static int ath_tx_edma_init(struct ath_softc
*sc
)
2332 err
= ath_txstatus_setup(sc
, ATH_TXSTATUS_RING_SIZE
);
2334 ath9k_hw_setup_statusring(sc
->sc_ah
, sc
->txsdma
.dd_desc
,
2335 sc
->txsdma
.dd_desc_paddr
,
2336 ATH_TXSTATUS_RING_SIZE
);
2341 static void ath_tx_edma_cleanup(struct ath_softc
*sc
)
2343 struct ath_descdma
*dd
= &sc
->txsdma
;
2345 dma_free_coherent(sc
->dev
, dd
->dd_desc_len
, dd
->dd_desc
,
2349 int ath_tx_init(struct ath_softc
*sc
, int nbufs
)
2351 struct ath_common
*common
= ath9k_hw_common(sc
->sc_ah
);
2354 spin_lock_init(&sc
->tx
.txbuflock
);
2356 error
= ath_descdma_setup(sc
, &sc
->tx
.txdma
, &sc
->tx
.txbuf
,
2359 ath_print(common
, ATH_DBG_FATAL
,
2360 "Failed to allocate tx descriptors: %d\n", error
);
2364 error
= ath_descdma_setup(sc
, &sc
->beacon
.bdma
, &sc
->beacon
.bbuf
,
2365 "beacon", ATH_BCBUF
, 1, 1);
2367 ath_print(common
, ATH_DBG_FATAL
,
2368 "Failed to allocate beacon descriptors: %d\n", error
);
2372 INIT_DELAYED_WORK(&sc
->tx_complete_work
, ath_tx_complete_poll_work
);
2374 if (sc
->sc_ah
->caps
.hw_caps
& ATH9K_HW_CAP_EDMA
) {
2375 error
= ath_tx_edma_init(sc
);
2387 void ath_tx_cleanup(struct ath_softc
*sc
)
2389 if (sc
->beacon
.bdma
.dd_desc_len
!= 0)
2390 ath_descdma_cleanup(sc
, &sc
->beacon
.bdma
, &sc
->beacon
.bbuf
);
2392 if (sc
->tx
.txdma
.dd_desc_len
!= 0)
2393 ath_descdma_cleanup(sc
, &sc
->tx
.txdma
, &sc
->tx
.txbuf
);
2395 if (sc
->sc_ah
->caps
.hw_caps
& ATH9K_HW_CAP_EDMA
)
2396 ath_tx_edma_cleanup(sc
);
2399 void ath_tx_node_init(struct ath_softc
*sc
, struct ath_node
*an
)
2401 struct ath_atx_tid
*tid
;
2402 struct ath_atx_ac
*ac
;
2405 for (tidno
= 0, tid
= &an
->tid
[tidno
];
2406 tidno
< WME_NUM_TID
;
2410 tid
->seq_start
= tid
->seq_next
= 0;
2411 tid
->baw_size
= WME_MAX_BA
;
2412 tid
->baw_head
= tid
->baw_tail
= 0;
2414 tid
->paused
= false;
2415 tid
->state
&= ~AGGR_CLEANUP
;
2416 INIT_LIST_HEAD(&tid
->buf_q
);
2417 acno
= TID_TO_WME_AC(tidno
);
2418 tid
->ac
= &an
->ac
[acno
];
2419 tid
->state
&= ~AGGR_ADDBA_COMPLETE
;
2420 tid
->state
&= ~AGGR_ADDBA_PROGRESS
;
2423 for (acno
= 0, ac
= &an
->ac
[acno
];
2424 acno
< WME_NUM_AC
; acno
++, ac
++) {
2426 ac
->qnum
= sc
->tx
.hwq_map
[acno
];
2427 INIT_LIST_HEAD(&ac
->tid_q
);
2431 void ath_tx_node_cleanup(struct ath_softc
*sc
, struct ath_node
*an
)
2433 struct ath_atx_ac
*ac
;
2434 struct ath_atx_tid
*tid
;
2435 struct ath_txq
*txq
;
2438 for (tidno
= 0, tid
= &an
->tid
[tidno
];
2439 tidno
< WME_NUM_TID
; tidno
++, tid
++) {
2442 if (!ATH_TXQ_SETUP(sc
, i
))
2445 txq
= &sc
->tx
.txq
[i
];
2448 spin_lock_bh(&txq
->axq_lock
);
2451 list_del(&tid
->list
);
2456 list_del(&ac
->list
);
2457 tid
->ac
->sched
= false;
2460 ath_tid_drain(sc
, txq
, tid
);
2461 tid
->state
&= ~AGGR_ADDBA_COMPLETE
;
2462 tid
->state
&= ~AGGR_CLEANUP
;
2464 spin_unlock_bh(&txq
->axq_lock
);