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ath9k: fix queue stopping threshold
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / xmit.c
1 /*
2 * Copyright (c) 2008-2009 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include "ath9k.h"
18 #include "ar9003_mac.h"
19
20 #define BITS_PER_BYTE 8
21 #define OFDM_PLCP_BITS 22
22 #define HT_RC_2_MCS(_rc) ((_rc) & 0x1f)
23 #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
24 #define L_STF 8
25 #define L_LTF 8
26 #define L_SIG 4
27 #define HT_SIG 8
28 #define HT_STF 4
29 #define HT_LTF(_ns) (4 * (_ns))
30 #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */
31 #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */
32 #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
33 #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
34
35 #define OFDM_SIFS_TIME 16
36
37 static u16 bits_per_symbol[][2] = {
38 /* 20MHz 40MHz */
39 { 26, 54 }, /* 0: BPSK */
40 { 52, 108 }, /* 1: QPSK 1/2 */
41 { 78, 162 }, /* 2: QPSK 3/4 */
42 { 104, 216 }, /* 3: 16-QAM 1/2 */
43 { 156, 324 }, /* 4: 16-QAM 3/4 */
44 { 208, 432 }, /* 5: 64-QAM 2/3 */
45 { 234, 486 }, /* 6: 64-QAM 3/4 */
46 { 260, 540 }, /* 7: 64-QAM 5/6 */
47 };
48
49 #define IS_HT_RATE(_rate) ((_rate) & 0x80)
50
51 static void ath_tx_send_ht_normal(struct ath_softc *sc, struct ath_txq *txq,
52 struct ath_atx_tid *tid,
53 struct list_head *bf_head);
54 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
55 struct ath_txq *txq, struct list_head *bf_q,
56 struct ath_tx_status *ts, int txok, int sendbar);
57 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
58 struct list_head *head);
59 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf);
60 static int ath_tx_num_badfrms(struct ath_softc *sc, struct ath_buf *bf,
61 struct ath_tx_status *ts, int txok);
62 static void ath_tx_rc_status(struct ath_buf *bf, struct ath_tx_status *ts,
63 int nbad, int txok, bool update_rc);
64
65 enum {
66 MCS_HT20,
67 MCS_HT20_SGI,
68 MCS_HT40,
69 MCS_HT40_SGI,
70 };
71
72 static int ath_max_4ms_framelen[4][32] = {
73 [MCS_HT20] = {
74 3212, 6432, 9648, 12864, 19300, 25736, 28952, 32172,
75 6424, 12852, 19280, 25708, 38568, 51424, 57852, 64280,
76 9628, 19260, 28896, 38528, 57792, 65532, 65532, 65532,
77 12828, 25656, 38488, 51320, 65532, 65532, 65532, 65532,
78 },
79 [MCS_HT20_SGI] = {
80 3572, 7144, 10720, 14296, 21444, 28596, 32172, 35744,
81 7140, 14284, 21428, 28568, 42856, 57144, 64288, 65532,
82 10700, 21408, 32112, 42816, 64228, 65532, 65532, 65532,
83 14256, 28516, 42780, 57040, 65532, 65532, 65532, 65532,
84 },
85 [MCS_HT40] = {
86 6680, 13360, 20044, 26724, 40092, 53456, 60140, 65532,
87 13348, 26700, 40052, 53400, 65532, 65532, 65532, 65532,
88 20004, 40008, 60016, 65532, 65532, 65532, 65532, 65532,
89 26644, 53292, 65532, 65532, 65532, 65532, 65532, 65532,
90 },
91 [MCS_HT40_SGI] = {
92 7420, 14844, 22272, 29696, 44544, 59396, 65532, 65532,
93 14832, 29668, 44504, 59340, 65532, 65532, 65532, 65532,
94 22232, 44464, 65532, 65532, 65532, 65532, 65532, 65532,
95 29616, 59232, 65532, 65532, 65532, 65532, 65532, 65532,
96 }
97 };
98
99 /*********************/
100 /* Aggregation logic */
101 /*********************/
102
103 static void ath_tx_queue_tid(struct ath_txq *txq, struct ath_atx_tid *tid)
104 {
105 struct ath_atx_ac *ac = tid->ac;
106
107 if (tid->paused)
108 return;
109
110 if (tid->sched)
111 return;
112
113 tid->sched = true;
114 list_add_tail(&tid->list, &ac->tid_q);
115
116 if (ac->sched)
117 return;
118
119 ac->sched = true;
120 list_add_tail(&ac->list, &txq->axq_acq);
121 }
122
123 static void ath_tx_pause_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
124 {
125 struct ath_txq *txq = &sc->tx.txq[tid->ac->qnum];
126
127 spin_lock_bh(&txq->axq_lock);
128 tid->paused++;
129 spin_unlock_bh(&txq->axq_lock);
130 }
131
132 static void ath_tx_resume_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
133 {
134 struct ath_txq *txq = &sc->tx.txq[tid->ac->qnum];
135
136 BUG_ON(tid->paused <= 0);
137 spin_lock_bh(&txq->axq_lock);
138
139 tid->paused--;
140
141 if (tid->paused > 0)
142 goto unlock;
143
144 if (list_empty(&tid->buf_q))
145 goto unlock;
146
147 ath_tx_queue_tid(txq, tid);
148 ath_txq_schedule(sc, txq);
149 unlock:
150 spin_unlock_bh(&txq->axq_lock);
151 }
152
153 static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
154 {
155 struct ath_txq *txq = &sc->tx.txq[tid->ac->qnum];
156 struct ath_buf *bf;
157 struct list_head bf_head;
158 INIT_LIST_HEAD(&bf_head);
159
160 BUG_ON(tid->paused <= 0);
161 spin_lock_bh(&txq->axq_lock);
162
163 tid->paused--;
164
165 if (tid->paused > 0) {
166 spin_unlock_bh(&txq->axq_lock);
167 return;
168 }
169
170 while (!list_empty(&tid->buf_q)) {
171 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
172 BUG_ON(bf_isretried(bf));
173 list_move_tail(&bf->list, &bf_head);
174 ath_tx_send_ht_normal(sc, txq, tid, &bf_head);
175 }
176
177 spin_unlock_bh(&txq->axq_lock);
178 }
179
180 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
181 int seqno)
182 {
183 int index, cindex;
184
185 index = ATH_BA_INDEX(tid->seq_start, seqno);
186 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
187
188 tid->tx_buf[cindex] = NULL;
189
190 while (tid->baw_head != tid->baw_tail && !tid->tx_buf[tid->baw_head]) {
191 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
192 INCR(tid->baw_head, ATH_TID_MAX_BUFS);
193 }
194 }
195
196 static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
197 struct ath_buf *bf)
198 {
199 int index, cindex;
200
201 if (bf_isretried(bf))
202 return;
203
204 index = ATH_BA_INDEX(tid->seq_start, bf->bf_seqno);
205 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
206
207 BUG_ON(tid->tx_buf[cindex] != NULL);
208 tid->tx_buf[cindex] = bf;
209
210 if (index >= ((tid->baw_tail - tid->baw_head) &
211 (ATH_TID_MAX_BUFS - 1))) {
212 tid->baw_tail = cindex;
213 INCR(tid->baw_tail, ATH_TID_MAX_BUFS);
214 }
215 }
216
217 /*
218 * TODO: For frame(s) that are in the retry state, we will reuse the
219 * sequence number(s) without setting the retry bit. The
220 * alternative is to give up on these and BAR the receiver's window
221 * forward.
222 */
223 static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq,
224 struct ath_atx_tid *tid)
225
226 {
227 struct ath_buf *bf;
228 struct list_head bf_head;
229 struct ath_tx_status ts;
230
231 memset(&ts, 0, sizeof(ts));
232 INIT_LIST_HEAD(&bf_head);
233
234 for (;;) {
235 if (list_empty(&tid->buf_q))
236 break;
237
238 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
239 list_move_tail(&bf->list, &bf_head);
240
241 if (bf_isretried(bf))
242 ath_tx_update_baw(sc, tid, bf->bf_seqno);
243
244 spin_unlock(&txq->axq_lock);
245 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 0);
246 spin_lock(&txq->axq_lock);
247 }
248
249 tid->seq_next = tid->seq_start;
250 tid->baw_tail = tid->baw_head;
251 }
252
253 static void ath_tx_set_retry(struct ath_softc *sc, struct ath_txq *txq,
254 struct ath_buf *bf)
255 {
256 struct sk_buff *skb;
257 struct ieee80211_hdr *hdr;
258
259 bf->bf_state.bf_type |= BUF_RETRY;
260 bf->bf_retries++;
261 TX_STAT_INC(txq->axq_qnum, a_retries);
262
263 skb = bf->bf_mpdu;
264 hdr = (struct ieee80211_hdr *)skb->data;
265 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY);
266 }
267
268 static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc)
269 {
270 struct ath_buf *bf = NULL;
271
272 spin_lock_bh(&sc->tx.txbuflock);
273
274 if (unlikely(list_empty(&sc->tx.txbuf))) {
275 spin_unlock_bh(&sc->tx.txbuflock);
276 return NULL;
277 }
278
279 bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list);
280 list_del(&bf->list);
281
282 spin_unlock_bh(&sc->tx.txbuflock);
283
284 return bf;
285 }
286
287 static void ath_tx_return_buffer(struct ath_softc *sc, struct ath_buf *bf)
288 {
289 spin_lock_bh(&sc->tx.txbuflock);
290 list_add_tail(&bf->list, &sc->tx.txbuf);
291 spin_unlock_bh(&sc->tx.txbuflock);
292 }
293
294 static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf)
295 {
296 struct ath_buf *tbf;
297
298 tbf = ath_tx_get_buffer(sc);
299 if (WARN_ON(!tbf))
300 return NULL;
301
302 ATH_TXBUF_RESET(tbf);
303
304 tbf->aphy = bf->aphy;
305 tbf->bf_mpdu = bf->bf_mpdu;
306 tbf->bf_buf_addr = bf->bf_buf_addr;
307 memcpy(tbf->bf_desc, bf->bf_desc, sc->sc_ah->caps.tx_desc_len);
308 tbf->bf_state = bf->bf_state;
309 tbf->bf_dmacontext = bf->bf_dmacontext;
310
311 return tbf;
312 }
313
314 static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
315 struct ath_buf *bf, struct list_head *bf_q,
316 struct ath_tx_status *ts, int txok)
317 {
318 struct ath_node *an = NULL;
319 struct sk_buff *skb;
320 struct ieee80211_sta *sta;
321 struct ieee80211_hw *hw;
322 struct ieee80211_hdr *hdr;
323 struct ieee80211_tx_info *tx_info;
324 struct ath_atx_tid *tid = NULL;
325 struct ath_buf *bf_next, *bf_last = bf->bf_lastbf;
326 struct list_head bf_head, bf_pending;
327 u16 seq_st = 0, acked_cnt = 0, txfail_cnt = 0;
328 u32 ba[WME_BA_BMP_SIZE >> 5];
329 int isaggr, txfail, txpending, sendbar = 0, needreset = 0, nbad = 0;
330 bool rc_update = true;
331
332 skb = bf->bf_mpdu;
333 hdr = (struct ieee80211_hdr *)skb->data;
334
335 tx_info = IEEE80211_SKB_CB(skb);
336 hw = bf->aphy->hw;
337
338 rcu_read_lock();
339
340 /* XXX: use ieee80211_find_sta! */
341 sta = ieee80211_find_sta_by_hw(hw, hdr->addr1);
342 if (!sta) {
343 rcu_read_unlock();
344 return;
345 }
346
347 an = (struct ath_node *)sta->drv_priv;
348 tid = ATH_AN_2_TID(an, bf->bf_tidno);
349
350 isaggr = bf_isaggr(bf);
351 memset(ba, 0, WME_BA_BMP_SIZE >> 3);
352
353 if (isaggr && txok) {
354 if (ts->ts_flags & ATH9K_TX_BA) {
355 seq_st = ts->ts_seqnum;
356 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
357 } else {
358 /*
359 * AR5416 can become deaf/mute when BA
360 * issue happens. Chip needs to be reset.
361 * But AP code may have sychronization issues
362 * when perform internal reset in this routine.
363 * Only enable reset in STA mode for now.
364 */
365 if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION)
366 needreset = 1;
367 }
368 }
369
370 INIT_LIST_HEAD(&bf_pending);
371 INIT_LIST_HEAD(&bf_head);
372
373 nbad = ath_tx_num_badfrms(sc, bf, ts, txok);
374 while (bf) {
375 txfail = txpending = 0;
376 bf_next = bf->bf_next;
377
378 if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, bf->bf_seqno))) {
379 /* transmit completion, subframe is
380 * acked by block ack */
381 acked_cnt++;
382 } else if (!isaggr && txok) {
383 /* transmit completion */
384 acked_cnt++;
385 } else {
386 if (!(tid->state & AGGR_CLEANUP) &&
387 !bf_last->bf_tx_aborted) {
388 if (bf->bf_retries < ATH_MAX_SW_RETRIES) {
389 ath_tx_set_retry(sc, txq, bf);
390 txpending = 1;
391 } else {
392 bf->bf_state.bf_type |= BUF_XRETRY;
393 txfail = 1;
394 sendbar = 1;
395 txfail_cnt++;
396 }
397 } else {
398 /*
399 * cleanup in progress, just fail
400 * the un-acked sub-frames
401 */
402 txfail = 1;
403 }
404 }
405
406 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
407 bf_next == NULL) {
408 /*
409 * Make sure the last desc is reclaimed if it
410 * not a holding desc.
411 */
412 if (!bf_last->bf_stale)
413 list_move_tail(&bf->list, &bf_head);
414 else
415 INIT_LIST_HEAD(&bf_head);
416 } else {
417 BUG_ON(list_empty(bf_q));
418 list_move_tail(&bf->list, &bf_head);
419 }
420
421 if (!txpending) {
422 /*
423 * complete the acked-ones/xretried ones; update
424 * block-ack window
425 */
426 spin_lock_bh(&txq->axq_lock);
427 ath_tx_update_baw(sc, tid, bf->bf_seqno);
428 spin_unlock_bh(&txq->axq_lock);
429
430 if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) {
431 ath_tx_rc_status(bf, ts, nbad, txok, true);
432 rc_update = false;
433 } else {
434 ath_tx_rc_status(bf, ts, nbad, txok, false);
435 }
436
437 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts,
438 !txfail, sendbar);
439 } else {
440 /* retry the un-acked ones */
441 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)) {
442 if (bf->bf_next == NULL && bf_last->bf_stale) {
443 struct ath_buf *tbf;
444
445 tbf = ath_clone_txbuf(sc, bf_last);
446 /*
447 * Update tx baw and complete the
448 * frame with failed status if we
449 * run out of tx buf.
450 */
451 if (!tbf) {
452 spin_lock_bh(&txq->axq_lock);
453 ath_tx_update_baw(sc, tid,
454 bf->bf_seqno);
455 spin_unlock_bh(&txq->axq_lock);
456
457 bf->bf_state.bf_type |=
458 BUF_XRETRY;
459 ath_tx_rc_status(bf, ts, nbad,
460 0, false);
461 ath_tx_complete_buf(sc, bf, txq,
462 &bf_head,
463 ts, 0, 0);
464 break;
465 }
466
467 ath9k_hw_cleartxdesc(sc->sc_ah,
468 tbf->bf_desc);
469 list_add_tail(&tbf->list, &bf_head);
470 } else {
471 /*
472 * Clear descriptor status words for
473 * software retry
474 */
475 ath9k_hw_cleartxdesc(sc->sc_ah,
476 bf->bf_desc);
477 }
478 }
479
480 /*
481 * Put this buffer to the temporary pending
482 * queue to retain ordering
483 */
484 list_splice_tail_init(&bf_head, &bf_pending);
485 }
486
487 bf = bf_next;
488 }
489
490 if (tid->state & AGGR_CLEANUP) {
491 if (tid->baw_head == tid->baw_tail) {
492 tid->state &= ~AGGR_ADDBA_COMPLETE;
493 tid->state &= ~AGGR_CLEANUP;
494
495 /* send buffered frames as singles */
496 ath_tx_flush_tid(sc, tid);
497 }
498 rcu_read_unlock();
499 return;
500 }
501
502 /* prepend un-acked frames to the beginning of the pending frame queue */
503 if (!list_empty(&bf_pending)) {
504 spin_lock_bh(&txq->axq_lock);
505 list_splice(&bf_pending, &tid->buf_q);
506 ath_tx_queue_tid(txq, tid);
507 spin_unlock_bh(&txq->axq_lock);
508 }
509
510 rcu_read_unlock();
511
512 if (needreset)
513 ath_reset(sc, false);
514 }
515
516 static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf,
517 struct ath_atx_tid *tid)
518 {
519 struct sk_buff *skb;
520 struct ieee80211_tx_info *tx_info;
521 struct ieee80211_tx_rate *rates;
522 u32 max_4ms_framelen, frmlen;
523 u16 aggr_limit, legacy = 0;
524 int i;
525
526 skb = bf->bf_mpdu;
527 tx_info = IEEE80211_SKB_CB(skb);
528 rates = tx_info->control.rates;
529
530 /*
531 * Find the lowest frame length among the rate series that will have a
532 * 4ms transmit duration.
533 * TODO - TXOP limit needs to be considered.
534 */
535 max_4ms_framelen = ATH_AMPDU_LIMIT_MAX;
536
537 for (i = 0; i < 4; i++) {
538 if (rates[i].count) {
539 int modeidx;
540 if (!(rates[i].flags & IEEE80211_TX_RC_MCS)) {
541 legacy = 1;
542 break;
543 }
544
545 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
546 modeidx = MCS_HT40;
547 else
548 modeidx = MCS_HT20;
549
550 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
551 modeidx++;
552
553 frmlen = ath_max_4ms_framelen[modeidx][rates[i].idx];
554 max_4ms_framelen = min(max_4ms_framelen, frmlen);
555 }
556 }
557
558 /*
559 * limit aggregate size by the minimum rate if rate selected is
560 * not a probe rate, if rate selected is a probe rate then
561 * avoid aggregation of this packet.
562 */
563 if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy)
564 return 0;
565
566 if (sc->sc_flags & SC_OP_BT_PRIORITY_DETECTED)
567 aggr_limit = min((max_4ms_framelen * 3) / 8,
568 (u32)ATH_AMPDU_LIMIT_MAX);
569 else
570 aggr_limit = min(max_4ms_framelen,
571 (u32)ATH_AMPDU_LIMIT_MAX);
572
573 /*
574 * h/w can accept aggregates upto 16 bit lengths (65535).
575 * The IE, however can hold upto 65536, which shows up here
576 * as zero. Ignore 65536 since we are constrained by hw.
577 */
578 if (tid->an->maxampdu)
579 aggr_limit = min(aggr_limit, tid->an->maxampdu);
580
581 return aggr_limit;
582 }
583
584 /*
585 * Returns the number of delimiters to be added to
586 * meet the minimum required mpdudensity.
587 */
588 static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid,
589 struct ath_buf *bf, u16 frmlen)
590 {
591 struct sk_buff *skb = bf->bf_mpdu;
592 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
593 u32 nsymbits, nsymbols;
594 u16 minlen;
595 u8 flags, rix;
596 int width, streams, half_gi, ndelim, mindelim;
597
598 /* Select standard number of delimiters based on frame length alone */
599 ndelim = ATH_AGGR_GET_NDELIM(frmlen);
600
601 /*
602 * If encryption enabled, hardware requires some more padding between
603 * subframes.
604 * TODO - this could be improved to be dependent on the rate.
605 * The hardware can keep up at lower rates, but not higher rates
606 */
607 if (bf->bf_keytype != ATH9K_KEY_TYPE_CLEAR)
608 ndelim += ATH_AGGR_ENCRYPTDELIM;
609
610 /*
611 * Convert desired mpdu density from microeconds to bytes based
612 * on highest rate in rate series (i.e. first rate) to determine
613 * required minimum length for subframe. Take into account
614 * whether high rate is 20 or 40Mhz and half or full GI.
615 *
616 * If there is no mpdu density restriction, no further calculation
617 * is needed.
618 */
619
620 if (tid->an->mpdudensity == 0)
621 return ndelim;
622
623 rix = tx_info->control.rates[0].idx;
624 flags = tx_info->control.rates[0].flags;
625 width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0;
626 half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0;
627
628 if (half_gi)
629 nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(tid->an->mpdudensity);
630 else
631 nsymbols = NUM_SYMBOLS_PER_USEC(tid->an->mpdudensity);
632
633 if (nsymbols == 0)
634 nsymbols = 1;
635
636 streams = HT_RC_2_STREAMS(rix);
637 nsymbits = bits_per_symbol[rix % 8][width] * streams;
638 minlen = (nsymbols * nsymbits) / BITS_PER_BYTE;
639
640 if (frmlen < minlen) {
641 mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ;
642 ndelim = max(mindelim, ndelim);
643 }
644
645 return ndelim;
646 }
647
648 static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc,
649 struct ath_txq *txq,
650 struct ath_atx_tid *tid,
651 struct list_head *bf_q)
652 {
653 #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
654 struct ath_buf *bf, *bf_first, *bf_prev = NULL;
655 int rl = 0, nframes = 0, ndelim, prev_al = 0;
656 u16 aggr_limit = 0, al = 0, bpad = 0,
657 al_delta, h_baw = tid->baw_size / 2;
658 enum ATH_AGGR_STATUS status = ATH_AGGR_DONE;
659
660 bf_first = list_first_entry(&tid->buf_q, struct ath_buf, list);
661
662 do {
663 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
664
665 /* do not step over block-ack window */
666 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, bf->bf_seqno)) {
667 status = ATH_AGGR_BAW_CLOSED;
668 break;
669 }
670
671 if (!rl) {
672 aggr_limit = ath_lookup_rate(sc, bf, tid);
673 rl = 1;
674 }
675
676 /* do not exceed aggregation limit */
677 al_delta = ATH_AGGR_DELIM_SZ + bf->bf_frmlen;
678
679 if (nframes &&
680 (aggr_limit < (al + bpad + al_delta + prev_al))) {
681 status = ATH_AGGR_LIMITED;
682 break;
683 }
684
685 /* do not exceed subframe limit */
686 if (nframes >= min((int)h_baw, ATH_AMPDU_SUBFRAME_DEFAULT)) {
687 status = ATH_AGGR_LIMITED;
688 break;
689 }
690 nframes++;
691
692 /* add padding for previous frame to aggregation length */
693 al += bpad + al_delta;
694
695 /*
696 * Get the delimiters needed to meet the MPDU
697 * density for this node.
698 */
699 ndelim = ath_compute_num_delims(sc, tid, bf_first, bf->bf_frmlen);
700 bpad = PADBYTES(al_delta) + (ndelim << 2);
701
702 bf->bf_next = NULL;
703 ath9k_hw_set_desc_link(sc->sc_ah, bf->bf_desc, 0);
704
705 /* link buffers of this frame to the aggregate */
706 ath_tx_addto_baw(sc, tid, bf);
707 ath9k_hw_set11n_aggr_middle(sc->sc_ah, bf->bf_desc, ndelim);
708 list_move_tail(&bf->list, bf_q);
709 if (bf_prev) {
710 bf_prev->bf_next = bf;
711 ath9k_hw_set_desc_link(sc->sc_ah, bf_prev->bf_desc,
712 bf->bf_daddr);
713 }
714 bf_prev = bf;
715
716 } while (!list_empty(&tid->buf_q));
717
718 bf_first->bf_al = al;
719 bf_first->bf_nframes = nframes;
720
721 return status;
722 #undef PADBYTES
723 }
724
725 static void ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq,
726 struct ath_atx_tid *tid)
727 {
728 struct ath_buf *bf;
729 enum ATH_AGGR_STATUS status;
730 struct list_head bf_q;
731
732 do {
733 if (list_empty(&tid->buf_q))
734 return;
735
736 INIT_LIST_HEAD(&bf_q);
737
738 status = ath_tx_form_aggr(sc, txq, tid, &bf_q);
739
740 /*
741 * no frames picked up to be aggregated;
742 * block-ack window is not open.
743 */
744 if (list_empty(&bf_q))
745 break;
746
747 bf = list_first_entry(&bf_q, struct ath_buf, list);
748 bf->bf_lastbf = list_entry(bf_q.prev, struct ath_buf, list);
749
750 /* if only one frame, send as non-aggregate */
751 if (bf->bf_nframes == 1) {
752 bf->bf_state.bf_type &= ~BUF_AGGR;
753 ath9k_hw_clr11n_aggr(sc->sc_ah, bf->bf_desc);
754 ath_buf_set_rate(sc, bf);
755 ath_tx_txqaddbuf(sc, txq, &bf_q);
756 continue;
757 }
758
759 /* setup first desc of aggregate */
760 bf->bf_state.bf_type |= BUF_AGGR;
761 ath_buf_set_rate(sc, bf);
762 ath9k_hw_set11n_aggr_first(sc->sc_ah, bf->bf_desc, bf->bf_al);
763
764 /* anchor last desc of aggregate */
765 ath9k_hw_set11n_aggr_last(sc->sc_ah, bf->bf_lastbf->bf_desc);
766
767 ath_tx_txqaddbuf(sc, txq, &bf_q);
768 TX_STAT_INC(txq->axq_qnum, a_aggr);
769
770 } while (txq->axq_depth < ATH_AGGR_MIN_QDEPTH &&
771 status != ATH_AGGR_BAW_CLOSED);
772 }
773
774 void ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
775 u16 tid, u16 *ssn)
776 {
777 struct ath_atx_tid *txtid;
778 struct ath_node *an;
779
780 an = (struct ath_node *)sta->drv_priv;
781 txtid = ATH_AN_2_TID(an, tid);
782 txtid->state |= AGGR_ADDBA_PROGRESS;
783 ath_tx_pause_tid(sc, txtid);
784 *ssn = txtid->seq_start;
785 }
786
787 void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
788 {
789 struct ath_node *an = (struct ath_node *)sta->drv_priv;
790 struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid);
791 struct ath_txq *txq = &sc->tx.txq[txtid->ac->qnum];
792 struct ath_tx_status ts;
793 struct ath_buf *bf;
794 struct list_head bf_head;
795
796 memset(&ts, 0, sizeof(ts));
797 INIT_LIST_HEAD(&bf_head);
798
799 if (txtid->state & AGGR_CLEANUP)
800 return;
801
802 if (!(txtid->state & AGGR_ADDBA_COMPLETE)) {
803 txtid->state &= ~AGGR_ADDBA_PROGRESS;
804 return;
805 }
806
807 ath_tx_pause_tid(sc, txtid);
808
809 /* drop all software retried frames and mark this TID */
810 spin_lock_bh(&txq->axq_lock);
811 while (!list_empty(&txtid->buf_q)) {
812 bf = list_first_entry(&txtid->buf_q, struct ath_buf, list);
813 if (!bf_isretried(bf)) {
814 /*
815 * NB: it's based on the assumption that
816 * software retried frame will always stay
817 * at the head of software queue.
818 */
819 break;
820 }
821 list_move_tail(&bf->list, &bf_head);
822 ath_tx_update_baw(sc, txtid, bf->bf_seqno);
823 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 0);
824 }
825 spin_unlock_bh(&txq->axq_lock);
826
827 if (txtid->baw_head != txtid->baw_tail) {
828 txtid->state |= AGGR_CLEANUP;
829 } else {
830 txtid->state &= ~AGGR_ADDBA_COMPLETE;
831 ath_tx_flush_tid(sc, txtid);
832 }
833 }
834
835 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
836 {
837 struct ath_atx_tid *txtid;
838 struct ath_node *an;
839
840 an = (struct ath_node *)sta->drv_priv;
841
842 if (sc->sc_flags & SC_OP_TXAGGR) {
843 txtid = ATH_AN_2_TID(an, tid);
844 txtid->baw_size =
845 IEEE80211_MIN_AMPDU_BUF << sta->ht_cap.ampdu_factor;
846 txtid->state |= AGGR_ADDBA_COMPLETE;
847 txtid->state &= ~AGGR_ADDBA_PROGRESS;
848 ath_tx_resume_tid(sc, txtid);
849 }
850 }
851
852 bool ath_tx_aggr_check(struct ath_softc *sc, struct ath_node *an, u8 tidno)
853 {
854 struct ath_atx_tid *txtid;
855
856 if (!(sc->sc_flags & SC_OP_TXAGGR))
857 return false;
858
859 txtid = ATH_AN_2_TID(an, tidno);
860
861 if (!(txtid->state & (AGGR_ADDBA_COMPLETE | AGGR_ADDBA_PROGRESS)))
862 return true;
863 return false;
864 }
865
866 /********************/
867 /* Queue Management */
868 /********************/
869
870 static void ath_txq_drain_pending_buffers(struct ath_softc *sc,
871 struct ath_txq *txq)
872 {
873 struct ath_atx_ac *ac, *ac_tmp;
874 struct ath_atx_tid *tid, *tid_tmp;
875
876 list_for_each_entry_safe(ac, ac_tmp, &txq->axq_acq, list) {
877 list_del(&ac->list);
878 ac->sched = false;
879 list_for_each_entry_safe(tid, tid_tmp, &ac->tid_q, list) {
880 list_del(&tid->list);
881 tid->sched = false;
882 ath_tid_drain(sc, txq, tid);
883 }
884 }
885 }
886
887 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
888 {
889 struct ath_hw *ah = sc->sc_ah;
890 struct ath_common *common = ath9k_hw_common(ah);
891 struct ath9k_tx_queue_info qi;
892 int qnum, i;
893
894 memset(&qi, 0, sizeof(qi));
895 qi.tqi_subtype = subtype;
896 qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT;
897 qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
898 qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT;
899 qi.tqi_physCompBuf = 0;
900
901 /*
902 * Enable interrupts only for EOL and DESC conditions.
903 * We mark tx descriptors to receive a DESC interrupt
904 * when a tx queue gets deep; otherwise waiting for the
905 * EOL to reap descriptors. Note that this is done to
906 * reduce interrupt load and this only defers reaping
907 * descriptors, never transmitting frames. Aside from
908 * reducing interrupts this also permits more concurrency.
909 * The only potential downside is if the tx queue backs
910 * up in which case the top half of the kernel may backup
911 * due to a lack of tx descriptors.
912 *
913 * The UAPSD queue is an exception, since we take a desc-
914 * based intr on the EOSP frames.
915 */
916 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
917 qi.tqi_qflags = TXQ_FLAG_TXOKINT_ENABLE |
918 TXQ_FLAG_TXERRINT_ENABLE;
919 } else {
920 if (qtype == ATH9K_TX_QUEUE_UAPSD)
921 qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE;
922 else
923 qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE |
924 TXQ_FLAG_TXDESCINT_ENABLE;
925 }
926 qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi);
927 if (qnum == -1) {
928 /*
929 * NB: don't print a message, this happens
930 * normally on parts with too few tx queues
931 */
932 return NULL;
933 }
934 if (qnum >= ARRAY_SIZE(sc->tx.txq)) {
935 ath_print(common, ATH_DBG_FATAL,
936 "qnum %u out of range, max %u!\n",
937 qnum, (unsigned int)ARRAY_SIZE(sc->tx.txq));
938 ath9k_hw_releasetxqueue(ah, qnum);
939 return NULL;
940 }
941 if (!ATH_TXQ_SETUP(sc, qnum)) {
942 struct ath_txq *txq = &sc->tx.txq[qnum];
943
944 txq->axq_class = subtype;
945 txq->axq_qnum = qnum;
946 txq->axq_link = NULL;
947 INIT_LIST_HEAD(&txq->axq_q);
948 INIT_LIST_HEAD(&txq->axq_acq);
949 spin_lock_init(&txq->axq_lock);
950 txq->axq_depth = 0;
951 txq->axq_tx_inprogress = false;
952 sc->tx.txqsetup |= 1<<qnum;
953
954 txq->txq_headidx = txq->txq_tailidx = 0;
955 for (i = 0; i < ATH_TXFIFO_DEPTH; i++)
956 INIT_LIST_HEAD(&txq->txq_fifo[i]);
957 INIT_LIST_HEAD(&txq->txq_fifo_pending);
958 }
959 return &sc->tx.txq[qnum];
960 }
961
962 int ath_txq_update(struct ath_softc *sc, int qnum,
963 struct ath9k_tx_queue_info *qinfo)
964 {
965 struct ath_hw *ah = sc->sc_ah;
966 int error = 0;
967 struct ath9k_tx_queue_info qi;
968
969 if (qnum == sc->beacon.beaconq) {
970 /*
971 * XXX: for beacon queue, we just save the parameter.
972 * It will be picked up by ath_beaconq_config when
973 * it's necessary.
974 */
975 sc->beacon.beacon_qi = *qinfo;
976 return 0;
977 }
978
979 BUG_ON(sc->tx.txq[qnum].axq_qnum != qnum);
980
981 ath9k_hw_get_txq_props(ah, qnum, &qi);
982 qi.tqi_aifs = qinfo->tqi_aifs;
983 qi.tqi_cwmin = qinfo->tqi_cwmin;
984 qi.tqi_cwmax = qinfo->tqi_cwmax;
985 qi.tqi_burstTime = qinfo->tqi_burstTime;
986 qi.tqi_readyTime = qinfo->tqi_readyTime;
987
988 if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) {
989 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
990 "Unable to update hardware queue %u!\n", qnum);
991 error = -EIO;
992 } else {
993 ath9k_hw_resettxqueue(ah, qnum);
994 }
995
996 return error;
997 }
998
999 int ath_cabq_update(struct ath_softc *sc)
1000 {
1001 struct ath9k_tx_queue_info qi;
1002 int qnum = sc->beacon.cabq->axq_qnum;
1003
1004 ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi);
1005 /*
1006 * Ensure the readytime % is within the bounds.
1007 */
1008 if (sc->config.cabqReadytime < ATH9K_READY_TIME_LO_BOUND)
1009 sc->config.cabqReadytime = ATH9K_READY_TIME_LO_BOUND;
1010 else if (sc->config.cabqReadytime > ATH9K_READY_TIME_HI_BOUND)
1011 sc->config.cabqReadytime = ATH9K_READY_TIME_HI_BOUND;
1012
1013 qi.tqi_readyTime = (sc->beacon_interval *
1014 sc->config.cabqReadytime) / 100;
1015 ath_txq_update(sc, qnum, &qi);
1016
1017 return 0;
1018 }
1019
1020 /*
1021 * Drain a given TX queue (could be Beacon or Data)
1022 *
1023 * This assumes output has been stopped and
1024 * we do not need to block ath_tx_tasklet.
1025 */
1026 void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq, bool retry_tx)
1027 {
1028 struct ath_buf *bf, *lastbf;
1029 struct list_head bf_head;
1030 struct ath_tx_status ts;
1031
1032 memset(&ts, 0, sizeof(ts));
1033 INIT_LIST_HEAD(&bf_head);
1034
1035 for (;;) {
1036 spin_lock_bh(&txq->axq_lock);
1037
1038 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1039 if (list_empty(&txq->txq_fifo[txq->txq_tailidx])) {
1040 txq->txq_headidx = txq->txq_tailidx = 0;
1041 spin_unlock_bh(&txq->axq_lock);
1042 break;
1043 } else {
1044 bf = list_first_entry(&txq->txq_fifo[txq->txq_tailidx],
1045 struct ath_buf, list);
1046 }
1047 } else {
1048 if (list_empty(&txq->axq_q)) {
1049 txq->axq_link = NULL;
1050 spin_unlock_bh(&txq->axq_lock);
1051 break;
1052 }
1053 bf = list_first_entry(&txq->axq_q, struct ath_buf,
1054 list);
1055
1056 if (bf->bf_stale) {
1057 list_del(&bf->list);
1058 spin_unlock_bh(&txq->axq_lock);
1059
1060 ath_tx_return_buffer(sc, bf);
1061 continue;
1062 }
1063 }
1064
1065 lastbf = bf->bf_lastbf;
1066 if (!retry_tx)
1067 lastbf->bf_tx_aborted = true;
1068
1069 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1070 list_cut_position(&bf_head,
1071 &txq->txq_fifo[txq->txq_tailidx],
1072 &lastbf->list);
1073 INCR(txq->txq_tailidx, ATH_TXFIFO_DEPTH);
1074 } else {
1075 /* remove ath_buf's of the same mpdu from txq */
1076 list_cut_position(&bf_head, &txq->axq_q, &lastbf->list);
1077 }
1078
1079 txq->axq_depth--;
1080
1081 spin_unlock_bh(&txq->axq_lock);
1082
1083 if (bf_isampdu(bf))
1084 ath_tx_complete_aggr(sc, txq, bf, &bf_head, &ts, 0);
1085 else
1086 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 0);
1087 }
1088
1089 spin_lock_bh(&txq->axq_lock);
1090 txq->axq_tx_inprogress = false;
1091 spin_unlock_bh(&txq->axq_lock);
1092
1093 /* flush any pending frames if aggregation is enabled */
1094 if (sc->sc_flags & SC_OP_TXAGGR) {
1095 if (!retry_tx) {
1096 spin_lock_bh(&txq->axq_lock);
1097 ath_txq_drain_pending_buffers(sc, txq);
1098 spin_unlock_bh(&txq->axq_lock);
1099 }
1100 }
1101
1102 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1103 spin_lock_bh(&txq->axq_lock);
1104 while (!list_empty(&txq->txq_fifo_pending)) {
1105 bf = list_first_entry(&txq->txq_fifo_pending,
1106 struct ath_buf, list);
1107 list_cut_position(&bf_head,
1108 &txq->txq_fifo_pending,
1109 &bf->bf_lastbf->list);
1110 spin_unlock_bh(&txq->axq_lock);
1111
1112 if (bf_isampdu(bf))
1113 ath_tx_complete_aggr(sc, txq, bf, &bf_head,
1114 &ts, 0);
1115 else
1116 ath_tx_complete_buf(sc, bf, txq, &bf_head,
1117 &ts, 0, 0);
1118 spin_lock_bh(&txq->axq_lock);
1119 }
1120 spin_unlock_bh(&txq->axq_lock);
1121 }
1122 }
1123
1124 void ath_drain_all_txq(struct ath_softc *sc, bool retry_tx)
1125 {
1126 struct ath_hw *ah = sc->sc_ah;
1127 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1128 struct ath_txq *txq;
1129 int i, npend = 0;
1130
1131 if (sc->sc_flags & SC_OP_INVALID)
1132 return;
1133
1134 /* Stop beacon queue */
1135 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
1136
1137 /* Stop data queues */
1138 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1139 if (ATH_TXQ_SETUP(sc, i)) {
1140 txq = &sc->tx.txq[i];
1141 ath9k_hw_stoptxdma(ah, txq->axq_qnum);
1142 npend += ath9k_hw_numtxpending(ah, txq->axq_qnum);
1143 }
1144 }
1145
1146 if (npend) {
1147 int r;
1148
1149 ath_print(common, ATH_DBG_FATAL,
1150 "Failed to stop TX DMA. Resetting hardware!\n");
1151
1152 spin_lock_bh(&sc->sc_resetlock);
1153 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false);
1154 if (r)
1155 ath_print(common, ATH_DBG_FATAL,
1156 "Unable to reset hardware; reset status %d\n",
1157 r);
1158 spin_unlock_bh(&sc->sc_resetlock);
1159 }
1160
1161 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1162 if (ATH_TXQ_SETUP(sc, i))
1163 ath_draintxq(sc, &sc->tx.txq[i], retry_tx);
1164 }
1165 }
1166
1167 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
1168 {
1169 ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum);
1170 sc->tx.txqsetup &= ~(1<<txq->axq_qnum);
1171 }
1172
1173 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq)
1174 {
1175 struct ath_atx_ac *ac;
1176 struct ath_atx_tid *tid;
1177
1178 if (list_empty(&txq->axq_acq))
1179 return;
1180
1181 ac = list_first_entry(&txq->axq_acq, struct ath_atx_ac, list);
1182 list_del(&ac->list);
1183 ac->sched = false;
1184
1185 do {
1186 if (list_empty(&ac->tid_q))
1187 return;
1188
1189 tid = list_first_entry(&ac->tid_q, struct ath_atx_tid, list);
1190 list_del(&tid->list);
1191 tid->sched = false;
1192
1193 if (tid->paused)
1194 continue;
1195
1196 ath_tx_sched_aggr(sc, txq, tid);
1197
1198 /*
1199 * add tid to round-robin queue if more frames
1200 * are pending for the tid
1201 */
1202 if (!list_empty(&tid->buf_q))
1203 ath_tx_queue_tid(txq, tid);
1204
1205 break;
1206 } while (!list_empty(&ac->tid_q));
1207
1208 if (!list_empty(&ac->tid_q)) {
1209 if (!ac->sched) {
1210 ac->sched = true;
1211 list_add_tail(&ac->list, &txq->axq_acq);
1212 }
1213 }
1214 }
1215
1216 int ath_tx_setup(struct ath_softc *sc, int haltype)
1217 {
1218 struct ath_txq *txq;
1219
1220 if (haltype >= ARRAY_SIZE(sc->tx.hwq_map)) {
1221 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
1222 "HAL AC %u out of range, max %zu!\n",
1223 haltype, ARRAY_SIZE(sc->tx.hwq_map));
1224 return 0;
1225 }
1226 txq = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, haltype);
1227 if (txq != NULL) {
1228 sc->tx.hwq_map[haltype] = txq->axq_qnum;
1229 return 1;
1230 } else
1231 return 0;
1232 }
1233
1234 /***********/
1235 /* TX, DMA */
1236 /***********/
1237
1238 /*
1239 * Insert a chain of ath_buf (descriptors) on a txq and
1240 * assume the descriptors are already chained together by caller.
1241 */
1242 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
1243 struct list_head *head)
1244 {
1245 struct ath_hw *ah = sc->sc_ah;
1246 struct ath_common *common = ath9k_hw_common(ah);
1247 struct ath_buf *bf;
1248
1249 /*
1250 * Insert the frame on the outbound list and
1251 * pass it on to the hardware.
1252 */
1253
1254 if (list_empty(head))
1255 return;
1256
1257 bf = list_first_entry(head, struct ath_buf, list);
1258
1259 ath_print(common, ATH_DBG_QUEUE,
1260 "qnum: %d, txq depth: %d\n", txq->axq_qnum, txq->axq_depth);
1261
1262 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1263 if (txq->axq_depth >= ATH_TXFIFO_DEPTH) {
1264 list_splice_tail_init(head, &txq->txq_fifo_pending);
1265 return;
1266 }
1267 if (!list_empty(&txq->txq_fifo[txq->txq_headidx]))
1268 ath_print(common, ATH_DBG_XMIT,
1269 "Initializing tx fifo %d which "
1270 "is non-empty\n",
1271 txq->txq_headidx);
1272 INIT_LIST_HEAD(&txq->txq_fifo[txq->txq_headidx]);
1273 list_splice_init(head, &txq->txq_fifo[txq->txq_headidx]);
1274 INCR(txq->txq_headidx, ATH_TXFIFO_DEPTH);
1275 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
1276 ath_print(common, ATH_DBG_XMIT,
1277 "TXDP[%u] = %llx (%p)\n",
1278 txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc);
1279 } else {
1280 list_splice_tail_init(head, &txq->axq_q);
1281
1282 if (txq->axq_link == NULL) {
1283 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
1284 ath_print(common, ATH_DBG_XMIT,
1285 "TXDP[%u] = %llx (%p)\n",
1286 txq->axq_qnum, ito64(bf->bf_daddr),
1287 bf->bf_desc);
1288 } else {
1289 *txq->axq_link = bf->bf_daddr;
1290 ath_print(common, ATH_DBG_XMIT,
1291 "link[%u] (%p)=%llx (%p)\n",
1292 txq->axq_qnum, txq->axq_link,
1293 ito64(bf->bf_daddr), bf->bf_desc);
1294 }
1295 ath9k_hw_get_desc_link(ah, bf->bf_lastbf->bf_desc,
1296 &txq->axq_link);
1297 ath9k_hw_txstart(ah, txq->axq_qnum);
1298 }
1299 txq->axq_depth++;
1300 }
1301
1302 static void ath_tx_send_ampdu(struct ath_softc *sc, struct ath_atx_tid *tid,
1303 struct list_head *bf_head,
1304 struct ath_tx_control *txctl)
1305 {
1306 struct ath_buf *bf;
1307
1308 bf = list_first_entry(bf_head, struct ath_buf, list);
1309 bf->bf_state.bf_type |= BUF_AMPDU;
1310 TX_STAT_INC(txctl->txq->axq_qnum, a_queued);
1311
1312 /*
1313 * Do not queue to h/w when any of the following conditions is true:
1314 * - there are pending frames in software queue
1315 * - the TID is currently paused for ADDBA/BAR request
1316 * - seqno is not within block-ack window
1317 * - h/w queue depth exceeds low water mark
1318 */
1319 if (!list_empty(&tid->buf_q) || tid->paused ||
1320 !BAW_WITHIN(tid->seq_start, tid->baw_size, bf->bf_seqno) ||
1321 txctl->txq->axq_depth >= ATH_AGGR_MIN_QDEPTH) {
1322 /*
1323 * Add this frame to software queue for scheduling later
1324 * for aggregation.
1325 */
1326 list_move_tail(&bf->list, &tid->buf_q);
1327 ath_tx_queue_tid(txctl->txq, tid);
1328 return;
1329 }
1330
1331 /* Add sub-frame to BAW */
1332 ath_tx_addto_baw(sc, tid, bf);
1333
1334 /* Queue to h/w without aggregation */
1335 bf->bf_nframes = 1;
1336 bf->bf_lastbf = bf;
1337 ath_buf_set_rate(sc, bf);
1338 ath_tx_txqaddbuf(sc, txctl->txq, bf_head);
1339 }
1340
1341 static void ath_tx_send_ht_normal(struct ath_softc *sc, struct ath_txq *txq,
1342 struct ath_atx_tid *tid,
1343 struct list_head *bf_head)
1344 {
1345 struct ath_buf *bf;
1346
1347 bf = list_first_entry(bf_head, struct ath_buf, list);
1348 bf->bf_state.bf_type &= ~BUF_AMPDU;
1349
1350 /* update starting sequence number for subsequent ADDBA request */
1351 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
1352
1353 bf->bf_nframes = 1;
1354 bf->bf_lastbf = bf;
1355 ath_buf_set_rate(sc, bf);
1356 ath_tx_txqaddbuf(sc, txq, bf_head);
1357 TX_STAT_INC(txq->axq_qnum, queued);
1358 }
1359
1360 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
1361 struct list_head *bf_head)
1362 {
1363 struct ath_buf *bf;
1364
1365 bf = list_first_entry(bf_head, struct ath_buf, list);
1366
1367 bf->bf_lastbf = bf;
1368 bf->bf_nframes = 1;
1369 ath_buf_set_rate(sc, bf);
1370 ath_tx_txqaddbuf(sc, txq, bf_head);
1371 TX_STAT_INC(txq->axq_qnum, queued);
1372 }
1373
1374 static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb)
1375 {
1376 struct ieee80211_hdr *hdr;
1377 enum ath9k_pkt_type htype;
1378 __le16 fc;
1379
1380 hdr = (struct ieee80211_hdr *)skb->data;
1381 fc = hdr->frame_control;
1382
1383 if (ieee80211_is_beacon(fc))
1384 htype = ATH9K_PKT_TYPE_BEACON;
1385 else if (ieee80211_is_probe_resp(fc))
1386 htype = ATH9K_PKT_TYPE_PROBE_RESP;
1387 else if (ieee80211_is_atim(fc))
1388 htype = ATH9K_PKT_TYPE_ATIM;
1389 else if (ieee80211_is_pspoll(fc))
1390 htype = ATH9K_PKT_TYPE_PSPOLL;
1391 else
1392 htype = ATH9K_PKT_TYPE_NORMAL;
1393
1394 return htype;
1395 }
1396
1397 static int get_hw_crypto_keytype(struct sk_buff *skb)
1398 {
1399 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1400
1401 if (tx_info->control.hw_key) {
1402 if (tx_info->control.hw_key->alg == ALG_WEP)
1403 return ATH9K_KEY_TYPE_WEP;
1404 else if (tx_info->control.hw_key->alg == ALG_TKIP)
1405 return ATH9K_KEY_TYPE_TKIP;
1406 else if (tx_info->control.hw_key->alg == ALG_CCMP)
1407 return ATH9K_KEY_TYPE_AES;
1408 }
1409
1410 return ATH9K_KEY_TYPE_CLEAR;
1411 }
1412
1413 static void assign_aggr_tid_seqno(struct sk_buff *skb,
1414 struct ath_buf *bf)
1415 {
1416 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1417 struct ieee80211_hdr *hdr;
1418 struct ath_node *an;
1419 struct ath_atx_tid *tid;
1420 __le16 fc;
1421 u8 *qc;
1422
1423 if (!tx_info->control.sta)
1424 return;
1425
1426 an = (struct ath_node *)tx_info->control.sta->drv_priv;
1427 hdr = (struct ieee80211_hdr *)skb->data;
1428 fc = hdr->frame_control;
1429
1430 if (ieee80211_is_data_qos(fc)) {
1431 qc = ieee80211_get_qos_ctl(hdr);
1432 bf->bf_tidno = qc[0] & 0xf;
1433 }
1434
1435 /*
1436 * For HT capable stations, we save tidno for later use.
1437 * We also override seqno set by upper layer with the one
1438 * in tx aggregation state.
1439 */
1440 tid = ATH_AN_2_TID(an, bf->bf_tidno);
1441 hdr->seq_ctrl = cpu_to_le16(tid->seq_next << IEEE80211_SEQ_SEQ_SHIFT);
1442 bf->bf_seqno = tid->seq_next;
1443 INCR(tid->seq_next, IEEE80211_SEQ_MAX);
1444 }
1445
1446 static int setup_tx_flags(struct sk_buff *skb, bool use_ldpc)
1447 {
1448 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1449 int flags = 0;
1450
1451 flags |= ATH9K_TXDESC_CLRDMASK; /* needed for crypto errors */
1452 flags |= ATH9K_TXDESC_INTREQ;
1453
1454 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
1455 flags |= ATH9K_TXDESC_NOACK;
1456
1457 if (use_ldpc)
1458 flags |= ATH9K_TXDESC_LDPC;
1459
1460 return flags;
1461 }
1462
1463 /*
1464 * rix - rate index
1465 * pktlen - total bytes (delims + data + fcs + pads + pad delims)
1466 * width - 0 for 20 MHz, 1 for 40 MHz
1467 * half_gi - to use 4us v/s 3.6 us for symbol time
1468 */
1469 static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, struct ath_buf *bf,
1470 int width, int half_gi, bool shortPreamble)
1471 {
1472 u32 nbits, nsymbits, duration, nsymbols;
1473 int streams, pktlen;
1474
1475 pktlen = bf_isaggr(bf) ? bf->bf_al : bf->bf_frmlen;
1476
1477 /* find number of symbols: PLCP + data */
1478 streams = HT_RC_2_STREAMS(rix);
1479 nbits = (pktlen << 3) + OFDM_PLCP_BITS;
1480 nsymbits = bits_per_symbol[rix % 8][width] * streams;
1481 nsymbols = (nbits + nsymbits - 1) / nsymbits;
1482
1483 if (!half_gi)
1484 duration = SYMBOL_TIME(nsymbols);
1485 else
1486 duration = SYMBOL_TIME_HALFGI(nsymbols);
1487
1488 /* addup duration for legacy/ht training and signal fields */
1489 duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
1490
1491 return duration;
1492 }
1493
1494 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf)
1495 {
1496 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1497 struct ath9k_11n_rate_series series[4];
1498 struct sk_buff *skb;
1499 struct ieee80211_tx_info *tx_info;
1500 struct ieee80211_tx_rate *rates;
1501 const struct ieee80211_rate *rate;
1502 struct ieee80211_hdr *hdr;
1503 int i, flags = 0;
1504 u8 rix = 0, ctsrate = 0;
1505 bool is_pspoll;
1506
1507 memset(series, 0, sizeof(struct ath9k_11n_rate_series) * 4);
1508
1509 skb = bf->bf_mpdu;
1510 tx_info = IEEE80211_SKB_CB(skb);
1511 rates = tx_info->control.rates;
1512 hdr = (struct ieee80211_hdr *)skb->data;
1513 is_pspoll = ieee80211_is_pspoll(hdr->frame_control);
1514
1515 /*
1516 * We check if Short Preamble is needed for the CTS rate by
1517 * checking the BSS's global flag.
1518 * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used.
1519 */
1520 rate = ieee80211_get_rts_cts_rate(sc->hw, tx_info);
1521 ctsrate = rate->hw_value;
1522 if (sc->sc_flags & SC_OP_PREAMBLE_SHORT)
1523 ctsrate |= rate->hw_value_short;
1524
1525 for (i = 0; i < 4; i++) {
1526 bool is_40, is_sgi, is_sp;
1527 int phy;
1528
1529 if (!rates[i].count || (rates[i].idx < 0))
1530 continue;
1531
1532 rix = rates[i].idx;
1533 series[i].Tries = rates[i].count;
1534 series[i].ChSel = common->tx_chainmask;
1535
1536 if ((sc->config.ath_aggr_prot && bf_isaggr(bf)) ||
1537 (rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS)) {
1538 series[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1539 flags |= ATH9K_TXDESC_RTSENA;
1540 } else if (rates[i].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
1541 series[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1542 flags |= ATH9K_TXDESC_CTSENA;
1543 }
1544
1545 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
1546 series[i].RateFlags |= ATH9K_RATESERIES_2040;
1547 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
1548 series[i].RateFlags |= ATH9K_RATESERIES_HALFGI;
1549
1550 is_sgi = !!(rates[i].flags & IEEE80211_TX_RC_SHORT_GI);
1551 is_40 = !!(rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH);
1552 is_sp = !!(rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE);
1553
1554 if (rates[i].flags & IEEE80211_TX_RC_MCS) {
1555 /* MCS rates */
1556 series[i].Rate = rix | 0x80;
1557 series[i].PktDuration = ath_pkt_duration(sc, rix, bf,
1558 is_40, is_sgi, is_sp);
1559 if (rix < 8 && (tx_info->flags & IEEE80211_TX_CTL_STBC))
1560 series[i].RateFlags |= ATH9K_RATESERIES_STBC;
1561 continue;
1562 }
1563
1564 /* legcay rates */
1565 if ((tx_info->band == IEEE80211_BAND_2GHZ) &&
1566 !(rate->flags & IEEE80211_RATE_ERP_G))
1567 phy = WLAN_RC_PHY_CCK;
1568 else
1569 phy = WLAN_RC_PHY_OFDM;
1570
1571 rate = &sc->sbands[tx_info->band].bitrates[rates[i].idx];
1572 series[i].Rate = rate->hw_value;
1573 if (rate->hw_value_short) {
1574 if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
1575 series[i].Rate |= rate->hw_value_short;
1576 } else {
1577 is_sp = false;
1578 }
1579
1580 series[i].PktDuration = ath9k_hw_computetxtime(sc->sc_ah,
1581 phy, rate->bitrate * 100, bf->bf_frmlen, rix, is_sp);
1582 }
1583
1584 /* For AR5416 - RTS cannot be followed by a frame larger than 8K */
1585 if (bf_isaggr(bf) && (bf->bf_al > sc->sc_ah->caps.rts_aggr_limit))
1586 flags &= ~ATH9K_TXDESC_RTSENA;
1587
1588 /* ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive. */
1589 if (flags & ATH9K_TXDESC_RTSENA)
1590 flags &= ~ATH9K_TXDESC_CTSENA;
1591
1592 /* set dur_update_en for l-sig computation except for PS-Poll frames */
1593 ath9k_hw_set11n_ratescenario(sc->sc_ah, bf->bf_desc,
1594 bf->bf_lastbf->bf_desc,
1595 !is_pspoll, ctsrate,
1596 0, series, 4, flags);
1597
1598 if (sc->config.ath_aggr_prot && flags)
1599 ath9k_hw_set11n_burstduration(sc->sc_ah, bf->bf_desc, 8192);
1600 }
1601
1602 static int ath_tx_setup_buffer(struct ieee80211_hw *hw, struct ath_buf *bf,
1603 struct sk_buff *skb,
1604 struct ath_tx_control *txctl)
1605 {
1606 struct ath_wiphy *aphy = hw->priv;
1607 struct ath_softc *sc = aphy->sc;
1608 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1609 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1610 int hdrlen;
1611 __le16 fc;
1612 int padpos, padsize;
1613 bool use_ldpc = false;
1614
1615 tx_info->pad[0] = 0;
1616 switch (txctl->frame_type) {
1617 case ATH9K_IFT_NOT_INTERNAL:
1618 break;
1619 case ATH9K_IFT_PAUSE:
1620 tx_info->pad[0] |= ATH_TX_INFO_FRAME_TYPE_PAUSE;
1621 /* fall through */
1622 case ATH9K_IFT_UNPAUSE:
1623 tx_info->pad[0] |= ATH_TX_INFO_FRAME_TYPE_INTERNAL;
1624 break;
1625 }
1626 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1627 fc = hdr->frame_control;
1628
1629 ATH_TXBUF_RESET(bf);
1630
1631 bf->aphy = aphy;
1632 bf->bf_frmlen = skb->len + FCS_LEN;
1633 /* Remove the padding size from bf_frmlen, if any */
1634 padpos = ath9k_cmn_padpos(hdr->frame_control);
1635 padsize = padpos & 3;
1636 if (padsize && skb->len>padpos+padsize) {
1637 bf->bf_frmlen -= padsize;
1638 }
1639
1640 if (conf_is_ht(&hw->conf)) {
1641 bf->bf_state.bf_type |= BUF_HT;
1642 if (tx_info->flags & IEEE80211_TX_CTL_LDPC)
1643 use_ldpc = true;
1644 }
1645
1646 bf->bf_flags = setup_tx_flags(skb, use_ldpc);
1647
1648 bf->bf_keytype = get_hw_crypto_keytype(skb);
1649 if (bf->bf_keytype != ATH9K_KEY_TYPE_CLEAR) {
1650 bf->bf_frmlen += tx_info->control.hw_key->icv_len;
1651 bf->bf_keyix = tx_info->control.hw_key->hw_key_idx;
1652 } else {
1653 bf->bf_keyix = ATH9K_TXKEYIX_INVALID;
1654 }
1655
1656 if (ieee80211_is_data_qos(fc) && bf_isht(bf) &&
1657 (sc->sc_flags & SC_OP_TXAGGR))
1658 assign_aggr_tid_seqno(skb, bf);
1659
1660 bf->bf_mpdu = skb;
1661
1662 bf->bf_dmacontext = dma_map_single(sc->dev, skb->data,
1663 skb->len, DMA_TO_DEVICE);
1664 if (unlikely(dma_mapping_error(sc->dev, bf->bf_dmacontext))) {
1665 bf->bf_mpdu = NULL;
1666 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
1667 "dma_mapping_error() on TX\n");
1668 return -ENOMEM;
1669 }
1670
1671 bf->bf_buf_addr = bf->bf_dmacontext;
1672
1673 /* tag if this is a nullfunc frame to enable PS when AP acks it */
1674 if (ieee80211_is_nullfunc(fc) && ieee80211_has_pm(fc)) {
1675 bf->bf_isnullfunc = true;
1676 sc->ps_flags &= ~PS_NULLFUNC_COMPLETED;
1677 } else
1678 bf->bf_isnullfunc = false;
1679
1680 bf->bf_tx_aborted = false;
1681
1682 return 0;
1683 }
1684
1685 /* FIXME: tx power */
1686 static void ath_tx_start_dma(struct ath_softc *sc, struct ath_buf *bf,
1687 struct ath_tx_control *txctl)
1688 {
1689 struct sk_buff *skb = bf->bf_mpdu;
1690 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1691 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1692 struct ath_node *an = NULL;
1693 struct list_head bf_head;
1694 struct ath_desc *ds;
1695 struct ath_atx_tid *tid;
1696 struct ath_hw *ah = sc->sc_ah;
1697 int frm_type;
1698 __le16 fc;
1699
1700 frm_type = get_hw_packet_type(skb);
1701 fc = hdr->frame_control;
1702
1703 INIT_LIST_HEAD(&bf_head);
1704 list_add_tail(&bf->list, &bf_head);
1705
1706 ds = bf->bf_desc;
1707 ath9k_hw_set_desc_link(ah, ds, 0);
1708
1709 ath9k_hw_set11n_txdesc(ah, ds, bf->bf_frmlen, frm_type, MAX_RATE_POWER,
1710 bf->bf_keyix, bf->bf_keytype, bf->bf_flags);
1711
1712 ath9k_hw_filltxdesc(ah, ds,
1713 skb->len, /* segment length */
1714 true, /* first segment */
1715 true, /* last segment */
1716 ds, /* first descriptor */
1717 bf->bf_buf_addr,
1718 txctl->txq->axq_qnum);
1719
1720 spin_lock_bh(&txctl->txq->axq_lock);
1721
1722 if (bf_isht(bf) && (sc->sc_flags & SC_OP_TXAGGR) &&
1723 tx_info->control.sta) {
1724 an = (struct ath_node *)tx_info->control.sta->drv_priv;
1725 tid = ATH_AN_2_TID(an, bf->bf_tidno);
1726
1727 if (!ieee80211_is_data_qos(fc)) {
1728 ath_tx_send_normal(sc, txctl->txq, &bf_head);
1729 goto tx_done;
1730 }
1731
1732 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
1733 /*
1734 * Try aggregation if it's a unicast data frame
1735 * and the destination is HT capable.
1736 */
1737 ath_tx_send_ampdu(sc, tid, &bf_head, txctl);
1738 } else {
1739 /*
1740 * Send this frame as regular when ADDBA
1741 * exchange is neither complete nor pending.
1742 */
1743 ath_tx_send_ht_normal(sc, txctl->txq,
1744 tid, &bf_head);
1745 }
1746 } else {
1747 ath_tx_send_normal(sc, txctl->txq, &bf_head);
1748 }
1749
1750 tx_done:
1751 spin_unlock_bh(&txctl->txq->axq_lock);
1752 }
1753
1754 /* Upon failure caller should free skb */
1755 int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
1756 struct ath_tx_control *txctl)
1757 {
1758 struct ath_wiphy *aphy = hw->priv;
1759 struct ath_softc *sc = aphy->sc;
1760 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1761 struct ath_txq *txq = txctl->txq;
1762 struct ath_buf *bf;
1763 int q, r;
1764
1765 bf = ath_tx_get_buffer(sc);
1766 if (!bf) {
1767 ath_print(common, ATH_DBG_XMIT, "TX buffers are full\n");
1768 return -1;
1769 }
1770
1771 r = ath_tx_setup_buffer(hw, bf, skb, txctl);
1772 if (unlikely(r)) {
1773 ath_print(common, ATH_DBG_FATAL, "TX mem alloc failure\n");
1774
1775 /* upon ath_tx_processq() this TX queue will be resumed, we
1776 * guarantee this will happen by knowing beforehand that
1777 * we will at least have to run TX completionon one buffer
1778 * on the queue */
1779 spin_lock_bh(&txq->axq_lock);
1780 if (!txq->stopped && txq->axq_depth > 1) {
1781 ath_mac80211_stop_queue(sc, skb_get_queue_mapping(skb));
1782 txq->stopped = 1;
1783 }
1784 spin_unlock_bh(&txq->axq_lock);
1785
1786 ath_tx_return_buffer(sc, bf);
1787
1788 return r;
1789 }
1790
1791 q = skb_get_queue_mapping(skb);
1792 if (q >= 4)
1793 q = 0;
1794
1795 spin_lock_bh(&txq->axq_lock);
1796 if (++sc->tx.pending_frames[q] > ATH_MAX_QDEPTH && !txq->stopped) {
1797 ath_mac80211_stop_queue(sc, skb_get_queue_mapping(skb));
1798 txq->stopped = 1;
1799 }
1800 spin_unlock_bh(&txq->axq_lock);
1801
1802 ath_tx_start_dma(sc, bf, txctl);
1803
1804 return 0;
1805 }
1806
1807 void ath_tx_cabq(struct ieee80211_hw *hw, struct sk_buff *skb)
1808 {
1809 struct ath_wiphy *aphy = hw->priv;
1810 struct ath_softc *sc = aphy->sc;
1811 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1812 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
1813 int padpos, padsize;
1814 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1815 struct ath_tx_control txctl;
1816
1817 memset(&txctl, 0, sizeof(struct ath_tx_control));
1818
1819 /*
1820 * As a temporary workaround, assign seq# here; this will likely need
1821 * to be cleaned up to work better with Beacon transmission and virtual
1822 * BSSes.
1823 */
1824 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1825 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
1826 sc->tx.seq_no += 0x10;
1827 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
1828 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
1829 }
1830
1831 /* Add the padding after the header if this is not already done */
1832 padpos = ath9k_cmn_padpos(hdr->frame_control);
1833 padsize = padpos & 3;
1834 if (padsize && skb->len>padpos) {
1835 if (skb_headroom(skb) < padsize) {
1836 ath_print(common, ATH_DBG_XMIT,
1837 "TX CABQ padding failed\n");
1838 dev_kfree_skb_any(skb);
1839 return;
1840 }
1841 skb_push(skb, padsize);
1842 memmove(skb->data, skb->data + padsize, padpos);
1843 }
1844
1845 txctl.txq = sc->beacon.cabq;
1846
1847 ath_print(common, ATH_DBG_XMIT,
1848 "transmitting CABQ packet, skb: %p\n", skb);
1849
1850 if (ath_tx_start(hw, skb, &txctl) != 0) {
1851 ath_print(common, ATH_DBG_XMIT, "CABQ TX failed\n");
1852 goto exit;
1853 }
1854
1855 return;
1856 exit:
1857 dev_kfree_skb_any(skb);
1858 }
1859
1860 /*****************/
1861 /* TX Completion */
1862 /*****************/
1863
1864 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
1865 struct ath_wiphy *aphy, int tx_flags)
1866 {
1867 struct ieee80211_hw *hw = sc->hw;
1868 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1869 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1870 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data;
1871 int q, padpos, padsize;
1872
1873 ath_print(common, ATH_DBG_XMIT, "TX complete: skb: %p\n", skb);
1874
1875 if (aphy)
1876 hw = aphy->hw;
1877
1878 if (tx_flags & ATH_TX_BAR)
1879 tx_info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
1880
1881 if (!(tx_flags & (ATH_TX_ERROR | ATH_TX_XRETRY))) {
1882 /* Frame was ACKed */
1883 tx_info->flags |= IEEE80211_TX_STAT_ACK;
1884 }
1885
1886 padpos = ath9k_cmn_padpos(hdr->frame_control);
1887 padsize = padpos & 3;
1888 if (padsize && skb->len>padpos+padsize) {
1889 /*
1890 * Remove MAC header padding before giving the frame back to
1891 * mac80211.
1892 */
1893 memmove(skb->data + padsize, skb->data, padpos);
1894 skb_pull(skb, padsize);
1895 }
1896
1897 if (sc->ps_flags & PS_WAIT_FOR_TX_ACK) {
1898 sc->ps_flags &= ~PS_WAIT_FOR_TX_ACK;
1899 ath_print(common, ATH_DBG_PS,
1900 "Going back to sleep after having "
1901 "received TX status (0x%lx)\n",
1902 sc->ps_flags & (PS_WAIT_FOR_BEACON |
1903 PS_WAIT_FOR_CAB |
1904 PS_WAIT_FOR_PSPOLL_DATA |
1905 PS_WAIT_FOR_TX_ACK));
1906 }
1907
1908 if (unlikely(tx_info->pad[0] & ATH_TX_INFO_FRAME_TYPE_INTERNAL))
1909 ath9k_tx_status(hw, skb);
1910 else {
1911 q = skb_get_queue_mapping(skb);
1912 if (q >= 4)
1913 q = 0;
1914
1915 if (--sc->tx.pending_frames[q] < 0)
1916 sc->tx.pending_frames[q] = 0;
1917
1918 ieee80211_tx_status(hw, skb);
1919 }
1920 }
1921
1922 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
1923 struct ath_txq *txq, struct list_head *bf_q,
1924 struct ath_tx_status *ts, int txok, int sendbar)
1925 {
1926 struct sk_buff *skb = bf->bf_mpdu;
1927 unsigned long flags;
1928 int tx_flags = 0;
1929
1930 if (sendbar)
1931 tx_flags = ATH_TX_BAR;
1932
1933 if (!txok) {
1934 tx_flags |= ATH_TX_ERROR;
1935
1936 if (bf_isxretried(bf))
1937 tx_flags |= ATH_TX_XRETRY;
1938 }
1939
1940 dma_unmap_single(sc->dev, bf->bf_dmacontext, skb->len, DMA_TO_DEVICE);
1941 ath_tx_complete(sc, skb, bf->aphy, tx_flags);
1942 ath_debug_stat_tx(sc, txq, bf, ts);
1943
1944 /*
1945 * Return the list of ath_buf of this mpdu to free queue
1946 */
1947 spin_lock_irqsave(&sc->tx.txbuflock, flags);
1948 list_splice_tail_init(bf_q, &sc->tx.txbuf);
1949 spin_unlock_irqrestore(&sc->tx.txbuflock, flags);
1950 }
1951
1952 static int ath_tx_num_badfrms(struct ath_softc *sc, struct ath_buf *bf,
1953 struct ath_tx_status *ts, int txok)
1954 {
1955 u16 seq_st = 0;
1956 u32 ba[WME_BA_BMP_SIZE >> 5];
1957 int ba_index;
1958 int nbad = 0;
1959 int isaggr = 0;
1960
1961 if (bf->bf_lastbf->bf_tx_aborted)
1962 return 0;
1963
1964 isaggr = bf_isaggr(bf);
1965 if (isaggr) {
1966 seq_st = ts->ts_seqnum;
1967 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
1968 }
1969
1970 while (bf) {
1971 ba_index = ATH_BA_INDEX(seq_st, bf->bf_seqno);
1972 if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index)))
1973 nbad++;
1974
1975 bf = bf->bf_next;
1976 }
1977
1978 return nbad;
1979 }
1980
1981 static void ath_tx_rc_status(struct ath_buf *bf, struct ath_tx_status *ts,
1982 int nbad, int txok, bool update_rc)
1983 {
1984 struct sk_buff *skb = bf->bf_mpdu;
1985 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1986 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1987 struct ieee80211_hw *hw = bf->aphy->hw;
1988 u8 i, tx_rateindex;
1989
1990 if (txok)
1991 tx_info->status.ack_signal = ts->ts_rssi;
1992
1993 tx_rateindex = ts->ts_rateindex;
1994 WARN_ON(tx_rateindex >= hw->max_rates);
1995
1996 if (ts->ts_status & ATH9K_TXERR_FILT)
1997 tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
1998 if ((tx_info->flags & IEEE80211_TX_CTL_AMPDU) && update_rc)
1999 tx_info->flags |= IEEE80211_TX_STAT_AMPDU;
2000
2001 if ((ts->ts_status & ATH9K_TXERR_FILT) == 0 &&
2002 (bf->bf_flags & ATH9K_TXDESC_NOACK) == 0 && update_rc) {
2003 if (ieee80211_is_data(hdr->frame_control)) {
2004 if (ts->ts_flags &
2005 (ATH9K_TX_DATA_UNDERRUN | ATH9K_TX_DELIM_UNDERRUN))
2006 tx_info->pad[0] |= ATH_TX_INFO_UNDERRUN;
2007 if ((ts->ts_status & ATH9K_TXERR_XRETRY) ||
2008 (ts->ts_status & ATH9K_TXERR_FIFO))
2009 tx_info->pad[0] |= ATH_TX_INFO_XRETRY;
2010 tx_info->status.ampdu_len = bf->bf_nframes;
2011 tx_info->status.ampdu_ack_len = bf->bf_nframes - nbad;
2012 }
2013 }
2014
2015 for (i = tx_rateindex + 1; i < hw->max_rates; i++) {
2016 tx_info->status.rates[i].count = 0;
2017 tx_info->status.rates[i].idx = -1;
2018 }
2019
2020 tx_info->status.rates[tx_rateindex].count = bf->bf_retries + 1;
2021 }
2022
2023 static void ath_wake_mac80211_queue(struct ath_softc *sc, struct ath_txq *txq)
2024 {
2025 int qnum;
2026
2027 qnum = ath_get_mac80211_qnum(txq->axq_class, sc);
2028 if (qnum == -1)
2029 return;
2030
2031 spin_lock_bh(&txq->axq_lock);
2032 if (txq->stopped && sc->tx.pending_frames[qnum] < ATH_MAX_QDEPTH) {
2033 ath_mac80211_start_queue(sc, qnum);
2034 txq->stopped = 0;
2035 }
2036 spin_unlock_bh(&txq->axq_lock);
2037 }
2038
2039 static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
2040 {
2041 struct ath_hw *ah = sc->sc_ah;
2042 struct ath_common *common = ath9k_hw_common(ah);
2043 struct ath_buf *bf, *lastbf, *bf_held = NULL;
2044 struct list_head bf_head;
2045 struct ath_desc *ds;
2046 struct ath_tx_status ts;
2047 int txok;
2048 int status;
2049
2050 ath_print(common, ATH_DBG_QUEUE, "tx queue %d (%x), link %p\n",
2051 txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum),
2052 txq->axq_link);
2053
2054 for (;;) {
2055 spin_lock_bh(&txq->axq_lock);
2056 if (list_empty(&txq->axq_q)) {
2057 txq->axq_link = NULL;
2058 spin_unlock_bh(&txq->axq_lock);
2059 break;
2060 }
2061 bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
2062
2063 /*
2064 * There is a race condition that a BH gets scheduled
2065 * after sw writes TxE and before hw re-load the last
2066 * descriptor to get the newly chained one.
2067 * Software must keep the last DONE descriptor as a
2068 * holding descriptor - software does so by marking
2069 * it with the STALE flag.
2070 */
2071 bf_held = NULL;
2072 if (bf->bf_stale) {
2073 bf_held = bf;
2074 if (list_is_last(&bf_held->list, &txq->axq_q)) {
2075 spin_unlock_bh(&txq->axq_lock);
2076 break;
2077 } else {
2078 bf = list_entry(bf_held->list.next,
2079 struct ath_buf, list);
2080 }
2081 }
2082
2083 lastbf = bf->bf_lastbf;
2084 ds = lastbf->bf_desc;
2085
2086 memset(&ts, 0, sizeof(ts));
2087 status = ath9k_hw_txprocdesc(ah, ds, &ts);
2088 if (status == -EINPROGRESS) {
2089 spin_unlock_bh(&txq->axq_lock);
2090 break;
2091 }
2092
2093 /*
2094 * We now know the nullfunc frame has been ACKed so we
2095 * can disable RX.
2096 */
2097 if (bf->bf_isnullfunc &&
2098 (ts.ts_status & ATH9K_TX_ACKED)) {
2099 if ((sc->ps_flags & PS_ENABLED))
2100 ath9k_enable_ps(sc);
2101 else
2102 sc->ps_flags |= PS_NULLFUNC_COMPLETED;
2103 }
2104
2105 /*
2106 * Remove ath_buf's of the same transmit unit from txq,
2107 * however leave the last descriptor back as the holding
2108 * descriptor for hw.
2109 */
2110 lastbf->bf_stale = true;
2111 INIT_LIST_HEAD(&bf_head);
2112 if (!list_is_singular(&lastbf->list))
2113 list_cut_position(&bf_head,
2114 &txq->axq_q, lastbf->list.prev);
2115
2116 txq->axq_depth--;
2117 txok = !(ts.ts_status & ATH9K_TXERR_MASK);
2118 txq->axq_tx_inprogress = false;
2119 if (bf_held)
2120 list_del(&bf_held->list);
2121 spin_unlock_bh(&txq->axq_lock);
2122
2123 if (bf_held)
2124 ath_tx_return_buffer(sc, bf_held);
2125
2126 if (!bf_isampdu(bf)) {
2127 /*
2128 * This frame is sent out as a single frame.
2129 * Use hardware retry status for this frame.
2130 */
2131 bf->bf_retries = ts.ts_longretry;
2132 if (ts.ts_status & ATH9K_TXERR_XRETRY)
2133 bf->bf_state.bf_type |= BUF_XRETRY;
2134 ath_tx_rc_status(bf, &ts, 0, txok, true);
2135 }
2136
2137 if (bf_isampdu(bf))
2138 ath_tx_complete_aggr(sc, txq, bf, &bf_head, &ts, txok);
2139 else
2140 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, txok, 0);
2141
2142 ath_wake_mac80211_queue(sc, txq);
2143
2144 spin_lock_bh(&txq->axq_lock);
2145 if (sc->sc_flags & SC_OP_TXAGGR)
2146 ath_txq_schedule(sc, txq);
2147 spin_unlock_bh(&txq->axq_lock);
2148 }
2149 }
2150
2151 static void ath_tx_complete_poll_work(struct work_struct *work)
2152 {
2153 struct ath_softc *sc = container_of(work, struct ath_softc,
2154 tx_complete_work.work);
2155 struct ath_txq *txq;
2156 int i;
2157 bool needreset = false;
2158
2159 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
2160 if (ATH_TXQ_SETUP(sc, i)) {
2161 txq = &sc->tx.txq[i];
2162 spin_lock_bh(&txq->axq_lock);
2163 if (txq->axq_depth) {
2164 if (txq->axq_tx_inprogress) {
2165 needreset = true;
2166 spin_unlock_bh(&txq->axq_lock);
2167 break;
2168 } else {
2169 txq->axq_tx_inprogress = true;
2170 }
2171 }
2172 spin_unlock_bh(&txq->axq_lock);
2173 }
2174
2175 if (needreset) {
2176 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_RESET,
2177 "tx hung, resetting the chip\n");
2178 ath9k_ps_wakeup(sc);
2179 ath_reset(sc, false);
2180 ath9k_ps_restore(sc);
2181 }
2182
2183 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work,
2184 msecs_to_jiffies(ATH_TX_COMPLETE_POLL_INT));
2185 }
2186
2187
2188
2189 void ath_tx_tasklet(struct ath_softc *sc)
2190 {
2191 int i;
2192 u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1);
2193
2194 ath9k_hw_gettxintrtxqs(sc->sc_ah, &qcumask);
2195
2196 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2197 if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i)))
2198 ath_tx_processq(sc, &sc->tx.txq[i]);
2199 }
2200 }
2201
2202 void ath_tx_edma_tasklet(struct ath_softc *sc)
2203 {
2204 struct ath_tx_status txs;
2205 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2206 struct ath_hw *ah = sc->sc_ah;
2207 struct ath_txq *txq;
2208 struct ath_buf *bf, *lastbf;
2209 struct list_head bf_head;
2210 int status;
2211 int txok;
2212
2213 for (;;) {
2214 status = ath9k_hw_txprocdesc(ah, NULL, (void *)&txs);
2215 if (status == -EINPROGRESS)
2216 break;
2217 if (status == -EIO) {
2218 ath_print(common, ATH_DBG_XMIT,
2219 "Error processing tx status\n");
2220 break;
2221 }
2222
2223 /* Skip beacon completions */
2224 if (txs.qid == sc->beacon.beaconq)
2225 continue;
2226
2227 txq = &sc->tx.txq[txs.qid];
2228
2229 spin_lock_bh(&txq->axq_lock);
2230 if (list_empty(&txq->txq_fifo[txq->txq_tailidx])) {
2231 spin_unlock_bh(&txq->axq_lock);
2232 return;
2233 }
2234
2235 bf = list_first_entry(&txq->txq_fifo[txq->txq_tailidx],
2236 struct ath_buf, list);
2237 lastbf = bf->bf_lastbf;
2238
2239 INIT_LIST_HEAD(&bf_head);
2240 list_cut_position(&bf_head, &txq->txq_fifo[txq->txq_tailidx],
2241 &lastbf->list);
2242 INCR(txq->txq_tailidx, ATH_TXFIFO_DEPTH);
2243 txq->axq_depth--;
2244 txq->axq_tx_inprogress = false;
2245 spin_unlock_bh(&txq->axq_lock);
2246
2247 txok = !(txs.ts_status & ATH9K_TXERR_MASK);
2248
2249 /*
2250 * Make sure null func frame is acked before configuring
2251 * hw into ps mode.
2252 */
2253 if (bf->bf_isnullfunc && txok) {
2254 if ((sc->ps_flags & PS_ENABLED))
2255 ath9k_enable_ps(sc);
2256 else
2257 sc->ps_flags |= PS_NULLFUNC_COMPLETED;
2258 }
2259
2260 if (!bf_isampdu(bf)) {
2261 bf->bf_retries = txs.ts_longretry;
2262 if (txs.ts_status & ATH9K_TXERR_XRETRY)
2263 bf->bf_state.bf_type |= BUF_XRETRY;
2264 ath_tx_rc_status(bf, &txs, 0, txok, true);
2265 }
2266
2267 if (bf_isampdu(bf))
2268 ath_tx_complete_aggr(sc, txq, bf, &bf_head, &txs, txok);
2269 else
2270 ath_tx_complete_buf(sc, bf, txq, &bf_head,
2271 &txs, txok, 0);
2272
2273 ath_wake_mac80211_queue(sc, txq);
2274
2275 spin_lock_bh(&txq->axq_lock);
2276 if (!list_empty(&txq->txq_fifo_pending)) {
2277 INIT_LIST_HEAD(&bf_head);
2278 bf = list_first_entry(&txq->txq_fifo_pending,
2279 struct ath_buf, list);
2280 list_cut_position(&bf_head, &txq->txq_fifo_pending,
2281 &bf->bf_lastbf->list);
2282 ath_tx_txqaddbuf(sc, txq, &bf_head);
2283 } else if (sc->sc_flags & SC_OP_TXAGGR)
2284 ath_txq_schedule(sc, txq);
2285 spin_unlock_bh(&txq->axq_lock);
2286 }
2287 }
2288
2289 /*****************/
2290 /* Init, Cleanup */
2291 /*****************/
2292
2293 static int ath_txstatus_setup(struct ath_softc *sc, int size)
2294 {
2295 struct ath_descdma *dd = &sc->txsdma;
2296 u8 txs_len = sc->sc_ah->caps.txs_len;
2297
2298 dd->dd_desc_len = size * txs_len;
2299 dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
2300 &dd->dd_desc_paddr, GFP_KERNEL);
2301 if (!dd->dd_desc)
2302 return -ENOMEM;
2303
2304 return 0;
2305 }
2306
2307 static int ath_tx_edma_init(struct ath_softc *sc)
2308 {
2309 int err;
2310
2311 err = ath_txstatus_setup(sc, ATH_TXSTATUS_RING_SIZE);
2312 if (!err)
2313 ath9k_hw_setup_statusring(sc->sc_ah, sc->txsdma.dd_desc,
2314 sc->txsdma.dd_desc_paddr,
2315 ATH_TXSTATUS_RING_SIZE);
2316
2317 return err;
2318 }
2319
2320 static void ath_tx_edma_cleanup(struct ath_softc *sc)
2321 {
2322 struct ath_descdma *dd = &sc->txsdma;
2323
2324 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
2325 dd->dd_desc_paddr);
2326 }
2327
2328 int ath_tx_init(struct ath_softc *sc, int nbufs)
2329 {
2330 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2331 int error = 0;
2332
2333 spin_lock_init(&sc->tx.txbuflock);
2334
2335 error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf,
2336 "tx", nbufs, 1, 1);
2337 if (error != 0) {
2338 ath_print(common, ATH_DBG_FATAL,
2339 "Failed to allocate tx descriptors: %d\n", error);
2340 goto err;
2341 }
2342
2343 error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf,
2344 "beacon", ATH_BCBUF, 1, 1);
2345 if (error != 0) {
2346 ath_print(common, ATH_DBG_FATAL,
2347 "Failed to allocate beacon descriptors: %d\n", error);
2348 goto err;
2349 }
2350
2351 INIT_DELAYED_WORK(&sc->tx_complete_work, ath_tx_complete_poll_work);
2352
2353 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
2354 error = ath_tx_edma_init(sc);
2355 if (error)
2356 goto err;
2357 }
2358
2359 err:
2360 if (error != 0)
2361 ath_tx_cleanup(sc);
2362
2363 return error;
2364 }
2365
2366 void ath_tx_cleanup(struct ath_softc *sc)
2367 {
2368 if (sc->beacon.bdma.dd_desc_len != 0)
2369 ath_descdma_cleanup(sc, &sc->beacon.bdma, &sc->beacon.bbuf);
2370
2371 if (sc->tx.txdma.dd_desc_len != 0)
2372 ath_descdma_cleanup(sc, &sc->tx.txdma, &sc->tx.txbuf);
2373
2374 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
2375 ath_tx_edma_cleanup(sc);
2376 }
2377
2378 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an)
2379 {
2380 struct ath_atx_tid *tid;
2381 struct ath_atx_ac *ac;
2382 int tidno, acno;
2383
2384 for (tidno = 0, tid = &an->tid[tidno];
2385 tidno < WME_NUM_TID;
2386 tidno++, tid++) {
2387 tid->an = an;
2388 tid->tidno = tidno;
2389 tid->seq_start = tid->seq_next = 0;
2390 tid->baw_size = WME_MAX_BA;
2391 tid->baw_head = tid->baw_tail = 0;
2392 tid->sched = false;
2393 tid->paused = false;
2394 tid->state &= ~AGGR_CLEANUP;
2395 INIT_LIST_HEAD(&tid->buf_q);
2396 acno = TID_TO_WME_AC(tidno);
2397 tid->ac = &an->ac[acno];
2398 tid->state &= ~AGGR_ADDBA_COMPLETE;
2399 tid->state &= ~AGGR_ADDBA_PROGRESS;
2400 }
2401
2402 for (acno = 0, ac = &an->ac[acno];
2403 acno < WME_NUM_AC; acno++, ac++) {
2404 ac->sched = false;
2405 ac->qnum = sc->tx.hwq_map[acno];
2406 INIT_LIST_HEAD(&ac->tid_q);
2407 }
2408 }
2409
2410 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an)
2411 {
2412 int i;
2413 struct ath_atx_ac *ac, *ac_tmp;
2414 struct ath_atx_tid *tid, *tid_tmp;
2415 struct ath_txq *txq;
2416
2417 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2418 if (ATH_TXQ_SETUP(sc, i)) {
2419 txq = &sc->tx.txq[i];
2420
2421 spin_lock_bh(&txq->axq_lock);
2422
2423 list_for_each_entry_safe(ac,
2424 ac_tmp, &txq->axq_acq, list) {
2425 tid = list_first_entry(&ac->tid_q,
2426 struct ath_atx_tid, list);
2427 if (tid && tid->an != an)
2428 continue;
2429 list_del(&ac->list);
2430 ac->sched = false;
2431
2432 list_for_each_entry_safe(tid,
2433 tid_tmp, &ac->tid_q, list) {
2434 list_del(&tid->list);
2435 tid->sched = false;
2436 ath_tid_drain(sc, txq, tid);
2437 tid->state &= ~AGGR_ADDBA_COMPLETE;
2438 tid->state &= ~AGGR_CLEANUP;
2439 }
2440 }
2441
2442 spin_unlock_bh(&txq->axq_lock);
2443 }
2444 }
2445 }
Linux kernel - Deliverables
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