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Merge branch 'core/debug' into core/urgent
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / xmit.c
1 /*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/dma-mapping.h>
18 #include "ath9k.h"
19 #include "ar9003_mac.h"
20
21 #define BITS_PER_BYTE 8
22 #define OFDM_PLCP_BITS 22
23 #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
24 #define L_STF 8
25 #define L_LTF 8
26 #define L_SIG 4
27 #define HT_SIG 8
28 #define HT_STF 4
29 #define HT_LTF(_ns) (4 * (_ns))
30 #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */
31 #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */
32 #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
33 #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
34
35
36 static u16 bits_per_symbol[][2] = {
37 /* 20MHz 40MHz */
38 { 26, 54 }, /* 0: BPSK */
39 { 52, 108 }, /* 1: QPSK 1/2 */
40 { 78, 162 }, /* 2: QPSK 3/4 */
41 { 104, 216 }, /* 3: 16-QAM 1/2 */
42 { 156, 324 }, /* 4: 16-QAM 3/4 */
43 { 208, 432 }, /* 5: 64-QAM 2/3 */
44 { 234, 486 }, /* 6: 64-QAM 3/4 */
45 { 260, 540 }, /* 7: 64-QAM 5/6 */
46 };
47
48 #define IS_HT_RATE(_rate) ((_rate) & 0x80)
49
50 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
51 struct ath_atx_tid *tid, struct sk_buff *skb);
52 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
53 int tx_flags, struct ath_txq *txq);
54 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
55 struct ath_txq *txq, struct list_head *bf_q,
56 struct ath_tx_status *ts, int txok);
57 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
58 struct list_head *head, bool internal);
59 static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
60 struct ath_tx_status *ts, int nframes, int nbad,
61 int txok);
62 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
63 int seqno);
64 static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc,
65 struct ath_txq *txq,
66 struct ath_atx_tid *tid,
67 struct sk_buff *skb,
68 bool dequeue);
69
70 enum {
71 MCS_HT20,
72 MCS_HT20_SGI,
73 MCS_HT40,
74 MCS_HT40_SGI,
75 };
76
77 static int ath_max_4ms_framelen[4][32] = {
78 [MCS_HT20] = {
79 3212, 6432, 9648, 12864, 19300, 25736, 28952, 32172,
80 6424, 12852, 19280, 25708, 38568, 51424, 57852, 64280,
81 9628, 19260, 28896, 38528, 57792, 65532, 65532, 65532,
82 12828, 25656, 38488, 51320, 65532, 65532, 65532, 65532,
83 },
84 [MCS_HT20_SGI] = {
85 3572, 7144, 10720, 14296, 21444, 28596, 32172, 35744,
86 7140, 14284, 21428, 28568, 42856, 57144, 64288, 65532,
87 10700, 21408, 32112, 42816, 64228, 65532, 65532, 65532,
88 14256, 28516, 42780, 57040, 65532, 65532, 65532, 65532,
89 },
90 [MCS_HT40] = {
91 6680, 13360, 20044, 26724, 40092, 53456, 60140, 65532,
92 13348, 26700, 40052, 53400, 65532, 65532, 65532, 65532,
93 20004, 40008, 60016, 65532, 65532, 65532, 65532, 65532,
94 26644, 53292, 65532, 65532, 65532, 65532, 65532, 65532,
95 },
96 [MCS_HT40_SGI] = {
97 7420, 14844, 22272, 29696, 44544, 59396, 65532, 65532,
98 14832, 29668, 44504, 59340, 65532, 65532, 65532, 65532,
99 22232, 44464, 65532, 65532, 65532, 65532, 65532, 65532,
100 29616, 59232, 65532, 65532, 65532, 65532, 65532, 65532,
101 }
102 };
103
104 /*********************/
105 /* Aggregation logic */
106 /*********************/
107
108 static void ath_txq_lock(struct ath_softc *sc, struct ath_txq *txq)
109 __acquires(&txq->axq_lock)
110 {
111 spin_lock_bh(&txq->axq_lock);
112 }
113
114 static void ath_txq_unlock(struct ath_softc *sc, struct ath_txq *txq)
115 __releases(&txq->axq_lock)
116 {
117 spin_unlock_bh(&txq->axq_lock);
118 }
119
120 static void ath_txq_unlock_complete(struct ath_softc *sc, struct ath_txq *txq)
121 __releases(&txq->axq_lock)
122 {
123 struct sk_buff_head q;
124 struct sk_buff *skb;
125
126 __skb_queue_head_init(&q);
127 skb_queue_splice_init(&txq->complete_q, &q);
128 spin_unlock_bh(&txq->axq_lock);
129
130 while ((skb = __skb_dequeue(&q)))
131 ieee80211_tx_status(sc->hw, skb);
132 }
133
134 static void ath_tx_queue_tid(struct ath_txq *txq, struct ath_atx_tid *tid)
135 {
136 struct ath_atx_ac *ac = tid->ac;
137
138 if (tid->paused)
139 return;
140
141 if (tid->sched)
142 return;
143
144 tid->sched = true;
145 list_add_tail(&tid->list, &ac->tid_q);
146
147 if (ac->sched)
148 return;
149
150 ac->sched = true;
151 list_add_tail(&ac->list, &txq->axq_acq);
152 }
153
154 static void ath_tx_resume_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
155 {
156 struct ath_txq *txq = tid->ac->txq;
157
158 WARN_ON(!tid->paused);
159
160 ath_txq_lock(sc, txq);
161 tid->paused = false;
162
163 if (skb_queue_empty(&tid->buf_q))
164 goto unlock;
165
166 ath_tx_queue_tid(txq, tid);
167 ath_txq_schedule(sc, txq);
168 unlock:
169 ath_txq_unlock_complete(sc, txq);
170 }
171
172 static struct ath_frame_info *get_frame_info(struct sk_buff *skb)
173 {
174 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
175 BUILD_BUG_ON(sizeof(struct ath_frame_info) >
176 sizeof(tx_info->rate_driver_data));
177 return (struct ath_frame_info *) &tx_info->rate_driver_data[0];
178 }
179
180 static void ath_send_bar(struct ath_atx_tid *tid, u16 seqno)
181 {
182 ieee80211_send_bar(tid->an->vif, tid->an->sta->addr, tid->tidno,
183 seqno << IEEE80211_SEQ_SEQ_SHIFT);
184 }
185
186 static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
187 {
188 struct ath_txq *txq = tid->ac->txq;
189 struct sk_buff *skb;
190 struct ath_buf *bf;
191 struct list_head bf_head;
192 struct ath_tx_status ts;
193 struct ath_frame_info *fi;
194 bool sendbar = false;
195
196 INIT_LIST_HEAD(&bf_head);
197
198 memset(&ts, 0, sizeof(ts));
199
200 while ((skb = __skb_dequeue(&tid->buf_q))) {
201 fi = get_frame_info(skb);
202 bf = fi->bf;
203
204 if (bf && fi->retries) {
205 list_add_tail(&bf->list, &bf_head);
206 ath_tx_update_baw(sc, tid, bf->bf_state.seqno);
207 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0);
208 sendbar = true;
209 } else {
210 ath_tx_send_normal(sc, txq, NULL, skb);
211 }
212 }
213
214 if (tid->baw_head == tid->baw_tail) {
215 tid->state &= ~AGGR_ADDBA_COMPLETE;
216 tid->state &= ~AGGR_CLEANUP;
217 }
218
219 if (sendbar) {
220 ath_txq_unlock(sc, txq);
221 ath_send_bar(tid, tid->seq_start);
222 ath_txq_lock(sc, txq);
223 }
224 }
225
226 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
227 int seqno)
228 {
229 int index, cindex;
230
231 index = ATH_BA_INDEX(tid->seq_start, seqno);
232 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
233
234 __clear_bit(cindex, tid->tx_buf);
235
236 while (tid->baw_head != tid->baw_tail && !test_bit(tid->baw_head, tid->tx_buf)) {
237 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
238 INCR(tid->baw_head, ATH_TID_MAX_BUFS);
239 if (tid->bar_index >= 0)
240 tid->bar_index--;
241 }
242 }
243
244 static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
245 u16 seqno)
246 {
247 int index, cindex;
248
249 index = ATH_BA_INDEX(tid->seq_start, seqno);
250 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
251 __set_bit(cindex, tid->tx_buf);
252
253 if (index >= ((tid->baw_tail - tid->baw_head) &
254 (ATH_TID_MAX_BUFS - 1))) {
255 tid->baw_tail = cindex;
256 INCR(tid->baw_tail, ATH_TID_MAX_BUFS);
257 }
258 }
259
260 /*
261 * TODO: For frame(s) that are in the retry state, we will reuse the
262 * sequence number(s) without setting the retry bit. The
263 * alternative is to give up on these and BAR the receiver's window
264 * forward.
265 */
266 static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq,
267 struct ath_atx_tid *tid)
268
269 {
270 struct sk_buff *skb;
271 struct ath_buf *bf;
272 struct list_head bf_head;
273 struct ath_tx_status ts;
274 struct ath_frame_info *fi;
275
276 memset(&ts, 0, sizeof(ts));
277 INIT_LIST_HEAD(&bf_head);
278
279 while ((skb = __skb_dequeue(&tid->buf_q))) {
280 fi = get_frame_info(skb);
281 bf = fi->bf;
282
283 if (!bf) {
284 ath_tx_complete(sc, skb, ATH_TX_ERROR, txq);
285 continue;
286 }
287
288 list_add_tail(&bf->list, &bf_head);
289
290 if (fi->retries)
291 ath_tx_update_baw(sc, tid, bf->bf_state.seqno);
292
293 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0);
294 }
295
296 tid->seq_next = tid->seq_start;
297 tid->baw_tail = tid->baw_head;
298 tid->bar_index = -1;
299 }
300
301 static void ath_tx_set_retry(struct ath_softc *sc, struct ath_txq *txq,
302 struct sk_buff *skb, int count)
303 {
304 struct ath_frame_info *fi = get_frame_info(skb);
305 struct ath_buf *bf = fi->bf;
306 struct ieee80211_hdr *hdr;
307 int prev = fi->retries;
308
309 TX_STAT_INC(txq->axq_qnum, a_retries);
310 fi->retries += count;
311
312 if (prev > 0)
313 return;
314
315 hdr = (struct ieee80211_hdr *)skb->data;
316 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY);
317 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
318 sizeof(*hdr), DMA_TO_DEVICE);
319 }
320
321 static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc)
322 {
323 struct ath_buf *bf = NULL;
324
325 spin_lock_bh(&sc->tx.txbuflock);
326
327 if (unlikely(list_empty(&sc->tx.txbuf))) {
328 spin_unlock_bh(&sc->tx.txbuflock);
329 return NULL;
330 }
331
332 bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list);
333 list_del(&bf->list);
334
335 spin_unlock_bh(&sc->tx.txbuflock);
336
337 return bf;
338 }
339
340 static void ath_tx_return_buffer(struct ath_softc *sc, struct ath_buf *bf)
341 {
342 spin_lock_bh(&sc->tx.txbuflock);
343 list_add_tail(&bf->list, &sc->tx.txbuf);
344 spin_unlock_bh(&sc->tx.txbuflock);
345 }
346
347 static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf)
348 {
349 struct ath_buf *tbf;
350
351 tbf = ath_tx_get_buffer(sc);
352 if (WARN_ON(!tbf))
353 return NULL;
354
355 ATH_TXBUF_RESET(tbf);
356
357 tbf->bf_mpdu = bf->bf_mpdu;
358 tbf->bf_buf_addr = bf->bf_buf_addr;
359 memcpy(tbf->bf_desc, bf->bf_desc, sc->sc_ah->caps.tx_desc_len);
360 tbf->bf_state = bf->bf_state;
361
362 return tbf;
363 }
364
365 static void ath_tx_count_frames(struct ath_softc *sc, struct ath_buf *bf,
366 struct ath_tx_status *ts, int txok,
367 int *nframes, int *nbad)
368 {
369 struct ath_frame_info *fi;
370 u16 seq_st = 0;
371 u32 ba[WME_BA_BMP_SIZE >> 5];
372 int ba_index;
373 int isaggr = 0;
374
375 *nbad = 0;
376 *nframes = 0;
377
378 isaggr = bf_isaggr(bf);
379 if (isaggr) {
380 seq_st = ts->ts_seqnum;
381 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
382 }
383
384 while (bf) {
385 fi = get_frame_info(bf->bf_mpdu);
386 ba_index = ATH_BA_INDEX(seq_st, bf->bf_state.seqno);
387
388 (*nframes)++;
389 if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index)))
390 (*nbad)++;
391
392 bf = bf->bf_next;
393 }
394 }
395
396
397 static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
398 struct ath_buf *bf, struct list_head *bf_q,
399 struct ath_tx_status *ts, int txok, bool retry)
400 {
401 struct ath_node *an = NULL;
402 struct sk_buff *skb;
403 struct ieee80211_sta *sta;
404 struct ieee80211_hw *hw = sc->hw;
405 struct ieee80211_hdr *hdr;
406 struct ieee80211_tx_info *tx_info;
407 struct ath_atx_tid *tid = NULL;
408 struct ath_buf *bf_next, *bf_last = bf->bf_lastbf;
409 struct list_head bf_head;
410 struct sk_buff_head bf_pending;
411 u16 seq_st = 0, acked_cnt = 0, txfail_cnt = 0, seq_first;
412 u32 ba[WME_BA_BMP_SIZE >> 5];
413 int isaggr, txfail, txpending, sendbar = 0, needreset = 0, nbad = 0;
414 bool rc_update = true;
415 struct ieee80211_tx_rate rates[4];
416 struct ath_frame_info *fi;
417 int nframes;
418 u8 tidno;
419 bool flush = !!(ts->ts_status & ATH9K_TX_FLUSH);
420 int i, retries;
421 int bar_index = -1;
422
423 skb = bf->bf_mpdu;
424 hdr = (struct ieee80211_hdr *)skb->data;
425
426 tx_info = IEEE80211_SKB_CB(skb);
427
428 memcpy(rates, tx_info->control.rates, sizeof(rates));
429
430 retries = ts->ts_longretry + 1;
431 for (i = 0; i < ts->ts_rateindex; i++)
432 retries += rates[i].count;
433
434 rcu_read_lock();
435
436 sta = ieee80211_find_sta_by_ifaddr(hw, hdr->addr1, hdr->addr2);
437 if (!sta) {
438 rcu_read_unlock();
439
440 INIT_LIST_HEAD(&bf_head);
441 while (bf) {
442 bf_next = bf->bf_next;
443
444 if (!bf->bf_stale || bf_next != NULL)
445 list_move_tail(&bf->list, &bf_head);
446
447 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts, 0);
448
449 bf = bf_next;
450 }
451 return;
452 }
453
454 an = (struct ath_node *)sta->drv_priv;
455 tidno = ieee80211_get_qos_ctl(hdr)[0] & IEEE80211_QOS_CTL_TID_MASK;
456 tid = ATH_AN_2_TID(an, tidno);
457 seq_first = tid->seq_start;
458
459 /*
460 * The hardware occasionally sends a tx status for the wrong TID.
461 * In this case, the BA status cannot be considered valid and all
462 * subframes need to be retransmitted
463 */
464 if (tidno != ts->tid)
465 txok = false;
466
467 isaggr = bf_isaggr(bf);
468 memset(ba, 0, WME_BA_BMP_SIZE >> 3);
469
470 if (isaggr && txok) {
471 if (ts->ts_flags & ATH9K_TX_BA) {
472 seq_st = ts->ts_seqnum;
473 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
474 } else {
475 /*
476 * AR5416 can become deaf/mute when BA
477 * issue happens. Chip needs to be reset.
478 * But AP code may have sychronization issues
479 * when perform internal reset in this routine.
480 * Only enable reset in STA mode for now.
481 */
482 if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION)
483 needreset = 1;
484 }
485 }
486
487 __skb_queue_head_init(&bf_pending);
488
489 ath_tx_count_frames(sc, bf, ts, txok, &nframes, &nbad);
490 while (bf) {
491 u16 seqno = bf->bf_state.seqno;
492
493 txfail = txpending = sendbar = 0;
494 bf_next = bf->bf_next;
495
496 skb = bf->bf_mpdu;
497 tx_info = IEEE80211_SKB_CB(skb);
498 fi = get_frame_info(skb);
499
500 if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, seqno))) {
501 /* transmit completion, subframe is
502 * acked by block ack */
503 acked_cnt++;
504 } else if (!isaggr && txok) {
505 /* transmit completion */
506 acked_cnt++;
507 } else if ((tid->state & AGGR_CLEANUP) || !retry) {
508 /*
509 * cleanup in progress, just fail
510 * the un-acked sub-frames
511 */
512 txfail = 1;
513 } else if (flush) {
514 txpending = 1;
515 } else if (fi->retries < ATH_MAX_SW_RETRIES) {
516 if (txok || !an->sleeping)
517 ath_tx_set_retry(sc, txq, bf->bf_mpdu,
518 retries);
519
520 txpending = 1;
521 } else {
522 txfail = 1;
523 txfail_cnt++;
524 bar_index = max_t(int, bar_index,
525 ATH_BA_INDEX(seq_first, seqno));
526 }
527
528 /*
529 * Make sure the last desc is reclaimed if it
530 * not a holding desc.
531 */
532 INIT_LIST_HEAD(&bf_head);
533 if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) ||
534 bf_next != NULL || !bf_last->bf_stale)
535 list_move_tail(&bf->list, &bf_head);
536
537 if (!txpending || (tid->state & AGGR_CLEANUP)) {
538 /*
539 * complete the acked-ones/xretried ones; update
540 * block-ack window
541 */
542 ath_tx_update_baw(sc, tid, seqno);
543
544 if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) {
545 memcpy(tx_info->control.rates, rates, sizeof(rates));
546 ath_tx_rc_status(sc, bf, ts, nframes, nbad, txok);
547 rc_update = false;
548 }
549
550 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts,
551 !txfail);
552 } else {
553 /* retry the un-acked ones */
554 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
555 bf->bf_next == NULL && bf_last->bf_stale) {
556 struct ath_buf *tbf;
557
558 tbf = ath_clone_txbuf(sc, bf_last);
559 /*
560 * Update tx baw and complete the
561 * frame with failed status if we
562 * run out of tx buf.
563 */
564 if (!tbf) {
565 ath_tx_update_baw(sc, tid, seqno);
566
567 ath_tx_complete_buf(sc, bf, txq,
568 &bf_head, ts, 0);
569 bar_index = max_t(int, bar_index,
570 ATH_BA_INDEX(seq_first, seqno));
571 break;
572 }
573
574 fi->bf = tbf;
575 }
576
577 /*
578 * Put this buffer to the temporary pending
579 * queue to retain ordering
580 */
581 __skb_queue_tail(&bf_pending, skb);
582 }
583
584 bf = bf_next;
585 }
586
587 /* prepend un-acked frames to the beginning of the pending frame queue */
588 if (!skb_queue_empty(&bf_pending)) {
589 if (an->sleeping)
590 ieee80211_sta_set_buffered(sta, tid->tidno, true);
591
592 skb_queue_splice(&bf_pending, &tid->buf_q);
593 if (!an->sleeping) {
594 ath_tx_queue_tid(txq, tid);
595
596 if (ts->ts_status & ATH9K_TXERR_FILT)
597 tid->ac->clear_ps_filter = true;
598 }
599 }
600
601 if (bar_index >= 0) {
602 u16 bar_seq = ATH_BA_INDEX2SEQ(seq_first, bar_index);
603
604 if (BAW_WITHIN(tid->seq_start, tid->baw_size, bar_seq))
605 tid->bar_index = ATH_BA_INDEX(tid->seq_start, bar_seq);
606
607 ath_txq_unlock(sc, txq);
608 ath_send_bar(tid, ATH_BA_INDEX2SEQ(seq_first, bar_index + 1));
609 ath_txq_lock(sc, txq);
610 }
611
612 if (tid->state & AGGR_CLEANUP)
613 ath_tx_flush_tid(sc, tid);
614
615 rcu_read_unlock();
616
617 if (needreset) {
618 RESET_STAT_INC(sc, RESET_TYPE_TX_ERROR);
619 ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
620 }
621 }
622
623 static bool ath_lookup_legacy(struct ath_buf *bf)
624 {
625 struct sk_buff *skb;
626 struct ieee80211_tx_info *tx_info;
627 struct ieee80211_tx_rate *rates;
628 int i;
629
630 skb = bf->bf_mpdu;
631 tx_info = IEEE80211_SKB_CB(skb);
632 rates = tx_info->control.rates;
633
634 for (i = 0; i < 4; i++) {
635 if (!rates[i].count || rates[i].idx < 0)
636 break;
637
638 if (!(rates[i].flags & IEEE80211_TX_RC_MCS))
639 return true;
640 }
641
642 return false;
643 }
644
645 static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf,
646 struct ath_atx_tid *tid)
647 {
648 struct sk_buff *skb;
649 struct ieee80211_tx_info *tx_info;
650 struct ieee80211_tx_rate *rates;
651 u32 max_4ms_framelen, frmlen;
652 u16 aggr_limit, bt_aggr_limit, legacy = 0;
653 int i;
654
655 skb = bf->bf_mpdu;
656 tx_info = IEEE80211_SKB_CB(skb);
657 rates = tx_info->control.rates;
658
659 /*
660 * Find the lowest frame length among the rate series that will have a
661 * 4ms transmit duration.
662 * TODO - TXOP limit needs to be considered.
663 */
664 max_4ms_framelen = ATH_AMPDU_LIMIT_MAX;
665
666 for (i = 0; i < 4; i++) {
667 int modeidx;
668
669 if (!rates[i].count)
670 continue;
671
672 if (!(rates[i].flags & IEEE80211_TX_RC_MCS)) {
673 legacy = 1;
674 break;
675 }
676
677 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
678 modeidx = MCS_HT40;
679 else
680 modeidx = MCS_HT20;
681
682 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
683 modeidx++;
684
685 frmlen = ath_max_4ms_framelen[modeidx][rates[i].idx];
686 max_4ms_framelen = min(max_4ms_framelen, frmlen);
687 }
688
689 /*
690 * limit aggregate size by the minimum rate if rate selected is
691 * not a probe rate, if rate selected is a probe rate then
692 * avoid aggregation of this packet.
693 */
694 if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy)
695 return 0;
696
697 aggr_limit = min(max_4ms_framelen, (u32)ATH_AMPDU_LIMIT_MAX);
698
699 /*
700 * Override the default aggregation limit for BTCOEX.
701 */
702 bt_aggr_limit = ath9k_btcoex_aggr_limit(sc, max_4ms_framelen);
703 if (bt_aggr_limit)
704 aggr_limit = bt_aggr_limit;
705
706 /*
707 * h/w can accept aggregates up to 16 bit lengths (65535).
708 * The IE, however can hold up to 65536, which shows up here
709 * as zero. Ignore 65536 since we are constrained by hw.
710 */
711 if (tid->an->maxampdu)
712 aggr_limit = min(aggr_limit, tid->an->maxampdu);
713
714 return aggr_limit;
715 }
716
717 /*
718 * Returns the number of delimiters to be added to
719 * meet the minimum required mpdudensity.
720 */
721 static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid,
722 struct ath_buf *bf, u16 frmlen,
723 bool first_subfrm)
724 {
725 #define FIRST_DESC_NDELIMS 60
726 struct sk_buff *skb = bf->bf_mpdu;
727 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
728 u32 nsymbits, nsymbols;
729 u16 minlen;
730 u8 flags, rix;
731 int width, streams, half_gi, ndelim, mindelim;
732 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
733
734 /* Select standard number of delimiters based on frame length alone */
735 ndelim = ATH_AGGR_GET_NDELIM(frmlen);
736
737 /*
738 * If encryption enabled, hardware requires some more padding between
739 * subframes.
740 * TODO - this could be improved to be dependent on the rate.
741 * The hardware can keep up at lower rates, but not higher rates
742 */
743 if ((fi->keyix != ATH9K_TXKEYIX_INVALID) &&
744 !(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA))
745 ndelim += ATH_AGGR_ENCRYPTDELIM;
746
747 /*
748 * Add delimiter when using RTS/CTS with aggregation
749 * and non enterprise AR9003 card
750 */
751 if (first_subfrm && !AR_SREV_9580_10_OR_LATER(sc->sc_ah) &&
752 (sc->sc_ah->ent_mode & AR_ENT_OTP_MIN_PKT_SIZE_DISABLE))
753 ndelim = max(ndelim, FIRST_DESC_NDELIMS);
754
755 /*
756 * Convert desired mpdu density from microeconds to bytes based
757 * on highest rate in rate series (i.e. first rate) to determine
758 * required minimum length for subframe. Take into account
759 * whether high rate is 20 or 40Mhz and half or full GI.
760 *
761 * If there is no mpdu density restriction, no further calculation
762 * is needed.
763 */
764
765 if (tid->an->mpdudensity == 0)
766 return ndelim;
767
768 rix = tx_info->control.rates[0].idx;
769 flags = tx_info->control.rates[0].flags;
770 width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0;
771 half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0;
772
773 if (half_gi)
774 nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(tid->an->mpdudensity);
775 else
776 nsymbols = NUM_SYMBOLS_PER_USEC(tid->an->mpdudensity);
777
778 if (nsymbols == 0)
779 nsymbols = 1;
780
781 streams = HT_RC_2_STREAMS(rix);
782 nsymbits = bits_per_symbol[rix % 8][width] * streams;
783 minlen = (nsymbols * nsymbits) / BITS_PER_BYTE;
784
785 if (frmlen < minlen) {
786 mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ;
787 ndelim = max(mindelim, ndelim);
788 }
789
790 return ndelim;
791 }
792
793 static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc,
794 struct ath_txq *txq,
795 struct ath_atx_tid *tid,
796 struct list_head *bf_q,
797 int *aggr_len)
798 {
799 #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
800 struct ath_buf *bf, *bf_first = NULL, *bf_prev = NULL;
801 int rl = 0, nframes = 0, ndelim, prev_al = 0;
802 u16 aggr_limit = 0, al = 0, bpad = 0,
803 al_delta, h_baw = tid->baw_size / 2;
804 enum ATH_AGGR_STATUS status = ATH_AGGR_DONE;
805 struct ieee80211_tx_info *tx_info;
806 struct ath_frame_info *fi;
807 struct sk_buff *skb;
808 u16 seqno;
809
810 do {
811 skb = skb_peek(&tid->buf_q);
812 fi = get_frame_info(skb);
813 bf = fi->bf;
814 if (!fi->bf)
815 bf = ath_tx_setup_buffer(sc, txq, tid, skb, true);
816
817 if (!bf)
818 continue;
819
820 bf->bf_state.bf_type = BUF_AMPDU | BUF_AGGR;
821 seqno = bf->bf_state.seqno;
822
823 /* do not step over block-ack window */
824 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno)) {
825 status = ATH_AGGR_BAW_CLOSED;
826 break;
827 }
828
829 if (tid->bar_index > ATH_BA_INDEX(tid->seq_start, seqno)) {
830 struct ath_tx_status ts = {};
831 struct list_head bf_head;
832
833 INIT_LIST_HEAD(&bf_head);
834 list_add(&bf->list, &bf_head);
835 __skb_unlink(skb, &tid->buf_q);
836 ath_tx_update_baw(sc, tid, seqno);
837 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0);
838 continue;
839 }
840
841 if (!bf_first)
842 bf_first = bf;
843
844 if (!rl) {
845 aggr_limit = ath_lookup_rate(sc, bf, tid);
846 rl = 1;
847 }
848
849 /* do not exceed aggregation limit */
850 al_delta = ATH_AGGR_DELIM_SZ + fi->framelen;
851
852 if (nframes &&
853 ((aggr_limit < (al + bpad + al_delta + prev_al)) ||
854 ath_lookup_legacy(bf))) {
855 status = ATH_AGGR_LIMITED;
856 break;
857 }
858
859 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
860 if (nframes && (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE))
861 break;
862
863 /* do not exceed subframe limit */
864 if (nframes >= min((int)h_baw, ATH_AMPDU_SUBFRAME_DEFAULT)) {
865 status = ATH_AGGR_LIMITED;
866 break;
867 }
868
869 /* add padding for previous frame to aggregation length */
870 al += bpad + al_delta;
871
872 /*
873 * Get the delimiters needed to meet the MPDU
874 * density for this node.
875 */
876 ndelim = ath_compute_num_delims(sc, tid, bf_first, fi->framelen,
877 !nframes);
878 bpad = PADBYTES(al_delta) + (ndelim << 2);
879
880 nframes++;
881 bf->bf_next = NULL;
882
883 /* link buffers of this frame to the aggregate */
884 if (!fi->retries)
885 ath_tx_addto_baw(sc, tid, seqno);
886 bf->bf_state.ndelim = ndelim;
887
888 __skb_unlink(skb, &tid->buf_q);
889 list_add_tail(&bf->list, bf_q);
890 if (bf_prev)
891 bf_prev->bf_next = bf;
892
893 bf_prev = bf;
894
895 } while (!skb_queue_empty(&tid->buf_q));
896
897 *aggr_len = al;
898
899 return status;
900 #undef PADBYTES
901 }
902
903 /*
904 * rix - rate index
905 * pktlen - total bytes (delims + data + fcs + pads + pad delims)
906 * width - 0 for 20 MHz, 1 for 40 MHz
907 * half_gi - to use 4us v/s 3.6 us for symbol time
908 */
909 static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, int pktlen,
910 int width, int half_gi, bool shortPreamble)
911 {
912 u32 nbits, nsymbits, duration, nsymbols;
913 int streams;
914
915 /* find number of symbols: PLCP + data */
916 streams = HT_RC_2_STREAMS(rix);
917 nbits = (pktlen << 3) + OFDM_PLCP_BITS;
918 nsymbits = bits_per_symbol[rix % 8][width] * streams;
919 nsymbols = (nbits + nsymbits - 1) / nsymbits;
920
921 if (!half_gi)
922 duration = SYMBOL_TIME(nsymbols);
923 else
924 duration = SYMBOL_TIME_HALFGI(nsymbols);
925
926 /* addup duration for legacy/ht training and signal fields */
927 duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
928
929 return duration;
930 }
931
932 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf,
933 struct ath_tx_info *info, int len)
934 {
935 struct ath_hw *ah = sc->sc_ah;
936 struct sk_buff *skb;
937 struct ieee80211_tx_info *tx_info;
938 struct ieee80211_tx_rate *rates;
939 const struct ieee80211_rate *rate;
940 struct ieee80211_hdr *hdr;
941 int i;
942 u8 rix = 0;
943
944 skb = bf->bf_mpdu;
945 tx_info = IEEE80211_SKB_CB(skb);
946 rates = tx_info->control.rates;
947 hdr = (struct ieee80211_hdr *)skb->data;
948
949 /* set dur_update_en for l-sig computation except for PS-Poll frames */
950 info->dur_update = !ieee80211_is_pspoll(hdr->frame_control);
951
952 /*
953 * We check if Short Preamble is needed for the CTS rate by
954 * checking the BSS's global flag.
955 * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used.
956 */
957 rate = ieee80211_get_rts_cts_rate(sc->hw, tx_info);
958 info->rtscts_rate = rate->hw_value;
959
960 if (tx_info->control.vif &&
961 tx_info->control.vif->bss_conf.use_short_preamble)
962 info->rtscts_rate |= rate->hw_value_short;
963
964 for (i = 0; i < 4; i++) {
965 bool is_40, is_sgi, is_sp;
966 int phy;
967
968 if (!rates[i].count || (rates[i].idx < 0))
969 continue;
970
971 rix = rates[i].idx;
972 info->rates[i].Tries = rates[i].count;
973
974 if (rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS) {
975 info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
976 info->flags |= ATH9K_TXDESC_RTSENA;
977 } else if (rates[i].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
978 info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
979 info->flags |= ATH9K_TXDESC_CTSENA;
980 }
981
982 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
983 info->rates[i].RateFlags |= ATH9K_RATESERIES_2040;
984 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
985 info->rates[i].RateFlags |= ATH9K_RATESERIES_HALFGI;
986
987 is_sgi = !!(rates[i].flags & IEEE80211_TX_RC_SHORT_GI);
988 is_40 = !!(rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH);
989 is_sp = !!(rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE);
990
991 if (rates[i].flags & IEEE80211_TX_RC_MCS) {
992 /* MCS rates */
993 info->rates[i].Rate = rix | 0x80;
994 info->rates[i].ChSel = ath_txchainmask_reduction(sc,
995 ah->txchainmask, info->rates[i].Rate);
996 info->rates[i].PktDuration = ath_pkt_duration(sc, rix, len,
997 is_40, is_sgi, is_sp);
998 if (rix < 8 && (tx_info->flags & IEEE80211_TX_CTL_STBC))
999 info->rates[i].RateFlags |= ATH9K_RATESERIES_STBC;
1000 continue;
1001 }
1002
1003 /* legacy rates */
1004 if ((tx_info->band == IEEE80211_BAND_2GHZ) &&
1005 !(rate->flags & IEEE80211_RATE_ERP_G))
1006 phy = WLAN_RC_PHY_CCK;
1007 else
1008 phy = WLAN_RC_PHY_OFDM;
1009
1010 rate = &sc->sbands[tx_info->band].bitrates[rates[i].idx];
1011 info->rates[i].Rate = rate->hw_value;
1012 if (rate->hw_value_short) {
1013 if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
1014 info->rates[i].Rate |= rate->hw_value_short;
1015 } else {
1016 is_sp = false;
1017 }
1018
1019 if (bf->bf_state.bfs_paprd)
1020 info->rates[i].ChSel = ah->txchainmask;
1021 else
1022 info->rates[i].ChSel = ath_txchainmask_reduction(sc,
1023 ah->txchainmask, info->rates[i].Rate);
1024
1025 info->rates[i].PktDuration = ath9k_hw_computetxtime(sc->sc_ah,
1026 phy, rate->bitrate * 100, len, rix, is_sp);
1027 }
1028
1029 /* For AR5416 - RTS cannot be followed by a frame larger than 8K */
1030 if (bf_isaggr(bf) && (len > sc->sc_ah->caps.rts_aggr_limit))
1031 info->flags &= ~ATH9K_TXDESC_RTSENA;
1032
1033 /* ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive. */
1034 if (info->flags & ATH9K_TXDESC_RTSENA)
1035 info->flags &= ~ATH9K_TXDESC_CTSENA;
1036 }
1037
1038 static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb)
1039 {
1040 struct ieee80211_hdr *hdr;
1041 enum ath9k_pkt_type htype;
1042 __le16 fc;
1043
1044 hdr = (struct ieee80211_hdr *)skb->data;
1045 fc = hdr->frame_control;
1046
1047 if (ieee80211_is_beacon(fc))
1048 htype = ATH9K_PKT_TYPE_BEACON;
1049 else if (ieee80211_is_probe_resp(fc))
1050 htype = ATH9K_PKT_TYPE_PROBE_RESP;
1051 else if (ieee80211_is_atim(fc))
1052 htype = ATH9K_PKT_TYPE_ATIM;
1053 else if (ieee80211_is_pspoll(fc))
1054 htype = ATH9K_PKT_TYPE_PSPOLL;
1055 else
1056 htype = ATH9K_PKT_TYPE_NORMAL;
1057
1058 return htype;
1059 }
1060
1061 static void ath_tx_fill_desc(struct ath_softc *sc, struct ath_buf *bf,
1062 struct ath_txq *txq, int len)
1063 {
1064 struct ath_hw *ah = sc->sc_ah;
1065 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
1066 struct ath_buf *bf_first = bf;
1067 struct ath_tx_info info;
1068 bool aggr = !!(bf->bf_state.bf_type & BUF_AGGR);
1069
1070 memset(&info, 0, sizeof(info));
1071 info.is_first = true;
1072 info.is_last = true;
1073 info.txpower = MAX_RATE_POWER;
1074 info.qcu = txq->axq_qnum;
1075
1076 info.flags = ATH9K_TXDESC_INTREQ;
1077 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
1078 info.flags |= ATH9K_TXDESC_NOACK;
1079 if (tx_info->flags & IEEE80211_TX_CTL_LDPC)
1080 info.flags |= ATH9K_TXDESC_LDPC;
1081
1082 ath_buf_set_rate(sc, bf, &info, len);
1083
1084 if (tx_info->flags & IEEE80211_TX_CTL_CLEAR_PS_FILT)
1085 info.flags |= ATH9K_TXDESC_CLRDMASK;
1086
1087 if (bf->bf_state.bfs_paprd)
1088 info.flags |= (u32) bf->bf_state.bfs_paprd << ATH9K_TXDESC_PAPRD_S;
1089
1090
1091 while (bf) {
1092 struct sk_buff *skb = bf->bf_mpdu;
1093 struct ath_frame_info *fi = get_frame_info(skb);
1094
1095 info.type = get_hw_packet_type(skb);
1096 if (bf->bf_next)
1097 info.link = bf->bf_next->bf_daddr;
1098 else
1099 info.link = 0;
1100
1101 info.buf_addr[0] = bf->bf_buf_addr;
1102 info.buf_len[0] = skb->len;
1103 info.pkt_len = fi->framelen;
1104 info.keyix = fi->keyix;
1105 info.keytype = fi->keytype;
1106
1107 if (aggr) {
1108 if (bf == bf_first)
1109 info.aggr = AGGR_BUF_FIRST;
1110 else if (!bf->bf_next)
1111 info.aggr = AGGR_BUF_LAST;
1112 else
1113 info.aggr = AGGR_BUF_MIDDLE;
1114
1115 info.ndelim = bf->bf_state.ndelim;
1116 info.aggr_len = len;
1117 }
1118
1119 ath9k_hw_set_txdesc(ah, bf->bf_desc, &info);
1120 bf = bf->bf_next;
1121 }
1122 }
1123
1124 static void ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq,
1125 struct ath_atx_tid *tid)
1126 {
1127 struct ath_buf *bf;
1128 enum ATH_AGGR_STATUS status;
1129 struct ieee80211_tx_info *tx_info;
1130 struct list_head bf_q;
1131 int aggr_len;
1132
1133 do {
1134 if (skb_queue_empty(&tid->buf_q))
1135 return;
1136
1137 INIT_LIST_HEAD(&bf_q);
1138
1139 status = ath_tx_form_aggr(sc, txq, tid, &bf_q, &aggr_len);
1140
1141 /*
1142 * no frames picked up to be aggregated;
1143 * block-ack window is not open.
1144 */
1145 if (list_empty(&bf_q))
1146 break;
1147
1148 bf = list_first_entry(&bf_q, struct ath_buf, list);
1149 bf->bf_lastbf = list_entry(bf_q.prev, struct ath_buf, list);
1150 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
1151
1152 if (tid->ac->clear_ps_filter) {
1153 tid->ac->clear_ps_filter = false;
1154 tx_info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT;
1155 } else {
1156 tx_info->flags &= ~IEEE80211_TX_CTL_CLEAR_PS_FILT;
1157 }
1158
1159 /* if only one frame, send as non-aggregate */
1160 if (bf == bf->bf_lastbf) {
1161 aggr_len = get_frame_info(bf->bf_mpdu)->framelen;
1162 bf->bf_state.bf_type = BUF_AMPDU;
1163 } else {
1164 TX_STAT_INC(txq->axq_qnum, a_aggr);
1165 }
1166
1167 ath_tx_fill_desc(sc, bf, txq, aggr_len);
1168 ath_tx_txqaddbuf(sc, txq, &bf_q, false);
1169 } while (txq->axq_ampdu_depth < ATH_AGGR_MIN_QDEPTH &&
1170 status != ATH_AGGR_BAW_CLOSED);
1171 }
1172
1173 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
1174 u16 tid, u16 *ssn)
1175 {
1176 struct ath_atx_tid *txtid;
1177 struct ath_node *an;
1178
1179 an = (struct ath_node *)sta->drv_priv;
1180 txtid = ATH_AN_2_TID(an, tid);
1181
1182 if (txtid->state & (AGGR_CLEANUP | AGGR_ADDBA_COMPLETE))
1183 return -EAGAIN;
1184
1185 txtid->state |= AGGR_ADDBA_PROGRESS;
1186 txtid->paused = true;
1187 *ssn = txtid->seq_start = txtid->seq_next;
1188 txtid->bar_index = -1;
1189
1190 memset(txtid->tx_buf, 0, sizeof(txtid->tx_buf));
1191 txtid->baw_head = txtid->baw_tail = 0;
1192
1193 return 0;
1194 }
1195
1196 void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
1197 {
1198 struct ath_node *an = (struct ath_node *)sta->drv_priv;
1199 struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid);
1200 struct ath_txq *txq = txtid->ac->txq;
1201
1202 if (txtid->state & AGGR_CLEANUP)
1203 return;
1204
1205 if (!(txtid->state & AGGR_ADDBA_COMPLETE)) {
1206 txtid->state &= ~AGGR_ADDBA_PROGRESS;
1207 return;
1208 }
1209
1210 ath_txq_lock(sc, txq);
1211 txtid->paused = true;
1212
1213 /*
1214 * If frames are still being transmitted for this TID, they will be
1215 * cleaned up during tx completion. To prevent race conditions, this
1216 * TID can only be reused after all in-progress subframes have been
1217 * completed.
1218 */
1219 if (txtid->baw_head != txtid->baw_tail)
1220 txtid->state |= AGGR_CLEANUP;
1221 else
1222 txtid->state &= ~AGGR_ADDBA_COMPLETE;
1223
1224 ath_tx_flush_tid(sc, txtid);
1225 ath_txq_unlock_complete(sc, txq);
1226 }
1227
1228 void ath_tx_aggr_sleep(struct ieee80211_sta *sta, struct ath_softc *sc,
1229 struct ath_node *an)
1230 {
1231 struct ath_atx_tid *tid;
1232 struct ath_atx_ac *ac;
1233 struct ath_txq *txq;
1234 bool buffered;
1235 int tidno;
1236
1237 for (tidno = 0, tid = &an->tid[tidno];
1238 tidno < WME_NUM_TID; tidno++, tid++) {
1239
1240 if (!tid->sched)
1241 continue;
1242
1243 ac = tid->ac;
1244 txq = ac->txq;
1245
1246 ath_txq_lock(sc, txq);
1247
1248 buffered = !skb_queue_empty(&tid->buf_q);
1249
1250 tid->sched = false;
1251 list_del(&tid->list);
1252
1253 if (ac->sched) {
1254 ac->sched = false;
1255 list_del(&ac->list);
1256 }
1257
1258 ath_txq_unlock(sc, txq);
1259
1260 ieee80211_sta_set_buffered(sta, tidno, buffered);
1261 }
1262 }
1263
1264 void ath_tx_aggr_wakeup(struct ath_softc *sc, struct ath_node *an)
1265 {
1266 struct ath_atx_tid *tid;
1267 struct ath_atx_ac *ac;
1268 struct ath_txq *txq;
1269 int tidno;
1270
1271 for (tidno = 0, tid = &an->tid[tidno];
1272 tidno < WME_NUM_TID; tidno++, tid++) {
1273
1274 ac = tid->ac;
1275 txq = ac->txq;
1276
1277 ath_txq_lock(sc, txq);
1278 ac->clear_ps_filter = true;
1279
1280 if (!skb_queue_empty(&tid->buf_q) && !tid->paused) {
1281 ath_tx_queue_tid(txq, tid);
1282 ath_txq_schedule(sc, txq);
1283 }
1284
1285 ath_txq_unlock_complete(sc, txq);
1286 }
1287 }
1288
1289 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
1290 {
1291 struct ath_atx_tid *txtid;
1292 struct ath_node *an;
1293
1294 an = (struct ath_node *)sta->drv_priv;
1295
1296 txtid = ATH_AN_2_TID(an, tid);
1297 txtid->baw_size = IEEE80211_MIN_AMPDU_BUF << sta->ht_cap.ampdu_factor;
1298 txtid->state |= AGGR_ADDBA_COMPLETE;
1299 txtid->state &= ~AGGR_ADDBA_PROGRESS;
1300 ath_tx_resume_tid(sc, txtid);
1301 }
1302
1303 /********************/
1304 /* Queue Management */
1305 /********************/
1306
1307 static void ath_txq_drain_pending_buffers(struct ath_softc *sc,
1308 struct ath_txq *txq)
1309 {
1310 struct ath_atx_ac *ac, *ac_tmp;
1311 struct ath_atx_tid *tid, *tid_tmp;
1312
1313 list_for_each_entry_safe(ac, ac_tmp, &txq->axq_acq, list) {
1314 list_del(&ac->list);
1315 ac->sched = false;
1316 list_for_each_entry_safe(tid, tid_tmp, &ac->tid_q, list) {
1317 list_del(&tid->list);
1318 tid->sched = false;
1319 ath_tid_drain(sc, txq, tid);
1320 }
1321 }
1322 }
1323
1324 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
1325 {
1326 struct ath_hw *ah = sc->sc_ah;
1327 struct ath9k_tx_queue_info qi;
1328 static const int subtype_txq_to_hwq[] = {
1329 [WME_AC_BE] = ATH_TXQ_AC_BE,
1330 [WME_AC_BK] = ATH_TXQ_AC_BK,
1331 [WME_AC_VI] = ATH_TXQ_AC_VI,
1332 [WME_AC_VO] = ATH_TXQ_AC_VO,
1333 };
1334 int axq_qnum, i;
1335
1336 memset(&qi, 0, sizeof(qi));
1337 qi.tqi_subtype = subtype_txq_to_hwq[subtype];
1338 qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT;
1339 qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
1340 qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT;
1341 qi.tqi_physCompBuf = 0;
1342
1343 /*
1344 * Enable interrupts only for EOL and DESC conditions.
1345 * We mark tx descriptors to receive a DESC interrupt
1346 * when a tx queue gets deep; otherwise waiting for the
1347 * EOL to reap descriptors. Note that this is done to
1348 * reduce interrupt load and this only defers reaping
1349 * descriptors, never transmitting frames. Aside from
1350 * reducing interrupts this also permits more concurrency.
1351 * The only potential downside is if the tx queue backs
1352 * up in which case the top half of the kernel may backup
1353 * due to a lack of tx descriptors.
1354 *
1355 * The UAPSD queue is an exception, since we take a desc-
1356 * based intr on the EOSP frames.
1357 */
1358 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1359 qi.tqi_qflags = TXQ_FLAG_TXINT_ENABLE;
1360 } else {
1361 if (qtype == ATH9K_TX_QUEUE_UAPSD)
1362 qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE;
1363 else
1364 qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE |
1365 TXQ_FLAG_TXDESCINT_ENABLE;
1366 }
1367 axq_qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi);
1368 if (axq_qnum == -1) {
1369 /*
1370 * NB: don't print a message, this happens
1371 * normally on parts with too few tx queues
1372 */
1373 return NULL;
1374 }
1375 if (!ATH_TXQ_SETUP(sc, axq_qnum)) {
1376 struct ath_txq *txq = &sc->tx.txq[axq_qnum];
1377
1378 txq->axq_qnum = axq_qnum;
1379 txq->mac80211_qnum = -1;
1380 txq->axq_link = NULL;
1381 __skb_queue_head_init(&txq->complete_q);
1382 INIT_LIST_HEAD(&txq->axq_q);
1383 INIT_LIST_HEAD(&txq->axq_acq);
1384 spin_lock_init(&txq->axq_lock);
1385 txq->axq_depth = 0;
1386 txq->axq_ampdu_depth = 0;
1387 txq->axq_tx_inprogress = false;
1388 sc->tx.txqsetup |= 1<<axq_qnum;
1389
1390 txq->txq_headidx = txq->txq_tailidx = 0;
1391 for (i = 0; i < ATH_TXFIFO_DEPTH; i++)
1392 INIT_LIST_HEAD(&txq->txq_fifo[i]);
1393 }
1394 return &sc->tx.txq[axq_qnum];
1395 }
1396
1397 int ath_txq_update(struct ath_softc *sc, int qnum,
1398 struct ath9k_tx_queue_info *qinfo)
1399 {
1400 struct ath_hw *ah = sc->sc_ah;
1401 int error = 0;
1402 struct ath9k_tx_queue_info qi;
1403
1404 if (qnum == sc->beacon.beaconq) {
1405 /*
1406 * XXX: for beacon queue, we just save the parameter.
1407 * It will be picked up by ath_beaconq_config when
1408 * it's necessary.
1409 */
1410 sc->beacon.beacon_qi = *qinfo;
1411 return 0;
1412 }
1413
1414 BUG_ON(sc->tx.txq[qnum].axq_qnum != qnum);
1415
1416 ath9k_hw_get_txq_props(ah, qnum, &qi);
1417 qi.tqi_aifs = qinfo->tqi_aifs;
1418 qi.tqi_cwmin = qinfo->tqi_cwmin;
1419 qi.tqi_cwmax = qinfo->tqi_cwmax;
1420 qi.tqi_burstTime = qinfo->tqi_burstTime;
1421 qi.tqi_readyTime = qinfo->tqi_readyTime;
1422
1423 if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) {
1424 ath_err(ath9k_hw_common(sc->sc_ah),
1425 "Unable to update hardware queue %u!\n", qnum);
1426 error = -EIO;
1427 } else {
1428 ath9k_hw_resettxqueue(ah, qnum);
1429 }
1430
1431 return error;
1432 }
1433
1434 int ath_cabq_update(struct ath_softc *sc)
1435 {
1436 struct ath9k_tx_queue_info qi;
1437 struct ath_beacon_config *cur_conf = &sc->cur_beacon_conf;
1438 int qnum = sc->beacon.cabq->axq_qnum;
1439
1440 ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi);
1441 /*
1442 * Ensure the readytime % is within the bounds.
1443 */
1444 if (sc->config.cabqReadytime < ATH9K_READY_TIME_LO_BOUND)
1445 sc->config.cabqReadytime = ATH9K_READY_TIME_LO_BOUND;
1446 else if (sc->config.cabqReadytime > ATH9K_READY_TIME_HI_BOUND)
1447 sc->config.cabqReadytime = ATH9K_READY_TIME_HI_BOUND;
1448
1449 qi.tqi_readyTime = (cur_conf->beacon_interval *
1450 sc->config.cabqReadytime) / 100;
1451 ath_txq_update(sc, qnum, &qi);
1452
1453 return 0;
1454 }
1455
1456 static bool bf_is_ampdu_not_probing(struct ath_buf *bf)
1457 {
1458 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(bf->bf_mpdu);
1459 return bf_isampdu(bf) && !(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE);
1460 }
1461
1462 static void ath_drain_txq_list(struct ath_softc *sc, struct ath_txq *txq,
1463 struct list_head *list, bool retry_tx)
1464 {
1465 struct ath_buf *bf, *lastbf;
1466 struct list_head bf_head;
1467 struct ath_tx_status ts;
1468
1469 memset(&ts, 0, sizeof(ts));
1470 ts.ts_status = ATH9K_TX_FLUSH;
1471 INIT_LIST_HEAD(&bf_head);
1472
1473 while (!list_empty(list)) {
1474 bf = list_first_entry(list, struct ath_buf, list);
1475
1476 if (bf->bf_stale) {
1477 list_del(&bf->list);
1478
1479 ath_tx_return_buffer(sc, bf);
1480 continue;
1481 }
1482
1483 lastbf = bf->bf_lastbf;
1484 list_cut_position(&bf_head, list, &lastbf->list);
1485
1486 txq->axq_depth--;
1487 if (bf_is_ampdu_not_probing(bf))
1488 txq->axq_ampdu_depth--;
1489
1490 if (bf_isampdu(bf))
1491 ath_tx_complete_aggr(sc, txq, bf, &bf_head, &ts, 0,
1492 retry_tx);
1493 else
1494 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0);
1495 }
1496 }
1497
1498 /*
1499 * Drain a given TX queue (could be Beacon or Data)
1500 *
1501 * This assumes output has been stopped and
1502 * we do not need to block ath_tx_tasklet.
1503 */
1504 void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq, bool retry_tx)
1505 {
1506 ath_txq_lock(sc, txq);
1507
1508 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1509 int idx = txq->txq_tailidx;
1510
1511 while (!list_empty(&txq->txq_fifo[idx])) {
1512 ath_drain_txq_list(sc, txq, &txq->txq_fifo[idx],
1513 retry_tx);
1514
1515 INCR(idx, ATH_TXFIFO_DEPTH);
1516 }
1517 txq->txq_tailidx = idx;
1518 }
1519
1520 txq->axq_link = NULL;
1521 txq->axq_tx_inprogress = false;
1522 ath_drain_txq_list(sc, txq, &txq->axq_q, retry_tx);
1523
1524 /* flush any pending frames if aggregation is enabled */
1525 if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) && !retry_tx)
1526 ath_txq_drain_pending_buffers(sc, txq);
1527
1528 ath_txq_unlock_complete(sc, txq);
1529 }
1530
1531 bool ath_drain_all_txq(struct ath_softc *sc, bool retry_tx)
1532 {
1533 struct ath_hw *ah = sc->sc_ah;
1534 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1535 struct ath_txq *txq;
1536 int i;
1537 u32 npend = 0;
1538
1539 if (sc->sc_flags & SC_OP_INVALID)
1540 return true;
1541
1542 ath9k_hw_abort_tx_dma(ah);
1543
1544 /* Check if any queue remains active */
1545 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1546 if (!ATH_TXQ_SETUP(sc, i))
1547 continue;
1548
1549 if (ath9k_hw_numtxpending(ah, sc->tx.txq[i].axq_qnum))
1550 npend |= BIT(i);
1551 }
1552
1553 if (npend)
1554 ath_err(common, "Failed to stop TX DMA, queues=0x%03x!\n", npend);
1555
1556 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1557 if (!ATH_TXQ_SETUP(sc, i))
1558 continue;
1559
1560 /*
1561 * The caller will resume queues with ieee80211_wake_queues.
1562 * Mark the queue as not stopped to prevent ath_tx_complete
1563 * from waking the queue too early.
1564 */
1565 txq = &sc->tx.txq[i];
1566 txq->stopped = false;
1567 ath_draintxq(sc, txq, retry_tx);
1568 }
1569
1570 return !npend;
1571 }
1572
1573 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
1574 {
1575 ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum);
1576 sc->tx.txqsetup &= ~(1<<txq->axq_qnum);
1577 }
1578
1579 /* For each axq_acq entry, for each tid, try to schedule packets
1580 * for transmit until ampdu_depth has reached min Q depth.
1581 */
1582 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq)
1583 {
1584 struct ath_atx_ac *ac, *ac_tmp, *last_ac;
1585 struct ath_atx_tid *tid, *last_tid;
1586
1587 if (work_pending(&sc->hw_reset_work) || list_empty(&txq->axq_acq) ||
1588 txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH)
1589 return;
1590
1591 ac = list_first_entry(&txq->axq_acq, struct ath_atx_ac, list);
1592 last_ac = list_entry(txq->axq_acq.prev, struct ath_atx_ac, list);
1593
1594 list_for_each_entry_safe(ac, ac_tmp, &txq->axq_acq, list) {
1595 last_tid = list_entry(ac->tid_q.prev, struct ath_atx_tid, list);
1596 list_del(&ac->list);
1597 ac->sched = false;
1598
1599 while (!list_empty(&ac->tid_q)) {
1600 tid = list_first_entry(&ac->tid_q, struct ath_atx_tid,
1601 list);
1602 list_del(&tid->list);
1603 tid->sched = false;
1604
1605 if (tid->paused)
1606 continue;
1607
1608 ath_tx_sched_aggr(sc, txq, tid);
1609
1610 /*
1611 * add tid to round-robin queue if more frames
1612 * are pending for the tid
1613 */
1614 if (!skb_queue_empty(&tid->buf_q))
1615 ath_tx_queue_tid(txq, tid);
1616
1617 if (tid == last_tid ||
1618 txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH)
1619 break;
1620 }
1621
1622 if (!list_empty(&ac->tid_q) && !ac->sched) {
1623 ac->sched = true;
1624 list_add_tail(&ac->list, &txq->axq_acq);
1625 }
1626
1627 if (ac == last_ac ||
1628 txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH)
1629 return;
1630 }
1631 }
1632
1633 /***********/
1634 /* TX, DMA */
1635 /***********/
1636
1637 /*
1638 * Insert a chain of ath_buf (descriptors) on a txq and
1639 * assume the descriptors are already chained together by caller.
1640 */
1641 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
1642 struct list_head *head, bool internal)
1643 {
1644 struct ath_hw *ah = sc->sc_ah;
1645 struct ath_common *common = ath9k_hw_common(ah);
1646 struct ath_buf *bf, *bf_last;
1647 bool puttxbuf = false;
1648 bool edma;
1649
1650 /*
1651 * Insert the frame on the outbound list and
1652 * pass it on to the hardware.
1653 */
1654
1655 if (list_empty(head))
1656 return;
1657
1658 edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
1659 bf = list_first_entry(head, struct ath_buf, list);
1660 bf_last = list_entry(head->prev, struct ath_buf, list);
1661
1662 ath_dbg(common, QUEUE, "qnum: %d, txq depth: %d\n",
1663 txq->axq_qnum, txq->axq_depth);
1664
1665 if (edma && list_empty(&txq->txq_fifo[txq->txq_headidx])) {
1666 list_splice_tail_init(head, &txq->txq_fifo[txq->txq_headidx]);
1667 INCR(txq->txq_headidx, ATH_TXFIFO_DEPTH);
1668 puttxbuf = true;
1669 } else {
1670 list_splice_tail_init(head, &txq->axq_q);
1671
1672 if (txq->axq_link) {
1673 ath9k_hw_set_desc_link(ah, txq->axq_link, bf->bf_daddr);
1674 ath_dbg(common, XMIT, "link[%u] (%p)=%llx (%p)\n",
1675 txq->axq_qnum, txq->axq_link,
1676 ito64(bf->bf_daddr), bf->bf_desc);
1677 } else if (!edma)
1678 puttxbuf = true;
1679
1680 txq->axq_link = bf_last->bf_desc;
1681 }
1682
1683 if (puttxbuf) {
1684 TX_STAT_INC(txq->axq_qnum, puttxbuf);
1685 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
1686 ath_dbg(common, XMIT, "TXDP[%u] = %llx (%p)\n",
1687 txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc);
1688 }
1689
1690 if (!edma) {
1691 TX_STAT_INC(txq->axq_qnum, txstart);
1692 ath9k_hw_txstart(ah, txq->axq_qnum);
1693 }
1694
1695 if (!internal) {
1696 txq->axq_depth++;
1697 if (bf_is_ampdu_not_probing(bf))
1698 txq->axq_ampdu_depth++;
1699 }
1700 }
1701
1702 static void ath_tx_send_ampdu(struct ath_softc *sc, struct ath_atx_tid *tid,
1703 struct sk_buff *skb, struct ath_tx_control *txctl)
1704 {
1705 struct ath_frame_info *fi = get_frame_info(skb);
1706 struct list_head bf_head;
1707 struct ath_buf *bf;
1708
1709 /*
1710 * Do not queue to h/w when any of the following conditions is true:
1711 * - there are pending frames in software queue
1712 * - the TID is currently paused for ADDBA/BAR request
1713 * - seqno is not within block-ack window
1714 * - h/w queue depth exceeds low water mark
1715 */
1716 if (!skb_queue_empty(&tid->buf_q) || tid->paused ||
1717 !BAW_WITHIN(tid->seq_start, tid->baw_size, tid->seq_next) ||
1718 txctl->txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH) {
1719 /*
1720 * Add this frame to software queue for scheduling later
1721 * for aggregation.
1722 */
1723 TX_STAT_INC(txctl->txq->axq_qnum, a_queued_sw);
1724 __skb_queue_tail(&tid->buf_q, skb);
1725 if (!txctl->an || !txctl->an->sleeping)
1726 ath_tx_queue_tid(txctl->txq, tid);
1727 return;
1728 }
1729
1730 bf = ath_tx_setup_buffer(sc, txctl->txq, tid, skb, false);
1731 if (!bf)
1732 return;
1733
1734 bf->bf_state.bf_type = BUF_AMPDU;
1735 INIT_LIST_HEAD(&bf_head);
1736 list_add(&bf->list, &bf_head);
1737
1738 /* Add sub-frame to BAW */
1739 ath_tx_addto_baw(sc, tid, bf->bf_state.seqno);
1740
1741 /* Queue to h/w without aggregation */
1742 TX_STAT_INC(txctl->txq->axq_qnum, a_queued_hw);
1743 bf->bf_lastbf = bf;
1744 ath_tx_fill_desc(sc, bf, txctl->txq, fi->framelen);
1745 ath_tx_txqaddbuf(sc, txctl->txq, &bf_head, false);
1746 }
1747
1748 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
1749 struct ath_atx_tid *tid, struct sk_buff *skb)
1750 {
1751 struct ath_frame_info *fi = get_frame_info(skb);
1752 struct list_head bf_head;
1753 struct ath_buf *bf;
1754
1755 bf = fi->bf;
1756 if (!bf)
1757 bf = ath_tx_setup_buffer(sc, txq, tid, skb, false);
1758
1759 if (!bf)
1760 return;
1761
1762 INIT_LIST_HEAD(&bf_head);
1763 list_add_tail(&bf->list, &bf_head);
1764 bf->bf_state.bf_type = 0;
1765
1766 bf->bf_lastbf = bf;
1767 ath_tx_fill_desc(sc, bf, txq, fi->framelen);
1768 ath_tx_txqaddbuf(sc, txq, &bf_head, false);
1769 TX_STAT_INC(txq->axq_qnum, queued);
1770 }
1771
1772 static void setup_frame_info(struct ieee80211_hw *hw, struct sk_buff *skb,
1773 int framelen)
1774 {
1775 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1776 struct ieee80211_sta *sta = tx_info->control.sta;
1777 struct ieee80211_key_conf *hw_key = tx_info->control.hw_key;
1778 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1779 struct ath_frame_info *fi = get_frame_info(skb);
1780 struct ath_node *an = NULL;
1781 enum ath9k_key_type keytype;
1782
1783 keytype = ath9k_cmn_get_hw_crypto_keytype(skb);
1784
1785 if (sta)
1786 an = (struct ath_node *) sta->drv_priv;
1787
1788 memset(fi, 0, sizeof(*fi));
1789 if (hw_key)
1790 fi->keyix = hw_key->hw_key_idx;
1791 else if (an && ieee80211_is_data(hdr->frame_control) && an->ps_key > 0)
1792 fi->keyix = an->ps_key;
1793 else
1794 fi->keyix = ATH9K_TXKEYIX_INVALID;
1795 fi->keytype = keytype;
1796 fi->framelen = framelen;
1797 }
1798
1799 u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate)
1800 {
1801 struct ath_hw *ah = sc->sc_ah;
1802 struct ath9k_channel *curchan = ah->curchan;
1803 if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) &&
1804 (curchan->channelFlags & CHANNEL_5GHZ) &&
1805 (chainmask == 0x7) && (rate < 0x90))
1806 return 0x3;
1807 else
1808 return chainmask;
1809 }
1810
1811 /*
1812 * Assign a descriptor (and sequence number if necessary,
1813 * and map buffer for DMA. Frees skb on error
1814 */
1815 static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc,
1816 struct ath_txq *txq,
1817 struct ath_atx_tid *tid,
1818 struct sk_buff *skb,
1819 bool dequeue)
1820 {
1821 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1822 struct ath_frame_info *fi = get_frame_info(skb);
1823 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1824 struct ath_buf *bf;
1825 int fragno;
1826 u16 seqno;
1827
1828 bf = ath_tx_get_buffer(sc);
1829 if (!bf) {
1830 ath_dbg(common, XMIT, "TX buffers are full\n");
1831 goto error;
1832 }
1833
1834 ATH_TXBUF_RESET(bf);
1835
1836 if (tid) {
1837 fragno = le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG;
1838 seqno = tid->seq_next;
1839 hdr->seq_ctrl = cpu_to_le16(tid->seq_next << IEEE80211_SEQ_SEQ_SHIFT);
1840
1841 if (fragno)
1842 hdr->seq_ctrl |= cpu_to_le16(fragno);
1843
1844 if (!ieee80211_has_morefrags(hdr->frame_control))
1845 INCR(tid->seq_next, IEEE80211_SEQ_MAX);
1846
1847 bf->bf_state.seqno = seqno;
1848 }
1849
1850 bf->bf_mpdu = skb;
1851
1852 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
1853 skb->len, DMA_TO_DEVICE);
1854 if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) {
1855 bf->bf_mpdu = NULL;
1856 bf->bf_buf_addr = 0;
1857 ath_err(ath9k_hw_common(sc->sc_ah),
1858 "dma_mapping_error() on TX\n");
1859 ath_tx_return_buffer(sc, bf);
1860 goto error;
1861 }
1862
1863 fi->bf = bf;
1864
1865 return bf;
1866
1867 error:
1868 if (dequeue)
1869 __skb_unlink(skb, &tid->buf_q);
1870 dev_kfree_skb_any(skb);
1871 return NULL;
1872 }
1873
1874 /* FIXME: tx power */
1875 static void ath_tx_start_dma(struct ath_softc *sc, struct sk_buff *skb,
1876 struct ath_tx_control *txctl)
1877 {
1878 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1879 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1880 struct ath_atx_tid *tid = NULL;
1881 struct ath_buf *bf;
1882 u8 tidno;
1883
1884 if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) && txctl->an &&
1885 ieee80211_is_data_qos(hdr->frame_control)) {
1886 tidno = ieee80211_get_qos_ctl(hdr)[0] &
1887 IEEE80211_QOS_CTL_TID_MASK;
1888 tid = ATH_AN_2_TID(txctl->an, tidno);
1889
1890 WARN_ON(tid->ac->txq != txctl->txq);
1891 }
1892
1893 if ((tx_info->flags & IEEE80211_TX_CTL_AMPDU) && tid) {
1894 /*
1895 * Try aggregation if it's a unicast data frame
1896 * and the destination is HT capable.
1897 */
1898 ath_tx_send_ampdu(sc, tid, skb, txctl);
1899 } else {
1900 bf = ath_tx_setup_buffer(sc, txctl->txq, tid, skb, false);
1901 if (!bf)
1902 return;
1903
1904 bf->bf_state.bfs_paprd = txctl->paprd;
1905
1906 if (txctl->paprd)
1907 bf->bf_state.bfs_paprd_timestamp = jiffies;
1908
1909 ath_tx_send_normal(sc, txctl->txq, tid, skb);
1910 }
1911 }
1912
1913 /* Upon failure caller should free skb */
1914 int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
1915 struct ath_tx_control *txctl)
1916 {
1917 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
1918 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1919 struct ieee80211_sta *sta = info->control.sta;
1920 struct ieee80211_vif *vif = info->control.vif;
1921 struct ath_softc *sc = hw->priv;
1922 struct ath_txq *txq = txctl->txq;
1923 int padpos, padsize;
1924 int frmlen = skb->len + FCS_LEN;
1925 int q;
1926
1927 /* NOTE: sta can be NULL according to net/mac80211.h */
1928 if (sta)
1929 txctl->an = (struct ath_node *)sta->drv_priv;
1930
1931 if (info->control.hw_key)
1932 frmlen += info->control.hw_key->icv_len;
1933
1934 /*
1935 * As a temporary workaround, assign seq# here; this will likely need
1936 * to be cleaned up to work better with Beacon transmission and virtual
1937 * BSSes.
1938 */
1939 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1940 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
1941 sc->tx.seq_no += 0x10;
1942 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
1943 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
1944 }
1945
1946 /* Add the padding after the header if this is not already done */
1947 padpos = ath9k_cmn_padpos(hdr->frame_control);
1948 padsize = padpos & 3;
1949 if (padsize && skb->len > padpos) {
1950 if (skb_headroom(skb) < padsize)
1951 return -ENOMEM;
1952
1953 skb_push(skb, padsize);
1954 memmove(skb->data, skb->data + padsize, padpos);
1955 hdr = (struct ieee80211_hdr *) skb->data;
1956 }
1957
1958 if ((vif && vif->type != NL80211_IFTYPE_AP &&
1959 vif->type != NL80211_IFTYPE_AP_VLAN) ||
1960 !ieee80211_is_data(hdr->frame_control))
1961 info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT;
1962
1963 setup_frame_info(hw, skb, frmlen);
1964
1965 /*
1966 * At this point, the vif, hw_key and sta pointers in the tx control
1967 * info are no longer valid (overwritten by the ath_frame_info data.
1968 */
1969
1970 q = skb_get_queue_mapping(skb);
1971
1972 ath_txq_lock(sc, txq);
1973 if (txq == sc->tx.txq_map[q] &&
1974 ++txq->pending_frames > ATH_MAX_QDEPTH && !txq->stopped) {
1975 ieee80211_stop_queue(sc->hw, q);
1976 txq->stopped = true;
1977 }
1978
1979 ath_tx_start_dma(sc, skb, txctl);
1980
1981 ath_txq_unlock(sc, txq);
1982
1983 return 0;
1984 }
1985
1986 /*****************/
1987 /* TX Completion */
1988 /*****************/
1989
1990 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
1991 int tx_flags, struct ath_txq *txq)
1992 {
1993 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1994 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1995 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data;
1996 int q, padpos, padsize;
1997
1998 ath_dbg(common, XMIT, "TX complete: skb: %p\n", skb);
1999
2000 if (!(tx_flags & ATH_TX_ERROR))
2001 /* Frame was ACKed */
2002 tx_info->flags |= IEEE80211_TX_STAT_ACK;
2003
2004 padpos = ath9k_cmn_padpos(hdr->frame_control);
2005 padsize = padpos & 3;
2006 if (padsize && skb->len>padpos+padsize) {
2007 /*
2008 * Remove MAC header padding before giving the frame back to
2009 * mac80211.
2010 */
2011 memmove(skb->data + padsize, skb->data, padpos);
2012 skb_pull(skb, padsize);
2013 }
2014
2015 if ((sc->ps_flags & PS_WAIT_FOR_TX_ACK) && !txq->axq_depth) {
2016 sc->ps_flags &= ~PS_WAIT_FOR_TX_ACK;
2017 ath_dbg(common, PS,
2018 "Going back to sleep after having received TX status (0x%lx)\n",
2019 sc->ps_flags & (PS_WAIT_FOR_BEACON |
2020 PS_WAIT_FOR_CAB |
2021 PS_WAIT_FOR_PSPOLL_DATA |
2022 PS_WAIT_FOR_TX_ACK));
2023 }
2024
2025 q = skb_get_queue_mapping(skb);
2026 if (txq == sc->tx.txq_map[q]) {
2027 if (WARN_ON(--txq->pending_frames < 0))
2028 txq->pending_frames = 0;
2029
2030 if (txq->stopped && txq->pending_frames < ATH_MAX_QDEPTH) {
2031 ieee80211_wake_queue(sc->hw, q);
2032 txq->stopped = false;
2033 }
2034 }
2035
2036 __skb_queue_tail(&txq->complete_q, skb);
2037 }
2038
2039 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
2040 struct ath_txq *txq, struct list_head *bf_q,
2041 struct ath_tx_status *ts, int txok)
2042 {
2043 struct sk_buff *skb = bf->bf_mpdu;
2044 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2045 unsigned long flags;
2046 int tx_flags = 0;
2047
2048 if (!txok)
2049 tx_flags |= ATH_TX_ERROR;
2050
2051 if (ts->ts_status & ATH9K_TXERR_FILT)
2052 tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
2053
2054 dma_unmap_single(sc->dev, bf->bf_buf_addr, skb->len, DMA_TO_DEVICE);
2055 bf->bf_buf_addr = 0;
2056
2057 if (bf->bf_state.bfs_paprd) {
2058 if (time_after(jiffies,
2059 bf->bf_state.bfs_paprd_timestamp +
2060 msecs_to_jiffies(ATH_PAPRD_TIMEOUT)))
2061 dev_kfree_skb_any(skb);
2062 else
2063 complete(&sc->paprd_complete);
2064 } else {
2065 ath_debug_stat_tx(sc, bf, ts, txq, tx_flags);
2066 ath_tx_complete(sc, skb, tx_flags, txq);
2067 }
2068 /* At this point, skb (bf->bf_mpdu) is consumed...make sure we don't
2069 * accidentally reference it later.
2070 */
2071 bf->bf_mpdu = NULL;
2072
2073 /*
2074 * Return the list of ath_buf of this mpdu to free queue
2075 */
2076 spin_lock_irqsave(&sc->tx.txbuflock, flags);
2077 list_splice_tail_init(bf_q, &sc->tx.txbuf);
2078 spin_unlock_irqrestore(&sc->tx.txbuflock, flags);
2079 }
2080
2081 static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
2082 struct ath_tx_status *ts, int nframes, int nbad,
2083 int txok)
2084 {
2085 struct sk_buff *skb = bf->bf_mpdu;
2086 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
2087 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2088 struct ieee80211_hw *hw = sc->hw;
2089 struct ath_hw *ah = sc->sc_ah;
2090 u8 i, tx_rateindex;
2091
2092 if (txok)
2093 tx_info->status.ack_signal = ts->ts_rssi;
2094
2095 tx_rateindex = ts->ts_rateindex;
2096 WARN_ON(tx_rateindex >= hw->max_rates);
2097
2098 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
2099 tx_info->flags |= IEEE80211_TX_STAT_AMPDU;
2100
2101 BUG_ON(nbad > nframes);
2102 }
2103 tx_info->status.ampdu_len = nframes;
2104 tx_info->status.ampdu_ack_len = nframes - nbad;
2105
2106 if ((ts->ts_status & ATH9K_TXERR_FILT) == 0 &&
2107 (tx_info->flags & IEEE80211_TX_CTL_NO_ACK) == 0) {
2108 /*
2109 * If an underrun error is seen assume it as an excessive
2110 * retry only if max frame trigger level has been reached
2111 * (2 KB for single stream, and 4 KB for dual stream).
2112 * Adjust the long retry as if the frame was tried
2113 * hw->max_rate_tries times to affect how rate control updates
2114 * PER for the failed rate.
2115 * In case of congestion on the bus penalizing this type of
2116 * underruns should help hardware actually transmit new frames
2117 * successfully by eventually preferring slower rates.
2118 * This itself should also alleviate congestion on the bus.
2119 */
2120 if (unlikely(ts->ts_flags & (ATH9K_TX_DATA_UNDERRUN |
2121 ATH9K_TX_DELIM_UNDERRUN)) &&
2122 ieee80211_is_data(hdr->frame_control) &&
2123 ah->tx_trig_level >= sc->sc_ah->config.max_txtrig_level)
2124 tx_info->status.rates[tx_rateindex].count =
2125 hw->max_rate_tries;
2126 }
2127
2128 for (i = tx_rateindex + 1; i < hw->max_rates; i++) {
2129 tx_info->status.rates[i].count = 0;
2130 tx_info->status.rates[i].idx = -1;
2131 }
2132
2133 tx_info->status.rates[tx_rateindex].count = ts->ts_longretry + 1;
2134 }
2135
2136 static void ath_tx_process_buffer(struct ath_softc *sc, struct ath_txq *txq,
2137 struct ath_tx_status *ts, struct ath_buf *bf,
2138 struct list_head *bf_head)
2139 {
2140 int txok;
2141
2142 txq->axq_depth--;
2143 txok = !(ts->ts_status & ATH9K_TXERR_MASK);
2144 txq->axq_tx_inprogress = false;
2145 if (bf_is_ampdu_not_probing(bf))
2146 txq->axq_ampdu_depth--;
2147
2148 if (!bf_isampdu(bf)) {
2149 ath_tx_rc_status(sc, bf, ts, 1, txok ? 0 : 1, txok);
2150 ath_tx_complete_buf(sc, bf, txq, bf_head, ts, txok);
2151 } else
2152 ath_tx_complete_aggr(sc, txq, bf, bf_head, ts, txok, true);
2153
2154 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
2155 ath_txq_schedule(sc, txq);
2156 }
2157
2158 static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
2159 {
2160 struct ath_hw *ah = sc->sc_ah;
2161 struct ath_common *common = ath9k_hw_common(ah);
2162 struct ath_buf *bf, *lastbf, *bf_held = NULL;
2163 struct list_head bf_head;
2164 struct ath_desc *ds;
2165 struct ath_tx_status ts;
2166 int status;
2167
2168 ath_dbg(common, QUEUE, "tx queue %d (%x), link %p\n",
2169 txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum),
2170 txq->axq_link);
2171
2172 ath_txq_lock(sc, txq);
2173 for (;;) {
2174 if (work_pending(&sc->hw_reset_work))
2175 break;
2176
2177 if (list_empty(&txq->axq_q)) {
2178 txq->axq_link = NULL;
2179 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
2180 ath_txq_schedule(sc, txq);
2181 break;
2182 }
2183 bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
2184
2185 /*
2186 * There is a race condition that a BH gets scheduled
2187 * after sw writes TxE and before hw re-load the last
2188 * descriptor to get the newly chained one.
2189 * Software must keep the last DONE descriptor as a
2190 * holding descriptor - software does so by marking
2191 * it with the STALE flag.
2192 */
2193 bf_held = NULL;
2194 if (bf->bf_stale) {
2195 bf_held = bf;
2196 if (list_is_last(&bf_held->list, &txq->axq_q))
2197 break;
2198
2199 bf = list_entry(bf_held->list.next, struct ath_buf,
2200 list);
2201 }
2202
2203 lastbf = bf->bf_lastbf;
2204 ds = lastbf->bf_desc;
2205
2206 memset(&ts, 0, sizeof(ts));
2207 status = ath9k_hw_txprocdesc(ah, ds, &ts);
2208 if (status == -EINPROGRESS)
2209 break;
2210
2211 TX_STAT_INC(txq->axq_qnum, txprocdesc);
2212
2213 /*
2214 * Remove ath_buf's of the same transmit unit from txq,
2215 * however leave the last descriptor back as the holding
2216 * descriptor for hw.
2217 */
2218 lastbf->bf_stale = true;
2219 INIT_LIST_HEAD(&bf_head);
2220 if (!list_is_singular(&lastbf->list))
2221 list_cut_position(&bf_head,
2222 &txq->axq_q, lastbf->list.prev);
2223
2224 if (bf_held) {
2225 list_del(&bf_held->list);
2226 ath_tx_return_buffer(sc, bf_held);
2227 }
2228
2229 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
2230 }
2231 ath_txq_unlock_complete(sc, txq);
2232 }
2233
2234 static void ath_tx_complete_poll_work(struct work_struct *work)
2235 {
2236 struct ath_softc *sc = container_of(work, struct ath_softc,
2237 tx_complete_work.work);
2238 struct ath_txq *txq;
2239 int i;
2240 bool needreset = false;
2241 #ifdef CONFIG_ATH9K_DEBUGFS
2242 sc->tx_complete_poll_work_seen++;
2243 #endif
2244
2245 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
2246 if (ATH_TXQ_SETUP(sc, i)) {
2247 txq = &sc->tx.txq[i];
2248 ath_txq_lock(sc, txq);
2249 if (txq->axq_depth) {
2250 if (txq->axq_tx_inprogress) {
2251 needreset = true;
2252 ath_txq_unlock(sc, txq);
2253 break;
2254 } else {
2255 txq->axq_tx_inprogress = true;
2256 }
2257 }
2258 ath_txq_unlock_complete(sc, txq);
2259 }
2260
2261 if (needreset) {
2262 ath_dbg(ath9k_hw_common(sc->sc_ah), RESET,
2263 "tx hung, resetting the chip\n");
2264 RESET_STAT_INC(sc, RESET_TYPE_TX_HANG);
2265 ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
2266 }
2267
2268 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work,
2269 msecs_to_jiffies(ATH_TX_COMPLETE_POLL_INT));
2270 }
2271
2272
2273
2274 void ath_tx_tasklet(struct ath_softc *sc)
2275 {
2276 struct ath_hw *ah = sc->sc_ah;
2277 u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1) & ah->intr_txqs;
2278 int i;
2279
2280 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2281 if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i)))
2282 ath_tx_processq(sc, &sc->tx.txq[i]);
2283 }
2284 }
2285
2286 void ath_tx_edma_tasklet(struct ath_softc *sc)
2287 {
2288 struct ath_tx_status ts;
2289 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2290 struct ath_hw *ah = sc->sc_ah;
2291 struct ath_txq *txq;
2292 struct ath_buf *bf, *lastbf;
2293 struct list_head bf_head;
2294 int status;
2295
2296 for (;;) {
2297 if (work_pending(&sc->hw_reset_work))
2298 break;
2299
2300 status = ath9k_hw_txprocdesc(ah, NULL, (void *)&ts);
2301 if (status == -EINPROGRESS)
2302 break;
2303 if (status == -EIO) {
2304 ath_dbg(common, XMIT, "Error processing tx status\n");
2305 break;
2306 }
2307
2308 /* Process beacon completions separately */
2309 if (ts.qid == sc->beacon.beaconq) {
2310 sc->beacon.tx_processed = true;
2311 sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
2312 continue;
2313 }
2314
2315 txq = &sc->tx.txq[ts.qid];
2316
2317 ath_txq_lock(sc, txq);
2318
2319 if (list_empty(&txq->txq_fifo[txq->txq_tailidx])) {
2320 ath_txq_unlock(sc, txq);
2321 return;
2322 }
2323
2324 bf = list_first_entry(&txq->txq_fifo[txq->txq_tailidx],
2325 struct ath_buf, list);
2326 lastbf = bf->bf_lastbf;
2327
2328 INIT_LIST_HEAD(&bf_head);
2329 list_cut_position(&bf_head, &txq->txq_fifo[txq->txq_tailidx],
2330 &lastbf->list);
2331
2332 if (list_empty(&txq->txq_fifo[txq->txq_tailidx])) {
2333 INCR(txq->txq_tailidx, ATH_TXFIFO_DEPTH);
2334
2335 if (!list_empty(&txq->axq_q)) {
2336 struct list_head bf_q;
2337
2338 INIT_LIST_HEAD(&bf_q);
2339 txq->axq_link = NULL;
2340 list_splice_tail_init(&txq->axq_q, &bf_q);
2341 ath_tx_txqaddbuf(sc, txq, &bf_q, true);
2342 }
2343 }
2344
2345 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
2346 ath_txq_unlock_complete(sc, txq);
2347 }
2348 }
2349
2350 /*****************/
2351 /* Init, Cleanup */
2352 /*****************/
2353
2354 static int ath_txstatus_setup(struct ath_softc *sc, int size)
2355 {
2356 struct ath_descdma *dd = &sc->txsdma;
2357 u8 txs_len = sc->sc_ah->caps.txs_len;
2358
2359 dd->dd_desc_len = size * txs_len;
2360 dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
2361 &dd->dd_desc_paddr, GFP_KERNEL);
2362 if (!dd->dd_desc)
2363 return -ENOMEM;
2364
2365 return 0;
2366 }
2367
2368 static int ath_tx_edma_init(struct ath_softc *sc)
2369 {
2370 int err;
2371
2372 err = ath_txstatus_setup(sc, ATH_TXSTATUS_RING_SIZE);
2373 if (!err)
2374 ath9k_hw_setup_statusring(sc->sc_ah, sc->txsdma.dd_desc,
2375 sc->txsdma.dd_desc_paddr,
2376 ATH_TXSTATUS_RING_SIZE);
2377
2378 return err;
2379 }
2380
2381 static void ath_tx_edma_cleanup(struct ath_softc *sc)
2382 {
2383 struct ath_descdma *dd = &sc->txsdma;
2384
2385 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
2386 dd->dd_desc_paddr);
2387 }
2388
2389 int ath_tx_init(struct ath_softc *sc, int nbufs)
2390 {
2391 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2392 int error = 0;
2393
2394 spin_lock_init(&sc->tx.txbuflock);
2395
2396 error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf,
2397 "tx", nbufs, 1, 1);
2398 if (error != 0) {
2399 ath_err(common,
2400 "Failed to allocate tx descriptors: %d\n", error);
2401 goto err;
2402 }
2403
2404 error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf,
2405 "beacon", ATH_BCBUF, 1, 1);
2406 if (error != 0) {
2407 ath_err(common,
2408 "Failed to allocate beacon descriptors: %d\n", error);
2409 goto err;
2410 }
2411
2412 INIT_DELAYED_WORK(&sc->tx_complete_work, ath_tx_complete_poll_work);
2413
2414 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
2415 error = ath_tx_edma_init(sc);
2416 if (error)
2417 goto err;
2418 }
2419
2420 err:
2421 if (error != 0)
2422 ath_tx_cleanup(sc);
2423
2424 return error;
2425 }
2426
2427 void ath_tx_cleanup(struct ath_softc *sc)
2428 {
2429 if (sc->beacon.bdma.dd_desc_len != 0)
2430 ath_descdma_cleanup(sc, &sc->beacon.bdma, &sc->beacon.bbuf);
2431
2432 if (sc->tx.txdma.dd_desc_len != 0)
2433 ath_descdma_cleanup(sc, &sc->tx.txdma, &sc->tx.txbuf);
2434
2435 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
2436 ath_tx_edma_cleanup(sc);
2437 }
2438
2439 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an)
2440 {
2441 struct ath_atx_tid *tid;
2442 struct ath_atx_ac *ac;
2443 int tidno, acno;
2444
2445 for (tidno = 0, tid = &an->tid[tidno];
2446 tidno < WME_NUM_TID;
2447 tidno++, tid++) {
2448 tid->an = an;
2449 tid->tidno = tidno;
2450 tid->seq_start = tid->seq_next = 0;
2451 tid->baw_size = WME_MAX_BA;
2452 tid->baw_head = tid->baw_tail = 0;
2453 tid->sched = false;
2454 tid->paused = false;
2455 tid->state &= ~AGGR_CLEANUP;
2456 __skb_queue_head_init(&tid->buf_q);
2457 acno = TID_TO_WME_AC(tidno);
2458 tid->ac = &an->ac[acno];
2459 tid->state &= ~AGGR_ADDBA_COMPLETE;
2460 tid->state &= ~AGGR_ADDBA_PROGRESS;
2461 }
2462
2463 for (acno = 0, ac = &an->ac[acno];
2464 acno < WME_NUM_AC; acno++, ac++) {
2465 ac->sched = false;
2466 ac->txq = sc->tx.txq_map[acno];
2467 INIT_LIST_HEAD(&ac->tid_q);
2468 }
2469 }
2470
2471 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an)
2472 {
2473 struct ath_atx_ac *ac;
2474 struct ath_atx_tid *tid;
2475 struct ath_txq *txq;
2476 int tidno;
2477
2478 for (tidno = 0, tid = &an->tid[tidno];
2479 tidno < WME_NUM_TID; tidno++, tid++) {
2480
2481 ac = tid->ac;
2482 txq = ac->txq;
2483
2484 ath_txq_lock(sc, txq);
2485
2486 if (tid->sched) {
2487 list_del(&tid->list);
2488 tid->sched = false;
2489 }
2490
2491 if (ac->sched) {
2492 list_del(&ac->list);
2493 tid->ac->sched = false;
2494 }
2495
2496 ath_tid_drain(sc, txq, tid);
2497 tid->state &= ~AGGR_ADDBA_COMPLETE;
2498 tid->state &= ~AGGR_CLEANUP;
2499
2500 ath_txq_unlock(sc, txq);
2501 }
2502 }
Linux kernel - Deliverables
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