drivers/net/wireless/ath/wil6210/wil6210.h

   1 /*
   2  * Copyright (c) 2012-2015 Qualcomm Atheros, Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #ifndef __WIL6210_H__
  18 #define __WIL6210_H__
  19
  20 #include <linux/netdevice.h>
  21 #include <linux/wireless.h>
  22 #include <net/cfg80211.h>
  23 #include <linux/timex.h>
  24 #include "wil_platform.h"
  25
  26 extern bool no_fw_recovery;
  27 extern unsigned int mtu_max;
  28 extern unsigned short rx_ring_overflow_thrsh;
  29 extern int agg_wsize;
  30 extern u32 vring_idle_trsh;
  31
  32 #define WIL_NAME "wil6210"
  33 #define WIL_FW_NAME "wil6210.fw" /* code */
  34 #define WIL_FW2_NAME "wil6210.board" /* board & radio parameters */
  35
  36 #define WIL_MAX_BUS_REQUEST_KBPS 800000 /* ~6.1Gbps */
  37
  38 /**
  39  * extract bits [@b0:@b1] (inclusive) from the value @x
  40  * it should be @b0 <= @b1, or result is incorrect
  41  */
  42 static inline u32 WIL_GET_BITS(u32 x, int b0, int b1)
  43 {
  44         return (x >> b0) & ((1 << (b1 - b0 + 1)) - 1);
  45 }
  46
  47 #define WIL6210_MEM_SIZE (2*1024*1024UL)
  48
  49 #define WIL_TX_Q_LEN_DEFAULT            (4000)
  50 #define WIL_RX_RING_SIZE_ORDER_DEFAULT  (10)
  51 #define WIL_TX_RING_SIZE_ORDER_DEFAULT  (10)
  52 /* limit ring size in range [32..32k] */
  53 #define WIL_RING_SIZE_ORDER_MIN (5)
  54 #define WIL_RING_SIZE_ORDER_MAX (15)
  55 #define WIL6210_MAX_TX_RINGS    (24) /* HW limit */
  56 #define WIL6210_MAX_CID         (8) /* HW limit */
  57 #define WIL6210_NAPI_BUDGET     (16) /* arbitrary */
  58 #define WIL_MAX_AMPDU_SIZE      (64 * 1024) /* FW/HW limit */
  59 #define WIL_MAX_AGG_WSIZE       (32) /* FW/HW limit */
  60 /* Hardware offload block adds the following:
  61  * 26 bytes - 3-address QoS data header
  62  *  8 bytes - IV + EIV (for GCMP)
  63  *  8 bytes - SNAP
  64  * 16 bytes - MIC (for GCMP)
  65  *  4 bytes - CRC
  66  */
  67 #define WIL_MAX_MPDU_OVERHEAD   (62)
  68
  69 /* Calculate MAC buffer size for the firmware. It includes all overhead,
  70  * as it will go over the air, and need to be 8 byte aligned
  71  */
  72 static inline u32 wil_mtu2macbuf(u32 mtu)
  73 {
  74         return ALIGN(mtu + WIL_MAX_MPDU_OVERHEAD, 8);
  75 }
  76
  77 /* MTU for Ethernet need to take into account 8-byte SNAP header
  78  * to be added when encapsulating Ethernet frame into 802.11
  79  */
  80 #define WIL_MAX_ETH_MTU         (IEEE80211_MAX_DATA_LEN_DMG - 8)
  81 /* Max supported by wil6210 value for interrupt threshold is 5sec. */
  82 #define WIL6210_ITR_TRSH_MAX (5000000)
  83 #define WIL6210_ITR_TX_INTERFRAME_TIMEOUT_DEFAULT (13) /* usec */
  84 #define WIL6210_ITR_RX_INTERFRAME_TIMEOUT_DEFAULT (13) /* usec */
  85 #define WIL6210_ITR_TX_MAX_BURST_DURATION_DEFAULT (500) /* usec */
  86 #define WIL6210_ITR_RX_MAX_BURST_DURATION_DEFAULT (500) /* usec */
  87 #define WIL6210_FW_RECOVERY_RETRIES     (5) /* try to recover this many times */
  88 #define WIL6210_FW_RECOVERY_TO  msecs_to_jiffies(5000)
  89 #define WIL6210_SCAN_TO         msecs_to_jiffies(10000)
  90 #define WIL6210_RX_HIGH_TRSH_INIT               (0)
  91 #define WIL6210_RX_HIGH_TRSH_DEFAULT \
  92                                 (1 << (WIL_RX_RING_SIZE_ORDER_DEFAULT - 3))
  93 /* Hardware definitions begin */
  94
  95 /*
  96  * Mapping
  97  * RGF File      | Host addr    |  FW addr
  98  *               |              |
  99  * user_rgf      | 0x000000     | 0x880000
 100  *  dma_rgf      | 0x001000     | 0x881000
 101  * pcie_rgf      | 0x002000     | 0x882000
 102  *               |              |
 103  */
 104
 105 /* Where various structures placed in host address space */
 106 #define WIL6210_FW_HOST_OFF      (0x880000UL)
 107
 108 #define HOSTADDR(fwaddr)        (fwaddr - WIL6210_FW_HOST_OFF)
 109
 110 /*
 111  * Interrupt control registers block
 112  *
 113  * each interrupt controlled by the same bit in all registers
 114  */
 115 struct RGF_ICR {
 116         u32 ICC; /* Cause Control, RW: 0 - W1C, 1 - COR */
 117         u32 ICR; /* Cause, W1C/COR depending on ICC */
 118         u32 ICM; /* Cause masked (ICR & ~IMV), W1C/COR depending on ICC */
 119         u32 ICS; /* Cause Set, WO */
 120         u32 IMV; /* Mask, RW+S/C */
 121         u32 IMS; /* Mask Set, write 1 to set */
 122         u32 IMC; /* Mask Clear, write 1 to clear */
 123 } __packed;
 124
 125 struct RGF_BL {
 126         u32 ready;              /* 0x880A3C bit [0] */
 127 #define BIT_BL_READY    BIT(0)
 128         u32 version;            /* 0x880A40 version of the BL struct */
 129         u32 rf_type;            /* 0x880A44 ID of the connected RF */
 130         u32 baseband_type;      /* 0x880A48 ID of the baseband */
 131         u8  mac_address[ETH_ALEN]; /* 0x880A4C permanent MAC */
 132         u8 pad[2];
 133 } __packed;
 134
 135 /* registers - FW addresses */
 136 #define RGF_USER_USAGE_1                (0x880004)
 137 #define RGF_USER_USAGE_6                (0x880018)
 138 #define RGF_USER_HW_MACHINE_STATE       (0x8801dc)
 139         #define HW_MACHINE_BOOT_DONE    (0x3fffffd)
 140 #define RGF_USER_USER_CPU_0             (0x8801e0)
 141         #define BIT_USER_USER_CPU_MAN_RST       BIT(1) /* user_cpu_man_rst */
 142 #define RGF_USER_MAC_CPU_0              (0x8801fc)
 143         #define BIT_USER_MAC_CPU_MAN_RST        BIT(1) /* mac_cpu_man_rst */
 144 #define RGF_USER_USER_SCRATCH_PAD       (0x8802bc)
 145 #define RGF_USER_BL                     (0x880A3C) /* Boot Loader */
 146 #define RGF_USER_FW_REV_ID              (0x880a8c) /* chip revision */
 147 #define RGF_USER_CLKS_CTL_0             (0x880abc)
 148         #define BIT_USER_CLKS_CAR_AHB_SW_SEL    BIT(1) /* ref clk/PLL */
 149         #define BIT_USER_CLKS_RST_PWGD  BIT(11) /* reset on "power good" */
 150 #define RGF_USER_CLKS_CTL_SW_RST_VEC_0  (0x880b04)
 151 #define RGF_USER_CLKS_CTL_SW_RST_VEC_1  (0x880b08)
 152 #define RGF_USER_CLKS_CTL_SW_RST_VEC_2  (0x880b0c)
 153 #define RGF_USER_CLKS_CTL_SW_RST_VEC_3  (0x880b10)
 154 #define RGF_USER_CLKS_CTL_SW_RST_MASK_0 (0x880b14)
 155         #define BIT_HPAL_PERST_FROM_PAD BIT(6)
 156         #define BIT_CAR_PERST_RST       BIT(7)
 157 #define RGF_USER_USER_ICR               (0x880b4c) /* struct RGF_ICR */
 158         #define BIT_USER_USER_ICR_SW_INT_2      BIT(18)
 159 #define RGF_USER_CLKS_CTL_EXT_SW_RST_VEC_0      (0x880c18)
 160 #define RGF_USER_CLKS_CTL_EXT_SW_RST_VEC_1      (0x880c2c)
 161 #define RGF_USER_SPARROW_M_4                    (0x880c50) /* Sparrow */
 162         #define BIT_SPARROW_M_4_SEL_SLEEP_OR_REF        BIT(2)
 163
 164 #define RGF_DMA_EP_TX_ICR               (0x881bb4) /* struct RGF_ICR */
 165         #define BIT_DMA_EP_TX_ICR_TX_DONE       BIT(0)
 166         #define BIT_DMA_EP_TX_ICR_TX_DONE_N(n)  BIT(n+1) /* n = [0..23] */
 167 #define RGF_DMA_EP_RX_ICR               (0x881bd0) /* struct RGF_ICR */
 168         #define BIT_DMA_EP_RX_ICR_RX_DONE       BIT(0)
 169         #define BIT_DMA_EP_RX_ICR_RX_HTRSH      BIT(1)
 170 #define RGF_DMA_EP_MISC_ICR             (0x881bec) /* struct RGF_ICR */
 171         #define BIT_DMA_EP_MISC_ICR_RX_HTRSH    BIT(0)
 172         #define BIT_DMA_EP_MISC_ICR_TX_NO_ACT   BIT(1)
 173         #define BIT_DMA_EP_MISC_ICR_FW_INT(n)   BIT(28+n) /* n = [0..3] */
 174
 175 /* Legacy interrupt moderation control (before Sparrow v2)*/
 176 #define RGF_DMA_ITR_CNT_TRSH            (0x881c5c)
 177 #define RGF_DMA_ITR_CNT_DATA            (0x881c60)
 178 #define RGF_DMA_ITR_CNT_CRL             (0x881c64)
 179         #define BIT_DMA_ITR_CNT_CRL_EN          BIT(0)
 180         #define BIT_DMA_ITR_CNT_CRL_EXT_TICK    BIT(1)
 181         #define BIT_DMA_ITR_CNT_CRL_FOREVER     BIT(2)
 182         #define BIT_DMA_ITR_CNT_CRL_CLR         BIT(3)
 183         #define BIT_DMA_ITR_CNT_CRL_REACH_TRSH  BIT(4)
 184
 185 /* Offload control (Sparrow B0+) */
 186 #define RGF_DMA_OFUL_NID_0              (0x881cd4)
 187         #define BIT_DMA_OFUL_NID_0_RX_EXT_TR_EN         BIT(0)
 188         #define BIT_DMA_OFUL_NID_0_TX_EXT_TR_EN         BIT(1)
 189         #define BIT_DMA_OFUL_NID_0_RX_EXT_A3_SRC        BIT(2)
 190         #define BIT_DMA_OFUL_NID_0_TX_EXT_A3_SRC        BIT(3)
 191
 192 /* New (sparrow v2+) interrupt moderation control */
 193 #define RGF_DMA_ITR_TX_DESQ_NO_MOD              (0x881d40)
 194 #define RGF_DMA_ITR_TX_CNT_TRSH                 (0x881d34)
 195 #define RGF_DMA_ITR_TX_CNT_DATA                 (0x881d38)
 196 #define RGF_DMA_ITR_TX_CNT_CTL                  (0x881d3c)
 197         #define BIT_DMA_ITR_TX_CNT_CTL_EN               BIT(0)
 198         #define BIT_DMA_ITR_TX_CNT_CTL_EXT_TIC_SEL      BIT(1)
 199         #define BIT_DMA_ITR_TX_CNT_CTL_FOREVER          BIT(2)
 200         #define BIT_DMA_ITR_TX_CNT_CTL_CLR              BIT(3)
 201         #define BIT_DMA_ITR_TX_CNT_CTL_REACHED_TRESH    BIT(4)
 202         #define BIT_DMA_ITR_TX_CNT_CTL_CROSS_EN         BIT(5)
 203         #define BIT_DMA_ITR_TX_CNT_CTL_FREE_RUNNIG      BIT(6)
 204 #define RGF_DMA_ITR_TX_IDL_CNT_TRSH                     (0x881d60)
 205 #define RGF_DMA_ITR_TX_IDL_CNT_DATA                     (0x881d64)
 206 #define RGF_DMA_ITR_TX_IDL_CNT_CTL                      (0x881d68)
 207         #define BIT_DMA_ITR_TX_IDL_CNT_CTL_EN                   BIT(0)
 208         #define BIT_DMA_ITR_TX_IDL_CNT_CTL_EXT_TIC_SEL          BIT(1)
 209         #define BIT_DMA_ITR_TX_IDL_CNT_CTL_FOREVER              BIT(2)
 210         #define BIT_DMA_ITR_TX_IDL_CNT_CTL_CLR                  BIT(3)
 211         #define BIT_DMA_ITR_TX_IDL_CNT_CTL_REACHED_TRESH        BIT(4)
 212 #define RGF_DMA_ITR_RX_DESQ_NO_MOD              (0x881d50)
 213 #define RGF_DMA_ITR_RX_CNT_TRSH                 (0x881d44)
 214 #define RGF_DMA_ITR_RX_CNT_DATA                 (0x881d48)
 215 #define RGF_DMA_ITR_RX_CNT_CTL                  (0x881d4c)
 216         #define BIT_DMA_ITR_RX_CNT_CTL_EN               BIT(0)
 217         #define BIT_DMA_ITR_RX_CNT_CTL_EXT_TIC_SEL      BIT(1)
 218         #define BIT_DMA_ITR_RX_CNT_CTL_FOREVER          BIT(2)
 219         #define BIT_DMA_ITR_RX_CNT_CTL_CLR              BIT(3)
 220         #define BIT_DMA_ITR_RX_CNT_CTL_REACHED_TRESH    BIT(4)
 221         #define BIT_DMA_ITR_RX_CNT_CTL_CROSS_EN         BIT(5)
 222         #define BIT_DMA_ITR_RX_CNT_CTL_FREE_RUNNIG      BIT(6)
 223 #define RGF_DMA_ITR_RX_IDL_CNT_TRSH                     (0x881d54)
 224 #define RGF_DMA_ITR_RX_IDL_CNT_DATA                     (0x881d58)
 225 #define RGF_DMA_ITR_RX_IDL_CNT_CTL                      (0x881d5c)
 226         #define BIT_DMA_ITR_RX_IDL_CNT_CTL_EN                   BIT(0)
 227         #define BIT_DMA_ITR_RX_IDL_CNT_CTL_EXT_TIC_SEL          BIT(1)
 228         #define BIT_DMA_ITR_RX_IDL_CNT_CTL_FOREVER              BIT(2)
 229         #define BIT_DMA_ITR_RX_IDL_CNT_CTL_CLR                  BIT(3)
 230         #define BIT_DMA_ITR_RX_IDL_CNT_CTL_REACHED_TRESH        BIT(4)
 231
 232 #define RGF_DMA_PSEUDO_CAUSE            (0x881c68)
 233 #define RGF_DMA_PSEUDO_CAUSE_MASK_SW    (0x881c6c)
 234 #define RGF_DMA_PSEUDO_CAUSE_MASK_FW    (0x881c70)
 235         #define BIT_DMA_PSEUDO_CAUSE_RX         BIT(0)
 236         #define BIT_DMA_PSEUDO_CAUSE_TX         BIT(1)
 237         #define BIT_DMA_PSEUDO_CAUSE_MISC       BIT(2)
 238
 239 #define RGF_HP_CTRL                     (0x88265c)
 240 #define RGF_PCIE_LOS_COUNTER_CTL        (0x882dc4)
 241
 242 /* MAC timer, usec, for packet lifetime */
 243 #define RGF_MAC_MTRL_COUNTER_0          (0x886aa8)
 244
 245 #define RGF_CAF_ICR                     (0x88946c) /* struct RGF_ICR */
 246 #define RGF_CAF_OSC_CONTROL             (0x88afa4)
 247         #define BIT_CAF_OSC_XTAL_EN             BIT(0)
 248 #define RGF_CAF_PLL_LOCK_STATUS         (0x88afec)
 249         #define BIT_CAF_OSC_DIG_XTAL_STABLE     BIT(0)
 250
 251 #define RGF_USER_JTAG_DEV_ID    (0x880b34) /* device ID */
 252         #define JTAG_DEV_ID_SPARROW_B0  (0x2632072f)
 253
 254 enum {
 255         HW_VER_UNKNOWN,
 256         HW_VER_SPARROW_B0, /* JTAG_DEV_ID_SPARROW_B0 */
 257 };
 258
 259 /* popular locations */
 260 #define HOST_MBOX   HOSTADDR(RGF_USER_USER_SCRATCH_PAD)
 261 #define HOST_SW_INT (HOSTADDR(RGF_USER_USER_ICR) + \
 262         offsetof(struct RGF_ICR, ICS))
 263 #define SW_INT_MBOX BIT_USER_USER_ICR_SW_INT_2
 264
 265 /* ISR register bits */
 266 #define ISR_MISC_FW_READY       BIT_DMA_EP_MISC_ICR_FW_INT(0)
 267 #define ISR_MISC_MBOX_EVT       BIT_DMA_EP_MISC_ICR_FW_INT(1)
 268 #define ISR_MISC_FW_ERROR       BIT_DMA_EP_MISC_ICR_FW_INT(3)
 269
 270 /* Hardware definitions end */
 271 struct fw_map {
 272         u32 from; /* linker address - from, inclusive */
 273         u32 to;   /* linker address - to, exclusive */
 274         u32 host; /* PCI/Host address - BAR0 + 0x880000 */
 275         const char *name; /* for debugfs */
 276 };
 277
 278 /* array size should be in sync with actual definition in the wmi.c */
 279 extern const struct fw_map fw_mapping[7];
 280
 281 /**
 282  * mk_cidxtid - construct @cidxtid field
 283  * @cid: CID value
 284  * @tid: TID value
 285  *
 286  * @cidxtid field encoded as bits 0..3 - CID; 4..7 - TID
 287  */
 288 static inline u8 mk_cidxtid(u8 cid, u8 tid)
 289 {
 290         return ((tid & 0xf) << 4) | (cid & 0xf);
 291 }
 292
 293 /**
 294  * parse_cidxtid - parse @cidxtid field
 295  * @cid: store CID value here
 296  * @tid: store TID value here
 297  *
 298  * @cidxtid field encoded as bits 0..3 - CID; 4..7 - TID
 299  */
 300 static inline void parse_cidxtid(u8 cidxtid, u8 *cid, u8 *tid)
 301 {
 302         *cid = cidxtid & 0xf;
 303         *tid = (cidxtid >> 4) & 0xf;
 304 }
 305
 306 struct wil6210_mbox_ring {
 307         u32 base;
 308         u16 entry_size; /* max. size of mbox entry, incl. all headers */
 309         u16 size;
 310         u32 tail;
 311         u32 head;
 312 } __packed;
 313
 314 struct wil6210_mbox_ring_desc {
 315         __le32 sync;
 316         __le32 addr;
 317 } __packed;
 318
 319 /* at HOST_OFF_WIL6210_MBOX_CTL */
 320 struct wil6210_mbox_ctl {
 321         struct wil6210_mbox_ring tx;
 322         struct wil6210_mbox_ring rx;
 323 } __packed;
 324
 325 struct wil6210_mbox_hdr {
 326         __le16 seq;
 327         __le16 len; /* payload, bytes after this header */
 328         __le16 type;
 329         u8 flags;
 330         u8 reserved;
 331 } __packed;
 332
 333 #define WIL_MBOX_HDR_TYPE_WMI (0)
 334
 335 /* max. value for wil6210_mbox_hdr.len */
 336 #define MAX_MBOXITEM_SIZE   (240)
 337
 338 /**
 339  * struct wil6210_mbox_hdr_wmi - WMI header
 340  *
 341  * @mid: MAC ID
 342  *      00 - default, created by FW
 343  *      01..0f - WiFi ports, driver to create
 344  *      10..fe - debug
 345  *      ff - broadcast
 346  * @id: command/event ID
 347  * @timestamp: FW fills for events, free-running msec timer
 348  */
 349 struct wil6210_mbox_hdr_wmi {
 350         u8 mid;
 351         u8 reserved;
 352         __le16 id;
 353         __le32 timestamp;
 354 } __packed;
 355
 356 struct pending_wmi_event {
 357         struct list_head list;
 358         struct {
 359                 struct wil6210_mbox_hdr hdr;
 360                 struct wil6210_mbox_hdr_wmi wmi;
 361                 u8 data[0];
 362         } __packed event;
 363 };
 364
 365 enum { /* for wil_ctx.mapped_as */
 366         wil_mapped_as_none = 0,
 367         wil_mapped_as_single = 1,
 368         wil_mapped_as_page = 2,
 369 };
 370
 371 /**
 372  * struct wil_ctx - software context for Vring descriptor
 373  */
 374 struct wil_ctx {
 375         struct sk_buff *skb;
 376         u8 nr_frags;
 377         u8 mapped_as;
 378 };
 379
 380 union vring_desc;
 381
 382 struct vring {
 383         dma_addr_t pa;
 384         volatile union vring_desc *va; /* vring_desc[size], WriteBack by DMA */
 385         u16 size; /* number of vring_desc elements */
 386         u32 swtail;
 387         u32 swhead;
 388         u32 hwtail; /* write here to inform hw */
 389         struct wil_ctx *ctx; /* ctx[size] - software context */
 390 };
 391
 392 /**
 393  * Additional data for Tx Vring
 394  */
 395 struct vring_tx_data {
 396         int enabled;
 397         cycles_t idle, last_idle, begin;
 398         u8 agg_wsize; /* agreed aggregation window, 0 - no agg */
 399         u16 agg_timeout;
 400         u8 agg_amsdu;
 401         bool addba_in_progress; /* if set, agg_xxx is for request in progress */
 402         spinlock_t lock;
 403 };
 404
 405 enum { /* for wil6210_priv.status */
 406         wil_status_fwready = 0,
 407         wil_status_fwconnecting,
 408         wil_status_fwconnected,
 409         wil_status_dontscan,
 410         wil_status_reset_done,
 411         wil_status_irqen, /* FIXME: interrupts enabled - for debug */
 412         wil_status_napi_en, /* NAPI enabled protected by wil->mutex */
 413         wil_status_last /* keep last */
 414 };
 415
 416 struct pci_dev;
 417
 418 /**
 419  * struct tid_ampdu_rx - TID aggregation information (Rx).
 420  *
 421  * @reorder_buf: buffer to reorder incoming aggregated MPDUs
 422  * @reorder_time: jiffies when skb was added
 423  * @session_timer: check if peer keeps Tx-ing on the TID (by timeout value)
 424  * @reorder_timer: releases expired frames from the reorder buffer.
 425  * @last_rx: jiffies of last rx activity
 426  * @head_seq_num: head sequence number in reordering buffer.
 427  * @stored_mpdu_num: number of MPDUs in reordering buffer
 428  * @ssn: Starting Sequence Number expected to be aggregated.
 429  * @buf_size: buffer size for incoming A-MPDUs
 430  * @timeout: reset timer value (in TUs).
 431  * @dialog_token: dialog token for aggregation session
 432  * @rcu_head: RCU head used for freeing this struct
 433  *
 434  * This structure's lifetime is managed by RCU, assignments to
 435  * the array holding it must hold the aggregation mutex.
 436  *
 437  */
 438 struct wil_tid_ampdu_rx {
 439         struct sk_buff **reorder_buf;
 440         unsigned long *reorder_time;
 441         struct timer_list session_timer;
 442         struct timer_list reorder_timer;
 443         unsigned long last_rx;
 444         u16 head_seq_num;
 445         u16 stored_mpdu_num;
 446         u16 ssn;
 447         u16 buf_size;
 448         u16 timeout;
 449         u16 ssn_last_drop;
 450         u8 dialog_token;
 451         bool first_time; /* is it 1-st time this buffer used? */
 452 };
 453
 454 enum wil_sta_status {
 455         wil_sta_unused = 0,
 456         wil_sta_conn_pending = 1,
 457         wil_sta_connected = 2,
 458 };
 459
 460 #define WIL_STA_TID_NUM (16)
 461
 462 struct wil_net_stats {
 463         unsigned long   rx_packets;
 464         unsigned long   tx_packets;
 465         unsigned long   rx_bytes;
 466         unsigned long   tx_bytes;
 467         unsigned long   tx_errors;
 468         unsigned long   rx_dropped;
 469         u16 last_mcs_rx;
 470 };
 471
 472 /**
 473  * struct wil_sta_info - data for peer
 474  *
 475  * Peer identified by its CID (connection ID)
 476  * NIC performs beam forming for each peer;
 477  * if no beam forming done, frame exchange is not
 478  * possible.
 479  */
 480 struct wil_sta_info {
 481         u8 addr[ETH_ALEN];
 482         enum wil_sta_status status;
 483         struct wil_net_stats stats;
 484         bool data_port_open; /* can send any data, not only EAPOL */
 485         /* Rx BACK */
 486         struct wil_tid_ampdu_rx *tid_rx[WIL_STA_TID_NUM];
 487         spinlock_t tid_rx_lock; /* guarding tid_rx array */
 488         unsigned long tid_rx_timer_expired[BITS_TO_LONGS(WIL_STA_TID_NUM)];
 489         unsigned long tid_rx_stop_requested[BITS_TO_LONGS(WIL_STA_TID_NUM)];
 490 };
 491
 492 enum {
 493         fw_recovery_idle = 0,
 494         fw_recovery_pending = 1,
 495         fw_recovery_running = 2,
 496 };
 497
 498 enum {
 499         hw_capability_last
 500 };
 501
 502 struct wil_back_rx {
 503         struct list_head list;
 504         /* request params, converted to CPU byte order - what we asked for */
 505         u8 cidxtid;
 506         u8 dialog_token;
 507         u16 ba_param_set;
 508         u16 ba_timeout;
 509         u16 ba_seq_ctrl;
 510 };
 511
 512 struct wil_back_tx {
 513         struct list_head list;
 514         /* request params, converted to CPU byte order - what we asked for */
 515         u8 ringid;
 516         u8 agg_wsize;
 517         u16 agg_timeout;
 518 };
 519
 520 struct wil_probe_client_req {
 521         struct list_head list;
 522         u64 cookie;
 523         u8 cid;
 524 };
 525
 526 struct wil6210_priv {
 527         struct pci_dev *pdev;
 528         int n_msi;
 529         struct wireless_dev *wdev;
 530         void __iomem *csr;
 531         DECLARE_BITMAP(status, wil_status_last);
 532         u32 fw_version;
 533         u32 hw_version;
 534         const char *hw_name;
 535         DECLARE_BITMAP(hw_capabilities, hw_capability_last);
 536         u8 n_mids; /* number of additional MIDs as reported by FW */
 537         u32 recovery_count; /* num of FW recovery attempts in a short time */
 538         u32 recovery_state; /* FW recovery state machine */
 539         unsigned long last_fw_recovery; /* jiffies of last fw recovery */
 540         wait_queue_head_t wq; /* for all wait_event() use */
 541         /* profile */
 542         u32 monitor_flags;
 543         u32 privacy; /* secure connection? */
 544         int sinfo_gen;
 545         u32 ap_isolate; /* no intra-BSS communication */
 546         /* interrupt moderation */
 547         u32 tx_max_burst_duration;
 548         u32 tx_interframe_timeout;
 549         u32 rx_max_burst_duration;
 550         u32 rx_interframe_timeout;
 551         /* cached ISR registers */
 552         u32 isr_misc;
 553         /* mailbox related */
 554         struct mutex wmi_mutex;
 555         struct wil6210_mbox_ctl mbox_ctl;
 556         struct completion wmi_ready;
 557         struct completion wmi_call;
 558         u16 wmi_seq;
 559         u16 reply_id; /**< wait for this WMI event */
 560         void *reply_buf;
 561         u16 reply_size;
 562         struct workqueue_struct *wmi_wq; /* for deferred calls */
 563         struct work_struct wmi_event_worker;
 564         struct workqueue_struct *wq_service;
 565         struct work_struct connect_worker;
 566         struct work_struct disconnect_worker;
 567         struct work_struct fw_error_worker;     /* for FW error recovery */
 568         struct timer_list connect_timer;
 569         struct timer_list scan_timer; /* detect scan timeout */
 570         int pending_connect_cid;
 571         struct list_head pending_wmi_ev;
 572         /*
 573          * protect pending_wmi_ev
 574          * - fill in IRQ from wil6210_irq_misc,
 575          * - consumed in thread by wmi_event_worker
 576          */
 577         spinlock_t wmi_ev_lock;
 578         struct napi_struct napi_rx;
 579         struct napi_struct napi_tx;
 580         /* BACK */
 581         struct list_head back_rx_pending;
 582         struct mutex back_rx_mutex; /* protect @back_rx_pending */
 583         struct work_struct back_rx_worker;
 584         struct list_head back_tx_pending;
 585         struct mutex back_tx_mutex; /* protect @back_tx_pending */
 586         struct work_struct back_tx_worker;
 587         /* keep alive */
 588         struct list_head probe_client_pending;
 589         struct mutex probe_client_mutex; /* protect @probe_client_pending */
 590         struct work_struct probe_client_worker;
 591         /* DMA related */
 592         struct vring vring_rx;
 593         struct vring vring_tx[WIL6210_MAX_TX_RINGS];
 594         struct vring_tx_data vring_tx_data[WIL6210_MAX_TX_RINGS];
 595         u8 vring2cid_tid[WIL6210_MAX_TX_RINGS][2]; /* [0] - CID, [1] - TID */
 596         struct wil_sta_info sta[WIL6210_MAX_CID];
 597         /* scan */
 598         struct cfg80211_scan_request *scan_request;
 599
 600         struct mutex mutex; /* for wil6210_priv access in wil_{up|down} */
 601         /* statistics */
 602         atomic_t isr_count_rx, isr_count_tx;
 603         /* debugfs */
 604         struct dentry *debug;
 605         struct debugfs_blob_wrapper blobs[ARRAY_SIZE(fw_mapping)];
 606
 607         void *platform_handle;
 608         struct wil_platform_ops platform_ops;
 609 };
 610
 611 #define wil_to_wiphy(i) (i->wdev->wiphy)
 612 #define wil_to_dev(i) (wiphy_dev(wil_to_wiphy(i)))
 613 #define wiphy_to_wil(w) (struct wil6210_priv *)(wiphy_priv(w))
 614 #define wil_to_wdev(i) (i->wdev)
 615 #define wdev_to_wil(w) (struct wil6210_priv *)(wdev_priv(w))
 616 #define wil_to_ndev(i) (wil_to_wdev(i)->netdev)
 617 #define ndev_to_wil(n) (wdev_to_wil(n->ieee80211_ptr))
 618
 619 __printf(2, 3)
 620 void wil_dbg_trace(struct wil6210_priv *wil, const char *fmt, ...);
 621 __printf(2, 3)
 622 void wil_err(struct wil6210_priv *wil, const char *fmt, ...);
 623 __printf(2, 3)
 624 void wil_err_ratelimited(struct wil6210_priv *wil, const char *fmt, ...);
 625 __printf(2, 3)
 626 void wil_info(struct wil6210_priv *wil, const char *fmt, ...);
 627 #define wil_dbg(wil, fmt, arg...) do { \
 628         netdev_dbg(wil_to_ndev(wil), fmt, ##arg); \
 629         wil_dbg_trace(wil, fmt, ##arg); \
 630 } while (0)
 631
 632 #define wil_dbg_irq(wil, fmt, arg...) wil_dbg(wil, "DBG[ IRQ]" fmt, ##arg)
 633 #define wil_dbg_txrx(wil, fmt, arg...) wil_dbg(wil, "DBG[TXRX]" fmt, ##arg)
 634 #define wil_dbg_wmi(wil, fmt, arg...) wil_dbg(wil, "DBG[ WMI]" fmt, ##arg)
 635 #define wil_dbg_misc(wil, fmt, arg...) wil_dbg(wil, "DBG[MISC]" fmt, ##arg)
 636
 637 #if defined(CONFIG_DYNAMIC_DEBUG)
 638 #define wil_hex_dump_txrx(prefix_str, prefix_type, rowsize,     \
 639                           groupsize, buf, len, ascii)           \
 640                           print_hex_dump_debug("DBG[TXRX]" prefix_str,\
 641                                          prefix_type, rowsize,  \
 642                                          groupsize, buf, len, ascii)
 643
 644 #define wil_hex_dump_wmi(prefix_str, prefix_type, rowsize,      \
 645                          groupsize, buf, len, ascii)            \
 646                          print_hex_dump_debug("DBG[ WMI]" prefix_str,\
 647                                         prefix_type, rowsize,   \
 648                                         groupsize, buf, len, ascii)
 649 #else /* defined(CONFIG_DYNAMIC_DEBUG) */
 650 static inline
 651 void wil_hex_dump_txrx(const char *prefix_str, int prefix_type, int rowsize,
 652                        int groupsize, const void *buf, size_t len, bool ascii)
 653 {
 654 }
 655
 656 static inline
 657 void wil_hex_dump_wmi(const char *prefix_str, int prefix_type, int rowsize,
 658                       int groupsize, const void *buf, size_t len, bool ascii)
 659 {
 660 }
 661 #endif /* defined(CONFIG_DYNAMIC_DEBUG) */
 662
 663 void wil_memcpy_fromio_32(void *dst, const volatile void __iomem *src,
 664                           size_t count);
 665 void wil_memcpy_toio_32(volatile void __iomem *dst, const void *src,
 666                         size_t count);
 667
 668 void *wil_if_alloc(struct device *dev, void __iomem *csr);
 669 void wil_if_free(struct wil6210_priv *wil);
 670 int wil_if_add(struct wil6210_priv *wil);
 671 void wil_if_remove(struct wil6210_priv *wil);
 672 int wil_priv_init(struct wil6210_priv *wil);
 673 void wil_priv_deinit(struct wil6210_priv *wil);
 674 int wil_reset(struct wil6210_priv *wil, bool no_fw);
 675 void wil_fw_error_recovery(struct wil6210_priv *wil);
 676 void wil_set_recovery_state(struct wil6210_priv *wil, int state);
 677 int wil_up(struct wil6210_priv *wil);
 678 int __wil_up(struct wil6210_priv *wil);
 679 int wil_down(struct wil6210_priv *wil);
 680 int __wil_down(struct wil6210_priv *wil);
 681 void wil_mbox_ring_le2cpus(struct wil6210_mbox_ring *r);
 682 int wil_find_cid(struct wil6210_priv *wil, const u8 *mac);
 683 void wil_set_ethtoolops(struct net_device *ndev);
 684
 685 void __iomem *wmi_buffer(struct wil6210_priv *wil, __le32 ptr);
 686 void __iomem *wmi_addr(struct wil6210_priv *wil, u32 ptr);
 687 int wmi_read_hdr(struct wil6210_priv *wil, __le32 ptr,
 688                  struct wil6210_mbox_hdr *hdr);
 689 int wmi_send(struct wil6210_priv *wil, u16 cmdid, void *buf, u16 len);
 690 void wmi_recv_cmd(struct wil6210_priv *wil);
 691 int wmi_call(struct wil6210_priv *wil, u16 cmdid, void *buf, u16 len,
 692              u16 reply_id, void *reply, u8 reply_size, int to_msec);
 693 void wmi_event_worker(struct work_struct *work);
 694 void wmi_event_flush(struct wil6210_priv *wil);
 695 int wmi_set_ssid(struct wil6210_priv *wil, u8 ssid_len, const void *ssid);
 696 int wmi_get_ssid(struct wil6210_priv *wil, u8 *ssid_len, void *ssid);
 697 int wmi_set_channel(struct wil6210_priv *wil, int channel);
 698 int wmi_get_channel(struct wil6210_priv *wil, int *channel);
 699 int wmi_del_cipher_key(struct wil6210_priv *wil, u8 key_index,
 700                        const void *mac_addr);
 701 int wmi_add_cipher_key(struct wil6210_priv *wil, u8 key_index,
 702                        const void *mac_addr, int key_len, const void *key);
 703 int wmi_echo(struct wil6210_priv *wil);
 704 int wmi_set_ie(struct wil6210_priv *wil, u8 type, u16 ie_len, const void *ie);
 705 int wmi_rx_chain_add(struct wil6210_priv *wil, struct vring *vring);
 706 int wmi_p2p_cfg(struct wil6210_priv *wil, int channel);
 707 int wmi_rxon(struct wil6210_priv *wil, bool on);
 708 int wmi_get_temperature(struct wil6210_priv *wil, u32 *t_m, u32 *t_r);
 709 int wmi_disconnect_sta(struct wil6210_priv *wil, const u8 *mac, u16 reason);
 710 int wmi_addba(struct wil6210_priv *wil, u8 ringid, u8 size, u16 timeout);
 711 int wmi_delba_tx(struct wil6210_priv *wil, u8 ringid, u16 reason);
 712 int wmi_delba_rx(struct wil6210_priv *wil, u8 cidxtid, u16 reason);
 713 int wmi_addba_rx_resp(struct wil6210_priv *wil, u8 cid, u8 tid, u8 token,
 714                       u16 status, bool amsdu, u16 agg_wsize, u16 timeout);
 715 int wil_addba_rx_request(struct wil6210_priv *wil, u8 cidxtid,
 716                          u8 dialog_token, __le16 ba_param_set,
 717                          __le16 ba_timeout, __le16 ba_seq_ctrl);
 718 void wil_back_rx_worker(struct work_struct *work);
 719 void wil_back_rx_flush(struct wil6210_priv *wil);
 720 int wil_addba_tx_request(struct wil6210_priv *wil, u8 ringid, u16 wsize);
 721 void wil_back_tx_worker(struct work_struct *work);
 722 void wil_back_tx_flush(struct wil6210_priv *wil);
 723
 724 void wil6210_clear_irq(struct wil6210_priv *wil);
 725 int wil6210_init_irq(struct wil6210_priv *wil, int irq);
 726 void wil6210_fini_irq(struct wil6210_priv *wil, int irq);
 727 void wil_mask_irq(struct wil6210_priv *wil);
 728 void wil_unmask_irq(struct wil6210_priv *wil);
 729 void wil_configure_interrupt_moderation(struct wil6210_priv *wil);
 730 void wil_disable_irq(struct wil6210_priv *wil);
 731 void wil_enable_irq(struct wil6210_priv *wil);
 732 int wil_cfg80211_mgmt_tx(struct wiphy *wiphy, struct wireless_dev *wdev,
 733                          struct cfg80211_mgmt_tx_params *params,
 734                          u64 *cookie);
 735
 736 int wil6210_debugfs_init(struct wil6210_priv *wil);
 737 void wil6210_debugfs_remove(struct wil6210_priv *wil);
 738 int wil_cid_fill_sinfo(struct wil6210_priv *wil, int cid,
 739                        struct station_info *sinfo);
 740
 741 struct wireless_dev *wil_cfg80211_init(struct device *dev);
 742 void wil_wdev_free(struct wil6210_priv *wil);
 743
 744 int wmi_set_mac_address(struct wil6210_priv *wil, void *addr);
 745 int wmi_pcp_start(struct wil6210_priv *wil, int bi, u8 wmi_nettype, u8 chan);
 746 int wmi_pcp_stop(struct wil6210_priv *wil);
 747 void wil6210_disconnect(struct wil6210_priv *wil, const u8 *bssid,
 748                         u16 reason_code, bool from_event);
 749 void wil_probe_client_flush(struct wil6210_priv *wil);
 750 void wil_probe_client_worker(struct work_struct *work);
 751
 752 int wil_rx_init(struct wil6210_priv *wil, u16 size);
 753 void wil_rx_fini(struct wil6210_priv *wil);
 754
 755 /* TX API */
 756 int wil_vring_init_tx(struct wil6210_priv *wil, int id, int size,
 757                       int cid, int tid);
 758 void wil_vring_fini_tx(struct wil6210_priv *wil, int id);
 759
 760 netdev_tx_t wil_start_xmit(struct sk_buff *skb, struct net_device *ndev);
 761 int wil_tx_complete(struct wil6210_priv *wil, int ringid);
 762 void wil6210_unmask_irq_tx(struct wil6210_priv *wil);
 763
 764 /* RX API */
 765 void wil_rx_handle(struct wil6210_priv *wil, int *quota);
 766 void wil6210_unmask_irq_rx(struct wil6210_priv *wil);
 767
 768 int wil_iftype_nl2wmi(enum nl80211_iftype type);
 769
 770 int wil_ioctl(struct wil6210_priv *wil, void __user *data, int cmd);
 771 int wil_request_firmware(struct wil6210_priv *wil, const char *name);
 772
 773 #endif /* __WIL6210_H__ */