2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
43 #include <linux/version.h>
44 #include <linux/module.h>
45 #include <linux/delay.h>
47 #include <linux/netdevice.h>
48 #include <linux/cache.h>
49 #include <linux/pci.h>
50 #include <linux/ethtool.h>
51 #include <linux/uaccess.h>
53 #include <net/ieee80211_radiotap.h>
55 #include <asm/unaligned.h>
61 /* unaligned little endian access */
62 #define LE_READ_2(_p) (le16_to_cpu(get_unaligned((__le16 *)(_p))))
63 #define LE_READ_4(_p) (le32_to_cpu(get_unaligned((__le32 *)(_p))))
70 static int ath5k_calinterval
= 10; /* Calibrate PHY every 10 secs (TODO: Fixme) */
78 MODULE_AUTHOR("Jiri Slaby");
79 MODULE_AUTHOR("Nick Kossifidis");
80 MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
81 MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
82 MODULE_LICENSE("Dual BSD/GPL");
83 MODULE_VERSION("0.1.1 (EXPERIMENTAL)");
87 static struct pci_device_id ath5k_pci_id_table
[] __devinitdata
= {
88 { PCI_VDEVICE(ATHEROS
, 0x0207), .driver_data
= AR5K_AR5210
}, /* 5210 early */
89 { PCI_VDEVICE(ATHEROS
, 0x0007), .driver_data
= AR5K_AR5210
}, /* 5210 */
90 { PCI_VDEVICE(ATHEROS
, 0x0011), .driver_data
= AR5K_AR5211
}, /* 5311 - this is on AHB bus !*/
91 { PCI_VDEVICE(ATHEROS
, 0x0012), .driver_data
= AR5K_AR5211
}, /* 5211 */
92 { PCI_VDEVICE(ATHEROS
, 0x0013), .driver_data
= AR5K_AR5212
}, /* 5212 */
93 { PCI_VDEVICE(3COM_2
, 0x0013), .driver_data
= AR5K_AR5212
}, /* 3com 5212 */
94 { PCI_VDEVICE(3COM
, 0x0013), .driver_data
= AR5K_AR5212
}, /* 3com 3CRDAG675 5212 */
95 { PCI_VDEVICE(ATHEROS
, 0x1014), .driver_data
= AR5K_AR5212
}, /* IBM minipci 5212 */
96 { PCI_VDEVICE(ATHEROS
, 0x0014), .driver_data
= AR5K_AR5212
}, /* 5212 combatible */
97 { PCI_VDEVICE(ATHEROS
, 0x0015), .driver_data
= AR5K_AR5212
}, /* 5212 combatible */
98 { PCI_VDEVICE(ATHEROS
, 0x0016), .driver_data
= AR5K_AR5212
}, /* 5212 combatible */
99 { PCI_VDEVICE(ATHEROS
, 0x0017), .driver_data
= AR5K_AR5212
}, /* 5212 combatible */
100 { PCI_VDEVICE(ATHEROS
, 0x0018), .driver_data
= AR5K_AR5212
}, /* 5212 combatible */
101 { PCI_VDEVICE(ATHEROS
, 0x0019), .driver_data
= AR5K_AR5212
}, /* 5212 combatible */
102 { PCI_VDEVICE(ATHEROS
, 0x001a), .driver_data
= AR5K_AR5212
}, /* 2413 Griffin-lite */
103 { PCI_VDEVICE(ATHEROS
, 0x001b), .driver_data
= AR5K_AR5212
}, /* 5413 Eagle */
104 { PCI_VDEVICE(ATHEROS
, 0x001c), .driver_data
= AR5K_AR5212
}, /* 5424 Condor (PCI-E)*/
105 { PCI_VDEVICE(ATHEROS
, 0x0023), .driver_data
= AR5K_AR5212
}, /* 5416 */
106 { PCI_VDEVICE(ATHEROS
, 0x0024), .driver_data
= AR5K_AR5212
}, /* 5418 */
109 MODULE_DEVICE_TABLE(pci
, ath5k_pci_id_table
);
112 static struct ath5k_srev_name srev_names
[] = {
113 { "5210", AR5K_VERSION_VER
, AR5K_SREV_VER_AR5210
},
114 { "5311", AR5K_VERSION_VER
, AR5K_SREV_VER_AR5311
},
115 { "5311A", AR5K_VERSION_VER
, AR5K_SREV_VER_AR5311A
},
116 { "5311B", AR5K_VERSION_VER
, AR5K_SREV_VER_AR5311B
},
117 { "5211", AR5K_VERSION_VER
, AR5K_SREV_VER_AR5211
},
118 { "5212", AR5K_VERSION_VER
, AR5K_SREV_VER_AR5212
},
119 { "5213", AR5K_VERSION_VER
, AR5K_SREV_VER_AR5213
},
120 { "5213A", AR5K_VERSION_VER
, AR5K_SREV_VER_AR5213A
},
121 { "2424", AR5K_VERSION_VER
, AR5K_SREV_VER_AR2424
},
122 { "5424", AR5K_VERSION_VER
, AR5K_SREV_VER_AR5424
},
123 { "5413", AR5K_VERSION_VER
, AR5K_SREV_VER_AR5413
},
124 { "5414", AR5K_VERSION_VER
, AR5K_SREV_VER_AR5414
},
125 { "5416", AR5K_VERSION_VER
, AR5K_SREV_VER_AR5416
},
126 { "5418", AR5K_VERSION_VER
, AR5K_SREV_VER_AR5418
},
127 { "xxxxx", AR5K_VERSION_VER
, AR5K_SREV_UNKNOWN
},
128 { "5110", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5110
},
129 { "5111", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5111
},
130 { "2111", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2111
},
131 { "5112", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5112
},
132 { "5112A", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5112A
},
133 { "2112", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2112
},
134 { "2112A", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2112A
},
135 { "SChip", AR5K_VERSION_RAD
, AR5K_SREV_RAD_SC1
},
136 { "SChip", AR5K_VERSION_RAD
, AR5K_SREV_RAD_SC2
},
137 { "5133", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5133
},
138 { "xxxxx", AR5K_VERSION_RAD
, AR5K_SREV_UNKNOWN
},
142 * Prototypes - PCI stack related functions
144 static int __devinit
ath5k_pci_probe(struct pci_dev
*pdev
,
145 const struct pci_device_id
*id
);
146 static void __devexit
ath5k_pci_remove(struct pci_dev
*pdev
);
148 static int ath5k_pci_suspend(struct pci_dev
*pdev
,
150 static int ath5k_pci_resume(struct pci_dev
*pdev
);
152 #define ath5k_pci_suspend NULL
153 #define ath5k_pci_resume NULL
154 #endif /* CONFIG_PM */
156 static struct pci_driver ath5k_pci_drv_id
= {
158 .id_table
= ath5k_pci_id_table
,
159 .probe
= ath5k_pci_probe
,
160 .remove
= __devexit_p(ath5k_pci_remove
),
161 .suspend
= ath5k_pci_suspend
,
162 .resume
= ath5k_pci_resume
,
168 * Prototypes - MAC 802.11 stack related functions
170 static int ath5k_tx(struct ieee80211_hw
*hw
, struct sk_buff
*skb
,
171 struct ieee80211_tx_control
*ctl
);
172 static int ath5k_reset(struct ieee80211_hw
*hw
);
173 static int ath5k_start(struct ieee80211_hw
*hw
);
174 static void ath5k_stop(struct ieee80211_hw
*hw
);
175 static int ath5k_add_interface(struct ieee80211_hw
*hw
,
176 struct ieee80211_if_init_conf
*conf
);
177 static void ath5k_remove_interface(struct ieee80211_hw
*hw
,
178 struct ieee80211_if_init_conf
*conf
);
179 static int ath5k_config(struct ieee80211_hw
*hw
,
180 struct ieee80211_conf
*conf
);
181 static int ath5k_config_interface(struct ieee80211_hw
*hw
,
182 struct ieee80211_vif
*vif
,
183 struct ieee80211_if_conf
*conf
);
184 static void ath5k_configure_filter(struct ieee80211_hw
*hw
,
185 unsigned int changed_flags
,
186 unsigned int *new_flags
,
187 int mc_count
, struct dev_mc_list
*mclist
);
188 static int ath5k_set_key(struct ieee80211_hw
*hw
,
189 enum set_key_cmd cmd
,
190 const u8
*local_addr
, const u8
*addr
,
191 struct ieee80211_key_conf
*key
);
192 static int ath5k_get_stats(struct ieee80211_hw
*hw
,
193 struct ieee80211_low_level_stats
*stats
);
194 static int ath5k_get_tx_stats(struct ieee80211_hw
*hw
,
195 struct ieee80211_tx_queue_stats
*stats
);
196 static u64
ath5k_get_tsf(struct ieee80211_hw
*hw
);
197 static void ath5k_reset_tsf(struct ieee80211_hw
*hw
);
198 static int ath5k_beacon_update(struct ieee80211_hw
*hw
,
200 struct ieee80211_tx_control
*ctl
);
202 static struct ieee80211_ops ath5k_hw_ops
= {
204 .start
= ath5k_start
,
206 .add_interface
= ath5k_add_interface
,
207 .remove_interface
= ath5k_remove_interface
,
208 .config
= ath5k_config
,
209 .config_interface
= ath5k_config_interface
,
210 .configure_filter
= ath5k_configure_filter
,
211 .set_key
= ath5k_set_key
,
212 .get_stats
= ath5k_get_stats
,
214 .get_tx_stats
= ath5k_get_tx_stats
,
215 .get_tsf
= ath5k_get_tsf
,
216 .reset_tsf
= ath5k_reset_tsf
,
217 .beacon_update
= ath5k_beacon_update
,
221 * Prototypes - Internal functions
224 static int ath5k_attach(struct pci_dev
*pdev
,
225 struct ieee80211_hw
*hw
);
226 static void ath5k_detach(struct pci_dev
*pdev
,
227 struct ieee80211_hw
*hw
);
228 /* Channel/mode setup */
229 static inline short ath5k_ieee2mhz(short chan
);
230 static unsigned int ath5k_copy_rates(struct ieee80211_rate
*rates
,
231 const struct ath5k_rate_table
*rt
,
233 static unsigned int ath5k_copy_channels(struct ath5k_hw
*ah
,
234 struct ieee80211_channel
*channels
,
237 static int ath5k_getchannels(struct ieee80211_hw
*hw
);
238 static int ath5k_chan_set(struct ath5k_softc
*sc
,
239 struct ieee80211_channel
*chan
);
240 static void ath5k_setcurmode(struct ath5k_softc
*sc
,
242 static void ath5k_mode_setup(struct ath5k_softc
*sc
);
243 /* Descriptor setup */
244 static int ath5k_desc_alloc(struct ath5k_softc
*sc
,
245 struct pci_dev
*pdev
);
246 static void ath5k_desc_free(struct ath5k_softc
*sc
,
247 struct pci_dev
*pdev
);
249 static int ath5k_rxbuf_setup(struct ath5k_softc
*sc
,
250 struct ath5k_buf
*bf
);
251 static int ath5k_txbuf_setup(struct ath5k_softc
*sc
,
252 struct ath5k_buf
*bf
,
253 struct ieee80211_tx_control
*ctl
);
255 static inline void ath5k_txbuf_free(struct ath5k_softc
*sc
,
256 struct ath5k_buf
*bf
)
261 pci_unmap_single(sc
->pdev
, bf
->skbaddr
, bf
->skb
->len
,
263 dev_kfree_skb(bf
->skb
);
268 static struct ath5k_txq
*ath5k_txq_setup(struct ath5k_softc
*sc
,
269 int qtype
, int subtype
);
270 static int ath5k_beaconq_setup(struct ath5k_hw
*ah
);
271 static int ath5k_beaconq_config(struct ath5k_softc
*sc
);
272 static void ath5k_txq_drainq(struct ath5k_softc
*sc
,
273 struct ath5k_txq
*txq
);
274 static void ath5k_txq_cleanup(struct ath5k_softc
*sc
);
275 static void ath5k_txq_release(struct ath5k_softc
*sc
);
277 static int ath5k_rx_start(struct ath5k_softc
*sc
);
278 static void ath5k_rx_stop(struct ath5k_softc
*sc
);
279 static unsigned int ath5k_rx_decrypted(struct ath5k_softc
*sc
,
280 struct ath5k_desc
*ds
,
281 struct sk_buff
*skb
);
282 static void ath5k_tasklet_rx(unsigned long data
);
284 static void ath5k_tx_processq(struct ath5k_softc
*sc
,
285 struct ath5k_txq
*txq
);
286 static void ath5k_tasklet_tx(unsigned long data
);
287 /* Beacon handling */
288 static int ath5k_beacon_setup(struct ath5k_softc
*sc
,
289 struct ath5k_buf
*bf
,
290 struct ieee80211_tx_control
*ctl
);
291 static void ath5k_beacon_send(struct ath5k_softc
*sc
);
292 static void ath5k_beacon_config(struct ath5k_softc
*sc
);
294 static inline u64
ath5k_extend_tsf(struct ath5k_hw
*ah
, u32 rstamp
)
296 u64 tsf
= ath5k_hw_get_tsf64(ah
);
298 if ((tsf
& 0x7fff) < rstamp
)
301 return (tsf
& ~0x7fff) | rstamp
;
304 /* Interrupt handling */
305 static int ath5k_init(struct ath5k_softc
*sc
);
306 static int ath5k_stop_locked(struct ath5k_softc
*sc
);
307 static int ath5k_stop_hw(struct ath5k_softc
*sc
);
308 static irqreturn_t
ath5k_intr(int irq
, void *dev_id
);
309 static void ath5k_tasklet_reset(unsigned long data
);
311 static void ath5k_calibrate(unsigned long data
);
313 static void ath5k_led_off(unsigned long data
);
314 static void ath5k_led_blink(struct ath5k_softc
*sc
,
317 static void ath5k_led_event(struct ath5k_softc
*sc
,
322 * Module init/exit functions
331 ret
= pci_register_driver(&ath5k_pci_drv_id
);
333 printk(KERN_ERR
"ath5k_pci: can't register pci driver\n");
343 pci_unregister_driver(&ath5k_pci_drv_id
);
345 ath5k_debug_finish();
348 module_init(init_ath5k_pci
);
349 module_exit(exit_ath5k_pci
);
352 /********************\
353 * PCI Initialization *
354 \********************/
357 ath5k_chip_name(enum ath5k_srev_type type
, u_int16_t val
)
359 const char *name
= "xxxxx";
362 for (i
= 0; i
< ARRAY_SIZE(srev_names
); i
++) {
363 if (srev_names
[i
].sr_type
!= type
)
365 if ((val
& 0xff) < srev_names
[i
+ 1].sr_val
) {
366 name
= srev_names
[i
].sr_name
;
375 ath5k_pci_probe(struct pci_dev
*pdev
,
376 const struct pci_device_id
*id
)
379 struct ath5k_softc
*sc
;
380 struct ieee80211_hw
*hw
;
384 ret
= pci_enable_device(pdev
);
386 dev_err(&pdev
->dev
, "can't enable device\n");
390 /* XXX 32-bit addressing only */
391 ret
= pci_set_dma_mask(pdev
, DMA_32BIT_MASK
);
393 dev_err(&pdev
->dev
, "32-bit DMA not available\n");
398 * Cache line size is used to size and align various
399 * structures used to communicate with the hardware.
401 pci_read_config_byte(pdev
, PCI_CACHE_LINE_SIZE
, &csz
);
404 * Linux 2.4.18 (at least) writes the cache line size
405 * register as a 16-bit wide register which is wrong.
406 * We must have this setup properly for rx buffer
407 * DMA to work so force a reasonable value here if it
410 csz
= L1_CACHE_BYTES
/ sizeof(u32
);
411 pci_write_config_byte(pdev
, PCI_CACHE_LINE_SIZE
, csz
);
414 * The default setting of latency timer yields poor results,
415 * set it to the value used by other systems. It may be worth
416 * tweaking this setting more.
418 pci_write_config_byte(pdev
, PCI_LATENCY_TIMER
, 0xa8);
420 /* Enable bus mastering */
421 pci_set_master(pdev
);
424 * Disable the RETRY_TIMEOUT register (0x41) to keep
425 * PCI Tx retries from interfering with C3 CPU state.
427 pci_write_config_byte(pdev
, 0x41, 0);
429 ret
= pci_request_region(pdev
, 0, "ath5k");
431 dev_err(&pdev
->dev
, "cannot reserve PCI memory region\n");
435 mem
= pci_iomap(pdev
, 0, 0);
437 dev_err(&pdev
->dev
, "cannot remap PCI memory region\n") ;
443 * Allocate hw (mac80211 main struct)
444 * and hw->priv (driver private data)
446 hw
= ieee80211_alloc_hw(sizeof(*sc
), &ath5k_hw_ops
);
448 dev_err(&pdev
->dev
, "cannot allocate ieee80211_hw\n");
453 dev_info(&pdev
->dev
, "registered as '%s'\n", wiphy_name(hw
->wiphy
));
455 /* Initialize driver private data */
456 SET_IEEE80211_DEV(hw
, &pdev
->dev
);
457 hw
->flags
= IEEE80211_HW_RX_INCLUDES_FCS
;
458 hw
->extra_tx_headroom
= 2;
459 hw
->channel_change_time
= 5000;
460 /* these names are misleading */
461 hw
->max_rssi
= -110; /* signal in dBm */
462 hw
->max_noise
= -110; /* noise in dBm */
463 hw
->max_signal
= 100; /* we will provide a percentage based on rssi */
468 ath5k_debug_init_device(sc
);
471 * Mark the device as detached to avoid processing
472 * interrupts until setup is complete.
474 __set_bit(ATH_STAT_INVALID
, sc
->status
);
476 sc
->iobase
= mem
; /* So we can unmap it on detach */
477 sc
->cachelsz
= csz
* sizeof(u32
); /* convert to bytes */
478 sc
->opmode
= IEEE80211_IF_TYPE_STA
;
479 mutex_init(&sc
->lock
);
480 spin_lock_init(&sc
->rxbuflock
);
481 spin_lock_init(&sc
->txbuflock
);
483 /* Set private data */
484 pci_set_drvdata(pdev
, hw
);
486 /* Enable msi for devices that support it */
487 pci_enable_msi(pdev
);
489 /* Setup interrupt handler */
490 ret
= request_irq(pdev
->irq
, ath5k_intr
, IRQF_SHARED
, "ath", sc
);
492 ATH5K_ERR(sc
, "request_irq failed\n");
496 /* Initialize device */
497 sc
->ah
= ath5k_hw_attach(sc
, id
->driver_data
);
498 if (IS_ERR(sc
->ah
)) {
499 ret
= PTR_ERR(sc
->ah
);
503 /* Finish private driver data initialization */
504 ret
= ath5k_attach(pdev
, hw
);
508 ATH5K_INFO(sc
, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
509 ath5k_chip_name(AR5K_VERSION_VER
,sc
->ah
->ah_mac_srev
),
511 sc
->ah
->ah_phy_revision
);
513 if(!sc
->ah
->ah_single_chip
){
514 /* Single chip radio (!RF5111) */
515 if(sc
->ah
->ah_radio_5ghz_revision
&& !sc
->ah
->ah_radio_2ghz_revision
) {
516 /* No 5GHz support -> report 2GHz radio */
517 if(!test_bit(MODE_IEEE80211A
, sc
->ah
->ah_capabilities
.cap_mode
)){
518 ATH5K_INFO(sc
, "RF%s 2GHz radio found (0x%x)\n",
519 ath5k_chip_name(AR5K_VERSION_RAD
,sc
->ah
->ah_radio_5ghz_revision
),
520 sc
->ah
->ah_radio_5ghz_revision
);
521 /* No 2GHz support (5110 and some 5Ghz only cards) -> report 5Ghz radio */
522 } else if(!test_bit(MODE_IEEE80211B
, sc
->ah
->ah_capabilities
.cap_mode
)){
523 ATH5K_INFO(sc
, "RF%s 5GHz radio found (0x%x)\n",
524 ath5k_chip_name(AR5K_VERSION_RAD
,sc
->ah
->ah_radio_5ghz_revision
),
525 sc
->ah
->ah_radio_5ghz_revision
);
526 /* Multiband radio */
528 ATH5K_INFO(sc
, "RF%s multiband radio found"
530 ath5k_chip_name(AR5K_VERSION_RAD
,sc
->ah
->ah_radio_5ghz_revision
),
531 sc
->ah
->ah_radio_5ghz_revision
);
534 /* Multi chip radio (RF5111 - RF2111) -> report both 2GHz/5GHz radios */
535 else if(sc
->ah
->ah_radio_5ghz_revision
&& sc
->ah
->ah_radio_2ghz_revision
){
536 ATH5K_INFO(sc
, "RF%s 5GHz radio found (0x%x)\n",
537 ath5k_chip_name(AR5K_VERSION_RAD
,sc
->ah
->ah_radio_5ghz_revision
),
538 sc
->ah
->ah_radio_5ghz_revision
);
539 ATH5K_INFO(sc
, "RF%s 2GHz radio found (0x%x)\n",
540 ath5k_chip_name(AR5K_VERSION_RAD
,sc
->ah
->ah_radio_2ghz_revision
),
541 sc
->ah
->ah_radio_2ghz_revision
);
546 /* ready to process interrupts */
547 __clear_bit(ATH_STAT_INVALID
, sc
->status
);
551 ath5k_hw_detach(sc
->ah
);
553 free_irq(pdev
->irq
, sc
);
555 pci_disable_msi(pdev
);
556 ieee80211_free_hw(hw
);
558 pci_iounmap(pdev
, mem
);
560 pci_release_region(pdev
, 0);
562 pci_disable_device(pdev
);
567 static void __devexit
568 ath5k_pci_remove(struct pci_dev
*pdev
)
570 struct ieee80211_hw
*hw
= pci_get_drvdata(pdev
);
571 struct ath5k_softc
*sc
= hw
->priv
;
573 ath5k_debug_finish_device(sc
);
574 ath5k_detach(pdev
, hw
);
575 ath5k_hw_detach(sc
->ah
);
576 free_irq(pdev
->irq
, sc
);
577 pci_disable_msi(pdev
);
578 pci_iounmap(pdev
, sc
->iobase
);
579 pci_release_region(pdev
, 0);
580 pci_disable_device(pdev
);
581 ieee80211_free_hw(hw
);
586 ath5k_pci_suspend(struct pci_dev
*pdev
, pm_message_t state
)
588 struct ieee80211_hw
*hw
= pci_get_drvdata(pdev
);
589 struct ath5k_softc
*sc
= hw
->priv
;
591 if (test_bit(ATH_STAT_LEDSOFT
, sc
->status
))
592 ath5k_hw_set_gpio(sc
->ah
, sc
->led_pin
, 1);
595 pci_save_state(pdev
);
596 pci_disable_device(pdev
);
597 pci_set_power_state(pdev
, PCI_D3hot
);
603 ath5k_pci_resume(struct pci_dev
*pdev
)
605 struct ieee80211_hw
*hw
= pci_get_drvdata(pdev
);
606 struct ath5k_softc
*sc
= hw
->priv
;
609 err
= pci_set_power_state(pdev
, PCI_D0
);
613 err
= pci_enable_device(pdev
);
617 pci_restore_state(pdev
);
619 * Suspend/Resume resets the PCI configuration space, so we have to
620 * re-disable the RETRY_TIMEOUT register (0x41) to keep
621 * PCI Tx retries from interfering with C3 CPU state
623 pci_write_config_byte(pdev
, 0x41, 0);
626 if (test_bit(ATH_STAT_LEDSOFT
, sc
->status
)) {
627 ath5k_hw_set_gpio_output(sc
->ah
, sc
->led_pin
);
628 ath5k_hw_set_gpio(sc
->ah
, sc
->led_pin
, 0);
633 #endif /* CONFIG_PM */
637 /***********************\
638 * Driver Initialization *
639 \***********************/
642 ath5k_attach(struct pci_dev
*pdev
, struct ieee80211_hw
*hw
)
644 struct ath5k_softc
*sc
= hw
->priv
;
645 struct ath5k_hw
*ah
= sc
->ah
;
650 ATH5K_DBG(sc
, ATH5K_DEBUG_ANY
, "devid 0x%x\n", pdev
->device
);
653 * Check if the MAC has multi-rate retry support.
654 * We do this by trying to setup a fake extended
655 * descriptor. MAC's that don't have support will
656 * return false w/o doing anything. MAC's that do
657 * support it will return true w/o doing anything.
659 if (ah
->ah_setup_xtx_desc(ah
, NULL
, 0, 0, 0, 0, 0, 0))
660 __set_bit(ATH_STAT_MRRETRY
, sc
->status
);
663 * Reset the key cache since some parts do not
664 * reset the contents on initial power up.
666 for (i
= 0; i
< AR5K_KEYCACHE_SIZE
; i
++)
667 ath5k_hw_reset_key(ah
, i
);
670 * Collect the channel list. The 802.11 layer
671 * is resposible for filtering this list based
672 * on settings like the phy mode and regulatory
673 * domain restrictions.
675 ret
= ath5k_getchannels(hw
);
677 ATH5K_ERR(sc
, "can't get channels\n");
681 /* NB: setup here so ath5k_rate_update is happy */
682 if (test_bit(MODE_IEEE80211A
, ah
->ah_modes
))
683 ath5k_setcurmode(sc
, MODE_IEEE80211A
);
685 ath5k_setcurmode(sc
, MODE_IEEE80211B
);
688 * Allocate tx+rx descriptors and populate the lists.
690 ret
= ath5k_desc_alloc(sc
, pdev
);
692 ATH5K_ERR(sc
, "can't allocate descriptors\n");
697 * Allocate hardware transmit queues: one queue for
698 * beacon frames and one data queue for each QoS
699 * priority. Note that hw functions handle reseting
700 * these queues at the needed time.
702 ret
= ath5k_beaconq_setup(ah
);
704 ATH5K_ERR(sc
, "can't setup a beacon xmit queue\n");
709 sc
->txq
= ath5k_txq_setup(sc
, AR5K_TX_QUEUE_DATA
, AR5K_WME_AC_BK
);
710 if (IS_ERR(sc
->txq
)) {
711 ATH5K_ERR(sc
, "can't setup xmit queue\n");
712 ret
= PTR_ERR(sc
->txq
);
716 tasklet_init(&sc
->rxtq
, ath5k_tasklet_rx
, (unsigned long)sc
);
717 tasklet_init(&sc
->txtq
, ath5k_tasklet_tx
, (unsigned long)sc
);
718 tasklet_init(&sc
->restq
, ath5k_tasklet_reset
, (unsigned long)sc
);
719 setup_timer(&sc
->calib_tim
, ath5k_calibrate
, (unsigned long)sc
);
720 setup_timer(&sc
->led_tim
, ath5k_led_off
, (unsigned long)sc
);
722 sc
->led_on
= 0; /* low true */
724 * Auto-enable soft led processing for IBM cards and for
725 * 5211 minipci cards.
727 if (pdev
->device
== PCI_DEVICE_ID_ATHEROS_AR5212_IBM
||
728 pdev
->device
== PCI_DEVICE_ID_ATHEROS_AR5211
) {
729 __set_bit(ATH_STAT_LEDSOFT
, sc
->status
);
732 /* Enable softled on PIN1 on HP Compaq nc6xx, nc4000 & nx5000 laptops */
733 if (pdev
->subsystem_vendor
== PCI_VENDOR_ID_COMPAQ
) {
734 __set_bit(ATH_STAT_LEDSOFT
, sc
->status
);
737 if (test_bit(ATH_STAT_LEDSOFT
, sc
->status
)) {
738 ath5k_hw_set_gpio_output(ah
, sc
->led_pin
);
739 ath5k_hw_set_gpio(ah
, sc
->led_pin
, !sc
->led_on
);
742 ath5k_hw_get_lladdr(ah
, mac
);
743 SET_IEEE80211_PERM_ADDR(hw
, mac
);
744 /* All MAC address bits matter for ACKs */
745 memset(sc
->bssidmask
, 0xff, ETH_ALEN
);
746 ath5k_hw_set_bssid_mask(sc
->ah
, sc
->bssidmask
);
748 ret
= ieee80211_register_hw(hw
);
750 ATH5K_ERR(sc
, "can't register ieee80211 hw\n");
756 ath5k_txq_release(sc
);
758 ath5k_hw_release_tx_queue(ah
, sc
->bhalq
);
760 ath5k_desc_free(sc
, pdev
);
766 ath5k_detach(struct pci_dev
*pdev
, struct ieee80211_hw
*hw
)
768 struct ath5k_softc
*sc
= hw
->priv
;
771 * NB: the order of these is important:
772 * o call the 802.11 layer before detaching ath5k_hw to
773 * insure callbacks into the driver to delete global
774 * key cache entries can be handled
775 * o reclaim the tx queue data structures after calling
776 * the 802.11 layer as we'll get called back to reclaim
777 * node state and potentially want to use them
778 * o to cleanup the tx queues the hal is called, so detach
780 * XXX: ??? detach ath5k_hw ???
781 * Other than that, it's straightforward...
783 ieee80211_unregister_hw(hw
);
784 ath5k_desc_free(sc
, pdev
);
785 ath5k_txq_release(sc
);
786 ath5k_hw_release_tx_queue(sc
->ah
, sc
->bhalq
);
789 * NB: can't reclaim these until after ieee80211_ifdetach
790 * returns because we'll get called back to reclaim node
791 * state and potentially want to use them.
798 /********************\
799 * Channel/mode setup *
800 \********************/
803 * Convert IEEE channel number to MHz frequency.
806 ath5k_ieee2mhz(short chan
)
808 if (chan
<= 14 || chan
>= 27)
809 return ieee80211chan2mhz(chan
);
811 return 2212 + chan
* 20;
815 ath5k_copy_rates(struct ieee80211_rate
*rates
,
816 const struct ath5k_rate_table
*rt
,
819 unsigned int i
, count
;
824 for (i
= 0, count
= 0; i
< rt
->rate_count
&& max
> 0; i
++) {
825 if (!rt
->rates
[i
].valid
)
827 rates
->rate
= rt
->rates
[i
].rate_kbps
/ 100;
828 rates
->val
= rt
->rates
[i
].rate_code
;
829 rates
->flags
= rt
->rates
[i
].modulation
;
839 ath5k_copy_channels(struct ath5k_hw
*ah
,
840 struct ieee80211_channel
*channels
,
844 static const struct { unsigned int mode
, mask
, chan
; } map
[] = {
845 [MODE_IEEE80211A
] = { CHANNEL_OFDM
, CHANNEL_OFDM
| CHANNEL_TURBO
, CHANNEL_A
},
846 [MODE_ATHEROS_TURBO
] = { CHANNEL_OFDM
|CHANNEL_TURBO
, CHANNEL_OFDM
| CHANNEL_TURBO
, CHANNEL_T
},
847 [MODE_IEEE80211B
] = { CHANNEL_CCK
, CHANNEL_CCK
, CHANNEL_B
},
848 [MODE_IEEE80211G
] = { CHANNEL_OFDM
, CHANNEL_OFDM
, CHANNEL_G
},
849 [MODE_ATHEROS_TURBOG
] = { CHANNEL_OFDM
| CHANNEL_TURBO
, CHANNEL_OFDM
| CHANNEL_TURBO
, CHANNEL_TG
},
851 static const struct ath5k_regchannel chans_2ghz
[] =
852 IEEE80211_CHANNELS_2GHZ
;
853 static const struct ath5k_regchannel chans_5ghz
[] =
854 IEEE80211_CHANNELS_5GHZ
;
855 const struct ath5k_regchannel
*chans
;
856 enum ath5k_regdom dmn
;
857 unsigned int i
, count
, size
, chfreq
, all
, f
, ch
;
859 if (!test_bit(mode
, ah
->ah_modes
))
862 all
= ah
->ah_regdomain
== DMN_DEFAULT
|| CHAN_DEBUG
== 1;
865 case MODE_IEEE80211A
:
866 case MODE_ATHEROS_TURBO
:
867 /* 1..220, but 2GHz frequencies are filtered by check_channel */
868 size
= all
? 220 : ARRAY_SIZE(chans_5ghz
);
870 dmn
= ath5k_regdom2flag(ah
->ah_regdomain
,
871 IEEE80211_CHANNELS_5GHZ_MIN
);
872 chfreq
= CHANNEL_5GHZ
;
874 case MODE_IEEE80211B
:
875 case MODE_IEEE80211G
:
876 case MODE_ATHEROS_TURBOG
:
877 size
= all
? 26 : ARRAY_SIZE(chans_2ghz
);
879 dmn
= ath5k_regdom2flag(ah
->ah_regdomain
,
880 IEEE80211_CHANNELS_2GHZ_MIN
);
881 chfreq
= CHANNEL_2GHZ
;
884 ATH5K_WARN(ah
->ah_sc
, "bad mode, not copying channels\n");
888 for (i
= 0, count
= 0; i
< size
&& max
> 0; i
++) {
889 ch
= all
? i
+ 1 : chans
[i
].chan
;
890 f
= ath5k_ieee2mhz(ch
);
891 /* Check if channel is supported by the chipset */
892 if (!ath5k_channel_ok(ah
, f
, chfreq
))
895 /* Match regulation domain */
896 if (!all
&& !(IEEE80211_DMN(chans
[i
].domain
) &
900 if (!all
&& (chans
[i
].mode
& map
[mode
].mask
) != map
[mode
].mode
)
903 /* Write channel and increment counter */
906 channels
->val
= map
[mode
].chan
;
915 /* Only tries to register modes our EEPROM says it can support */
916 #define REGISTER_MODE(m) do { \
917 ret = ath5k_register_mode(hw, m); \
923 ath5k_register_mode(struct ieee80211_hw
*hw
, u8 m
)
925 struct ath5k_softc
*sc
= hw
->priv
;
926 struct ieee80211_hw_mode
*modes
= sc
->modes
;
930 if (!test_bit(m
, sc
->ah
->ah_capabilities
.cap_mode
))
933 for (i
= 0; i
< NUM_DRIVER_MODES
; i
++) {
934 if (modes
[i
].mode
!= m
|| !modes
[i
].num_channels
)
936 ret
= ieee80211_register_hwmode(hw
, &modes
[i
]);
938 ATH5K_ERR(sc
, "can't register hwmode %u\n", m
);
947 ath5k_getchannels(struct ieee80211_hw
*hw
)
949 struct ath5k_softc
*sc
= hw
->priv
;
950 struct ath5k_hw
*ah
= sc
->ah
;
951 struct ieee80211_hw_mode
*modes
= sc
->modes
;
952 unsigned int i
, max_r
, max_c
;
955 BUILD_BUG_ON(ARRAY_SIZE(sc
->modes
) < 3);
957 /* The order here does not matter */
958 modes
[0].mode
= MODE_IEEE80211G
;
959 modes
[1].mode
= MODE_IEEE80211B
;
960 modes
[2].mode
= MODE_IEEE80211A
;
962 max_r
= ARRAY_SIZE(sc
->rates
);
963 max_c
= ARRAY_SIZE(sc
->channels
);
965 for (i
= 0; i
< NUM_DRIVER_MODES
; i
++) {
966 struct ieee80211_hw_mode
*mode
= &modes
[i
];
967 const struct ath5k_rate_table
*hw_rates
;
970 modes
[0].rates
= sc
->rates
;
971 modes
->channels
= sc
->channels
;
973 struct ieee80211_hw_mode
*prev_mode
= &modes
[i
-1];
974 int prev_num_r
= prev_mode
->num_rates
;
975 int prev_num_c
= prev_mode
->num_channels
;
976 mode
->rates
= &prev_mode
->rates
[prev_num_r
];
977 mode
->channels
= &prev_mode
->channels
[prev_num_c
];
980 hw_rates
= ath5k_hw_get_rate_table(ah
, mode
->mode
);
981 mode
->num_rates
= ath5k_copy_rates(mode
->rates
, hw_rates
,
983 mode
->num_channels
= ath5k_copy_channels(ah
, mode
->channels
,
985 max_r
-= mode
->num_rates
;
986 max_c
-= mode
->num_channels
;
989 /* We try to register all modes this driver supports. We don't bother
990 * with MODE_IEEE80211B for AR5212 as MODE_IEEE80211G already accounts
991 * for that as per mac80211. Then, REGISTER_MODE() will will actually
992 * check the eeprom reading for more reliable capability information.
993 * Order matters here as per mac80211's latest preference. This will
994 * all hopefullly soon go away. */
996 REGISTER_MODE(MODE_IEEE80211G
);
997 if (ah
->ah_version
!= AR5K_AR5212
)
998 REGISTER_MODE(MODE_IEEE80211B
);
999 REGISTER_MODE(MODE_IEEE80211A
);
1001 ath5k_debug_dump_modes(sc
, modes
);
1007 * Set/change channels. If the channel is really being changed,
1008 * it's done by reseting the chip. To accomplish this we must
1009 * first cleanup any pending DMA, then restart stuff after a la
1013 ath5k_chan_set(struct ath5k_softc
*sc
, struct ieee80211_channel
*chan
)
1015 struct ath5k_hw
*ah
= sc
->ah
;
1018 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "%u (%u MHz) -> %u (%u MHz)\n",
1019 sc
->curchan
->chan
, sc
->curchan
->freq
,
1020 chan
->chan
, chan
->freq
);
1022 if (chan
->freq
!= sc
->curchan
->freq
|| chan
->val
!= sc
->curchan
->val
) {
1024 * To switch channels clear any pending DMA operations;
1025 * wait long enough for the RX fifo to drain, reset the
1026 * hardware at the new frequency, and then re-enable
1027 * the relevant bits of the h/w.
1029 ath5k_hw_set_intr(ah
, 0); /* disable interrupts */
1030 ath5k_txq_cleanup(sc
); /* clear pending tx frames */
1031 ath5k_rx_stop(sc
); /* turn off frame recv */
1032 ret
= ath5k_hw_reset(ah
, sc
->opmode
, chan
, true);
1034 ATH5K_ERR(sc
, "%s: unable to reset channel %u "
1035 "(%u Mhz)\n", __func__
, chan
->chan
, chan
->freq
);
1039 ath5k_hw_set_txpower_limit(sc
->ah
, 0);
1042 * Re-enable rx framework.
1044 ret
= ath5k_rx_start(sc
);
1046 ATH5K_ERR(sc
, "%s: unable to restart recv logic\n",
1052 * Change channels and update the h/w rate map
1053 * if we're switching; e.g. 11a to 11b/g.
1057 /* ath5k_chan_change(sc, chan); */
1059 ath5k_beacon_config(sc
);
1061 * Re-enable interrupts.
1063 ath5k_hw_set_intr(ah
, sc
->imask
);
1070 ath5k_setcurmode(struct ath5k_softc
*sc
, unsigned int mode
)
1072 if (unlikely(test_bit(ATH_STAT_LEDSOFT
, sc
->status
))) {
1073 /* from Atheros NDIS driver, w/ permission */
1074 static const struct {
1075 u16 rate
; /* tx/rx 802.11 rate */
1076 u16 timeOn
; /* LED on time (ms) */
1077 u16 timeOff
; /* LED off time (ms) */
1094 const struct ath5k_rate_table
*rt
=
1095 ath5k_hw_get_rate_table(sc
->ah
, mode
);
1100 memset(sc
->hwmap
, 0, sizeof(sc
->hwmap
));
1101 for (i
= 0; i
< 32; i
++) {
1102 u8 ix
= rt
->rate_code_to_index
[i
];
1104 sc
->hwmap
[i
].ledon
= msecs_to_jiffies(500);
1105 sc
->hwmap
[i
].ledoff
= msecs_to_jiffies(130);
1108 sc
->hwmap
[i
].txflags
= IEEE80211_RADIOTAP_F_DATAPAD
;
1109 if (SHPREAMBLE_FLAG(ix
) || rt
->rates
[ix
].modulation
==
1110 IEEE80211_RATE_OFDM
)
1111 sc
->hwmap
[i
].txflags
|=
1112 IEEE80211_RADIOTAP_F_SHORTPRE
;
1113 /* receive frames include FCS */
1114 sc
->hwmap
[i
].rxflags
= sc
->hwmap
[i
].txflags
|
1115 IEEE80211_RADIOTAP_F_FCS
;
1116 /* setup blink rate table to avoid per-packet lookup */
1117 for (j
= 0; j
< ARRAY_SIZE(blinkrates
) - 1; j
++)
1118 if (blinkrates
[j
].rate
== /* XXX why 7f? */
1119 (rt
->rates
[ix
].dot11_rate
&0x7f))
1122 sc
->hwmap
[i
].ledon
= msecs_to_jiffies(blinkrates
[j
].
1124 sc
->hwmap
[i
].ledoff
= msecs_to_jiffies(blinkrates
[j
].
1133 ath5k_mode_setup(struct ath5k_softc
*sc
)
1135 struct ath5k_hw
*ah
= sc
->ah
;
1138 /* configure rx filter */
1139 rfilt
= sc
->filter_flags
;
1140 ath5k_hw_set_rx_filter(ah
, rfilt
);
1142 if (ath5k_hw_hasbssidmask(ah
))
1143 ath5k_hw_set_bssid_mask(ah
, sc
->bssidmask
);
1145 /* configure operational mode */
1146 ath5k_hw_set_opmode(ah
);
1148 ath5k_hw_set_mcast_filter(ah
, 0, 0);
1149 ATH5K_DBG(sc
, ATH5K_DEBUG_MODE
, "RX filter 0x%x\n", rfilt
);
1160 ath5k_rxbuf_setup(struct ath5k_softc
*sc
, struct ath5k_buf
*bf
)
1162 struct ath5k_hw
*ah
= sc
->ah
;
1163 struct sk_buff
*skb
= bf
->skb
;
1164 struct ath5k_desc
*ds
;
1166 if (likely(skb
== NULL
)) {
1170 * Allocate buffer with headroom_needed space for the
1171 * fake physical layer header at the start.
1173 skb
= dev_alloc_skb(sc
->rxbufsize
+ sc
->cachelsz
- 1);
1174 if (unlikely(skb
== NULL
)) {
1175 ATH5K_ERR(sc
, "can't alloc skbuff of size %u\n",
1176 sc
->rxbufsize
+ sc
->cachelsz
- 1);
1180 * Cache-line-align. This is important (for the
1181 * 5210 at least) as not doing so causes bogus data
1184 off
= ((unsigned long)skb
->data
) % sc
->cachelsz
;
1186 skb_reserve(skb
, sc
->cachelsz
- off
);
1189 bf
->skbaddr
= pci_map_single(sc
->pdev
,
1190 skb
->data
, sc
->rxbufsize
, PCI_DMA_FROMDEVICE
);
1191 if (unlikely(pci_dma_mapping_error(bf
->skbaddr
))) {
1192 ATH5K_ERR(sc
, "%s: DMA mapping failed\n", __func__
);
1200 * Setup descriptors. For receive we always terminate
1201 * the descriptor list with a self-linked entry so we'll
1202 * not get overrun under high load (as can happen with a
1203 * 5212 when ANI processing enables PHY error frames).
1205 * To insure the last descriptor is self-linked we create
1206 * each descriptor as self-linked and add it to the end. As
1207 * each additional descriptor is added the previous self-linked
1208 * entry is ``fixed'' naturally. This should be safe even
1209 * if DMA is happening. When processing RX interrupts we
1210 * never remove/process the last, self-linked, entry on the
1211 * descriptor list. This insures the hardware always has
1212 * someplace to write a new frame.
1215 ds
->ds_link
= bf
->daddr
; /* link to self */
1216 ds
->ds_data
= bf
->skbaddr
;
1217 ath5k_hw_setup_rx_desc(ah
, ds
,
1218 skb_tailroom(skb
), /* buffer size */
1221 if (sc
->rxlink
!= NULL
)
1222 *sc
->rxlink
= bf
->daddr
;
1223 sc
->rxlink
= &ds
->ds_link
;
1228 ath5k_txbuf_setup(struct ath5k_softc
*sc
, struct ath5k_buf
*bf
,
1229 struct ieee80211_tx_control
*ctl
)
1231 struct ath5k_hw
*ah
= sc
->ah
;
1232 struct ath5k_txq
*txq
= sc
->txq
;
1233 struct ath5k_desc
*ds
= bf
->desc
;
1234 struct sk_buff
*skb
= bf
->skb
;
1235 unsigned int pktlen
, flags
, keyidx
= AR5K_TXKEYIX_INVALID
;
1238 flags
= AR5K_TXDESC_INTREQ
| AR5K_TXDESC_CLRDMASK
;
1240 /* XXX endianness */
1241 bf
->skbaddr
= pci_map_single(sc
->pdev
, skb
->data
, skb
->len
,
1244 if (ctl
->flags
& IEEE80211_TXCTL_NO_ACK
)
1245 flags
|= AR5K_TXDESC_NOACK
;
1247 pktlen
= skb
->len
+ FCS_LEN
;
1249 if (!(ctl
->flags
& IEEE80211_TXCTL_DO_NOT_ENCRYPT
)) {
1250 keyidx
= ctl
->key_idx
;
1251 pktlen
+= ctl
->icv_len
;
1254 ret
= ah
->ah_setup_tx_desc(ah
, ds
, pktlen
,
1255 ieee80211_get_hdrlen_from_skb(skb
), AR5K_PKT_TYPE_NORMAL
,
1256 (ctl
->power_level
* 2), ctl
->tx_rate
, ctl
->retry_limit
, keyidx
, 0, flags
, 0, 0);
1261 ds
->ds_data
= bf
->skbaddr
;
1263 spin_lock_bh(&txq
->lock
);
1264 list_add_tail(&bf
->list
, &txq
->q
);
1265 sc
->tx_stats
.data
[txq
->qnum
].len
++;
1266 if (txq
->link
== NULL
) /* is this first packet? */
1267 ath5k_hw_put_tx_buf(ah
, txq
->qnum
, bf
->daddr
);
1268 else /* no, so only link it */
1269 *txq
->link
= bf
->daddr
;
1271 txq
->link
= &ds
->ds_link
;
1272 ath5k_hw_tx_start(ah
, txq
->qnum
);
1273 spin_unlock_bh(&txq
->lock
);
1277 pci_unmap_single(sc
->pdev
, bf
->skbaddr
, skb
->len
, PCI_DMA_TODEVICE
);
1281 /*******************\
1282 * Descriptors setup *
1283 \*******************/
1286 ath5k_desc_alloc(struct ath5k_softc
*sc
, struct pci_dev
*pdev
)
1288 struct ath5k_desc
*ds
;
1289 struct ath5k_buf
*bf
;
1294 /* allocate descriptors */
1295 sc
->desc_len
= sizeof(struct ath5k_desc
) *
1296 (ATH_TXBUF
+ ATH_RXBUF
+ ATH_BCBUF
+ 1);
1297 sc
->desc
= pci_alloc_consistent(pdev
, sc
->desc_len
, &sc
->desc_daddr
);
1298 if (sc
->desc
== NULL
) {
1299 ATH5K_ERR(sc
, "can't allocate descriptors\n");
1304 da
= sc
->desc_daddr
;
1305 ATH5K_DBG(sc
, ATH5K_DEBUG_ANY
, "DMA map: %p (%zu) -> %llx\n",
1306 ds
, sc
->desc_len
, (unsigned long long)sc
->desc_daddr
);
1308 bf
= kcalloc(1 + ATH_TXBUF
+ ATH_RXBUF
+ ATH_BCBUF
,
1309 sizeof(struct ath5k_buf
), GFP_KERNEL
);
1311 ATH5K_ERR(sc
, "can't allocate bufptr\n");
1317 INIT_LIST_HEAD(&sc
->rxbuf
);
1318 for (i
= 0; i
< ATH_RXBUF
; i
++, bf
++, ds
++, da
+= sizeof(*ds
)) {
1321 list_add_tail(&bf
->list
, &sc
->rxbuf
);
1324 INIT_LIST_HEAD(&sc
->txbuf
);
1325 sc
->txbuf_len
= ATH_TXBUF
;
1326 for (i
= 0; i
< ATH_TXBUF
; i
++, bf
++, ds
++,
1327 da
+= sizeof(*ds
)) {
1330 list_add_tail(&bf
->list
, &sc
->txbuf
);
1340 pci_free_consistent(pdev
, sc
->desc_len
, sc
->desc
, sc
->desc_daddr
);
1347 ath5k_desc_free(struct ath5k_softc
*sc
, struct pci_dev
*pdev
)
1349 struct ath5k_buf
*bf
;
1351 ath5k_txbuf_free(sc
, sc
->bbuf
);
1352 list_for_each_entry(bf
, &sc
->txbuf
, list
)
1353 ath5k_txbuf_free(sc
, bf
);
1354 list_for_each_entry(bf
, &sc
->rxbuf
, list
)
1355 ath5k_txbuf_free(sc
, bf
);
1357 /* Free memory associated with all descriptors */
1358 pci_free_consistent(pdev
, sc
->desc_len
, sc
->desc
, sc
->desc_daddr
);
1372 static struct ath5k_txq
*
1373 ath5k_txq_setup(struct ath5k_softc
*sc
,
1374 int qtype
, int subtype
)
1376 struct ath5k_hw
*ah
= sc
->ah
;
1377 struct ath5k_txq
*txq
;
1378 struct ath5k_txq_info qi
= {
1379 .tqi_subtype
= subtype
,
1380 .tqi_aifs
= AR5K_TXQ_USEDEFAULT
,
1381 .tqi_cw_min
= AR5K_TXQ_USEDEFAULT
,
1382 .tqi_cw_max
= AR5K_TXQ_USEDEFAULT
1387 * Enable interrupts only for EOL and DESC conditions.
1388 * We mark tx descriptors to receive a DESC interrupt
1389 * when a tx queue gets deep; otherwise waiting for the
1390 * EOL to reap descriptors. Note that this is done to
1391 * reduce interrupt load and this only defers reaping
1392 * descriptors, never transmitting frames. Aside from
1393 * reducing interrupts this also permits more concurrency.
1394 * The only potential downside is if the tx queue backs
1395 * up in which case the top half of the kernel may backup
1396 * due to a lack of tx descriptors.
1398 qi
.tqi_flags
= AR5K_TXQ_FLAG_TXEOLINT_ENABLE
|
1399 AR5K_TXQ_FLAG_TXDESCINT_ENABLE
;
1400 qnum
= ath5k_hw_setup_tx_queue(ah
, qtype
, &qi
);
1403 * NB: don't print a message, this happens
1404 * normally on parts with too few tx queues
1406 return ERR_PTR(qnum
);
1408 if (qnum
>= ARRAY_SIZE(sc
->txqs
)) {
1409 ATH5K_ERR(sc
, "hw qnum %u out of range, max %tu!\n",
1410 qnum
, ARRAY_SIZE(sc
->txqs
));
1411 ath5k_hw_release_tx_queue(ah
, qnum
);
1412 return ERR_PTR(-EINVAL
);
1414 txq
= &sc
->txqs
[qnum
];
1418 INIT_LIST_HEAD(&txq
->q
);
1419 spin_lock_init(&txq
->lock
);
1422 return &sc
->txqs
[qnum
];
1426 ath5k_beaconq_setup(struct ath5k_hw
*ah
)
1428 struct ath5k_txq_info qi
= {
1429 .tqi_aifs
= AR5K_TXQ_USEDEFAULT
,
1430 .tqi_cw_min
= AR5K_TXQ_USEDEFAULT
,
1431 .tqi_cw_max
= AR5K_TXQ_USEDEFAULT
,
1432 /* NB: for dynamic turbo, don't enable any other interrupts */
1433 .tqi_flags
= AR5K_TXQ_FLAG_TXDESCINT_ENABLE
1436 return ath5k_hw_setup_tx_queue(ah
, AR5K_TX_QUEUE_BEACON
, &qi
);
1440 ath5k_beaconq_config(struct ath5k_softc
*sc
)
1442 struct ath5k_hw
*ah
= sc
->ah
;
1443 struct ath5k_txq_info qi
;
1446 ret
= ath5k_hw_get_tx_queueprops(ah
, sc
->bhalq
, &qi
);
1449 if (sc
->opmode
== IEEE80211_IF_TYPE_AP
||
1450 sc
->opmode
== IEEE80211_IF_TYPE_IBSS
) {
1452 * Always burst out beacon and CAB traffic
1453 * (aifs = cwmin = cwmax = 0)
1460 ret
= ath5k_hw_setup_tx_queueprops(ah
, sc
->bhalq
, &qi
);
1462 ATH5K_ERR(sc
, "%s: unable to update parameters for beacon "
1463 "hardware queue!\n", __func__
);
1467 return ath5k_hw_reset_tx_queue(ah
, sc
->bhalq
); /* push to h/w */;
1471 ath5k_txq_drainq(struct ath5k_softc
*sc
, struct ath5k_txq
*txq
)
1473 struct ath5k_buf
*bf
, *bf0
;
1476 * NB: this assumes output has been stopped and
1477 * we do not need to block ath5k_tx_tasklet
1479 spin_lock_bh(&txq
->lock
);
1480 list_for_each_entry_safe(bf
, bf0
, &txq
->q
, list
) {
1481 ath5k_debug_printtxbuf(sc
, bf
, !sc
->ah
->ah_proc_tx_desc(sc
->ah
,
1484 ath5k_txbuf_free(sc
, bf
);
1486 spin_lock_bh(&sc
->txbuflock
);
1487 sc
->tx_stats
.data
[txq
->qnum
].len
--;
1488 list_move_tail(&bf
->list
, &sc
->txbuf
);
1490 spin_unlock_bh(&sc
->txbuflock
);
1493 spin_unlock_bh(&txq
->lock
);
1497 * Drain the transmit queues and reclaim resources.
1500 ath5k_txq_cleanup(struct ath5k_softc
*sc
)
1502 struct ath5k_hw
*ah
= sc
->ah
;
1505 /* XXX return value */
1506 if (likely(!test_bit(ATH_STAT_INVALID
, sc
->status
))) {
1507 /* don't touch the hardware if marked invalid */
1508 ath5k_hw_stop_tx_dma(ah
, sc
->bhalq
);
1509 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "beacon queue %x\n",
1510 ath5k_hw_get_tx_buf(ah
, sc
->bhalq
));
1511 for (i
= 0; i
< ARRAY_SIZE(sc
->txqs
); i
++)
1512 if (sc
->txqs
[i
].setup
) {
1513 ath5k_hw_stop_tx_dma(ah
, sc
->txqs
[i
].qnum
);
1514 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "txq [%u] %x, "
1517 ath5k_hw_get_tx_buf(ah
,
1522 ieee80211_start_queues(sc
->hw
); /* XXX move to callers */
1524 for (i
= 0; i
< ARRAY_SIZE(sc
->txqs
); i
++)
1525 if (sc
->txqs
[i
].setup
)
1526 ath5k_txq_drainq(sc
, &sc
->txqs
[i
]);
1530 ath5k_txq_release(struct ath5k_softc
*sc
)
1532 struct ath5k_txq
*txq
= sc
->txqs
;
1535 for (i
= 0; i
< ARRAY_SIZE(sc
->txqs
); i
++, txq
++)
1537 ath5k_hw_release_tx_queue(sc
->ah
, txq
->qnum
);
1550 * Enable the receive h/w following a reset.
1553 ath5k_rx_start(struct ath5k_softc
*sc
)
1555 struct ath5k_hw
*ah
= sc
->ah
;
1556 struct ath5k_buf
*bf
;
1559 sc
->rxbufsize
= roundup(IEEE80211_MAX_LEN
, sc
->cachelsz
);
1561 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "cachelsz %u rxbufsize %u\n",
1562 sc
->cachelsz
, sc
->rxbufsize
);
1566 spin_lock_bh(&sc
->rxbuflock
);
1567 list_for_each_entry(bf
, &sc
->rxbuf
, list
) {
1568 ret
= ath5k_rxbuf_setup(sc
, bf
);
1570 spin_unlock_bh(&sc
->rxbuflock
);
1574 bf
= list_first_entry(&sc
->rxbuf
, struct ath5k_buf
, list
);
1575 spin_unlock_bh(&sc
->rxbuflock
);
1577 ath5k_hw_put_rx_buf(ah
, bf
->daddr
);
1578 ath5k_hw_start_rx(ah
); /* enable recv descriptors */
1579 ath5k_mode_setup(sc
); /* set filters, etc. */
1580 ath5k_hw_start_rx_pcu(ah
); /* re-enable PCU/DMA engine */
1588 * Disable the receive h/w in preparation for a reset.
1591 ath5k_rx_stop(struct ath5k_softc
*sc
)
1593 struct ath5k_hw
*ah
= sc
->ah
;
1595 ath5k_hw_stop_pcu_recv(ah
); /* disable PCU */
1596 ath5k_hw_set_rx_filter(ah
, 0); /* clear recv filter */
1597 ath5k_hw_stop_rx_dma(ah
); /* disable DMA engine */
1598 mdelay(3); /* 3ms is long enough for 1 frame */
1600 ath5k_debug_printrxbuffs(sc
, ah
);
1602 sc
->rxlink
= NULL
; /* just in case */
1606 ath5k_rx_decrypted(struct ath5k_softc
*sc
, struct ath5k_desc
*ds
,
1607 struct sk_buff
*skb
)
1609 struct ieee80211_hdr
*hdr
= (void *)skb
->data
;
1610 unsigned int keyix
, hlen
= ieee80211_get_hdrlen_from_skb(skb
);
1612 if (!(ds
->ds_rxstat
.rs_status
& AR5K_RXERR_DECRYPT
) &&
1613 ds
->ds_rxstat
.rs_keyix
!= AR5K_RXKEYIX_INVALID
)
1614 return RX_FLAG_DECRYPTED
;
1616 /* Apparently when a default key is used to decrypt the packet
1617 the hw does not set the index used to decrypt. In such cases
1618 get the index from the packet. */
1619 if ((le16_to_cpu(hdr
->frame_control
) & IEEE80211_FCTL_PROTECTED
) &&
1620 !(ds
->ds_rxstat
.rs_status
& AR5K_RXERR_DECRYPT
) &&
1621 skb
->len
>= hlen
+ 4) {
1622 keyix
= skb
->data
[hlen
+ 3] >> 6;
1624 if (test_bit(keyix
, sc
->keymap
))
1625 return RX_FLAG_DECRYPTED
;
1632 ath5k_tasklet_rx(unsigned long data
)
1634 struct ieee80211_rx_status rxs
= {};
1635 struct sk_buff
*skb
;
1636 struct ath5k_softc
*sc
= (void *)data
;
1637 struct ath5k_buf
*bf
;
1638 struct ath5k_desc
*ds
;
1645 spin_lock(&sc
->rxbuflock
);
1647 if (unlikely(list_empty(&sc
->rxbuf
))) {
1648 ATH5K_WARN(sc
, "empty rx buf pool\n");
1651 bf
= list_first_entry(&sc
->rxbuf
, struct ath5k_buf
, list
);
1652 BUG_ON(bf
->skb
== NULL
);
1656 /* TODO only one segment */
1657 pci_dma_sync_single_for_cpu(sc
->pdev
, sc
->desc_daddr
,
1658 sc
->desc_len
, PCI_DMA_FROMDEVICE
);
1660 if (unlikely(ds
->ds_link
== bf
->daddr
)) /* this is the end */
1663 ret
= sc
->ah
->ah_proc_rx_desc(sc
->ah
, ds
);
1664 if (unlikely(ret
== -EINPROGRESS
))
1666 else if (unlikely(ret
)) {
1667 ATH5K_ERR(sc
, "error in processing rx descriptor\n");
1671 if (unlikely(ds
->ds_rxstat
.rs_more
)) {
1672 ATH5K_WARN(sc
, "unsupported jumbo\n");
1676 stat
= ds
->ds_rxstat
.rs_status
;
1677 if (unlikely(stat
)) {
1678 if (stat
& AR5K_RXERR_PHY
)
1680 if (stat
& AR5K_RXERR_DECRYPT
) {
1682 * Decrypt error. If the error occurred
1683 * because there was no hardware key, then
1684 * let the frame through so the upper layers
1685 * can process it. This is necessary for 5210
1686 * parts which have no way to setup a ``clear''
1689 * XXX do key cache faulting
1691 if (ds
->ds_rxstat
.rs_keyix
==
1692 AR5K_RXKEYIX_INVALID
&&
1693 !(stat
& AR5K_RXERR_CRC
))
1696 if (stat
& AR5K_RXERR_MIC
) {
1697 rxs
.flag
|= RX_FLAG_MMIC_ERROR
;
1701 /* let crypto-error packets fall through in MNTR */
1702 if ((stat
& ~(AR5K_RXERR_DECRYPT
|AR5K_RXERR_MIC
)) ||
1703 sc
->opmode
!= IEEE80211_IF_TYPE_MNTR
)
1707 len
= ds
->ds_rxstat
.rs_datalen
;
1708 pci_dma_sync_single_for_cpu(sc
->pdev
, bf
->skbaddr
, len
,
1709 PCI_DMA_FROMDEVICE
);
1710 pci_unmap_single(sc
->pdev
, bf
->skbaddr
, sc
->rxbufsize
,
1711 PCI_DMA_FROMDEVICE
);
1717 * the hardware adds a padding to 4 byte boundaries between
1718 * the header and the payload data if the header length is
1719 * not multiples of 4 - remove it
1721 hdrlen
= ieee80211_get_hdrlen_from_skb(skb
);
1724 memmove(skb
->data
+ pad
, skb
->data
, hdrlen
);
1728 if (sc
->opmode
== IEEE80211_IF_TYPE_MNTR
)
1729 rxs
.mactime
= ath5k_extend_tsf(sc
->ah
,
1730 ds
->ds_rxstat
.rs_tstamp
);
1732 rxs
.mactime
= ds
->ds_rxstat
.rs_tstamp
;
1733 rxs
.freq
= sc
->curchan
->freq
;
1734 rxs
.channel
= sc
->curchan
->chan
;
1735 rxs
.phymode
= sc
->curmode
;
1739 * the names here are misleading and the usage of these
1740 * values by iwconfig makes it even worse
1742 /* noise floor in dBm, from the last noise calibration */
1743 rxs
.noise
= sc
->ah
->ah_noise_floor
;
1744 /* signal level in dBm */
1745 rxs
.ssi
= rxs
.noise
+ ds
->ds_rxstat
.rs_rssi
;
1747 * "signal" is actually displayed as Link Quality by iwconfig
1748 * we provide a percentage based on rssi (assuming max rssi 64)
1750 rxs
.signal
= ds
->ds_rxstat
.rs_rssi
* 100 / 64;
1752 rxs
.antenna
= ds
->ds_rxstat
.rs_antenna
;
1753 rxs
.rate
= ds
->ds_rxstat
.rs_rate
;
1754 rxs
.flag
|= ath5k_rx_decrypted(sc
, ds
, skb
);
1756 ath5k_debug_dump_skb(sc
, skb
, "RX ", 0);
1758 __ieee80211_rx(sc
->hw
, skb
, &rxs
);
1759 sc
->led_rxrate
= ds
->ds_rxstat
.rs_rate
;
1760 ath5k_led_event(sc
, ATH_LED_RX
);
1762 list_move_tail(&bf
->list
, &sc
->rxbuf
);
1763 } while (ath5k_rxbuf_setup(sc
, bf
) == 0);
1764 spin_unlock(&sc
->rxbuflock
);
1775 ath5k_tx_processq(struct ath5k_softc
*sc
, struct ath5k_txq
*txq
)
1777 struct ieee80211_tx_status txs
= {};
1778 struct ath5k_buf
*bf
, *bf0
;
1779 struct ath5k_desc
*ds
;
1780 struct sk_buff
*skb
;
1783 spin_lock(&txq
->lock
);
1784 list_for_each_entry_safe(bf
, bf0
, &txq
->q
, list
) {
1787 /* TODO only one segment */
1788 pci_dma_sync_single_for_cpu(sc
->pdev
, sc
->desc_daddr
,
1789 sc
->desc_len
, PCI_DMA_FROMDEVICE
);
1790 ret
= sc
->ah
->ah_proc_tx_desc(sc
->ah
, ds
);
1791 if (unlikely(ret
== -EINPROGRESS
))
1793 else if (unlikely(ret
)) {
1794 ATH5K_ERR(sc
, "error %d while processing queue %u\n",
1801 pci_unmap_single(sc
->pdev
, bf
->skbaddr
, skb
->len
,
1804 txs
.control
= bf
->ctl
;
1805 txs
.retry_count
= ds
->ds_txstat
.ts_shortretry
+
1806 ds
->ds_txstat
.ts_longretry
/ 6;
1807 if (unlikely(ds
->ds_txstat
.ts_status
)) {
1808 sc
->ll_stats
.dot11ACKFailureCount
++;
1809 if (ds
->ds_txstat
.ts_status
& AR5K_TXERR_XRETRY
)
1810 txs
.excessive_retries
= 1;
1811 else if (ds
->ds_txstat
.ts_status
& AR5K_TXERR_FILT
)
1812 txs
.flags
|= IEEE80211_TX_STATUS_TX_FILTERED
;
1814 txs
.flags
|= IEEE80211_TX_STATUS_ACK
;
1815 txs
.ack_signal
= ds
->ds_txstat
.ts_rssi
;
1818 ieee80211_tx_status(sc
->hw
, skb
, &txs
);
1819 sc
->tx_stats
.data
[txq
->qnum
].count
++;
1821 spin_lock(&sc
->txbuflock
);
1822 sc
->tx_stats
.data
[txq
->qnum
].len
--;
1823 list_move_tail(&bf
->list
, &sc
->txbuf
);
1825 spin_unlock(&sc
->txbuflock
);
1827 if (likely(list_empty(&txq
->q
)))
1829 spin_unlock(&txq
->lock
);
1830 if (sc
->txbuf_len
> ATH_TXBUF
/ 5)
1831 ieee80211_wake_queues(sc
->hw
);
1835 ath5k_tasklet_tx(unsigned long data
)
1837 struct ath5k_softc
*sc
= (void *)data
;
1839 ath5k_tx_processq(sc
, sc
->txq
);
1841 ath5k_led_event(sc
, ATH_LED_TX
);
1852 * Setup the beacon frame for transmit.
1855 ath5k_beacon_setup(struct ath5k_softc
*sc
, struct ath5k_buf
*bf
,
1856 struct ieee80211_tx_control
*ctl
)
1858 struct sk_buff
*skb
= bf
->skb
;
1859 struct ath5k_hw
*ah
= sc
->ah
;
1860 struct ath5k_desc
*ds
;
1861 int ret
, antenna
= 0;
1864 bf
->skbaddr
= pci_map_single(sc
->pdev
, skb
->data
, skb
->len
,
1866 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON
, "skb %p [data %p len %u] "
1867 "skbaddr %llx\n", skb
, skb
->data
, skb
->len
,
1868 (unsigned long long)bf
->skbaddr
);
1869 if (pci_dma_mapping_error(bf
->skbaddr
)) {
1870 ATH5K_ERR(sc
, "beacon DMA mapping failed\n");
1876 flags
= AR5K_TXDESC_NOACK
;
1877 if (sc
->opmode
== IEEE80211_IF_TYPE_IBSS
&& ath5k_hw_hasveol(ah
)) {
1878 ds
->ds_link
= bf
->daddr
; /* self-linked */
1879 flags
|= AR5K_TXDESC_VEOL
;
1881 * Let hardware handle antenna switching if txantenna is not set
1886 * Switch antenna every 4 beacons if txantenna is not set
1887 * XXX assumes two antennas
1890 antenna
= sc
->bsent
& 4 ? 2 : 1;
1893 ds
->ds_data
= bf
->skbaddr
;
1894 ret
= ah
->ah_setup_tx_desc(ah
, ds
, skb
->len
+ FCS_LEN
,
1895 ieee80211_get_hdrlen_from_skb(skb
),
1896 AR5K_PKT_TYPE_BEACON
, (ctl
->power_level
* 2), ctl
->tx_rate
, 1,
1897 AR5K_TXKEYIX_INVALID
, antenna
, flags
, 0, 0);
1903 pci_unmap_single(sc
->pdev
, bf
->skbaddr
, skb
->len
, PCI_DMA_TODEVICE
);
1908 * Transmit a beacon frame at SWBA. Dynamic updates to the
1909 * frame contents are done as needed and the slot time is
1910 * also adjusted based on current state.
1912 * this is usually called from interrupt context (ath5k_intr())
1913 * but also from ath5k_beacon_config() in IBSS mode which in turn
1914 * can be called from a tasklet and user context
1917 ath5k_beacon_send(struct ath5k_softc
*sc
)
1919 struct ath5k_buf
*bf
= sc
->bbuf
;
1920 struct ath5k_hw
*ah
= sc
->ah
;
1922 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON_PROC
, "in beacon_send\n");
1924 if (unlikely(bf
->skb
== NULL
|| sc
->opmode
== IEEE80211_IF_TYPE_STA
||
1925 sc
->opmode
== IEEE80211_IF_TYPE_MNTR
)) {
1926 ATH5K_WARN(sc
, "bf=%p bf_skb=%p\n", bf
, bf
? bf
->skb
: NULL
);
1930 * Check if the previous beacon has gone out. If
1931 * not don't don't try to post another, skip this
1932 * period and wait for the next. Missed beacons
1933 * indicate a problem and should not occur. If we
1934 * miss too many consecutive beacons reset the device.
1936 if (unlikely(ath5k_hw_num_tx_pending(ah
, sc
->bhalq
) != 0)) {
1938 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON_PROC
,
1939 "missed %u consecutive beacons\n", sc
->bmisscount
);
1940 if (sc
->bmisscount
> 3) { /* NB: 3 is a guess */
1941 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON_PROC
,
1942 "stuck beacon time (%u missed)\n",
1944 tasklet_schedule(&sc
->restq
);
1948 if (unlikely(sc
->bmisscount
!= 0)) {
1949 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON_PROC
,
1950 "resume beacon xmit after %u misses\n",
1956 * Stop any current dma and put the new frame on the queue.
1957 * This should never fail since we check above that no frames
1958 * are still pending on the queue.
1960 if (unlikely(ath5k_hw_stop_tx_dma(ah
, sc
->bhalq
))) {
1961 ATH5K_WARN(sc
, "beacon queue %u didn't stop?\n", sc
->bhalq
);
1962 /* NB: hw still stops DMA, so proceed */
1964 pci_dma_sync_single_for_cpu(sc
->pdev
, bf
->skbaddr
, bf
->skb
->len
,
1967 ath5k_hw_put_tx_buf(ah
, sc
->bhalq
, bf
->daddr
);
1968 ath5k_hw_tx_start(ah
, sc
->bhalq
);
1969 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON_PROC
, "TXDP[%u] = %llx (%p)\n",
1970 sc
->bhalq
, (unsigned long long)bf
->daddr
, bf
->desc
);
1977 ath5k_beacon_update_timers(struct ath5k_softc
*sc
)
1979 struct ath5k_hw
*ah
= sc
->ah
;
1980 u32
uninitialized_var(nexttbtt
), intval
, tsftu
;
1983 intval
= sc
->bintval
& AR5K_BEACON_PERIOD
;
1984 if (WARN_ON(!intval
))
1987 /* current TSF converted to TU */
1988 tsf
= ath5k_hw_get_tsf64(ah
);
1989 tsftu
= TSF_TO_TU(tsf
);
1992 * Pull nexttbtt forward to reflect the current
1993 * TSF. Add one intval otherwise the timespan
1994 * can be too short for ibss merges.
1996 nexttbtt
= tsftu
+ 2 * intval
;
1998 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON
,
1999 "hw tsftu %u nexttbtt %u intval %u\n", tsftu
, nexttbtt
, intval
);
2001 intval
|= AR5K_BEACON_ENA
;
2003 ath5k_hw_init_beacon(ah
, nexttbtt
, intval
);
2008 * Configure the beacon timers and interrupts based on the operating mode
2010 * When operating in station mode we want to receive a BMISS interrupt when we
2011 * stop seeing beacons from the AP we've associated with so we can look for
2012 * another AP to associate with.
2014 * In IBSS mode we need to configure the beacon timers and use a self-linked tx
2015 * descriptor if possible. If the hardware cannot deal with that we enable SWBA
2016 * interrupts to send the beacons from the interrupt handler.
2019 ath5k_beacon_config(struct ath5k_softc
*sc
)
2021 struct ath5k_hw
*ah
= sc
->ah
;
2023 ath5k_hw_set_intr(ah
, 0);
2026 if (sc
->opmode
== IEEE80211_IF_TYPE_STA
) {
2027 sc
->imask
|= AR5K_INT_BMISS
;
2028 } else if (sc
->opmode
== IEEE80211_IF_TYPE_IBSS
) {
2030 * In IBSS mode enable the beacon timers but only enable SWBA
2031 * interrupts if we need to manually prepare beacon frames.
2032 * Otherwise we use a self-linked tx descriptor and let the
2033 * hardware deal with things. In that case we have to load it
2036 ath5k_beaconq_config(sc
);
2037 ath5k_beacon_update_timers(sc
);
2039 if (!ath5k_hw_hasveol(ah
))
2040 sc
->imask
|= AR5K_INT_SWBA
;
2042 ath5k_beacon_send(sc
);
2046 ath5k_hw_set_intr(ah
, sc
->imask
);
2050 /********************\
2051 * Interrupt handling *
2052 \********************/
2055 ath5k_init(struct ath5k_softc
*sc
)
2059 mutex_lock(&sc
->lock
);
2061 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "mode %d\n", sc
->opmode
);
2064 * Stop anything previously setup. This is safe
2065 * no matter this is the first time through or not.
2067 ath5k_stop_locked(sc
);
2070 * The basic interface to setting the hardware in a good
2071 * state is ``reset''. On return the hardware is known to
2072 * be powered up and with interrupts disabled. This must
2073 * be followed by initialization of the appropriate bits
2074 * and then setup of the interrupt mask.
2076 sc
->curchan
= sc
->hw
->conf
.chan
;
2077 ret
= ath5k_hw_reset(sc
->ah
, sc
->opmode
, sc
->curchan
, false);
2079 ATH5K_ERR(sc
, "unable to reset hardware: %d\n", ret
);
2083 * This is needed only to setup initial state
2084 * but it's best done after a reset.
2086 ath5k_hw_set_txpower_limit(sc
->ah
, 0);
2089 * Setup the hardware after reset: the key cache
2090 * is filled as needed and the receive engine is
2091 * set going. Frame transmit is handled entirely
2092 * in the frame output path; there's nothing to do
2093 * here except setup the interrupt mask.
2095 ret
= ath5k_rx_start(sc
);
2100 * Enable interrupts.
2102 sc
->imask
= AR5K_INT_RX
| AR5K_INT_TX
| AR5K_INT_RXEOL
|
2103 AR5K_INT_RXORN
| AR5K_INT_FATAL
| AR5K_INT_GLOBAL
;
2105 ath5k_hw_set_intr(sc
->ah
, sc
->imask
);
2106 /* Set ack to be sent at low bit-rates */
2107 ath5k_hw_set_ack_bitrate_high(sc
->ah
, false);
2109 mod_timer(&sc
->calib_tim
, round_jiffies(jiffies
+
2110 msecs_to_jiffies(ath5k_calinterval
* 1000)));
2114 mutex_unlock(&sc
->lock
);
2119 ath5k_stop_locked(struct ath5k_softc
*sc
)
2121 struct ath5k_hw
*ah
= sc
->ah
;
2123 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "invalid %u\n",
2124 test_bit(ATH_STAT_INVALID
, sc
->status
));
2127 * Shutdown the hardware and driver:
2128 * stop output from above
2129 * disable interrupts
2131 * turn off the radio
2132 * clear transmit machinery
2133 * clear receive machinery
2134 * drain and release tx queues
2135 * reclaim beacon resources
2136 * power down hardware
2138 * Note that some of this work is not possible if the
2139 * hardware is gone (invalid).
2141 ieee80211_stop_queues(sc
->hw
);
2143 if (!test_bit(ATH_STAT_INVALID
, sc
->status
)) {
2144 if (test_bit(ATH_STAT_LEDSOFT
, sc
->status
)) {
2145 del_timer_sync(&sc
->led_tim
);
2146 ath5k_hw_set_gpio(ah
, sc
->led_pin
, !sc
->led_on
);
2147 __clear_bit(ATH_STAT_LEDBLINKING
, sc
->status
);
2149 ath5k_hw_set_intr(ah
, 0);
2151 ath5k_txq_cleanup(sc
);
2152 if (!test_bit(ATH_STAT_INVALID
, sc
->status
)) {
2154 ath5k_hw_phy_disable(ah
);
2162 * Stop the device, grabbing the top-level lock to protect
2163 * against concurrent entry through ath5k_init (which can happen
2164 * if another thread does a system call and the thread doing the
2165 * stop is preempted).
2168 ath5k_stop_hw(struct ath5k_softc
*sc
)
2172 mutex_lock(&sc
->lock
);
2173 ret
= ath5k_stop_locked(sc
);
2174 if (ret
== 0 && !test_bit(ATH_STAT_INVALID
, sc
->status
)) {
2176 * Set the chip in full sleep mode. Note that we are
2177 * careful to do this only when bringing the interface
2178 * completely to a stop. When the chip is in this state
2179 * it must be carefully woken up or references to
2180 * registers in the PCI clock domain may freeze the bus
2181 * (and system). This varies by chip and is mostly an
2182 * issue with newer parts that go to sleep more quickly.
2184 if (sc
->ah
->ah_mac_srev
>= 0x78) {
2187 * don't put newer MAC revisions > 7.8 to sleep because
2188 * of the above mentioned problems
2190 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "mac version > 7.8, "
2191 "not putting device to sleep\n");
2193 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
,
2194 "putting device to full sleep\n");
2195 ath5k_hw_set_power(sc
->ah
, AR5K_PM_FULL_SLEEP
, true, 0);
2198 ath5k_txbuf_free(sc
, sc
->bbuf
);
2199 mutex_unlock(&sc
->lock
);
2201 del_timer_sync(&sc
->calib_tim
);
2207 ath5k_intr(int irq
, void *dev_id
)
2209 struct ath5k_softc
*sc
= dev_id
;
2210 struct ath5k_hw
*ah
= sc
->ah
;
2211 enum ath5k_int status
;
2212 unsigned int counter
= 1000;
2214 if (unlikely(test_bit(ATH_STAT_INVALID
, sc
->status
) ||
2215 !ath5k_hw_is_intr_pending(ah
)))
2220 * Figure out the reason(s) for the interrupt. Note
2221 * that get_isr returns a pseudo-ISR that may include
2222 * bits we haven't explicitly enabled so we mask the
2223 * value to insure we only process bits we requested.
2225 ath5k_hw_get_isr(ah
, &status
); /* NB: clears IRQ too */
2226 ATH5K_DBG(sc
, ATH5K_DEBUG_INTR
, "status 0x%x/0x%x\n",
2228 status
&= sc
->imask
; /* discard unasked for bits */
2229 if (unlikely(status
& AR5K_INT_FATAL
)) {
2231 * Fatal errors are unrecoverable.
2232 * Typically these are caused by DMA errors.
2234 tasklet_schedule(&sc
->restq
);
2235 } else if (unlikely(status
& AR5K_INT_RXORN
)) {
2236 tasklet_schedule(&sc
->restq
);
2238 if (status
& AR5K_INT_SWBA
) {
2240 * Software beacon alert--time to send a beacon.
2241 * Handle beacon transmission directly; deferring
2242 * this is too slow to meet timing constraints
2245 ath5k_beacon_send(sc
);
2247 if (status
& AR5K_INT_RXEOL
) {
2249 * NB: the hardware should re-read the link when
2250 * RXE bit is written, but it doesn't work at
2251 * least on older hardware revs.
2255 if (status
& AR5K_INT_TXURN
) {
2256 /* bump tx trigger level */
2257 ath5k_hw_update_tx_triglevel(ah
, true);
2259 if (status
& AR5K_INT_RX
)
2260 tasklet_schedule(&sc
->rxtq
);
2261 if (status
& AR5K_INT_TX
)
2262 tasklet_schedule(&sc
->txtq
);
2263 if (status
& AR5K_INT_BMISS
) {
2265 if (status
& AR5K_INT_MIB
) {
2269 } while (ath5k_hw_is_intr_pending(ah
) && counter
-- > 0);
2271 if (unlikely(!counter
))
2272 ATH5K_WARN(sc
, "too many interrupts, giving up for now\n");
2278 ath5k_tasklet_reset(unsigned long data
)
2280 struct ath5k_softc
*sc
= (void *)data
;
2282 ath5k_reset(sc
->hw
);
2286 * Periodically recalibrate the PHY to account
2287 * for temperature/environment changes.
2290 ath5k_calibrate(unsigned long data
)
2292 struct ath5k_softc
*sc
= (void *)data
;
2293 struct ath5k_hw
*ah
= sc
->ah
;
2295 ATH5K_DBG(sc
, ATH5K_DEBUG_CALIBRATE
, "channel %u/%x\n",
2296 sc
->curchan
->chan
, sc
->curchan
->val
);
2298 if (ath5k_hw_get_rf_gain(ah
) == AR5K_RFGAIN_NEED_CHANGE
) {
2300 * Rfgain is out of bounds, reset the chip
2301 * to load new gain values.
2303 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "calibration, resetting\n");
2304 ath5k_reset(sc
->hw
);
2306 if (ath5k_hw_phy_calibrate(ah
, sc
->curchan
))
2307 ATH5K_ERR(sc
, "calibration of channel %u failed\n",
2310 mod_timer(&sc
->calib_tim
, round_jiffies(jiffies
+
2311 msecs_to_jiffies(ath5k_calinterval
* 1000)));
2321 ath5k_led_off(unsigned long data
)
2323 struct ath5k_softc
*sc
= (void *)data
;
2325 if (test_bit(ATH_STAT_LEDENDBLINK
, sc
->status
))
2326 __clear_bit(ATH_STAT_LEDBLINKING
, sc
->status
);
2328 __set_bit(ATH_STAT_LEDENDBLINK
, sc
->status
);
2329 ath5k_hw_set_gpio(sc
->ah
, sc
->led_pin
, !sc
->led_on
);
2330 mod_timer(&sc
->led_tim
, jiffies
+ sc
->led_off
);
2335 * Blink the LED according to the specified on/off times.
2338 ath5k_led_blink(struct ath5k_softc
*sc
, unsigned int on
,
2341 ATH5K_DBG(sc
, ATH5K_DEBUG_LED
, "on %u off %u\n", on
, off
);
2342 ath5k_hw_set_gpio(sc
->ah
, sc
->led_pin
, sc
->led_on
);
2343 __set_bit(ATH_STAT_LEDBLINKING
, sc
->status
);
2344 __clear_bit(ATH_STAT_LEDENDBLINK
, sc
->status
);
2346 mod_timer(&sc
->led_tim
, jiffies
+ on
);
2350 ath5k_led_event(struct ath5k_softc
*sc
, int event
)
2352 if (likely(!test_bit(ATH_STAT_LEDSOFT
, sc
->status
)))
2354 if (unlikely(test_bit(ATH_STAT_LEDBLINKING
, sc
->status
)))
2355 return; /* don't interrupt active blink */
2358 ath5k_led_blink(sc
, sc
->hwmap
[sc
->led_txrate
].ledon
,
2359 sc
->hwmap
[sc
->led_txrate
].ledoff
);
2362 ath5k_led_blink(sc
, sc
->hwmap
[sc
->led_rxrate
].ledon
,
2363 sc
->hwmap
[sc
->led_rxrate
].ledoff
);
2371 /********************\
2372 * Mac80211 functions *
2373 \********************/
2376 ath5k_tx(struct ieee80211_hw
*hw
, struct sk_buff
*skb
,
2377 struct ieee80211_tx_control
*ctl
)
2379 struct ath5k_softc
*sc
= hw
->priv
;
2380 struct ath5k_buf
*bf
;
2381 unsigned long flags
;
2385 ath5k_debug_dump_skb(sc
, skb
, "TX ", 1);
2387 if (sc
->opmode
== IEEE80211_IF_TYPE_MNTR
)
2388 ATH5K_DBG(sc
, ATH5K_DEBUG_XMIT
, "tx in monitor (scan?)\n");
2391 * the hardware expects the header padded to 4 byte boundaries
2392 * if this is not the case we add the padding after the header
2394 hdrlen
= ieee80211_get_hdrlen_from_skb(skb
);
2397 if (skb_headroom(skb
) < pad
) {
2398 ATH5K_ERR(sc
, "tx hdrlen not %%4: %d not enough"
2399 " headroom to pad %d\n", hdrlen
, pad
);
2403 memmove(skb
->data
, skb
->data
+pad
, hdrlen
);
2406 sc
->led_txrate
= ctl
->tx_rate
;
2408 spin_lock_irqsave(&sc
->txbuflock
, flags
);
2409 if (list_empty(&sc
->txbuf
)) {
2410 ATH5K_ERR(sc
, "no further txbuf available, dropping packet\n");
2411 spin_unlock_irqrestore(&sc
->txbuflock
, flags
);
2412 ieee80211_stop_queue(hw
, ctl
->queue
);
2415 bf
= list_first_entry(&sc
->txbuf
, struct ath5k_buf
, list
);
2416 list_del(&bf
->list
);
2418 if (list_empty(&sc
->txbuf
))
2419 ieee80211_stop_queues(hw
);
2420 spin_unlock_irqrestore(&sc
->txbuflock
, flags
);
2424 if (ath5k_txbuf_setup(sc
, bf
, ctl
)) {
2426 spin_lock_irqsave(&sc
->txbuflock
, flags
);
2427 list_add_tail(&bf
->list
, &sc
->txbuf
);
2429 spin_unlock_irqrestore(&sc
->txbuflock
, flags
);
2430 dev_kfree_skb_any(skb
);
2438 ath5k_reset(struct ieee80211_hw
*hw
)
2440 struct ath5k_softc
*sc
= hw
->priv
;
2441 struct ath5k_hw
*ah
= sc
->ah
;
2444 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "resetting\n");
2446 * Convert to a hw channel description with the flags
2447 * constrained to reflect the current operating mode.
2449 sc
->curchan
= hw
->conf
.chan
;
2451 ath5k_hw_set_intr(ah
, 0);
2452 ath5k_txq_cleanup(sc
);
2455 ret
= ath5k_hw_reset(ah
, sc
->opmode
, sc
->curchan
, true);
2456 if (unlikely(ret
)) {
2457 ATH5K_ERR(sc
, "can't reset hardware (%d)\n", ret
);
2460 ath5k_hw_set_txpower_limit(sc
->ah
, 0);
2462 ret
= ath5k_rx_start(sc
);
2463 if (unlikely(ret
)) {
2464 ATH5K_ERR(sc
, "can't start recv logic\n");
2468 * We may be doing a reset in response to an ioctl
2469 * that changes the channel so update any state that
2470 * might change as a result.
2474 /* ath5k_chan_change(sc, c); */
2475 ath5k_beacon_config(sc
);
2476 /* intrs are started by ath5k_beacon_config */
2478 ieee80211_wake_queues(hw
);
2485 static int ath5k_start(struct ieee80211_hw
*hw
)
2487 return ath5k_init(hw
->priv
);
2490 static void ath5k_stop(struct ieee80211_hw
*hw
)
2492 ath5k_stop_hw(hw
->priv
);
2495 static int ath5k_add_interface(struct ieee80211_hw
*hw
,
2496 struct ieee80211_if_init_conf
*conf
)
2498 struct ath5k_softc
*sc
= hw
->priv
;
2501 mutex_lock(&sc
->lock
);
2507 sc
->vif
= conf
->vif
;
2509 switch (conf
->type
) {
2510 case IEEE80211_IF_TYPE_STA
:
2511 case IEEE80211_IF_TYPE_IBSS
:
2512 case IEEE80211_IF_TYPE_MNTR
:
2513 sc
->opmode
= conf
->type
;
2521 mutex_unlock(&sc
->lock
);
2526 ath5k_remove_interface(struct ieee80211_hw
*hw
,
2527 struct ieee80211_if_init_conf
*conf
)
2529 struct ath5k_softc
*sc
= hw
->priv
;
2531 mutex_lock(&sc
->lock
);
2532 if (sc
->vif
!= conf
->vif
)
2537 mutex_unlock(&sc
->lock
);
2541 ath5k_config(struct ieee80211_hw
*hw
,
2542 struct ieee80211_conf
*conf
)
2544 struct ath5k_softc
*sc
= hw
->priv
;
2546 sc
->bintval
= conf
->beacon_int
* 1000 / 1024;
2547 ath5k_setcurmode(sc
, conf
->phymode
);
2549 return ath5k_chan_set(sc
, conf
->chan
);
2553 ath5k_config_interface(struct ieee80211_hw
*hw
, struct ieee80211_vif
*vif
,
2554 struct ieee80211_if_conf
*conf
)
2556 struct ath5k_softc
*sc
= hw
->priv
;
2557 struct ath5k_hw
*ah
= sc
->ah
;
2560 /* Set to a reasonable value. Note that this will
2561 * be set to mac80211's value at ath5k_config(). */
2562 sc
->bintval
= 1000 * 1000 / 1024;
2563 mutex_lock(&sc
->lock
);
2564 if (sc
->vif
!= vif
) {
2569 /* Cache for later use during resets */
2570 memcpy(ah
->ah_bssid
, conf
->bssid
, ETH_ALEN
);
2571 /* XXX: assoc id is set to 0 for now, mac80211 doesn't have
2572 * a clean way of letting us retrieve this yet. */
2573 ath5k_hw_set_associd(ah
, ah
->ah_bssid
, 0);
2575 mutex_unlock(&sc
->lock
);
2577 return ath5k_reset(hw
);
2579 mutex_unlock(&sc
->lock
);
2583 #define SUPPORTED_FIF_FLAGS \
2584 FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \
2585 FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
2586 FIF_BCN_PRBRESP_PROMISC
2588 * o always accept unicast, broadcast, and multicast traffic
2589 * o multicast traffic for all BSSIDs will be enabled if mac80211
2591 * o maintain current state of phy ofdm or phy cck error reception.
2592 * If the hardware detects any of these type of errors then
2593 * ath5k_hw_get_rx_filter() will pass to us the respective
2594 * hardware filters to be able to receive these type of frames.
2595 * o probe request frames are accepted only when operating in
2596 * hostap, adhoc, or monitor modes
2597 * o enable promiscuous mode according to the interface state
2599 * - when operating in adhoc mode so the 802.11 layer creates
2600 * node table entries for peers,
2601 * - when operating in station mode for collecting rssi data when
2602 * the station is otherwise quiet, or
2605 static void ath5k_configure_filter(struct ieee80211_hw
*hw
,
2606 unsigned int changed_flags
,
2607 unsigned int *new_flags
,
2608 int mc_count
, struct dev_mc_list
*mclist
)
2610 struct ath5k_softc
*sc
= hw
->priv
;
2611 struct ath5k_hw
*ah
= sc
->ah
;
2612 u32 mfilt
[2], val
, rfilt
;
2619 /* Only deal with supported flags */
2620 changed_flags
&= SUPPORTED_FIF_FLAGS
;
2621 *new_flags
&= SUPPORTED_FIF_FLAGS
;
2623 /* If HW detects any phy or radar errors, leave those filters on.
2624 * Also, always enable Unicast, Broadcasts and Multicast
2625 * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
2626 rfilt
= (ath5k_hw_get_rx_filter(ah
) & (AR5K_RX_FILTER_PHYERR
)) |
2627 (AR5K_RX_FILTER_UCAST
| AR5K_RX_FILTER_BCAST
|
2628 AR5K_RX_FILTER_MCAST
);
2630 if (changed_flags
& (FIF_PROMISC_IN_BSS
| FIF_OTHER_BSS
)) {
2631 if (*new_flags
& FIF_PROMISC_IN_BSS
) {
2632 rfilt
|= AR5K_RX_FILTER_PROM
;
2633 __set_bit(ATH_STAT_PROMISC
, sc
->status
);
2636 __clear_bit(ATH_STAT_PROMISC
, sc
->status
);
2639 /* Note, AR5K_RX_FILTER_MCAST is already enabled */
2640 if (*new_flags
& FIF_ALLMULTI
) {
2644 for (i
= 0; i
< mc_count
; i
++) {
2647 /* calculate XOR of eight 6-bit values */
2648 val
= LE_READ_4(mclist
->dmi_addr
+ 0);
2649 pos
= (val
>> 18) ^ (val
>> 12) ^ (val
>> 6) ^ val
;
2650 val
= LE_READ_4(mclist
->dmi_addr
+ 3);
2651 pos
^= (val
>> 18) ^ (val
>> 12) ^ (val
>> 6) ^ val
;
2653 mfilt
[pos
/ 32] |= (1 << (pos
% 32));
2654 /* XXX: we might be able to just do this instead,
2655 * but not sure, needs testing, if we do use this we'd
2656 * neet to inform below to not reset the mcast */
2657 /* ath5k_hw_set_mcast_filterindex(ah,
2658 * mclist->dmi_addr[5]); */
2659 mclist
= mclist
->next
;
2663 /* This is the best we can do */
2664 if (*new_flags
& (FIF_FCSFAIL
| FIF_PLCPFAIL
))
2665 rfilt
|= AR5K_RX_FILTER_PHYERR
;
2667 /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
2668 * and probes for any BSSID, this needs testing */
2669 if (*new_flags
& FIF_BCN_PRBRESP_PROMISC
)
2670 rfilt
|= AR5K_RX_FILTER_BEACON
| AR5K_RX_FILTER_PROBEREQ
;
2672 /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
2673 * set we should only pass on control frames for this
2674 * station. This needs testing. I believe right now this
2675 * enables *all* control frames, which is OK.. but
2676 * but we should see if we can improve on granularity */
2677 if (*new_flags
& FIF_CONTROL
)
2678 rfilt
|= AR5K_RX_FILTER_CONTROL
;
2680 /* Additional settings per mode -- this is per ath5k */
2682 /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
2684 if (sc
->opmode
== IEEE80211_IF_TYPE_MNTR
)
2685 rfilt
|= AR5K_RX_FILTER_CONTROL
| AR5K_RX_FILTER_BEACON
|
2686 AR5K_RX_FILTER_PROBEREQ
| AR5K_RX_FILTER_PROM
;
2687 if (sc
->opmode
!= IEEE80211_IF_TYPE_STA
)
2688 rfilt
|= AR5K_RX_FILTER_PROBEREQ
;
2689 if (sc
->opmode
!= IEEE80211_IF_TYPE_AP
&&
2690 test_bit(ATH_STAT_PROMISC
, sc
->status
))
2691 rfilt
|= AR5K_RX_FILTER_PROM
;
2692 if (sc
->opmode
== IEEE80211_IF_TYPE_STA
||
2693 sc
->opmode
== IEEE80211_IF_TYPE_IBSS
) {
2694 rfilt
|= AR5K_RX_FILTER_BEACON
;
2698 ath5k_hw_set_rx_filter(ah
,rfilt
);
2700 /* Set multicast bits */
2701 ath5k_hw_set_mcast_filter(ah
, mfilt
[0], mfilt
[1]);
2702 /* Set the cached hw filter flags, this will alter actually
2704 sc
->filter_flags
= rfilt
;
2708 ath5k_set_key(struct ieee80211_hw
*hw
, enum set_key_cmd cmd
,
2709 const u8
*local_addr
, const u8
*addr
,
2710 struct ieee80211_key_conf
*key
)
2712 struct ath5k_softc
*sc
= hw
->priv
;
2726 mutex_lock(&sc
->lock
);
2730 ret
= ath5k_hw_set_key(sc
->ah
, key
->keyidx
, key
, addr
);
2732 ATH5K_ERR(sc
, "can't set the key\n");
2735 __set_bit(key
->keyidx
, sc
->keymap
);
2736 key
->hw_key_idx
= key
->keyidx
;
2739 ath5k_hw_reset_key(sc
->ah
, key
->keyidx
);
2740 __clear_bit(key
->keyidx
, sc
->keymap
);
2748 mutex_unlock(&sc
->lock
);
2753 ath5k_get_stats(struct ieee80211_hw
*hw
,
2754 struct ieee80211_low_level_stats
*stats
)
2756 struct ath5k_softc
*sc
= hw
->priv
;
2758 memcpy(stats
, &sc
->ll_stats
, sizeof(sc
->ll_stats
));
2764 ath5k_get_tx_stats(struct ieee80211_hw
*hw
,
2765 struct ieee80211_tx_queue_stats
*stats
)
2767 struct ath5k_softc
*sc
= hw
->priv
;
2769 memcpy(stats
, &sc
->tx_stats
, sizeof(sc
->tx_stats
));
2775 ath5k_get_tsf(struct ieee80211_hw
*hw
)
2777 struct ath5k_softc
*sc
= hw
->priv
;
2779 return ath5k_hw_get_tsf64(sc
->ah
);
2783 ath5k_reset_tsf(struct ieee80211_hw
*hw
)
2785 struct ath5k_softc
*sc
= hw
->priv
;
2787 ath5k_hw_reset_tsf(sc
->ah
);
2791 ath5k_beacon_update(struct ieee80211_hw
*hw
, struct sk_buff
*skb
,
2792 struct ieee80211_tx_control
*ctl
)
2794 struct ath5k_softc
*sc
= hw
->priv
;
2797 ath5k_debug_dump_skb(sc
, skb
, "BC ", 1);
2799 mutex_lock(&sc
->lock
);
2801 if (sc
->opmode
!= IEEE80211_IF_TYPE_IBSS
) {
2806 ath5k_txbuf_free(sc
, sc
->bbuf
);
2807 sc
->bbuf
->skb
= skb
;
2808 ret
= ath5k_beacon_setup(sc
, sc
->bbuf
, ctl
);
2810 sc
->bbuf
->skb
= NULL
;
2812 ath5k_beacon_config(sc
);
2815 mutex_unlock(&sc
->lock
);