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mac80211: introduce hw config change flags
[deliverable/linux.git] / drivers / net / wireless / ath5k / base.c
1 /*-
2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
7 *
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
23 *
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
27 *
28 * NO WARRANTY
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
40 *
41 */
42
43 #include <linux/module.h>
44 #include <linux/delay.h>
45 #include <linux/hardirq.h>
46 #include <linux/if.h>
47 #include <linux/io.h>
48 #include <linux/netdevice.h>
49 #include <linux/cache.h>
50 #include <linux/pci.h>
51 #include <linux/ethtool.h>
52 #include <linux/uaccess.h>
53
54 #include <net/ieee80211_radiotap.h>
55
56 #include <asm/unaligned.h>
57
58 #include "base.h"
59 #include "reg.h"
60 #include "debug.h"
61
62 static int ath5k_calinterval = 10; /* Calibrate PHY every 10 secs (TODO: Fixme) */
63
64
65 /******************\
66 * Internal defines *
67 \******************/
68
69 /* Module info */
70 MODULE_AUTHOR("Jiri Slaby");
71 MODULE_AUTHOR("Nick Kossifidis");
72 MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
73 MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
74 MODULE_LICENSE("Dual BSD/GPL");
75 MODULE_VERSION("0.6.0 (EXPERIMENTAL)");
76
77
78 /* Known PCI ids */
79 static struct pci_device_id ath5k_pci_id_table[] __devinitdata = {
80 { PCI_VDEVICE(ATHEROS, 0x0207), .driver_data = AR5K_AR5210 }, /* 5210 early */
81 { PCI_VDEVICE(ATHEROS, 0x0007), .driver_data = AR5K_AR5210 }, /* 5210 */
82 { PCI_VDEVICE(ATHEROS, 0x0011), .driver_data = AR5K_AR5211 }, /* 5311 - this is on AHB bus !*/
83 { PCI_VDEVICE(ATHEROS, 0x0012), .driver_data = AR5K_AR5211 }, /* 5211 */
84 { PCI_VDEVICE(ATHEROS, 0x0013), .driver_data = AR5K_AR5212 }, /* 5212 */
85 { PCI_VDEVICE(3COM_2, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 5212 */
86 { PCI_VDEVICE(3COM, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 3CRDAG675 5212 */
87 { PCI_VDEVICE(ATHEROS, 0x1014), .driver_data = AR5K_AR5212 }, /* IBM minipci 5212 */
88 { PCI_VDEVICE(ATHEROS, 0x0014), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
89 { PCI_VDEVICE(ATHEROS, 0x0015), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
90 { PCI_VDEVICE(ATHEROS, 0x0016), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
91 { PCI_VDEVICE(ATHEROS, 0x0017), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
92 { PCI_VDEVICE(ATHEROS, 0x0018), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
93 { PCI_VDEVICE(ATHEROS, 0x0019), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
94 { PCI_VDEVICE(ATHEROS, 0x001a), .driver_data = AR5K_AR5212 }, /* 2413 Griffin-lite */
95 { PCI_VDEVICE(ATHEROS, 0x001b), .driver_data = AR5K_AR5212 }, /* 5413 Eagle */
96 { PCI_VDEVICE(ATHEROS, 0x001c), .driver_data = AR5K_AR5212 }, /* PCI-E cards */
97 { PCI_VDEVICE(ATHEROS, 0x001d), .driver_data = AR5K_AR5212 }, /* 2417 Nala */
98 { 0 }
99 };
100 MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table);
101
102 /* Known SREVs */
103 static struct ath5k_srev_name srev_names[] = {
104 { "5210", AR5K_VERSION_MAC, AR5K_SREV_AR5210 },
105 { "5311", AR5K_VERSION_MAC, AR5K_SREV_AR5311 },
106 { "5311A", AR5K_VERSION_MAC, AR5K_SREV_AR5311A },
107 { "5311B", AR5K_VERSION_MAC, AR5K_SREV_AR5311B },
108 { "5211", AR5K_VERSION_MAC, AR5K_SREV_AR5211 },
109 { "5212", AR5K_VERSION_MAC, AR5K_SREV_AR5212 },
110 { "5213", AR5K_VERSION_MAC, AR5K_SREV_AR5213 },
111 { "5213A", AR5K_VERSION_MAC, AR5K_SREV_AR5213A },
112 { "2413", AR5K_VERSION_MAC, AR5K_SREV_AR2413 },
113 { "2414", AR5K_VERSION_MAC, AR5K_SREV_AR2414 },
114 { "5424", AR5K_VERSION_MAC, AR5K_SREV_AR5424 },
115 { "5413", AR5K_VERSION_MAC, AR5K_SREV_AR5413 },
116 { "5414", AR5K_VERSION_MAC, AR5K_SREV_AR5414 },
117 { "2415", AR5K_VERSION_MAC, AR5K_SREV_AR2415 },
118 { "5416", AR5K_VERSION_MAC, AR5K_SREV_AR5416 },
119 { "5418", AR5K_VERSION_MAC, AR5K_SREV_AR5418 },
120 { "2425", AR5K_VERSION_MAC, AR5K_SREV_AR2425 },
121 { "2417", AR5K_VERSION_MAC, AR5K_SREV_AR2417 },
122 { "xxxxx", AR5K_VERSION_MAC, AR5K_SREV_UNKNOWN },
123 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
124 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
125 { "5111A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111A },
126 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
127 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
128 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
129 { "5112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112B },
130 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
131 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
132 { "2112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112B },
133 { "2413", AR5K_VERSION_RAD, AR5K_SREV_RAD_2413 },
134 { "5413", AR5K_VERSION_RAD, AR5K_SREV_RAD_5413 },
135 { "2316", AR5K_VERSION_RAD, AR5K_SREV_RAD_2316 },
136 { "2317", AR5K_VERSION_RAD, AR5K_SREV_RAD_2317 },
137 { "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_5424 },
138 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
139 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
140 };
141
142 static struct ieee80211_rate ath5k_rates[] = {
143 { .bitrate = 10,
144 .hw_value = ATH5K_RATE_CODE_1M, },
145 { .bitrate = 20,
146 .hw_value = ATH5K_RATE_CODE_2M,
147 .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE,
148 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
149 { .bitrate = 55,
150 .hw_value = ATH5K_RATE_CODE_5_5M,
151 .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE,
152 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
153 { .bitrate = 110,
154 .hw_value = ATH5K_RATE_CODE_11M,
155 .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE,
156 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
157 { .bitrate = 60,
158 .hw_value = ATH5K_RATE_CODE_6M,
159 .flags = 0 },
160 { .bitrate = 90,
161 .hw_value = ATH5K_RATE_CODE_9M,
162 .flags = 0 },
163 { .bitrate = 120,
164 .hw_value = ATH5K_RATE_CODE_12M,
165 .flags = 0 },
166 { .bitrate = 180,
167 .hw_value = ATH5K_RATE_CODE_18M,
168 .flags = 0 },
169 { .bitrate = 240,
170 .hw_value = ATH5K_RATE_CODE_24M,
171 .flags = 0 },
172 { .bitrate = 360,
173 .hw_value = ATH5K_RATE_CODE_36M,
174 .flags = 0 },
175 { .bitrate = 480,
176 .hw_value = ATH5K_RATE_CODE_48M,
177 .flags = 0 },
178 { .bitrate = 540,
179 .hw_value = ATH5K_RATE_CODE_54M,
180 .flags = 0 },
181 /* XR missing */
182 };
183
184 /*
185 * Prototypes - PCI stack related functions
186 */
187 static int __devinit ath5k_pci_probe(struct pci_dev *pdev,
188 const struct pci_device_id *id);
189 static void __devexit ath5k_pci_remove(struct pci_dev *pdev);
190 #ifdef CONFIG_PM
191 static int ath5k_pci_suspend(struct pci_dev *pdev,
192 pm_message_t state);
193 static int ath5k_pci_resume(struct pci_dev *pdev);
194 #else
195 #define ath5k_pci_suspend NULL
196 #define ath5k_pci_resume NULL
197 #endif /* CONFIG_PM */
198
199 static struct pci_driver ath5k_pci_driver = {
200 .name = "ath5k_pci",
201 .id_table = ath5k_pci_id_table,
202 .probe = ath5k_pci_probe,
203 .remove = __devexit_p(ath5k_pci_remove),
204 .suspend = ath5k_pci_suspend,
205 .resume = ath5k_pci_resume,
206 };
207
208
209
210 /*
211 * Prototypes - MAC 802.11 stack related functions
212 */
213 static int ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb);
214 static int ath5k_reset(struct ath5k_softc *sc, bool stop, bool change_channel);
215 static int ath5k_reset_wake(struct ath5k_softc *sc);
216 static int ath5k_start(struct ieee80211_hw *hw);
217 static void ath5k_stop(struct ieee80211_hw *hw);
218 static int ath5k_add_interface(struct ieee80211_hw *hw,
219 struct ieee80211_if_init_conf *conf);
220 static void ath5k_remove_interface(struct ieee80211_hw *hw,
221 struct ieee80211_if_init_conf *conf);
222 static int ath5k_config(struct ieee80211_hw *hw, u32 changed);
223 static int ath5k_config_interface(struct ieee80211_hw *hw,
224 struct ieee80211_vif *vif,
225 struct ieee80211_if_conf *conf);
226 static void ath5k_configure_filter(struct ieee80211_hw *hw,
227 unsigned int changed_flags,
228 unsigned int *new_flags,
229 int mc_count, struct dev_mc_list *mclist);
230 static int ath5k_set_key(struct ieee80211_hw *hw,
231 enum set_key_cmd cmd,
232 const u8 *local_addr, const u8 *addr,
233 struct ieee80211_key_conf *key);
234 static int ath5k_get_stats(struct ieee80211_hw *hw,
235 struct ieee80211_low_level_stats *stats);
236 static int ath5k_get_tx_stats(struct ieee80211_hw *hw,
237 struct ieee80211_tx_queue_stats *stats);
238 static u64 ath5k_get_tsf(struct ieee80211_hw *hw);
239 static void ath5k_reset_tsf(struct ieee80211_hw *hw);
240 static int ath5k_beacon_update(struct ieee80211_hw *hw,
241 struct sk_buff *skb);
242
243 static struct ieee80211_ops ath5k_hw_ops = {
244 .tx = ath5k_tx,
245 .start = ath5k_start,
246 .stop = ath5k_stop,
247 .add_interface = ath5k_add_interface,
248 .remove_interface = ath5k_remove_interface,
249 .config = ath5k_config,
250 .config_interface = ath5k_config_interface,
251 .configure_filter = ath5k_configure_filter,
252 .set_key = ath5k_set_key,
253 .get_stats = ath5k_get_stats,
254 .conf_tx = NULL,
255 .get_tx_stats = ath5k_get_tx_stats,
256 .get_tsf = ath5k_get_tsf,
257 .reset_tsf = ath5k_reset_tsf,
258 };
259
260 /*
261 * Prototypes - Internal functions
262 */
263 /* Attach detach */
264 static int ath5k_attach(struct pci_dev *pdev,
265 struct ieee80211_hw *hw);
266 static void ath5k_detach(struct pci_dev *pdev,
267 struct ieee80211_hw *hw);
268 /* Channel/mode setup */
269 static inline short ath5k_ieee2mhz(short chan);
270 static unsigned int ath5k_copy_channels(struct ath5k_hw *ah,
271 struct ieee80211_channel *channels,
272 unsigned int mode,
273 unsigned int max);
274 static int ath5k_setup_bands(struct ieee80211_hw *hw);
275 static int ath5k_chan_set(struct ath5k_softc *sc,
276 struct ieee80211_channel *chan);
277 static void ath5k_setcurmode(struct ath5k_softc *sc,
278 unsigned int mode);
279 static void ath5k_mode_setup(struct ath5k_softc *sc);
280
281 /* Descriptor setup */
282 static int ath5k_desc_alloc(struct ath5k_softc *sc,
283 struct pci_dev *pdev);
284 static void ath5k_desc_free(struct ath5k_softc *sc,
285 struct pci_dev *pdev);
286 /* Buffers setup */
287 static int ath5k_rxbuf_setup(struct ath5k_softc *sc,
288 struct ath5k_buf *bf);
289 static int ath5k_txbuf_setup(struct ath5k_softc *sc,
290 struct ath5k_buf *bf);
291 static inline void ath5k_txbuf_free(struct ath5k_softc *sc,
292 struct ath5k_buf *bf)
293 {
294 BUG_ON(!bf);
295 if (!bf->skb)
296 return;
297 pci_unmap_single(sc->pdev, bf->skbaddr, bf->skb->len,
298 PCI_DMA_TODEVICE);
299 dev_kfree_skb_any(bf->skb);
300 bf->skb = NULL;
301 }
302
303 /* Queues setup */
304 static struct ath5k_txq *ath5k_txq_setup(struct ath5k_softc *sc,
305 int qtype, int subtype);
306 static int ath5k_beaconq_setup(struct ath5k_hw *ah);
307 static int ath5k_beaconq_config(struct ath5k_softc *sc);
308 static void ath5k_txq_drainq(struct ath5k_softc *sc,
309 struct ath5k_txq *txq);
310 static void ath5k_txq_cleanup(struct ath5k_softc *sc);
311 static void ath5k_txq_release(struct ath5k_softc *sc);
312 /* Rx handling */
313 static int ath5k_rx_start(struct ath5k_softc *sc);
314 static void ath5k_rx_stop(struct ath5k_softc *sc);
315 static unsigned int ath5k_rx_decrypted(struct ath5k_softc *sc,
316 struct ath5k_desc *ds,
317 struct sk_buff *skb,
318 struct ath5k_rx_status *rs);
319 static void ath5k_tasklet_rx(unsigned long data);
320 /* Tx handling */
321 static void ath5k_tx_processq(struct ath5k_softc *sc,
322 struct ath5k_txq *txq);
323 static void ath5k_tasklet_tx(unsigned long data);
324 /* Beacon handling */
325 static int ath5k_beacon_setup(struct ath5k_softc *sc,
326 struct ath5k_buf *bf);
327 static void ath5k_beacon_send(struct ath5k_softc *sc);
328 static void ath5k_beacon_config(struct ath5k_softc *sc);
329 static void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf);
330
331 static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
332 {
333 u64 tsf = ath5k_hw_get_tsf64(ah);
334
335 if ((tsf & 0x7fff) < rstamp)
336 tsf -= 0x8000;
337
338 return (tsf & ~0x7fff) | rstamp;
339 }
340
341 /* Interrupt handling */
342 static int ath5k_init(struct ath5k_softc *sc, bool is_resume);
343 static int ath5k_stop_locked(struct ath5k_softc *sc);
344 static int ath5k_stop_hw(struct ath5k_softc *sc, bool is_suspend);
345 static irqreturn_t ath5k_intr(int irq, void *dev_id);
346 static void ath5k_tasklet_reset(unsigned long data);
347
348 static void ath5k_calibrate(unsigned long data);
349 /* LED functions */
350 static int ath5k_init_leds(struct ath5k_softc *sc);
351 static void ath5k_led_enable(struct ath5k_softc *sc);
352 static void ath5k_led_off(struct ath5k_softc *sc);
353 static void ath5k_unregister_leds(struct ath5k_softc *sc);
354
355 /*
356 * Module init/exit functions
357 */
358 static int __init
359 init_ath5k_pci(void)
360 {
361 int ret;
362
363 ath5k_debug_init();
364
365 ret = pci_register_driver(&ath5k_pci_driver);
366 if (ret) {
367 printk(KERN_ERR "ath5k_pci: can't register pci driver\n");
368 return ret;
369 }
370
371 return 0;
372 }
373
374 static void __exit
375 exit_ath5k_pci(void)
376 {
377 pci_unregister_driver(&ath5k_pci_driver);
378
379 ath5k_debug_finish();
380 }
381
382 module_init(init_ath5k_pci);
383 module_exit(exit_ath5k_pci);
384
385
386 /********************\
387 * PCI Initialization *
388 \********************/
389
390 static const char *
391 ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
392 {
393 const char *name = "xxxxx";
394 unsigned int i;
395
396 for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
397 if (srev_names[i].sr_type != type)
398 continue;
399
400 if ((val & 0xf0) == srev_names[i].sr_val)
401 name = srev_names[i].sr_name;
402
403 if ((val & 0xff) == srev_names[i].sr_val) {
404 name = srev_names[i].sr_name;
405 break;
406 }
407 }
408
409 return name;
410 }
411
412 static int __devinit
413 ath5k_pci_probe(struct pci_dev *pdev,
414 const struct pci_device_id *id)
415 {
416 void __iomem *mem;
417 struct ath5k_softc *sc;
418 struct ieee80211_hw *hw;
419 int ret;
420 u8 csz;
421
422 ret = pci_enable_device(pdev);
423 if (ret) {
424 dev_err(&pdev->dev, "can't enable device\n");
425 goto err;
426 }
427
428 /* XXX 32-bit addressing only */
429 ret = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
430 if (ret) {
431 dev_err(&pdev->dev, "32-bit DMA not available\n");
432 goto err_dis;
433 }
434
435 /*
436 * Cache line size is used to size and align various
437 * structures used to communicate with the hardware.
438 */
439 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
440 if (csz == 0) {
441 /*
442 * Linux 2.4.18 (at least) writes the cache line size
443 * register as a 16-bit wide register which is wrong.
444 * We must have this setup properly for rx buffer
445 * DMA to work so force a reasonable value here if it
446 * comes up zero.
447 */
448 csz = L1_CACHE_BYTES / sizeof(u32);
449 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
450 }
451 /*
452 * The default setting of latency timer yields poor results,
453 * set it to the value used by other systems. It may be worth
454 * tweaking this setting more.
455 */
456 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
457
458 /* Enable bus mastering */
459 pci_set_master(pdev);
460
461 /*
462 * Disable the RETRY_TIMEOUT register (0x41) to keep
463 * PCI Tx retries from interfering with C3 CPU state.
464 */
465 pci_write_config_byte(pdev, 0x41, 0);
466
467 ret = pci_request_region(pdev, 0, "ath5k");
468 if (ret) {
469 dev_err(&pdev->dev, "cannot reserve PCI memory region\n");
470 goto err_dis;
471 }
472
473 mem = pci_iomap(pdev, 0, 0);
474 if (!mem) {
475 dev_err(&pdev->dev, "cannot remap PCI memory region\n") ;
476 ret = -EIO;
477 goto err_reg;
478 }
479
480 /*
481 * Allocate hw (mac80211 main struct)
482 * and hw->priv (driver private data)
483 */
484 hw = ieee80211_alloc_hw(sizeof(*sc), &ath5k_hw_ops);
485 if (hw == NULL) {
486 dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n");
487 ret = -ENOMEM;
488 goto err_map;
489 }
490
491 dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy));
492
493 /* Initialize driver private data */
494 SET_IEEE80211_DEV(hw, &pdev->dev);
495 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
496 IEEE80211_HW_SIGNAL_DBM |
497 IEEE80211_HW_NOISE_DBM;
498
499 hw->wiphy->interface_modes =
500 BIT(NL80211_IFTYPE_STATION) |
501 BIT(NL80211_IFTYPE_ADHOC) |
502 BIT(NL80211_IFTYPE_MESH_POINT);
503
504 hw->extra_tx_headroom = 2;
505 hw->channel_change_time = 5000;
506 sc = hw->priv;
507 sc->hw = hw;
508 sc->pdev = pdev;
509
510 ath5k_debug_init_device(sc);
511
512 /*
513 * Mark the device as detached to avoid processing
514 * interrupts until setup is complete.
515 */
516 __set_bit(ATH_STAT_INVALID, sc->status);
517
518 sc->iobase = mem; /* So we can unmap it on detach */
519 sc->cachelsz = csz * sizeof(u32); /* convert to bytes */
520 sc->opmode = NL80211_IFTYPE_STATION;
521 mutex_init(&sc->lock);
522 spin_lock_init(&sc->rxbuflock);
523 spin_lock_init(&sc->txbuflock);
524 spin_lock_init(&sc->block);
525
526 /* Set private data */
527 pci_set_drvdata(pdev, hw);
528
529 /* Setup interrupt handler */
530 ret = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
531 if (ret) {
532 ATH5K_ERR(sc, "request_irq failed\n");
533 goto err_free;
534 }
535
536 /* Initialize device */
537 sc->ah = ath5k_hw_attach(sc, id->driver_data);
538 if (IS_ERR(sc->ah)) {
539 ret = PTR_ERR(sc->ah);
540 goto err_irq;
541 }
542
543 /* set up multi-rate retry capabilities */
544 if (sc->ah->ah_version == AR5K_AR5212) {
545 hw->max_altrates = 3;
546 hw->max_altrate_tries = 11;
547 }
548
549 /* Finish private driver data initialization */
550 ret = ath5k_attach(pdev, hw);
551 if (ret)
552 goto err_ah;
553
554 ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
555 ath5k_chip_name(AR5K_VERSION_MAC, sc->ah->ah_mac_srev),
556 sc->ah->ah_mac_srev,
557 sc->ah->ah_phy_revision);
558
559 if (!sc->ah->ah_single_chip) {
560 /* Single chip radio (!RF5111) */
561 if (sc->ah->ah_radio_5ghz_revision &&
562 !sc->ah->ah_radio_2ghz_revision) {
563 /* No 5GHz support -> report 2GHz radio */
564 if (!test_bit(AR5K_MODE_11A,
565 sc->ah->ah_capabilities.cap_mode)) {
566 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
567 ath5k_chip_name(AR5K_VERSION_RAD,
568 sc->ah->ah_radio_5ghz_revision),
569 sc->ah->ah_radio_5ghz_revision);
570 /* No 2GHz support (5110 and some
571 * 5Ghz only cards) -> report 5Ghz radio */
572 } else if (!test_bit(AR5K_MODE_11B,
573 sc->ah->ah_capabilities.cap_mode)) {
574 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
575 ath5k_chip_name(AR5K_VERSION_RAD,
576 sc->ah->ah_radio_5ghz_revision),
577 sc->ah->ah_radio_5ghz_revision);
578 /* Multiband radio */
579 } else {
580 ATH5K_INFO(sc, "RF%s multiband radio found"
581 " (0x%x)\n",
582 ath5k_chip_name(AR5K_VERSION_RAD,
583 sc->ah->ah_radio_5ghz_revision),
584 sc->ah->ah_radio_5ghz_revision);
585 }
586 }
587 /* Multi chip radio (RF5111 - RF2111) ->
588 * report both 2GHz/5GHz radios */
589 else if (sc->ah->ah_radio_5ghz_revision &&
590 sc->ah->ah_radio_2ghz_revision){
591 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
592 ath5k_chip_name(AR5K_VERSION_RAD,
593 sc->ah->ah_radio_5ghz_revision),
594 sc->ah->ah_radio_5ghz_revision);
595 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
596 ath5k_chip_name(AR5K_VERSION_RAD,
597 sc->ah->ah_radio_2ghz_revision),
598 sc->ah->ah_radio_2ghz_revision);
599 }
600 }
601
602
603 /* ready to process interrupts */
604 __clear_bit(ATH_STAT_INVALID, sc->status);
605
606 return 0;
607 err_ah:
608 ath5k_hw_detach(sc->ah);
609 err_irq:
610 free_irq(pdev->irq, sc);
611 err_free:
612 ieee80211_free_hw(hw);
613 err_map:
614 pci_iounmap(pdev, mem);
615 err_reg:
616 pci_release_region(pdev, 0);
617 err_dis:
618 pci_disable_device(pdev);
619 err:
620 return ret;
621 }
622
623 static void __devexit
624 ath5k_pci_remove(struct pci_dev *pdev)
625 {
626 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
627 struct ath5k_softc *sc = hw->priv;
628
629 ath5k_debug_finish_device(sc);
630 ath5k_detach(pdev, hw);
631 ath5k_hw_detach(sc->ah);
632 free_irq(pdev->irq, sc);
633 pci_iounmap(pdev, sc->iobase);
634 pci_release_region(pdev, 0);
635 pci_disable_device(pdev);
636 ieee80211_free_hw(hw);
637 }
638
639 #ifdef CONFIG_PM
640 static int
641 ath5k_pci_suspend(struct pci_dev *pdev, pm_message_t state)
642 {
643 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
644 struct ath5k_softc *sc = hw->priv;
645
646 ath5k_led_off(sc);
647
648 ath5k_stop_hw(sc, true);
649
650 free_irq(pdev->irq, sc);
651 pci_save_state(pdev);
652 pci_disable_device(pdev);
653 pci_set_power_state(pdev, PCI_D3hot);
654
655 return 0;
656 }
657
658 static int
659 ath5k_pci_resume(struct pci_dev *pdev)
660 {
661 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
662 struct ath5k_softc *sc = hw->priv;
663 int err;
664
665 pci_restore_state(pdev);
666
667 err = pci_enable_device(pdev);
668 if (err)
669 return err;
670
671 /*
672 * Suspend/Resume resets the PCI configuration space, so we have to
673 * re-disable the RETRY_TIMEOUT register (0x41) to keep
674 * PCI Tx retries from interfering with C3 CPU state
675 */
676 pci_write_config_byte(pdev, 0x41, 0);
677
678 err = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
679 if (err) {
680 ATH5K_ERR(sc, "request_irq failed\n");
681 goto err_no_irq;
682 }
683
684 err = ath5k_init(sc, true);
685 if (err)
686 goto err_irq;
687 ath5k_led_enable(sc);
688
689 return 0;
690 err_irq:
691 free_irq(pdev->irq, sc);
692 err_no_irq:
693 pci_disable_device(pdev);
694 return err;
695 }
696 #endif /* CONFIG_PM */
697
698
699 /***********************\
700 * Driver Initialization *
701 \***********************/
702
703 static int
704 ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw)
705 {
706 struct ath5k_softc *sc = hw->priv;
707 struct ath5k_hw *ah = sc->ah;
708 u8 mac[ETH_ALEN];
709 int ret;
710
711 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "devid 0x%x\n", pdev->device);
712
713 /*
714 * Check if the MAC has multi-rate retry support.
715 * We do this by trying to setup a fake extended
716 * descriptor. MAC's that don't have support will
717 * return false w/o doing anything. MAC's that do
718 * support it will return true w/o doing anything.
719 */
720 ret = ah->ah_setup_mrr_tx_desc(ah, NULL, 0, 0, 0, 0, 0, 0);
721 if (ret < 0)
722 goto err;
723 if (ret > 0)
724 __set_bit(ATH_STAT_MRRETRY, sc->status);
725
726 /*
727 * Collect the channel list. The 802.11 layer
728 * is resposible for filtering this list based
729 * on settings like the phy mode and regulatory
730 * domain restrictions.
731 */
732 ret = ath5k_setup_bands(hw);
733 if (ret) {
734 ATH5K_ERR(sc, "can't get channels\n");
735 goto err;
736 }
737
738 /* NB: setup here so ath5k_rate_update is happy */
739 if (test_bit(AR5K_MODE_11A, ah->ah_modes))
740 ath5k_setcurmode(sc, AR5K_MODE_11A);
741 else
742 ath5k_setcurmode(sc, AR5K_MODE_11B);
743
744 /*
745 * Allocate tx+rx descriptors and populate the lists.
746 */
747 ret = ath5k_desc_alloc(sc, pdev);
748 if (ret) {
749 ATH5K_ERR(sc, "can't allocate descriptors\n");
750 goto err;
751 }
752
753 /*
754 * Allocate hardware transmit queues: one queue for
755 * beacon frames and one data queue for each QoS
756 * priority. Note that hw functions handle reseting
757 * these queues at the needed time.
758 */
759 ret = ath5k_beaconq_setup(ah);
760 if (ret < 0) {
761 ATH5K_ERR(sc, "can't setup a beacon xmit queue\n");
762 goto err_desc;
763 }
764 sc->bhalq = ret;
765
766 sc->txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
767 if (IS_ERR(sc->txq)) {
768 ATH5K_ERR(sc, "can't setup xmit queue\n");
769 ret = PTR_ERR(sc->txq);
770 goto err_bhal;
771 }
772
773 tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
774 tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
775 tasklet_init(&sc->restq, ath5k_tasklet_reset, (unsigned long)sc);
776 setup_timer(&sc->calib_tim, ath5k_calibrate, (unsigned long)sc);
777
778 ath5k_hw_get_lladdr(ah, mac);
779 SET_IEEE80211_PERM_ADDR(hw, mac);
780 /* All MAC address bits matter for ACKs */
781 memset(sc->bssidmask, 0xff, ETH_ALEN);
782 ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
783
784 ret = ieee80211_register_hw(hw);
785 if (ret) {
786 ATH5K_ERR(sc, "can't register ieee80211 hw\n");
787 goto err_queues;
788 }
789
790 ath5k_init_leds(sc);
791
792 return 0;
793 err_queues:
794 ath5k_txq_release(sc);
795 err_bhal:
796 ath5k_hw_release_tx_queue(ah, sc->bhalq);
797 err_desc:
798 ath5k_desc_free(sc, pdev);
799 err:
800 return ret;
801 }
802
803 static void
804 ath5k_detach(struct pci_dev *pdev, struct ieee80211_hw *hw)
805 {
806 struct ath5k_softc *sc = hw->priv;
807
808 /*
809 * NB: the order of these is important:
810 * o call the 802.11 layer before detaching ath5k_hw to
811 * insure callbacks into the driver to delete global
812 * key cache entries can be handled
813 * o reclaim the tx queue data structures after calling
814 * the 802.11 layer as we'll get called back to reclaim
815 * node state and potentially want to use them
816 * o to cleanup the tx queues the hal is called, so detach
817 * it last
818 * XXX: ??? detach ath5k_hw ???
819 * Other than that, it's straightforward...
820 */
821 ieee80211_unregister_hw(hw);
822 ath5k_desc_free(sc, pdev);
823 ath5k_txq_release(sc);
824 ath5k_hw_release_tx_queue(sc->ah, sc->bhalq);
825 ath5k_unregister_leds(sc);
826
827 /*
828 * NB: can't reclaim these until after ieee80211_ifdetach
829 * returns because we'll get called back to reclaim node
830 * state and potentially want to use them.
831 */
832 }
833
834
835
836
837 /********************\
838 * Channel/mode setup *
839 \********************/
840
841 /*
842 * Convert IEEE channel number to MHz frequency.
843 */
844 static inline short
845 ath5k_ieee2mhz(short chan)
846 {
847 if (chan <= 14 || chan >= 27)
848 return ieee80211chan2mhz(chan);
849 else
850 return 2212 + chan * 20;
851 }
852
853 static unsigned int
854 ath5k_copy_channels(struct ath5k_hw *ah,
855 struct ieee80211_channel *channels,
856 unsigned int mode,
857 unsigned int max)
858 {
859 unsigned int i, count, size, chfreq, freq, ch;
860
861 if (!test_bit(mode, ah->ah_modes))
862 return 0;
863
864 switch (mode) {
865 case AR5K_MODE_11A:
866 case AR5K_MODE_11A_TURBO:
867 /* 1..220, but 2GHz frequencies are filtered by check_channel */
868 size = 220 ;
869 chfreq = CHANNEL_5GHZ;
870 break;
871 case AR5K_MODE_11B:
872 case AR5K_MODE_11G:
873 case AR5K_MODE_11G_TURBO:
874 size = 26;
875 chfreq = CHANNEL_2GHZ;
876 break;
877 default:
878 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n");
879 return 0;
880 }
881
882 for (i = 0, count = 0; i < size && max > 0; i++) {
883 ch = i + 1 ;
884 freq = ath5k_ieee2mhz(ch);
885
886 /* Check if channel is supported by the chipset */
887 if (!ath5k_channel_ok(ah, freq, chfreq))
888 continue;
889
890 /* Write channel info and increment counter */
891 channels[count].center_freq = freq;
892 channels[count].band = (chfreq == CHANNEL_2GHZ) ?
893 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
894 switch (mode) {
895 case AR5K_MODE_11A:
896 case AR5K_MODE_11G:
897 channels[count].hw_value = chfreq | CHANNEL_OFDM;
898 break;
899 case AR5K_MODE_11A_TURBO:
900 case AR5K_MODE_11G_TURBO:
901 channels[count].hw_value = chfreq |
902 CHANNEL_OFDM | CHANNEL_TURBO;
903 break;
904 case AR5K_MODE_11B:
905 channels[count].hw_value = CHANNEL_B;
906 }
907
908 count++;
909 max--;
910 }
911
912 return count;
913 }
914
915 static void
916 ath5k_setup_rate_idx(struct ath5k_softc *sc, struct ieee80211_supported_band *b)
917 {
918 u8 i;
919
920 for (i = 0; i < AR5K_MAX_RATES; i++)
921 sc->rate_idx[b->band][i] = -1;
922
923 for (i = 0; i < b->n_bitrates; i++) {
924 sc->rate_idx[b->band][b->bitrates[i].hw_value] = i;
925 if (b->bitrates[i].hw_value_short)
926 sc->rate_idx[b->band][b->bitrates[i].hw_value_short] = i;
927 }
928 }
929
930 static int
931 ath5k_setup_bands(struct ieee80211_hw *hw)
932 {
933 struct ath5k_softc *sc = hw->priv;
934 struct ath5k_hw *ah = sc->ah;
935 struct ieee80211_supported_band *sband;
936 int max_c, count_c = 0;
937 int i;
938
939 BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS);
940 max_c = ARRAY_SIZE(sc->channels);
941
942 /* 2GHz band */
943 sband = &sc->sbands[IEEE80211_BAND_2GHZ];
944 sband->band = IEEE80211_BAND_2GHZ;
945 sband->bitrates = &sc->rates[IEEE80211_BAND_2GHZ][0];
946
947 if (test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) {
948 /* G mode */
949 memcpy(sband->bitrates, &ath5k_rates[0],
950 sizeof(struct ieee80211_rate) * 12);
951 sband->n_bitrates = 12;
952
953 sband->channels = sc->channels;
954 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
955 AR5K_MODE_11G, max_c);
956
957 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
958 count_c = sband->n_channels;
959 max_c -= count_c;
960 } else if (test_bit(AR5K_MODE_11B, sc->ah->ah_capabilities.cap_mode)) {
961 /* B mode */
962 memcpy(sband->bitrates, &ath5k_rates[0],
963 sizeof(struct ieee80211_rate) * 4);
964 sband->n_bitrates = 4;
965
966 /* 5211 only supports B rates and uses 4bit rate codes
967 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
968 * fix them up here:
969 */
970 if (ah->ah_version == AR5K_AR5211) {
971 for (i = 0; i < 4; i++) {
972 sband->bitrates[i].hw_value =
973 sband->bitrates[i].hw_value & 0xF;
974 sband->bitrates[i].hw_value_short =
975 sband->bitrates[i].hw_value_short & 0xF;
976 }
977 }
978
979 sband->channels = sc->channels;
980 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
981 AR5K_MODE_11B, max_c);
982
983 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
984 count_c = sband->n_channels;
985 max_c -= count_c;
986 }
987 ath5k_setup_rate_idx(sc, sband);
988
989 /* 5GHz band, A mode */
990 if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) {
991 sband = &sc->sbands[IEEE80211_BAND_5GHZ];
992 sband->band = IEEE80211_BAND_5GHZ;
993 sband->bitrates = &sc->rates[IEEE80211_BAND_5GHZ][0];
994
995 memcpy(sband->bitrates, &ath5k_rates[4],
996 sizeof(struct ieee80211_rate) * 8);
997 sband->n_bitrates = 8;
998
999 sband->channels = &sc->channels[count_c];
1000 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1001 AR5K_MODE_11A, max_c);
1002
1003 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
1004 }
1005 ath5k_setup_rate_idx(sc, sband);
1006
1007 ath5k_debug_dump_bands(sc);
1008
1009 return 0;
1010 }
1011
1012 /*
1013 * Set/change channels. If the channel is really being changed,
1014 * it's done by reseting the chip. To accomplish this we must
1015 * first cleanup any pending DMA, then restart stuff after a la
1016 * ath5k_init.
1017 */
1018 static int
1019 ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
1020 {
1021 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "(%u MHz) -> (%u MHz)\n",
1022 sc->curchan->center_freq, chan->center_freq);
1023
1024 if (chan->center_freq != sc->curchan->center_freq ||
1025 chan->hw_value != sc->curchan->hw_value) {
1026
1027 sc->curchan = chan;
1028 sc->curband = &sc->sbands[chan->band];
1029
1030 /*
1031 * To switch channels clear any pending DMA operations;
1032 * wait long enough for the RX fifo to drain, reset the
1033 * hardware at the new frequency, and then re-enable
1034 * the relevant bits of the h/w.
1035 */
1036 return ath5k_reset(sc, true, true);
1037 }
1038
1039 return 0;
1040 }
1041
1042 static void
1043 ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode)
1044 {
1045 sc->curmode = mode;
1046
1047 if (mode == AR5K_MODE_11A) {
1048 sc->curband = &sc->sbands[IEEE80211_BAND_5GHZ];
1049 } else {
1050 sc->curband = &sc->sbands[IEEE80211_BAND_2GHZ];
1051 }
1052 }
1053
1054 static void
1055 ath5k_mode_setup(struct ath5k_softc *sc)
1056 {
1057 struct ath5k_hw *ah = sc->ah;
1058 u32 rfilt;
1059
1060 /* configure rx filter */
1061 rfilt = sc->filter_flags;
1062 ath5k_hw_set_rx_filter(ah, rfilt);
1063
1064 if (ath5k_hw_hasbssidmask(ah))
1065 ath5k_hw_set_bssid_mask(ah, sc->bssidmask);
1066
1067 /* configure operational mode */
1068 ath5k_hw_set_opmode(ah);
1069
1070 ath5k_hw_set_mcast_filter(ah, 0, 0);
1071 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
1072 }
1073
1074 static inline int
1075 ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix)
1076 {
1077 WARN_ON(hw_rix < 0 || hw_rix > AR5K_MAX_RATES);
1078 return sc->rate_idx[sc->curband->band][hw_rix];
1079 }
1080
1081 /***************\
1082 * Buffers setup *
1083 \***************/
1084
1085 static int
1086 ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1087 {
1088 struct ath5k_hw *ah = sc->ah;
1089 struct sk_buff *skb = bf->skb;
1090 struct ath5k_desc *ds;
1091
1092 if (likely(skb == NULL)) {
1093 unsigned int off;
1094
1095 /*
1096 * Allocate buffer with headroom_needed space for the
1097 * fake physical layer header at the start.
1098 */
1099 skb = dev_alloc_skb(sc->rxbufsize + sc->cachelsz - 1);
1100 if (unlikely(skb == NULL)) {
1101 ATH5K_ERR(sc, "can't alloc skbuff of size %u\n",
1102 sc->rxbufsize + sc->cachelsz - 1);
1103 return -ENOMEM;
1104 }
1105 /*
1106 * Cache-line-align. This is important (for the
1107 * 5210 at least) as not doing so causes bogus data
1108 * in rx'd frames.
1109 */
1110 off = ((unsigned long)skb->data) % sc->cachelsz;
1111 if (off != 0)
1112 skb_reserve(skb, sc->cachelsz - off);
1113
1114 bf->skb = skb;
1115 bf->skbaddr = pci_map_single(sc->pdev,
1116 skb->data, sc->rxbufsize, PCI_DMA_FROMDEVICE);
1117 if (unlikely(pci_dma_mapping_error(sc->pdev, bf->skbaddr))) {
1118 ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__);
1119 dev_kfree_skb(skb);
1120 bf->skb = NULL;
1121 return -ENOMEM;
1122 }
1123 }
1124
1125 /*
1126 * Setup descriptors. For receive we always terminate
1127 * the descriptor list with a self-linked entry so we'll
1128 * not get overrun under high load (as can happen with a
1129 * 5212 when ANI processing enables PHY error frames).
1130 *
1131 * To insure the last descriptor is self-linked we create
1132 * each descriptor as self-linked and add it to the end. As
1133 * each additional descriptor is added the previous self-linked
1134 * entry is ``fixed'' naturally. This should be safe even
1135 * if DMA is happening. When processing RX interrupts we
1136 * never remove/process the last, self-linked, entry on the
1137 * descriptor list. This insures the hardware always has
1138 * someplace to write a new frame.
1139 */
1140 ds = bf->desc;
1141 ds->ds_link = bf->daddr; /* link to self */
1142 ds->ds_data = bf->skbaddr;
1143 ah->ah_setup_rx_desc(ah, ds,
1144 skb_tailroom(skb), /* buffer size */
1145 0);
1146
1147 if (sc->rxlink != NULL)
1148 *sc->rxlink = bf->daddr;
1149 sc->rxlink = &ds->ds_link;
1150 return 0;
1151 }
1152
1153 static int
1154 ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1155 {
1156 struct ath5k_hw *ah = sc->ah;
1157 struct ath5k_txq *txq = sc->txq;
1158 struct ath5k_desc *ds = bf->desc;
1159 struct sk_buff *skb = bf->skb;
1160 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1161 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
1162 struct ieee80211_rate *rate;
1163 unsigned int mrr_rate[3], mrr_tries[3];
1164 int i, ret;
1165
1166 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
1167
1168 /* XXX endianness */
1169 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1170 PCI_DMA_TODEVICE);
1171
1172 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
1173 flags |= AR5K_TXDESC_NOACK;
1174
1175 pktlen = skb->len;
1176
1177 if (info->control.hw_key) {
1178 keyidx = info->control.hw_key->hw_key_idx;
1179 pktlen += info->control.hw_key->icv_len;
1180 }
1181 ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
1182 ieee80211_get_hdrlen_from_skb(skb), AR5K_PKT_TYPE_NORMAL,
1183 (sc->power_level * 2),
1184 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
1185 info->control.retry_limit, keyidx, 0, flags, 0, 0);
1186 if (ret)
1187 goto err_unmap;
1188
1189 memset(mrr_rate, 0, sizeof(mrr_rate));
1190 memset(mrr_tries, 0, sizeof(mrr_tries));
1191 for (i = 0; i < 3; i++) {
1192 rate = ieee80211_get_alt_retry_rate(sc->hw, info, i);
1193 if (!rate)
1194 break;
1195
1196 mrr_rate[i] = rate->hw_value;
1197 mrr_tries[i] = info->control.retries[i].limit;
1198 }
1199
1200 ah->ah_setup_mrr_tx_desc(ah, ds,
1201 mrr_rate[0], mrr_tries[0],
1202 mrr_rate[1], mrr_tries[1],
1203 mrr_rate[2], mrr_tries[2]);
1204
1205 ds->ds_link = 0;
1206 ds->ds_data = bf->skbaddr;
1207
1208 spin_lock_bh(&txq->lock);
1209 list_add_tail(&bf->list, &txq->q);
1210 sc->tx_stats[txq->qnum].len++;
1211 if (txq->link == NULL) /* is this first packet? */
1212 ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr);
1213 else /* no, so only link it */
1214 *txq->link = bf->daddr;
1215
1216 txq->link = &ds->ds_link;
1217 ath5k_hw_start_tx_dma(ah, txq->qnum);
1218 mmiowb();
1219 spin_unlock_bh(&txq->lock);
1220
1221 return 0;
1222 err_unmap:
1223 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1224 return ret;
1225 }
1226
1227 /*******************\
1228 * Descriptors setup *
1229 \*******************/
1230
1231 static int
1232 ath5k_desc_alloc(struct ath5k_softc *sc, struct pci_dev *pdev)
1233 {
1234 struct ath5k_desc *ds;
1235 struct ath5k_buf *bf;
1236 dma_addr_t da;
1237 unsigned int i;
1238 int ret;
1239
1240 /* allocate descriptors */
1241 sc->desc_len = sizeof(struct ath5k_desc) *
1242 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
1243 sc->desc = pci_alloc_consistent(pdev, sc->desc_len, &sc->desc_daddr);
1244 if (sc->desc == NULL) {
1245 ATH5K_ERR(sc, "can't allocate descriptors\n");
1246 ret = -ENOMEM;
1247 goto err;
1248 }
1249 ds = sc->desc;
1250 da = sc->desc_daddr;
1251 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
1252 ds, sc->desc_len, (unsigned long long)sc->desc_daddr);
1253
1254 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
1255 sizeof(struct ath5k_buf), GFP_KERNEL);
1256 if (bf == NULL) {
1257 ATH5K_ERR(sc, "can't allocate bufptr\n");
1258 ret = -ENOMEM;
1259 goto err_free;
1260 }
1261 sc->bufptr = bf;
1262
1263 INIT_LIST_HEAD(&sc->rxbuf);
1264 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
1265 bf->desc = ds;
1266 bf->daddr = da;
1267 list_add_tail(&bf->list, &sc->rxbuf);
1268 }
1269
1270 INIT_LIST_HEAD(&sc->txbuf);
1271 sc->txbuf_len = ATH_TXBUF;
1272 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++,
1273 da += sizeof(*ds)) {
1274 bf->desc = ds;
1275 bf->daddr = da;
1276 list_add_tail(&bf->list, &sc->txbuf);
1277 }
1278
1279 /* beacon buffer */
1280 bf->desc = ds;
1281 bf->daddr = da;
1282 sc->bbuf = bf;
1283
1284 return 0;
1285 err_free:
1286 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1287 err:
1288 sc->desc = NULL;
1289 return ret;
1290 }
1291
1292 static void
1293 ath5k_desc_free(struct ath5k_softc *sc, struct pci_dev *pdev)
1294 {
1295 struct ath5k_buf *bf;
1296
1297 ath5k_txbuf_free(sc, sc->bbuf);
1298 list_for_each_entry(bf, &sc->txbuf, list)
1299 ath5k_txbuf_free(sc, bf);
1300 list_for_each_entry(bf, &sc->rxbuf, list)
1301 ath5k_txbuf_free(sc, bf);
1302
1303 /* Free memory associated with all descriptors */
1304 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1305
1306 kfree(sc->bufptr);
1307 sc->bufptr = NULL;
1308 }
1309
1310
1311
1312
1313
1314 /**************\
1315 * Queues setup *
1316 \**************/
1317
1318 static struct ath5k_txq *
1319 ath5k_txq_setup(struct ath5k_softc *sc,
1320 int qtype, int subtype)
1321 {
1322 struct ath5k_hw *ah = sc->ah;
1323 struct ath5k_txq *txq;
1324 struct ath5k_txq_info qi = {
1325 .tqi_subtype = subtype,
1326 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1327 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1328 .tqi_cw_max = AR5K_TXQ_USEDEFAULT
1329 };
1330 int qnum;
1331
1332 /*
1333 * Enable interrupts only for EOL and DESC conditions.
1334 * We mark tx descriptors to receive a DESC interrupt
1335 * when a tx queue gets deep; otherwise waiting for the
1336 * EOL to reap descriptors. Note that this is done to
1337 * reduce interrupt load and this only defers reaping
1338 * descriptors, never transmitting frames. Aside from
1339 * reducing interrupts this also permits more concurrency.
1340 * The only potential downside is if the tx queue backs
1341 * up in which case the top half of the kernel may backup
1342 * due to a lack of tx descriptors.
1343 */
1344 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
1345 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
1346 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
1347 if (qnum < 0) {
1348 /*
1349 * NB: don't print a message, this happens
1350 * normally on parts with too few tx queues
1351 */
1352 return ERR_PTR(qnum);
1353 }
1354 if (qnum >= ARRAY_SIZE(sc->txqs)) {
1355 ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n",
1356 qnum, ARRAY_SIZE(sc->txqs));
1357 ath5k_hw_release_tx_queue(ah, qnum);
1358 return ERR_PTR(-EINVAL);
1359 }
1360 txq = &sc->txqs[qnum];
1361 if (!txq->setup) {
1362 txq->qnum = qnum;
1363 txq->link = NULL;
1364 INIT_LIST_HEAD(&txq->q);
1365 spin_lock_init(&txq->lock);
1366 txq->setup = true;
1367 }
1368 return &sc->txqs[qnum];
1369 }
1370
1371 static int
1372 ath5k_beaconq_setup(struct ath5k_hw *ah)
1373 {
1374 struct ath5k_txq_info qi = {
1375 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1376 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1377 .tqi_cw_max = AR5K_TXQ_USEDEFAULT,
1378 /* NB: for dynamic turbo, don't enable any other interrupts */
1379 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
1380 };
1381
1382 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
1383 }
1384
1385 static int
1386 ath5k_beaconq_config(struct ath5k_softc *sc)
1387 {
1388 struct ath5k_hw *ah = sc->ah;
1389 struct ath5k_txq_info qi;
1390 int ret;
1391
1392 ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi);
1393 if (ret)
1394 return ret;
1395 if (sc->opmode == NL80211_IFTYPE_AP ||
1396 sc->opmode == NL80211_IFTYPE_MESH_POINT) {
1397 /*
1398 * Always burst out beacon and CAB traffic
1399 * (aifs = cwmin = cwmax = 0)
1400 */
1401 qi.tqi_aifs = 0;
1402 qi.tqi_cw_min = 0;
1403 qi.tqi_cw_max = 0;
1404 } else if (sc->opmode == NL80211_IFTYPE_ADHOC) {
1405 /*
1406 * Adhoc mode; backoff between 0 and (2 * cw_min).
1407 */
1408 qi.tqi_aifs = 0;
1409 qi.tqi_cw_min = 0;
1410 qi.tqi_cw_max = 2 * ah->ah_cw_min;
1411 }
1412
1413 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1414 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1415 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
1416
1417 ret = ath5k_hw_set_tx_queueprops(ah, sc->bhalq, &qi);
1418 if (ret) {
1419 ATH5K_ERR(sc, "%s: unable to update parameters for beacon "
1420 "hardware queue!\n", __func__);
1421 return ret;
1422 }
1423
1424 return ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */;
1425 }
1426
1427 static void
1428 ath5k_txq_drainq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1429 {
1430 struct ath5k_buf *bf, *bf0;
1431
1432 /*
1433 * NB: this assumes output has been stopped and
1434 * we do not need to block ath5k_tx_tasklet
1435 */
1436 spin_lock_bh(&txq->lock);
1437 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1438 ath5k_debug_printtxbuf(sc, bf);
1439
1440 ath5k_txbuf_free(sc, bf);
1441
1442 spin_lock_bh(&sc->txbuflock);
1443 sc->tx_stats[txq->qnum].len--;
1444 list_move_tail(&bf->list, &sc->txbuf);
1445 sc->txbuf_len++;
1446 spin_unlock_bh(&sc->txbuflock);
1447 }
1448 txq->link = NULL;
1449 spin_unlock_bh(&txq->lock);
1450 }
1451
1452 /*
1453 * Drain the transmit queues and reclaim resources.
1454 */
1455 static void
1456 ath5k_txq_cleanup(struct ath5k_softc *sc)
1457 {
1458 struct ath5k_hw *ah = sc->ah;
1459 unsigned int i;
1460
1461 /* XXX return value */
1462 if (likely(!test_bit(ATH_STAT_INVALID, sc->status))) {
1463 /* don't touch the hardware if marked invalid */
1464 ath5k_hw_stop_tx_dma(ah, sc->bhalq);
1465 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "beacon queue %x\n",
1466 ath5k_hw_get_txdp(ah, sc->bhalq));
1467 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1468 if (sc->txqs[i].setup) {
1469 ath5k_hw_stop_tx_dma(ah, sc->txqs[i].qnum);
1470 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "txq [%u] %x, "
1471 "link %p\n",
1472 sc->txqs[i].qnum,
1473 ath5k_hw_get_txdp(ah,
1474 sc->txqs[i].qnum),
1475 sc->txqs[i].link);
1476 }
1477 }
1478 ieee80211_wake_queues(sc->hw); /* XXX move to callers */
1479
1480 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1481 if (sc->txqs[i].setup)
1482 ath5k_txq_drainq(sc, &sc->txqs[i]);
1483 }
1484
1485 static void
1486 ath5k_txq_release(struct ath5k_softc *sc)
1487 {
1488 struct ath5k_txq *txq = sc->txqs;
1489 unsigned int i;
1490
1491 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++)
1492 if (txq->setup) {
1493 ath5k_hw_release_tx_queue(sc->ah, txq->qnum);
1494 txq->setup = false;
1495 }
1496 }
1497
1498
1499
1500
1501 /*************\
1502 * RX Handling *
1503 \*************/
1504
1505 /*
1506 * Enable the receive h/w following a reset.
1507 */
1508 static int
1509 ath5k_rx_start(struct ath5k_softc *sc)
1510 {
1511 struct ath5k_hw *ah = sc->ah;
1512 struct ath5k_buf *bf;
1513 int ret;
1514
1515 sc->rxbufsize = roundup(IEEE80211_MAX_LEN, sc->cachelsz);
1516
1517 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rxbufsize %u\n",
1518 sc->cachelsz, sc->rxbufsize);
1519
1520 sc->rxlink = NULL;
1521
1522 spin_lock_bh(&sc->rxbuflock);
1523 list_for_each_entry(bf, &sc->rxbuf, list) {
1524 ret = ath5k_rxbuf_setup(sc, bf);
1525 if (ret != 0) {
1526 spin_unlock_bh(&sc->rxbuflock);
1527 goto err;
1528 }
1529 }
1530 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1531 spin_unlock_bh(&sc->rxbuflock);
1532
1533 ath5k_hw_set_rxdp(ah, bf->daddr);
1534 ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */
1535 ath5k_mode_setup(sc); /* set filters, etc. */
1536 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
1537
1538 return 0;
1539 err:
1540 return ret;
1541 }
1542
1543 /*
1544 * Disable the receive h/w in preparation for a reset.
1545 */
1546 static void
1547 ath5k_rx_stop(struct ath5k_softc *sc)
1548 {
1549 struct ath5k_hw *ah = sc->ah;
1550
1551 ath5k_hw_stop_rx_pcu(ah); /* disable PCU */
1552 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */
1553 ath5k_hw_stop_rx_dma(ah); /* disable DMA engine */
1554
1555 ath5k_debug_printrxbuffs(sc, ah);
1556
1557 sc->rxlink = NULL; /* just in case */
1558 }
1559
1560 static unsigned int
1561 ath5k_rx_decrypted(struct ath5k_softc *sc, struct ath5k_desc *ds,
1562 struct sk_buff *skb, struct ath5k_rx_status *rs)
1563 {
1564 struct ieee80211_hdr *hdr = (void *)skb->data;
1565 unsigned int keyix, hlen;
1566
1567 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1568 rs->rs_keyix != AR5K_RXKEYIX_INVALID)
1569 return RX_FLAG_DECRYPTED;
1570
1571 /* Apparently when a default key is used to decrypt the packet
1572 the hw does not set the index used to decrypt. In such cases
1573 get the index from the packet. */
1574 hlen = ieee80211_hdrlen(hdr->frame_control);
1575 if (ieee80211_has_protected(hdr->frame_control) &&
1576 !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1577 skb->len >= hlen + 4) {
1578 keyix = skb->data[hlen + 3] >> 6;
1579
1580 if (test_bit(keyix, sc->keymap))
1581 return RX_FLAG_DECRYPTED;
1582 }
1583
1584 return 0;
1585 }
1586
1587
1588 static void
1589 ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb,
1590 struct ieee80211_rx_status *rxs)
1591 {
1592 u64 tsf, bc_tstamp;
1593 u32 hw_tu;
1594 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1595
1596 if (ieee80211_is_beacon(mgmt->frame_control) &&
1597 le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS &&
1598 memcmp(mgmt->bssid, sc->ah->ah_bssid, ETH_ALEN) == 0) {
1599 /*
1600 * Received an IBSS beacon with the same BSSID. Hardware *must*
1601 * have updated the local TSF. We have to work around various
1602 * hardware bugs, though...
1603 */
1604 tsf = ath5k_hw_get_tsf64(sc->ah);
1605 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
1606 hw_tu = TSF_TO_TU(tsf);
1607
1608 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1609 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
1610 (unsigned long long)bc_tstamp,
1611 (unsigned long long)rxs->mactime,
1612 (unsigned long long)(rxs->mactime - bc_tstamp),
1613 (unsigned long long)tsf);
1614
1615 /*
1616 * Sometimes the HW will give us a wrong tstamp in the rx
1617 * status, causing the timestamp extension to go wrong.
1618 * (This seems to happen especially with beacon frames bigger
1619 * than 78 byte (incl. FCS))
1620 * But we know that the receive timestamp must be later than the
1621 * timestamp of the beacon since HW must have synced to that.
1622 *
1623 * NOTE: here we assume mactime to be after the frame was
1624 * received, not like mac80211 which defines it at the start.
1625 */
1626 if (bc_tstamp > rxs->mactime) {
1627 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1628 "fixing mactime from %llx to %llx\n",
1629 (unsigned long long)rxs->mactime,
1630 (unsigned long long)tsf);
1631 rxs->mactime = tsf;
1632 }
1633
1634 /*
1635 * Local TSF might have moved higher than our beacon timers,
1636 * in that case we have to update them to continue sending
1637 * beacons. This also takes care of synchronizing beacon sending
1638 * times with other stations.
1639 */
1640 if (hw_tu >= sc->nexttbtt)
1641 ath5k_beacon_update_timers(sc, bc_tstamp);
1642 }
1643 }
1644
1645
1646 static void
1647 ath5k_tasklet_rx(unsigned long data)
1648 {
1649 struct ieee80211_rx_status rxs = {};
1650 struct ath5k_rx_status rs = {};
1651 struct sk_buff *skb;
1652 struct ath5k_softc *sc = (void *)data;
1653 struct ath5k_buf *bf, *bf_last;
1654 struct ath5k_desc *ds;
1655 int ret;
1656 int hdrlen;
1657 int pad;
1658
1659 spin_lock(&sc->rxbuflock);
1660 if (list_empty(&sc->rxbuf)) {
1661 ATH5K_WARN(sc, "empty rx buf pool\n");
1662 goto unlock;
1663 }
1664 bf_last = list_entry(sc->rxbuf.prev, struct ath5k_buf, list);
1665 do {
1666 rxs.flag = 0;
1667
1668 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1669 BUG_ON(bf->skb == NULL);
1670 skb = bf->skb;
1671 ds = bf->desc;
1672
1673 /*
1674 * last buffer must not be freed to ensure proper hardware
1675 * function. When the hardware finishes also a packet next to
1676 * it, we are sure, it doesn't use it anymore and we can go on.
1677 */
1678 if (bf_last == bf)
1679 bf->flags |= 1;
1680 if (bf->flags) {
1681 struct ath5k_buf *bf_next = list_entry(bf->list.next,
1682 struct ath5k_buf, list);
1683 ret = sc->ah->ah_proc_rx_desc(sc->ah, bf_next->desc,
1684 &rs);
1685 if (ret)
1686 break;
1687 bf->flags &= ~1;
1688 /* skip the overwritten one (even status is martian) */
1689 goto next;
1690 }
1691
1692 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs);
1693 if (unlikely(ret == -EINPROGRESS))
1694 break;
1695 else if (unlikely(ret)) {
1696 ATH5K_ERR(sc, "error in processing rx descriptor\n");
1697 spin_unlock(&sc->rxbuflock);
1698 return;
1699 }
1700
1701 if (unlikely(rs.rs_more)) {
1702 ATH5K_WARN(sc, "unsupported jumbo\n");
1703 goto next;
1704 }
1705
1706 if (unlikely(rs.rs_status)) {
1707 if (rs.rs_status & AR5K_RXERR_PHY)
1708 goto next;
1709 if (rs.rs_status & AR5K_RXERR_DECRYPT) {
1710 /*
1711 * Decrypt error. If the error occurred
1712 * because there was no hardware key, then
1713 * let the frame through so the upper layers
1714 * can process it. This is necessary for 5210
1715 * parts which have no way to setup a ``clear''
1716 * key cache entry.
1717 *
1718 * XXX do key cache faulting
1719 */
1720 if (rs.rs_keyix == AR5K_RXKEYIX_INVALID &&
1721 !(rs.rs_status & AR5K_RXERR_CRC))
1722 goto accept;
1723 }
1724 if (rs.rs_status & AR5K_RXERR_MIC) {
1725 rxs.flag |= RX_FLAG_MMIC_ERROR;
1726 goto accept;
1727 }
1728
1729 /* let crypto-error packets fall through in MNTR */
1730 if ((rs.rs_status &
1731 ~(AR5K_RXERR_DECRYPT|AR5K_RXERR_MIC)) ||
1732 sc->opmode != NL80211_IFTYPE_MONITOR)
1733 goto next;
1734 }
1735 accept:
1736 pci_unmap_single(sc->pdev, bf->skbaddr, sc->rxbufsize,
1737 PCI_DMA_FROMDEVICE);
1738 bf->skb = NULL;
1739
1740 skb_put(skb, rs.rs_datalen);
1741
1742 /*
1743 * the hardware adds a padding to 4 byte boundaries between
1744 * the header and the payload data if the header length is
1745 * not multiples of 4 - remove it
1746 */
1747 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1748 if (hdrlen & 3) {
1749 pad = hdrlen % 4;
1750 memmove(skb->data + pad, skb->data, hdrlen);
1751 skb_pull(skb, pad);
1752 }
1753
1754 /*
1755 * always extend the mac timestamp, since this information is
1756 * also needed for proper IBSS merging.
1757 *
1758 * XXX: it might be too late to do it here, since rs_tstamp is
1759 * 15bit only. that means TSF extension has to be done within
1760 * 32768usec (about 32ms). it might be necessary to move this to
1761 * the interrupt handler, like it is done in madwifi.
1762 *
1763 * Unfortunately we don't know when the hardware takes the rx
1764 * timestamp (beginning of phy frame, data frame, end of rx?).
1765 * The only thing we know is that it is hardware specific...
1766 * On AR5213 it seems the rx timestamp is at the end of the
1767 * frame, but i'm not sure.
1768 *
1769 * NOTE: mac80211 defines mactime at the beginning of the first
1770 * data symbol. Since we don't have any time references it's
1771 * impossible to comply to that. This affects IBSS merge only
1772 * right now, so it's not too bad...
1773 */
1774 rxs.mactime = ath5k_extend_tsf(sc->ah, rs.rs_tstamp);
1775 rxs.flag |= RX_FLAG_TSFT;
1776
1777 rxs.freq = sc->curchan->center_freq;
1778 rxs.band = sc->curband->band;
1779
1780 rxs.noise = sc->ah->ah_noise_floor;
1781 rxs.signal = rxs.noise + rs.rs_rssi;
1782 rxs.qual = rs.rs_rssi * 100 / 64;
1783
1784 rxs.antenna = rs.rs_antenna;
1785 rxs.rate_idx = ath5k_hw_to_driver_rix(sc, rs.rs_rate);
1786 rxs.flag |= ath5k_rx_decrypted(sc, ds, skb, &rs);
1787
1788 if (rxs.rate_idx >= 0 && rs.rs_rate ==
1789 sc->curband->bitrates[rxs.rate_idx].hw_value_short)
1790 rxs.flag |= RX_FLAG_SHORTPRE;
1791
1792 ath5k_debug_dump_skb(sc, skb, "RX ", 0);
1793
1794 /* check beacons in IBSS mode */
1795 if (sc->opmode == NL80211_IFTYPE_ADHOC)
1796 ath5k_check_ibss_tsf(sc, skb, &rxs);
1797
1798 __ieee80211_rx(sc->hw, skb, &rxs);
1799 next:
1800 list_move_tail(&bf->list, &sc->rxbuf);
1801 } while (ath5k_rxbuf_setup(sc, bf) == 0);
1802 unlock:
1803 spin_unlock(&sc->rxbuflock);
1804 }
1805
1806
1807
1808
1809 /*************\
1810 * TX Handling *
1811 \*************/
1812
1813 static void
1814 ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1815 {
1816 struct ath5k_tx_status ts = {};
1817 struct ath5k_buf *bf, *bf0;
1818 struct ath5k_desc *ds;
1819 struct sk_buff *skb;
1820 struct ieee80211_tx_info *info;
1821 int i, ret;
1822
1823 spin_lock(&txq->lock);
1824 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1825 ds = bf->desc;
1826
1827 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts);
1828 if (unlikely(ret == -EINPROGRESS))
1829 break;
1830 else if (unlikely(ret)) {
1831 ATH5K_ERR(sc, "error %d while processing queue %u\n",
1832 ret, txq->qnum);
1833 break;
1834 }
1835
1836 skb = bf->skb;
1837 info = IEEE80211_SKB_CB(skb);
1838 bf->skb = NULL;
1839
1840 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len,
1841 PCI_DMA_TODEVICE);
1842
1843 memset(&info->status, 0, sizeof(info->status));
1844 info->tx_rate_idx = ath5k_hw_to_driver_rix(sc,
1845 ts.ts_rate[ts.ts_final_idx]);
1846 info->status.retry_count = ts.ts_longretry;
1847
1848 for (i = 0; i < 4; i++) {
1849 struct ieee80211_tx_altrate *r =
1850 &info->status.retries[i];
1851
1852 if (ts.ts_rate[i]) {
1853 r->rate_idx = ath5k_hw_to_driver_rix(sc, ts.ts_rate[i]);
1854 r->limit = ts.ts_retry[i];
1855 } else {
1856 r->rate_idx = -1;
1857 r->limit = 0;
1858 }
1859 }
1860
1861 info->status.excessive_retries = 0;
1862 if (unlikely(ts.ts_status)) {
1863 sc->ll_stats.dot11ACKFailureCount++;
1864 if (ts.ts_status & AR5K_TXERR_XRETRY)
1865 info->status.excessive_retries = 1;
1866 else if (ts.ts_status & AR5K_TXERR_FILT)
1867 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
1868 } else {
1869 info->flags |= IEEE80211_TX_STAT_ACK;
1870 info->status.ack_signal = ts.ts_rssi;
1871 }
1872
1873 ieee80211_tx_status(sc->hw, skb);
1874 sc->tx_stats[txq->qnum].count++;
1875
1876 spin_lock(&sc->txbuflock);
1877 sc->tx_stats[txq->qnum].len--;
1878 list_move_tail(&bf->list, &sc->txbuf);
1879 sc->txbuf_len++;
1880 spin_unlock(&sc->txbuflock);
1881 }
1882 if (likely(list_empty(&txq->q)))
1883 txq->link = NULL;
1884 spin_unlock(&txq->lock);
1885 if (sc->txbuf_len > ATH_TXBUF / 5)
1886 ieee80211_wake_queues(sc->hw);
1887 }
1888
1889 static void
1890 ath5k_tasklet_tx(unsigned long data)
1891 {
1892 struct ath5k_softc *sc = (void *)data;
1893
1894 ath5k_tx_processq(sc, sc->txq);
1895 }
1896
1897
1898 /*****************\
1899 * Beacon handling *
1900 \*****************/
1901
1902 /*
1903 * Setup the beacon frame for transmit.
1904 */
1905 static int
1906 ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1907 {
1908 struct sk_buff *skb = bf->skb;
1909 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1910 struct ath5k_hw *ah = sc->ah;
1911 struct ath5k_desc *ds;
1912 int ret, antenna = 0;
1913 u32 flags;
1914
1915 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1916 PCI_DMA_TODEVICE);
1917 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
1918 "skbaddr %llx\n", skb, skb->data, skb->len,
1919 (unsigned long long)bf->skbaddr);
1920 if (pci_dma_mapping_error(sc->pdev, bf->skbaddr)) {
1921 ATH5K_ERR(sc, "beacon DMA mapping failed\n");
1922 return -EIO;
1923 }
1924
1925 ds = bf->desc;
1926
1927 flags = AR5K_TXDESC_NOACK;
1928 if (sc->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) {
1929 ds->ds_link = bf->daddr; /* self-linked */
1930 flags |= AR5K_TXDESC_VEOL;
1931 /*
1932 * Let hardware handle antenna switching if txantenna is not set
1933 */
1934 } else {
1935 ds->ds_link = 0;
1936 /*
1937 * Switch antenna every 4 beacons if txantenna is not set
1938 * XXX assumes two antennas
1939 */
1940 if (antenna == 0)
1941 antenna = sc->bsent & 4 ? 2 : 1;
1942 }
1943
1944 ds->ds_data = bf->skbaddr;
1945 ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
1946 ieee80211_get_hdrlen_from_skb(skb),
1947 AR5K_PKT_TYPE_BEACON, (sc->power_level * 2),
1948 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
1949 1, AR5K_TXKEYIX_INVALID,
1950 antenna, flags, 0, 0);
1951 if (ret)
1952 goto err_unmap;
1953
1954 return 0;
1955 err_unmap:
1956 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1957 return ret;
1958 }
1959
1960 /*
1961 * Transmit a beacon frame at SWBA. Dynamic updates to the
1962 * frame contents are done as needed and the slot time is
1963 * also adjusted based on current state.
1964 *
1965 * this is usually called from interrupt context (ath5k_intr())
1966 * but also from ath5k_beacon_config() in IBSS mode which in turn
1967 * can be called from a tasklet and user context
1968 */
1969 static void
1970 ath5k_beacon_send(struct ath5k_softc *sc)
1971 {
1972 struct ath5k_buf *bf = sc->bbuf;
1973 struct ath5k_hw *ah = sc->ah;
1974
1975 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n");
1976
1977 if (unlikely(bf->skb == NULL || sc->opmode == NL80211_IFTYPE_STATION ||
1978 sc->opmode == NL80211_IFTYPE_MONITOR)) {
1979 ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
1980 return;
1981 }
1982 /*
1983 * Check if the previous beacon has gone out. If
1984 * not don't don't try to post another, skip this
1985 * period and wait for the next. Missed beacons
1986 * indicate a problem and should not occur. If we
1987 * miss too many consecutive beacons reset the device.
1988 */
1989 if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) {
1990 sc->bmisscount++;
1991 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1992 "missed %u consecutive beacons\n", sc->bmisscount);
1993 if (sc->bmisscount > 3) { /* NB: 3 is a guess */
1994 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1995 "stuck beacon time (%u missed)\n",
1996 sc->bmisscount);
1997 tasklet_schedule(&sc->restq);
1998 }
1999 return;
2000 }
2001 if (unlikely(sc->bmisscount != 0)) {
2002 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2003 "resume beacon xmit after %u misses\n",
2004 sc->bmisscount);
2005 sc->bmisscount = 0;
2006 }
2007
2008 /*
2009 * Stop any current dma and put the new frame on the queue.
2010 * This should never fail since we check above that no frames
2011 * are still pending on the queue.
2012 */
2013 if (unlikely(ath5k_hw_stop_tx_dma(ah, sc->bhalq))) {
2014 ATH5K_WARN(sc, "beacon queue %u didn't stop?\n", sc->bhalq);
2015 /* NB: hw still stops DMA, so proceed */
2016 }
2017
2018 ath5k_hw_set_txdp(ah, sc->bhalq, bf->daddr);
2019 ath5k_hw_start_tx_dma(ah, sc->bhalq);
2020 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
2021 sc->bhalq, (unsigned long long)bf->daddr, bf->desc);
2022
2023 sc->bsent++;
2024 }
2025
2026
2027 /**
2028 * ath5k_beacon_update_timers - update beacon timers
2029 *
2030 * @sc: struct ath5k_softc pointer we are operating on
2031 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
2032 * beacon timer update based on the current HW TSF.
2033 *
2034 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
2035 * of a received beacon or the current local hardware TSF and write it to the
2036 * beacon timer registers.
2037 *
2038 * This is called in a variety of situations, e.g. when a beacon is received,
2039 * when a TSF update has been detected, but also when an new IBSS is created or
2040 * when we otherwise know we have to update the timers, but we keep it in this
2041 * function to have it all together in one place.
2042 */
2043 static void
2044 ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
2045 {
2046 struct ath5k_hw *ah = sc->ah;
2047 u32 nexttbtt, intval, hw_tu, bc_tu;
2048 u64 hw_tsf;
2049
2050 intval = sc->bintval & AR5K_BEACON_PERIOD;
2051 if (WARN_ON(!intval))
2052 return;
2053
2054 /* beacon TSF converted to TU */
2055 bc_tu = TSF_TO_TU(bc_tsf);
2056
2057 /* current TSF converted to TU */
2058 hw_tsf = ath5k_hw_get_tsf64(ah);
2059 hw_tu = TSF_TO_TU(hw_tsf);
2060
2061 #define FUDGE 3
2062 /* we use FUDGE to make sure the next TBTT is ahead of the current TU */
2063 if (bc_tsf == -1) {
2064 /*
2065 * no beacons received, called internally.
2066 * just need to refresh timers based on HW TSF.
2067 */
2068 nexttbtt = roundup(hw_tu + FUDGE, intval);
2069 } else if (bc_tsf == 0) {
2070 /*
2071 * no beacon received, probably called by ath5k_reset_tsf().
2072 * reset TSF to start with 0.
2073 */
2074 nexttbtt = intval;
2075 intval |= AR5K_BEACON_RESET_TSF;
2076 } else if (bc_tsf > hw_tsf) {
2077 /*
2078 * beacon received, SW merge happend but HW TSF not yet updated.
2079 * not possible to reconfigure timers yet, but next time we
2080 * receive a beacon with the same BSSID, the hardware will
2081 * automatically update the TSF and then we need to reconfigure
2082 * the timers.
2083 */
2084 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2085 "need to wait for HW TSF sync\n");
2086 return;
2087 } else {
2088 /*
2089 * most important case for beacon synchronization between STA.
2090 *
2091 * beacon received and HW TSF has been already updated by HW.
2092 * update next TBTT based on the TSF of the beacon, but make
2093 * sure it is ahead of our local TSF timer.
2094 */
2095 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
2096 }
2097 #undef FUDGE
2098
2099 sc->nexttbtt = nexttbtt;
2100
2101 intval |= AR5K_BEACON_ENA;
2102 ath5k_hw_init_beacon(ah, nexttbtt, intval);
2103
2104 /*
2105 * debugging output last in order to preserve the time critical aspect
2106 * of this function
2107 */
2108 if (bc_tsf == -1)
2109 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2110 "reconfigured timers based on HW TSF\n");
2111 else if (bc_tsf == 0)
2112 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2113 "reset HW TSF and timers\n");
2114 else
2115 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2116 "updated timers based on beacon TSF\n");
2117
2118 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2119 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2120 (unsigned long long) bc_tsf,
2121 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
2122 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
2123 intval & AR5K_BEACON_PERIOD,
2124 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2125 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
2126 }
2127
2128
2129 /**
2130 * ath5k_beacon_config - Configure the beacon queues and interrupts
2131 *
2132 * @sc: struct ath5k_softc pointer we are operating on
2133 *
2134 * When operating in station mode we want to receive a BMISS interrupt when we
2135 * stop seeing beacons from the AP we've associated with so we can look for
2136 * another AP to associate with.
2137 *
2138 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
2139 * interrupts to detect TSF updates only.
2140 *
2141 * AP mode is missing.
2142 */
2143 static void
2144 ath5k_beacon_config(struct ath5k_softc *sc)
2145 {
2146 struct ath5k_hw *ah = sc->ah;
2147
2148 ath5k_hw_set_imr(ah, 0);
2149 sc->bmisscount = 0;
2150 sc->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
2151
2152 if (sc->opmode == NL80211_IFTYPE_STATION) {
2153 sc->imask |= AR5K_INT_BMISS;
2154 } else if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2155 /*
2156 * In IBSS mode we use a self-linked tx descriptor and let the
2157 * hardware send the beacons automatically. We have to load it
2158 * only once here.
2159 * We use the SWBA interrupt only to keep track of the beacon
2160 * timers in order to detect automatic TSF updates.
2161 */
2162 ath5k_beaconq_config(sc);
2163
2164 sc->imask |= AR5K_INT_SWBA;
2165
2166 if (ath5k_hw_hasveol(ah)) {
2167 spin_lock(&sc->block);
2168 ath5k_beacon_send(sc);
2169 spin_unlock(&sc->block);
2170 }
2171 }
2172 /* TODO else AP */
2173
2174 ath5k_hw_set_imr(ah, sc->imask);
2175 }
2176
2177
2178 /********************\
2179 * Interrupt handling *
2180 \********************/
2181
2182 static int
2183 ath5k_init(struct ath5k_softc *sc, bool is_resume)
2184 {
2185 struct ath5k_hw *ah = sc->ah;
2186 int ret, i;
2187
2188 mutex_lock(&sc->lock);
2189
2190 if (is_resume && !test_bit(ATH_STAT_STARTED, sc->status))
2191 goto out_ok;
2192
2193 __clear_bit(ATH_STAT_STARTED, sc->status);
2194
2195 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode);
2196
2197 /*
2198 * Stop anything previously setup. This is safe
2199 * no matter this is the first time through or not.
2200 */
2201 ath5k_stop_locked(sc);
2202
2203 /*
2204 * The basic interface to setting the hardware in a good
2205 * state is ``reset''. On return the hardware is known to
2206 * be powered up and with interrupts disabled. This must
2207 * be followed by initialization of the appropriate bits
2208 * and then setup of the interrupt mask.
2209 */
2210 sc->curchan = sc->hw->conf.channel;
2211 sc->curband = &sc->sbands[sc->curchan->band];
2212 sc->imask = AR5K_INT_RX | AR5K_INT_TX | AR5K_INT_RXEOL |
2213 AR5K_INT_RXORN | AR5K_INT_FATAL | AR5K_INT_GLOBAL |
2214 AR5K_INT_MIB;
2215 ret = ath5k_reset(sc, false, false);
2216 if (ret)
2217 goto done;
2218
2219 /*
2220 * Reset the key cache since some parts do not reset the
2221 * contents on initial power up or resume from suspend.
2222 */
2223 for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
2224 ath5k_hw_reset_key(ah, i);
2225
2226 __set_bit(ATH_STAT_STARTED, sc->status);
2227
2228 /* Set ack to be sent at low bit-rates */
2229 ath5k_hw_set_ack_bitrate_high(ah, false);
2230
2231 mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2232 msecs_to_jiffies(ath5k_calinterval * 1000)));
2233
2234 out_ok:
2235 ret = 0;
2236 done:
2237 mmiowb();
2238 mutex_unlock(&sc->lock);
2239 return ret;
2240 }
2241
2242 static int
2243 ath5k_stop_locked(struct ath5k_softc *sc)
2244 {
2245 struct ath5k_hw *ah = sc->ah;
2246
2247 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n",
2248 test_bit(ATH_STAT_INVALID, sc->status));
2249
2250 /*
2251 * Shutdown the hardware and driver:
2252 * stop output from above
2253 * disable interrupts
2254 * turn off timers
2255 * turn off the radio
2256 * clear transmit machinery
2257 * clear receive machinery
2258 * drain and release tx queues
2259 * reclaim beacon resources
2260 * power down hardware
2261 *
2262 * Note that some of this work is not possible if the
2263 * hardware is gone (invalid).
2264 */
2265 ieee80211_stop_queues(sc->hw);
2266
2267 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2268 ath5k_led_off(sc);
2269 ath5k_hw_set_imr(ah, 0);
2270 synchronize_irq(sc->pdev->irq);
2271 }
2272 ath5k_txq_cleanup(sc);
2273 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2274 ath5k_rx_stop(sc);
2275 ath5k_hw_phy_disable(ah);
2276 } else
2277 sc->rxlink = NULL;
2278
2279 return 0;
2280 }
2281
2282 /*
2283 * Stop the device, grabbing the top-level lock to protect
2284 * against concurrent entry through ath5k_init (which can happen
2285 * if another thread does a system call and the thread doing the
2286 * stop is preempted).
2287 */
2288 static int
2289 ath5k_stop_hw(struct ath5k_softc *sc, bool is_suspend)
2290 {
2291 int ret;
2292
2293 mutex_lock(&sc->lock);
2294 ret = ath5k_stop_locked(sc);
2295 if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
2296 /*
2297 * Set the chip in full sleep mode. Note that we are
2298 * careful to do this only when bringing the interface
2299 * completely to a stop. When the chip is in this state
2300 * it must be carefully woken up or references to
2301 * registers in the PCI clock domain may freeze the bus
2302 * (and system). This varies by chip and is mostly an
2303 * issue with newer parts that go to sleep more quickly.
2304 */
2305 if (sc->ah->ah_mac_srev >= 0x78) {
2306 /*
2307 * XXX
2308 * don't put newer MAC revisions > 7.8 to sleep because
2309 * of the above mentioned problems
2310 */
2311 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mac version > 7.8, "
2312 "not putting device to sleep\n");
2313 } else {
2314 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2315 "putting device to full sleep\n");
2316 ath5k_hw_set_power(sc->ah, AR5K_PM_FULL_SLEEP, true, 0);
2317 }
2318 }
2319 ath5k_txbuf_free(sc, sc->bbuf);
2320 if (!is_suspend)
2321 __clear_bit(ATH_STAT_STARTED, sc->status);
2322
2323 mmiowb();
2324 mutex_unlock(&sc->lock);
2325
2326 del_timer_sync(&sc->calib_tim);
2327 tasklet_kill(&sc->rxtq);
2328 tasklet_kill(&sc->txtq);
2329 tasklet_kill(&sc->restq);
2330
2331 return ret;
2332 }
2333
2334 static irqreturn_t
2335 ath5k_intr(int irq, void *dev_id)
2336 {
2337 struct ath5k_softc *sc = dev_id;
2338 struct ath5k_hw *ah = sc->ah;
2339 enum ath5k_int status;
2340 unsigned int counter = 1000;
2341
2342 if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) ||
2343 !ath5k_hw_is_intr_pending(ah)))
2344 return IRQ_NONE;
2345
2346 do {
2347 /*
2348 * Figure out the reason(s) for the interrupt. Note
2349 * that get_isr returns a pseudo-ISR that may include
2350 * bits we haven't explicitly enabled so we mask the
2351 * value to insure we only process bits we requested.
2352 */
2353 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
2354 ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2355 status, sc->imask);
2356 status &= sc->imask; /* discard unasked for bits */
2357 if (unlikely(status & AR5K_INT_FATAL)) {
2358 /*
2359 * Fatal errors are unrecoverable.
2360 * Typically these are caused by DMA errors.
2361 */
2362 tasklet_schedule(&sc->restq);
2363 } else if (unlikely(status & AR5K_INT_RXORN)) {
2364 tasklet_schedule(&sc->restq);
2365 } else {
2366 if (status & AR5K_INT_SWBA) {
2367 /*
2368 * Software beacon alert--time to send a beacon.
2369 * Handle beacon transmission directly; deferring
2370 * this is too slow to meet timing constraints
2371 * under load.
2372 *
2373 * In IBSS mode we use this interrupt just to
2374 * keep track of the next TBTT (target beacon
2375 * transmission time) in order to detect wether
2376 * automatic TSF updates happened.
2377 */
2378 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2379 /* XXX: only if VEOL suppported */
2380 u64 tsf = ath5k_hw_get_tsf64(ah);
2381 sc->nexttbtt += sc->bintval;
2382 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2383 "SWBA nexttbtt: %x hw_tu: %x "
2384 "TSF: %llx\n",
2385 sc->nexttbtt,
2386 TSF_TO_TU(tsf),
2387 (unsigned long long) tsf);
2388 } else {
2389 spin_lock(&sc->block);
2390 ath5k_beacon_send(sc);
2391 spin_unlock(&sc->block);
2392 }
2393 }
2394 if (status & AR5K_INT_RXEOL) {
2395 /*
2396 * NB: the hardware should re-read the link when
2397 * RXE bit is written, but it doesn't work at
2398 * least on older hardware revs.
2399 */
2400 sc->rxlink = NULL;
2401 }
2402 if (status & AR5K_INT_TXURN) {
2403 /* bump tx trigger level */
2404 ath5k_hw_update_tx_triglevel(ah, true);
2405 }
2406 if (status & AR5K_INT_RX)
2407 tasklet_schedule(&sc->rxtq);
2408 if (status & AR5K_INT_TX)
2409 tasklet_schedule(&sc->txtq);
2410 if (status & AR5K_INT_BMISS) {
2411 }
2412 if (status & AR5K_INT_MIB) {
2413 /*
2414 * These stats are also used for ANI i think
2415 * so how about updating them more often ?
2416 */
2417 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
2418 }
2419 }
2420 } while (ath5k_hw_is_intr_pending(ah) && counter-- > 0);
2421
2422 if (unlikely(!counter))
2423 ATH5K_WARN(sc, "too many interrupts, giving up for now\n");
2424
2425 return IRQ_HANDLED;
2426 }
2427
2428 static void
2429 ath5k_tasklet_reset(unsigned long data)
2430 {
2431 struct ath5k_softc *sc = (void *)data;
2432
2433 ath5k_reset_wake(sc);
2434 }
2435
2436 /*
2437 * Periodically recalibrate the PHY to account
2438 * for temperature/environment changes.
2439 */
2440 static void
2441 ath5k_calibrate(unsigned long data)
2442 {
2443 struct ath5k_softc *sc = (void *)data;
2444 struct ath5k_hw *ah = sc->ah;
2445
2446 ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
2447 ieee80211_frequency_to_channel(sc->curchan->center_freq),
2448 sc->curchan->hw_value);
2449
2450 if (ath5k_hw_get_rf_gain(ah) == AR5K_RFGAIN_NEED_CHANGE) {
2451 /*
2452 * Rfgain is out of bounds, reset the chip
2453 * to load new gain values.
2454 */
2455 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n");
2456 ath5k_reset_wake(sc);
2457 }
2458 if (ath5k_hw_phy_calibrate(ah, sc->curchan))
2459 ATH5K_ERR(sc, "calibration of channel %u failed\n",
2460 ieee80211_frequency_to_channel(
2461 sc->curchan->center_freq));
2462
2463 mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2464 msecs_to_jiffies(ath5k_calinterval * 1000)));
2465 }
2466
2467
2468
2469 /***************\
2470 * LED functions *
2471 \***************/
2472
2473 static void
2474 ath5k_led_enable(struct ath5k_softc *sc)
2475 {
2476 if (test_bit(ATH_STAT_LEDSOFT, sc->status)) {
2477 ath5k_hw_set_gpio_output(sc->ah, sc->led_pin);
2478 ath5k_led_off(sc);
2479 }
2480 }
2481
2482 static void
2483 ath5k_led_on(struct ath5k_softc *sc)
2484 {
2485 if (!test_bit(ATH_STAT_LEDSOFT, sc->status))
2486 return;
2487 ath5k_hw_set_gpio(sc->ah, sc->led_pin, sc->led_on);
2488 }
2489
2490 static void
2491 ath5k_led_off(struct ath5k_softc *sc)
2492 {
2493 if (!test_bit(ATH_STAT_LEDSOFT, sc->status))
2494 return;
2495 ath5k_hw_set_gpio(sc->ah, sc->led_pin, !sc->led_on);
2496 }
2497
2498 static void
2499 ath5k_led_brightness_set(struct led_classdev *led_dev,
2500 enum led_brightness brightness)
2501 {
2502 struct ath5k_led *led = container_of(led_dev, struct ath5k_led,
2503 led_dev);
2504
2505 if (brightness == LED_OFF)
2506 ath5k_led_off(led->sc);
2507 else
2508 ath5k_led_on(led->sc);
2509 }
2510
2511 static int
2512 ath5k_register_led(struct ath5k_softc *sc, struct ath5k_led *led,
2513 const char *name, char *trigger)
2514 {
2515 int err;
2516
2517 led->sc = sc;
2518 strncpy(led->name, name, sizeof(led->name));
2519 led->led_dev.name = led->name;
2520 led->led_dev.default_trigger = trigger;
2521 led->led_dev.brightness_set = ath5k_led_brightness_set;
2522
2523 err = led_classdev_register(&sc->pdev->dev, &led->led_dev);
2524 if (err)
2525 {
2526 ATH5K_WARN(sc, "could not register LED %s\n", name);
2527 led->sc = NULL;
2528 }
2529 return err;
2530 }
2531
2532 static void
2533 ath5k_unregister_led(struct ath5k_led *led)
2534 {
2535 if (!led->sc)
2536 return;
2537 led_classdev_unregister(&led->led_dev);
2538 ath5k_led_off(led->sc);
2539 led->sc = NULL;
2540 }
2541
2542 static void
2543 ath5k_unregister_leds(struct ath5k_softc *sc)
2544 {
2545 ath5k_unregister_led(&sc->rx_led);
2546 ath5k_unregister_led(&sc->tx_led);
2547 }
2548
2549
2550 static int
2551 ath5k_init_leds(struct ath5k_softc *sc)
2552 {
2553 int ret = 0;
2554 struct ieee80211_hw *hw = sc->hw;
2555 struct pci_dev *pdev = sc->pdev;
2556 char name[ATH5K_LED_MAX_NAME_LEN + 1];
2557
2558 /*
2559 * Auto-enable soft led processing for IBM cards and for
2560 * 5211 minipci cards.
2561 */
2562 if (pdev->device == PCI_DEVICE_ID_ATHEROS_AR5212_IBM ||
2563 pdev->device == PCI_DEVICE_ID_ATHEROS_AR5211) {
2564 __set_bit(ATH_STAT_LEDSOFT, sc->status);
2565 sc->led_pin = 0;
2566 sc->led_on = 0; /* active low */
2567 }
2568 /* Enable softled on PIN1 on HP Compaq nc6xx, nc4000 & nx5000 laptops */
2569 if (pdev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ) {
2570 __set_bit(ATH_STAT_LEDSOFT, sc->status);
2571 sc->led_pin = 1;
2572 sc->led_on = 1; /* active high */
2573 }
2574 if (!test_bit(ATH_STAT_LEDSOFT, sc->status))
2575 goto out;
2576
2577 ath5k_led_enable(sc);
2578
2579 snprintf(name, sizeof(name), "ath5k-%s::rx", wiphy_name(hw->wiphy));
2580 ret = ath5k_register_led(sc, &sc->rx_led, name,
2581 ieee80211_get_rx_led_name(hw));
2582 if (ret)
2583 goto out;
2584
2585 snprintf(name, sizeof(name), "ath5k-%s::tx", wiphy_name(hw->wiphy));
2586 ret = ath5k_register_led(sc, &sc->tx_led, name,
2587 ieee80211_get_tx_led_name(hw));
2588 out:
2589 return ret;
2590 }
2591
2592
2593 /********************\
2594 * Mac80211 functions *
2595 \********************/
2596
2597 static int
2598 ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
2599 {
2600 struct ath5k_softc *sc = hw->priv;
2601 struct ath5k_buf *bf;
2602 unsigned long flags;
2603 int hdrlen;
2604 int pad;
2605
2606 ath5k_debug_dump_skb(sc, skb, "TX ", 1);
2607
2608 if (sc->opmode == NL80211_IFTYPE_MONITOR)
2609 ATH5K_DBG(sc, ATH5K_DEBUG_XMIT, "tx in monitor (scan?)\n");
2610
2611 /*
2612 * the hardware expects the header padded to 4 byte boundaries
2613 * if this is not the case we add the padding after the header
2614 */
2615 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2616 if (hdrlen & 3) {
2617 pad = hdrlen % 4;
2618 if (skb_headroom(skb) < pad) {
2619 ATH5K_ERR(sc, "tx hdrlen not %%4: %d not enough"
2620 " headroom to pad %d\n", hdrlen, pad);
2621 return -1;
2622 }
2623 skb_push(skb, pad);
2624 memmove(skb->data, skb->data+pad, hdrlen);
2625 }
2626
2627 spin_lock_irqsave(&sc->txbuflock, flags);
2628 if (list_empty(&sc->txbuf)) {
2629 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n");
2630 spin_unlock_irqrestore(&sc->txbuflock, flags);
2631 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
2632 return -1;
2633 }
2634 bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list);
2635 list_del(&bf->list);
2636 sc->txbuf_len--;
2637 if (list_empty(&sc->txbuf))
2638 ieee80211_stop_queues(hw);
2639 spin_unlock_irqrestore(&sc->txbuflock, flags);
2640
2641 bf->skb = skb;
2642
2643 if (ath5k_txbuf_setup(sc, bf)) {
2644 bf->skb = NULL;
2645 spin_lock_irqsave(&sc->txbuflock, flags);
2646 list_add_tail(&bf->list, &sc->txbuf);
2647 sc->txbuf_len++;
2648 spin_unlock_irqrestore(&sc->txbuflock, flags);
2649 dev_kfree_skb_any(skb);
2650 return 0;
2651 }
2652
2653 return 0;
2654 }
2655
2656 static int
2657 ath5k_reset(struct ath5k_softc *sc, bool stop, bool change_channel)
2658 {
2659 struct ath5k_hw *ah = sc->ah;
2660 int ret;
2661
2662 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
2663
2664 if (stop) {
2665 ath5k_hw_set_imr(ah, 0);
2666 ath5k_txq_cleanup(sc);
2667 ath5k_rx_stop(sc);
2668 }
2669 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, true);
2670 if (ret) {
2671 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
2672 goto err;
2673 }
2674
2675 /*
2676 * This is needed only to setup initial state
2677 * but it's best done after a reset.
2678 */
2679 ath5k_hw_set_txpower_limit(sc->ah, 0);
2680
2681 ret = ath5k_rx_start(sc);
2682 if (ret) {
2683 ATH5K_ERR(sc, "can't start recv logic\n");
2684 goto err;
2685 }
2686
2687 /*
2688 * Change channels and update the h/w rate map if we're switching;
2689 * e.g. 11a to 11b/g.
2690 *
2691 * We may be doing a reset in response to an ioctl that changes the
2692 * channel so update any state that might change as a result.
2693 *
2694 * XXX needed?
2695 */
2696 /* ath5k_chan_change(sc, c); */
2697
2698 ath5k_beacon_config(sc);
2699 /* intrs are enabled by ath5k_beacon_config */
2700
2701 return 0;
2702 err:
2703 return ret;
2704 }
2705
2706 static int
2707 ath5k_reset_wake(struct ath5k_softc *sc)
2708 {
2709 int ret;
2710
2711 ret = ath5k_reset(sc, true, true);
2712 if (!ret)
2713 ieee80211_wake_queues(sc->hw);
2714
2715 return ret;
2716 }
2717
2718 static int ath5k_start(struct ieee80211_hw *hw)
2719 {
2720 return ath5k_init(hw->priv, false);
2721 }
2722
2723 static void ath5k_stop(struct ieee80211_hw *hw)
2724 {
2725 ath5k_stop_hw(hw->priv, false);
2726 }
2727
2728 static int ath5k_add_interface(struct ieee80211_hw *hw,
2729 struct ieee80211_if_init_conf *conf)
2730 {
2731 struct ath5k_softc *sc = hw->priv;
2732 int ret;
2733
2734 mutex_lock(&sc->lock);
2735 if (sc->vif) {
2736 ret = 0;
2737 goto end;
2738 }
2739
2740 sc->vif = conf->vif;
2741
2742 switch (conf->type) {
2743 case NL80211_IFTYPE_STATION:
2744 case NL80211_IFTYPE_ADHOC:
2745 case NL80211_IFTYPE_MONITOR:
2746 sc->opmode = conf->type;
2747 break;
2748 default:
2749 ret = -EOPNOTSUPP;
2750 goto end;
2751 }
2752
2753 /* Set to a reasonable value. Note that this will
2754 * be set to mac80211's value at ath5k_config(). */
2755 sc->bintval = 1000;
2756
2757 ret = 0;
2758 end:
2759 mutex_unlock(&sc->lock);
2760 return ret;
2761 }
2762
2763 static void
2764 ath5k_remove_interface(struct ieee80211_hw *hw,
2765 struct ieee80211_if_init_conf *conf)
2766 {
2767 struct ath5k_softc *sc = hw->priv;
2768
2769 mutex_lock(&sc->lock);
2770 if (sc->vif != conf->vif)
2771 goto end;
2772
2773 sc->vif = NULL;
2774 end:
2775 mutex_unlock(&sc->lock);
2776 }
2777
2778 /*
2779 * TODO: Phy disable/diversity etc
2780 */
2781 static int
2782 ath5k_config(struct ieee80211_hw *hw, u32 changed)
2783 {
2784 struct ath5k_softc *sc = hw->priv;
2785 struct ieee80211_conf *conf = &hw->conf;
2786
2787 sc->bintval = conf->beacon_int;
2788 sc->power_level = conf->power_level;
2789
2790 return ath5k_chan_set(sc, conf->channel);
2791 }
2792
2793 static int
2794 ath5k_config_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2795 struct ieee80211_if_conf *conf)
2796 {
2797 struct ath5k_softc *sc = hw->priv;
2798 struct ath5k_hw *ah = sc->ah;
2799 int ret;
2800
2801 mutex_lock(&sc->lock);
2802 if (sc->vif != vif) {
2803 ret = -EIO;
2804 goto unlock;
2805 }
2806 if (conf->bssid) {
2807 /* Cache for later use during resets */
2808 memcpy(ah->ah_bssid, conf->bssid, ETH_ALEN);
2809 /* XXX: assoc id is set to 0 for now, mac80211 doesn't have
2810 * a clean way of letting us retrieve this yet. */
2811 ath5k_hw_set_associd(ah, ah->ah_bssid, 0);
2812 mmiowb();
2813 }
2814
2815 if (conf->changed & IEEE80211_IFCC_BEACON &&
2816 vif->type == NL80211_IFTYPE_ADHOC) {
2817 struct sk_buff *beacon = ieee80211_beacon_get(hw, vif);
2818 if (!beacon) {
2819 ret = -ENOMEM;
2820 goto unlock;
2821 }
2822 /* call old handler for now */
2823 ath5k_beacon_update(hw, beacon);
2824 }
2825
2826 mutex_unlock(&sc->lock);
2827
2828 return ath5k_reset_wake(sc);
2829 unlock:
2830 mutex_unlock(&sc->lock);
2831 return ret;
2832 }
2833
2834 #define SUPPORTED_FIF_FLAGS \
2835 FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \
2836 FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
2837 FIF_BCN_PRBRESP_PROMISC
2838 /*
2839 * o always accept unicast, broadcast, and multicast traffic
2840 * o multicast traffic for all BSSIDs will be enabled if mac80211
2841 * says it should be
2842 * o maintain current state of phy ofdm or phy cck error reception.
2843 * If the hardware detects any of these type of errors then
2844 * ath5k_hw_get_rx_filter() will pass to us the respective
2845 * hardware filters to be able to receive these type of frames.
2846 * o probe request frames are accepted only when operating in
2847 * hostap, adhoc, or monitor modes
2848 * o enable promiscuous mode according to the interface state
2849 * o accept beacons:
2850 * - when operating in adhoc mode so the 802.11 layer creates
2851 * node table entries for peers,
2852 * - when operating in station mode for collecting rssi data when
2853 * the station is otherwise quiet, or
2854 * - when scanning
2855 */
2856 static void ath5k_configure_filter(struct ieee80211_hw *hw,
2857 unsigned int changed_flags,
2858 unsigned int *new_flags,
2859 int mc_count, struct dev_mc_list *mclist)
2860 {
2861 struct ath5k_softc *sc = hw->priv;
2862 struct ath5k_hw *ah = sc->ah;
2863 u32 mfilt[2], val, rfilt;
2864 u8 pos;
2865 int i;
2866
2867 mfilt[0] = 0;
2868 mfilt[1] = 0;
2869
2870 /* Only deal with supported flags */
2871 changed_flags &= SUPPORTED_FIF_FLAGS;
2872 *new_flags &= SUPPORTED_FIF_FLAGS;
2873
2874 /* If HW detects any phy or radar errors, leave those filters on.
2875 * Also, always enable Unicast, Broadcasts and Multicast
2876 * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
2877 rfilt = (ath5k_hw_get_rx_filter(ah) & (AR5K_RX_FILTER_PHYERR)) |
2878 (AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST |
2879 AR5K_RX_FILTER_MCAST);
2880
2881 if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) {
2882 if (*new_flags & FIF_PROMISC_IN_BSS) {
2883 rfilt |= AR5K_RX_FILTER_PROM;
2884 __set_bit(ATH_STAT_PROMISC, sc->status);
2885 }
2886 else
2887 __clear_bit(ATH_STAT_PROMISC, sc->status);
2888 }
2889
2890 /* Note, AR5K_RX_FILTER_MCAST is already enabled */
2891 if (*new_flags & FIF_ALLMULTI) {
2892 mfilt[0] = ~0;
2893 mfilt[1] = ~0;
2894 } else {
2895 for (i = 0; i < mc_count; i++) {
2896 if (!mclist)
2897 break;
2898 /* calculate XOR of eight 6-bit values */
2899 val = get_unaligned_le32(mclist->dmi_addr + 0);
2900 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2901 val = get_unaligned_le32(mclist->dmi_addr + 3);
2902 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2903 pos &= 0x3f;
2904 mfilt[pos / 32] |= (1 << (pos % 32));
2905 /* XXX: we might be able to just do this instead,
2906 * but not sure, needs testing, if we do use this we'd
2907 * neet to inform below to not reset the mcast */
2908 /* ath5k_hw_set_mcast_filterindex(ah,
2909 * mclist->dmi_addr[5]); */
2910 mclist = mclist->next;
2911 }
2912 }
2913
2914 /* This is the best we can do */
2915 if (*new_flags & (FIF_FCSFAIL | FIF_PLCPFAIL))
2916 rfilt |= AR5K_RX_FILTER_PHYERR;
2917
2918 /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
2919 * and probes for any BSSID, this needs testing */
2920 if (*new_flags & FIF_BCN_PRBRESP_PROMISC)
2921 rfilt |= AR5K_RX_FILTER_BEACON | AR5K_RX_FILTER_PROBEREQ;
2922
2923 /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
2924 * set we should only pass on control frames for this
2925 * station. This needs testing. I believe right now this
2926 * enables *all* control frames, which is OK.. but
2927 * but we should see if we can improve on granularity */
2928 if (*new_flags & FIF_CONTROL)
2929 rfilt |= AR5K_RX_FILTER_CONTROL;
2930
2931 /* Additional settings per mode -- this is per ath5k */
2932
2933 /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
2934
2935 if (sc->opmode == NL80211_IFTYPE_MONITOR)
2936 rfilt |= AR5K_RX_FILTER_CONTROL | AR5K_RX_FILTER_BEACON |
2937 AR5K_RX_FILTER_PROBEREQ | AR5K_RX_FILTER_PROM;
2938 if (sc->opmode != NL80211_IFTYPE_STATION)
2939 rfilt |= AR5K_RX_FILTER_PROBEREQ;
2940 if (sc->opmode != NL80211_IFTYPE_AP &&
2941 sc->opmode != NL80211_IFTYPE_MESH_POINT &&
2942 test_bit(ATH_STAT_PROMISC, sc->status))
2943 rfilt |= AR5K_RX_FILTER_PROM;
2944 if (sc->opmode == NL80211_IFTYPE_ADHOC)
2945 rfilt |= AR5K_RX_FILTER_BEACON;
2946
2947 /* Set filters */
2948 ath5k_hw_set_rx_filter(ah,rfilt);
2949
2950 /* Set multicast bits */
2951 ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]);
2952 /* Set the cached hw filter flags, this will alter actually
2953 * be set in HW */
2954 sc->filter_flags = rfilt;
2955 }
2956
2957 static int
2958 ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
2959 const u8 *local_addr, const u8 *addr,
2960 struct ieee80211_key_conf *key)
2961 {
2962 struct ath5k_softc *sc = hw->priv;
2963 int ret = 0;
2964
2965 switch(key->alg) {
2966 case ALG_WEP:
2967 /* XXX: fix hardware encryption, its not working. For now
2968 * allow software encryption */
2969 /* break; */
2970 case ALG_TKIP:
2971 case ALG_CCMP:
2972 return -EOPNOTSUPP;
2973 default:
2974 WARN_ON(1);
2975 return -EINVAL;
2976 }
2977
2978 mutex_lock(&sc->lock);
2979
2980 switch (cmd) {
2981 case SET_KEY:
2982 ret = ath5k_hw_set_key(sc->ah, key->keyidx, key, addr);
2983 if (ret) {
2984 ATH5K_ERR(sc, "can't set the key\n");
2985 goto unlock;
2986 }
2987 __set_bit(key->keyidx, sc->keymap);
2988 key->hw_key_idx = key->keyidx;
2989 break;
2990 case DISABLE_KEY:
2991 ath5k_hw_reset_key(sc->ah, key->keyidx);
2992 __clear_bit(key->keyidx, sc->keymap);
2993 break;
2994 default:
2995 ret = -EINVAL;
2996 goto unlock;
2997 }
2998
2999 unlock:
3000 mmiowb();
3001 mutex_unlock(&sc->lock);
3002 return ret;
3003 }
3004
3005 static int
3006 ath5k_get_stats(struct ieee80211_hw *hw,
3007 struct ieee80211_low_level_stats *stats)
3008 {
3009 struct ath5k_softc *sc = hw->priv;
3010 struct ath5k_hw *ah = sc->ah;
3011
3012 /* Force update */
3013 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
3014
3015 memcpy(stats, &sc->ll_stats, sizeof(sc->ll_stats));
3016
3017 return 0;
3018 }
3019
3020 static int
3021 ath5k_get_tx_stats(struct ieee80211_hw *hw,
3022 struct ieee80211_tx_queue_stats *stats)
3023 {
3024 struct ath5k_softc *sc = hw->priv;
3025
3026 memcpy(stats, &sc->tx_stats, sizeof(sc->tx_stats));
3027
3028 return 0;
3029 }
3030
3031 static u64
3032 ath5k_get_tsf(struct ieee80211_hw *hw)
3033 {
3034 struct ath5k_softc *sc = hw->priv;
3035
3036 return ath5k_hw_get_tsf64(sc->ah);
3037 }
3038
3039 static void
3040 ath5k_reset_tsf(struct ieee80211_hw *hw)
3041 {
3042 struct ath5k_softc *sc = hw->priv;
3043
3044 /*
3045 * in IBSS mode we need to update the beacon timers too.
3046 * this will also reset the TSF if we call it with 0
3047 */
3048 if (sc->opmode == NL80211_IFTYPE_ADHOC)
3049 ath5k_beacon_update_timers(sc, 0);
3050 else
3051 ath5k_hw_reset_tsf(sc->ah);
3052 }
3053
3054 static int
3055 ath5k_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb)
3056 {
3057 struct ath5k_softc *sc = hw->priv;
3058 unsigned long flags;
3059 int ret;
3060
3061 ath5k_debug_dump_skb(sc, skb, "BC ", 1);
3062
3063 if (sc->opmode != NL80211_IFTYPE_ADHOC) {
3064 ret = -EIO;
3065 goto end;
3066 }
3067
3068 spin_lock_irqsave(&sc->block, flags);
3069 ath5k_txbuf_free(sc, sc->bbuf);
3070 sc->bbuf->skb = skb;
3071 ret = ath5k_beacon_setup(sc, sc->bbuf);
3072 if (ret)
3073 sc->bbuf->skb = NULL;
3074 spin_unlock_irqrestore(&sc->block, flags);
3075 if (!ret) {
3076 ath5k_beacon_config(sc);
3077 mmiowb();
3078 }
3079
3080 end:
3081 return ret;
3082 }
3083
Linux kernel - Deliverables
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