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Merge branch 'master' of master.kernel.org:/pub/scm/linux/kernel/git/torvalds/linux-2.6
[deliverable/linux.git] / drivers / net / wireless / ath5k / base.c
1 /*-
2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
7 *
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
23 *
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
27 *
28 * NO WARRANTY
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
40 *
41 */
42
43 #include <linux/version.h>
44 #include <linux/module.h>
45 #include <linux/delay.h>
46 #include <linux/if.h>
47 #include <linux/netdevice.h>
48 #include <linux/cache.h>
49 #include <linux/pci.h>
50 #include <linux/ethtool.h>
51 #include <linux/uaccess.h>
52
53 #include <net/ieee80211_radiotap.h>
54
55 #include <asm/unaligned.h>
56
57 #include "base.h"
58 #include "reg.h"
59 #include "debug.h"
60
61 /* unaligned little endian access */
62 #define LE_READ_2(_p) (le16_to_cpu(get_unaligned((__le16 *)(_p))))
63 #define LE_READ_4(_p) (le32_to_cpu(get_unaligned((__le32 *)(_p))))
64
65 enum {
66 ATH_LED_TX,
67 ATH_LED_RX,
68 };
69
70 static int ath5k_calinterval = 10; /* Calibrate PHY every 10 secs (TODO: Fixme) */
71
72
73 /******************\
74 * Internal defines *
75 \******************/
76
77 /* Module info */
78 MODULE_AUTHOR("Jiri Slaby");
79 MODULE_AUTHOR("Nick Kossifidis");
80 MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
81 MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
82 MODULE_LICENSE("Dual BSD/GPL");
83 MODULE_VERSION("0.5.0 (EXPERIMENTAL)");
84
85
86 /* Known PCI ids */
87 static struct pci_device_id ath5k_pci_id_table[] __devinitdata = {
88 { PCI_VDEVICE(ATHEROS, 0x0207), .driver_data = AR5K_AR5210 }, /* 5210 early */
89 { PCI_VDEVICE(ATHEROS, 0x0007), .driver_data = AR5K_AR5210 }, /* 5210 */
90 { PCI_VDEVICE(ATHEROS, 0x0011), .driver_data = AR5K_AR5211 }, /* 5311 - this is on AHB bus !*/
91 { PCI_VDEVICE(ATHEROS, 0x0012), .driver_data = AR5K_AR5211 }, /* 5211 */
92 { PCI_VDEVICE(ATHEROS, 0x0013), .driver_data = AR5K_AR5212 }, /* 5212 */
93 { PCI_VDEVICE(3COM_2, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 5212 */
94 { PCI_VDEVICE(3COM, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 3CRDAG675 5212 */
95 { PCI_VDEVICE(ATHEROS, 0x1014), .driver_data = AR5K_AR5212 }, /* IBM minipci 5212 */
96 { PCI_VDEVICE(ATHEROS, 0x0014), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
97 { PCI_VDEVICE(ATHEROS, 0x0015), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
98 { PCI_VDEVICE(ATHEROS, 0x0016), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
99 { PCI_VDEVICE(ATHEROS, 0x0017), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
100 { PCI_VDEVICE(ATHEROS, 0x0018), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
101 { PCI_VDEVICE(ATHEROS, 0x0019), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
102 { PCI_VDEVICE(ATHEROS, 0x001a), .driver_data = AR5K_AR5212 }, /* 2413 Griffin-lite */
103 { PCI_VDEVICE(ATHEROS, 0x001b), .driver_data = AR5K_AR5212 }, /* 5413 Eagle */
104 { PCI_VDEVICE(ATHEROS, 0x001c), .driver_data = AR5K_AR5212 }, /* 5424 Condor (PCI-E)*/
105 { PCI_VDEVICE(ATHEROS, 0x0023), .driver_data = AR5K_AR5212 }, /* 5416 */
106 { PCI_VDEVICE(ATHEROS, 0x0024), .driver_data = AR5K_AR5212 }, /* 5418 */
107 { 0 }
108 };
109 MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table);
110
111 /* Known SREVs */
112 static struct ath5k_srev_name srev_names[] = {
113 { "5210", AR5K_VERSION_VER, AR5K_SREV_VER_AR5210 },
114 { "5311", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311 },
115 { "5311A", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311A },
116 { "5311B", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311B },
117 { "5211", AR5K_VERSION_VER, AR5K_SREV_VER_AR5211 },
118 { "5212", AR5K_VERSION_VER, AR5K_SREV_VER_AR5212 },
119 { "5213", AR5K_VERSION_VER, AR5K_SREV_VER_AR5213 },
120 { "5213A", AR5K_VERSION_VER, AR5K_SREV_VER_AR5213A },
121 { "2413", AR5K_VERSION_VER, AR5K_SREV_VER_AR2413 },
122 { "2414", AR5K_VERSION_VER, AR5K_SREV_VER_AR2414 },
123 { "2424", AR5K_VERSION_VER, AR5K_SREV_VER_AR2424 },
124 { "5424", AR5K_VERSION_VER, AR5K_SREV_VER_AR5424 },
125 { "5413", AR5K_VERSION_VER, AR5K_SREV_VER_AR5413 },
126 { "5414", AR5K_VERSION_VER, AR5K_SREV_VER_AR5414 },
127 { "5416", AR5K_VERSION_VER, AR5K_SREV_VER_AR5416 },
128 { "5418", AR5K_VERSION_VER, AR5K_SREV_VER_AR5418 },
129 { "2425", AR5K_VERSION_VER, AR5K_SREV_VER_AR2425 },
130 { "xxxxx", AR5K_VERSION_VER, AR5K_SREV_UNKNOWN },
131 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
132 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
133 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
134 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
135 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
136 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
137 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
138 { "SChip", AR5K_VERSION_RAD, AR5K_SREV_RAD_SC0 },
139 { "SChip", AR5K_VERSION_RAD, AR5K_SREV_RAD_SC1 },
140 { "SChip", AR5K_VERSION_RAD, AR5K_SREV_RAD_SC2 },
141 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
142 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
143 };
144
145 /*
146 * Prototypes - PCI stack related functions
147 */
148 static int __devinit ath5k_pci_probe(struct pci_dev *pdev,
149 const struct pci_device_id *id);
150 static void __devexit ath5k_pci_remove(struct pci_dev *pdev);
151 #ifdef CONFIG_PM
152 static int ath5k_pci_suspend(struct pci_dev *pdev,
153 pm_message_t state);
154 static int ath5k_pci_resume(struct pci_dev *pdev);
155 #else
156 #define ath5k_pci_suspend NULL
157 #define ath5k_pci_resume NULL
158 #endif /* CONFIG_PM */
159
160 static struct pci_driver ath5k_pci_driver = {
161 .name = "ath5k_pci",
162 .id_table = ath5k_pci_id_table,
163 .probe = ath5k_pci_probe,
164 .remove = __devexit_p(ath5k_pci_remove),
165 .suspend = ath5k_pci_suspend,
166 .resume = ath5k_pci_resume,
167 };
168
169
170
171 /*
172 * Prototypes - MAC 802.11 stack related functions
173 */
174 static int ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb,
175 struct ieee80211_tx_control *ctl);
176 static int ath5k_reset(struct ieee80211_hw *hw);
177 static int ath5k_start(struct ieee80211_hw *hw);
178 static void ath5k_stop(struct ieee80211_hw *hw);
179 static int ath5k_add_interface(struct ieee80211_hw *hw,
180 struct ieee80211_if_init_conf *conf);
181 static void ath5k_remove_interface(struct ieee80211_hw *hw,
182 struct ieee80211_if_init_conf *conf);
183 static int ath5k_config(struct ieee80211_hw *hw,
184 struct ieee80211_conf *conf);
185 static int ath5k_config_interface(struct ieee80211_hw *hw,
186 struct ieee80211_vif *vif,
187 struct ieee80211_if_conf *conf);
188 static void ath5k_configure_filter(struct ieee80211_hw *hw,
189 unsigned int changed_flags,
190 unsigned int *new_flags,
191 int mc_count, struct dev_mc_list *mclist);
192 static int ath5k_set_key(struct ieee80211_hw *hw,
193 enum set_key_cmd cmd,
194 const u8 *local_addr, const u8 *addr,
195 struct ieee80211_key_conf *key);
196 static int ath5k_get_stats(struct ieee80211_hw *hw,
197 struct ieee80211_low_level_stats *stats);
198 static int ath5k_get_tx_stats(struct ieee80211_hw *hw,
199 struct ieee80211_tx_queue_stats *stats);
200 static u64 ath5k_get_tsf(struct ieee80211_hw *hw);
201 static void ath5k_reset_tsf(struct ieee80211_hw *hw);
202 static int ath5k_beacon_update(struct ieee80211_hw *hw,
203 struct sk_buff *skb,
204 struct ieee80211_tx_control *ctl);
205
206 static struct ieee80211_ops ath5k_hw_ops = {
207 .tx = ath5k_tx,
208 .start = ath5k_start,
209 .stop = ath5k_stop,
210 .add_interface = ath5k_add_interface,
211 .remove_interface = ath5k_remove_interface,
212 .config = ath5k_config,
213 .config_interface = ath5k_config_interface,
214 .configure_filter = ath5k_configure_filter,
215 .set_key = ath5k_set_key,
216 .get_stats = ath5k_get_stats,
217 .conf_tx = NULL,
218 .get_tx_stats = ath5k_get_tx_stats,
219 .get_tsf = ath5k_get_tsf,
220 .reset_tsf = ath5k_reset_tsf,
221 .beacon_update = ath5k_beacon_update,
222 };
223
224 /*
225 * Prototypes - Internal functions
226 */
227 /* Attach detach */
228 static int ath5k_attach(struct pci_dev *pdev,
229 struct ieee80211_hw *hw);
230 static void ath5k_detach(struct pci_dev *pdev,
231 struct ieee80211_hw *hw);
232 /* Channel/mode setup */
233 static inline short ath5k_ieee2mhz(short chan);
234 static unsigned int ath5k_copy_rates(struct ieee80211_rate *rates,
235 const struct ath5k_rate_table *rt,
236 unsigned int max);
237 static unsigned int ath5k_copy_channels(struct ath5k_hw *ah,
238 struct ieee80211_channel *channels,
239 unsigned int mode,
240 unsigned int max);
241 static int ath5k_getchannels(struct ieee80211_hw *hw);
242 static int ath5k_chan_set(struct ath5k_softc *sc,
243 struct ieee80211_channel *chan);
244 static void ath5k_setcurmode(struct ath5k_softc *sc,
245 unsigned int mode);
246 static void ath5k_mode_setup(struct ath5k_softc *sc);
247 static void ath5k_set_total_hw_rates(struct ath5k_softc *sc);
248
249 /* Descriptor setup */
250 static int ath5k_desc_alloc(struct ath5k_softc *sc,
251 struct pci_dev *pdev);
252 static void ath5k_desc_free(struct ath5k_softc *sc,
253 struct pci_dev *pdev);
254 /* Buffers setup */
255 static int ath5k_rxbuf_setup(struct ath5k_softc *sc,
256 struct ath5k_buf *bf);
257 static int ath5k_txbuf_setup(struct ath5k_softc *sc,
258 struct ath5k_buf *bf,
259 struct ieee80211_tx_control *ctl);
260
261 static inline void ath5k_txbuf_free(struct ath5k_softc *sc,
262 struct ath5k_buf *bf)
263 {
264 BUG_ON(!bf);
265 if (!bf->skb)
266 return;
267 pci_unmap_single(sc->pdev, bf->skbaddr, bf->skb->len,
268 PCI_DMA_TODEVICE);
269 dev_kfree_skb(bf->skb);
270 bf->skb = NULL;
271 }
272
273 /* Queues setup */
274 static struct ath5k_txq *ath5k_txq_setup(struct ath5k_softc *sc,
275 int qtype, int subtype);
276 static int ath5k_beaconq_setup(struct ath5k_hw *ah);
277 static int ath5k_beaconq_config(struct ath5k_softc *sc);
278 static void ath5k_txq_drainq(struct ath5k_softc *sc,
279 struct ath5k_txq *txq);
280 static void ath5k_txq_cleanup(struct ath5k_softc *sc);
281 static void ath5k_txq_release(struct ath5k_softc *sc);
282 /* Rx handling */
283 static int ath5k_rx_start(struct ath5k_softc *sc);
284 static void ath5k_rx_stop(struct ath5k_softc *sc);
285 static unsigned int ath5k_rx_decrypted(struct ath5k_softc *sc,
286 struct ath5k_desc *ds,
287 struct sk_buff *skb,
288 struct ath5k_rx_status *rs);
289 static void ath5k_tasklet_rx(unsigned long data);
290 /* Tx handling */
291 static void ath5k_tx_processq(struct ath5k_softc *sc,
292 struct ath5k_txq *txq);
293 static void ath5k_tasklet_tx(unsigned long data);
294 /* Beacon handling */
295 static int ath5k_beacon_setup(struct ath5k_softc *sc,
296 struct ath5k_buf *bf,
297 struct ieee80211_tx_control *ctl);
298 static void ath5k_beacon_send(struct ath5k_softc *sc);
299 static void ath5k_beacon_config(struct ath5k_softc *sc);
300 static void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf);
301
302 static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
303 {
304 u64 tsf = ath5k_hw_get_tsf64(ah);
305
306 if ((tsf & 0x7fff) < rstamp)
307 tsf -= 0x8000;
308
309 return (tsf & ~0x7fff) | rstamp;
310 }
311
312 /* Interrupt handling */
313 static int ath5k_init(struct ath5k_softc *sc);
314 static int ath5k_stop_locked(struct ath5k_softc *sc);
315 static int ath5k_stop_hw(struct ath5k_softc *sc);
316 static irqreturn_t ath5k_intr(int irq, void *dev_id);
317 static void ath5k_tasklet_reset(unsigned long data);
318
319 static void ath5k_calibrate(unsigned long data);
320 /* LED functions */
321 static void ath5k_led_off(unsigned long data);
322 static void ath5k_led_blink(struct ath5k_softc *sc,
323 unsigned int on,
324 unsigned int off);
325 static void ath5k_led_event(struct ath5k_softc *sc,
326 int event);
327
328
329 /*
330 * Module init/exit functions
331 */
332 static int __init
333 init_ath5k_pci(void)
334 {
335 int ret;
336
337 ath5k_debug_init();
338
339 ret = pci_register_driver(&ath5k_pci_driver);
340 if (ret) {
341 printk(KERN_ERR "ath5k_pci: can't register pci driver\n");
342 return ret;
343 }
344
345 return 0;
346 }
347
348 static void __exit
349 exit_ath5k_pci(void)
350 {
351 pci_unregister_driver(&ath5k_pci_driver);
352
353 ath5k_debug_finish();
354 }
355
356 module_init(init_ath5k_pci);
357 module_exit(exit_ath5k_pci);
358
359
360 /********************\
361 * PCI Initialization *
362 \********************/
363
364 static const char *
365 ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
366 {
367 const char *name = "xxxxx";
368 unsigned int i;
369
370 for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
371 if (srev_names[i].sr_type != type)
372 continue;
373 if ((val & 0xff) < srev_names[i + 1].sr_val) {
374 name = srev_names[i].sr_name;
375 break;
376 }
377 }
378
379 return name;
380 }
381
382 static int __devinit
383 ath5k_pci_probe(struct pci_dev *pdev,
384 const struct pci_device_id *id)
385 {
386 void __iomem *mem;
387 struct ath5k_softc *sc;
388 struct ieee80211_hw *hw;
389 int ret;
390 u8 csz;
391
392 ret = pci_enable_device(pdev);
393 if (ret) {
394 dev_err(&pdev->dev, "can't enable device\n");
395 goto err;
396 }
397
398 /* XXX 32-bit addressing only */
399 ret = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
400 if (ret) {
401 dev_err(&pdev->dev, "32-bit DMA not available\n");
402 goto err_dis;
403 }
404
405 /*
406 * Cache line size is used to size and align various
407 * structures used to communicate with the hardware.
408 */
409 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
410 if (csz == 0) {
411 /*
412 * Linux 2.4.18 (at least) writes the cache line size
413 * register as a 16-bit wide register which is wrong.
414 * We must have this setup properly for rx buffer
415 * DMA to work so force a reasonable value here if it
416 * comes up zero.
417 */
418 csz = L1_CACHE_BYTES / sizeof(u32);
419 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
420 }
421 /*
422 * The default setting of latency timer yields poor results,
423 * set it to the value used by other systems. It may be worth
424 * tweaking this setting more.
425 */
426 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
427
428 /* Enable bus mastering */
429 pci_set_master(pdev);
430
431 /*
432 * Disable the RETRY_TIMEOUT register (0x41) to keep
433 * PCI Tx retries from interfering with C3 CPU state.
434 */
435 pci_write_config_byte(pdev, 0x41, 0);
436
437 ret = pci_request_region(pdev, 0, "ath5k");
438 if (ret) {
439 dev_err(&pdev->dev, "cannot reserve PCI memory region\n");
440 goto err_dis;
441 }
442
443 mem = pci_iomap(pdev, 0, 0);
444 if (!mem) {
445 dev_err(&pdev->dev, "cannot remap PCI memory region\n") ;
446 ret = -EIO;
447 goto err_reg;
448 }
449
450 /*
451 * Allocate hw (mac80211 main struct)
452 * and hw->priv (driver private data)
453 */
454 hw = ieee80211_alloc_hw(sizeof(*sc), &ath5k_hw_ops);
455 if (hw == NULL) {
456 dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n");
457 ret = -ENOMEM;
458 goto err_map;
459 }
460
461 dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy));
462
463 /* Initialize driver private data */
464 SET_IEEE80211_DEV(hw, &pdev->dev);
465 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS;
466 hw->extra_tx_headroom = 2;
467 hw->channel_change_time = 5000;
468 /* these names are misleading */
469 hw->max_rssi = -110; /* signal in dBm */
470 hw->max_noise = -110; /* noise in dBm */
471 hw->max_signal = 100; /* we will provide a percentage based on rssi */
472 sc = hw->priv;
473 sc->hw = hw;
474 sc->pdev = pdev;
475
476 ath5k_debug_init_device(sc);
477
478 /*
479 * Mark the device as detached to avoid processing
480 * interrupts until setup is complete.
481 */
482 __set_bit(ATH_STAT_INVALID, sc->status);
483
484 sc->iobase = mem; /* So we can unmap it on detach */
485 sc->cachelsz = csz * sizeof(u32); /* convert to bytes */
486 sc->opmode = IEEE80211_IF_TYPE_STA;
487 mutex_init(&sc->lock);
488 spin_lock_init(&sc->rxbuflock);
489 spin_lock_init(&sc->txbuflock);
490
491 /* Set private data */
492 pci_set_drvdata(pdev, hw);
493
494 /* Enable msi for devices that support it */
495 pci_enable_msi(pdev);
496
497 /* Setup interrupt handler */
498 ret = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
499 if (ret) {
500 ATH5K_ERR(sc, "request_irq failed\n");
501 goto err_free;
502 }
503
504 /* Initialize device */
505 sc->ah = ath5k_hw_attach(sc, id->driver_data);
506 if (IS_ERR(sc->ah)) {
507 ret = PTR_ERR(sc->ah);
508 goto err_irq;
509 }
510
511 /* Finish private driver data initialization */
512 ret = ath5k_attach(pdev, hw);
513 if (ret)
514 goto err_ah;
515
516 ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
517 ath5k_chip_name(AR5K_VERSION_VER,sc->ah->ah_mac_srev),
518 sc->ah->ah_mac_srev,
519 sc->ah->ah_phy_revision);
520
521 if (!sc->ah->ah_single_chip) {
522 /* Single chip radio (!RF5111) */
523 if (sc->ah->ah_radio_5ghz_revision &&
524 !sc->ah->ah_radio_2ghz_revision) {
525 /* No 5GHz support -> report 2GHz radio */
526 if (!test_bit(AR5K_MODE_11A,
527 sc->ah->ah_capabilities.cap_mode)) {
528 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
529 ath5k_chip_name(AR5K_VERSION_RAD,
530 sc->ah->ah_radio_5ghz_revision),
531 sc->ah->ah_radio_5ghz_revision);
532 /* No 2GHz support (5110 and some
533 * 5Ghz only cards) -> report 5Ghz radio */
534 } else if (!test_bit(AR5K_MODE_11B,
535 sc->ah->ah_capabilities.cap_mode)) {
536 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
537 ath5k_chip_name(AR5K_VERSION_RAD,
538 sc->ah->ah_radio_5ghz_revision),
539 sc->ah->ah_radio_5ghz_revision);
540 /* Multiband radio */
541 } else {
542 ATH5K_INFO(sc, "RF%s multiband radio found"
543 " (0x%x)\n",
544 ath5k_chip_name(AR5K_VERSION_RAD,
545 sc->ah->ah_radio_5ghz_revision),
546 sc->ah->ah_radio_5ghz_revision);
547 }
548 }
549 /* Multi chip radio (RF5111 - RF2111) ->
550 * report both 2GHz/5GHz radios */
551 else if (sc->ah->ah_radio_5ghz_revision &&
552 sc->ah->ah_radio_2ghz_revision){
553 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
554 ath5k_chip_name(AR5K_VERSION_RAD,
555 sc->ah->ah_radio_5ghz_revision),
556 sc->ah->ah_radio_5ghz_revision);
557 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
558 ath5k_chip_name(AR5K_VERSION_RAD,
559 sc->ah->ah_radio_2ghz_revision),
560 sc->ah->ah_radio_2ghz_revision);
561 }
562 }
563
564
565 /* ready to process interrupts */
566 __clear_bit(ATH_STAT_INVALID, sc->status);
567
568 return 0;
569 err_ah:
570 ath5k_hw_detach(sc->ah);
571 err_irq:
572 free_irq(pdev->irq, sc);
573 err_free:
574 pci_disable_msi(pdev);
575 ieee80211_free_hw(hw);
576 err_map:
577 pci_iounmap(pdev, mem);
578 err_reg:
579 pci_release_region(pdev, 0);
580 err_dis:
581 pci_disable_device(pdev);
582 err:
583 return ret;
584 }
585
586 static void __devexit
587 ath5k_pci_remove(struct pci_dev *pdev)
588 {
589 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
590 struct ath5k_softc *sc = hw->priv;
591
592 ath5k_debug_finish_device(sc);
593 ath5k_detach(pdev, hw);
594 ath5k_hw_detach(sc->ah);
595 free_irq(pdev->irq, sc);
596 pci_disable_msi(pdev);
597 pci_iounmap(pdev, sc->iobase);
598 pci_release_region(pdev, 0);
599 pci_disable_device(pdev);
600 ieee80211_free_hw(hw);
601 }
602
603 #ifdef CONFIG_PM
604 static int
605 ath5k_pci_suspend(struct pci_dev *pdev, pm_message_t state)
606 {
607 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
608 struct ath5k_softc *sc = hw->priv;
609
610 if (test_bit(ATH_STAT_LEDSOFT, sc->status))
611 ath5k_hw_set_gpio(sc->ah, sc->led_pin, 1);
612
613 ath5k_stop_hw(sc);
614 pci_save_state(pdev);
615 pci_disable_device(pdev);
616 pci_set_power_state(pdev, PCI_D3hot);
617
618 return 0;
619 }
620
621 static int
622 ath5k_pci_resume(struct pci_dev *pdev)
623 {
624 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
625 struct ath5k_softc *sc = hw->priv;
626 struct ath5k_hw *ah = sc->ah;
627 int i, err;
628
629 err = pci_set_power_state(pdev, PCI_D0);
630 if (err)
631 return err;
632
633 err = pci_enable_device(pdev);
634 if (err)
635 return err;
636
637 pci_restore_state(pdev);
638 /*
639 * Suspend/Resume resets the PCI configuration space, so we have to
640 * re-disable the RETRY_TIMEOUT register (0x41) to keep
641 * PCI Tx retries from interfering with C3 CPU state
642 */
643 pci_write_config_byte(pdev, 0x41, 0);
644
645 ath5k_init(sc);
646 if (test_bit(ATH_STAT_LEDSOFT, sc->status)) {
647 ath5k_hw_set_gpio_output(ah, sc->led_pin);
648 ath5k_hw_set_gpio(ah, sc->led_pin, 0);
649 }
650
651 /*
652 * Reset the key cache since some parts do not
653 * reset the contents on initial power up or resume.
654 *
655 * FIXME: This may need to be revisited when mac80211 becomes
656 * aware of suspend/resume.
657 */
658 for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
659 ath5k_hw_reset_key(ah, i);
660
661 return 0;
662 }
663 #endif /* CONFIG_PM */
664
665
666
667 /***********************\
668 * Driver Initialization *
669 \***********************/
670
671 static int
672 ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw)
673 {
674 struct ath5k_softc *sc = hw->priv;
675 struct ath5k_hw *ah = sc->ah;
676 u8 mac[ETH_ALEN];
677 unsigned int i;
678 int ret;
679
680 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "devid 0x%x\n", pdev->device);
681
682 /*
683 * Check if the MAC has multi-rate retry support.
684 * We do this by trying to setup a fake extended
685 * descriptor. MAC's that don't have support will
686 * return false w/o doing anything. MAC's that do
687 * support it will return true w/o doing anything.
688 */
689 ret = ah->ah_setup_xtx_desc(ah, NULL, 0, 0, 0, 0, 0, 0);
690 if (ret < 0)
691 goto err;
692 if (ret > 0)
693 __set_bit(ATH_STAT_MRRETRY, sc->status);
694
695 /*
696 * Reset the key cache since some parts do not
697 * reset the contents on initial power up.
698 */
699 for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
700 ath5k_hw_reset_key(ah, i);
701
702 /*
703 * Collect the channel list. The 802.11 layer
704 * is resposible for filtering this list based
705 * on settings like the phy mode and regulatory
706 * domain restrictions.
707 */
708 ret = ath5k_getchannels(hw);
709 if (ret) {
710 ATH5K_ERR(sc, "can't get channels\n");
711 goto err;
712 }
713
714 /* Set *_rates so we can map hw rate index */
715 ath5k_set_total_hw_rates(sc);
716
717 /* NB: setup here so ath5k_rate_update is happy */
718 if (test_bit(AR5K_MODE_11A, ah->ah_modes))
719 ath5k_setcurmode(sc, AR5K_MODE_11A);
720 else
721 ath5k_setcurmode(sc, AR5K_MODE_11B);
722
723 /*
724 * Allocate tx+rx descriptors and populate the lists.
725 */
726 ret = ath5k_desc_alloc(sc, pdev);
727 if (ret) {
728 ATH5K_ERR(sc, "can't allocate descriptors\n");
729 goto err;
730 }
731
732 /*
733 * Allocate hardware transmit queues: one queue for
734 * beacon frames and one data queue for each QoS
735 * priority. Note that hw functions handle reseting
736 * these queues at the needed time.
737 */
738 ret = ath5k_beaconq_setup(ah);
739 if (ret < 0) {
740 ATH5K_ERR(sc, "can't setup a beacon xmit queue\n");
741 goto err_desc;
742 }
743 sc->bhalq = ret;
744
745 sc->txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
746 if (IS_ERR(sc->txq)) {
747 ATH5K_ERR(sc, "can't setup xmit queue\n");
748 ret = PTR_ERR(sc->txq);
749 goto err_bhal;
750 }
751
752 tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
753 tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
754 tasklet_init(&sc->restq, ath5k_tasklet_reset, (unsigned long)sc);
755 setup_timer(&sc->calib_tim, ath5k_calibrate, (unsigned long)sc);
756 setup_timer(&sc->led_tim, ath5k_led_off, (unsigned long)sc);
757
758 sc->led_on = 0; /* low true */
759 /*
760 * Auto-enable soft led processing for IBM cards and for
761 * 5211 minipci cards.
762 */
763 if (pdev->device == PCI_DEVICE_ID_ATHEROS_AR5212_IBM ||
764 pdev->device == PCI_DEVICE_ID_ATHEROS_AR5211) {
765 __set_bit(ATH_STAT_LEDSOFT, sc->status);
766 sc->led_pin = 0;
767 }
768 /* Enable softled on PIN1 on HP Compaq nc6xx, nc4000 & nx5000 laptops */
769 if (pdev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ) {
770 __set_bit(ATH_STAT_LEDSOFT, sc->status);
771 sc->led_pin = 0;
772 }
773 if (test_bit(ATH_STAT_LEDSOFT, sc->status)) {
774 ath5k_hw_set_gpio_output(ah, sc->led_pin);
775 ath5k_hw_set_gpio(ah, sc->led_pin, !sc->led_on);
776 }
777
778 ath5k_hw_get_lladdr(ah, mac);
779 SET_IEEE80211_PERM_ADDR(hw, mac);
780 /* All MAC address bits matter for ACKs */
781 memset(sc->bssidmask, 0xff, ETH_ALEN);
782 ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
783
784 ret = ieee80211_register_hw(hw);
785 if (ret) {
786 ATH5K_ERR(sc, "can't register ieee80211 hw\n");
787 goto err_queues;
788 }
789
790 return 0;
791 err_queues:
792 ath5k_txq_release(sc);
793 err_bhal:
794 ath5k_hw_release_tx_queue(ah, sc->bhalq);
795 err_desc:
796 ath5k_desc_free(sc, pdev);
797 err:
798 return ret;
799 }
800
801 static void
802 ath5k_detach(struct pci_dev *pdev, struct ieee80211_hw *hw)
803 {
804 struct ath5k_softc *sc = hw->priv;
805
806 /*
807 * NB: the order of these is important:
808 * o call the 802.11 layer before detaching ath5k_hw to
809 * insure callbacks into the driver to delete global
810 * key cache entries can be handled
811 * o reclaim the tx queue data structures after calling
812 * the 802.11 layer as we'll get called back to reclaim
813 * node state and potentially want to use them
814 * o to cleanup the tx queues the hal is called, so detach
815 * it last
816 * XXX: ??? detach ath5k_hw ???
817 * Other than that, it's straightforward...
818 */
819 ieee80211_unregister_hw(hw);
820 ath5k_desc_free(sc, pdev);
821 ath5k_txq_release(sc);
822 ath5k_hw_release_tx_queue(sc->ah, sc->bhalq);
823
824 /*
825 * NB: can't reclaim these until after ieee80211_ifdetach
826 * returns because we'll get called back to reclaim node
827 * state and potentially want to use them.
828 */
829 }
830
831
832
833
834 /********************\
835 * Channel/mode setup *
836 \********************/
837
838 /*
839 * Convert IEEE channel number to MHz frequency.
840 */
841 static inline short
842 ath5k_ieee2mhz(short chan)
843 {
844 if (chan <= 14 || chan >= 27)
845 return ieee80211chan2mhz(chan);
846 else
847 return 2212 + chan * 20;
848 }
849
850 static unsigned int
851 ath5k_copy_rates(struct ieee80211_rate *rates,
852 const struct ath5k_rate_table *rt,
853 unsigned int max)
854 {
855 unsigned int i, count;
856
857 if (rt == NULL)
858 return 0;
859
860 for (i = 0, count = 0; i < rt->rate_count && max > 0; i++) {
861 rates[count].bitrate = rt->rates[i].rate_kbps / 100;
862 rates[count].hw_value = rt->rates[i].rate_code;
863 rates[count].flags = rt->rates[i].modulation;
864 count++;
865 max--;
866 }
867
868 return count;
869 }
870
871 static unsigned int
872 ath5k_copy_channels(struct ath5k_hw *ah,
873 struct ieee80211_channel *channels,
874 unsigned int mode,
875 unsigned int max)
876 {
877 unsigned int i, count, size, chfreq, freq, ch;
878
879 if (!test_bit(mode, ah->ah_modes))
880 return 0;
881
882 switch (mode) {
883 case AR5K_MODE_11A:
884 case AR5K_MODE_11A_TURBO:
885 /* 1..220, but 2GHz frequencies are filtered by check_channel */
886 size = 220 ;
887 chfreq = CHANNEL_5GHZ;
888 break;
889 case AR5K_MODE_11B:
890 case AR5K_MODE_11G:
891 case AR5K_MODE_11G_TURBO:
892 size = 26;
893 chfreq = CHANNEL_2GHZ;
894 break;
895 default:
896 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n");
897 return 0;
898 }
899
900 for (i = 0, count = 0; i < size && max > 0; i++) {
901 ch = i + 1 ;
902 freq = ath5k_ieee2mhz(ch);
903
904 /* Check if channel is supported by the chipset */
905 if (!ath5k_channel_ok(ah, freq, chfreq))
906 continue;
907
908 /* Write channel info and increment counter */
909 channels[count].center_freq = freq;
910 channels[count].band = (chfreq == CHANNEL_2GHZ) ?
911 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
912 switch (mode) {
913 case AR5K_MODE_11A:
914 case AR5K_MODE_11G:
915 channels[count].hw_value = chfreq | CHANNEL_OFDM;
916 break;
917 case AR5K_MODE_11A_TURBO:
918 case AR5K_MODE_11G_TURBO:
919 channels[count].hw_value = chfreq |
920 CHANNEL_OFDM | CHANNEL_TURBO;
921 break;
922 case AR5K_MODE_11B:
923 channels[count].hw_value = CHANNEL_B;
924 }
925
926 count++;
927 max--;
928 }
929
930 return count;
931 }
932
933 static int
934 ath5k_getchannels(struct ieee80211_hw *hw)
935 {
936 struct ath5k_softc *sc = hw->priv;
937 struct ath5k_hw *ah = sc->ah;
938 struct ieee80211_supported_band *sbands = sc->sbands;
939 const struct ath5k_rate_table *hw_rates;
940 unsigned int max_r, max_c, count_r, count_c;
941 int mode2g = AR5K_MODE_11G;
942
943 BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS);
944
945 max_r = ARRAY_SIZE(sc->rates);
946 max_c = ARRAY_SIZE(sc->channels);
947 count_r = count_c = 0;
948
949 /* 2GHz band */
950 if (!test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) {
951 mode2g = AR5K_MODE_11B;
952 if (!test_bit(AR5K_MODE_11B,
953 sc->ah->ah_capabilities.cap_mode))
954 mode2g = -1;
955 }
956
957 if (mode2g > 0) {
958 struct ieee80211_supported_band *sband =
959 &sbands[IEEE80211_BAND_2GHZ];
960
961 sband->bitrates = sc->rates;
962 sband->channels = sc->channels;
963
964 sband->band = IEEE80211_BAND_2GHZ;
965 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
966 mode2g, max_c);
967
968 hw_rates = ath5k_hw_get_rate_table(ah, mode2g);
969 sband->n_bitrates = ath5k_copy_rates(sband->bitrates,
970 hw_rates, max_r);
971
972 count_c = sband->n_channels;
973 count_r = sband->n_bitrates;
974
975 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
976
977 max_r -= count_r;
978 max_c -= count_c;
979
980 }
981
982 /* 5GHz band */
983
984 if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) {
985 struct ieee80211_supported_band *sband =
986 &sbands[IEEE80211_BAND_5GHZ];
987
988 sband->bitrates = &sc->rates[count_r];
989 sband->channels = &sc->channels[count_c];
990
991 sband->band = IEEE80211_BAND_5GHZ;
992 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
993 AR5K_MODE_11A, max_c);
994
995 hw_rates = ath5k_hw_get_rate_table(ah, AR5K_MODE_11A);
996 sband->n_bitrates = ath5k_copy_rates(sband->bitrates,
997 hw_rates, max_r);
998
999 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
1000 }
1001
1002 ath5k_debug_dump_bands(sc);
1003
1004 return 0;
1005 }
1006
1007 /*
1008 * Set/change channels. If the channel is really being changed,
1009 * it's done by reseting the chip. To accomplish this we must
1010 * first cleanup any pending DMA, then restart stuff after a la
1011 * ath5k_init.
1012 */
1013 static int
1014 ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
1015 {
1016 struct ath5k_hw *ah = sc->ah;
1017 int ret;
1018
1019 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "(%u MHz) -> (%u MHz)\n",
1020 sc->curchan->center_freq, chan->center_freq);
1021
1022 if (chan->center_freq != sc->curchan->center_freq ||
1023 chan->hw_value != sc->curchan->hw_value) {
1024
1025 sc->curchan = chan;
1026 sc->curband = &sc->sbands[chan->band];
1027
1028 /*
1029 * To switch channels clear any pending DMA operations;
1030 * wait long enough for the RX fifo to drain, reset the
1031 * hardware at the new frequency, and then re-enable
1032 * the relevant bits of the h/w.
1033 */
1034 ath5k_hw_set_intr(ah, 0); /* disable interrupts */
1035 ath5k_txq_cleanup(sc); /* clear pending tx frames */
1036 ath5k_rx_stop(sc); /* turn off frame recv */
1037 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, true);
1038 if (ret) {
1039 ATH5K_ERR(sc, "%s: unable to reset channel "
1040 "(%u Mhz)\n", __func__, chan->center_freq);
1041 return ret;
1042 }
1043
1044 ath5k_hw_set_txpower_limit(sc->ah, 0);
1045
1046 /*
1047 * Re-enable rx framework.
1048 */
1049 ret = ath5k_rx_start(sc);
1050 if (ret) {
1051 ATH5K_ERR(sc, "%s: unable to restart recv logic\n",
1052 __func__);
1053 return ret;
1054 }
1055
1056 /*
1057 * Change channels and update the h/w rate map
1058 * if we're switching; e.g. 11a to 11b/g.
1059 *
1060 * XXX needed?
1061 */
1062 /* ath5k_chan_change(sc, chan); */
1063
1064 ath5k_beacon_config(sc);
1065 /*
1066 * Re-enable interrupts.
1067 */
1068 ath5k_hw_set_intr(ah, sc->imask);
1069 }
1070
1071 return 0;
1072 }
1073
1074 /*
1075 * TODO: CLEAN THIS !!!
1076 */
1077 static void
1078 ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode)
1079 {
1080 if (unlikely(test_bit(ATH_STAT_LEDSOFT, sc->status))) {
1081 /* from Atheros NDIS driver, w/ permission */
1082 static const struct {
1083 u16 rate; /* tx/rx 802.11 rate */
1084 u16 timeOn; /* LED on time (ms) */
1085 u16 timeOff; /* LED off time (ms) */
1086 } blinkrates[] = {
1087 { 108, 40, 10 },
1088 { 96, 44, 11 },
1089 { 72, 50, 13 },
1090 { 48, 57, 14 },
1091 { 36, 67, 16 },
1092 { 24, 80, 20 },
1093 { 22, 100, 25 },
1094 { 18, 133, 34 },
1095 { 12, 160, 40 },
1096 { 10, 200, 50 },
1097 { 6, 240, 58 },
1098 { 4, 267, 66 },
1099 { 2, 400, 100 },
1100 { 0, 500, 130 }
1101 };
1102 const struct ath5k_rate_table *rt =
1103 ath5k_hw_get_rate_table(sc->ah, mode);
1104 unsigned int i, j;
1105
1106 BUG_ON(rt == NULL);
1107
1108 memset(sc->hwmap, 0, sizeof(sc->hwmap));
1109 for (i = 0; i < 32; i++) {
1110 u8 ix = rt->rate_code_to_index[i];
1111 if (ix == 0xff) {
1112 sc->hwmap[i].ledon = msecs_to_jiffies(500);
1113 sc->hwmap[i].ledoff = msecs_to_jiffies(130);
1114 continue;
1115 }
1116 sc->hwmap[i].txflags = IEEE80211_RADIOTAP_F_DATAPAD;
1117 /* receive frames include FCS */
1118 sc->hwmap[i].rxflags = sc->hwmap[i].txflags |
1119 IEEE80211_RADIOTAP_F_FCS;
1120 /* setup blink rate table to avoid per-packet lookup */
1121 for (j = 0; j < ARRAY_SIZE(blinkrates) - 1; j++)
1122 if (blinkrates[j].rate == /* XXX why 7f? */
1123 (rt->rates[ix].dot11_rate&0x7f))
1124 break;
1125
1126 sc->hwmap[i].ledon = msecs_to_jiffies(blinkrates[j].
1127 timeOn);
1128 sc->hwmap[i].ledoff = msecs_to_jiffies(blinkrates[j].
1129 timeOff);
1130 }
1131 }
1132
1133 sc->curmode = mode;
1134
1135 if (mode == AR5K_MODE_11A) {
1136 sc->curband = &sc->sbands[IEEE80211_BAND_5GHZ];
1137 } else {
1138 sc->curband = &sc->sbands[IEEE80211_BAND_2GHZ];
1139 }
1140 }
1141
1142 static void
1143 ath5k_mode_setup(struct ath5k_softc *sc)
1144 {
1145 struct ath5k_hw *ah = sc->ah;
1146 u32 rfilt;
1147
1148 /* configure rx filter */
1149 rfilt = sc->filter_flags;
1150 ath5k_hw_set_rx_filter(ah, rfilt);
1151
1152 if (ath5k_hw_hasbssidmask(ah))
1153 ath5k_hw_set_bssid_mask(ah, sc->bssidmask);
1154
1155 /* configure operational mode */
1156 ath5k_hw_set_opmode(ah);
1157
1158 ath5k_hw_set_mcast_filter(ah, 0, 0);
1159 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
1160 }
1161
1162 /*
1163 * Match the hw provided rate index (through descriptors)
1164 * to an index for sc->curband->bitrates, so it can be used
1165 * by the stack.
1166 *
1167 * This one is a little bit tricky but i think i'm right
1168 * about this...
1169 *
1170 * We have 4 rate tables in the following order:
1171 * XR (4 rates)
1172 * 802.11a (8 rates)
1173 * 802.11b (4 rates)
1174 * 802.11g (12 rates)
1175 * that make the hw rate table.
1176 *
1177 * Lets take a 5211 for example that supports a and b modes only.
1178 * First comes the 802.11a table and then 802.11b (total 12 rates).
1179 * When hw returns eg. 11 it points to the last 802.11b rate (11Mbit),
1180 * if it returns 2 it points to the second 802.11a rate etc.
1181 *
1182 * Same goes for 5212 who has xr/a/b/g support (total 28 rates).
1183 * First comes the XR table, then 802.11a, 802.11b and 802.11g.
1184 * When hw returns eg. 27 it points to the last 802.11g rate (54Mbits) etc
1185 */
1186 static void
1187 ath5k_set_total_hw_rates(struct ath5k_softc *sc) {
1188
1189 struct ath5k_hw *ah = sc->ah;
1190
1191 if (test_bit(AR5K_MODE_11A, ah->ah_modes))
1192 sc->a_rates = 8;
1193
1194 if (test_bit(AR5K_MODE_11B, ah->ah_modes))
1195 sc->b_rates = 4;
1196
1197 if (test_bit(AR5K_MODE_11G, ah->ah_modes))
1198 sc->g_rates = 12;
1199
1200 /* XXX: Need to see what what happens when
1201 xr disable bits in eeprom are set */
1202 if (ah->ah_version >= AR5K_AR5212)
1203 sc->xr_rates = 4;
1204
1205 }
1206
1207 static inline int
1208 ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix) {
1209
1210 int mac80211_rix;
1211
1212 if(sc->curband->band == IEEE80211_BAND_2GHZ) {
1213 /* We setup a g ratetable for both b/g modes */
1214 mac80211_rix =
1215 hw_rix - sc->b_rates - sc->a_rates - sc->xr_rates;
1216 } else {
1217 mac80211_rix = hw_rix - sc->xr_rates;
1218 }
1219
1220 /* Something went wrong, fallback to basic rate for this band */
1221 if ((mac80211_rix >= sc->curband->n_bitrates) ||
1222 (mac80211_rix <= 0 ))
1223 mac80211_rix = 1;
1224
1225 return mac80211_rix;
1226 }
1227
1228
1229
1230
1231 /***************\
1232 * Buffers setup *
1233 \***************/
1234
1235 static int
1236 ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1237 {
1238 struct ath5k_hw *ah = sc->ah;
1239 struct sk_buff *skb = bf->skb;
1240 struct ath5k_desc *ds;
1241
1242 if (likely(skb == NULL)) {
1243 unsigned int off;
1244
1245 /*
1246 * Allocate buffer with headroom_needed space for the
1247 * fake physical layer header at the start.
1248 */
1249 skb = dev_alloc_skb(sc->rxbufsize + sc->cachelsz - 1);
1250 if (unlikely(skb == NULL)) {
1251 ATH5K_ERR(sc, "can't alloc skbuff of size %u\n",
1252 sc->rxbufsize + sc->cachelsz - 1);
1253 return -ENOMEM;
1254 }
1255 /*
1256 * Cache-line-align. This is important (for the
1257 * 5210 at least) as not doing so causes bogus data
1258 * in rx'd frames.
1259 */
1260 off = ((unsigned long)skb->data) % sc->cachelsz;
1261 if (off != 0)
1262 skb_reserve(skb, sc->cachelsz - off);
1263
1264 bf->skb = skb;
1265 bf->skbaddr = pci_map_single(sc->pdev,
1266 skb->data, sc->rxbufsize, PCI_DMA_FROMDEVICE);
1267 if (unlikely(pci_dma_mapping_error(bf->skbaddr))) {
1268 ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__);
1269 dev_kfree_skb(skb);
1270 bf->skb = NULL;
1271 return -ENOMEM;
1272 }
1273 }
1274
1275 /*
1276 * Setup descriptors. For receive we always terminate
1277 * the descriptor list with a self-linked entry so we'll
1278 * not get overrun under high load (as can happen with a
1279 * 5212 when ANI processing enables PHY error frames).
1280 *
1281 * To insure the last descriptor is self-linked we create
1282 * each descriptor as self-linked and add it to the end. As
1283 * each additional descriptor is added the previous self-linked
1284 * entry is ``fixed'' naturally. This should be safe even
1285 * if DMA is happening. When processing RX interrupts we
1286 * never remove/process the last, self-linked, entry on the
1287 * descriptor list. This insures the hardware always has
1288 * someplace to write a new frame.
1289 */
1290 ds = bf->desc;
1291 ds->ds_link = bf->daddr; /* link to self */
1292 ds->ds_data = bf->skbaddr;
1293 ath5k_hw_setup_rx_desc(ah, ds,
1294 skb_tailroom(skb), /* buffer size */
1295 0);
1296
1297 if (sc->rxlink != NULL)
1298 *sc->rxlink = bf->daddr;
1299 sc->rxlink = &ds->ds_link;
1300 return 0;
1301 }
1302
1303 static int
1304 ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf,
1305 struct ieee80211_tx_control *ctl)
1306 {
1307 struct ath5k_hw *ah = sc->ah;
1308 struct ath5k_txq *txq = sc->txq;
1309 struct ath5k_desc *ds = bf->desc;
1310 struct sk_buff *skb = bf->skb;
1311 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
1312 int ret;
1313
1314 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
1315 bf->ctl = *ctl;
1316 /* XXX endianness */
1317 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1318 PCI_DMA_TODEVICE);
1319
1320 if (ctl->flags & IEEE80211_TXCTL_NO_ACK)
1321 flags |= AR5K_TXDESC_NOACK;
1322
1323 pktlen = skb->len;
1324
1325 if (!(ctl->flags & IEEE80211_TXCTL_DO_NOT_ENCRYPT)) {
1326 keyidx = ctl->key_idx;
1327 pktlen += ctl->icv_len;
1328 }
1329
1330 ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
1331 ieee80211_get_hdrlen_from_skb(skb), AR5K_PKT_TYPE_NORMAL,
1332 (sc->power_level * 2), ctl->tx_rate->hw_value,
1333 ctl->retry_limit, keyidx, 0, flags, 0, 0);
1334 if (ret)
1335 goto err_unmap;
1336
1337 ds->ds_link = 0;
1338 ds->ds_data = bf->skbaddr;
1339
1340 spin_lock_bh(&txq->lock);
1341 list_add_tail(&bf->list, &txq->q);
1342 sc->tx_stats.data[txq->qnum].len++;
1343 if (txq->link == NULL) /* is this first packet? */
1344 ath5k_hw_put_tx_buf(ah, txq->qnum, bf->daddr);
1345 else /* no, so only link it */
1346 *txq->link = bf->daddr;
1347
1348 txq->link = &ds->ds_link;
1349 ath5k_hw_tx_start(ah, txq->qnum);
1350 spin_unlock_bh(&txq->lock);
1351
1352 return 0;
1353 err_unmap:
1354 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1355 return ret;
1356 }
1357
1358 /*******************\
1359 * Descriptors setup *
1360 \*******************/
1361
1362 static int
1363 ath5k_desc_alloc(struct ath5k_softc *sc, struct pci_dev *pdev)
1364 {
1365 struct ath5k_desc *ds;
1366 struct ath5k_buf *bf;
1367 dma_addr_t da;
1368 unsigned int i;
1369 int ret;
1370
1371 /* allocate descriptors */
1372 sc->desc_len = sizeof(struct ath5k_desc) *
1373 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
1374 sc->desc = pci_alloc_consistent(pdev, sc->desc_len, &sc->desc_daddr);
1375 if (sc->desc == NULL) {
1376 ATH5K_ERR(sc, "can't allocate descriptors\n");
1377 ret = -ENOMEM;
1378 goto err;
1379 }
1380 ds = sc->desc;
1381 da = sc->desc_daddr;
1382 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
1383 ds, sc->desc_len, (unsigned long long)sc->desc_daddr);
1384
1385 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
1386 sizeof(struct ath5k_buf), GFP_KERNEL);
1387 if (bf == NULL) {
1388 ATH5K_ERR(sc, "can't allocate bufptr\n");
1389 ret = -ENOMEM;
1390 goto err_free;
1391 }
1392 sc->bufptr = bf;
1393
1394 INIT_LIST_HEAD(&sc->rxbuf);
1395 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
1396 bf->desc = ds;
1397 bf->daddr = da;
1398 list_add_tail(&bf->list, &sc->rxbuf);
1399 }
1400
1401 INIT_LIST_HEAD(&sc->txbuf);
1402 sc->txbuf_len = ATH_TXBUF;
1403 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++,
1404 da += sizeof(*ds)) {
1405 bf->desc = ds;
1406 bf->daddr = da;
1407 list_add_tail(&bf->list, &sc->txbuf);
1408 }
1409
1410 /* beacon buffer */
1411 bf->desc = ds;
1412 bf->daddr = da;
1413 sc->bbuf = bf;
1414
1415 return 0;
1416 err_free:
1417 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1418 err:
1419 sc->desc = NULL;
1420 return ret;
1421 }
1422
1423 static void
1424 ath5k_desc_free(struct ath5k_softc *sc, struct pci_dev *pdev)
1425 {
1426 struct ath5k_buf *bf;
1427
1428 ath5k_txbuf_free(sc, sc->bbuf);
1429 list_for_each_entry(bf, &sc->txbuf, list)
1430 ath5k_txbuf_free(sc, bf);
1431 list_for_each_entry(bf, &sc->rxbuf, list)
1432 ath5k_txbuf_free(sc, bf);
1433
1434 /* Free memory associated with all descriptors */
1435 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1436
1437 kfree(sc->bufptr);
1438 sc->bufptr = NULL;
1439 }
1440
1441
1442
1443
1444
1445 /**************\
1446 * Queues setup *
1447 \**************/
1448
1449 static struct ath5k_txq *
1450 ath5k_txq_setup(struct ath5k_softc *sc,
1451 int qtype, int subtype)
1452 {
1453 struct ath5k_hw *ah = sc->ah;
1454 struct ath5k_txq *txq;
1455 struct ath5k_txq_info qi = {
1456 .tqi_subtype = subtype,
1457 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1458 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1459 .tqi_cw_max = AR5K_TXQ_USEDEFAULT
1460 };
1461 int qnum;
1462
1463 /*
1464 * Enable interrupts only for EOL and DESC conditions.
1465 * We mark tx descriptors to receive a DESC interrupt
1466 * when a tx queue gets deep; otherwise waiting for the
1467 * EOL to reap descriptors. Note that this is done to
1468 * reduce interrupt load and this only defers reaping
1469 * descriptors, never transmitting frames. Aside from
1470 * reducing interrupts this also permits more concurrency.
1471 * The only potential downside is if the tx queue backs
1472 * up in which case the top half of the kernel may backup
1473 * due to a lack of tx descriptors.
1474 */
1475 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
1476 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
1477 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
1478 if (qnum < 0) {
1479 /*
1480 * NB: don't print a message, this happens
1481 * normally on parts with too few tx queues
1482 */
1483 return ERR_PTR(qnum);
1484 }
1485 if (qnum >= ARRAY_SIZE(sc->txqs)) {
1486 ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n",
1487 qnum, ARRAY_SIZE(sc->txqs));
1488 ath5k_hw_release_tx_queue(ah, qnum);
1489 return ERR_PTR(-EINVAL);
1490 }
1491 txq = &sc->txqs[qnum];
1492 if (!txq->setup) {
1493 txq->qnum = qnum;
1494 txq->link = NULL;
1495 INIT_LIST_HEAD(&txq->q);
1496 spin_lock_init(&txq->lock);
1497 txq->setup = true;
1498 }
1499 return &sc->txqs[qnum];
1500 }
1501
1502 static int
1503 ath5k_beaconq_setup(struct ath5k_hw *ah)
1504 {
1505 struct ath5k_txq_info qi = {
1506 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1507 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1508 .tqi_cw_max = AR5K_TXQ_USEDEFAULT,
1509 /* NB: for dynamic turbo, don't enable any other interrupts */
1510 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
1511 };
1512
1513 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
1514 }
1515
1516 static int
1517 ath5k_beaconq_config(struct ath5k_softc *sc)
1518 {
1519 struct ath5k_hw *ah = sc->ah;
1520 struct ath5k_txq_info qi;
1521 int ret;
1522
1523 ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi);
1524 if (ret)
1525 return ret;
1526 if (sc->opmode == IEEE80211_IF_TYPE_AP) {
1527 /*
1528 * Always burst out beacon and CAB traffic
1529 * (aifs = cwmin = cwmax = 0)
1530 */
1531 qi.tqi_aifs = 0;
1532 qi.tqi_cw_min = 0;
1533 qi.tqi_cw_max = 0;
1534 } else if (sc->opmode == IEEE80211_IF_TYPE_IBSS) {
1535 /*
1536 * Adhoc mode; backoff between 0 and (2 * cw_min).
1537 */
1538 qi.tqi_aifs = 0;
1539 qi.tqi_cw_min = 0;
1540 qi.tqi_cw_max = 2 * ah->ah_cw_min;
1541 }
1542
1543 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1544 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1545 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
1546
1547 ret = ath5k_hw_setup_tx_queueprops(ah, sc->bhalq, &qi);
1548 if (ret) {
1549 ATH5K_ERR(sc, "%s: unable to update parameters for beacon "
1550 "hardware queue!\n", __func__);
1551 return ret;
1552 }
1553
1554 return ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */;
1555 }
1556
1557 static void
1558 ath5k_txq_drainq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1559 {
1560 struct ath5k_buf *bf, *bf0;
1561
1562 /*
1563 * NB: this assumes output has been stopped and
1564 * we do not need to block ath5k_tx_tasklet
1565 */
1566 spin_lock_bh(&txq->lock);
1567 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1568 ath5k_debug_printtxbuf(sc, bf);
1569
1570 ath5k_txbuf_free(sc, bf);
1571
1572 spin_lock_bh(&sc->txbuflock);
1573 sc->tx_stats.data[txq->qnum].len--;
1574 list_move_tail(&bf->list, &sc->txbuf);
1575 sc->txbuf_len++;
1576 spin_unlock_bh(&sc->txbuflock);
1577 }
1578 txq->link = NULL;
1579 spin_unlock_bh(&txq->lock);
1580 }
1581
1582 /*
1583 * Drain the transmit queues and reclaim resources.
1584 */
1585 static void
1586 ath5k_txq_cleanup(struct ath5k_softc *sc)
1587 {
1588 struct ath5k_hw *ah = sc->ah;
1589 unsigned int i;
1590
1591 /* XXX return value */
1592 if (likely(!test_bit(ATH_STAT_INVALID, sc->status))) {
1593 /* don't touch the hardware if marked invalid */
1594 ath5k_hw_stop_tx_dma(ah, sc->bhalq);
1595 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "beacon queue %x\n",
1596 ath5k_hw_get_tx_buf(ah, sc->bhalq));
1597 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1598 if (sc->txqs[i].setup) {
1599 ath5k_hw_stop_tx_dma(ah, sc->txqs[i].qnum);
1600 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "txq [%u] %x, "
1601 "link %p\n",
1602 sc->txqs[i].qnum,
1603 ath5k_hw_get_tx_buf(ah,
1604 sc->txqs[i].qnum),
1605 sc->txqs[i].link);
1606 }
1607 }
1608 ieee80211_start_queues(sc->hw); /* XXX move to callers */
1609
1610 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1611 if (sc->txqs[i].setup)
1612 ath5k_txq_drainq(sc, &sc->txqs[i]);
1613 }
1614
1615 static void
1616 ath5k_txq_release(struct ath5k_softc *sc)
1617 {
1618 struct ath5k_txq *txq = sc->txqs;
1619 unsigned int i;
1620
1621 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++)
1622 if (txq->setup) {
1623 ath5k_hw_release_tx_queue(sc->ah, txq->qnum);
1624 txq->setup = false;
1625 }
1626 }
1627
1628
1629
1630
1631 /*************\
1632 * RX Handling *
1633 \*************/
1634
1635 /*
1636 * Enable the receive h/w following a reset.
1637 */
1638 static int
1639 ath5k_rx_start(struct ath5k_softc *sc)
1640 {
1641 struct ath5k_hw *ah = sc->ah;
1642 struct ath5k_buf *bf;
1643 int ret;
1644
1645 sc->rxbufsize = roundup(IEEE80211_MAX_LEN, sc->cachelsz);
1646
1647 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rxbufsize %u\n",
1648 sc->cachelsz, sc->rxbufsize);
1649
1650 sc->rxlink = NULL;
1651
1652 spin_lock_bh(&sc->rxbuflock);
1653 list_for_each_entry(bf, &sc->rxbuf, list) {
1654 ret = ath5k_rxbuf_setup(sc, bf);
1655 if (ret != 0) {
1656 spin_unlock_bh(&sc->rxbuflock);
1657 goto err;
1658 }
1659 }
1660 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1661 spin_unlock_bh(&sc->rxbuflock);
1662
1663 ath5k_hw_put_rx_buf(ah, bf->daddr);
1664 ath5k_hw_start_rx(ah); /* enable recv descriptors */
1665 ath5k_mode_setup(sc); /* set filters, etc. */
1666 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
1667
1668 return 0;
1669 err:
1670 return ret;
1671 }
1672
1673 /*
1674 * Disable the receive h/w in preparation for a reset.
1675 */
1676 static void
1677 ath5k_rx_stop(struct ath5k_softc *sc)
1678 {
1679 struct ath5k_hw *ah = sc->ah;
1680
1681 ath5k_hw_stop_pcu_recv(ah); /* disable PCU */
1682 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */
1683 ath5k_hw_stop_rx_dma(ah); /* disable DMA engine */
1684 mdelay(3); /* 3ms is long enough for 1 frame */
1685
1686 ath5k_debug_printrxbuffs(sc, ah);
1687
1688 sc->rxlink = NULL; /* just in case */
1689 }
1690
1691 static unsigned int
1692 ath5k_rx_decrypted(struct ath5k_softc *sc, struct ath5k_desc *ds,
1693 struct sk_buff *skb, struct ath5k_rx_status *rs)
1694 {
1695 struct ieee80211_hdr *hdr = (void *)skb->data;
1696 unsigned int keyix, hlen = ieee80211_get_hdrlen_from_skb(skb);
1697
1698 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1699 rs->rs_keyix != AR5K_RXKEYIX_INVALID)
1700 return RX_FLAG_DECRYPTED;
1701
1702 /* Apparently when a default key is used to decrypt the packet
1703 the hw does not set the index used to decrypt. In such cases
1704 get the index from the packet. */
1705 if ((le16_to_cpu(hdr->frame_control) & IEEE80211_FCTL_PROTECTED) &&
1706 !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1707 skb->len >= hlen + 4) {
1708 keyix = skb->data[hlen + 3] >> 6;
1709
1710 if (test_bit(keyix, sc->keymap))
1711 return RX_FLAG_DECRYPTED;
1712 }
1713
1714 return 0;
1715 }
1716
1717
1718 static void
1719 ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb,
1720 struct ieee80211_rx_status *rxs)
1721 {
1722 u64 tsf, bc_tstamp;
1723 u32 hw_tu;
1724 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1725
1726 if ((le16_to_cpu(mgmt->frame_control) & IEEE80211_FCTL_FTYPE) ==
1727 IEEE80211_FTYPE_MGMT &&
1728 (le16_to_cpu(mgmt->frame_control) & IEEE80211_FCTL_STYPE) ==
1729 IEEE80211_STYPE_BEACON &&
1730 le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS &&
1731 memcmp(mgmt->bssid, sc->ah->ah_bssid, ETH_ALEN) == 0) {
1732 /*
1733 * Received an IBSS beacon with the same BSSID. Hardware *must*
1734 * have updated the local TSF. We have to work around various
1735 * hardware bugs, though...
1736 */
1737 tsf = ath5k_hw_get_tsf64(sc->ah);
1738 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
1739 hw_tu = TSF_TO_TU(tsf);
1740
1741 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1742 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
1743 (unsigned long long)bc_tstamp,
1744 (unsigned long long)rxs->mactime,
1745 (unsigned long long)(rxs->mactime - bc_tstamp),
1746 (unsigned long long)tsf);
1747
1748 /*
1749 * Sometimes the HW will give us a wrong tstamp in the rx
1750 * status, causing the timestamp extension to go wrong.
1751 * (This seems to happen especially with beacon frames bigger
1752 * than 78 byte (incl. FCS))
1753 * But we know that the receive timestamp must be later than the
1754 * timestamp of the beacon since HW must have synced to that.
1755 *
1756 * NOTE: here we assume mactime to be after the frame was
1757 * received, not like mac80211 which defines it at the start.
1758 */
1759 if (bc_tstamp > rxs->mactime) {
1760 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1761 "fixing mactime from %llx to %llx\n",
1762 (unsigned long long)rxs->mactime,
1763 (unsigned long long)tsf);
1764 rxs->mactime = tsf;
1765 }
1766
1767 /*
1768 * Local TSF might have moved higher than our beacon timers,
1769 * in that case we have to update them to continue sending
1770 * beacons. This also takes care of synchronizing beacon sending
1771 * times with other stations.
1772 */
1773 if (hw_tu >= sc->nexttbtt)
1774 ath5k_beacon_update_timers(sc, bc_tstamp);
1775 }
1776 }
1777
1778
1779 static void
1780 ath5k_tasklet_rx(unsigned long data)
1781 {
1782 struct ieee80211_rx_status rxs = {};
1783 struct ath5k_rx_status rs = {};
1784 struct sk_buff *skb;
1785 struct ath5k_softc *sc = (void *)data;
1786 struct ath5k_buf *bf;
1787 struct ath5k_desc *ds;
1788 int ret;
1789 int hdrlen;
1790 int pad;
1791
1792 spin_lock(&sc->rxbuflock);
1793 do {
1794 if (unlikely(list_empty(&sc->rxbuf))) {
1795 ATH5K_WARN(sc, "empty rx buf pool\n");
1796 break;
1797 }
1798 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1799 BUG_ON(bf->skb == NULL);
1800 skb = bf->skb;
1801 ds = bf->desc;
1802
1803 /* TODO only one segment */
1804 pci_dma_sync_single_for_cpu(sc->pdev, sc->desc_daddr,
1805 sc->desc_len, PCI_DMA_FROMDEVICE);
1806
1807 if (unlikely(ds->ds_link == bf->daddr)) /* this is the end */
1808 break;
1809
1810 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs);
1811 if (unlikely(ret == -EINPROGRESS))
1812 break;
1813 else if (unlikely(ret)) {
1814 ATH5K_ERR(sc, "error in processing rx descriptor\n");
1815 spin_unlock(&sc->rxbuflock);
1816 return;
1817 }
1818
1819 if (unlikely(rs.rs_more)) {
1820 ATH5K_WARN(sc, "unsupported jumbo\n");
1821 goto next;
1822 }
1823
1824 if (unlikely(rs.rs_status)) {
1825 if (rs.rs_status & AR5K_RXERR_PHY)
1826 goto next;
1827 if (rs.rs_status & AR5K_RXERR_DECRYPT) {
1828 /*
1829 * Decrypt error. If the error occurred
1830 * because there was no hardware key, then
1831 * let the frame through so the upper layers
1832 * can process it. This is necessary for 5210
1833 * parts which have no way to setup a ``clear''
1834 * key cache entry.
1835 *
1836 * XXX do key cache faulting
1837 */
1838 if (rs.rs_keyix == AR5K_RXKEYIX_INVALID &&
1839 !(rs.rs_status & AR5K_RXERR_CRC))
1840 goto accept;
1841 }
1842 if (rs.rs_status & AR5K_RXERR_MIC) {
1843 rxs.flag |= RX_FLAG_MMIC_ERROR;
1844 goto accept;
1845 }
1846
1847 /* let crypto-error packets fall through in MNTR */
1848 if ((rs.rs_status &
1849 ~(AR5K_RXERR_DECRYPT|AR5K_RXERR_MIC)) ||
1850 sc->opmode != IEEE80211_IF_TYPE_MNTR)
1851 goto next;
1852 }
1853 accept:
1854 pci_dma_sync_single_for_cpu(sc->pdev, bf->skbaddr,
1855 rs.rs_datalen, PCI_DMA_FROMDEVICE);
1856 pci_unmap_single(sc->pdev, bf->skbaddr, sc->rxbufsize,
1857 PCI_DMA_FROMDEVICE);
1858 bf->skb = NULL;
1859
1860 skb_put(skb, rs.rs_datalen);
1861
1862 /*
1863 * the hardware adds a padding to 4 byte boundaries between
1864 * the header and the payload data if the header length is
1865 * not multiples of 4 - remove it
1866 */
1867 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1868 if (hdrlen & 3) {
1869 pad = hdrlen % 4;
1870 memmove(skb->data + pad, skb->data, hdrlen);
1871 skb_pull(skb, pad);
1872 }
1873
1874 /*
1875 * always extend the mac timestamp, since this information is
1876 * also needed for proper IBSS merging.
1877 *
1878 * XXX: it might be too late to do it here, since rs_tstamp is
1879 * 15bit only. that means TSF extension has to be done within
1880 * 32768usec (about 32ms). it might be necessary to move this to
1881 * the interrupt handler, like it is done in madwifi.
1882 *
1883 * Unfortunately we don't know when the hardware takes the rx
1884 * timestamp (beginning of phy frame, data frame, end of rx?).
1885 * The only thing we know is that it is hardware specific...
1886 * On AR5213 it seems the rx timestamp is at the end of the
1887 * frame, but i'm not sure.
1888 *
1889 * NOTE: mac80211 defines mactime at the beginning of the first
1890 * data symbol. Since we don't have any time references it's
1891 * impossible to comply to that. This affects IBSS merge only
1892 * right now, so it's not too bad...
1893 */
1894 rxs.mactime = ath5k_extend_tsf(sc->ah, rs.rs_tstamp);
1895 rxs.flag |= RX_FLAG_TSFT;
1896
1897 rxs.freq = sc->curchan->center_freq;
1898 rxs.band = sc->curband->band;
1899
1900 /*
1901 * signal quality:
1902 * the names here are misleading and the usage of these
1903 * values by iwconfig makes it even worse
1904 */
1905 /* noise floor in dBm, from the last noise calibration */
1906 rxs.noise = sc->ah->ah_noise_floor;
1907 /* signal level in dBm */
1908 rxs.ssi = rxs.noise + rs.rs_rssi;
1909 /*
1910 * "signal" is actually displayed as Link Quality by iwconfig
1911 * we provide a percentage based on rssi (assuming max rssi 64)
1912 */
1913 rxs.signal = rs.rs_rssi * 100 / 64;
1914
1915 rxs.antenna = rs.rs_antenna;
1916 rxs.rate_idx = ath5k_hw_to_driver_rix(sc, rs.rs_rate);
1917 rxs.flag |= ath5k_rx_decrypted(sc, ds, skb, &rs);
1918
1919 ath5k_debug_dump_skb(sc, skb, "RX ", 0);
1920
1921 /* check beacons in IBSS mode */
1922 if (sc->opmode == IEEE80211_IF_TYPE_IBSS)
1923 ath5k_check_ibss_tsf(sc, skb, &rxs);
1924
1925 __ieee80211_rx(sc->hw, skb, &rxs);
1926 sc->led_rxrate = rs.rs_rate;
1927 ath5k_led_event(sc, ATH_LED_RX);
1928 next:
1929 list_move_tail(&bf->list, &sc->rxbuf);
1930 } while (ath5k_rxbuf_setup(sc, bf) == 0);
1931 spin_unlock(&sc->rxbuflock);
1932 }
1933
1934
1935
1936
1937 /*************\
1938 * TX Handling *
1939 \*************/
1940
1941 static void
1942 ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1943 {
1944 struct ieee80211_tx_status txs = {};
1945 struct ath5k_tx_status ts = {};
1946 struct ath5k_buf *bf, *bf0;
1947 struct ath5k_desc *ds;
1948 struct sk_buff *skb;
1949 int ret;
1950
1951 spin_lock(&txq->lock);
1952 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1953 ds = bf->desc;
1954
1955 /* TODO only one segment */
1956 pci_dma_sync_single_for_cpu(sc->pdev, sc->desc_daddr,
1957 sc->desc_len, PCI_DMA_FROMDEVICE);
1958 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts);
1959 if (unlikely(ret == -EINPROGRESS))
1960 break;
1961 else if (unlikely(ret)) {
1962 ATH5K_ERR(sc, "error %d while processing queue %u\n",
1963 ret, txq->qnum);
1964 break;
1965 }
1966
1967 skb = bf->skb;
1968 bf->skb = NULL;
1969 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len,
1970 PCI_DMA_TODEVICE);
1971
1972 txs.control = bf->ctl;
1973 txs.retry_count = ts.ts_shortretry + ts.ts_longretry / 6;
1974 if (unlikely(ts.ts_status)) {
1975 sc->ll_stats.dot11ACKFailureCount++;
1976 if (ts.ts_status & AR5K_TXERR_XRETRY)
1977 txs.excessive_retries = 1;
1978 else if (ts.ts_status & AR5K_TXERR_FILT)
1979 txs.flags |= IEEE80211_TX_STATUS_TX_FILTERED;
1980 } else {
1981 txs.flags |= IEEE80211_TX_STATUS_ACK;
1982 txs.ack_signal = ts.ts_rssi;
1983 }
1984
1985 ieee80211_tx_status(sc->hw, skb, &txs);
1986 sc->tx_stats.data[txq->qnum].count++;
1987
1988 spin_lock(&sc->txbuflock);
1989 sc->tx_stats.data[txq->qnum].len--;
1990 list_move_tail(&bf->list, &sc->txbuf);
1991 sc->txbuf_len++;
1992 spin_unlock(&sc->txbuflock);
1993 }
1994 if (likely(list_empty(&txq->q)))
1995 txq->link = NULL;
1996 spin_unlock(&txq->lock);
1997 if (sc->txbuf_len > ATH_TXBUF / 5)
1998 ieee80211_wake_queues(sc->hw);
1999 }
2000
2001 static void
2002 ath5k_tasklet_tx(unsigned long data)
2003 {
2004 struct ath5k_softc *sc = (void *)data;
2005
2006 ath5k_tx_processq(sc, sc->txq);
2007
2008 ath5k_led_event(sc, ATH_LED_TX);
2009 }
2010
2011
2012
2013
2014 /*****************\
2015 * Beacon handling *
2016 \*****************/
2017
2018 /*
2019 * Setup the beacon frame for transmit.
2020 */
2021 static int
2022 ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf,
2023 struct ieee80211_tx_control *ctl)
2024 {
2025 struct sk_buff *skb = bf->skb;
2026 struct ath5k_hw *ah = sc->ah;
2027 struct ath5k_desc *ds;
2028 int ret, antenna = 0;
2029 u32 flags;
2030
2031 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
2032 PCI_DMA_TODEVICE);
2033 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
2034 "skbaddr %llx\n", skb, skb->data, skb->len,
2035 (unsigned long long)bf->skbaddr);
2036 if (pci_dma_mapping_error(bf->skbaddr)) {
2037 ATH5K_ERR(sc, "beacon DMA mapping failed\n");
2038 return -EIO;
2039 }
2040
2041 ds = bf->desc;
2042
2043 flags = AR5K_TXDESC_NOACK;
2044 if (sc->opmode == IEEE80211_IF_TYPE_IBSS && ath5k_hw_hasveol(ah)) {
2045 ds->ds_link = bf->daddr; /* self-linked */
2046 flags |= AR5K_TXDESC_VEOL;
2047 /*
2048 * Let hardware handle antenna switching if txantenna is not set
2049 */
2050 } else {
2051 ds->ds_link = 0;
2052 /*
2053 * Switch antenna every 4 beacons if txantenna is not set
2054 * XXX assumes two antennas
2055 */
2056 if (antenna == 0)
2057 antenna = sc->bsent & 4 ? 2 : 1;
2058 }
2059
2060 ds->ds_data = bf->skbaddr;
2061 ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
2062 ieee80211_get_hdrlen_from_skb(skb),
2063 AR5K_PKT_TYPE_BEACON, (sc->power_level * 2),
2064 ctl->tx_rate->hw_value, 1, AR5K_TXKEYIX_INVALID,
2065 antenna, flags, 0, 0);
2066 if (ret)
2067 goto err_unmap;
2068
2069 return 0;
2070 err_unmap:
2071 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
2072 return ret;
2073 }
2074
2075 /*
2076 * Transmit a beacon frame at SWBA. Dynamic updates to the
2077 * frame contents are done as needed and the slot time is
2078 * also adjusted based on current state.
2079 *
2080 * this is usually called from interrupt context (ath5k_intr())
2081 * but also from ath5k_beacon_config() in IBSS mode which in turn
2082 * can be called from a tasklet and user context
2083 */
2084 static void
2085 ath5k_beacon_send(struct ath5k_softc *sc)
2086 {
2087 struct ath5k_buf *bf = sc->bbuf;
2088 struct ath5k_hw *ah = sc->ah;
2089
2090 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n");
2091
2092 if (unlikely(bf->skb == NULL || sc->opmode == IEEE80211_IF_TYPE_STA ||
2093 sc->opmode == IEEE80211_IF_TYPE_MNTR)) {
2094 ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
2095 return;
2096 }
2097 /*
2098 * Check if the previous beacon has gone out. If
2099 * not don't don't try to post another, skip this
2100 * period and wait for the next. Missed beacons
2101 * indicate a problem and should not occur. If we
2102 * miss too many consecutive beacons reset the device.
2103 */
2104 if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) {
2105 sc->bmisscount++;
2106 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2107 "missed %u consecutive beacons\n", sc->bmisscount);
2108 if (sc->bmisscount > 3) { /* NB: 3 is a guess */
2109 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2110 "stuck beacon time (%u missed)\n",
2111 sc->bmisscount);
2112 tasklet_schedule(&sc->restq);
2113 }
2114 return;
2115 }
2116 if (unlikely(sc->bmisscount != 0)) {
2117 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2118 "resume beacon xmit after %u misses\n",
2119 sc->bmisscount);
2120 sc->bmisscount = 0;
2121 }
2122
2123 /*
2124 * Stop any current dma and put the new frame on the queue.
2125 * This should never fail since we check above that no frames
2126 * are still pending on the queue.
2127 */
2128 if (unlikely(ath5k_hw_stop_tx_dma(ah, sc->bhalq))) {
2129 ATH5K_WARN(sc, "beacon queue %u didn't stop?\n", sc->bhalq);
2130 /* NB: hw still stops DMA, so proceed */
2131 }
2132 pci_dma_sync_single_for_cpu(sc->pdev, bf->skbaddr, bf->skb->len,
2133 PCI_DMA_TODEVICE);
2134
2135 ath5k_hw_put_tx_buf(ah, sc->bhalq, bf->daddr);
2136 ath5k_hw_tx_start(ah, sc->bhalq);
2137 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
2138 sc->bhalq, (unsigned long long)bf->daddr, bf->desc);
2139
2140 sc->bsent++;
2141 }
2142
2143
2144 /**
2145 * ath5k_beacon_update_timers - update beacon timers
2146 *
2147 * @sc: struct ath5k_softc pointer we are operating on
2148 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
2149 * beacon timer update based on the current HW TSF.
2150 *
2151 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
2152 * of a received beacon or the current local hardware TSF and write it to the
2153 * beacon timer registers.
2154 *
2155 * This is called in a variety of situations, e.g. when a beacon is received,
2156 * when a TSF update has been detected, but also when an new IBSS is created or
2157 * when we otherwise know we have to update the timers, but we keep it in this
2158 * function to have it all together in one place.
2159 */
2160 static void
2161 ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
2162 {
2163 struct ath5k_hw *ah = sc->ah;
2164 u32 nexttbtt, intval, hw_tu, bc_tu;
2165 u64 hw_tsf;
2166
2167 intval = sc->bintval & AR5K_BEACON_PERIOD;
2168 if (WARN_ON(!intval))
2169 return;
2170
2171 /* beacon TSF converted to TU */
2172 bc_tu = TSF_TO_TU(bc_tsf);
2173
2174 /* current TSF converted to TU */
2175 hw_tsf = ath5k_hw_get_tsf64(ah);
2176 hw_tu = TSF_TO_TU(hw_tsf);
2177
2178 #define FUDGE 3
2179 /* we use FUDGE to make sure the next TBTT is ahead of the current TU */
2180 if (bc_tsf == -1) {
2181 /*
2182 * no beacons received, called internally.
2183 * just need to refresh timers based on HW TSF.
2184 */
2185 nexttbtt = roundup(hw_tu + FUDGE, intval);
2186 } else if (bc_tsf == 0) {
2187 /*
2188 * no beacon received, probably called by ath5k_reset_tsf().
2189 * reset TSF to start with 0.
2190 */
2191 nexttbtt = intval;
2192 intval |= AR5K_BEACON_RESET_TSF;
2193 } else if (bc_tsf > hw_tsf) {
2194 /*
2195 * beacon received, SW merge happend but HW TSF not yet updated.
2196 * not possible to reconfigure timers yet, but next time we
2197 * receive a beacon with the same BSSID, the hardware will
2198 * automatically update the TSF and then we need to reconfigure
2199 * the timers.
2200 */
2201 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2202 "need to wait for HW TSF sync\n");
2203 return;
2204 } else {
2205 /*
2206 * most important case for beacon synchronization between STA.
2207 *
2208 * beacon received and HW TSF has been already updated by HW.
2209 * update next TBTT based on the TSF of the beacon, but make
2210 * sure it is ahead of our local TSF timer.
2211 */
2212 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
2213 }
2214 #undef FUDGE
2215
2216 sc->nexttbtt = nexttbtt;
2217
2218 intval |= AR5K_BEACON_ENA;
2219 ath5k_hw_init_beacon(ah, nexttbtt, intval);
2220
2221 /*
2222 * debugging output last in order to preserve the time critical aspect
2223 * of this function
2224 */
2225 if (bc_tsf == -1)
2226 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2227 "reconfigured timers based on HW TSF\n");
2228 else if (bc_tsf == 0)
2229 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2230 "reset HW TSF and timers\n");
2231 else
2232 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2233 "updated timers based on beacon TSF\n");
2234
2235 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2236 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2237 (unsigned long long) bc_tsf,
2238 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
2239 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
2240 intval & AR5K_BEACON_PERIOD,
2241 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2242 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
2243 }
2244
2245
2246 /**
2247 * ath5k_beacon_config - Configure the beacon queues and interrupts
2248 *
2249 * @sc: struct ath5k_softc pointer we are operating on
2250 *
2251 * When operating in station mode we want to receive a BMISS interrupt when we
2252 * stop seeing beacons from the AP we've associated with so we can look for
2253 * another AP to associate with.
2254 *
2255 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
2256 * interrupts to detect TSF updates only.
2257 *
2258 * AP mode is missing.
2259 */
2260 static void
2261 ath5k_beacon_config(struct ath5k_softc *sc)
2262 {
2263 struct ath5k_hw *ah = sc->ah;
2264
2265 ath5k_hw_set_intr(ah, 0);
2266 sc->bmisscount = 0;
2267
2268 if (sc->opmode == IEEE80211_IF_TYPE_STA) {
2269 sc->imask |= AR5K_INT_BMISS;
2270 } else if (sc->opmode == IEEE80211_IF_TYPE_IBSS) {
2271 /*
2272 * In IBSS mode we use a self-linked tx descriptor and let the
2273 * hardware send the beacons automatically. We have to load it
2274 * only once here.
2275 * We use the SWBA interrupt only to keep track of the beacon
2276 * timers in order to detect automatic TSF updates.
2277 */
2278 ath5k_beaconq_config(sc);
2279
2280 sc->imask |= AR5K_INT_SWBA;
2281
2282 if (ath5k_hw_hasveol(ah))
2283 ath5k_beacon_send(sc);
2284 }
2285 /* TODO else AP */
2286
2287 ath5k_hw_set_intr(ah, sc->imask);
2288 }
2289
2290
2291 /********************\
2292 * Interrupt handling *
2293 \********************/
2294
2295 static int
2296 ath5k_init(struct ath5k_softc *sc)
2297 {
2298 int ret;
2299
2300 mutex_lock(&sc->lock);
2301
2302 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode);
2303
2304 /*
2305 * Stop anything previously setup. This is safe
2306 * no matter this is the first time through or not.
2307 */
2308 ath5k_stop_locked(sc);
2309
2310 /*
2311 * The basic interface to setting the hardware in a good
2312 * state is ``reset''. On return the hardware is known to
2313 * be powered up and with interrupts disabled. This must
2314 * be followed by initialization of the appropriate bits
2315 * and then setup of the interrupt mask.
2316 */
2317 sc->curchan = sc->hw->conf.channel;
2318 sc->curband = &sc->sbands[sc->curchan->band];
2319 ret = ath5k_hw_reset(sc->ah, sc->opmode, sc->curchan, false);
2320 if (ret) {
2321 ATH5K_ERR(sc, "unable to reset hardware: %d\n", ret);
2322 goto done;
2323 }
2324 /*
2325 * This is needed only to setup initial state
2326 * but it's best done after a reset.
2327 */
2328 ath5k_hw_set_txpower_limit(sc->ah, 0);
2329
2330 /*
2331 * Setup the hardware after reset: the key cache
2332 * is filled as needed and the receive engine is
2333 * set going. Frame transmit is handled entirely
2334 * in the frame output path; there's nothing to do
2335 * here except setup the interrupt mask.
2336 */
2337 ret = ath5k_rx_start(sc);
2338 if (ret)
2339 goto done;
2340
2341 /*
2342 * Enable interrupts.
2343 */
2344 sc->imask = AR5K_INT_RX | AR5K_INT_TX | AR5K_INT_RXEOL |
2345 AR5K_INT_RXORN | AR5K_INT_FATAL | AR5K_INT_GLOBAL |
2346 AR5K_INT_MIB;
2347
2348 ath5k_hw_set_intr(sc->ah, sc->imask);
2349 /* Set ack to be sent at low bit-rates */
2350 ath5k_hw_set_ack_bitrate_high(sc->ah, false);
2351
2352 mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2353 msecs_to_jiffies(ath5k_calinterval * 1000)));
2354
2355 ret = 0;
2356 done:
2357 mutex_unlock(&sc->lock);
2358 return ret;
2359 }
2360
2361 static int
2362 ath5k_stop_locked(struct ath5k_softc *sc)
2363 {
2364 struct ath5k_hw *ah = sc->ah;
2365
2366 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n",
2367 test_bit(ATH_STAT_INVALID, sc->status));
2368
2369 /*
2370 * Shutdown the hardware and driver:
2371 * stop output from above
2372 * disable interrupts
2373 * turn off timers
2374 * turn off the radio
2375 * clear transmit machinery
2376 * clear receive machinery
2377 * drain and release tx queues
2378 * reclaim beacon resources
2379 * power down hardware
2380 *
2381 * Note that some of this work is not possible if the
2382 * hardware is gone (invalid).
2383 */
2384 ieee80211_stop_queues(sc->hw);
2385
2386 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2387 if (test_bit(ATH_STAT_LEDSOFT, sc->status)) {
2388 del_timer_sync(&sc->led_tim);
2389 ath5k_hw_set_gpio(ah, sc->led_pin, !sc->led_on);
2390 __clear_bit(ATH_STAT_LEDBLINKING, sc->status);
2391 }
2392 ath5k_hw_set_intr(ah, 0);
2393 }
2394 ath5k_txq_cleanup(sc);
2395 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2396 ath5k_rx_stop(sc);
2397 ath5k_hw_phy_disable(ah);
2398 } else
2399 sc->rxlink = NULL;
2400
2401 return 0;
2402 }
2403
2404 /*
2405 * Stop the device, grabbing the top-level lock to protect
2406 * against concurrent entry through ath5k_init (which can happen
2407 * if another thread does a system call and the thread doing the
2408 * stop is preempted).
2409 */
2410 static int
2411 ath5k_stop_hw(struct ath5k_softc *sc)
2412 {
2413 int ret;
2414
2415 mutex_lock(&sc->lock);
2416 ret = ath5k_stop_locked(sc);
2417 if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
2418 /*
2419 * Set the chip in full sleep mode. Note that we are
2420 * careful to do this only when bringing the interface
2421 * completely to a stop. When the chip is in this state
2422 * it must be carefully woken up or references to
2423 * registers in the PCI clock domain may freeze the bus
2424 * (and system). This varies by chip and is mostly an
2425 * issue with newer parts that go to sleep more quickly.
2426 */
2427 if (sc->ah->ah_mac_srev >= 0x78) {
2428 /*
2429 * XXX
2430 * don't put newer MAC revisions > 7.8 to sleep because
2431 * of the above mentioned problems
2432 */
2433 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mac version > 7.8, "
2434 "not putting device to sleep\n");
2435 } else {
2436 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2437 "putting device to full sleep\n");
2438 ath5k_hw_set_power(sc->ah, AR5K_PM_FULL_SLEEP, true, 0);
2439 }
2440 }
2441 ath5k_txbuf_free(sc, sc->bbuf);
2442 mutex_unlock(&sc->lock);
2443
2444 del_timer_sync(&sc->calib_tim);
2445
2446 return ret;
2447 }
2448
2449 static irqreturn_t
2450 ath5k_intr(int irq, void *dev_id)
2451 {
2452 struct ath5k_softc *sc = dev_id;
2453 struct ath5k_hw *ah = sc->ah;
2454 enum ath5k_int status;
2455 unsigned int counter = 1000;
2456
2457 if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) ||
2458 !ath5k_hw_is_intr_pending(ah)))
2459 return IRQ_NONE;
2460
2461 do {
2462 /*
2463 * Figure out the reason(s) for the interrupt. Note
2464 * that get_isr returns a pseudo-ISR that may include
2465 * bits we haven't explicitly enabled so we mask the
2466 * value to insure we only process bits we requested.
2467 */
2468 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
2469 ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2470 status, sc->imask);
2471 status &= sc->imask; /* discard unasked for bits */
2472 if (unlikely(status & AR5K_INT_FATAL)) {
2473 /*
2474 * Fatal errors are unrecoverable.
2475 * Typically these are caused by DMA errors.
2476 */
2477 tasklet_schedule(&sc->restq);
2478 } else if (unlikely(status & AR5K_INT_RXORN)) {
2479 tasklet_schedule(&sc->restq);
2480 } else {
2481 if (status & AR5K_INT_SWBA) {
2482 /*
2483 * Software beacon alert--time to send a beacon.
2484 * Handle beacon transmission directly; deferring
2485 * this is too slow to meet timing constraints
2486 * under load.
2487 *
2488 * In IBSS mode we use this interrupt just to
2489 * keep track of the next TBTT (target beacon
2490 * transmission time) in order to detect wether
2491 * automatic TSF updates happened.
2492 */
2493 if (sc->opmode == IEEE80211_IF_TYPE_IBSS) {
2494 /* XXX: only if VEOL suppported */
2495 u64 tsf = ath5k_hw_get_tsf64(ah);
2496 sc->nexttbtt += sc->bintval;
2497 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2498 "SWBA nexttbtt: %x hw_tu: %x "
2499 "TSF: %llx\n",
2500 sc->nexttbtt,
2501 TSF_TO_TU(tsf),
2502 (unsigned long long) tsf);
2503 } else {
2504 ath5k_beacon_send(sc);
2505 }
2506 }
2507 if (status & AR5K_INT_RXEOL) {
2508 /*
2509 * NB: the hardware should re-read the link when
2510 * RXE bit is written, but it doesn't work at
2511 * least on older hardware revs.
2512 */
2513 sc->rxlink = NULL;
2514 }
2515 if (status & AR5K_INT_TXURN) {
2516 /* bump tx trigger level */
2517 ath5k_hw_update_tx_triglevel(ah, true);
2518 }
2519 if (status & AR5K_INT_RX)
2520 tasklet_schedule(&sc->rxtq);
2521 if (status & AR5K_INT_TX)
2522 tasklet_schedule(&sc->txtq);
2523 if (status & AR5K_INT_BMISS) {
2524 }
2525 if (status & AR5K_INT_MIB) {
2526 /*
2527 * These stats are also used for ANI i think
2528 * so how about updating them more often ?
2529 */
2530 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
2531 }
2532 }
2533 } while (ath5k_hw_is_intr_pending(ah) && counter-- > 0);
2534
2535 if (unlikely(!counter))
2536 ATH5K_WARN(sc, "too many interrupts, giving up for now\n");
2537
2538 return IRQ_HANDLED;
2539 }
2540
2541 static void
2542 ath5k_tasklet_reset(unsigned long data)
2543 {
2544 struct ath5k_softc *sc = (void *)data;
2545
2546 ath5k_reset(sc->hw);
2547 }
2548
2549 /*
2550 * Periodically recalibrate the PHY to account
2551 * for temperature/environment changes.
2552 */
2553 static void
2554 ath5k_calibrate(unsigned long data)
2555 {
2556 struct ath5k_softc *sc = (void *)data;
2557 struct ath5k_hw *ah = sc->ah;
2558
2559 ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
2560 ieee80211_frequency_to_channel(sc->curchan->center_freq),
2561 sc->curchan->hw_value);
2562
2563 if (ath5k_hw_get_rf_gain(ah) == AR5K_RFGAIN_NEED_CHANGE) {
2564 /*
2565 * Rfgain is out of bounds, reset the chip
2566 * to load new gain values.
2567 */
2568 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n");
2569 ath5k_reset(sc->hw);
2570 }
2571 if (ath5k_hw_phy_calibrate(ah, sc->curchan))
2572 ATH5K_ERR(sc, "calibration of channel %u failed\n",
2573 ieee80211_frequency_to_channel(
2574 sc->curchan->center_freq));
2575
2576 mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2577 msecs_to_jiffies(ath5k_calinterval * 1000)));
2578 }
2579
2580
2581
2582 /***************\
2583 * LED functions *
2584 \***************/
2585
2586 static void
2587 ath5k_led_off(unsigned long data)
2588 {
2589 struct ath5k_softc *sc = (void *)data;
2590
2591 if (test_bit(ATH_STAT_LEDENDBLINK, sc->status))
2592 __clear_bit(ATH_STAT_LEDBLINKING, sc->status);
2593 else {
2594 __set_bit(ATH_STAT_LEDENDBLINK, sc->status);
2595 ath5k_hw_set_gpio(sc->ah, sc->led_pin, !sc->led_on);
2596 mod_timer(&sc->led_tim, jiffies + sc->led_off);
2597 }
2598 }
2599
2600 /*
2601 * Blink the LED according to the specified on/off times.
2602 */
2603 static void
2604 ath5k_led_blink(struct ath5k_softc *sc, unsigned int on,
2605 unsigned int off)
2606 {
2607 ATH5K_DBG(sc, ATH5K_DEBUG_LED, "on %u off %u\n", on, off);
2608 ath5k_hw_set_gpio(sc->ah, sc->led_pin, sc->led_on);
2609 __set_bit(ATH_STAT_LEDBLINKING, sc->status);
2610 __clear_bit(ATH_STAT_LEDENDBLINK, sc->status);
2611 sc->led_off = off;
2612 mod_timer(&sc->led_tim, jiffies + on);
2613 }
2614
2615 static void
2616 ath5k_led_event(struct ath5k_softc *sc, int event)
2617 {
2618 if (likely(!test_bit(ATH_STAT_LEDSOFT, sc->status)))
2619 return;
2620 if (unlikely(test_bit(ATH_STAT_LEDBLINKING, sc->status)))
2621 return; /* don't interrupt active blink */
2622 switch (event) {
2623 case ATH_LED_TX:
2624 ath5k_led_blink(sc, sc->hwmap[sc->led_txrate].ledon,
2625 sc->hwmap[sc->led_txrate].ledoff);
2626 break;
2627 case ATH_LED_RX:
2628 ath5k_led_blink(sc, sc->hwmap[sc->led_rxrate].ledon,
2629 sc->hwmap[sc->led_rxrate].ledoff);
2630 break;
2631 }
2632 }
2633
2634
2635
2636
2637 /********************\
2638 * Mac80211 functions *
2639 \********************/
2640
2641 static int
2642 ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb,
2643 struct ieee80211_tx_control *ctl)
2644 {
2645 struct ath5k_softc *sc = hw->priv;
2646 struct ath5k_buf *bf;
2647 unsigned long flags;
2648 int hdrlen;
2649 int pad;
2650
2651 ath5k_debug_dump_skb(sc, skb, "TX ", 1);
2652
2653 if (sc->opmode == IEEE80211_IF_TYPE_MNTR)
2654 ATH5K_DBG(sc, ATH5K_DEBUG_XMIT, "tx in monitor (scan?)\n");
2655
2656 /*
2657 * the hardware expects the header padded to 4 byte boundaries
2658 * if this is not the case we add the padding after the header
2659 */
2660 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2661 if (hdrlen & 3) {
2662 pad = hdrlen % 4;
2663 if (skb_headroom(skb) < pad) {
2664 ATH5K_ERR(sc, "tx hdrlen not %%4: %d not enough"
2665 " headroom to pad %d\n", hdrlen, pad);
2666 return -1;
2667 }
2668 skb_push(skb, pad);
2669 memmove(skb->data, skb->data+pad, hdrlen);
2670 }
2671
2672 sc->led_txrate = ctl->tx_rate->hw_value;
2673
2674 spin_lock_irqsave(&sc->txbuflock, flags);
2675 if (list_empty(&sc->txbuf)) {
2676 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n");
2677 spin_unlock_irqrestore(&sc->txbuflock, flags);
2678 ieee80211_stop_queue(hw, ctl->queue);
2679 return -1;
2680 }
2681 bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list);
2682 list_del(&bf->list);
2683 sc->txbuf_len--;
2684 if (list_empty(&sc->txbuf))
2685 ieee80211_stop_queues(hw);
2686 spin_unlock_irqrestore(&sc->txbuflock, flags);
2687
2688 bf->skb = skb;
2689
2690 if (ath5k_txbuf_setup(sc, bf, ctl)) {
2691 bf->skb = NULL;
2692 spin_lock_irqsave(&sc->txbuflock, flags);
2693 list_add_tail(&bf->list, &sc->txbuf);
2694 sc->txbuf_len++;
2695 spin_unlock_irqrestore(&sc->txbuflock, flags);
2696 dev_kfree_skb_any(skb);
2697 return 0;
2698 }
2699
2700 return 0;
2701 }
2702
2703 static int
2704 ath5k_reset(struct ieee80211_hw *hw)
2705 {
2706 struct ath5k_softc *sc = hw->priv;
2707 struct ath5k_hw *ah = sc->ah;
2708 int ret;
2709
2710 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
2711
2712 ath5k_hw_set_intr(ah, 0);
2713 ath5k_txq_cleanup(sc);
2714 ath5k_rx_stop(sc);
2715
2716 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, true);
2717 if (unlikely(ret)) {
2718 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
2719 goto err;
2720 }
2721 ath5k_hw_set_txpower_limit(sc->ah, 0);
2722
2723 ret = ath5k_rx_start(sc);
2724 if (unlikely(ret)) {
2725 ATH5K_ERR(sc, "can't start recv logic\n");
2726 goto err;
2727 }
2728 /*
2729 * We may be doing a reset in response to an ioctl
2730 * that changes the channel so update any state that
2731 * might change as a result.
2732 *
2733 * XXX needed?
2734 */
2735 /* ath5k_chan_change(sc, c); */
2736 ath5k_beacon_config(sc);
2737 /* intrs are started by ath5k_beacon_config */
2738
2739 ieee80211_wake_queues(hw);
2740
2741 return 0;
2742 err:
2743 return ret;
2744 }
2745
2746 static int ath5k_start(struct ieee80211_hw *hw)
2747 {
2748 return ath5k_init(hw->priv);
2749 }
2750
2751 static void ath5k_stop(struct ieee80211_hw *hw)
2752 {
2753 ath5k_stop_hw(hw->priv);
2754 }
2755
2756 static int ath5k_add_interface(struct ieee80211_hw *hw,
2757 struct ieee80211_if_init_conf *conf)
2758 {
2759 struct ath5k_softc *sc = hw->priv;
2760 int ret;
2761
2762 mutex_lock(&sc->lock);
2763 if (sc->vif) {
2764 ret = 0;
2765 goto end;
2766 }
2767
2768 sc->vif = conf->vif;
2769
2770 switch (conf->type) {
2771 case IEEE80211_IF_TYPE_STA:
2772 case IEEE80211_IF_TYPE_IBSS:
2773 case IEEE80211_IF_TYPE_MNTR:
2774 sc->opmode = conf->type;
2775 break;
2776 default:
2777 ret = -EOPNOTSUPP;
2778 goto end;
2779 }
2780 ret = 0;
2781 end:
2782 mutex_unlock(&sc->lock);
2783 return ret;
2784 }
2785
2786 static void
2787 ath5k_remove_interface(struct ieee80211_hw *hw,
2788 struct ieee80211_if_init_conf *conf)
2789 {
2790 struct ath5k_softc *sc = hw->priv;
2791
2792 mutex_lock(&sc->lock);
2793 if (sc->vif != conf->vif)
2794 goto end;
2795
2796 sc->vif = NULL;
2797 end:
2798 mutex_unlock(&sc->lock);
2799 }
2800
2801 /*
2802 * TODO: Phy disable/diversity etc
2803 */
2804 static int
2805 ath5k_config(struct ieee80211_hw *hw,
2806 struct ieee80211_conf *conf)
2807 {
2808 struct ath5k_softc *sc = hw->priv;
2809
2810 sc->bintval = conf->beacon_int;
2811 sc->power_level = conf->power_level;
2812
2813 return ath5k_chan_set(sc, conf->channel);
2814 }
2815
2816 static int
2817 ath5k_config_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2818 struct ieee80211_if_conf *conf)
2819 {
2820 struct ath5k_softc *sc = hw->priv;
2821 struct ath5k_hw *ah = sc->ah;
2822 int ret;
2823
2824 /* Set to a reasonable value. Note that this will
2825 * be set to mac80211's value at ath5k_config(). */
2826 sc->bintval = 1000;
2827 mutex_lock(&sc->lock);
2828 if (sc->vif != vif) {
2829 ret = -EIO;
2830 goto unlock;
2831 }
2832 if (conf->bssid) {
2833 /* Cache for later use during resets */
2834 memcpy(ah->ah_bssid, conf->bssid, ETH_ALEN);
2835 /* XXX: assoc id is set to 0 for now, mac80211 doesn't have
2836 * a clean way of letting us retrieve this yet. */
2837 ath5k_hw_set_associd(ah, ah->ah_bssid, 0);
2838 }
2839 mutex_unlock(&sc->lock);
2840
2841 return ath5k_reset(hw);
2842 unlock:
2843 mutex_unlock(&sc->lock);
2844 return ret;
2845 }
2846
2847 #define SUPPORTED_FIF_FLAGS \
2848 FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \
2849 FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
2850 FIF_BCN_PRBRESP_PROMISC
2851 /*
2852 * o always accept unicast, broadcast, and multicast traffic
2853 * o multicast traffic for all BSSIDs will be enabled if mac80211
2854 * says it should be
2855 * o maintain current state of phy ofdm or phy cck error reception.
2856 * If the hardware detects any of these type of errors then
2857 * ath5k_hw_get_rx_filter() will pass to us the respective
2858 * hardware filters to be able to receive these type of frames.
2859 * o probe request frames are accepted only when operating in
2860 * hostap, adhoc, or monitor modes
2861 * o enable promiscuous mode according to the interface state
2862 * o accept beacons:
2863 * - when operating in adhoc mode so the 802.11 layer creates
2864 * node table entries for peers,
2865 * - when operating in station mode for collecting rssi data when
2866 * the station is otherwise quiet, or
2867 * - when scanning
2868 */
2869 static void ath5k_configure_filter(struct ieee80211_hw *hw,
2870 unsigned int changed_flags,
2871 unsigned int *new_flags,
2872 int mc_count, struct dev_mc_list *mclist)
2873 {
2874 struct ath5k_softc *sc = hw->priv;
2875 struct ath5k_hw *ah = sc->ah;
2876 u32 mfilt[2], val, rfilt;
2877 u8 pos;
2878 int i;
2879
2880 mfilt[0] = 0;
2881 mfilt[1] = 0;
2882
2883 /* Only deal with supported flags */
2884 changed_flags &= SUPPORTED_FIF_FLAGS;
2885 *new_flags &= SUPPORTED_FIF_FLAGS;
2886
2887 /* If HW detects any phy or radar errors, leave those filters on.
2888 * Also, always enable Unicast, Broadcasts and Multicast
2889 * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
2890 rfilt = (ath5k_hw_get_rx_filter(ah) & (AR5K_RX_FILTER_PHYERR)) |
2891 (AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST |
2892 AR5K_RX_FILTER_MCAST);
2893
2894 if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) {
2895 if (*new_flags & FIF_PROMISC_IN_BSS) {
2896 rfilt |= AR5K_RX_FILTER_PROM;
2897 __set_bit(ATH_STAT_PROMISC, sc->status);
2898 }
2899 else
2900 __clear_bit(ATH_STAT_PROMISC, sc->status);
2901 }
2902
2903 /* Note, AR5K_RX_FILTER_MCAST is already enabled */
2904 if (*new_flags & FIF_ALLMULTI) {
2905 mfilt[0] = ~0;
2906 mfilt[1] = ~0;
2907 } else {
2908 for (i = 0; i < mc_count; i++) {
2909 if (!mclist)
2910 break;
2911 /* calculate XOR of eight 6-bit values */
2912 val = LE_READ_4(mclist->dmi_addr + 0);
2913 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2914 val = LE_READ_4(mclist->dmi_addr + 3);
2915 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2916 pos &= 0x3f;
2917 mfilt[pos / 32] |= (1 << (pos % 32));
2918 /* XXX: we might be able to just do this instead,
2919 * but not sure, needs testing, if we do use this we'd
2920 * neet to inform below to not reset the mcast */
2921 /* ath5k_hw_set_mcast_filterindex(ah,
2922 * mclist->dmi_addr[5]); */
2923 mclist = mclist->next;
2924 }
2925 }
2926
2927 /* This is the best we can do */
2928 if (*new_flags & (FIF_FCSFAIL | FIF_PLCPFAIL))
2929 rfilt |= AR5K_RX_FILTER_PHYERR;
2930
2931 /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
2932 * and probes for any BSSID, this needs testing */
2933 if (*new_flags & FIF_BCN_PRBRESP_PROMISC)
2934 rfilt |= AR5K_RX_FILTER_BEACON | AR5K_RX_FILTER_PROBEREQ;
2935
2936 /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
2937 * set we should only pass on control frames for this
2938 * station. This needs testing. I believe right now this
2939 * enables *all* control frames, which is OK.. but
2940 * but we should see if we can improve on granularity */
2941 if (*new_flags & FIF_CONTROL)
2942 rfilt |= AR5K_RX_FILTER_CONTROL;
2943
2944 /* Additional settings per mode -- this is per ath5k */
2945
2946 /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
2947
2948 if (sc->opmode == IEEE80211_IF_TYPE_MNTR)
2949 rfilt |= AR5K_RX_FILTER_CONTROL | AR5K_RX_FILTER_BEACON |
2950 AR5K_RX_FILTER_PROBEREQ | AR5K_RX_FILTER_PROM;
2951 if (sc->opmode != IEEE80211_IF_TYPE_STA)
2952 rfilt |= AR5K_RX_FILTER_PROBEREQ;
2953 if (sc->opmode != IEEE80211_IF_TYPE_AP &&
2954 test_bit(ATH_STAT_PROMISC, sc->status))
2955 rfilt |= AR5K_RX_FILTER_PROM;
2956 if (sc->opmode == IEEE80211_IF_TYPE_STA ||
2957 sc->opmode == IEEE80211_IF_TYPE_IBSS) {
2958 rfilt |= AR5K_RX_FILTER_BEACON;
2959 }
2960
2961 /* Set filters */
2962 ath5k_hw_set_rx_filter(ah,rfilt);
2963
2964 /* Set multicast bits */
2965 ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]);
2966 /* Set the cached hw filter flags, this will alter actually
2967 * be set in HW */
2968 sc->filter_flags = rfilt;
2969 }
2970
2971 static int
2972 ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
2973 const u8 *local_addr, const u8 *addr,
2974 struct ieee80211_key_conf *key)
2975 {
2976 struct ath5k_softc *sc = hw->priv;
2977 int ret = 0;
2978
2979 switch(key->alg) {
2980 case ALG_WEP:
2981 /* XXX: fix hardware encryption, its not working. For now
2982 * allow software encryption */
2983 /* break; */
2984 case ALG_TKIP:
2985 case ALG_CCMP:
2986 return -EOPNOTSUPP;
2987 default:
2988 WARN_ON(1);
2989 return -EINVAL;
2990 }
2991
2992 mutex_lock(&sc->lock);
2993
2994 switch (cmd) {
2995 case SET_KEY:
2996 ret = ath5k_hw_set_key(sc->ah, key->keyidx, key, addr);
2997 if (ret) {
2998 ATH5K_ERR(sc, "can't set the key\n");
2999 goto unlock;
3000 }
3001 __set_bit(key->keyidx, sc->keymap);
3002 key->hw_key_idx = key->keyidx;
3003 break;
3004 case DISABLE_KEY:
3005 ath5k_hw_reset_key(sc->ah, key->keyidx);
3006 __clear_bit(key->keyidx, sc->keymap);
3007 break;
3008 default:
3009 ret = -EINVAL;
3010 goto unlock;
3011 }
3012
3013 unlock:
3014 mutex_unlock(&sc->lock);
3015 return ret;
3016 }
3017
3018 static int
3019 ath5k_get_stats(struct ieee80211_hw *hw,
3020 struct ieee80211_low_level_stats *stats)
3021 {
3022 struct ath5k_softc *sc = hw->priv;
3023 struct ath5k_hw *ah = sc->ah;
3024
3025 /* Force update */
3026 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
3027
3028 memcpy(stats, &sc->ll_stats, sizeof(sc->ll_stats));
3029
3030 return 0;
3031 }
3032
3033 static int
3034 ath5k_get_tx_stats(struct ieee80211_hw *hw,
3035 struct ieee80211_tx_queue_stats *stats)
3036 {
3037 struct ath5k_softc *sc = hw->priv;
3038
3039 memcpy(stats, &sc->tx_stats, sizeof(sc->tx_stats));
3040
3041 return 0;
3042 }
3043
3044 static u64
3045 ath5k_get_tsf(struct ieee80211_hw *hw)
3046 {
3047 struct ath5k_softc *sc = hw->priv;
3048
3049 return ath5k_hw_get_tsf64(sc->ah);
3050 }
3051
3052 static void
3053 ath5k_reset_tsf(struct ieee80211_hw *hw)
3054 {
3055 struct ath5k_softc *sc = hw->priv;
3056
3057 /*
3058 * in IBSS mode we need to update the beacon timers too.
3059 * this will also reset the TSF if we call it with 0
3060 */
3061 if (sc->opmode == IEEE80211_IF_TYPE_IBSS)
3062 ath5k_beacon_update_timers(sc, 0);
3063 else
3064 ath5k_hw_reset_tsf(sc->ah);
3065 }
3066
3067 static int
3068 ath5k_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
3069 struct ieee80211_tx_control *ctl)
3070 {
3071 struct ath5k_softc *sc = hw->priv;
3072 int ret;
3073
3074 ath5k_debug_dump_skb(sc, skb, "BC ", 1);
3075
3076 mutex_lock(&sc->lock);
3077
3078 if (sc->opmode != IEEE80211_IF_TYPE_IBSS) {
3079 ret = -EIO;
3080 goto end;
3081 }
3082
3083 ath5k_txbuf_free(sc, sc->bbuf);
3084 sc->bbuf->skb = skb;
3085 ret = ath5k_beacon_setup(sc, sc->bbuf, ctl);
3086 if (ret)
3087 sc->bbuf->skb = NULL;
3088 else
3089 ath5k_beacon_config(sc);
3090
3091 end:
3092 mutex_unlock(&sc->lock);
3093 return ret;
3094 }
3095
Linux kernel - Deliverables
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