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ath5k: Add 2413 to srev_names so that it shows up during module load
[deliverable/linux.git] / drivers / net / wireless / ath5k / base.c
1 /*-
2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
7 *
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
23 *
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
27 *
28 * NO WARRANTY
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
40 *
41 */
42
43 #include <linux/version.h>
44 #include <linux/module.h>
45 #include <linux/delay.h>
46 #include <linux/if.h>
47 #include <linux/netdevice.h>
48 #include <linux/cache.h>
49 #include <linux/pci.h>
50 #include <linux/ethtool.h>
51 #include <linux/uaccess.h>
52
53 #include <net/ieee80211_radiotap.h>
54
55 #include <asm/unaligned.h>
56
57 #include "base.h"
58 #include "reg.h"
59 #include "debug.h"
60
61 /* unaligned little endian access */
62 #define LE_READ_2(_p) (le16_to_cpu(get_unaligned((__le16 *)(_p))))
63 #define LE_READ_4(_p) (le32_to_cpu(get_unaligned((__le32 *)(_p))))
64
65 enum {
66 ATH_LED_TX,
67 ATH_LED_RX,
68 };
69
70 static int ath5k_calinterval = 10; /* Calibrate PHY every 10 secs (TODO: Fixme) */
71
72
73 /******************\
74 * Internal defines *
75 \******************/
76
77 /* Module info */
78 MODULE_AUTHOR("Jiri Slaby");
79 MODULE_AUTHOR("Nick Kossifidis");
80 MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
81 MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
82 MODULE_LICENSE("Dual BSD/GPL");
83 MODULE_VERSION("0.5.0 (EXPERIMENTAL)");
84
85
86 /* Known PCI ids */
87 static struct pci_device_id ath5k_pci_id_table[] __devinitdata = {
88 { PCI_VDEVICE(ATHEROS, 0x0207), .driver_data = AR5K_AR5210 }, /* 5210 early */
89 { PCI_VDEVICE(ATHEROS, 0x0007), .driver_data = AR5K_AR5210 }, /* 5210 */
90 { PCI_VDEVICE(ATHEROS, 0x0011), .driver_data = AR5K_AR5211 }, /* 5311 - this is on AHB bus !*/
91 { PCI_VDEVICE(ATHEROS, 0x0012), .driver_data = AR5K_AR5211 }, /* 5211 */
92 { PCI_VDEVICE(ATHEROS, 0x0013), .driver_data = AR5K_AR5212 }, /* 5212 */
93 { PCI_VDEVICE(3COM_2, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 5212 */
94 { PCI_VDEVICE(3COM, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 3CRDAG675 5212 */
95 { PCI_VDEVICE(ATHEROS, 0x1014), .driver_data = AR5K_AR5212 }, /* IBM minipci 5212 */
96 { PCI_VDEVICE(ATHEROS, 0x0014), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
97 { PCI_VDEVICE(ATHEROS, 0x0015), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
98 { PCI_VDEVICE(ATHEROS, 0x0016), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
99 { PCI_VDEVICE(ATHEROS, 0x0017), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
100 { PCI_VDEVICE(ATHEROS, 0x0018), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
101 { PCI_VDEVICE(ATHEROS, 0x0019), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
102 { PCI_VDEVICE(ATHEROS, 0x001a), .driver_data = AR5K_AR5212 }, /* 2413 Griffin-lite */
103 { PCI_VDEVICE(ATHEROS, 0x001b), .driver_data = AR5K_AR5212 }, /* 5413 Eagle */
104 { PCI_VDEVICE(ATHEROS, 0x001c), .driver_data = AR5K_AR5212 }, /* 5424 Condor (PCI-E)*/
105 { PCI_VDEVICE(ATHEROS, 0x0023), .driver_data = AR5K_AR5212 }, /* 5416 */
106 { PCI_VDEVICE(ATHEROS, 0x0024), .driver_data = AR5K_AR5212 }, /* 5418 */
107 { 0 }
108 };
109 MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table);
110
111 /* Known SREVs */
112 static struct ath5k_srev_name srev_names[] = {
113 { "5210", AR5K_VERSION_VER, AR5K_SREV_VER_AR5210 },
114 { "5311", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311 },
115 { "5311A", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311A },
116 { "5311B", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311B },
117 { "5211", AR5K_VERSION_VER, AR5K_SREV_VER_AR5211 },
118 { "5212", AR5K_VERSION_VER, AR5K_SREV_VER_AR5212 },
119 { "5213", AR5K_VERSION_VER, AR5K_SREV_VER_AR5213 },
120 { "5213A", AR5K_VERSION_VER, AR5K_SREV_VER_AR5213A },
121 { "2413", AR5K_VERSION_VER, AR5K_SREV_VER_AR2413 },
122 { "2414", AR5K_VERSION_VER, AR5K_SREV_VER_AR2414 },
123 { "2424", AR5K_VERSION_VER, AR5K_SREV_VER_AR2424 },
124 { "5424", AR5K_VERSION_VER, AR5K_SREV_VER_AR5424 },
125 { "5413", AR5K_VERSION_VER, AR5K_SREV_VER_AR5413 },
126 { "5414", AR5K_VERSION_VER, AR5K_SREV_VER_AR5414 },
127 { "5416", AR5K_VERSION_VER, AR5K_SREV_VER_AR5416 },
128 { "5418", AR5K_VERSION_VER, AR5K_SREV_VER_AR5418 },
129 { "xxxxx", AR5K_VERSION_VER, AR5K_SREV_UNKNOWN },
130 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
131 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
132 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
133 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
134 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
135 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
136 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
137 { "SChip", AR5K_VERSION_RAD, AR5K_SREV_RAD_SC0 },
138 { "SChip", AR5K_VERSION_RAD, AR5K_SREV_RAD_SC1 },
139 { "SChip", AR5K_VERSION_RAD, AR5K_SREV_RAD_SC2 },
140 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
141 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
142 };
143
144 /*
145 * Prototypes - PCI stack related functions
146 */
147 static int __devinit ath5k_pci_probe(struct pci_dev *pdev,
148 const struct pci_device_id *id);
149 static void __devexit ath5k_pci_remove(struct pci_dev *pdev);
150 #ifdef CONFIG_PM
151 static int ath5k_pci_suspend(struct pci_dev *pdev,
152 pm_message_t state);
153 static int ath5k_pci_resume(struct pci_dev *pdev);
154 #else
155 #define ath5k_pci_suspend NULL
156 #define ath5k_pci_resume NULL
157 #endif /* CONFIG_PM */
158
159 static struct pci_driver ath5k_pci_driver = {
160 .name = "ath5k_pci",
161 .id_table = ath5k_pci_id_table,
162 .probe = ath5k_pci_probe,
163 .remove = __devexit_p(ath5k_pci_remove),
164 .suspend = ath5k_pci_suspend,
165 .resume = ath5k_pci_resume,
166 };
167
168
169
170 /*
171 * Prototypes - MAC 802.11 stack related functions
172 */
173 static int ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb,
174 struct ieee80211_tx_control *ctl);
175 static int ath5k_reset(struct ieee80211_hw *hw);
176 static int ath5k_start(struct ieee80211_hw *hw);
177 static void ath5k_stop(struct ieee80211_hw *hw);
178 static int ath5k_add_interface(struct ieee80211_hw *hw,
179 struct ieee80211_if_init_conf *conf);
180 static void ath5k_remove_interface(struct ieee80211_hw *hw,
181 struct ieee80211_if_init_conf *conf);
182 static int ath5k_config(struct ieee80211_hw *hw,
183 struct ieee80211_conf *conf);
184 static int ath5k_config_interface(struct ieee80211_hw *hw,
185 struct ieee80211_vif *vif,
186 struct ieee80211_if_conf *conf);
187 static void ath5k_configure_filter(struct ieee80211_hw *hw,
188 unsigned int changed_flags,
189 unsigned int *new_flags,
190 int mc_count, struct dev_mc_list *mclist);
191 static int ath5k_set_key(struct ieee80211_hw *hw,
192 enum set_key_cmd cmd,
193 const u8 *local_addr, const u8 *addr,
194 struct ieee80211_key_conf *key);
195 static int ath5k_get_stats(struct ieee80211_hw *hw,
196 struct ieee80211_low_level_stats *stats);
197 static int ath5k_get_tx_stats(struct ieee80211_hw *hw,
198 struct ieee80211_tx_queue_stats *stats);
199 static u64 ath5k_get_tsf(struct ieee80211_hw *hw);
200 static void ath5k_reset_tsf(struct ieee80211_hw *hw);
201 static int ath5k_beacon_update(struct ieee80211_hw *hw,
202 struct sk_buff *skb,
203 struct ieee80211_tx_control *ctl);
204
205 static struct ieee80211_ops ath5k_hw_ops = {
206 .tx = ath5k_tx,
207 .start = ath5k_start,
208 .stop = ath5k_stop,
209 .add_interface = ath5k_add_interface,
210 .remove_interface = ath5k_remove_interface,
211 .config = ath5k_config,
212 .config_interface = ath5k_config_interface,
213 .configure_filter = ath5k_configure_filter,
214 .set_key = ath5k_set_key,
215 .get_stats = ath5k_get_stats,
216 .conf_tx = NULL,
217 .get_tx_stats = ath5k_get_tx_stats,
218 .get_tsf = ath5k_get_tsf,
219 .reset_tsf = ath5k_reset_tsf,
220 .beacon_update = ath5k_beacon_update,
221 };
222
223 /*
224 * Prototypes - Internal functions
225 */
226 /* Attach detach */
227 static int ath5k_attach(struct pci_dev *pdev,
228 struct ieee80211_hw *hw);
229 static void ath5k_detach(struct pci_dev *pdev,
230 struct ieee80211_hw *hw);
231 /* Channel/mode setup */
232 static inline short ath5k_ieee2mhz(short chan);
233 static unsigned int ath5k_copy_rates(struct ieee80211_rate *rates,
234 const struct ath5k_rate_table *rt,
235 unsigned int max);
236 static unsigned int ath5k_copy_channels(struct ath5k_hw *ah,
237 struct ieee80211_channel *channels,
238 unsigned int mode,
239 unsigned int max);
240 static int ath5k_getchannels(struct ieee80211_hw *hw);
241 static int ath5k_chan_set(struct ath5k_softc *sc,
242 struct ieee80211_channel *chan);
243 static void ath5k_setcurmode(struct ath5k_softc *sc,
244 unsigned int mode);
245 static void ath5k_mode_setup(struct ath5k_softc *sc);
246 static void ath5k_set_total_hw_rates(struct ath5k_softc *sc);
247
248 /* Descriptor setup */
249 static int ath5k_desc_alloc(struct ath5k_softc *sc,
250 struct pci_dev *pdev);
251 static void ath5k_desc_free(struct ath5k_softc *sc,
252 struct pci_dev *pdev);
253 /* Buffers setup */
254 static int ath5k_rxbuf_setup(struct ath5k_softc *sc,
255 struct ath5k_buf *bf);
256 static int ath5k_txbuf_setup(struct ath5k_softc *sc,
257 struct ath5k_buf *bf,
258 struct ieee80211_tx_control *ctl);
259
260 static inline void ath5k_txbuf_free(struct ath5k_softc *sc,
261 struct ath5k_buf *bf)
262 {
263 BUG_ON(!bf);
264 if (!bf->skb)
265 return;
266 pci_unmap_single(sc->pdev, bf->skbaddr, bf->skb->len,
267 PCI_DMA_TODEVICE);
268 dev_kfree_skb(bf->skb);
269 bf->skb = NULL;
270 }
271
272 /* Queues setup */
273 static struct ath5k_txq *ath5k_txq_setup(struct ath5k_softc *sc,
274 int qtype, int subtype);
275 static int ath5k_beaconq_setup(struct ath5k_hw *ah);
276 static int ath5k_beaconq_config(struct ath5k_softc *sc);
277 static void ath5k_txq_drainq(struct ath5k_softc *sc,
278 struct ath5k_txq *txq);
279 static void ath5k_txq_cleanup(struct ath5k_softc *sc);
280 static void ath5k_txq_release(struct ath5k_softc *sc);
281 /* Rx handling */
282 static int ath5k_rx_start(struct ath5k_softc *sc);
283 static void ath5k_rx_stop(struct ath5k_softc *sc);
284 static unsigned int ath5k_rx_decrypted(struct ath5k_softc *sc,
285 struct ath5k_desc *ds,
286 struct sk_buff *skb);
287 static void ath5k_tasklet_rx(unsigned long data);
288 /* Tx handling */
289 static void ath5k_tx_processq(struct ath5k_softc *sc,
290 struct ath5k_txq *txq);
291 static void ath5k_tasklet_tx(unsigned long data);
292 /* Beacon handling */
293 static int ath5k_beacon_setup(struct ath5k_softc *sc,
294 struct ath5k_buf *bf,
295 struct ieee80211_tx_control *ctl);
296 static void ath5k_beacon_send(struct ath5k_softc *sc);
297 static void ath5k_beacon_config(struct ath5k_softc *sc);
298 static void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf);
299
300 static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
301 {
302 u64 tsf = ath5k_hw_get_tsf64(ah);
303
304 if ((tsf & 0x7fff) < rstamp)
305 tsf -= 0x8000;
306
307 return (tsf & ~0x7fff) | rstamp;
308 }
309
310 /* Interrupt handling */
311 static int ath5k_init(struct ath5k_softc *sc);
312 static int ath5k_stop_locked(struct ath5k_softc *sc);
313 static int ath5k_stop_hw(struct ath5k_softc *sc);
314 static irqreturn_t ath5k_intr(int irq, void *dev_id);
315 static void ath5k_tasklet_reset(unsigned long data);
316
317 static void ath5k_calibrate(unsigned long data);
318 /* LED functions */
319 static void ath5k_led_off(unsigned long data);
320 static void ath5k_led_blink(struct ath5k_softc *sc,
321 unsigned int on,
322 unsigned int off);
323 static void ath5k_led_event(struct ath5k_softc *sc,
324 int event);
325
326
327 /*
328 * Module init/exit functions
329 */
330 static int __init
331 init_ath5k_pci(void)
332 {
333 int ret;
334
335 ath5k_debug_init();
336
337 ret = pci_register_driver(&ath5k_pci_driver);
338 if (ret) {
339 printk(KERN_ERR "ath5k_pci: can't register pci driver\n");
340 return ret;
341 }
342
343 return 0;
344 }
345
346 static void __exit
347 exit_ath5k_pci(void)
348 {
349 pci_unregister_driver(&ath5k_pci_driver);
350
351 ath5k_debug_finish();
352 }
353
354 module_init(init_ath5k_pci);
355 module_exit(exit_ath5k_pci);
356
357
358 /********************\
359 * PCI Initialization *
360 \********************/
361
362 static const char *
363 ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
364 {
365 const char *name = "xxxxx";
366 unsigned int i;
367
368 for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
369 if (srev_names[i].sr_type != type)
370 continue;
371 if ((val & 0xff) < srev_names[i + 1].sr_val) {
372 name = srev_names[i].sr_name;
373 break;
374 }
375 }
376
377 return name;
378 }
379
380 static int __devinit
381 ath5k_pci_probe(struct pci_dev *pdev,
382 const struct pci_device_id *id)
383 {
384 void __iomem *mem;
385 struct ath5k_softc *sc;
386 struct ieee80211_hw *hw;
387 int ret;
388 u8 csz;
389
390 ret = pci_enable_device(pdev);
391 if (ret) {
392 dev_err(&pdev->dev, "can't enable device\n");
393 goto err;
394 }
395
396 /* XXX 32-bit addressing only */
397 ret = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
398 if (ret) {
399 dev_err(&pdev->dev, "32-bit DMA not available\n");
400 goto err_dis;
401 }
402
403 /*
404 * Cache line size is used to size and align various
405 * structures used to communicate with the hardware.
406 */
407 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
408 if (csz == 0) {
409 /*
410 * Linux 2.4.18 (at least) writes the cache line size
411 * register as a 16-bit wide register which is wrong.
412 * We must have this setup properly for rx buffer
413 * DMA to work so force a reasonable value here if it
414 * comes up zero.
415 */
416 csz = L1_CACHE_BYTES / sizeof(u32);
417 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
418 }
419 /*
420 * The default setting of latency timer yields poor results,
421 * set it to the value used by other systems. It may be worth
422 * tweaking this setting more.
423 */
424 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
425
426 /* Enable bus mastering */
427 pci_set_master(pdev);
428
429 /*
430 * Disable the RETRY_TIMEOUT register (0x41) to keep
431 * PCI Tx retries from interfering with C3 CPU state.
432 */
433 pci_write_config_byte(pdev, 0x41, 0);
434
435 ret = pci_request_region(pdev, 0, "ath5k");
436 if (ret) {
437 dev_err(&pdev->dev, "cannot reserve PCI memory region\n");
438 goto err_dis;
439 }
440
441 mem = pci_iomap(pdev, 0, 0);
442 if (!mem) {
443 dev_err(&pdev->dev, "cannot remap PCI memory region\n") ;
444 ret = -EIO;
445 goto err_reg;
446 }
447
448 /*
449 * Allocate hw (mac80211 main struct)
450 * and hw->priv (driver private data)
451 */
452 hw = ieee80211_alloc_hw(sizeof(*sc), &ath5k_hw_ops);
453 if (hw == NULL) {
454 dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n");
455 ret = -ENOMEM;
456 goto err_map;
457 }
458
459 dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy));
460
461 /* Initialize driver private data */
462 SET_IEEE80211_DEV(hw, &pdev->dev);
463 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS;
464 hw->extra_tx_headroom = 2;
465 hw->channel_change_time = 5000;
466 /* these names are misleading */
467 hw->max_rssi = -110; /* signal in dBm */
468 hw->max_noise = -110; /* noise in dBm */
469 hw->max_signal = 100; /* we will provide a percentage based on rssi */
470 sc = hw->priv;
471 sc->hw = hw;
472 sc->pdev = pdev;
473
474 ath5k_debug_init_device(sc);
475
476 /*
477 * Mark the device as detached to avoid processing
478 * interrupts until setup is complete.
479 */
480 __set_bit(ATH_STAT_INVALID, sc->status);
481
482 sc->iobase = mem; /* So we can unmap it on detach */
483 sc->cachelsz = csz * sizeof(u32); /* convert to bytes */
484 sc->opmode = IEEE80211_IF_TYPE_STA;
485 mutex_init(&sc->lock);
486 spin_lock_init(&sc->rxbuflock);
487 spin_lock_init(&sc->txbuflock);
488
489 /* Set private data */
490 pci_set_drvdata(pdev, hw);
491
492 /* Enable msi for devices that support it */
493 pci_enable_msi(pdev);
494
495 /* Setup interrupt handler */
496 ret = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
497 if (ret) {
498 ATH5K_ERR(sc, "request_irq failed\n");
499 goto err_free;
500 }
501
502 /* Initialize device */
503 sc->ah = ath5k_hw_attach(sc, id->driver_data);
504 if (IS_ERR(sc->ah)) {
505 ret = PTR_ERR(sc->ah);
506 goto err_irq;
507 }
508
509 /* Finish private driver data initialization */
510 ret = ath5k_attach(pdev, hw);
511 if (ret)
512 goto err_ah;
513
514 ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
515 ath5k_chip_name(AR5K_VERSION_VER,sc->ah->ah_mac_srev),
516 sc->ah->ah_mac_srev,
517 sc->ah->ah_phy_revision);
518
519 if (!sc->ah->ah_single_chip) {
520 /* Single chip radio (!RF5111) */
521 if (sc->ah->ah_radio_5ghz_revision &&
522 !sc->ah->ah_radio_2ghz_revision) {
523 /* No 5GHz support -> report 2GHz radio */
524 if (!test_bit(AR5K_MODE_11A,
525 sc->ah->ah_capabilities.cap_mode)) {
526 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
527 ath5k_chip_name(AR5K_VERSION_RAD,
528 sc->ah->ah_radio_5ghz_revision),
529 sc->ah->ah_radio_5ghz_revision);
530 /* No 2GHz support (5110 and some
531 * 5Ghz only cards) -> report 5Ghz radio */
532 } else if (!test_bit(AR5K_MODE_11B,
533 sc->ah->ah_capabilities.cap_mode)) {
534 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
535 ath5k_chip_name(AR5K_VERSION_RAD,
536 sc->ah->ah_radio_5ghz_revision),
537 sc->ah->ah_radio_5ghz_revision);
538 /* Multiband radio */
539 } else {
540 ATH5K_INFO(sc, "RF%s multiband radio found"
541 " (0x%x)\n",
542 ath5k_chip_name(AR5K_VERSION_RAD,
543 sc->ah->ah_radio_5ghz_revision),
544 sc->ah->ah_radio_5ghz_revision);
545 }
546 }
547 /* Multi chip radio (RF5111 - RF2111) ->
548 * report both 2GHz/5GHz radios */
549 else if (sc->ah->ah_radio_5ghz_revision &&
550 sc->ah->ah_radio_2ghz_revision){
551 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
552 ath5k_chip_name(AR5K_VERSION_RAD,
553 sc->ah->ah_radio_5ghz_revision),
554 sc->ah->ah_radio_5ghz_revision);
555 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
556 ath5k_chip_name(AR5K_VERSION_RAD,
557 sc->ah->ah_radio_2ghz_revision),
558 sc->ah->ah_radio_2ghz_revision);
559 }
560 }
561
562
563 /* ready to process interrupts */
564 __clear_bit(ATH_STAT_INVALID, sc->status);
565
566 return 0;
567 err_ah:
568 ath5k_hw_detach(sc->ah);
569 err_irq:
570 free_irq(pdev->irq, sc);
571 err_free:
572 pci_disable_msi(pdev);
573 ieee80211_free_hw(hw);
574 err_map:
575 pci_iounmap(pdev, mem);
576 err_reg:
577 pci_release_region(pdev, 0);
578 err_dis:
579 pci_disable_device(pdev);
580 err:
581 return ret;
582 }
583
584 static void __devexit
585 ath5k_pci_remove(struct pci_dev *pdev)
586 {
587 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
588 struct ath5k_softc *sc = hw->priv;
589
590 ath5k_debug_finish_device(sc);
591 ath5k_detach(pdev, hw);
592 ath5k_hw_detach(sc->ah);
593 free_irq(pdev->irq, sc);
594 pci_disable_msi(pdev);
595 pci_iounmap(pdev, sc->iobase);
596 pci_release_region(pdev, 0);
597 pci_disable_device(pdev);
598 ieee80211_free_hw(hw);
599 }
600
601 #ifdef CONFIG_PM
602 static int
603 ath5k_pci_suspend(struct pci_dev *pdev, pm_message_t state)
604 {
605 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
606 struct ath5k_softc *sc = hw->priv;
607
608 if (test_bit(ATH_STAT_LEDSOFT, sc->status))
609 ath5k_hw_set_gpio(sc->ah, sc->led_pin, 1);
610
611 ath5k_stop_hw(sc);
612 pci_save_state(pdev);
613 pci_disable_device(pdev);
614 pci_set_power_state(pdev, PCI_D3hot);
615
616 return 0;
617 }
618
619 static int
620 ath5k_pci_resume(struct pci_dev *pdev)
621 {
622 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
623 struct ath5k_softc *sc = hw->priv;
624 struct ath5k_hw *ah = sc->ah;
625 int i, err;
626
627 err = pci_set_power_state(pdev, PCI_D0);
628 if (err)
629 return err;
630
631 err = pci_enable_device(pdev);
632 if (err)
633 return err;
634
635 pci_restore_state(pdev);
636 /*
637 * Suspend/Resume resets the PCI configuration space, so we have to
638 * re-disable the RETRY_TIMEOUT register (0x41) to keep
639 * PCI Tx retries from interfering with C3 CPU state
640 */
641 pci_write_config_byte(pdev, 0x41, 0);
642
643 ath5k_init(sc);
644 if (test_bit(ATH_STAT_LEDSOFT, sc->status)) {
645 ath5k_hw_set_gpio_output(ah, sc->led_pin);
646 ath5k_hw_set_gpio(ah, sc->led_pin, 0);
647 }
648
649 /*
650 * Reset the key cache since some parts do not
651 * reset the contents on initial power up or resume.
652 *
653 * FIXME: This may need to be revisited when mac80211 becomes
654 * aware of suspend/resume.
655 */
656 for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
657 ath5k_hw_reset_key(ah, i);
658
659 return 0;
660 }
661 #endif /* CONFIG_PM */
662
663
664
665 /***********************\
666 * Driver Initialization *
667 \***********************/
668
669 static int
670 ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw)
671 {
672 struct ath5k_softc *sc = hw->priv;
673 struct ath5k_hw *ah = sc->ah;
674 u8 mac[ETH_ALEN];
675 unsigned int i;
676 int ret;
677
678 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "devid 0x%x\n", pdev->device);
679
680 /*
681 * Check if the MAC has multi-rate retry support.
682 * We do this by trying to setup a fake extended
683 * descriptor. MAC's that don't have support will
684 * return false w/o doing anything. MAC's that do
685 * support it will return true w/o doing anything.
686 */
687 ret = ah->ah_setup_xtx_desc(ah, NULL, 0, 0, 0, 0, 0, 0);
688 if (ret < 0)
689 goto err;
690 if (ret > 0)
691 __set_bit(ATH_STAT_MRRETRY, sc->status);
692
693 /*
694 * Reset the key cache since some parts do not
695 * reset the contents on initial power up.
696 */
697 for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
698 ath5k_hw_reset_key(ah, i);
699
700 /*
701 * Collect the channel list. The 802.11 layer
702 * is resposible for filtering this list based
703 * on settings like the phy mode and regulatory
704 * domain restrictions.
705 */
706 ret = ath5k_getchannels(hw);
707 if (ret) {
708 ATH5K_ERR(sc, "can't get channels\n");
709 goto err;
710 }
711
712 /* Set *_rates so we can map hw rate index */
713 ath5k_set_total_hw_rates(sc);
714
715 /* NB: setup here so ath5k_rate_update is happy */
716 if (test_bit(AR5K_MODE_11A, ah->ah_modes))
717 ath5k_setcurmode(sc, AR5K_MODE_11A);
718 else
719 ath5k_setcurmode(sc, AR5K_MODE_11B);
720
721 /*
722 * Allocate tx+rx descriptors and populate the lists.
723 */
724 ret = ath5k_desc_alloc(sc, pdev);
725 if (ret) {
726 ATH5K_ERR(sc, "can't allocate descriptors\n");
727 goto err;
728 }
729
730 /*
731 * Allocate hardware transmit queues: one queue for
732 * beacon frames and one data queue for each QoS
733 * priority. Note that hw functions handle reseting
734 * these queues at the needed time.
735 */
736 ret = ath5k_beaconq_setup(ah);
737 if (ret < 0) {
738 ATH5K_ERR(sc, "can't setup a beacon xmit queue\n");
739 goto err_desc;
740 }
741 sc->bhalq = ret;
742
743 sc->txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
744 if (IS_ERR(sc->txq)) {
745 ATH5K_ERR(sc, "can't setup xmit queue\n");
746 ret = PTR_ERR(sc->txq);
747 goto err_bhal;
748 }
749
750 tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
751 tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
752 tasklet_init(&sc->restq, ath5k_tasklet_reset, (unsigned long)sc);
753 setup_timer(&sc->calib_tim, ath5k_calibrate, (unsigned long)sc);
754 setup_timer(&sc->led_tim, ath5k_led_off, (unsigned long)sc);
755
756 sc->led_on = 0; /* low true */
757 /*
758 * Auto-enable soft led processing for IBM cards and for
759 * 5211 minipci cards.
760 */
761 if (pdev->device == PCI_DEVICE_ID_ATHEROS_AR5212_IBM ||
762 pdev->device == PCI_DEVICE_ID_ATHEROS_AR5211) {
763 __set_bit(ATH_STAT_LEDSOFT, sc->status);
764 sc->led_pin = 0;
765 }
766 /* Enable softled on PIN1 on HP Compaq nc6xx, nc4000 & nx5000 laptops */
767 if (pdev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ) {
768 __set_bit(ATH_STAT_LEDSOFT, sc->status);
769 sc->led_pin = 0;
770 }
771 if (test_bit(ATH_STAT_LEDSOFT, sc->status)) {
772 ath5k_hw_set_gpio_output(ah, sc->led_pin);
773 ath5k_hw_set_gpio(ah, sc->led_pin, !sc->led_on);
774 }
775
776 ath5k_hw_get_lladdr(ah, mac);
777 SET_IEEE80211_PERM_ADDR(hw, mac);
778 /* All MAC address bits matter for ACKs */
779 memset(sc->bssidmask, 0xff, ETH_ALEN);
780 ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
781
782 ret = ieee80211_register_hw(hw);
783 if (ret) {
784 ATH5K_ERR(sc, "can't register ieee80211 hw\n");
785 goto err_queues;
786 }
787
788 return 0;
789 err_queues:
790 ath5k_txq_release(sc);
791 err_bhal:
792 ath5k_hw_release_tx_queue(ah, sc->bhalq);
793 err_desc:
794 ath5k_desc_free(sc, pdev);
795 err:
796 return ret;
797 }
798
799 static void
800 ath5k_detach(struct pci_dev *pdev, struct ieee80211_hw *hw)
801 {
802 struct ath5k_softc *sc = hw->priv;
803
804 /*
805 * NB: the order of these is important:
806 * o call the 802.11 layer before detaching ath5k_hw to
807 * insure callbacks into the driver to delete global
808 * key cache entries can be handled
809 * o reclaim the tx queue data structures after calling
810 * the 802.11 layer as we'll get called back to reclaim
811 * node state and potentially want to use them
812 * o to cleanup the tx queues the hal is called, so detach
813 * it last
814 * XXX: ??? detach ath5k_hw ???
815 * Other than that, it's straightforward...
816 */
817 ieee80211_unregister_hw(hw);
818 ath5k_desc_free(sc, pdev);
819 ath5k_txq_release(sc);
820 ath5k_hw_release_tx_queue(sc->ah, sc->bhalq);
821
822 /*
823 * NB: can't reclaim these until after ieee80211_ifdetach
824 * returns because we'll get called back to reclaim node
825 * state and potentially want to use them.
826 */
827 }
828
829
830
831
832 /********************\
833 * Channel/mode setup *
834 \********************/
835
836 /*
837 * Convert IEEE channel number to MHz frequency.
838 */
839 static inline short
840 ath5k_ieee2mhz(short chan)
841 {
842 if (chan <= 14 || chan >= 27)
843 return ieee80211chan2mhz(chan);
844 else
845 return 2212 + chan * 20;
846 }
847
848 static unsigned int
849 ath5k_copy_rates(struct ieee80211_rate *rates,
850 const struct ath5k_rate_table *rt,
851 unsigned int max)
852 {
853 unsigned int i, count;
854
855 if (rt == NULL)
856 return 0;
857
858 for (i = 0, count = 0; i < rt->rate_count && max > 0; i++) {
859 rates[count].bitrate = rt->rates[i].rate_kbps / 100;
860 rates[count].hw_value = rt->rates[i].rate_code;
861 rates[count].flags = rt->rates[i].modulation;
862 count++;
863 max--;
864 }
865
866 return count;
867 }
868
869 static unsigned int
870 ath5k_copy_channels(struct ath5k_hw *ah,
871 struct ieee80211_channel *channels,
872 unsigned int mode,
873 unsigned int max)
874 {
875 unsigned int i, count, size, chfreq, freq, ch;
876
877 if (!test_bit(mode, ah->ah_modes))
878 return 0;
879
880 switch (mode) {
881 case AR5K_MODE_11A:
882 case AR5K_MODE_11A_TURBO:
883 /* 1..220, but 2GHz frequencies are filtered by check_channel */
884 size = 220 ;
885 chfreq = CHANNEL_5GHZ;
886 break;
887 case AR5K_MODE_11B:
888 case AR5K_MODE_11G:
889 case AR5K_MODE_11G_TURBO:
890 size = 26;
891 chfreq = CHANNEL_2GHZ;
892 break;
893 default:
894 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n");
895 return 0;
896 }
897
898 for (i = 0, count = 0; i < size && max > 0; i++) {
899 ch = i + 1 ;
900 freq = ath5k_ieee2mhz(ch);
901
902 /* Check if channel is supported by the chipset */
903 if (!ath5k_channel_ok(ah, freq, chfreq))
904 continue;
905
906 /* Write channel info and increment counter */
907 channels[count].center_freq = freq;
908 channels[count].band = (chfreq == CHANNEL_2GHZ) ?
909 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
910 switch (mode) {
911 case AR5K_MODE_11A:
912 case AR5K_MODE_11G:
913 channels[count].hw_value = chfreq | CHANNEL_OFDM;
914 break;
915 case AR5K_MODE_11A_TURBO:
916 case AR5K_MODE_11G_TURBO:
917 channels[count].hw_value = chfreq |
918 CHANNEL_OFDM | CHANNEL_TURBO;
919 break;
920 case AR5K_MODE_11B:
921 channels[count].hw_value = CHANNEL_B;
922 }
923
924 count++;
925 max--;
926 }
927
928 return count;
929 }
930
931 static int
932 ath5k_getchannels(struct ieee80211_hw *hw)
933 {
934 struct ath5k_softc *sc = hw->priv;
935 struct ath5k_hw *ah = sc->ah;
936 struct ieee80211_supported_band *sbands = sc->sbands;
937 const struct ath5k_rate_table *hw_rates;
938 unsigned int max_r, max_c, count_r, count_c;
939 int mode2g = AR5K_MODE_11G;
940
941 BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS);
942
943 max_r = ARRAY_SIZE(sc->rates);
944 max_c = ARRAY_SIZE(sc->channels);
945 count_r = count_c = 0;
946
947 /* 2GHz band */
948 if (!test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) {
949 mode2g = AR5K_MODE_11B;
950 if (!test_bit(AR5K_MODE_11B,
951 sc->ah->ah_capabilities.cap_mode))
952 mode2g = -1;
953 }
954
955 if (mode2g > 0) {
956 struct ieee80211_supported_band *sband =
957 &sbands[IEEE80211_BAND_2GHZ];
958
959 sband->bitrates = sc->rates;
960 sband->channels = sc->channels;
961
962 sband->band = IEEE80211_BAND_2GHZ;
963 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
964 mode2g, max_c);
965
966 hw_rates = ath5k_hw_get_rate_table(ah, mode2g);
967 sband->n_bitrates = ath5k_copy_rates(sband->bitrates,
968 hw_rates, max_r);
969
970 count_c = sband->n_channels;
971 count_r = sband->n_bitrates;
972
973 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
974
975 max_r -= count_r;
976 max_c -= count_c;
977
978 }
979
980 /* 5GHz band */
981
982 if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) {
983 struct ieee80211_supported_band *sband =
984 &sbands[IEEE80211_BAND_5GHZ];
985
986 sband->bitrates = &sc->rates[count_r];
987 sband->channels = &sc->channels[count_c];
988
989 sband->band = IEEE80211_BAND_5GHZ;
990 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
991 AR5K_MODE_11A, max_c);
992
993 hw_rates = ath5k_hw_get_rate_table(ah, AR5K_MODE_11A);
994 sband->n_bitrates = ath5k_copy_rates(sband->bitrates,
995 hw_rates, max_r);
996
997 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
998 }
999
1000 ath5k_debug_dump_bands(sc);
1001
1002 return 0;
1003 }
1004
1005 /*
1006 * Set/change channels. If the channel is really being changed,
1007 * it's done by reseting the chip. To accomplish this we must
1008 * first cleanup any pending DMA, then restart stuff after a la
1009 * ath5k_init.
1010 */
1011 static int
1012 ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
1013 {
1014 struct ath5k_hw *ah = sc->ah;
1015 int ret;
1016
1017 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "(%u MHz) -> (%u MHz)\n",
1018 sc->curchan->center_freq, chan->center_freq);
1019
1020 if (chan->center_freq != sc->curchan->center_freq ||
1021 chan->hw_value != sc->curchan->hw_value) {
1022
1023 sc->curchan = chan;
1024 sc->curband = &sc->sbands[chan->band];
1025
1026 /*
1027 * To switch channels clear any pending DMA operations;
1028 * wait long enough for the RX fifo to drain, reset the
1029 * hardware at the new frequency, and then re-enable
1030 * the relevant bits of the h/w.
1031 */
1032 ath5k_hw_set_intr(ah, 0); /* disable interrupts */
1033 ath5k_txq_cleanup(sc); /* clear pending tx frames */
1034 ath5k_rx_stop(sc); /* turn off frame recv */
1035 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, true);
1036 if (ret) {
1037 ATH5K_ERR(sc, "%s: unable to reset channel "
1038 "(%u Mhz)\n", __func__, chan->center_freq);
1039 return ret;
1040 }
1041
1042 ath5k_hw_set_txpower_limit(sc->ah, 0);
1043
1044 /*
1045 * Re-enable rx framework.
1046 */
1047 ret = ath5k_rx_start(sc);
1048 if (ret) {
1049 ATH5K_ERR(sc, "%s: unable to restart recv logic\n",
1050 __func__);
1051 return ret;
1052 }
1053
1054 /*
1055 * Change channels and update the h/w rate map
1056 * if we're switching; e.g. 11a to 11b/g.
1057 *
1058 * XXX needed?
1059 */
1060 /* ath5k_chan_change(sc, chan); */
1061
1062 ath5k_beacon_config(sc);
1063 /*
1064 * Re-enable interrupts.
1065 */
1066 ath5k_hw_set_intr(ah, sc->imask);
1067 }
1068
1069 return 0;
1070 }
1071
1072 /*
1073 * TODO: CLEAN THIS !!!
1074 */
1075 static void
1076 ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode)
1077 {
1078 if (unlikely(test_bit(ATH_STAT_LEDSOFT, sc->status))) {
1079 /* from Atheros NDIS driver, w/ permission */
1080 static const struct {
1081 u16 rate; /* tx/rx 802.11 rate */
1082 u16 timeOn; /* LED on time (ms) */
1083 u16 timeOff; /* LED off time (ms) */
1084 } blinkrates[] = {
1085 { 108, 40, 10 },
1086 { 96, 44, 11 },
1087 { 72, 50, 13 },
1088 { 48, 57, 14 },
1089 { 36, 67, 16 },
1090 { 24, 80, 20 },
1091 { 22, 100, 25 },
1092 { 18, 133, 34 },
1093 { 12, 160, 40 },
1094 { 10, 200, 50 },
1095 { 6, 240, 58 },
1096 { 4, 267, 66 },
1097 { 2, 400, 100 },
1098 { 0, 500, 130 }
1099 };
1100 const struct ath5k_rate_table *rt =
1101 ath5k_hw_get_rate_table(sc->ah, mode);
1102 unsigned int i, j;
1103
1104 BUG_ON(rt == NULL);
1105
1106 memset(sc->hwmap, 0, sizeof(sc->hwmap));
1107 for (i = 0; i < 32; i++) {
1108 u8 ix = rt->rate_code_to_index[i];
1109 if (ix == 0xff) {
1110 sc->hwmap[i].ledon = msecs_to_jiffies(500);
1111 sc->hwmap[i].ledoff = msecs_to_jiffies(130);
1112 continue;
1113 }
1114 sc->hwmap[i].txflags = IEEE80211_RADIOTAP_F_DATAPAD;
1115 /* receive frames include FCS */
1116 sc->hwmap[i].rxflags = sc->hwmap[i].txflags |
1117 IEEE80211_RADIOTAP_F_FCS;
1118 /* setup blink rate table to avoid per-packet lookup */
1119 for (j = 0; j < ARRAY_SIZE(blinkrates) - 1; j++)
1120 if (blinkrates[j].rate == /* XXX why 7f? */
1121 (rt->rates[ix].dot11_rate&0x7f))
1122 break;
1123
1124 sc->hwmap[i].ledon = msecs_to_jiffies(blinkrates[j].
1125 timeOn);
1126 sc->hwmap[i].ledoff = msecs_to_jiffies(blinkrates[j].
1127 timeOff);
1128 }
1129 }
1130
1131 sc->curmode = mode;
1132
1133 if (mode == AR5K_MODE_11A) {
1134 sc->curband = &sc->sbands[IEEE80211_BAND_5GHZ];
1135 } else {
1136 sc->curband = &sc->sbands[IEEE80211_BAND_2GHZ];
1137 }
1138 }
1139
1140 static void
1141 ath5k_mode_setup(struct ath5k_softc *sc)
1142 {
1143 struct ath5k_hw *ah = sc->ah;
1144 u32 rfilt;
1145
1146 /* configure rx filter */
1147 rfilt = sc->filter_flags;
1148 ath5k_hw_set_rx_filter(ah, rfilt);
1149
1150 if (ath5k_hw_hasbssidmask(ah))
1151 ath5k_hw_set_bssid_mask(ah, sc->bssidmask);
1152
1153 /* configure operational mode */
1154 ath5k_hw_set_opmode(ah);
1155
1156 ath5k_hw_set_mcast_filter(ah, 0, 0);
1157 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
1158 }
1159
1160 /*
1161 * Match the hw provided rate index (through descriptors)
1162 * to an index for sc->curband->bitrates, so it can be used
1163 * by the stack.
1164 *
1165 * This one is a little bit tricky but i think i'm right
1166 * about this...
1167 *
1168 * We have 4 rate tables in the following order:
1169 * XR (4 rates)
1170 * 802.11a (8 rates)
1171 * 802.11b (4 rates)
1172 * 802.11g (12 rates)
1173 * that make the hw rate table.
1174 *
1175 * Lets take a 5211 for example that supports a and b modes only.
1176 * First comes the 802.11a table and then 802.11b (total 12 rates).
1177 * When hw returns eg. 11 it points to the last 802.11b rate (11Mbit),
1178 * if it returns 2 it points to the second 802.11a rate etc.
1179 *
1180 * Same goes for 5212 who has xr/a/b/g support (total 28 rates).
1181 * First comes the XR table, then 802.11a, 802.11b and 802.11g.
1182 * When hw returns eg. 27 it points to the last 802.11g rate (54Mbits) etc
1183 */
1184 static void
1185 ath5k_set_total_hw_rates(struct ath5k_softc *sc) {
1186
1187 struct ath5k_hw *ah = sc->ah;
1188
1189 if (test_bit(AR5K_MODE_11A, ah->ah_modes))
1190 sc->a_rates = 8;
1191
1192 if (test_bit(AR5K_MODE_11B, ah->ah_modes))
1193 sc->b_rates = 4;
1194
1195 if (test_bit(AR5K_MODE_11G, ah->ah_modes))
1196 sc->g_rates = 12;
1197
1198 /* XXX: Need to see what what happens when
1199 xr disable bits in eeprom are set */
1200 if (ah->ah_version >= AR5K_AR5212)
1201 sc->xr_rates = 4;
1202
1203 }
1204
1205 static inline int
1206 ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix) {
1207
1208 int mac80211_rix;
1209
1210 if(sc->curband->band == IEEE80211_BAND_2GHZ) {
1211 /* We setup a g ratetable for both b/g modes */
1212 mac80211_rix =
1213 hw_rix - sc->b_rates - sc->a_rates - sc->xr_rates;
1214 } else {
1215 mac80211_rix = hw_rix - sc->xr_rates;
1216 }
1217
1218 /* Something went wrong, fallback to basic rate for this band */
1219 if ((mac80211_rix >= sc->curband->n_bitrates) ||
1220 (mac80211_rix <= 0 ))
1221 mac80211_rix = 1;
1222
1223 return mac80211_rix;
1224 }
1225
1226
1227
1228
1229 /***************\
1230 * Buffers setup *
1231 \***************/
1232
1233 static int
1234 ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1235 {
1236 struct ath5k_hw *ah = sc->ah;
1237 struct sk_buff *skb = bf->skb;
1238 struct ath5k_desc *ds;
1239
1240 if (likely(skb == NULL)) {
1241 unsigned int off;
1242
1243 /*
1244 * Allocate buffer with headroom_needed space for the
1245 * fake physical layer header at the start.
1246 */
1247 skb = dev_alloc_skb(sc->rxbufsize + sc->cachelsz - 1);
1248 if (unlikely(skb == NULL)) {
1249 ATH5K_ERR(sc, "can't alloc skbuff of size %u\n",
1250 sc->rxbufsize + sc->cachelsz - 1);
1251 return -ENOMEM;
1252 }
1253 /*
1254 * Cache-line-align. This is important (for the
1255 * 5210 at least) as not doing so causes bogus data
1256 * in rx'd frames.
1257 */
1258 off = ((unsigned long)skb->data) % sc->cachelsz;
1259 if (off != 0)
1260 skb_reserve(skb, sc->cachelsz - off);
1261
1262 bf->skb = skb;
1263 bf->skbaddr = pci_map_single(sc->pdev,
1264 skb->data, sc->rxbufsize, PCI_DMA_FROMDEVICE);
1265 if (unlikely(pci_dma_mapping_error(bf->skbaddr))) {
1266 ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__);
1267 dev_kfree_skb(skb);
1268 bf->skb = NULL;
1269 return -ENOMEM;
1270 }
1271 }
1272
1273 /*
1274 * Setup descriptors. For receive we always terminate
1275 * the descriptor list with a self-linked entry so we'll
1276 * not get overrun under high load (as can happen with a
1277 * 5212 when ANI processing enables PHY error frames).
1278 *
1279 * To insure the last descriptor is self-linked we create
1280 * each descriptor as self-linked and add it to the end. As
1281 * each additional descriptor is added the previous self-linked
1282 * entry is ``fixed'' naturally. This should be safe even
1283 * if DMA is happening. When processing RX interrupts we
1284 * never remove/process the last, self-linked, entry on the
1285 * descriptor list. This insures the hardware always has
1286 * someplace to write a new frame.
1287 */
1288 ds = bf->desc;
1289 ds->ds_link = bf->daddr; /* link to self */
1290 ds->ds_data = bf->skbaddr;
1291 ath5k_hw_setup_rx_desc(ah, ds,
1292 skb_tailroom(skb), /* buffer size */
1293 0);
1294
1295 if (sc->rxlink != NULL)
1296 *sc->rxlink = bf->daddr;
1297 sc->rxlink = &ds->ds_link;
1298 return 0;
1299 }
1300
1301 static int
1302 ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf,
1303 struct ieee80211_tx_control *ctl)
1304 {
1305 struct ath5k_hw *ah = sc->ah;
1306 struct ath5k_txq *txq = sc->txq;
1307 struct ath5k_desc *ds = bf->desc;
1308 struct sk_buff *skb = bf->skb;
1309 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
1310 int ret;
1311
1312 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
1313 bf->ctl = *ctl;
1314 /* XXX endianness */
1315 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1316 PCI_DMA_TODEVICE);
1317
1318 if (ctl->flags & IEEE80211_TXCTL_NO_ACK)
1319 flags |= AR5K_TXDESC_NOACK;
1320
1321 pktlen = skb->len;
1322
1323 if (!(ctl->flags & IEEE80211_TXCTL_DO_NOT_ENCRYPT)) {
1324 keyidx = ctl->key_idx;
1325 pktlen += ctl->icv_len;
1326 }
1327
1328 ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
1329 ieee80211_get_hdrlen_from_skb(skb), AR5K_PKT_TYPE_NORMAL,
1330 (sc->power_level * 2), ctl->tx_rate->hw_value,
1331 ctl->retry_limit, keyidx, 0, flags, 0, 0);
1332 if (ret)
1333 goto err_unmap;
1334
1335 ds->ds_link = 0;
1336 ds->ds_data = bf->skbaddr;
1337
1338 spin_lock_bh(&txq->lock);
1339 list_add_tail(&bf->list, &txq->q);
1340 sc->tx_stats.data[txq->qnum].len++;
1341 if (txq->link == NULL) /* is this first packet? */
1342 ath5k_hw_put_tx_buf(ah, txq->qnum, bf->daddr);
1343 else /* no, so only link it */
1344 *txq->link = bf->daddr;
1345
1346 txq->link = &ds->ds_link;
1347 ath5k_hw_tx_start(ah, txq->qnum);
1348 spin_unlock_bh(&txq->lock);
1349
1350 return 0;
1351 err_unmap:
1352 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1353 return ret;
1354 }
1355
1356 /*******************\
1357 * Descriptors setup *
1358 \*******************/
1359
1360 static int
1361 ath5k_desc_alloc(struct ath5k_softc *sc, struct pci_dev *pdev)
1362 {
1363 struct ath5k_desc *ds;
1364 struct ath5k_buf *bf;
1365 dma_addr_t da;
1366 unsigned int i;
1367 int ret;
1368
1369 /* allocate descriptors */
1370 sc->desc_len = sizeof(struct ath5k_desc) *
1371 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
1372 sc->desc = pci_alloc_consistent(pdev, sc->desc_len, &sc->desc_daddr);
1373 if (sc->desc == NULL) {
1374 ATH5K_ERR(sc, "can't allocate descriptors\n");
1375 ret = -ENOMEM;
1376 goto err;
1377 }
1378 ds = sc->desc;
1379 da = sc->desc_daddr;
1380 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
1381 ds, sc->desc_len, (unsigned long long)sc->desc_daddr);
1382
1383 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
1384 sizeof(struct ath5k_buf), GFP_KERNEL);
1385 if (bf == NULL) {
1386 ATH5K_ERR(sc, "can't allocate bufptr\n");
1387 ret = -ENOMEM;
1388 goto err_free;
1389 }
1390 sc->bufptr = bf;
1391
1392 INIT_LIST_HEAD(&sc->rxbuf);
1393 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
1394 bf->desc = ds;
1395 bf->daddr = da;
1396 list_add_tail(&bf->list, &sc->rxbuf);
1397 }
1398
1399 INIT_LIST_HEAD(&sc->txbuf);
1400 sc->txbuf_len = ATH_TXBUF;
1401 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++,
1402 da += sizeof(*ds)) {
1403 bf->desc = ds;
1404 bf->daddr = da;
1405 list_add_tail(&bf->list, &sc->txbuf);
1406 }
1407
1408 /* beacon buffer */
1409 bf->desc = ds;
1410 bf->daddr = da;
1411 sc->bbuf = bf;
1412
1413 return 0;
1414 err_free:
1415 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1416 err:
1417 sc->desc = NULL;
1418 return ret;
1419 }
1420
1421 static void
1422 ath5k_desc_free(struct ath5k_softc *sc, struct pci_dev *pdev)
1423 {
1424 struct ath5k_buf *bf;
1425
1426 ath5k_txbuf_free(sc, sc->bbuf);
1427 list_for_each_entry(bf, &sc->txbuf, list)
1428 ath5k_txbuf_free(sc, bf);
1429 list_for_each_entry(bf, &sc->rxbuf, list)
1430 ath5k_txbuf_free(sc, bf);
1431
1432 /* Free memory associated with all descriptors */
1433 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1434
1435 kfree(sc->bufptr);
1436 sc->bufptr = NULL;
1437 }
1438
1439
1440
1441
1442
1443 /**************\
1444 * Queues setup *
1445 \**************/
1446
1447 static struct ath5k_txq *
1448 ath5k_txq_setup(struct ath5k_softc *sc,
1449 int qtype, int subtype)
1450 {
1451 struct ath5k_hw *ah = sc->ah;
1452 struct ath5k_txq *txq;
1453 struct ath5k_txq_info qi = {
1454 .tqi_subtype = subtype,
1455 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1456 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1457 .tqi_cw_max = AR5K_TXQ_USEDEFAULT
1458 };
1459 int qnum;
1460
1461 /*
1462 * Enable interrupts only for EOL and DESC conditions.
1463 * We mark tx descriptors to receive a DESC interrupt
1464 * when a tx queue gets deep; otherwise waiting for the
1465 * EOL to reap descriptors. Note that this is done to
1466 * reduce interrupt load and this only defers reaping
1467 * descriptors, never transmitting frames. Aside from
1468 * reducing interrupts this also permits more concurrency.
1469 * The only potential downside is if the tx queue backs
1470 * up in which case the top half of the kernel may backup
1471 * due to a lack of tx descriptors.
1472 */
1473 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
1474 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
1475 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
1476 if (qnum < 0) {
1477 /*
1478 * NB: don't print a message, this happens
1479 * normally on parts with too few tx queues
1480 */
1481 return ERR_PTR(qnum);
1482 }
1483 if (qnum >= ARRAY_SIZE(sc->txqs)) {
1484 ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n",
1485 qnum, ARRAY_SIZE(sc->txqs));
1486 ath5k_hw_release_tx_queue(ah, qnum);
1487 return ERR_PTR(-EINVAL);
1488 }
1489 txq = &sc->txqs[qnum];
1490 if (!txq->setup) {
1491 txq->qnum = qnum;
1492 txq->link = NULL;
1493 INIT_LIST_HEAD(&txq->q);
1494 spin_lock_init(&txq->lock);
1495 txq->setup = true;
1496 }
1497 return &sc->txqs[qnum];
1498 }
1499
1500 static int
1501 ath5k_beaconq_setup(struct ath5k_hw *ah)
1502 {
1503 struct ath5k_txq_info qi = {
1504 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1505 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1506 .tqi_cw_max = AR5K_TXQ_USEDEFAULT,
1507 /* NB: for dynamic turbo, don't enable any other interrupts */
1508 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
1509 };
1510
1511 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
1512 }
1513
1514 static int
1515 ath5k_beaconq_config(struct ath5k_softc *sc)
1516 {
1517 struct ath5k_hw *ah = sc->ah;
1518 struct ath5k_txq_info qi;
1519 int ret;
1520
1521 ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi);
1522 if (ret)
1523 return ret;
1524 if (sc->opmode == IEEE80211_IF_TYPE_AP) {
1525 /*
1526 * Always burst out beacon and CAB traffic
1527 * (aifs = cwmin = cwmax = 0)
1528 */
1529 qi.tqi_aifs = 0;
1530 qi.tqi_cw_min = 0;
1531 qi.tqi_cw_max = 0;
1532 } else if (sc->opmode == IEEE80211_IF_TYPE_IBSS) {
1533 /*
1534 * Adhoc mode; backoff between 0 and (2 * cw_min).
1535 */
1536 qi.tqi_aifs = 0;
1537 qi.tqi_cw_min = 0;
1538 qi.tqi_cw_max = 2 * ah->ah_cw_min;
1539 }
1540
1541 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1542 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1543 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
1544
1545 ret = ath5k_hw_setup_tx_queueprops(ah, sc->bhalq, &qi);
1546 if (ret) {
1547 ATH5K_ERR(sc, "%s: unable to update parameters for beacon "
1548 "hardware queue!\n", __func__);
1549 return ret;
1550 }
1551
1552 return ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */;
1553 }
1554
1555 static void
1556 ath5k_txq_drainq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1557 {
1558 struct ath5k_buf *bf, *bf0;
1559
1560 /*
1561 * NB: this assumes output has been stopped and
1562 * we do not need to block ath5k_tx_tasklet
1563 */
1564 spin_lock_bh(&txq->lock);
1565 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1566 ath5k_debug_printtxbuf(sc, bf, !sc->ah->ah_proc_tx_desc(sc->ah,
1567 bf->desc));
1568
1569 ath5k_txbuf_free(sc, bf);
1570
1571 spin_lock_bh(&sc->txbuflock);
1572 sc->tx_stats.data[txq->qnum].len--;
1573 list_move_tail(&bf->list, &sc->txbuf);
1574 sc->txbuf_len++;
1575 spin_unlock_bh(&sc->txbuflock);
1576 }
1577 txq->link = NULL;
1578 spin_unlock_bh(&txq->lock);
1579 }
1580
1581 /*
1582 * Drain the transmit queues and reclaim resources.
1583 */
1584 static void
1585 ath5k_txq_cleanup(struct ath5k_softc *sc)
1586 {
1587 struct ath5k_hw *ah = sc->ah;
1588 unsigned int i;
1589
1590 /* XXX return value */
1591 if (likely(!test_bit(ATH_STAT_INVALID, sc->status))) {
1592 /* don't touch the hardware if marked invalid */
1593 ath5k_hw_stop_tx_dma(ah, sc->bhalq);
1594 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "beacon queue %x\n",
1595 ath5k_hw_get_tx_buf(ah, sc->bhalq));
1596 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1597 if (sc->txqs[i].setup) {
1598 ath5k_hw_stop_tx_dma(ah, sc->txqs[i].qnum);
1599 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "txq [%u] %x, "
1600 "link %p\n",
1601 sc->txqs[i].qnum,
1602 ath5k_hw_get_tx_buf(ah,
1603 sc->txqs[i].qnum),
1604 sc->txqs[i].link);
1605 }
1606 }
1607 ieee80211_start_queues(sc->hw); /* XXX move to callers */
1608
1609 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1610 if (sc->txqs[i].setup)
1611 ath5k_txq_drainq(sc, &sc->txqs[i]);
1612 }
1613
1614 static void
1615 ath5k_txq_release(struct ath5k_softc *sc)
1616 {
1617 struct ath5k_txq *txq = sc->txqs;
1618 unsigned int i;
1619
1620 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++)
1621 if (txq->setup) {
1622 ath5k_hw_release_tx_queue(sc->ah, txq->qnum);
1623 txq->setup = false;
1624 }
1625 }
1626
1627
1628
1629
1630 /*************\
1631 * RX Handling *
1632 \*************/
1633
1634 /*
1635 * Enable the receive h/w following a reset.
1636 */
1637 static int
1638 ath5k_rx_start(struct ath5k_softc *sc)
1639 {
1640 struct ath5k_hw *ah = sc->ah;
1641 struct ath5k_buf *bf;
1642 int ret;
1643
1644 sc->rxbufsize = roundup(IEEE80211_MAX_LEN, sc->cachelsz);
1645
1646 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rxbufsize %u\n",
1647 sc->cachelsz, sc->rxbufsize);
1648
1649 sc->rxlink = NULL;
1650
1651 spin_lock_bh(&sc->rxbuflock);
1652 list_for_each_entry(bf, &sc->rxbuf, list) {
1653 ret = ath5k_rxbuf_setup(sc, bf);
1654 if (ret != 0) {
1655 spin_unlock_bh(&sc->rxbuflock);
1656 goto err;
1657 }
1658 }
1659 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1660 spin_unlock_bh(&sc->rxbuflock);
1661
1662 ath5k_hw_put_rx_buf(ah, bf->daddr);
1663 ath5k_hw_start_rx(ah); /* enable recv descriptors */
1664 ath5k_mode_setup(sc); /* set filters, etc. */
1665 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
1666
1667 return 0;
1668 err:
1669 return ret;
1670 }
1671
1672 /*
1673 * Disable the receive h/w in preparation for a reset.
1674 */
1675 static void
1676 ath5k_rx_stop(struct ath5k_softc *sc)
1677 {
1678 struct ath5k_hw *ah = sc->ah;
1679
1680 ath5k_hw_stop_pcu_recv(ah); /* disable PCU */
1681 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */
1682 ath5k_hw_stop_rx_dma(ah); /* disable DMA engine */
1683 mdelay(3); /* 3ms is long enough for 1 frame */
1684
1685 ath5k_debug_printrxbuffs(sc, ah);
1686
1687 sc->rxlink = NULL; /* just in case */
1688 }
1689
1690 static unsigned int
1691 ath5k_rx_decrypted(struct ath5k_softc *sc, struct ath5k_desc *ds,
1692 struct sk_buff *skb)
1693 {
1694 struct ieee80211_hdr *hdr = (void *)skb->data;
1695 unsigned int keyix, hlen = ieee80211_get_hdrlen_from_skb(skb);
1696
1697 if (!(ds->ds_rxstat.rs_status & AR5K_RXERR_DECRYPT) &&
1698 ds->ds_rxstat.rs_keyix != AR5K_RXKEYIX_INVALID)
1699 return RX_FLAG_DECRYPTED;
1700
1701 /* Apparently when a default key is used to decrypt the packet
1702 the hw does not set the index used to decrypt. In such cases
1703 get the index from the packet. */
1704 if ((le16_to_cpu(hdr->frame_control) & IEEE80211_FCTL_PROTECTED) &&
1705 !(ds->ds_rxstat.rs_status & AR5K_RXERR_DECRYPT) &&
1706 skb->len >= hlen + 4) {
1707 keyix = skb->data[hlen + 3] >> 6;
1708
1709 if (test_bit(keyix, sc->keymap))
1710 return RX_FLAG_DECRYPTED;
1711 }
1712
1713 return 0;
1714 }
1715
1716
1717 static void
1718 ath5k_check_ibss_hw_merge(struct ath5k_softc *sc, struct sk_buff *skb)
1719 {
1720 u32 hw_tu;
1721 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1722
1723 if ((le16_to_cpu(mgmt->frame_control) & IEEE80211_FCTL_FTYPE) ==
1724 IEEE80211_FTYPE_MGMT &&
1725 (le16_to_cpu(mgmt->frame_control) & IEEE80211_FCTL_STYPE) ==
1726 IEEE80211_STYPE_BEACON &&
1727 le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS &&
1728 memcmp(mgmt->bssid, sc->ah->ah_bssid, ETH_ALEN) == 0) {
1729 /*
1730 * Received an IBSS beacon with the same BSSID. Hardware might
1731 * have updated the TSF, check if we need to update timers.
1732 */
1733 hw_tu = TSF_TO_TU(ath5k_hw_get_tsf64(sc->ah));
1734 if (hw_tu >= sc->nexttbtt) {
1735 ath5k_beacon_update_timers(sc,
1736 le64_to_cpu(mgmt->u.beacon.timestamp));
1737 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1738 "detected HW merge from received beacon\n");
1739 }
1740 }
1741 }
1742
1743
1744 static void
1745 ath5k_tasklet_rx(unsigned long data)
1746 {
1747 struct ieee80211_rx_status rxs = {};
1748 struct sk_buff *skb;
1749 struct ath5k_softc *sc = (void *)data;
1750 struct ath5k_buf *bf;
1751 struct ath5k_desc *ds;
1752 u16 len;
1753 u8 stat;
1754 int ret;
1755 int hdrlen;
1756 int pad;
1757
1758 spin_lock(&sc->rxbuflock);
1759 do {
1760 if (unlikely(list_empty(&sc->rxbuf))) {
1761 ATH5K_WARN(sc, "empty rx buf pool\n");
1762 break;
1763 }
1764 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1765 BUG_ON(bf->skb == NULL);
1766 skb = bf->skb;
1767 ds = bf->desc;
1768
1769 /* TODO only one segment */
1770 pci_dma_sync_single_for_cpu(sc->pdev, sc->desc_daddr,
1771 sc->desc_len, PCI_DMA_FROMDEVICE);
1772
1773 if (unlikely(ds->ds_link == bf->daddr)) /* this is the end */
1774 break;
1775
1776 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds);
1777 if (unlikely(ret == -EINPROGRESS))
1778 break;
1779 else if (unlikely(ret)) {
1780 ATH5K_ERR(sc, "error in processing rx descriptor\n");
1781 spin_unlock(&sc->rxbuflock);
1782 return;
1783 }
1784
1785 if (unlikely(ds->ds_rxstat.rs_more)) {
1786 ATH5K_WARN(sc, "unsupported jumbo\n");
1787 goto next;
1788 }
1789
1790 stat = ds->ds_rxstat.rs_status;
1791 if (unlikely(stat)) {
1792 if (stat & AR5K_RXERR_PHY)
1793 goto next;
1794 if (stat & AR5K_RXERR_DECRYPT) {
1795 /*
1796 * Decrypt error. If the error occurred
1797 * because there was no hardware key, then
1798 * let the frame through so the upper layers
1799 * can process it. This is necessary for 5210
1800 * parts which have no way to setup a ``clear''
1801 * key cache entry.
1802 *
1803 * XXX do key cache faulting
1804 */
1805 if (ds->ds_rxstat.rs_keyix ==
1806 AR5K_RXKEYIX_INVALID &&
1807 !(stat & AR5K_RXERR_CRC))
1808 goto accept;
1809 }
1810 if (stat & AR5K_RXERR_MIC) {
1811 rxs.flag |= RX_FLAG_MMIC_ERROR;
1812 goto accept;
1813 }
1814
1815 /* let crypto-error packets fall through in MNTR */
1816 if ((stat & ~(AR5K_RXERR_DECRYPT|AR5K_RXERR_MIC)) ||
1817 sc->opmode != IEEE80211_IF_TYPE_MNTR)
1818 goto next;
1819 }
1820 accept:
1821 len = ds->ds_rxstat.rs_datalen;
1822 pci_dma_sync_single_for_cpu(sc->pdev, bf->skbaddr, len,
1823 PCI_DMA_FROMDEVICE);
1824 pci_unmap_single(sc->pdev, bf->skbaddr, sc->rxbufsize,
1825 PCI_DMA_FROMDEVICE);
1826 bf->skb = NULL;
1827
1828 skb_put(skb, len);
1829
1830 /*
1831 * the hardware adds a padding to 4 byte boundaries between
1832 * the header and the payload data if the header length is
1833 * not multiples of 4 - remove it
1834 */
1835 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1836 if (hdrlen & 3) {
1837 pad = hdrlen % 4;
1838 memmove(skb->data + pad, skb->data, hdrlen);
1839 skb_pull(skb, pad);
1840 }
1841
1842 /*
1843 * always extend the mac timestamp, since this information is
1844 * also needed for proper IBSS merging.
1845 *
1846 * XXX: it might be too late to do it here, since rs_tstamp is
1847 * 15bit only. that means TSF extension has to be done within
1848 * 32768usec (about 32ms). it might be necessary to move this to
1849 * the interrupt handler, like it is done in madwifi.
1850 */
1851 rxs.mactime = ath5k_extend_tsf(sc->ah, ds->ds_rxstat.rs_tstamp);
1852 rxs.flag |= RX_FLAG_TSFT;
1853
1854 rxs.freq = sc->curchan->center_freq;
1855 rxs.band = sc->curband->band;
1856
1857 /*
1858 * signal quality:
1859 * the names here are misleading and the usage of these
1860 * values by iwconfig makes it even worse
1861 */
1862 /* noise floor in dBm, from the last noise calibration */
1863 rxs.noise = sc->ah->ah_noise_floor;
1864 /* signal level in dBm */
1865 rxs.ssi = rxs.noise + ds->ds_rxstat.rs_rssi;
1866 /*
1867 * "signal" is actually displayed as Link Quality by iwconfig
1868 * we provide a percentage based on rssi (assuming max rssi 64)
1869 */
1870 rxs.signal = ds->ds_rxstat.rs_rssi * 100 / 64;
1871
1872 rxs.antenna = ds->ds_rxstat.rs_antenna;
1873 rxs.rate_idx = ath5k_hw_to_driver_rix(sc,
1874 ds->ds_rxstat.rs_rate);
1875 rxs.flag |= ath5k_rx_decrypted(sc, ds, skb);
1876
1877 ath5k_debug_dump_skb(sc, skb, "RX ", 0);
1878
1879 /* check beacons in IBSS mode */
1880 if (sc->opmode == IEEE80211_IF_TYPE_IBSS)
1881 ath5k_check_ibss_hw_merge(sc, skb);
1882
1883 __ieee80211_rx(sc->hw, skb, &rxs);
1884 sc->led_rxrate = ds->ds_rxstat.rs_rate;
1885 ath5k_led_event(sc, ATH_LED_RX);
1886 next:
1887 list_move_tail(&bf->list, &sc->rxbuf);
1888 } while (ath5k_rxbuf_setup(sc, bf) == 0);
1889 spin_unlock(&sc->rxbuflock);
1890 }
1891
1892
1893
1894
1895 /*************\
1896 * TX Handling *
1897 \*************/
1898
1899 static void
1900 ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1901 {
1902 struct ieee80211_tx_status txs = {};
1903 struct ath5k_buf *bf, *bf0;
1904 struct ath5k_desc *ds;
1905 struct sk_buff *skb;
1906 int ret;
1907
1908 spin_lock(&txq->lock);
1909 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1910 ds = bf->desc;
1911
1912 /* TODO only one segment */
1913 pci_dma_sync_single_for_cpu(sc->pdev, sc->desc_daddr,
1914 sc->desc_len, PCI_DMA_FROMDEVICE);
1915 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds);
1916 if (unlikely(ret == -EINPROGRESS))
1917 break;
1918 else if (unlikely(ret)) {
1919 ATH5K_ERR(sc, "error %d while processing queue %u\n",
1920 ret, txq->qnum);
1921 break;
1922 }
1923
1924 skb = bf->skb;
1925 bf->skb = NULL;
1926 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len,
1927 PCI_DMA_TODEVICE);
1928
1929 txs.control = bf->ctl;
1930 txs.retry_count = ds->ds_txstat.ts_shortretry +
1931 ds->ds_txstat.ts_longretry / 6;
1932 if (unlikely(ds->ds_txstat.ts_status)) {
1933 sc->ll_stats.dot11ACKFailureCount++;
1934 if (ds->ds_txstat.ts_status & AR5K_TXERR_XRETRY)
1935 txs.excessive_retries = 1;
1936 else if (ds->ds_txstat.ts_status & AR5K_TXERR_FILT)
1937 txs.flags |= IEEE80211_TX_STATUS_TX_FILTERED;
1938 } else {
1939 txs.flags |= IEEE80211_TX_STATUS_ACK;
1940 txs.ack_signal = ds->ds_txstat.ts_rssi;
1941 }
1942
1943 ieee80211_tx_status(sc->hw, skb, &txs);
1944 sc->tx_stats.data[txq->qnum].count++;
1945
1946 spin_lock(&sc->txbuflock);
1947 sc->tx_stats.data[txq->qnum].len--;
1948 list_move_tail(&bf->list, &sc->txbuf);
1949 sc->txbuf_len++;
1950 spin_unlock(&sc->txbuflock);
1951 }
1952 if (likely(list_empty(&txq->q)))
1953 txq->link = NULL;
1954 spin_unlock(&txq->lock);
1955 if (sc->txbuf_len > ATH_TXBUF / 5)
1956 ieee80211_wake_queues(sc->hw);
1957 }
1958
1959 static void
1960 ath5k_tasklet_tx(unsigned long data)
1961 {
1962 struct ath5k_softc *sc = (void *)data;
1963
1964 ath5k_tx_processq(sc, sc->txq);
1965
1966 ath5k_led_event(sc, ATH_LED_TX);
1967 }
1968
1969
1970
1971
1972 /*****************\
1973 * Beacon handling *
1974 \*****************/
1975
1976 /*
1977 * Setup the beacon frame for transmit.
1978 */
1979 static int
1980 ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf,
1981 struct ieee80211_tx_control *ctl)
1982 {
1983 struct sk_buff *skb = bf->skb;
1984 struct ath5k_hw *ah = sc->ah;
1985 struct ath5k_desc *ds;
1986 int ret, antenna = 0;
1987 u32 flags;
1988
1989 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1990 PCI_DMA_TODEVICE);
1991 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
1992 "skbaddr %llx\n", skb, skb->data, skb->len,
1993 (unsigned long long)bf->skbaddr);
1994 if (pci_dma_mapping_error(bf->skbaddr)) {
1995 ATH5K_ERR(sc, "beacon DMA mapping failed\n");
1996 return -EIO;
1997 }
1998
1999 ds = bf->desc;
2000
2001 flags = AR5K_TXDESC_NOACK;
2002 if (sc->opmode == IEEE80211_IF_TYPE_IBSS && ath5k_hw_hasveol(ah)) {
2003 ds->ds_link = bf->daddr; /* self-linked */
2004 flags |= AR5K_TXDESC_VEOL;
2005 /*
2006 * Let hardware handle antenna switching if txantenna is not set
2007 */
2008 } else {
2009 ds->ds_link = 0;
2010 /*
2011 * Switch antenna every 4 beacons if txantenna is not set
2012 * XXX assumes two antennas
2013 */
2014 if (antenna == 0)
2015 antenna = sc->bsent & 4 ? 2 : 1;
2016 }
2017
2018 ds->ds_data = bf->skbaddr;
2019 ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
2020 ieee80211_get_hdrlen_from_skb(skb),
2021 AR5K_PKT_TYPE_BEACON, (sc->power_level * 2),
2022 ctl->tx_rate->hw_value, 1, AR5K_TXKEYIX_INVALID,
2023 antenna, flags, 0, 0);
2024 if (ret)
2025 goto err_unmap;
2026
2027 return 0;
2028 err_unmap:
2029 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
2030 return ret;
2031 }
2032
2033 /*
2034 * Transmit a beacon frame at SWBA. Dynamic updates to the
2035 * frame contents are done as needed and the slot time is
2036 * also adjusted based on current state.
2037 *
2038 * this is usually called from interrupt context (ath5k_intr())
2039 * but also from ath5k_beacon_config() in IBSS mode which in turn
2040 * can be called from a tasklet and user context
2041 */
2042 static void
2043 ath5k_beacon_send(struct ath5k_softc *sc)
2044 {
2045 struct ath5k_buf *bf = sc->bbuf;
2046 struct ath5k_hw *ah = sc->ah;
2047
2048 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n");
2049
2050 if (unlikely(bf->skb == NULL || sc->opmode == IEEE80211_IF_TYPE_STA ||
2051 sc->opmode == IEEE80211_IF_TYPE_MNTR)) {
2052 ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
2053 return;
2054 }
2055 /*
2056 * Check if the previous beacon has gone out. If
2057 * not don't don't try to post another, skip this
2058 * period and wait for the next. Missed beacons
2059 * indicate a problem and should not occur. If we
2060 * miss too many consecutive beacons reset the device.
2061 */
2062 if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) {
2063 sc->bmisscount++;
2064 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2065 "missed %u consecutive beacons\n", sc->bmisscount);
2066 if (sc->bmisscount > 3) { /* NB: 3 is a guess */
2067 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2068 "stuck beacon time (%u missed)\n",
2069 sc->bmisscount);
2070 tasklet_schedule(&sc->restq);
2071 }
2072 return;
2073 }
2074 if (unlikely(sc->bmisscount != 0)) {
2075 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2076 "resume beacon xmit after %u misses\n",
2077 sc->bmisscount);
2078 sc->bmisscount = 0;
2079 }
2080
2081 /*
2082 * Stop any current dma and put the new frame on the queue.
2083 * This should never fail since we check above that no frames
2084 * are still pending on the queue.
2085 */
2086 if (unlikely(ath5k_hw_stop_tx_dma(ah, sc->bhalq))) {
2087 ATH5K_WARN(sc, "beacon queue %u didn't stop?\n", sc->bhalq);
2088 /* NB: hw still stops DMA, so proceed */
2089 }
2090 pci_dma_sync_single_for_cpu(sc->pdev, bf->skbaddr, bf->skb->len,
2091 PCI_DMA_TODEVICE);
2092
2093 ath5k_hw_put_tx_buf(ah, sc->bhalq, bf->daddr);
2094 ath5k_hw_tx_start(ah, sc->bhalq);
2095 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
2096 sc->bhalq, (unsigned long long)bf->daddr, bf->desc);
2097
2098 sc->bsent++;
2099 }
2100
2101
2102 /**
2103 * ath5k_beacon_update_timers - update beacon timers
2104 *
2105 * @sc: struct ath5k_softc pointer we are operating on
2106 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
2107 * beacon timer update based on the current HW TSF.
2108 *
2109 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
2110 * of a received beacon or the current local hardware TSF and write it to the
2111 * beacon timer registers.
2112 *
2113 * This is called in a variety of situations, e.g. when a beacon is received,
2114 * when a HW merge has been detected, but also when an new IBSS is created or
2115 * when we otherwise know we have to update the timers, but we keep it in this
2116 * function to have it all together in one place.
2117 */
2118 static void
2119 ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
2120 {
2121 struct ath5k_hw *ah = sc->ah;
2122 u32 nexttbtt, intval, hw_tu, bc_tu;
2123 u64 hw_tsf;
2124
2125 intval = sc->bintval & AR5K_BEACON_PERIOD;
2126 if (WARN_ON(!intval))
2127 return;
2128
2129 /* beacon TSF converted to TU */
2130 bc_tu = TSF_TO_TU(bc_tsf);
2131
2132 /* current TSF converted to TU */
2133 hw_tsf = ath5k_hw_get_tsf64(ah);
2134 hw_tu = TSF_TO_TU(hw_tsf);
2135
2136 #define FUDGE 3
2137 /* we use FUDGE to make sure the next TBTT is ahead of the current TU */
2138 if (bc_tsf == -1) {
2139 /*
2140 * no beacons received, called internally.
2141 * just need to refresh timers based on HW TSF.
2142 */
2143 nexttbtt = roundup(hw_tu + FUDGE, intval);
2144 } else if (bc_tsf == 0) {
2145 /*
2146 * no beacon received, probably called by ath5k_reset_tsf().
2147 * reset TSF to start with 0.
2148 */
2149 nexttbtt = intval;
2150 intval |= AR5K_BEACON_RESET_TSF;
2151 } else if (bc_tsf > hw_tsf) {
2152 /*
2153 * beacon received, SW merge happend but HW TSF not yet updated.
2154 * not possible to reconfigure timers yet, but next time we
2155 * receive a beacon with the same BSSID, the hardware will
2156 * automatically update the TSF and then we need to reconfigure
2157 * the timers.
2158 */
2159 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2160 "need to wait for HW TSF sync\n");
2161 return;
2162 } else {
2163 /*
2164 * most important case for beacon synchronization between STA.
2165 *
2166 * beacon received and HW TSF has been already updated by HW.
2167 * update next TBTT based on the TSF of the beacon, but make
2168 * sure it is ahead of our local TSF timer.
2169 */
2170 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
2171 }
2172 #undef FUDGE
2173
2174 sc->nexttbtt = nexttbtt;
2175
2176 intval |= AR5K_BEACON_ENA;
2177 ath5k_hw_init_beacon(ah, nexttbtt, intval);
2178
2179 /*
2180 * debugging output last in order to preserve the time critical aspect
2181 * of this function
2182 */
2183 if (bc_tsf == -1)
2184 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2185 "reconfigured timers based on HW TSF\n");
2186 else if (bc_tsf == 0)
2187 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2188 "reset HW TSF and timers\n");
2189 else
2190 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2191 "updated timers based on beacon TSF\n");
2192
2193 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2194 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2195 (unsigned long long) bc_tsf,
2196 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
2197 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
2198 intval & AR5K_BEACON_PERIOD,
2199 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2200 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
2201 }
2202
2203
2204 /**
2205 * ath5k_beacon_config - Configure the beacon queues and interrupts
2206 *
2207 * @sc: struct ath5k_softc pointer we are operating on
2208 *
2209 * When operating in station mode we want to receive a BMISS interrupt when we
2210 * stop seeing beacons from the AP we've associated with so we can look for
2211 * another AP to associate with.
2212 *
2213 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
2214 * interrupts to detect HW merges only.
2215 *
2216 * AP mode is missing.
2217 */
2218 static void
2219 ath5k_beacon_config(struct ath5k_softc *sc)
2220 {
2221 struct ath5k_hw *ah = sc->ah;
2222
2223 ath5k_hw_set_intr(ah, 0);
2224 sc->bmisscount = 0;
2225
2226 if (sc->opmode == IEEE80211_IF_TYPE_STA) {
2227 sc->imask |= AR5K_INT_BMISS;
2228 } else if (sc->opmode == IEEE80211_IF_TYPE_IBSS) {
2229 /*
2230 * In IBSS mode we use a self-linked tx descriptor and let the
2231 * hardware send the beacons automatically. We have to load it
2232 * only once here.
2233 * We use the SWBA interrupt only to keep track of the beacon
2234 * timers in order to detect HW merges (automatic TSF updates).
2235 */
2236 ath5k_beaconq_config(sc);
2237
2238 sc->imask |= AR5K_INT_SWBA;
2239
2240 if (ath5k_hw_hasveol(ah))
2241 ath5k_beacon_send(sc);
2242 }
2243 /* TODO else AP */
2244
2245 ath5k_hw_set_intr(ah, sc->imask);
2246 }
2247
2248
2249 /********************\
2250 * Interrupt handling *
2251 \********************/
2252
2253 static int
2254 ath5k_init(struct ath5k_softc *sc)
2255 {
2256 int ret;
2257
2258 mutex_lock(&sc->lock);
2259
2260 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode);
2261
2262 /*
2263 * Stop anything previously setup. This is safe
2264 * no matter this is the first time through or not.
2265 */
2266 ath5k_stop_locked(sc);
2267
2268 /*
2269 * The basic interface to setting the hardware in a good
2270 * state is ``reset''. On return the hardware is known to
2271 * be powered up and with interrupts disabled. This must
2272 * be followed by initialization of the appropriate bits
2273 * and then setup of the interrupt mask.
2274 */
2275 sc->curchan = sc->hw->conf.channel;
2276 sc->curband = &sc->sbands[sc->curchan->band];
2277 ret = ath5k_hw_reset(sc->ah, sc->opmode, sc->curchan, false);
2278 if (ret) {
2279 ATH5K_ERR(sc, "unable to reset hardware: %d\n", ret);
2280 goto done;
2281 }
2282 /*
2283 * This is needed only to setup initial state
2284 * but it's best done after a reset.
2285 */
2286 ath5k_hw_set_txpower_limit(sc->ah, 0);
2287
2288 /*
2289 * Setup the hardware after reset: the key cache
2290 * is filled as needed and the receive engine is
2291 * set going. Frame transmit is handled entirely
2292 * in the frame output path; there's nothing to do
2293 * here except setup the interrupt mask.
2294 */
2295 ret = ath5k_rx_start(sc);
2296 if (ret)
2297 goto done;
2298
2299 /*
2300 * Enable interrupts.
2301 */
2302 sc->imask = AR5K_INT_RX | AR5K_INT_TX | AR5K_INT_RXEOL |
2303 AR5K_INT_RXORN | AR5K_INT_FATAL | AR5K_INT_GLOBAL;
2304
2305 ath5k_hw_set_intr(sc->ah, sc->imask);
2306 /* Set ack to be sent at low bit-rates */
2307 ath5k_hw_set_ack_bitrate_high(sc->ah, false);
2308
2309 mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2310 msecs_to_jiffies(ath5k_calinterval * 1000)));
2311
2312 ret = 0;
2313 done:
2314 mutex_unlock(&sc->lock);
2315 return ret;
2316 }
2317
2318 static int
2319 ath5k_stop_locked(struct ath5k_softc *sc)
2320 {
2321 struct ath5k_hw *ah = sc->ah;
2322
2323 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n",
2324 test_bit(ATH_STAT_INVALID, sc->status));
2325
2326 /*
2327 * Shutdown the hardware and driver:
2328 * stop output from above
2329 * disable interrupts
2330 * turn off timers
2331 * turn off the radio
2332 * clear transmit machinery
2333 * clear receive machinery
2334 * drain and release tx queues
2335 * reclaim beacon resources
2336 * power down hardware
2337 *
2338 * Note that some of this work is not possible if the
2339 * hardware is gone (invalid).
2340 */
2341 ieee80211_stop_queues(sc->hw);
2342
2343 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2344 if (test_bit(ATH_STAT_LEDSOFT, sc->status)) {
2345 del_timer_sync(&sc->led_tim);
2346 ath5k_hw_set_gpio(ah, sc->led_pin, !sc->led_on);
2347 __clear_bit(ATH_STAT_LEDBLINKING, sc->status);
2348 }
2349 ath5k_hw_set_intr(ah, 0);
2350 }
2351 ath5k_txq_cleanup(sc);
2352 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2353 ath5k_rx_stop(sc);
2354 ath5k_hw_phy_disable(ah);
2355 } else
2356 sc->rxlink = NULL;
2357
2358 return 0;
2359 }
2360
2361 /*
2362 * Stop the device, grabbing the top-level lock to protect
2363 * against concurrent entry through ath5k_init (which can happen
2364 * if another thread does a system call and the thread doing the
2365 * stop is preempted).
2366 */
2367 static int
2368 ath5k_stop_hw(struct ath5k_softc *sc)
2369 {
2370 int ret;
2371
2372 mutex_lock(&sc->lock);
2373 ret = ath5k_stop_locked(sc);
2374 if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
2375 /*
2376 * Set the chip in full sleep mode. Note that we are
2377 * careful to do this only when bringing the interface
2378 * completely to a stop. When the chip is in this state
2379 * it must be carefully woken up or references to
2380 * registers in the PCI clock domain may freeze the bus
2381 * (and system). This varies by chip and is mostly an
2382 * issue with newer parts that go to sleep more quickly.
2383 */
2384 if (sc->ah->ah_mac_srev >= 0x78) {
2385 /*
2386 * XXX
2387 * don't put newer MAC revisions > 7.8 to sleep because
2388 * of the above mentioned problems
2389 */
2390 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mac version > 7.8, "
2391 "not putting device to sleep\n");
2392 } else {
2393 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2394 "putting device to full sleep\n");
2395 ath5k_hw_set_power(sc->ah, AR5K_PM_FULL_SLEEP, true, 0);
2396 }
2397 }
2398 ath5k_txbuf_free(sc, sc->bbuf);
2399 mutex_unlock(&sc->lock);
2400
2401 del_timer_sync(&sc->calib_tim);
2402
2403 return ret;
2404 }
2405
2406 static irqreturn_t
2407 ath5k_intr(int irq, void *dev_id)
2408 {
2409 struct ath5k_softc *sc = dev_id;
2410 struct ath5k_hw *ah = sc->ah;
2411 enum ath5k_int status;
2412 unsigned int counter = 1000;
2413
2414 if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) ||
2415 !ath5k_hw_is_intr_pending(ah)))
2416 return IRQ_NONE;
2417
2418 do {
2419 /*
2420 * Figure out the reason(s) for the interrupt. Note
2421 * that get_isr returns a pseudo-ISR that may include
2422 * bits we haven't explicitly enabled so we mask the
2423 * value to insure we only process bits we requested.
2424 */
2425 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
2426 ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2427 status, sc->imask);
2428 status &= sc->imask; /* discard unasked for bits */
2429 if (unlikely(status & AR5K_INT_FATAL)) {
2430 /*
2431 * Fatal errors are unrecoverable.
2432 * Typically these are caused by DMA errors.
2433 */
2434 tasklet_schedule(&sc->restq);
2435 } else if (unlikely(status & AR5K_INT_RXORN)) {
2436 tasklet_schedule(&sc->restq);
2437 } else {
2438 if (status & AR5K_INT_SWBA) {
2439 /*
2440 * Software beacon alert--time to send a beacon.
2441 * Handle beacon transmission directly; deferring
2442 * this is too slow to meet timing constraints
2443 * under load.
2444 *
2445 * In IBSS mode we use this interrupt just to
2446 * keep track of the next TBTT (target beacon
2447 * transmission time) in order to detect hardware
2448 * merges (TSF updates).
2449 */
2450 if (sc->opmode == IEEE80211_IF_TYPE_IBSS) {
2451 /* XXX: only if VEOL suppported */
2452 u64 tsf = ath5k_hw_get_tsf64(ah);
2453 sc->nexttbtt += sc->bintval;
2454 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2455 "SWBA nexttbtt: %x hw_tu: %x "
2456 "TSF: %llx\n",
2457 sc->nexttbtt,
2458 TSF_TO_TU(tsf),
2459 (unsigned long long) tsf);
2460 } else {
2461 ath5k_beacon_send(sc);
2462 }
2463 }
2464 if (status & AR5K_INT_RXEOL) {
2465 /*
2466 * NB: the hardware should re-read the link when
2467 * RXE bit is written, but it doesn't work at
2468 * least on older hardware revs.
2469 */
2470 sc->rxlink = NULL;
2471 }
2472 if (status & AR5K_INT_TXURN) {
2473 /* bump tx trigger level */
2474 ath5k_hw_update_tx_triglevel(ah, true);
2475 }
2476 if (status & AR5K_INT_RX)
2477 tasklet_schedule(&sc->rxtq);
2478 if (status & AR5K_INT_TX)
2479 tasklet_schedule(&sc->txtq);
2480 if (status & AR5K_INT_BMISS) {
2481 }
2482 if (status & AR5K_INT_MIB) {
2483 /* TODO */
2484 }
2485 }
2486 } while (ath5k_hw_is_intr_pending(ah) && counter-- > 0);
2487
2488 if (unlikely(!counter))
2489 ATH5K_WARN(sc, "too many interrupts, giving up for now\n");
2490
2491 return IRQ_HANDLED;
2492 }
2493
2494 static void
2495 ath5k_tasklet_reset(unsigned long data)
2496 {
2497 struct ath5k_softc *sc = (void *)data;
2498
2499 ath5k_reset(sc->hw);
2500 }
2501
2502 /*
2503 * Periodically recalibrate the PHY to account
2504 * for temperature/environment changes.
2505 */
2506 static void
2507 ath5k_calibrate(unsigned long data)
2508 {
2509 struct ath5k_softc *sc = (void *)data;
2510 struct ath5k_hw *ah = sc->ah;
2511
2512 ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
2513 ieee80211_frequency_to_channel(sc->curchan->center_freq),
2514 sc->curchan->hw_value);
2515
2516 if (ath5k_hw_get_rf_gain(ah) == AR5K_RFGAIN_NEED_CHANGE) {
2517 /*
2518 * Rfgain is out of bounds, reset the chip
2519 * to load new gain values.
2520 */
2521 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n");
2522 ath5k_reset(sc->hw);
2523 }
2524 if (ath5k_hw_phy_calibrate(ah, sc->curchan))
2525 ATH5K_ERR(sc, "calibration of channel %u failed\n",
2526 ieee80211_frequency_to_channel(
2527 sc->curchan->center_freq));
2528
2529 mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2530 msecs_to_jiffies(ath5k_calinterval * 1000)));
2531 }
2532
2533
2534
2535 /***************\
2536 * LED functions *
2537 \***************/
2538
2539 static void
2540 ath5k_led_off(unsigned long data)
2541 {
2542 struct ath5k_softc *sc = (void *)data;
2543
2544 if (test_bit(ATH_STAT_LEDENDBLINK, sc->status))
2545 __clear_bit(ATH_STAT_LEDBLINKING, sc->status);
2546 else {
2547 __set_bit(ATH_STAT_LEDENDBLINK, sc->status);
2548 ath5k_hw_set_gpio(sc->ah, sc->led_pin, !sc->led_on);
2549 mod_timer(&sc->led_tim, jiffies + sc->led_off);
2550 }
2551 }
2552
2553 /*
2554 * Blink the LED according to the specified on/off times.
2555 */
2556 static void
2557 ath5k_led_blink(struct ath5k_softc *sc, unsigned int on,
2558 unsigned int off)
2559 {
2560 ATH5K_DBG(sc, ATH5K_DEBUG_LED, "on %u off %u\n", on, off);
2561 ath5k_hw_set_gpio(sc->ah, sc->led_pin, sc->led_on);
2562 __set_bit(ATH_STAT_LEDBLINKING, sc->status);
2563 __clear_bit(ATH_STAT_LEDENDBLINK, sc->status);
2564 sc->led_off = off;
2565 mod_timer(&sc->led_tim, jiffies + on);
2566 }
2567
2568 static void
2569 ath5k_led_event(struct ath5k_softc *sc, int event)
2570 {
2571 if (likely(!test_bit(ATH_STAT_LEDSOFT, sc->status)))
2572 return;
2573 if (unlikely(test_bit(ATH_STAT_LEDBLINKING, sc->status)))
2574 return; /* don't interrupt active blink */
2575 switch (event) {
2576 case ATH_LED_TX:
2577 ath5k_led_blink(sc, sc->hwmap[sc->led_txrate].ledon,
2578 sc->hwmap[sc->led_txrate].ledoff);
2579 break;
2580 case ATH_LED_RX:
2581 ath5k_led_blink(sc, sc->hwmap[sc->led_rxrate].ledon,
2582 sc->hwmap[sc->led_rxrate].ledoff);
2583 break;
2584 }
2585 }
2586
2587
2588
2589
2590 /********************\
2591 * Mac80211 functions *
2592 \********************/
2593
2594 static int
2595 ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb,
2596 struct ieee80211_tx_control *ctl)
2597 {
2598 struct ath5k_softc *sc = hw->priv;
2599 struct ath5k_buf *bf;
2600 unsigned long flags;
2601 int hdrlen;
2602 int pad;
2603
2604 ath5k_debug_dump_skb(sc, skb, "TX ", 1);
2605
2606 if (sc->opmode == IEEE80211_IF_TYPE_MNTR)
2607 ATH5K_DBG(sc, ATH5K_DEBUG_XMIT, "tx in monitor (scan?)\n");
2608
2609 /*
2610 * the hardware expects the header padded to 4 byte boundaries
2611 * if this is not the case we add the padding after the header
2612 */
2613 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2614 if (hdrlen & 3) {
2615 pad = hdrlen % 4;
2616 if (skb_headroom(skb) < pad) {
2617 ATH5K_ERR(sc, "tx hdrlen not %%4: %d not enough"
2618 " headroom to pad %d\n", hdrlen, pad);
2619 return -1;
2620 }
2621 skb_push(skb, pad);
2622 memmove(skb->data, skb->data+pad, hdrlen);
2623 }
2624
2625 sc->led_txrate = ctl->tx_rate->hw_value;
2626
2627 spin_lock_irqsave(&sc->txbuflock, flags);
2628 if (list_empty(&sc->txbuf)) {
2629 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n");
2630 spin_unlock_irqrestore(&sc->txbuflock, flags);
2631 ieee80211_stop_queue(hw, ctl->queue);
2632 return -1;
2633 }
2634 bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list);
2635 list_del(&bf->list);
2636 sc->txbuf_len--;
2637 if (list_empty(&sc->txbuf))
2638 ieee80211_stop_queues(hw);
2639 spin_unlock_irqrestore(&sc->txbuflock, flags);
2640
2641 bf->skb = skb;
2642
2643 if (ath5k_txbuf_setup(sc, bf, ctl)) {
2644 bf->skb = NULL;
2645 spin_lock_irqsave(&sc->txbuflock, flags);
2646 list_add_tail(&bf->list, &sc->txbuf);
2647 sc->txbuf_len++;
2648 spin_unlock_irqrestore(&sc->txbuflock, flags);
2649 dev_kfree_skb_any(skb);
2650 return 0;
2651 }
2652
2653 return 0;
2654 }
2655
2656 static int
2657 ath5k_reset(struct ieee80211_hw *hw)
2658 {
2659 struct ath5k_softc *sc = hw->priv;
2660 struct ath5k_hw *ah = sc->ah;
2661 int ret;
2662
2663 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
2664
2665 ath5k_hw_set_intr(ah, 0);
2666 ath5k_txq_cleanup(sc);
2667 ath5k_rx_stop(sc);
2668
2669 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, true);
2670 if (unlikely(ret)) {
2671 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
2672 goto err;
2673 }
2674 ath5k_hw_set_txpower_limit(sc->ah, 0);
2675
2676 ret = ath5k_rx_start(sc);
2677 if (unlikely(ret)) {
2678 ATH5K_ERR(sc, "can't start recv logic\n");
2679 goto err;
2680 }
2681 /*
2682 * We may be doing a reset in response to an ioctl
2683 * that changes the channel so update any state that
2684 * might change as a result.
2685 *
2686 * XXX needed?
2687 */
2688 /* ath5k_chan_change(sc, c); */
2689 ath5k_beacon_config(sc);
2690 /* intrs are started by ath5k_beacon_config */
2691
2692 ieee80211_wake_queues(hw);
2693
2694 return 0;
2695 err:
2696 return ret;
2697 }
2698
2699 static int ath5k_start(struct ieee80211_hw *hw)
2700 {
2701 return ath5k_init(hw->priv);
2702 }
2703
2704 static void ath5k_stop(struct ieee80211_hw *hw)
2705 {
2706 ath5k_stop_hw(hw->priv);
2707 }
2708
2709 static int ath5k_add_interface(struct ieee80211_hw *hw,
2710 struct ieee80211_if_init_conf *conf)
2711 {
2712 struct ath5k_softc *sc = hw->priv;
2713 int ret;
2714
2715 mutex_lock(&sc->lock);
2716 if (sc->vif) {
2717 ret = 0;
2718 goto end;
2719 }
2720
2721 sc->vif = conf->vif;
2722
2723 switch (conf->type) {
2724 case IEEE80211_IF_TYPE_STA:
2725 case IEEE80211_IF_TYPE_IBSS:
2726 case IEEE80211_IF_TYPE_MNTR:
2727 sc->opmode = conf->type;
2728 break;
2729 default:
2730 ret = -EOPNOTSUPP;
2731 goto end;
2732 }
2733 ret = 0;
2734 end:
2735 mutex_unlock(&sc->lock);
2736 return ret;
2737 }
2738
2739 static void
2740 ath5k_remove_interface(struct ieee80211_hw *hw,
2741 struct ieee80211_if_init_conf *conf)
2742 {
2743 struct ath5k_softc *sc = hw->priv;
2744
2745 mutex_lock(&sc->lock);
2746 if (sc->vif != conf->vif)
2747 goto end;
2748
2749 sc->vif = NULL;
2750 end:
2751 mutex_unlock(&sc->lock);
2752 }
2753
2754 /*
2755 * TODO: Phy disable/diversity etc
2756 */
2757 static int
2758 ath5k_config(struct ieee80211_hw *hw,
2759 struct ieee80211_conf *conf)
2760 {
2761 struct ath5k_softc *sc = hw->priv;
2762
2763 sc->bintval = conf->beacon_int;
2764 sc->power_level = conf->power_level;
2765
2766 return ath5k_chan_set(sc, conf->channel);
2767 }
2768
2769 static int
2770 ath5k_config_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2771 struct ieee80211_if_conf *conf)
2772 {
2773 struct ath5k_softc *sc = hw->priv;
2774 struct ath5k_hw *ah = sc->ah;
2775 int ret;
2776
2777 /* Set to a reasonable value. Note that this will
2778 * be set to mac80211's value at ath5k_config(). */
2779 sc->bintval = 1000;
2780 mutex_lock(&sc->lock);
2781 if (sc->vif != vif) {
2782 ret = -EIO;
2783 goto unlock;
2784 }
2785 if (conf->bssid) {
2786 /* Cache for later use during resets */
2787 memcpy(ah->ah_bssid, conf->bssid, ETH_ALEN);
2788 /* XXX: assoc id is set to 0 for now, mac80211 doesn't have
2789 * a clean way of letting us retrieve this yet. */
2790 ath5k_hw_set_associd(ah, ah->ah_bssid, 0);
2791 }
2792 mutex_unlock(&sc->lock);
2793
2794 return ath5k_reset(hw);
2795 unlock:
2796 mutex_unlock(&sc->lock);
2797 return ret;
2798 }
2799
2800 #define SUPPORTED_FIF_FLAGS \
2801 FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \
2802 FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
2803 FIF_BCN_PRBRESP_PROMISC
2804 /*
2805 * o always accept unicast, broadcast, and multicast traffic
2806 * o multicast traffic for all BSSIDs will be enabled if mac80211
2807 * says it should be
2808 * o maintain current state of phy ofdm or phy cck error reception.
2809 * If the hardware detects any of these type of errors then
2810 * ath5k_hw_get_rx_filter() will pass to us the respective
2811 * hardware filters to be able to receive these type of frames.
2812 * o probe request frames are accepted only when operating in
2813 * hostap, adhoc, or monitor modes
2814 * o enable promiscuous mode according to the interface state
2815 * o accept beacons:
2816 * - when operating in adhoc mode so the 802.11 layer creates
2817 * node table entries for peers,
2818 * - when operating in station mode for collecting rssi data when
2819 * the station is otherwise quiet, or
2820 * - when scanning
2821 */
2822 static void ath5k_configure_filter(struct ieee80211_hw *hw,
2823 unsigned int changed_flags,
2824 unsigned int *new_flags,
2825 int mc_count, struct dev_mc_list *mclist)
2826 {
2827 struct ath5k_softc *sc = hw->priv;
2828 struct ath5k_hw *ah = sc->ah;
2829 u32 mfilt[2], val, rfilt;
2830 u8 pos;
2831 int i;
2832
2833 mfilt[0] = 0;
2834 mfilt[1] = 0;
2835
2836 /* Only deal with supported flags */
2837 changed_flags &= SUPPORTED_FIF_FLAGS;
2838 *new_flags &= SUPPORTED_FIF_FLAGS;
2839
2840 /* If HW detects any phy or radar errors, leave those filters on.
2841 * Also, always enable Unicast, Broadcasts and Multicast
2842 * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
2843 rfilt = (ath5k_hw_get_rx_filter(ah) & (AR5K_RX_FILTER_PHYERR)) |
2844 (AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST |
2845 AR5K_RX_FILTER_MCAST);
2846
2847 if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) {
2848 if (*new_flags & FIF_PROMISC_IN_BSS) {
2849 rfilt |= AR5K_RX_FILTER_PROM;
2850 __set_bit(ATH_STAT_PROMISC, sc->status);
2851 }
2852 else
2853 __clear_bit(ATH_STAT_PROMISC, sc->status);
2854 }
2855
2856 /* Note, AR5K_RX_FILTER_MCAST is already enabled */
2857 if (*new_flags & FIF_ALLMULTI) {
2858 mfilt[0] = ~0;
2859 mfilt[1] = ~0;
2860 } else {
2861 for (i = 0; i < mc_count; i++) {
2862 if (!mclist)
2863 break;
2864 /* calculate XOR of eight 6-bit values */
2865 val = LE_READ_4(mclist->dmi_addr + 0);
2866 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2867 val = LE_READ_4(mclist->dmi_addr + 3);
2868 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2869 pos &= 0x3f;
2870 mfilt[pos / 32] |= (1 << (pos % 32));
2871 /* XXX: we might be able to just do this instead,
2872 * but not sure, needs testing, if we do use this we'd
2873 * neet to inform below to not reset the mcast */
2874 /* ath5k_hw_set_mcast_filterindex(ah,
2875 * mclist->dmi_addr[5]); */
2876 mclist = mclist->next;
2877 }
2878 }
2879
2880 /* This is the best we can do */
2881 if (*new_flags & (FIF_FCSFAIL | FIF_PLCPFAIL))
2882 rfilt |= AR5K_RX_FILTER_PHYERR;
2883
2884 /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
2885 * and probes for any BSSID, this needs testing */
2886 if (*new_flags & FIF_BCN_PRBRESP_PROMISC)
2887 rfilt |= AR5K_RX_FILTER_BEACON | AR5K_RX_FILTER_PROBEREQ;
2888
2889 /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
2890 * set we should only pass on control frames for this
2891 * station. This needs testing. I believe right now this
2892 * enables *all* control frames, which is OK.. but
2893 * but we should see if we can improve on granularity */
2894 if (*new_flags & FIF_CONTROL)
2895 rfilt |= AR5K_RX_FILTER_CONTROL;
2896
2897 /* Additional settings per mode -- this is per ath5k */
2898
2899 /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
2900
2901 if (sc->opmode == IEEE80211_IF_TYPE_MNTR)
2902 rfilt |= AR5K_RX_FILTER_CONTROL | AR5K_RX_FILTER_BEACON |
2903 AR5K_RX_FILTER_PROBEREQ | AR5K_RX_FILTER_PROM;
2904 if (sc->opmode != IEEE80211_IF_TYPE_STA)
2905 rfilt |= AR5K_RX_FILTER_PROBEREQ;
2906 if (sc->opmode != IEEE80211_IF_TYPE_AP &&
2907 test_bit(ATH_STAT_PROMISC, sc->status))
2908 rfilt |= AR5K_RX_FILTER_PROM;
2909 if (sc->opmode == IEEE80211_IF_TYPE_STA ||
2910 sc->opmode == IEEE80211_IF_TYPE_IBSS) {
2911 rfilt |= AR5K_RX_FILTER_BEACON;
2912 }
2913
2914 /* Set filters */
2915 ath5k_hw_set_rx_filter(ah,rfilt);
2916
2917 /* Set multicast bits */
2918 ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]);
2919 /* Set the cached hw filter flags, this will alter actually
2920 * be set in HW */
2921 sc->filter_flags = rfilt;
2922 }
2923
2924 static int
2925 ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
2926 const u8 *local_addr, const u8 *addr,
2927 struct ieee80211_key_conf *key)
2928 {
2929 struct ath5k_softc *sc = hw->priv;
2930 int ret = 0;
2931
2932 switch(key->alg) {
2933 case ALG_WEP:
2934 /* XXX: fix hardware encryption, its not working. For now
2935 * allow software encryption */
2936 /* break; */
2937 case ALG_TKIP:
2938 case ALG_CCMP:
2939 return -EOPNOTSUPP;
2940 default:
2941 WARN_ON(1);
2942 return -EINVAL;
2943 }
2944
2945 mutex_lock(&sc->lock);
2946
2947 switch (cmd) {
2948 case SET_KEY:
2949 ret = ath5k_hw_set_key(sc->ah, key->keyidx, key, addr);
2950 if (ret) {
2951 ATH5K_ERR(sc, "can't set the key\n");
2952 goto unlock;
2953 }
2954 __set_bit(key->keyidx, sc->keymap);
2955 key->hw_key_idx = key->keyidx;
2956 break;
2957 case DISABLE_KEY:
2958 ath5k_hw_reset_key(sc->ah, key->keyidx);
2959 __clear_bit(key->keyidx, sc->keymap);
2960 break;
2961 default:
2962 ret = -EINVAL;
2963 goto unlock;
2964 }
2965
2966 unlock:
2967 mutex_unlock(&sc->lock);
2968 return ret;
2969 }
2970
2971 static int
2972 ath5k_get_stats(struct ieee80211_hw *hw,
2973 struct ieee80211_low_level_stats *stats)
2974 {
2975 struct ath5k_softc *sc = hw->priv;
2976
2977 memcpy(stats, &sc->ll_stats, sizeof(sc->ll_stats));
2978
2979 return 0;
2980 }
2981
2982 static int
2983 ath5k_get_tx_stats(struct ieee80211_hw *hw,
2984 struct ieee80211_tx_queue_stats *stats)
2985 {
2986 struct ath5k_softc *sc = hw->priv;
2987
2988 memcpy(stats, &sc->tx_stats, sizeof(sc->tx_stats));
2989
2990 return 0;
2991 }
2992
2993 static u64
2994 ath5k_get_tsf(struct ieee80211_hw *hw)
2995 {
2996 struct ath5k_softc *sc = hw->priv;
2997
2998 return ath5k_hw_get_tsf64(sc->ah);
2999 }
3000
3001 static void
3002 ath5k_reset_tsf(struct ieee80211_hw *hw)
3003 {
3004 struct ath5k_softc *sc = hw->priv;
3005
3006 /*
3007 * in IBSS mode we need to update the beacon timers too.
3008 * this will also reset the TSF if we call it with 0
3009 */
3010 if (sc->opmode == IEEE80211_IF_TYPE_IBSS)
3011 ath5k_beacon_update_timers(sc, 0);
3012 else
3013 ath5k_hw_reset_tsf(sc->ah);
3014 }
3015
3016 static int
3017 ath5k_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
3018 struct ieee80211_tx_control *ctl)
3019 {
3020 struct ath5k_softc *sc = hw->priv;
3021 int ret;
3022
3023 ath5k_debug_dump_skb(sc, skb, "BC ", 1);
3024
3025 mutex_lock(&sc->lock);
3026
3027 if (sc->opmode != IEEE80211_IF_TYPE_IBSS) {
3028 ret = -EIO;
3029 goto end;
3030 }
3031
3032 ath5k_txbuf_free(sc, sc->bbuf);
3033 sc->bbuf->skb = skb;
3034 ret = ath5k_beacon_setup(sc, sc->bbuf, ctl);
3035 if (ret)
3036 sc->bbuf->skb = NULL;
3037 else
3038 ath5k_beacon_config(sc);
3039
3040 end:
3041 mutex_unlock(&sc->lock);
3042 return ret;
3043 }
3044
Linux kernel - Deliverables
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