2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
43 #include <linux/version.h>
44 #include <linux/module.h>
45 #include <linux/delay.h>
47 #include <linux/netdevice.h>
48 #include <linux/cache.h>
49 #include <linux/pci.h>
50 #include <linux/ethtool.h>
51 #include <linux/uaccess.h>
53 #include <net/ieee80211_radiotap.h>
55 #include <asm/unaligned.h>
66 static int ath5k_calinterval
= 10; /* Calibrate PHY every 10 secs (TODO: Fixme) */
74 MODULE_AUTHOR("Jiri Slaby");
75 MODULE_AUTHOR("Nick Kossifidis");
76 MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
77 MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
78 MODULE_LICENSE("Dual BSD/GPL");
79 MODULE_VERSION("0.5.0 (EXPERIMENTAL)");
83 static struct pci_device_id ath5k_pci_id_table
[] __devinitdata
= {
84 { PCI_VDEVICE(ATHEROS
, 0x0207), .driver_data
= AR5K_AR5210
}, /* 5210 early */
85 { PCI_VDEVICE(ATHEROS
, 0x0007), .driver_data
= AR5K_AR5210
}, /* 5210 */
86 { PCI_VDEVICE(ATHEROS
, 0x0011), .driver_data
= AR5K_AR5211
}, /* 5311 - this is on AHB bus !*/
87 { PCI_VDEVICE(ATHEROS
, 0x0012), .driver_data
= AR5K_AR5211
}, /* 5211 */
88 { PCI_VDEVICE(ATHEROS
, 0x0013), .driver_data
= AR5K_AR5212
}, /* 5212 */
89 { PCI_VDEVICE(3COM_2
, 0x0013), .driver_data
= AR5K_AR5212
}, /* 3com 5212 */
90 { PCI_VDEVICE(3COM
, 0x0013), .driver_data
= AR5K_AR5212
}, /* 3com 3CRDAG675 5212 */
91 { PCI_VDEVICE(ATHEROS
, 0x1014), .driver_data
= AR5K_AR5212
}, /* IBM minipci 5212 */
92 { PCI_VDEVICE(ATHEROS
, 0x0014), .driver_data
= AR5K_AR5212
}, /* 5212 combatible */
93 { PCI_VDEVICE(ATHEROS
, 0x0015), .driver_data
= AR5K_AR5212
}, /* 5212 combatible */
94 { PCI_VDEVICE(ATHEROS
, 0x0016), .driver_data
= AR5K_AR5212
}, /* 5212 combatible */
95 { PCI_VDEVICE(ATHEROS
, 0x0017), .driver_data
= AR5K_AR5212
}, /* 5212 combatible */
96 { PCI_VDEVICE(ATHEROS
, 0x0018), .driver_data
= AR5K_AR5212
}, /* 5212 combatible */
97 { PCI_VDEVICE(ATHEROS
, 0x0019), .driver_data
= AR5K_AR5212
}, /* 5212 combatible */
98 { PCI_VDEVICE(ATHEROS
, 0x001a), .driver_data
= AR5K_AR5212
}, /* 2413 Griffin-lite */
99 { PCI_VDEVICE(ATHEROS
, 0x001b), .driver_data
= AR5K_AR5212
}, /* 5413 Eagle */
100 { PCI_VDEVICE(ATHEROS
, 0x001c), .driver_data
= AR5K_AR5212
}, /* 5424 Condor (PCI-E)*/
101 { PCI_VDEVICE(ATHEROS
, 0x0023), .driver_data
= AR5K_AR5212
}, /* 5416 */
102 { PCI_VDEVICE(ATHEROS
, 0x0024), .driver_data
= AR5K_AR5212
}, /* 5418 */
105 MODULE_DEVICE_TABLE(pci
, ath5k_pci_id_table
);
108 static struct ath5k_srev_name srev_names
[] = {
109 { "5210", AR5K_VERSION_VER
, AR5K_SREV_VER_AR5210
},
110 { "5311", AR5K_VERSION_VER
, AR5K_SREV_VER_AR5311
},
111 { "5311A", AR5K_VERSION_VER
, AR5K_SREV_VER_AR5311A
},
112 { "5311B", AR5K_VERSION_VER
, AR5K_SREV_VER_AR5311B
},
113 { "5211", AR5K_VERSION_VER
, AR5K_SREV_VER_AR5211
},
114 { "5212", AR5K_VERSION_VER
, AR5K_SREV_VER_AR5212
},
115 { "5213", AR5K_VERSION_VER
, AR5K_SREV_VER_AR5213
},
116 { "5213A", AR5K_VERSION_VER
, AR5K_SREV_VER_AR5213A
},
117 { "2413", AR5K_VERSION_VER
, AR5K_SREV_VER_AR2413
},
118 { "2414", AR5K_VERSION_VER
, AR5K_SREV_VER_AR2414
},
119 { "2424", AR5K_VERSION_VER
, AR5K_SREV_VER_AR2424
},
120 { "5424", AR5K_VERSION_VER
, AR5K_SREV_VER_AR5424
},
121 { "5413", AR5K_VERSION_VER
, AR5K_SREV_VER_AR5413
},
122 { "5414", AR5K_VERSION_VER
, AR5K_SREV_VER_AR5414
},
123 { "5416", AR5K_VERSION_VER
, AR5K_SREV_VER_AR5416
},
124 { "5418", AR5K_VERSION_VER
, AR5K_SREV_VER_AR5418
},
125 { "2425", AR5K_VERSION_VER
, AR5K_SREV_VER_AR2425
},
126 { "xxxxx", AR5K_VERSION_VER
, AR5K_SREV_UNKNOWN
},
127 { "5110", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5110
},
128 { "5111", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5111
},
129 { "2111", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2111
},
130 { "5112", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5112
},
131 { "5112A", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5112A
},
132 { "2112", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2112
},
133 { "2112A", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2112A
},
134 { "SChip", AR5K_VERSION_RAD
, AR5K_SREV_RAD_SC0
},
135 { "SChip", AR5K_VERSION_RAD
, AR5K_SREV_RAD_SC1
},
136 { "SChip", AR5K_VERSION_RAD
, AR5K_SREV_RAD_SC2
},
137 { "5133", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5133
},
138 { "xxxxx", AR5K_VERSION_RAD
, AR5K_SREV_UNKNOWN
},
142 * Prototypes - PCI stack related functions
144 static int __devinit
ath5k_pci_probe(struct pci_dev
*pdev
,
145 const struct pci_device_id
*id
);
146 static void __devexit
ath5k_pci_remove(struct pci_dev
*pdev
);
148 static int ath5k_pci_suspend(struct pci_dev
*pdev
,
150 static int ath5k_pci_resume(struct pci_dev
*pdev
);
152 #define ath5k_pci_suspend NULL
153 #define ath5k_pci_resume NULL
154 #endif /* CONFIG_PM */
156 static struct pci_driver ath5k_pci_driver
= {
158 .id_table
= ath5k_pci_id_table
,
159 .probe
= ath5k_pci_probe
,
160 .remove
= __devexit_p(ath5k_pci_remove
),
161 .suspend
= ath5k_pci_suspend
,
162 .resume
= ath5k_pci_resume
,
168 * Prototypes - MAC 802.11 stack related functions
170 static int ath5k_tx(struct ieee80211_hw
*hw
, struct sk_buff
*skb
);
171 static int ath5k_reset(struct ieee80211_hw
*hw
);
172 static int ath5k_start(struct ieee80211_hw
*hw
);
173 static void ath5k_stop(struct ieee80211_hw
*hw
);
174 static int ath5k_add_interface(struct ieee80211_hw
*hw
,
175 struct ieee80211_if_init_conf
*conf
);
176 static void ath5k_remove_interface(struct ieee80211_hw
*hw
,
177 struct ieee80211_if_init_conf
*conf
);
178 static int ath5k_config(struct ieee80211_hw
*hw
,
179 struct ieee80211_conf
*conf
);
180 static int ath5k_config_interface(struct ieee80211_hw
*hw
,
181 struct ieee80211_vif
*vif
,
182 struct ieee80211_if_conf
*conf
);
183 static void ath5k_configure_filter(struct ieee80211_hw
*hw
,
184 unsigned int changed_flags
,
185 unsigned int *new_flags
,
186 int mc_count
, struct dev_mc_list
*mclist
);
187 static int ath5k_set_key(struct ieee80211_hw
*hw
,
188 enum set_key_cmd cmd
,
189 const u8
*local_addr
, const u8
*addr
,
190 struct ieee80211_key_conf
*key
);
191 static int ath5k_get_stats(struct ieee80211_hw
*hw
,
192 struct ieee80211_low_level_stats
*stats
);
193 static int ath5k_get_tx_stats(struct ieee80211_hw
*hw
,
194 struct ieee80211_tx_queue_stats
*stats
);
195 static u64
ath5k_get_tsf(struct ieee80211_hw
*hw
);
196 static void ath5k_reset_tsf(struct ieee80211_hw
*hw
);
197 static int ath5k_beacon_update(struct ieee80211_hw
*hw
,
198 struct sk_buff
*skb
);
200 static struct ieee80211_ops ath5k_hw_ops
= {
202 .start
= ath5k_start
,
204 .add_interface
= ath5k_add_interface
,
205 .remove_interface
= ath5k_remove_interface
,
206 .config
= ath5k_config
,
207 .config_interface
= ath5k_config_interface
,
208 .configure_filter
= ath5k_configure_filter
,
209 .set_key
= ath5k_set_key
,
210 .get_stats
= ath5k_get_stats
,
212 .get_tx_stats
= ath5k_get_tx_stats
,
213 .get_tsf
= ath5k_get_tsf
,
214 .reset_tsf
= ath5k_reset_tsf
,
215 .beacon_update
= ath5k_beacon_update
,
219 * Prototypes - Internal functions
222 static int ath5k_attach(struct pci_dev
*pdev
,
223 struct ieee80211_hw
*hw
);
224 static void ath5k_detach(struct pci_dev
*pdev
,
225 struct ieee80211_hw
*hw
);
226 /* Channel/mode setup */
227 static inline short ath5k_ieee2mhz(short chan
);
228 static unsigned int ath5k_copy_rates(struct ieee80211_rate
*rates
,
229 const struct ath5k_rate_table
*rt
,
231 static unsigned int ath5k_copy_channels(struct ath5k_hw
*ah
,
232 struct ieee80211_channel
*channels
,
235 static int ath5k_getchannels(struct ieee80211_hw
*hw
);
236 static int ath5k_chan_set(struct ath5k_softc
*sc
,
237 struct ieee80211_channel
*chan
);
238 static void ath5k_setcurmode(struct ath5k_softc
*sc
,
240 static void ath5k_mode_setup(struct ath5k_softc
*sc
);
241 static void ath5k_set_total_hw_rates(struct ath5k_softc
*sc
);
243 /* Descriptor setup */
244 static int ath5k_desc_alloc(struct ath5k_softc
*sc
,
245 struct pci_dev
*pdev
);
246 static void ath5k_desc_free(struct ath5k_softc
*sc
,
247 struct pci_dev
*pdev
);
249 static int ath5k_rxbuf_setup(struct ath5k_softc
*sc
,
250 struct ath5k_buf
*bf
);
251 static int ath5k_txbuf_setup(struct ath5k_softc
*sc
,
252 struct ath5k_buf
*bf
);
253 static inline void ath5k_txbuf_free(struct ath5k_softc
*sc
,
254 struct ath5k_buf
*bf
)
259 pci_unmap_single(sc
->pdev
, bf
->skbaddr
, bf
->skb
->len
,
261 dev_kfree_skb(bf
->skb
);
266 static struct ath5k_txq
*ath5k_txq_setup(struct ath5k_softc
*sc
,
267 int qtype
, int subtype
);
268 static int ath5k_beaconq_setup(struct ath5k_hw
*ah
);
269 static int ath5k_beaconq_config(struct ath5k_softc
*sc
);
270 static void ath5k_txq_drainq(struct ath5k_softc
*sc
,
271 struct ath5k_txq
*txq
);
272 static void ath5k_txq_cleanup(struct ath5k_softc
*sc
);
273 static void ath5k_txq_release(struct ath5k_softc
*sc
);
275 static int ath5k_rx_start(struct ath5k_softc
*sc
);
276 static void ath5k_rx_stop(struct ath5k_softc
*sc
);
277 static unsigned int ath5k_rx_decrypted(struct ath5k_softc
*sc
,
278 struct ath5k_desc
*ds
,
280 struct ath5k_rx_status
*rs
);
281 static void ath5k_tasklet_rx(unsigned long data
);
283 static void ath5k_tx_processq(struct ath5k_softc
*sc
,
284 struct ath5k_txq
*txq
);
285 static void ath5k_tasklet_tx(unsigned long data
);
286 /* Beacon handling */
287 static int ath5k_beacon_setup(struct ath5k_softc
*sc
,
288 struct ath5k_buf
*bf
);
289 static void ath5k_beacon_send(struct ath5k_softc
*sc
);
290 static void ath5k_beacon_config(struct ath5k_softc
*sc
);
291 static void ath5k_beacon_update_timers(struct ath5k_softc
*sc
, u64 bc_tsf
);
293 static inline u64
ath5k_extend_tsf(struct ath5k_hw
*ah
, u32 rstamp
)
295 u64 tsf
= ath5k_hw_get_tsf64(ah
);
297 if ((tsf
& 0x7fff) < rstamp
)
300 return (tsf
& ~0x7fff) | rstamp
;
303 /* Interrupt handling */
304 static int ath5k_init(struct ath5k_softc
*sc
);
305 static int ath5k_stop_locked(struct ath5k_softc
*sc
);
306 static int ath5k_stop_hw(struct ath5k_softc
*sc
);
307 static irqreturn_t
ath5k_intr(int irq
, void *dev_id
);
308 static void ath5k_tasklet_reset(unsigned long data
);
310 static void ath5k_calibrate(unsigned long data
);
312 static void ath5k_led_off(unsigned long data
);
313 static void ath5k_led_blink(struct ath5k_softc
*sc
,
316 static void ath5k_led_event(struct ath5k_softc
*sc
,
321 * Module init/exit functions
330 ret
= pci_register_driver(&ath5k_pci_driver
);
332 printk(KERN_ERR
"ath5k_pci: can't register pci driver\n");
342 pci_unregister_driver(&ath5k_pci_driver
);
344 ath5k_debug_finish();
347 module_init(init_ath5k_pci
);
348 module_exit(exit_ath5k_pci
);
351 /********************\
352 * PCI Initialization *
353 \********************/
356 ath5k_chip_name(enum ath5k_srev_type type
, u_int16_t val
)
358 const char *name
= "xxxxx";
361 for (i
= 0; i
< ARRAY_SIZE(srev_names
); i
++) {
362 if (srev_names
[i
].sr_type
!= type
)
364 if ((val
& 0xff) < srev_names
[i
+ 1].sr_val
) {
365 name
= srev_names
[i
].sr_name
;
374 ath5k_pci_probe(struct pci_dev
*pdev
,
375 const struct pci_device_id
*id
)
378 struct ath5k_softc
*sc
;
379 struct ieee80211_hw
*hw
;
383 ret
= pci_enable_device(pdev
);
385 dev_err(&pdev
->dev
, "can't enable device\n");
389 /* XXX 32-bit addressing only */
390 ret
= pci_set_dma_mask(pdev
, DMA_32BIT_MASK
);
392 dev_err(&pdev
->dev
, "32-bit DMA not available\n");
397 * Cache line size is used to size and align various
398 * structures used to communicate with the hardware.
400 pci_read_config_byte(pdev
, PCI_CACHE_LINE_SIZE
, &csz
);
403 * Linux 2.4.18 (at least) writes the cache line size
404 * register as a 16-bit wide register which is wrong.
405 * We must have this setup properly for rx buffer
406 * DMA to work so force a reasonable value here if it
409 csz
= L1_CACHE_BYTES
/ sizeof(u32
);
410 pci_write_config_byte(pdev
, PCI_CACHE_LINE_SIZE
, csz
);
413 * The default setting of latency timer yields poor results,
414 * set it to the value used by other systems. It may be worth
415 * tweaking this setting more.
417 pci_write_config_byte(pdev
, PCI_LATENCY_TIMER
, 0xa8);
419 /* Enable bus mastering */
420 pci_set_master(pdev
);
423 * Disable the RETRY_TIMEOUT register (0x41) to keep
424 * PCI Tx retries from interfering with C3 CPU state.
426 pci_write_config_byte(pdev
, 0x41, 0);
428 ret
= pci_request_region(pdev
, 0, "ath5k");
430 dev_err(&pdev
->dev
, "cannot reserve PCI memory region\n");
434 mem
= pci_iomap(pdev
, 0, 0);
436 dev_err(&pdev
->dev
, "cannot remap PCI memory region\n") ;
442 * Allocate hw (mac80211 main struct)
443 * and hw->priv (driver private data)
445 hw
= ieee80211_alloc_hw(sizeof(*sc
), &ath5k_hw_ops
);
447 dev_err(&pdev
->dev
, "cannot allocate ieee80211_hw\n");
452 dev_info(&pdev
->dev
, "registered as '%s'\n", wiphy_name(hw
->wiphy
));
454 /* Initialize driver private data */
455 SET_IEEE80211_DEV(hw
, &pdev
->dev
);
456 hw
->flags
= IEEE80211_HW_RX_INCLUDES_FCS
|
457 IEEE80211_HW_SIGNAL_DBM
|
458 IEEE80211_HW_NOISE_DBM
;
459 hw
->extra_tx_headroom
= 2;
460 hw
->channel_change_time
= 5000;
465 ath5k_debug_init_device(sc
);
468 * Mark the device as detached to avoid processing
469 * interrupts until setup is complete.
471 __set_bit(ATH_STAT_INVALID
, sc
->status
);
473 sc
->iobase
= mem
; /* So we can unmap it on detach */
474 sc
->cachelsz
= csz
* sizeof(u32
); /* convert to bytes */
475 sc
->opmode
= IEEE80211_IF_TYPE_STA
;
476 mutex_init(&sc
->lock
);
477 spin_lock_init(&sc
->rxbuflock
);
478 spin_lock_init(&sc
->txbuflock
);
480 /* Set private data */
481 pci_set_drvdata(pdev
, hw
);
483 /* Enable msi for devices that support it */
484 pci_enable_msi(pdev
);
486 /* Setup interrupt handler */
487 ret
= request_irq(pdev
->irq
, ath5k_intr
, IRQF_SHARED
, "ath", sc
);
489 ATH5K_ERR(sc
, "request_irq failed\n");
493 /* Initialize device */
494 sc
->ah
= ath5k_hw_attach(sc
, id
->driver_data
);
495 if (IS_ERR(sc
->ah
)) {
496 ret
= PTR_ERR(sc
->ah
);
500 /* Finish private driver data initialization */
501 ret
= ath5k_attach(pdev
, hw
);
505 ATH5K_INFO(sc
, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
506 ath5k_chip_name(AR5K_VERSION_VER
,sc
->ah
->ah_mac_srev
),
508 sc
->ah
->ah_phy_revision
);
510 if (!sc
->ah
->ah_single_chip
) {
511 /* Single chip radio (!RF5111) */
512 if (sc
->ah
->ah_radio_5ghz_revision
&&
513 !sc
->ah
->ah_radio_2ghz_revision
) {
514 /* No 5GHz support -> report 2GHz radio */
515 if (!test_bit(AR5K_MODE_11A
,
516 sc
->ah
->ah_capabilities
.cap_mode
)) {
517 ATH5K_INFO(sc
, "RF%s 2GHz radio found (0x%x)\n",
518 ath5k_chip_name(AR5K_VERSION_RAD
,
519 sc
->ah
->ah_radio_5ghz_revision
),
520 sc
->ah
->ah_radio_5ghz_revision
);
521 /* No 2GHz support (5110 and some
522 * 5Ghz only cards) -> report 5Ghz radio */
523 } else if (!test_bit(AR5K_MODE_11B
,
524 sc
->ah
->ah_capabilities
.cap_mode
)) {
525 ATH5K_INFO(sc
, "RF%s 5GHz radio found (0x%x)\n",
526 ath5k_chip_name(AR5K_VERSION_RAD
,
527 sc
->ah
->ah_radio_5ghz_revision
),
528 sc
->ah
->ah_radio_5ghz_revision
);
529 /* Multiband radio */
531 ATH5K_INFO(sc
, "RF%s multiband radio found"
533 ath5k_chip_name(AR5K_VERSION_RAD
,
534 sc
->ah
->ah_radio_5ghz_revision
),
535 sc
->ah
->ah_radio_5ghz_revision
);
538 /* Multi chip radio (RF5111 - RF2111) ->
539 * report both 2GHz/5GHz radios */
540 else if (sc
->ah
->ah_radio_5ghz_revision
&&
541 sc
->ah
->ah_radio_2ghz_revision
){
542 ATH5K_INFO(sc
, "RF%s 5GHz radio found (0x%x)\n",
543 ath5k_chip_name(AR5K_VERSION_RAD
,
544 sc
->ah
->ah_radio_5ghz_revision
),
545 sc
->ah
->ah_radio_5ghz_revision
);
546 ATH5K_INFO(sc
, "RF%s 2GHz radio found (0x%x)\n",
547 ath5k_chip_name(AR5K_VERSION_RAD
,
548 sc
->ah
->ah_radio_2ghz_revision
),
549 sc
->ah
->ah_radio_2ghz_revision
);
554 /* ready to process interrupts */
555 __clear_bit(ATH_STAT_INVALID
, sc
->status
);
559 ath5k_hw_detach(sc
->ah
);
561 free_irq(pdev
->irq
, sc
);
563 pci_disable_msi(pdev
);
564 ieee80211_free_hw(hw
);
566 pci_iounmap(pdev
, mem
);
568 pci_release_region(pdev
, 0);
570 pci_disable_device(pdev
);
575 static void __devexit
576 ath5k_pci_remove(struct pci_dev
*pdev
)
578 struct ieee80211_hw
*hw
= pci_get_drvdata(pdev
);
579 struct ath5k_softc
*sc
= hw
->priv
;
581 ath5k_debug_finish_device(sc
);
582 ath5k_detach(pdev
, hw
);
583 ath5k_hw_detach(sc
->ah
);
584 free_irq(pdev
->irq
, sc
);
585 pci_disable_msi(pdev
);
586 pci_iounmap(pdev
, sc
->iobase
);
587 pci_release_region(pdev
, 0);
588 pci_disable_device(pdev
);
589 ieee80211_free_hw(hw
);
594 ath5k_pci_suspend(struct pci_dev
*pdev
, pm_message_t state
)
596 struct ieee80211_hw
*hw
= pci_get_drvdata(pdev
);
597 struct ath5k_softc
*sc
= hw
->priv
;
599 if (test_bit(ATH_STAT_LEDSOFT
, sc
->status
))
600 ath5k_hw_set_gpio(sc
->ah
, sc
->led_pin
, 1);
603 pci_save_state(pdev
);
604 pci_disable_device(pdev
);
605 pci_set_power_state(pdev
, PCI_D3hot
);
611 ath5k_pci_resume(struct pci_dev
*pdev
)
613 struct ieee80211_hw
*hw
= pci_get_drvdata(pdev
);
614 struct ath5k_softc
*sc
= hw
->priv
;
615 struct ath5k_hw
*ah
= sc
->ah
;
618 err
= pci_set_power_state(pdev
, PCI_D0
);
622 err
= pci_enable_device(pdev
);
626 pci_restore_state(pdev
);
628 * Suspend/Resume resets the PCI configuration space, so we have to
629 * re-disable the RETRY_TIMEOUT register (0x41) to keep
630 * PCI Tx retries from interfering with C3 CPU state
632 pci_write_config_byte(pdev
, 0x41, 0);
635 if (test_bit(ATH_STAT_LEDSOFT
, sc
->status
)) {
636 ath5k_hw_set_gpio_output(ah
, sc
->led_pin
);
637 ath5k_hw_set_gpio(ah
, sc
->led_pin
, 0);
641 * Reset the key cache since some parts do not
642 * reset the contents on initial power up or resume.
644 * FIXME: This may need to be revisited when mac80211 becomes
645 * aware of suspend/resume.
647 for (i
= 0; i
< AR5K_KEYTABLE_SIZE
; i
++)
648 ath5k_hw_reset_key(ah
, i
);
652 #endif /* CONFIG_PM */
656 /***********************\
657 * Driver Initialization *
658 \***********************/
661 ath5k_attach(struct pci_dev
*pdev
, struct ieee80211_hw
*hw
)
663 struct ath5k_softc
*sc
= hw
->priv
;
664 struct ath5k_hw
*ah
= sc
->ah
;
669 ATH5K_DBG(sc
, ATH5K_DEBUG_ANY
, "devid 0x%x\n", pdev
->device
);
672 * Check if the MAC has multi-rate retry support.
673 * We do this by trying to setup a fake extended
674 * descriptor. MAC's that don't have support will
675 * return false w/o doing anything. MAC's that do
676 * support it will return true w/o doing anything.
678 ret
= ah
->ah_setup_xtx_desc(ah
, NULL
, 0, 0, 0, 0, 0, 0);
682 __set_bit(ATH_STAT_MRRETRY
, sc
->status
);
685 * Reset the key cache since some parts do not
686 * reset the contents on initial power up.
688 for (i
= 0; i
< AR5K_KEYTABLE_SIZE
; i
++)
689 ath5k_hw_reset_key(ah
, i
);
692 * Collect the channel list. The 802.11 layer
693 * is resposible for filtering this list based
694 * on settings like the phy mode and regulatory
695 * domain restrictions.
697 ret
= ath5k_getchannels(hw
);
699 ATH5K_ERR(sc
, "can't get channels\n");
703 /* Set *_rates so we can map hw rate index */
704 ath5k_set_total_hw_rates(sc
);
706 /* NB: setup here so ath5k_rate_update is happy */
707 if (test_bit(AR5K_MODE_11A
, ah
->ah_modes
))
708 ath5k_setcurmode(sc
, AR5K_MODE_11A
);
710 ath5k_setcurmode(sc
, AR5K_MODE_11B
);
713 * Allocate tx+rx descriptors and populate the lists.
715 ret
= ath5k_desc_alloc(sc
, pdev
);
717 ATH5K_ERR(sc
, "can't allocate descriptors\n");
722 * Allocate hardware transmit queues: one queue for
723 * beacon frames and one data queue for each QoS
724 * priority. Note that hw functions handle reseting
725 * these queues at the needed time.
727 ret
= ath5k_beaconq_setup(ah
);
729 ATH5K_ERR(sc
, "can't setup a beacon xmit queue\n");
734 sc
->txq
= ath5k_txq_setup(sc
, AR5K_TX_QUEUE_DATA
, AR5K_WME_AC_BK
);
735 if (IS_ERR(sc
->txq
)) {
736 ATH5K_ERR(sc
, "can't setup xmit queue\n");
737 ret
= PTR_ERR(sc
->txq
);
741 tasklet_init(&sc
->rxtq
, ath5k_tasklet_rx
, (unsigned long)sc
);
742 tasklet_init(&sc
->txtq
, ath5k_tasklet_tx
, (unsigned long)sc
);
743 tasklet_init(&sc
->restq
, ath5k_tasklet_reset
, (unsigned long)sc
);
744 setup_timer(&sc
->calib_tim
, ath5k_calibrate
, (unsigned long)sc
);
745 setup_timer(&sc
->led_tim
, ath5k_led_off
, (unsigned long)sc
);
747 sc
->led_on
= 0; /* low true */
749 * Auto-enable soft led processing for IBM cards and for
750 * 5211 minipci cards.
752 if (pdev
->device
== PCI_DEVICE_ID_ATHEROS_AR5212_IBM
||
753 pdev
->device
== PCI_DEVICE_ID_ATHEROS_AR5211
) {
754 __set_bit(ATH_STAT_LEDSOFT
, sc
->status
);
757 /* Enable softled on PIN1 on HP Compaq nc6xx, nc4000 & nx5000 laptops */
758 if (pdev
->subsystem_vendor
== PCI_VENDOR_ID_COMPAQ
) {
759 __set_bit(ATH_STAT_LEDSOFT
, sc
->status
);
762 if (test_bit(ATH_STAT_LEDSOFT
, sc
->status
)) {
763 ath5k_hw_set_gpio_output(ah
, sc
->led_pin
);
764 ath5k_hw_set_gpio(ah
, sc
->led_pin
, !sc
->led_on
);
767 ath5k_hw_get_lladdr(ah
, mac
);
768 SET_IEEE80211_PERM_ADDR(hw
, mac
);
769 /* All MAC address bits matter for ACKs */
770 memset(sc
->bssidmask
, 0xff, ETH_ALEN
);
771 ath5k_hw_set_bssid_mask(sc
->ah
, sc
->bssidmask
);
773 ret
= ieee80211_register_hw(hw
);
775 ATH5K_ERR(sc
, "can't register ieee80211 hw\n");
781 ath5k_txq_release(sc
);
783 ath5k_hw_release_tx_queue(ah
, sc
->bhalq
);
785 ath5k_desc_free(sc
, pdev
);
791 ath5k_detach(struct pci_dev
*pdev
, struct ieee80211_hw
*hw
)
793 struct ath5k_softc
*sc
= hw
->priv
;
796 * NB: the order of these is important:
797 * o call the 802.11 layer before detaching ath5k_hw to
798 * insure callbacks into the driver to delete global
799 * key cache entries can be handled
800 * o reclaim the tx queue data structures after calling
801 * the 802.11 layer as we'll get called back to reclaim
802 * node state and potentially want to use them
803 * o to cleanup the tx queues the hal is called, so detach
805 * XXX: ??? detach ath5k_hw ???
806 * Other than that, it's straightforward...
808 ieee80211_unregister_hw(hw
);
809 ath5k_desc_free(sc
, pdev
);
810 ath5k_txq_release(sc
);
811 ath5k_hw_release_tx_queue(sc
->ah
, sc
->bhalq
);
814 * NB: can't reclaim these until after ieee80211_ifdetach
815 * returns because we'll get called back to reclaim node
816 * state and potentially want to use them.
823 /********************\
824 * Channel/mode setup *
825 \********************/
828 * Convert IEEE channel number to MHz frequency.
831 ath5k_ieee2mhz(short chan
)
833 if (chan
<= 14 || chan
>= 27)
834 return ieee80211chan2mhz(chan
);
836 return 2212 + chan
* 20;
840 ath5k_copy_rates(struct ieee80211_rate
*rates
,
841 const struct ath5k_rate_table
*rt
,
844 unsigned int i
, count
;
849 for (i
= 0, count
= 0; i
< rt
->rate_count
&& max
> 0; i
++) {
850 rates
[count
].bitrate
= rt
->rates
[i
].rate_kbps
/ 100;
851 rates
[count
].hw_value
= rt
->rates
[i
].rate_code
;
852 rates
[count
].flags
= rt
->rates
[i
].modulation
;
861 ath5k_copy_channels(struct ath5k_hw
*ah
,
862 struct ieee80211_channel
*channels
,
866 unsigned int i
, count
, size
, chfreq
, freq
, ch
;
868 if (!test_bit(mode
, ah
->ah_modes
))
873 case AR5K_MODE_11A_TURBO
:
874 /* 1..220, but 2GHz frequencies are filtered by check_channel */
876 chfreq
= CHANNEL_5GHZ
;
880 case AR5K_MODE_11G_TURBO
:
882 chfreq
= CHANNEL_2GHZ
;
885 ATH5K_WARN(ah
->ah_sc
, "bad mode, not copying channels\n");
889 for (i
= 0, count
= 0; i
< size
&& max
> 0; i
++) {
891 freq
= ath5k_ieee2mhz(ch
);
893 /* Check if channel is supported by the chipset */
894 if (!ath5k_channel_ok(ah
, freq
, chfreq
))
897 /* Write channel info and increment counter */
898 channels
[count
].center_freq
= freq
;
899 channels
[count
].band
= (chfreq
== CHANNEL_2GHZ
) ?
900 IEEE80211_BAND_2GHZ
: IEEE80211_BAND_5GHZ
;
904 channels
[count
].hw_value
= chfreq
| CHANNEL_OFDM
;
906 case AR5K_MODE_11A_TURBO
:
907 case AR5K_MODE_11G_TURBO
:
908 channels
[count
].hw_value
= chfreq
|
909 CHANNEL_OFDM
| CHANNEL_TURBO
;
912 channels
[count
].hw_value
= CHANNEL_B
;
923 ath5k_getchannels(struct ieee80211_hw
*hw
)
925 struct ath5k_softc
*sc
= hw
->priv
;
926 struct ath5k_hw
*ah
= sc
->ah
;
927 struct ieee80211_supported_band
*sbands
= sc
->sbands
;
928 const struct ath5k_rate_table
*hw_rates
;
929 unsigned int max_r
, max_c
, count_r
, count_c
;
930 int mode2g
= AR5K_MODE_11G
;
932 BUILD_BUG_ON(ARRAY_SIZE(sc
->sbands
) < IEEE80211_NUM_BANDS
);
934 max_r
= ARRAY_SIZE(sc
->rates
);
935 max_c
= ARRAY_SIZE(sc
->channels
);
936 count_r
= count_c
= 0;
939 if (!test_bit(AR5K_MODE_11G
, sc
->ah
->ah_capabilities
.cap_mode
)) {
940 mode2g
= AR5K_MODE_11B
;
941 if (!test_bit(AR5K_MODE_11B
,
942 sc
->ah
->ah_capabilities
.cap_mode
))
947 struct ieee80211_supported_band
*sband
=
948 &sbands
[IEEE80211_BAND_2GHZ
];
950 sband
->bitrates
= sc
->rates
;
951 sband
->channels
= sc
->channels
;
953 sband
->band
= IEEE80211_BAND_2GHZ
;
954 sband
->n_channels
= ath5k_copy_channels(ah
, sband
->channels
,
957 hw_rates
= ath5k_hw_get_rate_table(ah
, mode2g
);
958 sband
->n_bitrates
= ath5k_copy_rates(sband
->bitrates
,
961 count_c
= sband
->n_channels
;
962 count_r
= sband
->n_bitrates
;
964 hw
->wiphy
->bands
[IEEE80211_BAND_2GHZ
] = sband
;
973 if (test_bit(AR5K_MODE_11A
, sc
->ah
->ah_capabilities
.cap_mode
)) {
974 struct ieee80211_supported_band
*sband
=
975 &sbands
[IEEE80211_BAND_5GHZ
];
977 sband
->bitrates
= &sc
->rates
[count_r
];
978 sband
->channels
= &sc
->channels
[count_c
];
980 sband
->band
= IEEE80211_BAND_5GHZ
;
981 sband
->n_channels
= ath5k_copy_channels(ah
, sband
->channels
,
982 AR5K_MODE_11A
, max_c
);
984 hw_rates
= ath5k_hw_get_rate_table(ah
, AR5K_MODE_11A
);
985 sband
->n_bitrates
= ath5k_copy_rates(sband
->bitrates
,
988 hw
->wiphy
->bands
[IEEE80211_BAND_5GHZ
] = sband
;
991 ath5k_debug_dump_bands(sc
);
997 * Set/change channels. If the channel is really being changed,
998 * it's done by reseting the chip. To accomplish this we must
999 * first cleanup any pending DMA, then restart stuff after a la
1003 ath5k_chan_set(struct ath5k_softc
*sc
, struct ieee80211_channel
*chan
)
1005 struct ath5k_hw
*ah
= sc
->ah
;
1008 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "(%u MHz) -> (%u MHz)\n",
1009 sc
->curchan
->center_freq
, chan
->center_freq
);
1011 if (chan
->center_freq
!= sc
->curchan
->center_freq
||
1012 chan
->hw_value
!= sc
->curchan
->hw_value
) {
1015 sc
->curband
= &sc
->sbands
[chan
->band
];
1018 * To switch channels clear any pending DMA operations;
1019 * wait long enough for the RX fifo to drain, reset the
1020 * hardware at the new frequency, and then re-enable
1021 * the relevant bits of the h/w.
1023 ath5k_hw_set_intr(ah
, 0); /* disable interrupts */
1024 ath5k_txq_cleanup(sc
); /* clear pending tx frames */
1025 ath5k_rx_stop(sc
); /* turn off frame recv */
1026 ret
= ath5k_hw_reset(ah
, sc
->opmode
, sc
->curchan
, true);
1028 ATH5K_ERR(sc
, "%s: unable to reset channel "
1029 "(%u Mhz)\n", __func__
, chan
->center_freq
);
1033 ath5k_hw_set_txpower_limit(sc
->ah
, 0);
1036 * Re-enable rx framework.
1038 ret
= ath5k_rx_start(sc
);
1040 ATH5K_ERR(sc
, "%s: unable to restart recv logic\n",
1046 * Change channels and update the h/w rate map
1047 * if we're switching; e.g. 11a to 11b/g.
1051 /* ath5k_chan_change(sc, chan); */
1053 ath5k_beacon_config(sc
);
1055 * Re-enable interrupts.
1057 ath5k_hw_set_intr(ah
, sc
->imask
);
1064 * TODO: CLEAN THIS !!!
1067 ath5k_setcurmode(struct ath5k_softc
*sc
, unsigned int mode
)
1069 if (unlikely(test_bit(ATH_STAT_LEDSOFT
, sc
->status
))) {
1070 /* from Atheros NDIS driver, w/ permission */
1071 static const struct {
1072 u16 rate
; /* tx/rx 802.11 rate */
1073 u16 timeOn
; /* LED on time (ms) */
1074 u16 timeOff
; /* LED off time (ms) */
1091 const struct ath5k_rate_table
*rt
=
1092 ath5k_hw_get_rate_table(sc
->ah
, mode
);
1097 memset(sc
->hwmap
, 0, sizeof(sc
->hwmap
));
1098 for (i
= 0; i
< 32; i
++) {
1099 u8 ix
= rt
->rate_code_to_index
[i
];
1101 sc
->hwmap
[i
].ledon
= msecs_to_jiffies(500);
1102 sc
->hwmap
[i
].ledoff
= msecs_to_jiffies(130);
1105 sc
->hwmap
[i
].txflags
= IEEE80211_RADIOTAP_F_DATAPAD
;
1106 /* receive frames include FCS */
1107 sc
->hwmap
[i
].rxflags
= sc
->hwmap
[i
].txflags
|
1108 IEEE80211_RADIOTAP_F_FCS
;
1109 /* setup blink rate table to avoid per-packet lookup */
1110 for (j
= 0; j
< ARRAY_SIZE(blinkrates
) - 1; j
++)
1111 if (blinkrates
[j
].rate
== /* XXX why 7f? */
1112 (rt
->rates
[ix
].dot11_rate
&0x7f))
1115 sc
->hwmap
[i
].ledon
= msecs_to_jiffies(blinkrates
[j
].
1117 sc
->hwmap
[i
].ledoff
= msecs_to_jiffies(blinkrates
[j
].
1124 if (mode
== AR5K_MODE_11A
) {
1125 sc
->curband
= &sc
->sbands
[IEEE80211_BAND_5GHZ
];
1127 sc
->curband
= &sc
->sbands
[IEEE80211_BAND_2GHZ
];
1132 ath5k_mode_setup(struct ath5k_softc
*sc
)
1134 struct ath5k_hw
*ah
= sc
->ah
;
1137 /* configure rx filter */
1138 rfilt
= sc
->filter_flags
;
1139 ath5k_hw_set_rx_filter(ah
, rfilt
);
1141 if (ath5k_hw_hasbssidmask(ah
))
1142 ath5k_hw_set_bssid_mask(ah
, sc
->bssidmask
);
1144 /* configure operational mode */
1145 ath5k_hw_set_opmode(ah
);
1147 ath5k_hw_set_mcast_filter(ah
, 0, 0);
1148 ATH5K_DBG(sc
, ATH5K_DEBUG_MODE
, "RX filter 0x%x\n", rfilt
);
1152 * Match the hw provided rate index (through descriptors)
1153 * to an index for sc->curband->bitrates, so it can be used
1156 * This one is a little bit tricky but i think i'm right
1159 * We have 4 rate tables in the following order:
1163 * 802.11g (12 rates)
1164 * that make the hw rate table.
1166 * Lets take a 5211 for example that supports a and b modes only.
1167 * First comes the 802.11a table and then 802.11b (total 12 rates).
1168 * When hw returns eg. 11 it points to the last 802.11b rate (11Mbit),
1169 * if it returns 2 it points to the second 802.11a rate etc.
1171 * Same goes for 5212 who has xr/a/b/g support (total 28 rates).
1172 * First comes the XR table, then 802.11a, 802.11b and 802.11g.
1173 * When hw returns eg. 27 it points to the last 802.11g rate (54Mbits) etc
1176 ath5k_set_total_hw_rates(struct ath5k_softc
*sc
) {
1178 struct ath5k_hw
*ah
= sc
->ah
;
1180 if (test_bit(AR5K_MODE_11A
, ah
->ah_modes
))
1183 if (test_bit(AR5K_MODE_11B
, ah
->ah_modes
))
1186 if (test_bit(AR5K_MODE_11G
, ah
->ah_modes
))
1189 /* XXX: Need to see what what happens when
1190 xr disable bits in eeprom are set */
1191 if (ah
->ah_version
>= AR5K_AR5212
)
1197 ath5k_hw_to_driver_rix(struct ath5k_softc
*sc
, int hw_rix
) {
1201 if(sc
->curband
->band
== IEEE80211_BAND_2GHZ
) {
1202 /* We setup a g ratetable for both b/g modes */
1204 hw_rix
- sc
->b_rates
- sc
->a_rates
- sc
->xr_rates
;
1206 mac80211_rix
= hw_rix
- sc
->xr_rates
;
1209 /* Something went wrong, fallback to basic rate for this band */
1210 if ((mac80211_rix
>= sc
->curband
->n_bitrates
) ||
1211 (mac80211_rix
<= 0 ))
1214 return mac80211_rix
;
1225 ath5k_rxbuf_setup(struct ath5k_softc
*sc
, struct ath5k_buf
*bf
)
1227 struct ath5k_hw
*ah
= sc
->ah
;
1228 struct sk_buff
*skb
= bf
->skb
;
1229 struct ath5k_desc
*ds
;
1231 if (likely(skb
== NULL
)) {
1235 * Allocate buffer with headroom_needed space for the
1236 * fake physical layer header at the start.
1238 skb
= dev_alloc_skb(sc
->rxbufsize
+ sc
->cachelsz
- 1);
1239 if (unlikely(skb
== NULL
)) {
1240 ATH5K_ERR(sc
, "can't alloc skbuff of size %u\n",
1241 sc
->rxbufsize
+ sc
->cachelsz
- 1);
1245 * Cache-line-align. This is important (for the
1246 * 5210 at least) as not doing so causes bogus data
1249 off
= ((unsigned long)skb
->data
) % sc
->cachelsz
;
1251 skb_reserve(skb
, sc
->cachelsz
- off
);
1254 bf
->skbaddr
= pci_map_single(sc
->pdev
,
1255 skb
->data
, sc
->rxbufsize
, PCI_DMA_FROMDEVICE
);
1256 if (unlikely(pci_dma_mapping_error(bf
->skbaddr
))) {
1257 ATH5K_ERR(sc
, "%s: DMA mapping failed\n", __func__
);
1265 * Setup descriptors. For receive we always terminate
1266 * the descriptor list with a self-linked entry so we'll
1267 * not get overrun under high load (as can happen with a
1268 * 5212 when ANI processing enables PHY error frames).
1270 * To insure the last descriptor is self-linked we create
1271 * each descriptor as self-linked and add it to the end. As
1272 * each additional descriptor is added the previous self-linked
1273 * entry is ``fixed'' naturally. This should be safe even
1274 * if DMA is happening. When processing RX interrupts we
1275 * never remove/process the last, self-linked, entry on the
1276 * descriptor list. This insures the hardware always has
1277 * someplace to write a new frame.
1280 ds
->ds_link
= bf
->daddr
; /* link to self */
1281 ds
->ds_data
= bf
->skbaddr
;
1282 ath5k_hw_setup_rx_desc(ah
, ds
,
1283 skb_tailroom(skb
), /* buffer size */
1286 if (sc
->rxlink
!= NULL
)
1287 *sc
->rxlink
= bf
->daddr
;
1288 sc
->rxlink
= &ds
->ds_link
;
1293 ath5k_txbuf_setup(struct ath5k_softc
*sc
, struct ath5k_buf
*bf
)
1295 struct ath5k_hw
*ah
= sc
->ah
;
1296 struct ath5k_txq
*txq
= sc
->txq
;
1297 struct ath5k_desc
*ds
= bf
->desc
;
1298 struct sk_buff
*skb
= bf
->skb
;
1299 struct ieee80211_tx_info
*info
= (void*) skb
->cb
;
1300 unsigned int pktlen
, flags
, keyidx
= AR5K_TXKEYIX_INVALID
;
1303 flags
= AR5K_TXDESC_INTREQ
| AR5K_TXDESC_CLRDMASK
;
1305 /* XXX endianness */
1306 bf
->skbaddr
= pci_map_single(sc
->pdev
, skb
->data
, skb
->len
,
1309 if (info
->flags
& IEEE80211_TX_CTL_NO_ACK
)
1310 flags
|= AR5K_TXDESC_NOACK
;
1314 if (!(info
->flags
& IEEE80211_TX_CTL_DO_NOT_ENCRYPT
)) {
1315 keyidx
= info
->control
.hw_key
->hw_key_idx
;
1316 pktlen
+= info
->control
.icv_len
;
1318 ret
= ah
->ah_setup_tx_desc(ah
, ds
, pktlen
,
1319 ieee80211_get_hdrlen_from_skb(skb
), AR5K_PKT_TYPE_NORMAL
,
1320 (sc
->power_level
* 2),
1321 ieee80211_get_tx_rate(sc
->hw
, info
)->hw_value
,
1322 info
->control
.retry_limit
, keyidx
, 0, flags
, 0, 0);
1327 ds
->ds_data
= bf
->skbaddr
;
1329 spin_lock_bh(&txq
->lock
);
1330 list_add_tail(&bf
->list
, &txq
->q
);
1331 sc
->tx_stats
[txq
->qnum
].len
++;
1332 if (txq
->link
== NULL
) /* is this first packet? */
1333 ath5k_hw_put_tx_buf(ah
, txq
->qnum
, bf
->daddr
);
1334 else /* no, so only link it */
1335 *txq
->link
= bf
->daddr
;
1337 txq
->link
= &ds
->ds_link
;
1338 ath5k_hw_tx_start(ah
, txq
->qnum
);
1339 spin_unlock_bh(&txq
->lock
);
1343 pci_unmap_single(sc
->pdev
, bf
->skbaddr
, skb
->len
, PCI_DMA_TODEVICE
);
1347 /*******************\
1348 * Descriptors setup *
1349 \*******************/
1352 ath5k_desc_alloc(struct ath5k_softc
*sc
, struct pci_dev
*pdev
)
1354 struct ath5k_desc
*ds
;
1355 struct ath5k_buf
*bf
;
1360 /* allocate descriptors */
1361 sc
->desc_len
= sizeof(struct ath5k_desc
) *
1362 (ATH_TXBUF
+ ATH_RXBUF
+ ATH_BCBUF
+ 1);
1363 sc
->desc
= pci_alloc_consistent(pdev
, sc
->desc_len
, &sc
->desc_daddr
);
1364 if (sc
->desc
== NULL
) {
1365 ATH5K_ERR(sc
, "can't allocate descriptors\n");
1370 da
= sc
->desc_daddr
;
1371 ATH5K_DBG(sc
, ATH5K_DEBUG_ANY
, "DMA map: %p (%zu) -> %llx\n",
1372 ds
, sc
->desc_len
, (unsigned long long)sc
->desc_daddr
);
1374 bf
= kcalloc(1 + ATH_TXBUF
+ ATH_RXBUF
+ ATH_BCBUF
,
1375 sizeof(struct ath5k_buf
), GFP_KERNEL
);
1377 ATH5K_ERR(sc
, "can't allocate bufptr\n");
1383 INIT_LIST_HEAD(&sc
->rxbuf
);
1384 for (i
= 0; i
< ATH_RXBUF
; i
++, bf
++, ds
++, da
+= sizeof(*ds
)) {
1387 list_add_tail(&bf
->list
, &sc
->rxbuf
);
1390 INIT_LIST_HEAD(&sc
->txbuf
);
1391 sc
->txbuf_len
= ATH_TXBUF
;
1392 for (i
= 0; i
< ATH_TXBUF
; i
++, bf
++, ds
++,
1393 da
+= sizeof(*ds
)) {
1396 list_add_tail(&bf
->list
, &sc
->txbuf
);
1406 pci_free_consistent(pdev
, sc
->desc_len
, sc
->desc
, sc
->desc_daddr
);
1413 ath5k_desc_free(struct ath5k_softc
*sc
, struct pci_dev
*pdev
)
1415 struct ath5k_buf
*bf
;
1417 ath5k_txbuf_free(sc
, sc
->bbuf
);
1418 list_for_each_entry(bf
, &sc
->txbuf
, list
)
1419 ath5k_txbuf_free(sc
, bf
);
1420 list_for_each_entry(bf
, &sc
->rxbuf
, list
)
1421 ath5k_txbuf_free(sc
, bf
);
1423 /* Free memory associated with all descriptors */
1424 pci_free_consistent(pdev
, sc
->desc_len
, sc
->desc
, sc
->desc_daddr
);
1438 static struct ath5k_txq
*
1439 ath5k_txq_setup(struct ath5k_softc
*sc
,
1440 int qtype
, int subtype
)
1442 struct ath5k_hw
*ah
= sc
->ah
;
1443 struct ath5k_txq
*txq
;
1444 struct ath5k_txq_info qi
= {
1445 .tqi_subtype
= subtype
,
1446 .tqi_aifs
= AR5K_TXQ_USEDEFAULT
,
1447 .tqi_cw_min
= AR5K_TXQ_USEDEFAULT
,
1448 .tqi_cw_max
= AR5K_TXQ_USEDEFAULT
1453 * Enable interrupts only for EOL and DESC conditions.
1454 * We mark tx descriptors to receive a DESC interrupt
1455 * when a tx queue gets deep; otherwise waiting for the
1456 * EOL to reap descriptors. Note that this is done to
1457 * reduce interrupt load and this only defers reaping
1458 * descriptors, never transmitting frames. Aside from
1459 * reducing interrupts this also permits more concurrency.
1460 * The only potential downside is if the tx queue backs
1461 * up in which case the top half of the kernel may backup
1462 * due to a lack of tx descriptors.
1464 qi
.tqi_flags
= AR5K_TXQ_FLAG_TXEOLINT_ENABLE
|
1465 AR5K_TXQ_FLAG_TXDESCINT_ENABLE
;
1466 qnum
= ath5k_hw_setup_tx_queue(ah
, qtype
, &qi
);
1469 * NB: don't print a message, this happens
1470 * normally on parts with too few tx queues
1472 return ERR_PTR(qnum
);
1474 if (qnum
>= ARRAY_SIZE(sc
->txqs
)) {
1475 ATH5K_ERR(sc
, "hw qnum %u out of range, max %tu!\n",
1476 qnum
, ARRAY_SIZE(sc
->txqs
));
1477 ath5k_hw_release_tx_queue(ah
, qnum
);
1478 return ERR_PTR(-EINVAL
);
1480 txq
= &sc
->txqs
[qnum
];
1484 INIT_LIST_HEAD(&txq
->q
);
1485 spin_lock_init(&txq
->lock
);
1488 return &sc
->txqs
[qnum
];
1492 ath5k_beaconq_setup(struct ath5k_hw
*ah
)
1494 struct ath5k_txq_info qi
= {
1495 .tqi_aifs
= AR5K_TXQ_USEDEFAULT
,
1496 .tqi_cw_min
= AR5K_TXQ_USEDEFAULT
,
1497 .tqi_cw_max
= AR5K_TXQ_USEDEFAULT
,
1498 /* NB: for dynamic turbo, don't enable any other interrupts */
1499 .tqi_flags
= AR5K_TXQ_FLAG_TXDESCINT_ENABLE
1502 return ath5k_hw_setup_tx_queue(ah
, AR5K_TX_QUEUE_BEACON
, &qi
);
1506 ath5k_beaconq_config(struct ath5k_softc
*sc
)
1508 struct ath5k_hw
*ah
= sc
->ah
;
1509 struct ath5k_txq_info qi
;
1512 ret
= ath5k_hw_get_tx_queueprops(ah
, sc
->bhalq
, &qi
);
1515 if (sc
->opmode
== IEEE80211_IF_TYPE_AP
) {
1517 * Always burst out beacon and CAB traffic
1518 * (aifs = cwmin = cwmax = 0)
1523 } else if (sc
->opmode
== IEEE80211_IF_TYPE_IBSS
) {
1525 * Adhoc mode; backoff between 0 and (2 * cw_min).
1529 qi
.tqi_cw_max
= 2 * ah
->ah_cw_min
;
1532 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON
,
1533 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1534 qi
.tqi_aifs
, qi
.tqi_cw_min
, qi
.tqi_cw_max
);
1536 ret
= ath5k_hw_setup_tx_queueprops(ah
, sc
->bhalq
, &qi
);
1538 ATH5K_ERR(sc
, "%s: unable to update parameters for beacon "
1539 "hardware queue!\n", __func__
);
1543 return ath5k_hw_reset_tx_queue(ah
, sc
->bhalq
); /* push to h/w */;
1547 ath5k_txq_drainq(struct ath5k_softc
*sc
, struct ath5k_txq
*txq
)
1549 struct ath5k_buf
*bf
, *bf0
;
1552 * NB: this assumes output has been stopped and
1553 * we do not need to block ath5k_tx_tasklet
1555 spin_lock_bh(&txq
->lock
);
1556 list_for_each_entry_safe(bf
, bf0
, &txq
->q
, list
) {
1557 ath5k_debug_printtxbuf(sc
, bf
);
1559 ath5k_txbuf_free(sc
, bf
);
1561 spin_lock_bh(&sc
->txbuflock
);
1562 sc
->tx_stats
[txq
->qnum
].len
--;
1563 list_move_tail(&bf
->list
, &sc
->txbuf
);
1565 spin_unlock_bh(&sc
->txbuflock
);
1568 spin_unlock_bh(&txq
->lock
);
1572 * Drain the transmit queues and reclaim resources.
1575 ath5k_txq_cleanup(struct ath5k_softc
*sc
)
1577 struct ath5k_hw
*ah
= sc
->ah
;
1580 /* XXX return value */
1581 if (likely(!test_bit(ATH_STAT_INVALID
, sc
->status
))) {
1582 /* don't touch the hardware if marked invalid */
1583 ath5k_hw_stop_tx_dma(ah
, sc
->bhalq
);
1584 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "beacon queue %x\n",
1585 ath5k_hw_get_tx_buf(ah
, sc
->bhalq
));
1586 for (i
= 0; i
< ARRAY_SIZE(sc
->txqs
); i
++)
1587 if (sc
->txqs
[i
].setup
) {
1588 ath5k_hw_stop_tx_dma(ah
, sc
->txqs
[i
].qnum
);
1589 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "txq [%u] %x, "
1592 ath5k_hw_get_tx_buf(ah
,
1597 ieee80211_wake_queues(sc
->hw
); /* XXX move to callers */
1599 for (i
= 0; i
< ARRAY_SIZE(sc
->txqs
); i
++)
1600 if (sc
->txqs
[i
].setup
)
1601 ath5k_txq_drainq(sc
, &sc
->txqs
[i
]);
1605 ath5k_txq_release(struct ath5k_softc
*sc
)
1607 struct ath5k_txq
*txq
= sc
->txqs
;
1610 for (i
= 0; i
< ARRAY_SIZE(sc
->txqs
); i
++, txq
++)
1612 ath5k_hw_release_tx_queue(sc
->ah
, txq
->qnum
);
1625 * Enable the receive h/w following a reset.
1628 ath5k_rx_start(struct ath5k_softc
*sc
)
1630 struct ath5k_hw
*ah
= sc
->ah
;
1631 struct ath5k_buf
*bf
;
1634 sc
->rxbufsize
= roundup(IEEE80211_MAX_LEN
, sc
->cachelsz
);
1636 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "cachelsz %u rxbufsize %u\n",
1637 sc
->cachelsz
, sc
->rxbufsize
);
1641 spin_lock_bh(&sc
->rxbuflock
);
1642 list_for_each_entry(bf
, &sc
->rxbuf
, list
) {
1643 ret
= ath5k_rxbuf_setup(sc
, bf
);
1645 spin_unlock_bh(&sc
->rxbuflock
);
1649 bf
= list_first_entry(&sc
->rxbuf
, struct ath5k_buf
, list
);
1650 spin_unlock_bh(&sc
->rxbuflock
);
1652 ath5k_hw_put_rx_buf(ah
, bf
->daddr
);
1653 ath5k_hw_start_rx(ah
); /* enable recv descriptors */
1654 ath5k_mode_setup(sc
); /* set filters, etc. */
1655 ath5k_hw_start_rx_pcu(ah
); /* re-enable PCU/DMA engine */
1663 * Disable the receive h/w in preparation for a reset.
1666 ath5k_rx_stop(struct ath5k_softc
*sc
)
1668 struct ath5k_hw
*ah
= sc
->ah
;
1670 ath5k_hw_stop_pcu_recv(ah
); /* disable PCU */
1671 ath5k_hw_set_rx_filter(ah
, 0); /* clear recv filter */
1672 ath5k_hw_stop_rx_dma(ah
); /* disable DMA engine */
1673 mdelay(3); /* 3ms is long enough for 1 frame */
1675 ath5k_debug_printrxbuffs(sc
, ah
);
1677 sc
->rxlink
= NULL
; /* just in case */
1681 ath5k_rx_decrypted(struct ath5k_softc
*sc
, struct ath5k_desc
*ds
,
1682 struct sk_buff
*skb
, struct ath5k_rx_status
*rs
)
1684 struct ieee80211_hdr
*hdr
= (void *)skb
->data
;
1685 unsigned int keyix
, hlen
= ieee80211_get_hdrlen_from_skb(skb
);
1687 if (!(rs
->rs_status
& AR5K_RXERR_DECRYPT
) &&
1688 rs
->rs_keyix
!= AR5K_RXKEYIX_INVALID
)
1689 return RX_FLAG_DECRYPTED
;
1691 /* Apparently when a default key is used to decrypt the packet
1692 the hw does not set the index used to decrypt. In such cases
1693 get the index from the packet. */
1694 if ((le16_to_cpu(hdr
->frame_control
) & IEEE80211_FCTL_PROTECTED
) &&
1695 !(rs
->rs_status
& AR5K_RXERR_DECRYPT
) &&
1696 skb
->len
>= hlen
+ 4) {
1697 keyix
= skb
->data
[hlen
+ 3] >> 6;
1699 if (test_bit(keyix
, sc
->keymap
))
1700 return RX_FLAG_DECRYPTED
;
1708 ath5k_check_ibss_tsf(struct ath5k_softc
*sc
, struct sk_buff
*skb
,
1709 struct ieee80211_rx_status
*rxs
)
1713 struct ieee80211_mgmt
*mgmt
= (struct ieee80211_mgmt
*)skb
->data
;
1715 if ((le16_to_cpu(mgmt
->frame_control
) & IEEE80211_FCTL_FTYPE
) ==
1716 IEEE80211_FTYPE_MGMT
&&
1717 (le16_to_cpu(mgmt
->frame_control
) & IEEE80211_FCTL_STYPE
) ==
1718 IEEE80211_STYPE_BEACON
&&
1719 le16_to_cpu(mgmt
->u
.beacon
.capab_info
) & WLAN_CAPABILITY_IBSS
&&
1720 memcmp(mgmt
->bssid
, sc
->ah
->ah_bssid
, ETH_ALEN
) == 0) {
1722 * Received an IBSS beacon with the same BSSID. Hardware *must*
1723 * have updated the local TSF. We have to work around various
1724 * hardware bugs, though...
1726 tsf
= ath5k_hw_get_tsf64(sc
->ah
);
1727 bc_tstamp
= le64_to_cpu(mgmt
->u
.beacon
.timestamp
);
1728 hw_tu
= TSF_TO_TU(tsf
);
1730 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
,
1731 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
1732 (unsigned long long)bc_tstamp
,
1733 (unsigned long long)rxs
->mactime
,
1734 (unsigned long long)(rxs
->mactime
- bc_tstamp
),
1735 (unsigned long long)tsf
);
1738 * Sometimes the HW will give us a wrong tstamp in the rx
1739 * status, causing the timestamp extension to go wrong.
1740 * (This seems to happen especially with beacon frames bigger
1741 * than 78 byte (incl. FCS))
1742 * But we know that the receive timestamp must be later than the
1743 * timestamp of the beacon since HW must have synced to that.
1745 * NOTE: here we assume mactime to be after the frame was
1746 * received, not like mac80211 which defines it at the start.
1748 if (bc_tstamp
> rxs
->mactime
) {
1749 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
,
1750 "fixing mactime from %llx to %llx\n",
1751 (unsigned long long)rxs
->mactime
,
1752 (unsigned long long)tsf
);
1757 * Local TSF might have moved higher than our beacon timers,
1758 * in that case we have to update them to continue sending
1759 * beacons. This also takes care of synchronizing beacon sending
1760 * times with other stations.
1762 if (hw_tu
>= sc
->nexttbtt
)
1763 ath5k_beacon_update_timers(sc
, bc_tstamp
);
1769 ath5k_tasklet_rx(unsigned long data
)
1771 struct ieee80211_rx_status rxs
= {};
1772 struct ath5k_rx_status rs
= {};
1773 struct sk_buff
*skb
;
1774 struct ath5k_softc
*sc
= (void *)data
;
1775 struct ath5k_buf
*bf
;
1776 struct ath5k_desc
*ds
;
1781 spin_lock(&sc
->rxbuflock
);
1785 if (unlikely(list_empty(&sc
->rxbuf
))) {
1786 ATH5K_WARN(sc
, "empty rx buf pool\n");
1789 bf
= list_first_entry(&sc
->rxbuf
, struct ath5k_buf
, list
);
1790 BUG_ON(bf
->skb
== NULL
);
1794 /* TODO only one segment */
1795 pci_dma_sync_single_for_cpu(sc
->pdev
, sc
->desc_daddr
,
1796 sc
->desc_len
, PCI_DMA_FROMDEVICE
);
1798 if (unlikely(ds
->ds_link
== bf
->daddr
)) /* this is the end */
1801 ret
= sc
->ah
->ah_proc_rx_desc(sc
->ah
, ds
, &rs
);
1802 if (unlikely(ret
== -EINPROGRESS
))
1804 else if (unlikely(ret
)) {
1805 ATH5K_ERR(sc
, "error in processing rx descriptor\n");
1806 spin_unlock(&sc
->rxbuflock
);
1810 if (unlikely(rs
.rs_more
)) {
1811 ATH5K_WARN(sc
, "unsupported jumbo\n");
1815 if (unlikely(rs
.rs_status
)) {
1816 if (rs
.rs_status
& AR5K_RXERR_PHY
)
1818 if (rs
.rs_status
& AR5K_RXERR_DECRYPT
) {
1820 * Decrypt error. If the error occurred
1821 * because there was no hardware key, then
1822 * let the frame through so the upper layers
1823 * can process it. This is necessary for 5210
1824 * parts which have no way to setup a ``clear''
1827 * XXX do key cache faulting
1829 if (rs
.rs_keyix
== AR5K_RXKEYIX_INVALID
&&
1830 !(rs
.rs_status
& AR5K_RXERR_CRC
))
1833 if (rs
.rs_status
& AR5K_RXERR_MIC
) {
1834 rxs
.flag
|= RX_FLAG_MMIC_ERROR
;
1838 /* let crypto-error packets fall through in MNTR */
1840 ~(AR5K_RXERR_DECRYPT
|AR5K_RXERR_MIC
)) ||
1841 sc
->opmode
!= IEEE80211_IF_TYPE_MNTR
)
1845 pci_dma_sync_single_for_cpu(sc
->pdev
, bf
->skbaddr
,
1846 rs
.rs_datalen
, PCI_DMA_FROMDEVICE
);
1847 pci_unmap_single(sc
->pdev
, bf
->skbaddr
, sc
->rxbufsize
,
1848 PCI_DMA_FROMDEVICE
);
1851 skb_put(skb
, rs
.rs_datalen
);
1854 * the hardware adds a padding to 4 byte boundaries between
1855 * the header and the payload data if the header length is
1856 * not multiples of 4 - remove it
1858 hdrlen
= ieee80211_get_hdrlen_from_skb(skb
);
1861 memmove(skb
->data
+ pad
, skb
->data
, hdrlen
);
1866 * always extend the mac timestamp, since this information is
1867 * also needed for proper IBSS merging.
1869 * XXX: it might be too late to do it here, since rs_tstamp is
1870 * 15bit only. that means TSF extension has to be done within
1871 * 32768usec (about 32ms). it might be necessary to move this to
1872 * the interrupt handler, like it is done in madwifi.
1874 * Unfortunately we don't know when the hardware takes the rx
1875 * timestamp (beginning of phy frame, data frame, end of rx?).
1876 * The only thing we know is that it is hardware specific...
1877 * On AR5213 it seems the rx timestamp is at the end of the
1878 * frame, but i'm not sure.
1880 * NOTE: mac80211 defines mactime at the beginning of the first
1881 * data symbol. Since we don't have any time references it's
1882 * impossible to comply to that. This affects IBSS merge only
1883 * right now, so it's not too bad...
1885 rxs
.mactime
= ath5k_extend_tsf(sc
->ah
, rs
.rs_tstamp
);
1886 rxs
.flag
|= RX_FLAG_TSFT
;
1888 rxs
.freq
= sc
->curchan
->center_freq
;
1889 rxs
.band
= sc
->curband
->band
;
1891 rxs
.noise
= sc
->ah
->ah_noise_floor
;
1892 rxs
.signal
= rxs
.noise
+ rs
.rs_rssi
;
1893 rxs
.qual
= rs
.rs_rssi
* 100 / 64;
1895 rxs
.antenna
= rs
.rs_antenna
;
1896 rxs
.rate_idx
= ath5k_hw_to_driver_rix(sc
, rs
.rs_rate
);
1897 rxs
.flag
|= ath5k_rx_decrypted(sc
, ds
, skb
, &rs
);
1899 ath5k_debug_dump_skb(sc
, skb
, "RX ", 0);
1901 /* check beacons in IBSS mode */
1902 if (sc
->opmode
== IEEE80211_IF_TYPE_IBSS
)
1903 ath5k_check_ibss_tsf(sc
, skb
, &rxs
);
1905 __ieee80211_rx(sc
->hw
, skb
, &rxs
);
1906 sc
->led_rxrate
= rs
.rs_rate
;
1907 ath5k_led_event(sc
, ATH_LED_RX
);
1909 list_move_tail(&bf
->list
, &sc
->rxbuf
);
1910 } while (ath5k_rxbuf_setup(sc
, bf
) == 0);
1911 spin_unlock(&sc
->rxbuflock
);
1922 ath5k_tx_processq(struct ath5k_softc
*sc
, struct ath5k_txq
*txq
)
1924 struct ath5k_tx_status ts
= {};
1925 struct ath5k_buf
*bf
, *bf0
;
1926 struct ath5k_desc
*ds
;
1927 struct sk_buff
*skb
;
1928 struct ieee80211_tx_info
*info
;
1931 spin_lock(&txq
->lock
);
1932 list_for_each_entry_safe(bf
, bf0
, &txq
->q
, list
) {
1935 /* TODO only one segment */
1936 pci_dma_sync_single_for_cpu(sc
->pdev
, sc
->desc_daddr
,
1937 sc
->desc_len
, PCI_DMA_FROMDEVICE
);
1938 ret
= sc
->ah
->ah_proc_tx_desc(sc
->ah
, ds
, &ts
);
1939 if (unlikely(ret
== -EINPROGRESS
))
1941 else if (unlikely(ret
)) {
1942 ATH5K_ERR(sc
, "error %d while processing queue %u\n",
1948 info
= (void*) skb
->cb
;
1951 pci_unmap_single(sc
->pdev
, bf
->skbaddr
, skb
->len
,
1954 info
->status
.retry_count
= ts
.ts_shortretry
+ ts
.ts_longretry
/ 6;
1955 if (unlikely(ts
.ts_status
)) {
1956 sc
->ll_stats
.dot11ACKFailureCount
++;
1957 if (ts
.ts_status
& AR5K_TXERR_XRETRY
)
1958 info
->status
.excessive_retries
= 1;
1959 else if (ts
.ts_status
& AR5K_TXERR_FILT
)
1960 info
->flags
|= IEEE80211_TX_STAT_TX_FILTERED
;
1962 info
->flags
|= IEEE80211_TX_STAT_ACK
;
1963 info
->status
.ack_signal
= ts
.ts_rssi
;
1966 ieee80211_tx_status(sc
->hw
, skb
);
1967 sc
->tx_stats
[txq
->qnum
].count
++;
1969 spin_lock(&sc
->txbuflock
);
1970 sc
->tx_stats
[txq
->qnum
].len
--;
1971 list_move_tail(&bf
->list
, &sc
->txbuf
);
1973 spin_unlock(&sc
->txbuflock
);
1975 if (likely(list_empty(&txq
->q
)))
1977 spin_unlock(&txq
->lock
);
1978 if (sc
->txbuf_len
> ATH_TXBUF
/ 5)
1979 ieee80211_wake_queues(sc
->hw
);
1983 ath5k_tasklet_tx(unsigned long data
)
1985 struct ath5k_softc
*sc
= (void *)data
;
1987 ath5k_tx_processq(sc
, sc
->txq
);
1989 ath5k_led_event(sc
, ATH_LED_TX
);
2000 * Setup the beacon frame for transmit.
2003 ath5k_beacon_setup(struct ath5k_softc
*sc
, struct ath5k_buf
*bf
)
2005 struct sk_buff
*skb
= bf
->skb
;
2006 struct ieee80211_tx_info
*info
= (void*) skb
->cb
;
2007 struct ath5k_hw
*ah
= sc
->ah
;
2008 struct ath5k_desc
*ds
;
2009 int ret
, antenna
= 0;
2012 bf
->skbaddr
= pci_map_single(sc
->pdev
, skb
->data
, skb
->len
,
2014 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON
, "skb %p [data %p len %u] "
2015 "skbaddr %llx\n", skb
, skb
->data
, skb
->len
,
2016 (unsigned long long)bf
->skbaddr
);
2017 if (pci_dma_mapping_error(bf
->skbaddr
)) {
2018 ATH5K_ERR(sc
, "beacon DMA mapping failed\n");
2024 flags
= AR5K_TXDESC_NOACK
;
2025 if (sc
->opmode
== IEEE80211_IF_TYPE_IBSS
&& ath5k_hw_hasveol(ah
)) {
2026 ds
->ds_link
= bf
->daddr
; /* self-linked */
2027 flags
|= AR5K_TXDESC_VEOL
;
2029 * Let hardware handle antenna switching if txantenna is not set
2034 * Switch antenna every 4 beacons if txantenna is not set
2035 * XXX assumes two antennas
2038 antenna
= sc
->bsent
& 4 ? 2 : 1;
2041 ds
->ds_data
= bf
->skbaddr
;
2042 ret
= ah
->ah_setup_tx_desc(ah
, ds
, skb
->len
,
2043 ieee80211_get_hdrlen_from_skb(skb
),
2044 AR5K_PKT_TYPE_BEACON
, (sc
->power_level
* 2),
2045 ieee80211_get_tx_rate(sc
->hw
, info
)->hw_value
,
2046 1, AR5K_TXKEYIX_INVALID
,
2047 antenna
, flags
, 0, 0);
2053 pci_unmap_single(sc
->pdev
, bf
->skbaddr
, skb
->len
, PCI_DMA_TODEVICE
);
2058 * Transmit a beacon frame at SWBA. Dynamic updates to the
2059 * frame contents are done as needed and the slot time is
2060 * also adjusted based on current state.
2062 * this is usually called from interrupt context (ath5k_intr())
2063 * but also from ath5k_beacon_config() in IBSS mode which in turn
2064 * can be called from a tasklet and user context
2067 ath5k_beacon_send(struct ath5k_softc
*sc
)
2069 struct ath5k_buf
*bf
= sc
->bbuf
;
2070 struct ath5k_hw
*ah
= sc
->ah
;
2072 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
, "in beacon_send\n");
2074 if (unlikely(bf
->skb
== NULL
|| sc
->opmode
== IEEE80211_IF_TYPE_STA
||
2075 sc
->opmode
== IEEE80211_IF_TYPE_MNTR
)) {
2076 ATH5K_WARN(sc
, "bf=%p bf_skb=%p\n", bf
, bf
? bf
->skb
: NULL
);
2080 * Check if the previous beacon has gone out. If
2081 * not don't don't try to post another, skip this
2082 * period and wait for the next. Missed beacons
2083 * indicate a problem and should not occur. If we
2084 * miss too many consecutive beacons reset the device.
2086 if (unlikely(ath5k_hw_num_tx_pending(ah
, sc
->bhalq
) != 0)) {
2088 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON
,
2089 "missed %u consecutive beacons\n", sc
->bmisscount
);
2090 if (sc
->bmisscount
> 3) { /* NB: 3 is a guess */
2091 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON
,
2092 "stuck beacon time (%u missed)\n",
2094 tasklet_schedule(&sc
->restq
);
2098 if (unlikely(sc
->bmisscount
!= 0)) {
2099 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON
,
2100 "resume beacon xmit after %u misses\n",
2106 * Stop any current dma and put the new frame on the queue.
2107 * This should never fail since we check above that no frames
2108 * are still pending on the queue.
2110 if (unlikely(ath5k_hw_stop_tx_dma(ah
, sc
->bhalq
))) {
2111 ATH5K_WARN(sc
, "beacon queue %u didn't stop?\n", sc
->bhalq
);
2112 /* NB: hw still stops DMA, so proceed */
2114 pci_dma_sync_single_for_cpu(sc
->pdev
, bf
->skbaddr
, bf
->skb
->len
,
2117 ath5k_hw_put_tx_buf(ah
, sc
->bhalq
, bf
->daddr
);
2118 ath5k_hw_tx_start(ah
, sc
->bhalq
);
2119 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON
, "TXDP[%u] = %llx (%p)\n",
2120 sc
->bhalq
, (unsigned long long)bf
->daddr
, bf
->desc
);
2127 * ath5k_beacon_update_timers - update beacon timers
2129 * @sc: struct ath5k_softc pointer we are operating on
2130 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
2131 * beacon timer update based on the current HW TSF.
2133 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
2134 * of a received beacon or the current local hardware TSF and write it to the
2135 * beacon timer registers.
2137 * This is called in a variety of situations, e.g. when a beacon is received,
2138 * when a TSF update has been detected, but also when an new IBSS is created or
2139 * when we otherwise know we have to update the timers, but we keep it in this
2140 * function to have it all together in one place.
2143 ath5k_beacon_update_timers(struct ath5k_softc
*sc
, u64 bc_tsf
)
2145 struct ath5k_hw
*ah
= sc
->ah
;
2146 u32 nexttbtt
, intval
, hw_tu
, bc_tu
;
2149 intval
= sc
->bintval
& AR5K_BEACON_PERIOD
;
2150 if (WARN_ON(!intval
))
2153 /* beacon TSF converted to TU */
2154 bc_tu
= TSF_TO_TU(bc_tsf
);
2156 /* current TSF converted to TU */
2157 hw_tsf
= ath5k_hw_get_tsf64(ah
);
2158 hw_tu
= TSF_TO_TU(hw_tsf
);
2161 /* we use FUDGE to make sure the next TBTT is ahead of the current TU */
2164 * no beacons received, called internally.
2165 * just need to refresh timers based on HW TSF.
2167 nexttbtt
= roundup(hw_tu
+ FUDGE
, intval
);
2168 } else if (bc_tsf
== 0) {
2170 * no beacon received, probably called by ath5k_reset_tsf().
2171 * reset TSF to start with 0.
2174 intval
|= AR5K_BEACON_RESET_TSF
;
2175 } else if (bc_tsf
> hw_tsf
) {
2177 * beacon received, SW merge happend but HW TSF not yet updated.
2178 * not possible to reconfigure timers yet, but next time we
2179 * receive a beacon with the same BSSID, the hardware will
2180 * automatically update the TSF and then we need to reconfigure
2183 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
,
2184 "need to wait for HW TSF sync\n");
2188 * most important case for beacon synchronization between STA.
2190 * beacon received and HW TSF has been already updated by HW.
2191 * update next TBTT based on the TSF of the beacon, but make
2192 * sure it is ahead of our local TSF timer.
2194 nexttbtt
= bc_tu
+ roundup(hw_tu
+ FUDGE
- bc_tu
, intval
);
2198 sc
->nexttbtt
= nexttbtt
;
2200 intval
|= AR5K_BEACON_ENA
;
2201 ath5k_hw_init_beacon(ah
, nexttbtt
, intval
);
2204 * debugging output last in order to preserve the time critical aspect
2208 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
,
2209 "reconfigured timers based on HW TSF\n");
2210 else if (bc_tsf
== 0)
2211 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
,
2212 "reset HW TSF and timers\n");
2214 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
,
2215 "updated timers based on beacon TSF\n");
2217 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
,
2218 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2219 (unsigned long long) bc_tsf
,
2220 (unsigned long long) hw_tsf
, bc_tu
, hw_tu
, nexttbtt
);
2221 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
, "intval %u %s %s\n",
2222 intval
& AR5K_BEACON_PERIOD
,
2223 intval
& AR5K_BEACON_ENA
? "AR5K_BEACON_ENA" : "",
2224 intval
& AR5K_BEACON_RESET_TSF
? "AR5K_BEACON_RESET_TSF" : "");
2229 * ath5k_beacon_config - Configure the beacon queues and interrupts
2231 * @sc: struct ath5k_softc pointer we are operating on
2233 * When operating in station mode we want to receive a BMISS interrupt when we
2234 * stop seeing beacons from the AP we've associated with so we can look for
2235 * another AP to associate with.
2237 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
2238 * interrupts to detect TSF updates only.
2240 * AP mode is missing.
2243 ath5k_beacon_config(struct ath5k_softc
*sc
)
2245 struct ath5k_hw
*ah
= sc
->ah
;
2247 ath5k_hw_set_intr(ah
, 0);
2250 if (sc
->opmode
== IEEE80211_IF_TYPE_STA
) {
2251 sc
->imask
|= AR5K_INT_BMISS
;
2252 } else if (sc
->opmode
== IEEE80211_IF_TYPE_IBSS
) {
2254 * In IBSS mode we use a self-linked tx descriptor and let the
2255 * hardware send the beacons automatically. We have to load it
2257 * We use the SWBA interrupt only to keep track of the beacon
2258 * timers in order to detect automatic TSF updates.
2260 ath5k_beaconq_config(sc
);
2262 sc
->imask
|= AR5K_INT_SWBA
;
2264 if (ath5k_hw_hasveol(ah
))
2265 ath5k_beacon_send(sc
);
2269 ath5k_hw_set_intr(ah
, sc
->imask
);
2273 /********************\
2274 * Interrupt handling *
2275 \********************/
2278 ath5k_init(struct ath5k_softc
*sc
)
2282 mutex_lock(&sc
->lock
);
2284 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "mode %d\n", sc
->opmode
);
2287 * Stop anything previously setup. This is safe
2288 * no matter this is the first time through or not.
2290 ath5k_stop_locked(sc
);
2293 * The basic interface to setting the hardware in a good
2294 * state is ``reset''. On return the hardware is known to
2295 * be powered up and with interrupts disabled. This must
2296 * be followed by initialization of the appropriate bits
2297 * and then setup of the interrupt mask.
2299 sc
->curchan
= sc
->hw
->conf
.channel
;
2300 sc
->curband
= &sc
->sbands
[sc
->curchan
->band
];
2301 ret
= ath5k_hw_reset(sc
->ah
, sc
->opmode
, sc
->curchan
, false);
2303 ATH5K_ERR(sc
, "unable to reset hardware: %d\n", ret
);
2307 * This is needed only to setup initial state
2308 * but it's best done after a reset.
2310 ath5k_hw_set_txpower_limit(sc
->ah
, 0);
2313 * Setup the hardware after reset: the key cache
2314 * is filled as needed and the receive engine is
2315 * set going. Frame transmit is handled entirely
2316 * in the frame output path; there's nothing to do
2317 * here except setup the interrupt mask.
2319 ret
= ath5k_rx_start(sc
);
2324 * Enable interrupts.
2326 sc
->imask
= AR5K_INT_RX
| AR5K_INT_TX
| AR5K_INT_RXEOL
|
2327 AR5K_INT_RXORN
| AR5K_INT_FATAL
| AR5K_INT_GLOBAL
|
2330 ath5k_hw_set_intr(sc
->ah
, sc
->imask
);
2331 /* Set ack to be sent at low bit-rates */
2332 ath5k_hw_set_ack_bitrate_high(sc
->ah
, false);
2334 mod_timer(&sc
->calib_tim
, round_jiffies(jiffies
+
2335 msecs_to_jiffies(ath5k_calinterval
* 1000)));
2339 mutex_unlock(&sc
->lock
);
2344 ath5k_stop_locked(struct ath5k_softc
*sc
)
2346 struct ath5k_hw
*ah
= sc
->ah
;
2348 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "invalid %u\n",
2349 test_bit(ATH_STAT_INVALID
, sc
->status
));
2352 * Shutdown the hardware and driver:
2353 * stop output from above
2354 * disable interrupts
2356 * turn off the radio
2357 * clear transmit machinery
2358 * clear receive machinery
2359 * drain and release tx queues
2360 * reclaim beacon resources
2361 * power down hardware
2363 * Note that some of this work is not possible if the
2364 * hardware is gone (invalid).
2366 ieee80211_stop_queues(sc
->hw
);
2368 if (!test_bit(ATH_STAT_INVALID
, sc
->status
)) {
2369 if (test_bit(ATH_STAT_LEDSOFT
, sc
->status
)) {
2370 del_timer_sync(&sc
->led_tim
);
2371 ath5k_hw_set_gpio(ah
, sc
->led_pin
, !sc
->led_on
);
2372 __clear_bit(ATH_STAT_LEDBLINKING
, sc
->status
);
2374 ath5k_hw_set_intr(ah
, 0);
2376 ath5k_txq_cleanup(sc
);
2377 if (!test_bit(ATH_STAT_INVALID
, sc
->status
)) {
2379 ath5k_hw_phy_disable(ah
);
2387 * Stop the device, grabbing the top-level lock to protect
2388 * against concurrent entry through ath5k_init (which can happen
2389 * if another thread does a system call and the thread doing the
2390 * stop is preempted).
2393 ath5k_stop_hw(struct ath5k_softc
*sc
)
2397 mutex_lock(&sc
->lock
);
2398 ret
= ath5k_stop_locked(sc
);
2399 if (ret
== 0 && !test_bit(ATH_STAT_INVALID
, sc
->status
)) {
2401 * Set the chip in full sleep mode. Note that we are
2402 * careful to do this only when bringing the interface
2403 * completely to a stop. When the chip is in this state
2404 * it must be carefully woken up or references to
2405 * registers in the PCI clock domain may freeze the bus
2406 * (and system). This varies by chip and is mostly an
2407 * issue with newer parts that go to sleep more quickly.
2409 if (sc
->ah
->ah_mac_srev
>= 0x78) {
2412 * don't put newer MAC revisions > 7.8 to sleep because
2413 * of the above mentioned problems
2415 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "mac version > 7.8, "
2416 "not putting device to sleep\n");
2418 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
,
2419 "putting device to full sleep\n");
2420 ath5k_hw_set_power(sc
->ah
, AR5K_PM_FULL_SLEEP
, true, 0);
2423 ath5k_txbuf_free(sc
, sc
->bbuf
);
2424 mutex_unlock(&sc
->lock
);
2426 del_timer_sync(&sc
->calib_tim
);
2432 ath5k_intr(int irq
, void *dev_id
)
2434 struct ath5k_softc
*sc
= dev_id
;
2435 struct ath5k_hw
*ah
= sc
->ah
;
2436 enum ath5k_int status
;
2437 unsigned int counter
= 1000;
2439 if (unlikely(test_bit(ATH_STAT_INVALID
, sc
->status
) ||
2440 !ath5k_hw_is_intr_pending(ah
)))
2445 * Figure out the reason(s) for the interrupt. Note
2446 * that get_isr returns a pseudo-ISR that may include
2447 * bits we haven't explicitly enabled so we mask the
2448 * value to insure we only process bits we requested.
2450 ath5k_hw_get_isr(ah
, &status
); /* NB: clears IRQ too */
2451 ATH5K_DBG(sc
, ATH5K_DEBUG_INTR
, "status 0x%x/0x%x\n",
2453 status
&= sc
->imask
; /* discard unasked for bits */
2454 if (unlikely(status
& AR5K_INT_FATAL
)) {
2456 * Fatal errors are unrecoverable.
2457 * Typically these are caused by DMA errors.
2459 tasklet_schedule(&sc
->restq
);
2460 } else if (unlikely(status
& AR5K_INT_RXORN
)) {
2461 tasklet_schedule(&sc
->restq
);
2463 if (status
& AR5K_INT_SWBA
) {
2465 * Software beacon alert--time to send a beacon.
2466 * Handle beacon transmission directly; deferring
2467 * this is too slow to meet timing constraints
2470 * In IBSS mode we use this interrupt just to
2471 * keep track of the next TBTT (target beacon
2472 * transmission time) in order to detect wether
2473 * automatic TSF updates happened.
2475 if (sc
->opmode
== IEEE80211_IF_TYPE_IBSS
) {
2476 /* XXX: only if VEOL suppported */
2477 u64 tsf
= ath5k_hw_get_tsf64(ah
);
2478 sc
->nexttbtt
+= sc
->bintval
;
2479 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON
,
2480 "SWBA nexttbtt: %x hw_tu: %x "
2484 (unsigned long long) tsf
);
2486 ath5k_beacon_send(sc
);
2489 if (status
& AR5K_INT_RXEOL
) {
2491 * NB: the hardware should re-read the link when
2492 * RXE bit is written, but it doesn't work at
2493 * least on older hardware revs.
2497 if (status
& AR5K_INT_TXURN
) {
2498 /* bump tx trigger level */
2499 ath5k_hw_update_tx_triglevel(ah
, true);
2501 if (status
& AR5K_INT_RX
)
2502 tasklet_schedule(&sc
->rxtq
);
2503 if (status
& AR5K_INT_TX
)
2504 tasklet_schedule(&sc
->txtq
);
2505 if (status
& AR5K_INT_BMISS
) {
2507 if (status
& AR5K_INT_MIB
) {
2509 * These stats are also used for ANI i think
2510 * so how about updating them more often ?
2512 ath5k_hw_update_mib_counters(ah
, &sc
->ll_stats
);
2515 } while (ath5k_hw_is_intr_pending(ah
) && counter
-- > 0);
2517 if (unlikely(!counter
))
2518 ATH5K_WARN(sc
, "too many interrupts, giving up for now\n");
2524 ath5k_tasklet_reset(unsigned long data
)
2526 struct ath5k_softc
*sc
= (void *)data
;
2528 ath5k_reset(sc
->hw
);
2532 * Periodically recalibrate the PHY to account
2533 * for temperature/environment changes.
2536 ath5k_calibrate(unsigned long data
)
2538 struct ath5k_softc
*sc
= (void *)data
;
2539 struct ath5k_hw
*ah
= sc
->ah
;
2541 ATH5K_DBG(sc
, ATH5K_DEBUG_CALIBRATE
, "channel %u/%x\n",
2542 ieee80211_frequency_to_channel(sc
->curchan
->center_freq
),
2543 sc
->curchan
->hw_value
);
2545 if (ath5k_hw_get_rf_gain(ah
) == AR5K_RFGAIN_NEED_CHANGE
) {
2547 * Rfgain is out of bounds, reset the chip
2548 * to load new gain values.
2550 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "calibration, resetting\n");
2551 ath5k_reset(sc
->hw
);
2553 if (ath5k_hw_phy_calibrate(ah
, sc
->curchan
))
2554 ATH5K_ERR(sc
, "calibration of channel %u failed\n",
2555 ieee80211_frequency_to_channel(
2556 sc
->curchan
->center_freq
));
2558 mod_timer(&sc
->calib_tim
, round_jiffies(jiffies
+
2559 msecs_to_jiffies(ath5k_calinterval
* 1000)));
2569 ath5k_led_off(unsigned long data
)
2571 struct ath5k_softc
*sc
= (void *)data
;
2573 if (test_bit(ATH_STAT_LEDENDBLINK
, sc
->status
))
2574 __clear_bit(ATH_STAT_LEDBLINKING
, sc
->status
);
2576 __set_bit(ATH_STAT_LEDENDBLINK
, sc
->status
);
2577 ath5k_hw_set_gpio(sc
->ah
, sc
->led_pin
, !sc
->led_on
);
2578 mod_timer(&sc
->led_tim
, jiffies
+ sc
->led_off
);
2583 * Blink the LED according to the specified on/off times.
2586 ath5k_led_blink(struct ath5k_softc
*sc
, unsigned int on
,
2589 ATH5K_DBG(sc
, ATH5K_DEBUG_LED
, "on %u off %u\n", on
, off
);
2590 ath5k_hw_set_gpio(sc
->ah
, sc
->led_pin
, sc
->led_on
);
2591 __set_bit(ATH_STAT_LEDBLINKING
, sc
->status
);
2592 __clear_bit(ATH_STAT_LEDENDBLINK
, sc
->status
);
2594 mod_timer(&sc
->led_tim
, jiffies
+ on
);
2598 ath5k_led_event(struct ath5k_softc
*sc
, int event
)
2600 if (likely(!test_bit(ATH_STAT_LEDSOFT
, sc
->status
)))
2602 if (unlikely(test_bit(ATH_STAT_LEDBLINKING
, sc
->status
)))
2603 return; /* don't interrupt active blink */
2606 ath5k_led_blink(sc
, sc
->hwmap
[sc
->led_txrate
].ledon
,
2607 sc
->hwmap
[sc
->led_txrate
].ledoff
);
2610 ath5k_led_blink(sc
, sc
->hwmap
[sc
->led_rxrate
].ledon
,
2611 sc
->hwmap
[sc
->led_rxrate
].ledoff
);
2619 /********************\
2620 * Mac80211 functions *
2621 \********************/
2624 ath5k_tx(struct ieee80211_hw
*hw
, struct sk_buff
*skb
)
2626 struct ath5k_softc
*sc
= hw
->priv
;
2627 struct ath5k_buf
*bf
;
2628 struct ieee80211_tx_info
*info
= (void*) skb
->cb
;
2629 unsigned long flags
;
2633 ath5k_debug_dump_skb(sc
, skb
, "TX ", 1);
2635 if (sc
->opmode
== IEEE80211_IF_TYPE_MNTR
)
2636 ATH5K_DBG(sc
, ATH5K_DEBUG_XMIT
, "tx in monitor (scan?)\n");
2639 * the hardware expects the header padded to 4 byte boundaries
2640 * if this is not the case we add the padding after the header
2642 hdrlen
= ieee80211_get_hdrlen_from_skb(skb
);
2645 if (skb_headroom(skb
) < pad
) {
2646 ATH5K_ERR(sc
, "tx hdrlen not %%4: %d not enough"
2647 " headroom to pad %d\n", hdrlen
, pad
);
2651 memmove(skb
->data
, skb
->data
+pad
, hdrlen
);
2654 sc
->led_txrate
= ieee80211_get_tx_rate(hw
, info
)->hw_value
;
2656 spin_lock_irqsave(&sc
->txbuflock
, flags
);
2657 if (list_empty(&sc
->txbuf
)) {
2658 ATH5K_ERR(sc
, "no further txbuf available, dropping packet\n");
2659 spin_unlock_irqrestore(&sc
->txbuflock
, flags
);
2660 ieee80211_stop_queue(hw
, skb_get_queue_mapping(skb
));
2663 bf
= list_first_entry(&sc
->txbuf
, struct ath5k_buf
, list
);
2664 list_del(&bf
->list
);
2666 if (list_empty(&sc
->txbuf
))
2667 ieee80211_stop_queues(hw
);
2668 spin_unlock_irqrestore(&sc
->txbuflock
, flags
);
2672 if (ath5k_txbuf_setup(sc
, bf
)) {
2674 spin_lock_irqsave(&sc
->txbuflock
, flags
);
2675 list_add_tail(&bf
->list
, &sc
->txbuf
);
2677 spin_unlock_irqrestore(&sc
->txbuflock
, flags
);
2678 dev_kfree_skb_any(skb
);
2686 ath5k_reset(struct ieee80211_hw
*hw
)
2688 struct ath5k_softc
*sc
= hw
->priv
;
2689 struct ath5k_hw
*ah
= sc
->ah
;
2692 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "resetting\n");
2694 ath5k_hw_set_intr(ah
, 0);
2695 ath5k_txq_cleanup(sc
);
2698 ret
= ath5k_hw_reset(ah
, sc
->opmode
, sc
->curchan
, true);
2699 if (unlikely(ret
)) {
2700 ATH5K_ERR(sc
, "can't reset hardware (%d)\n", ret
);
2703 ath5k_hw_set_txpower_limit(sc
->ah
, 0);
2705 ret
= ath5k_rx_start(sc
);
2706 if (unlikely(ret
)) {
2707 ATH5K_ERR(sc
, "can't start recv logic\n");
2711 * We may be doing a reset in response to an ioctl
2712 * that changes the channel so update any state that
2713 * might change as a result.
2717 /* ath5k_chan_change(sc, c); */
2718 ath5k_beacon_config(sc
);
2719 /* intrs are started by ath5k_beacon_config */
2721 ieee80211_wake_queues(hw
);
2728 static int ath5k_start(struct ieee80211_hw
*hw
)
2730 return ath5k_init(hw
->priv
);
2733 static void ath5k_stop(struct ieee80211_hw
*hw
)
2735 ath5k_stop_hw(hw
->priv
);
2738 static int ath5k_add_interface(struct ieee80211_hw
*hw
,
2739 struct ieee80211_if_init_conf
*conf
)
2741 struct ath5k_softc
*sc
= hw
->priv
;
2744 mutex_lock(&sc
->lock
);
2750 sc
->vif
= conf
->vif
;
2752 switch (conf
->type
) {
2753 case IEEE80211_IF_TYPE_STA
:
2754 case IEEE80211_IF_TYPE_IBSS
:
2755 case IEEE80211_IF_TYPE_MNTR
:
2756 sc
->opmode
= conf
->type
;
2764 mutex_unlock(&sc
->lock
);
2769 ath5k_remove_interface(struct ieee80211_hw
*hw
,
2770 struct ieee80211_if_init_conf
*conf
)
2772 struct ath5k_softc
*sc
= hw
->priv
;
2774 mutex_lock(&sc
->lock
);
2775 if (sc
->vif
!= conf
->vif
)
2780 mutex_unlock(&sc
->lock
);
2784 * TODO: Phy disable/diversity etc
2787 ath5k_config(struct ieee80211_hw
*hw
,
2788 struct ieee80211_conf
*conf
)
2790 struct ath5k_softc
*sc
= hw
->priv
;
2792 sc
->bintval
= conf
->beacon_int
;
2793 sc
->power_level
= conf
->power_level
;
2795 return ath5k_chan_set(sc
, conf
->channel
);
2799 ath5k_config_interface(struct ieee80211_hw
*hw
, struct ieee80211_vif
*vif
,
2800 struct ieee80211_if_conf
*conf
)
2802 struct ath5k_softc
*sc
= hw
->priv
;
2803 struct ath5k_hw
*ah
= sc
->ah
;
2806 /* Set to a reasonable value. Note that this will
2807 * be set to mac80211's value at ath5k_config(). */
2809 mutex_lock(&sc
->lock
);
2810 if (sc
->vif
!= vif
) {
2815 /* Cache for later use during resets */
2816 memcpy(ah
->ah_bssid
, conf
->bssid
, ETH_ALEN
);
2817 /* XXX: assoc id is set to 0 for now, mac80211 doesn't have
2818 * a clean way of letting us retrieve this yet. */
2819 ath5k_hw_set_associd(ah
, ah
->ah_bssid
, 0);
2821 mutex_unlock(&sc
->lock
);
2823 return ath5k_reset(hw
);
2825 mutex_unlock(&sc
->lock
);
2829 #define SUPPORTED_FIF_FLAGS \
2830 FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \
2831 FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
2832 FIF_BCN_PRBRESP_PROMISC
2834 * o always accept unicast, broadcast, and multicast traffic
2835 * o multicast traffic for all BSSIDs will be enabled if mac80211
2837 * o maintain current state of phy ofdm or phy cck error reception.
2838 * If the hardware detects any of these type of errors then
2839 * ath5k_hw_get_rx_filter() will pass to us the respective
2840 * hardware filters to be able to receive these type of frames.
2841 * o probe request frames are accepted only when operating in
2842 * hostap, adhoc, or monitor modes
2843 * o enable promiscuous mode according to the interface state
2845 * - when operating in adhoc mode so the 802.11 layer creates
2846 * node table entries for peers,
2847 * - when operating in station mode for collecting rssi data when
2848 * the station is otherwise quiet, or
2851 static void ath5k_configure_filter(struct ieee80211_hw
*hw
,
2852 unsigned int changed_flags
,
2853 unsigned int *new_flags
,
2854 int mc_count
, struct dev_mc_list
*mclist
)
2856 struct ath5k_softc
*sc
= hw
->priv
;
2857 struct ath5k_hw
*ah
= sc
->ah
;
2858 u32 mfilt
[2], val
, rfilt
;
2865 /* Only deal with supported flags */
2866 changed_flags
&= SUPPORTED_FIF_FLAGS
;
2867 *new_flags
&= SUPPORTED_FIF_FLAGS
;
2869 /* If HW detects any phy or radar errors, leave those filters on.
2870 * Also, always enable Unicast, Broadcasts and Multicast
2871 * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
2872 rfilt
= (ath5k_hw_get_rx_filter(ah
) & (AR5K_RX_FILTER_PHYERR
)) |
2873 (AR5K_RX_FILTER_UCAST
| AR5K_RX_FILTER_BCAST
|
2874 AR5K_RX_FILTER_MCAST
);
2876 if (changed_flags
& (FIF_PROMISC_IN_BSS
| FIF_OTHER_BSS
)) {
2877 if (*new_flags
& FIF_PROMISC_IN_BSS
) {
2878 rfilt
|= AR5K_RX_FILTER_PROM
;
2879 __set_bit(ATH_STAT_PROMISC
, sc
->status
);
2882 __clear_bit(ATH_STAT_PROMISC
, sc
->status
);
2885 /* Note, AR5K_RX_FILTER_MCAST is already enabled */
2886 if (*new_flags
& FIF_ALLMULTI
) {
2890 for (i
= 0; i
< mc_count
; i
++) {
2893 /* calculate XOR of eight 6-bit values */
2894 val
= get_unaligned_le32(mclist
->dmi_addr
+ 0);
2895 pos
= (val
>> 18) ^ (val
>> 12) ^ (val
>> 6) ^ val
;
2896 val
= get_unaligned_le32(mclist
->dmi_addr
+ 3);
2897 pos
^= (val
>> 18) ^ (val
>> 12) ^ (val
>> 6) ^ val
;
2899 mfilt
[pos
/ 32] |= (1 << (pos
% 32));
2900 /* XXX: we might be able to just do this instead,
2901 * but not sure, needs testing, if we do use this we'd
2902 * neet to inform below to not reset the mcast */
2903 /* ath5k_hw_set_mcast_filterindex(ah,
2904 * mclist->dmi_addr[5]); */
2905 mclist
= mclist
->next
;
2909 /* This is the best we can do */
2910 if (*new_flags
& (FIF_FCSFAIL
| FIF_PLCPFAIL
))
2911 rfilt
|= AR5K_RX_FILTER_PHYERR
;
2913 /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
2914 * and probes for any BSSID, this needs testing */
2915 if (*new_flags
& FIF_BCN_PRBRESP_PROMISC
)
2916 rfilt
|= AR5K_RX_FILTER_BEACON
| AR5K_RX_FILTER_PROBEREQ
;
2918 /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
2919 * set we should only pass on control frames for this
2920 * station. This needs testing. I believe right now this
2921 * enables *all* control frames, which is OK.. but
2922 * but we should see if we can improve on granularity */
2923 if (*new_flags
& FIF_CONTROL
)
2924 rfilt
|= AR5K_RX_FILTER_CONTROL
;
2926 /* Additional settings per mode -- this is per ath5k */
2928 /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
2930 if (sc
->opmode
== IEEE80211_IF_TYPE_MNTR
)
2931 rfilt
|= AR5K_RX_FILTER_CONTROL
| AR5K_RX_FILTER_BEACON
|
2932 AR5K_RX_FILTER_PROBEREQ
| AR5K_RX_FILTER_PROM
;
2933 if (sc
->opmode
!= IEEE80211_IF_TYPE_STA
)
2934 rfilt
|= AR5K_RX_FILTER_PROBEREQ
;
2935 if (sc
->opmode
!= IEEE80211_IF_TYPE_AP
&&
2936 test_bit(ATH_STAT_PROMISC
, sc
->status
))
2937 rfilt
|= AR5K_RX_FILTER_PROM
;
2938 if (sc
->opmode
== IEEE80211_IF_TYPE_STA
||
2939 sc
->opmode
== IEEE80211_IF_TYPE_IBSS
) {
2940 rfilt
|= AR5K_RX_FILTER_BEACON
;
2944 ath5k_hw_set_rx_filter(ah
,rfilt
);
2946 /* Set multicast bits */
2947 ath5k_hw_set_mcast_filter(ah
, mfilt
[0], mfilt
[1]);
2948 /* Set the cached hw filter flags, this will alter actually
2950 sc
->filter_flags
= rfilt
;
2954 ath5k_set_key(struct ieee80211_hw
*hw
, enum set_key_cmd cmd
,
2955 const u8
*local_addr
, const u8
*addr
,
2956 struct ieee80211_key_conf
*key
)
2958 struct ath5k_softc
*sc
= hw
->priv
;
2963 /* XXX: fix hardware encryption, its not working. For now
2964 * allow software encryption */
2974 mutex_lock(&sc
->lock
);
2978 ret
= ath5k_hw_set_key(sc
->ah
, key
->keyidx
, key
, addr
);
2980 ATH5K_ERR(sc
, "can't set the key\n");
2983 __set_bit(key
->keyidx
, sc
->keymap
);
2984 key
->hw_key_idx
= key
->keyidx
;
2987 ath5k_hw_reset_key(sc
->ah
, key
->keyidx
);
2988 __clear_bit(key
->keyidx
, sc
->keymap
);
2996 mutex_unlock(&sc
->lock
);
3001 ath5k_get_stats(struct ieee80211_hw
*hw
,
3002 struct ieee80211_low_level_stats
*stats
)
3004 struct ath5k_softc
*sc
= hw
->priv
;
3005 struct ath5k_hw
*ah
= sc
->ah
;
3008 ath5k_hw_update_mib_counters(ah
, &sc
->ll_stats
);
3010 memcpy(stats
, &sc
->ll_stats
, sizeof(sc
->ll_stats
));
3016 ath5k_get_tx_stats(struct ieee80211_hw
*hw
,
3017 struct ieee80211_tx_queue_stats
*stats
)
3019 struct ath5k_softc
*sc
= hw
->priv
;
3021 memcpy(stats
, &sc
->tx_stats
, sizeof(sc
->tx_stats
));
3027 ath5k_get_tsf(struct ieee80211_hw
*hw
)
3029 struct ath5k_softc
*sc
= hw
->priv
;
3031 return ath5k_hw_get_tsf64(sc
->ah
);
3035 ath5k_reset_tsf(struct ieee80211_hw
*hw
)
3037 struct ath5k_softc
*sc
= hw
->priv
;
3040 * in IBSS mode we need to update the beacon timers too.
3041 * this will also reset the TSF if we call it with 0
3043 if (sc
->opmode
== IEEE80211_IF_TYPE_IBSS
)
3044 ath5k_beacon_update_timers(sc
, 0);
3046 ath5k_hw_reset_tsf(sc
->ah
);
3050 ath5k_beacon_update(struct ieee80211_hw
*hw
, struct sk_buff
*skb
)
3052 struct ath5k_softc
*sc
= hw
->priv
;
3055 ath5k_debug_dump_skb(sc
, skb
, "BC ", 1);
3057 mutex_lock(&sc
->lock
);
3059 if (sc
->opmode
!= IEEE80211_IF_TYPE_IBSS
) {
3064 ath5k_txbuf_free(sc
, sc
->bbuf
);
3065 sc
->bbuf
->skb
= skb
;
3066 ret
= ath5k_beacon_setup(sc
, sc
->bbuf
);
3068 sc
->bbuf
->skb
= NULL
;
3070 ath5k_beacon_config(sc
);
3073 mutex_unlock(&sc
->lock
);