projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
hwmon: (max6650) Add support for alarms
[deliverable/linux.git] / drivers / net / wireless / ath5k / eeprom.h
1 /*
2 * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
3 * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
4 *
5 * Permission to use, copy, modify, and distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 *
17 */
18
19 /*
20 * Common ar5xxx EEPROM data offsets (set these on AR5K_EEPROM_BASE)
21 */
22 #define AR5K_EEPROM_MAGIC 0x003d /* EEPROM Magic number */
23 #define AR5K_EEPROM_MAGIC_VALUE 0x5aa5 /* Default - found on EEPROM */
24 #define AR5K_EEPROM_MAGIC_5212 0x0000145c /* 5212 */
25 #define AR5K_EEPROM_MAGIC_5211 0x0000145b /* 5211 */
26 #define AR5K_EEPROM_MAGIC_5210 0x0000145a /* 5210 */
27
28 #define AR5K_EEPROM_IS_HB63 0x000b /* Talon detect */
29 #define AR5K_EEPROM_REG_DOMAIN 0x00bf /* EEPROM regdom */
30 #define AR5K_EEPROM_CHECKSUM 0x00c0 /* EEPROM checksum */
31 #define AR5K_EEPROM_INFO_BASE 0x00c0 /* EEPROM header */
32 #define AR5K_EEPROM_INFO_MAX (0x400 - AR5K_EEPROM_INFO_BASE)
33 #define AR5K_EEPROM_INFO_CKSUM 0xffff
34 #define AR5K_EEPROM_INFO(_n) (AR5K_EEPROM_INFO_BASE + (_n))
35
36 #define AR5K_EEPROM_VERSION AR5K_EEPROM_INFO(1) /* EEPROM Version */
37 #define AR5K_EEPROM_VERSION_3_0 0x3000 /* No idea what's going on before this version */
38 #define AR5K_EEPROM_VERSION_3_1 0x3001 /* ob/db values for 2Ghz (ar5211_rfregs) */
39 #define AR5K_EEPROM_VERSION_3_2 0x3002 /* different frequency representation (eeprom_bin2freq) */
40 #define AR5K_EEPROM_VERSION_3_3 0x3003 /* offsets changed, has 32 CTLs (see below) and ee_false_detect (eeprom_read_modes) */
41 #define AR5K_EEPROM_VERSION_3_4 0x3004 /* has ee_i_gain, ee_cck_ofdm_power_delta (eeprom_read_modes) */
42 #define AR5K_EEPROM_VERSION_4_0 0x4000 /* has ee_misc, ee_cal_pier, ee_turbo_max_power and ee_xr_power (eeprom_init) */
43 #define AR5K_EEPROM_VERSION_4_1 0x4001 /* has ee_margin_tx_rx (eeprom_init) */
44 #define AR5K_EEPROM_VERSION_4_2 0x4002 /* has ee_cck_ofdm_gain_delta (eeprom_init) */
45 #define AR5K_EEPROM_VERSION_4_3 0x4003 /* power calibration changes */
46 #define AR5K_EEPROM_VERSION_4_4 0x4004
47 #define AR5K_EEPROM_VERSION_4_5 0x4005
48 #define AR5K_EEPROM_VERSION_4_6 0x4006 /* has ee_scaled_cck_delta */
49 #define AR5K_EEPROM_VERSION_4_7 0x3007 /* 4007 ? */
50 #define AR5K_EEPROM_VERSION_4_9 0x4009 /* EAR futureproofing */
51 #define AR5K_EEPROM_VERSION_5_0 0x5000 /* Has 2413 PDADC calibration etc */
52 #define AR5K_EEPROM_VERSION_5_1 0x5001 /* Has capability values */
53 #define AR5K_EEPROM_VERSION_5_3 0x5003 /* Has spur mitigation tables */
54
55 #define AR5K_EEPROM_MODE_11A 0
56 #define AR5K_EEPROM_MODE_11B 1
57 #define AR5K_EEPROM_MODE_11G 2
58
59 #define AR5K_EEPROM_HDR AR5K_EEPROM_INFO(2) /* Header that contains the device caps */
60 #define AR5K_EEPROM_HDR_11A(_v) (((_v) >> AR5K_EEPROM_MODE_11A) & 0x1)
61 #define AR5K_EEPROM_HDR_11B(_v) (((_v) >> AR5K_EEPROM_MODE_11B) & 0x1)
62 #define AR5K_EEPROM_HDR_11G(_v) (((_v) >> AR5K_EEPROM_MODE_11G) & 0x1)
63 #define AR5K_EEPROM_HDR_T_2GHZ_DIS(_v) (((_v) >> 3) & 0x1) /* Disable turbo for 2Ghz (?) */
64 #define AR5K_EEPROM_HDR_T_5GHZ_DBM(_v) (((_v) >> 4) & 0x7f) /* Max turbo power for a/XR mode (eeprom_init) */
65 #define AR5K_EEPROM_HDR_DEVICE(_v) (((_v) >> 11) & 0x7)
66 #define AR5K_EEPROM_HDR_RFKILL(_v) (((_v) >> 14) & 0x1) /* Device has RFKill support */
67 #define AR5K_EEPROM_HDR_T_5GHZ_DIS(_v) (((_v) >> 15) & 0x1) /* Disable turbo for 5Ghz */
68
69 #define AR5K_EEPROM_RFKILL_GPIO_SEL 0x0000001c
70 #define AR5K_EEPROM_RFKILL_GPIO_SEL_S 2
71 #define AR5K_EEPROM_RFKILL_POLARITY 0x00000002
72 #define AR5K_EEPROM_RFKILL_POLARITY_S 1
73
74 /* Newer EEPROMs are using a different offset */
75 #define AR5K_EEPROM_OFF(_v, _v3_0, _v3_3) \
76 (((_v) >= AR5K_EEPROM_VERSION_3_3) ? _v3_3 : _v3_0)
77
78 #define AR5K_EEPROM_ANT_GAIN(_v) AR5K_EEPROM_OFF(_v, 0x00c4, 0x00c3)
79 #define AR5K_EEPROM_ANT_GAIN_5GHZ(_v) ((s8)(((_v) >> 8) & 0xff))
80 #define AR5K_EEPROM_ANT_GAIN_2GHZ(_v) ((s8)((_v) & 0xff))
81
82 /* Misc values available since EEPROM 4.0 */
83 #define AR5K_EEPROM_MISC0 AR5K_EEPROM_INFO(4)
84 #define AR5K_EEPROM_EARSTART(_v) ((_v) & 0xfff)
85 #define AR5K_EEPROM_HDR_XR2_DIS(_v) (((_v) >> 12) & 0x1)
86 #define AR5K_EEPROM_HDR_XR5_DIS(_v) (((_v) >> 13) & 0x1)
87 #define AR5K_EEPROM_EEMAP(_v) (((_v) >> 14) & 0x3)
88
89 #define AR5K_EEPROM_MISC1 AR5K_EEPROM_INFO(5)
90 #define AR5K_EEPROM_TARGET_PWRSTART(_v) ((_v) & 0xfff)
91 #define AR5K_EEPROM_HAS32KHZCRYSTAL(_v) (((_v) >> 14) & 0x1)
92 #define AR5K_EEPROM_HAS32KHZCRYSTAL_OLD(_v) (((_v) >> 15) & 0x1)
93
94 #define AR5K_EEPROM_MISC2 AR5K_EEPROM_INFO(6)
95 #define AR5K_EEPROM_EEP_FILE_VERSION(_v) (((_v) >> 8) & 0xff)
96 #define AR5K_EEPROM_EAR_FILE_VERSION(_v) ((_v) & 0xff)
97
98 #define AR5K_EEPROM_MISC3 AR5K_EEPROM_INFO(7)
99 #define AR5K_EEPROM_ART_BUILD_NUM(_v) (((_v) >> 10) & 0x3f)
100 #define AR5K_EEPROM_EAR_FILE_ID(_v) ((_v) & 0xff)
101
102 #define AR5K_EEPROM_MISC4 AR5K_EEPROM_INFO(8)
103 #define AR5K_EEPROM_CAL_DATA_START(_v) (((_v) >> 4) & 0xfff)
104 #define AR5K_EEPROM_MASK_R0(_v) (((_v) >> 2) & 0x3)
105 #define AR5K_EEPROM_MASK_R1(_v) ((_v) & 0x3)
106
107 #define AR5K_EEPROM_MISC5 AR5K_EEPROM_INFO(9)
108 #define AR5K_EEPROM_COMP_DIS(_v) ((_v) & 0x1)
109 #define AR5K_EEPROM_AES_DIS(_v) (((_v) >> 1) & 0x1)
110 #define AR5K_EEPROM_FF_DIS(_v) (((_v) >> 2) & 0x1)
111 #define AR5K_EEPROM_BURST_DIS(_v) (((_v) >> 3) & 0x1)
112 #define AR5K_EEPROM_MAX_QCU(_v) (((_v) >> 4) & 0xf)
113 #define AR5K_EEPROM_HEAVY_CLIP_EN(_v) (((_v) >> 8) & 0x1)
114 #define AR5K_EEPROM_KEY_CACHE_SIZE(_v) (((_v) >> 12) & 0xf)
115
116 #define AR5K_EEPROM_MISC6 AR5K_EEPROM_INFO(10)
117 #define AR5K_EEPROM_TX_CHAIN_DIS ((_v) & 0x8)
118 #define AR5K_EEPROM_RX_CHAIN_DIS (((_v) >> 3) & 0x8)
119 #define AR5K_EEPROM_FCC_MID_EN (((_v) >> 6) & 0x1)
120 #define AR5K_EEPROM_JAP_U1EVEN_EN (((_v) >> 7) & 0x1)
121 #define AR5K_EEPROM_JAP_U2_EN (((_v) >> 8) & 0x1)
122 #define AR5K_EEPROM_JAP_U1ODD_EN (((_v) >> 9) & 0x1)
123 #define AR5K_EEPROM_JAP_11A_NEW_EN (((_v) >> 10) & 0x1)
124
125 /* calibration settings */
126 #define AR5K_EEPROM_MODES_11A(_v) AR5K_EEPROM_OFF(_v, 0x00c5, 0x00d4)
127 #define AR5K_EEPROM_MODES_11B(_v) AR5K_EEPROM_OFF(_v, 0x00d0, 0x00f2)
128 #define AR5K_EEPROM_MODES_11G(_v) AR5K_EEPROM_OFF(_v, 0x00da, 0x010d)
129 #define AR5K_EEPROM_CTL(_v) AR5K_EEPROM_OFF(_v, 0x00e4, 0x0128) /* Conformance test limits */
130 #define AR5K_EEPROM_GROUPS_START(_v) AR5K_EEPROM_OFF(_v, 0x0100, 0x0150) /* Start of Groups */
131 #define AR5K_EEPROM_GROUP1_OFFSET 0x0
132 #define AR5K_EEPROM_GROUP2_OFFSET 0x5
133 #define AR5K_EEPROM_GROUP3_OFFSET 0x37
134 #define AR5K_EEPROM_GROUP4_OFFSET 0x46
135 #define AR5K_EEPROM_GROUP5_OFFSET 0x55
136 #define AR5K_EEPROM_GROUP6_OFFSET 0x65
137 #define AR5K_EEPROM_GROUP7_OFFSET 0x69
138 #define AR5K_EEPROM_GROUP8_OFFSET 0x6f
139
140 #define AR5K_EEPROM_TARGET_PWR_OFF_11A(_v) AR5K_EEPROM_OFF(_v, AR5K_EEPROM_GROUPS_START(_v) + \
141 AR5K_EEPROM_GROUP5_OFFSET, 0x0000)
142 #define AR5K_EEPROM_TARGET_PWR_OFF_11B(_v) AR5K_EEPROM_OFF(_v, AR5K_EEPROM_GROUPS_START(_v) + \
143 AR5K_EEPROM_GROUP6_OFFSET, 0x0010)
144 #define AR5K_EEPROM_TARGET_PWR_OFF_11G(_v) AR5K_EEPROM_OFF(_v, AR5K_EEPROM_GROUPS_START(_v) + \
145 AR5K_EEPROM_GROUP7_OFFSET, 0x0014)
146
147 /* [3.1 - 3.3] */
148 #define AR5K_EEPROM_OBDB0_2GHZ 0x00ec
149 #define AR5K_EEPROM_OBDB1_2GHZ 0x00ed
150
151 #define AR5K_EEPROM_PROTECT 0x003f /* EEPROM protect status */
152 #define AR5K_EEPROM_PROTECT_RD_0_31 0x0001 /* Read protection bit for offsets 0x0 - 0x1f */
153 #define AR5K_EEPROM_PROTECT_WR_0_31 0x0002 /* Write protection bit for offsets 0x0 - 0x1f */
154 #define AR5K_EEPROM_PROTECT_RD_32_63 0x0004 /* 0x20 - 0x3f */
155 #define AR5K_EEPROM_PROTECT_WR_32_63 0x0008
156 #define AR5K_EEPROM_PROTECT_RD_64_127 0x0010 /* 0x40 - 0x7f */
157 #define AR5K_EEPROM_PROTECT_WR_64_127 0x0020
158 #define AR5K_EEPROM_PROTECT_RD_128_191 0x0040 /* 0x80 - 0xbf (regdom) */
159 #define AR5K_EEPROM_PROTECT_WR_128_191 0x0080
160 #define AR5K_EEPROM_PROTECT_RD_192_207 0x0100 /* 0xc0 - 0xcf */
161 #define AR5K_EEPROM_PROTECT_WR_192_207 0x0200
162 #define AR5K_EEPROM_PROTECT_RD_208_223 0x0400 /* 0xd0 - 0xdf */
163 #define AR5K_EEPROM_PROTECT_WR_208_223 0x0800
164 #define AR5K_EEPROM_PROTECT_RD_224_239 0x1000 /* 0xe0 - 0xef */
165 #define AR5K_EEPROM_PROTECT_WR_224_239 0x2000
166 #define AR5K_EEPROM_PROTECT_RD_240_255 0x4000 /* 0xf0 - 0xff */
167 #define AR5K_EEPROM_PROTECT_WR_240_255 0x8000
168
169 /* Some EEPROM defines */
170 #define AR5K_EEPROM_EEP_SCALE 100
171 #define AR5K_EEPROM_EEP_DELTA 10
172 #define AR5K_EEPROM_N_MODES 3
173 #define AR5K_EEPROM_N_5GHZ_CHAN 10
174 #define AR5K_EEPROM_N_2GHZ_CHAN 3
175 #define AR5K_EEPROM_N_2GHZ_CHAN_2413 4
176 #define AR5K_EEPROM_N_2GHZ_CHAN_MAX 4
177 #define AR5K_EEPROM_MAX_CHAN 10
178 #define AR5K_EEPROM_N_PWR_POINTS_5111 11
179 #define AR5K_EEPROM_N_PCDAC 11
180 #define AR5K_EEPROM_N_PHASE_CAL 5
181 #define AR5K_EEPROM_N_TEST_FREQ 8
182 #define AR5K_EEPROM_N_EDGES 8
183 #define AR5K_EEPROM_N_INTERCEPTS 11
184 #define AR5K_EEPROM_FREQ_M(_v) AR5K_EEPROM_OFF(_v, 0x7f, 0xff)
185 #define AR5K_EEPROM_PCDAC_M 0x3f
186 #define AR5K_EEPROM_PCDAC_START 1
187 #define AR5K_EEPROM_PCDAC_STOP 63
188 #define AR5K_EEPROM_PCDAC_STEP 1
189 #define AR5K_EEPROM_NON_EDGE_M 0x40
190 #define AR5K_EEPROM_CHANNEL_POWER 8
191 #define AR5K_EEPROM_N_OBDB 4
192 #define AR5K_EEPROM_OBDB_DIS 0xffff
193 #define AR5K_EEPROM_CHANNEL_DIS 0xff
194 #define AR5K_EEPROM_SCALE_OC_DELTA(_x) (((_x) * 2) / 10)
195 #define AR5K_EEPROM_N_CTLS(_v) AR5K_EEPROM_OFF(_v, 16, 32)
196 #define AR5K_EEPROM_MAX_CTLS 32
197 #define AR5K_EEPROM_N_PD_CURVES 4
198 #define AR5K_EEPROM_N_XPD0_POINTS 4
199 #define AR5K_EEPROM_N_XPD3_POINTS 3
200 #define AR5K_EEPROM_N_PD_GAINS 4
201 #define AR5K_EEPROM_N_PD_POINTS 5
202 #define AR5K_EEPROM_N_INTERCEPT_10_2GHZ 35
203 #define AR5K_EEPROM_N_INTERCEPT_10_5GHZ 55
204 #define AR5K_EEPROM_POWER_M 0x3f
205 #define AR5K_EEPROM_POWER_MIN 0
206 #define AR5K_EEPROM_POWER_MAX 3150
207 #define AR5K_EEPROM_POWER_STEP 50
208 #define AR5K_EEPROM_POWER_TABLE_SIZE 64
209 #define AR5K_EEPROM_N_POWER_LOC_11B 4
210 #define AR5K_EEPROM_N_POWER_LOC_11G 6
211 #define AR5K_EEPROM_I_GAIN 10
212 #define AR5K_EEPROM_CCK_OFDM_DELTA 15
213 #define AR5K_EEPROM_N_IQ_CAL 2
214
215 #define AR5K_EEPROM_READ(_o, _v) do { \
216 ret = ath5k_hw_eeprom_read(ah, (_o), &(_v)); \
217 if (ret) \
218 return ret; \
219 } while (0)
220
221 #define AR5K_EEPROM_READ_HDR(_o, _v) \
222 AR5K_EEPROM_READ(_o, ah->ah_capabilities.cap_eeprom._v); \
223
224 enum ath5k_ant_setting {
225 AR5K_ANT_VARIABLE = 0, /* variable by programming */
226 AR5K_ANT_FIXED_A = 1, /* fixed to 11a frequencies */
227 AR5K_ANT_FIXED_B = 2, /* fixed to 11b frequencies */
228 AR5K_ANT_MAX = 3,
229 };
230
231 enum ath5k_ctl_mode {
232 AR5K_CTL_11A = 0,
233 AR5K_CTL_11B = 1,
234 AR5K_CTL_11G = 2,
235 AR5K_CTL_TURBO = 3,
236 AR5K_CTL_TURBOG = 4,
237 AR5K_CTL_2GHT20 = 5,
238 AR5K_CTL_5GHT20 = 6,
239 AR5K_CTL_2GHT40 = 7,
240 AR5K_CTL_5GHT40 = 8,
241 AR5K_CTL_MODE_M = 15,
242 };
243
244 /* Default CTL ids for the 3 main reg domains.
245 * Atheros only uses these by default but vendors
246 * can have up to 32 different CTLs for different
247 * scenarios. Note that theese values are ORed with
248 * the mode id (above) so we can have up to 24 CTL
249 * datasets out of these 3 main regdomains. That leaves
250 * 8 ids that can be used by vendors and since 0x20 is
251 * missing from HAL sources i guess this is the set of
252 * custom CTLs vendors can use. */
253 #define AR5K_CTL_FCC 0x10
254 #define AR5K_CTL_CUSTOM 0x20
255 #define AR5K_CTL_ETSI 0x30
256 #define AR5K_CTL_MKK 0x40
257
258 /* Indicates a CTL with only mode set and
259 * no reg domain mapping, such CTLs are used
260 * for world roaming domains or simply when
261 * a reg domain is not set */
262 #define AR5K_CTL_NO_REGDOMAIN 0xf0
263
264 /* Indicates an empty (invalid) CTL */
265 #define AR5K_CTL_NO_CTL 0xff
266
267 /* Per channel calibration data, used for power table setup */
268 struct ath5k_chan_pcal_info_rf5111 {
269 /* Power levels in half dbm units
270 * for one power curve. */
271 u8 pwr[AR5K_EEPROM_N_PWR_POINTS_5111];
272 /* PCDAC table steps
273 * for the above values */
274 u8 pcdac[AR5K_EEPROM_N_PWR_POINTS_5111];
275 /* Starting PCDAC step */
276 u8 pcdac_min;
277 /* Final PCDAC step */
278 u8 pcdac_max;
279 };
280
281 struct ath5k_chan_pcal_info_rf5112 {
282 /* Power levels in quarter dBm units
283 * for lower (0) and higher (3)
284 * level curves in 0.25dB units */
285 s8 pwr_x0[AR5K_EEPROM_N_XPD0_POINTS];
286 s8 pwr_x3[AR5K_EEPROM_N_XPD3_POINTS];
287 /* PCDAC table steps
288 * for the above values */
289 u8 pcdac_x0[AR5K_EEPROM_N_XPD0_POINTS];
290 u8 pcdac_x3[AR5K_EEPROM_N_XPD3_POINTS];
291 };
292
293 struct ath5k_chan_pcal_info_rf2413 {
294 /* Starting pwr/pddac values */
295 s8 pwr_i[AR5K_EEPROM_N_PD_GAINS];
296 u8 pddac_i[AR5K_EEPROM_N_PD_GAINS];
297 /* (pwr,pddac) points
298 * power levels in 0.5dB units */
299 s8 pwr[AR5K_EEPROM_N_PD_GAINS]
300 [AR5K_EEPROM_N_PD_POINTS];
301 u8 pddac[AR5K_EEPROM_N_PD_GAINS]
302 [AR5K_EEPROM_N_PD_POINTS];
303 };
304
305 enum ath5k_powertable_type {
306 AR5K_PWRTABLE_PWR_TO_PCDAC = 0,
307 AR5K_PWRTABLE_LINEAR_PCDAC = 1,
308 AR5K_PWRTABLE_PWR_TO_PDADC = 2,
309 };
310
311 struct ath5k_pdgain_info {
312 u8 pd_points;
313 u8 *pd_step;
314 /* Power values are in
315 * 0.25dB units */
316 s16 *pd_pwr;
317 };
318
319 struct ath5k_chan_pcal_info {
320 /* Frequency */
321 u16 freq;
322 /* Tx power boundaries */
323 s16 max_pwr;
324 s16 min_pwr;
325 union {
326 struct ath5k_chan_pcal_info_rf5111 rf5111_info;
327 struct ath5k_chan_pcal_info_rf5112 rf5112_info;
328 struct ath5k_chan_pcal_info_rf2413 rf2413_info;
329 };
330 /* Raw values used by phy code
331 * Curves are stored in order from lower
332 * gain to higher gain (max txpower -> min txpower) */
333 struct ath5k_pdgain_info *pd_curves;
334 };
335
336 /* Per rate calibration data for each mode,
337 * used for rate power table setup.
338 * Note: Values in 0.5dB units */
339 struct ath5k_rate_pcal_info {
340 u16 freq; /* Frequency */
341 /* Power level for 6-24Mbit/s rates or
342 * 1Mb rate */
343 u16 target_power_6to24;
344 /* Power level for 36Mbit rate or
345 * 2Mb rate */
346 u16 target_power_36;
347 /* Power level for 48Mbit rate or
348 * 5.5Mbit rate */
349 u16 target_power_48;
350 /* Power level for 54Mbit rate or
351 * 11Mbit rate */
352 u16 target_power_54;
353 };
354
355 /* Power edges for conformance test limits */
356 struct ath5k_edge_power {
357 u16 freq;
358 u16 edge; /* in half dBm */
359 bool flag;
360 };
361
362 /* EEPROM calibration data */
363 struct ath5k_eeprom_info {
364
365 /* Header information */
366 u16 ee_magic;
367 u16 ee_protect;
368 u16 ee_regdomain;
369 u16 ee_version;
370 u16 ee_header;
371 u16 ee_ant_gain;
372 u16 ee_misc0;
373 u16 ee_misc1;
374 u16 ee_misc2;
375 u16 ee_misc3;
376 u16 ee_misc4;
377 u16 ee_misc5;
378 u16 ee_misc6;
379 u16 ee_cck_ofdm_gain_delta;
380 u16 ee_cck_ofdm_power_delta;
381 u16 ee_scaled_cck_delta;
382
383 /* RF Calibration settings (reset, rfregs) */
384 u16 ee_i_cal[AR5K_EEPROM_N_MODES];
385 u16 ee_q_cal[AR5K_EEPROM_N_MODES];
386 u16 ee_fixed_bias[AR5K_EEPROM_N_MODES];
387 u16 ee_turbo_max_power[AR5K_EEPROM_N_MODES];
388 u16 ee_xr_power[AR5K_EEPROM_N_MODES];
389 u16 ee_switch_settling[AR5K_EEPROM_N_MODES];
390 u16 ee_atn_tx_rx[AR5K_EEPROM_N_MODES];
391 u16 ee_ant_control[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_PCDAC];
392 u16 ee_ob[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_OBDB];
393 u16 ee_db[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_OBDB];
394 u16 ee_tx_end2xlna_enable[AR5K_EEPROM_N_MODES];
395 u16 ee_tx_end2xpa_disable[AR5K_EEPROM_N_MODES];
396 u16 ee_tx_frm2xpa_enable[AR5K_EEPROM_N_MODES];
397 u16 ee_thr_62[AR5K_EEPROM_N_MODES];
398 u16 ee_xlna_gain[AR5K_EEPROM_N_MODES];
399 u16 ee_xpd[AR5K_EEPROM_N_MODES];
400 u16 ee_x_gain[AR5K_EEPROM_N_MODES];
401 u16 ee_i_gain[AR5K_EEPROM_N_MODES];
402 u16 ee_margin_tx_rx[AR5K_EEPROM_N_MODES];
403 u16 ee_switch_settling_turbo[AR5K_EEPROM_N_MODES];
404 u16 ee_margin_tx_rx_turbo[AR5K_EEPROM_N_MODES];
405 u16 ee_atn_tx_rx_turbo[AR5K_EEPROM_N_MODES];
406
407 /* Power calibration data */
408 u16 ee_false_detect[AR5K_EEPROM_N_MODES];
409
410 /* Number of pd gain curves per mode */
411 u8 ee_pd_gains[AR5K_EEPROM_N_MODES];
412 /* Back mapping pdcurve number -> pdcurve index in pd->pd_curves */
413 u8 ee_pdc_to_idx[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_PD_GAINS];
414
415 u8 ee_n_piers[AR5K_EEPROM_N_MODES];
416 struct ath5k_chan_pcal_info ee_pwr_cal_a[AR5K_EEPROM_N_5GHZ_CHAN];
417 struct ath5k_chan_pcal_info ee_pwr_cal_b[AR5K_EEPROM_N_2GHZ_CHAN_MAX];
418 struct ath5k_chan_pcal_info ee_pwr_cal_g[AR5K_EEPROM_N_2GHZ_CHAN_MAX];
419
420 /* Per rate target power levels */
421 u8 ee_rate_target_pwr_num[AR5K_EEPROM_N_MODES];
422 struct ath5k_rate_pcal_info ee_rate_tpwr_a[AR5K_EEPROM_N_5GHZ_CHAN];
423 struct ath5k_rate_pcal_info ee_rate_tpwr_b[AR5K_EEPROM_N_2GHZ_CHAN_MAX];
424 struct ath5k_rate_pcal_info ee_rate_tpwr_g[AR5K_EEPROM_N_2GHZ_CHAN_MAX];
425
426 /* Conformance test limits (Unused) */
427 u8 ee_ctls;
428 u8 ee_ctl[AR5K_EEPROM_MAX_CTLS];
429 struct ath5k_edge_power ee_ctl_pwr[AR5K_EEPROM_N_EDGES * AR5K_EEPROM_MAX_CTLS];
430
431 /* Noise Floor Calibration settings */
432 s16 ee_noise_floor_thr[AR5K_EEPROM_N_MODES];
433 s8 ee_adc_desired_size[AR5K_EEPROM_N_MODES];
434 s8 ee_pga_desired_size[AR5K_EEPROM_N_MODES];
435 s8 ee_adc_desired_size_turbo[AR5K_EEPROM_N_MODES];
436 s8 ee_pga_desired_size_turbo[AR5K_EEPROM_N_MODES];
437 s8 ee_pd_gain_overlap;
438
439 u32 ee_antenna[AR5K_EEPROM_N_MODES][AR5K_ANT_MAX];
440 };
441
Linux kernel - Deliverables
This page took 0.040828 seconds and 6 git commands to generate.