4 * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org>
5 * Copyright (c) 2006-2009 Nick Kossifidis <mickflemm@gmail.com>
6 * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com>
7 * Copyright (c) 2008-2009 Felix Fietkau <nbd@openwrt.org>
9 * Permission to use, copy, modify, and distribute this software for any
10 * purpose with or without fee is hereby granted, provided that the above
11 * copyright notice and this permission notice appear in all copies.
13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
25 #include <linux/delay.h>
34 * Used to modify RF Banks before writing them to AR5K_RF_BUFFER
36 static unsigned int ath5k_hw_rfb_op(struct ath5k_hw
*ah
,
37 const struct ath5k_rf_reg
*rf_regs
,
38 u32 val
, u8 reg_id
, bool set
)
40 const struct ath5k_rf_reg
*rfreg
= NULL
;
41 u8 offset
, bank
, num_bits
, col
, position
;
43 u32 mask
, data
, last_bit
, bits_shifted
, first_bit
;
49 rfb
= ah
->ah_rf_banks
;
51 for (i
= 0; i
< ah
->ah_rf_regs_count
; i
++) {
52 if (rf_regs
[i
].index
== reg_id
) {
58 if (rfb
== NULL
|| rfreg
== NULL
) {
59 ATH5K_PRINTF("Rf register not found!\n");
60 /* should not happen */
65 num_bits
= rfreg
->field
.len
;
66 first_bit
= rfreg
->field
.pos
;
67 col
= rfreg
->field
.col
;
69 /* first_bit is an offset from bank's
70 * start. Since we have all banks on
71 * the same array, we use this offset
72 * to mark each bank's start */
73 offset
= ah
->ah_offset
[bank
];
76 if (!(col
<= 3 && num_bits
<= 32 && first_bit
+ num_bits
<= 319)) {
77 ATH5K_PRINTF("invalid values at offset %u\n", offset
);
81 entry
= ((first_bit
- 1) / 8) + offset
;
82 position
= (first_bit
- 1) % 8;
85 data
= ath5k_hw_bitswap(val
, num_bits
);
87 for (bits_shifted
= 0, bits_left
= num_bits
; bits_left
> 0;
88 position
= 0, entry
++) {
90 last_bit
= (position
+ bits_left
> 8) ? 8 :
93 mask
= (((1 << last_bit
) - 1) ^ ((1 << position
) - 1)) <<
98 rfb
[entry
] |= ((data
<< position
) << (col
* 8)) & mask
;
99 data
>>= (8 - position
);
101 data
|= (((rfb
[entry
] & mask
) >> (col
* 8)) >> position
)
103 bits_shifted
+= last_bit
- position
;
106 bits_left
-= 8 - position
;
109 data
= set
? 1 : ath5k_hw_bitswap(data
, num_bits
);
114 /**********************\
115 * RF Gain optimization *
116 \**********************/
119 * This code is used to optimize rf gain on different environments
120 * (temprature mostly) based on feedback from a power detector.
122 * It's only used on RF5111 and RF5112, later RF chips seem to have
123 * auto adjustment on hw -notice they have a much smaller BANK 7 and
124 * no gain optimization ladder-.
126 * For more infos check out this patent doc
127 * http://www.freepatentsonline.com/7400691.html
129 * This paper describes power drops as seen on the receiver due to
131 * http://www.cnri.dit.ie/publications/ICT08%20-%20Practical%20Issues
132 * %20of%20Power%20Control.pdf
134 * And this is the MadWiFi bug entry related to the above
135 * http://madwifi-project.org/ticket/1659
136 * with various measurements and diagrams
138 * TODO: Deal with power drops due to probes by setting an apropriate
139 * tx power on the probe packets ! Make this part of the calibration process.
142 /* Initialize ah_gain durring attach */
143 int ath5k_hw_rfgain_opt_init(struct ath5k_hw
*ah
)
145 /* Initialize the gain optimization values */
146 switch (ah
->ah_radio
) {
148 ah
->ah_gain
.g_step_idx
= rfgain_opt_5111
.go_default
;
149 ah
->ah_gain
.g_low
= 20;
150 ah
->ah_gain
.g_high
= 35;
151 ah
->ah_gain
.g_state
= AR5K_RFGAIN_ACTIVE
;
154 ah
->ah_gain
.g_step_idx
= rfgain_opt_5112
.go_default
;
155 ah
->ah_gain
.g_low
= 20;
156 ah
->ah_gain
.g_high
= 85;
157 ah
->ah_gain
.g_state
= AR5K_RFGAIN_ACTIVE
;
166 /* Schedule a gain probe check on the next transmited packet.
167 * That means our next packet is going to be sent with lower
168 * tx power and a Peak to Average Power Detector (PAPD) will try
169 * to measure the gain.
171 * TODO: Use propper tx power setting for the probe packet so
172 * that we don't observe a serious power drop on the receiver
174 * XXX: How about forcing a tx packet (bypassing PCU arbitrator etc)
175 * just after we enable the probe so that we don't mess with
176 * standard traffic ? Maybe it's time to use sw interrupts and
177 * a probe tasklet !!!
179 static void ath5k_hw_request_rfgain_probe(struct ath5k_hw
*ah
)
182 /* Skip if gain calibration is inactive or
183 * we already handle a probe request */
184 if (ah
->ah_gain
.g_state
!= AR5K_RFGAIN_ACTIVE
)
187 /* Send the packet with 2dB below max power as
188 * patent doc suggest */
189 ath5k_hw_reg_write(ah
, AR5K_REG_SM(ah
->ah_txpower
.txp_max_pwr
- 4,
190 AR5K_PHY_PAPD_PROBE_TXPOWER
) |
191 AR5K_PHY_PAPD_PROBE_TX_NEXT
, AR5K_PHY_PAPD_PROBE
);
193 ah
->ah_gain
.g_state
= AR5K_RFGAIN_READ_REQUESTED
;
197 /* Calculate gain_F measurement correction
198 * based on the current step for RF5112 rev. 2 */
199 static u32
ath5k_hw_rf_gainf_corr(struct ath5k_hw
*ah
)
203 const struct ath5k_gain_opt
*go
;
204 const struct ath5k_gain_opt_step
*g_step
;
205 const struct ath5k_rf_reg
*rf_regs
;
207 /* Only RF5112 Rev. 2 supports it */
208 if ((ah
->ah_radio
!= AR5K_RF5112
) ||
209 (ah
->ah_radio_5ghz_revision
<= AR5K_SREV_RAD_5112A
))
212 go
= &rfgain_opt_5112
;
213 rf_regs
= rf_regs_5112a
;
214 ah
->ah_rf_regs_count
= ARRAY_SIZE(rf_regs_5112a
);
216 g_step
= &go
->go_step
[ah
->ah_gain
.g_step_idx
];
218 if (ah
->ah_rf_banks
== NULL
)
221 rf
= ah
->ah_rf_banks
;
222 ah
->ah_gain
.g_f_corr
= 0;
224 /* No VGA (Variable Gain Amplifier) override, skip */
225 if (ath5k_hw_rfb_op(ah
, rf_regs
, 0, AR5K_RF_MIXVGA_OVR
, false) != 1)
228 /* Mix gain stepping */
229 step
= ath5k_hw_rfb_op(ah
, rf_regs
, 0, AR5K_RF_MIXGAIN_STEP
, false);
231 /* Mix gain override */
232 mix
= g_step
->gos_param
[0];
236 ah
->ah_gain
.g_f_corr
= step
* 2;
239 ah
->ah_gain
.g_f_corr
= (step
- 5) * 2;
242 ah
->ah_gain
.g_f_corr
= step
;
245 ah
->ah_gain
.g_f_corr
= 0;
249 return ah
->ah_gain
.g_f_corr
;
252 /* Check if current gain_F measurement is in the range of our
253 * power detector windows. If we get a measurement outside range
254 * we know it's not accurate (detectors can't measure anything outside
255 * their detection window) so we must ignore it */
256 static bool ath5k_hw_rf_check_gainf_readback(struct ath5k_hw
*ah
)
258 const struct ath5k_rf_reg
*rf_regs
;
259 u32 step
, mix_ovr
, level
[4];
262 if (ah
->ah_rf_banks
== NULL
)
265 rf
= ah
->ah_rf_banks
;
267 if (ah
->ah_radio
== AR5K_RF5111
) {
269 rf_regs
= rf_regs_5111
;
270 ah
->ah_rf_regs_count
= ARRAY_SIZE(rf_regs_5111
);
272 step
= ath5k_hw_rfb_op(ah
, rf_regs
, 0, AR5K_RF_RFGAIN_STEP
,
276 level
[1] = (step
== 63) ? 50 : step
+ 4;
277 level
[2] = (step
!= 63) ? 64 : level
[0];
278 level
[3] = level
[2] + 50 ;
280 ah
->ah_gain
.g_high
= level
[3] -
281 (step
== 63 ? AR5K_GAIN_DYN_ADJUST_HI_MARGIN
: -5);
282 ah
->ah_gain
.g_low
= level
[0] +
283 (step
== 63 ? AR5K_GAIN_DYN_ADJUST_LO_MARGIN
: 0);
286 rf_regs
= rf_regs_5112
;
287 ah
->ah_rf_regs_count
= ARRAY_SIZE(rf_regs_5112
);
289 mix_ovr
= ath5k_hw_rfb_op(ah
, rf_regs
, 0, AR5K_RF_MIXVGA_OVR
,
292 level
[0] = level
[2] = 0;
295 level
[1] = level
[3] = 83;
297 level
[1] = level
[3] = 107;
298 ah
->ah_gain
.g_high
= 55;
302 return (ah
->ah_gain
.g_current
>= level
[0] &&
303 ah
->ah_gain
.g_current
<= level
[1]) ||
304 (ah
->ah_gain
.g_current
>= level
[2] &&
305 ah
->ah_gain
.g_current
<= level
[3]);
308 /* Perform gain_F adjustment by choosing the right set
309 * of parameters from rf gain optimization ladder */
310 static s8
ath5k_hw_rf_gainf_adjust(struct ath5k_hw
*ah
)
312 const struct ath5k_gain_opt
*go
;
313 const struct ath5k_gain_opt_step
*g_step
;
316 switch (ah
->ah_radio
) {
318 go
= &rfgain_opt_5111
;
321 go
= &rfgain_opt_5112
;
327 g_step
= &go
->go_step
[ah
->ah_gain
.g_step_idx
];
329 if (ah
->ah_gain
.g_current
>= ah
->ah_gain
.g_high
) {
331 /* Reached maximum */
332 if (ah
->ah_gain
.g_step_idx
== 0)
335 for (ah
->ah_gain
.g_target
= ah
->ah_gain
.g_current
;
336 ah
->ah_gain
.g_target
>= ah
->ah_gain
.g_high
&&
337 ah
->ah_gain
.g_step_idx
> 0;
338 g_step
= &go
->go_step
[ah
->ah_gain
.g_step_idx
])
339 ah
->ah_gain
.g_target
-= 2 *
340 (go
->go_step
[--(ah
->ah_gain
.g_step_idx
)].gos_gain
-
347 if (ah
->ah_gain
.g_current
<= ah
->ah_gain
.g_low
) {
349 /* Reached minimum */
350 if (ah
->ah_gain
.g_step_idx
== (go
->go_steps_count
- 1))
353 for (ah
->ah_gain
.g_target
= ah
->ah_gain
.g_current
;
354 ah
->ah_gain
.g_target
<= ah
->ah_gain
.g_low
&&
355 ah
->ah_gain
.g_step_idx
< go
->go_steps_count
-1;
356 g_step
= &go
->go_step
[ah
->ah_gain
.g_step_idx
])
357 ah
->ah_gain
.g_target
-= 2 *
358 (go
->go_step
[++ah
->ah_gain
.g_step_idx
].gos_gain
-
366 ATH5K_DBG(ah
->ah_sc
, ATH5K_DEBUG_CALIBRATE
,
367 "ret %d, gain step %u, current gain %u, target gain %u\n",
368 ret
, ah
->ah_gain
.g_step_idx
, ah
->ah_gain
.g_current
,
369 ah
->ah_gain
.g_target
);
374 /* Main callback for thermal rf gain calibration engine
375 * Check for a new gain reading and schedule an adjustment
378 * TODO: Use sw interrupt to schedule reset if gain_F needs
380 enum ath5k_rfgain
ath5k_hw_gainf_calibrate(struct ath5k_hw
*ah
)
383 struct ath5k_eeprom_info
*ee
= &ah
->ah_capabilities
.cap_eeprom
;
385 ATH5K_TRACE(ah
->ah_sc
);
387 if (ah
->ah_rf_banks
== NULL
||
388 ah
->ah_gain
.g_state
== AR5K_RFGAIN_INACTIVE
)
389 return AR5K_RFGAIN_INACTIVE
;
391 /* No check requested, either engine is inactive
392 * or an adjustment is already requested */
393 if (ah
->ah_gain
.g_state
!= AR5K_RFGAIN_READ_REQUESTED
)
396 /* Read the PAPD (Peak to Average Power Detector)
398 data
= ath5k_hw_reg_read(ah
, AR5K_PHY_PAPD_PROBE
);
400 /* No probe is scheduled, read gain_F measurement */
401 if (!(data
& AR5K_PHY_PAPD_PROBE_TX_NEXT
)) {
402 ah
->ah_gain
.g_current
= data
>> AR5K_PHY_PAPD_PROBE_GAINF_S
;
403 type
= AR5K_REG_MS(data
, AR5K_PHY_PAPD_PROBE_TYPE
);
405 /* If tx packet is CCK correct the gain_F measurement
406 * by cck ofdm gain delta */
407 if (type
== AR5K_PHY_PAPD_PROBE_TYPE_CCK
) {
408 if (ah
->ah_radio_5ghz_revision
>= AR5K_SREV_RAD_5112A
)
409 ah
->ah_gain
.g_current
+=
410 ee
->ee_cck_ofdm_gain_delta
;
412 ah
->ah_gain
.g_current
+=
413 AR5K_GAIN_CCK_PROBE_CORR
;
416 /* Further correct gain_F measurement for
418 if (ah
->ah_radio_5ghz_revision
>= AR5K_SREV_RAD_5112A
) {
419 ath5k_hw_rf_gainf_corr(ah
);
420 ah
->ah_gain
.g_current
=
421 ah
->ah_gain
.g_current
>= ah
->ah_gain
.g_f_corr
?
422 (ah
->ah_gain
.g_current
-ah
->ah_gain
.g_f_corr
) :
426 /* Check if measurement is ok and if we need
427 * to adjust gain, schedule a gain adjustment,
428 * else switch back to the acive state */
429 if (ath5k_hw_rf_check_gainf_readback(ah
) &&
430 AR5K_GAIN_CHECK_ADJUST(&ah
->ah_gain
) &&
431 ath5k_hw_rf_gainf_adjust(ah
)) {
432 ah
->ah_gain
.g_state
= AR5K_RFGAIN_NEED_CHANGE
;
434 ah
->ah_gain
.g_state
= AR5K_RFGAIN_ACTIVE
;
439 return ah
->ah_gain
.g_state
;
442 /* Write initial rf gain table to set the RF sensitivity
443 * this one works on all RF chips and has nothing to do
444 * with gain_F calibration */
445 int ath5k_hw_rfgain_init(struct ath5k_hw
*ah
, unsigned int freq
)
447 const struct ath5k_ini_rfgain
*ath5k_rfg
;
448 unsigned int i
, size
;
450 switch (ah
->ah_radio
) {
452 ath5k_rfg
= rfgain_5111
;
453 size
= ARRAY_SIZE(rfgain_5111
);
456 ath5k_rfg
= rfgain_5112
;
457 size
= ARRAY_SIZE(rfgain_5112
);
460 ath5k_rfg
= rfgain_2413
;
461 size
= ARRAY_SIZE(rfgain_2413
);
464 ath5k_rfg
= rfgain_2316
;
465 size
= ARRAY_SIZE(rfgain_2316
);
468 ath5k_rfg
= rfgain_5413
;
469 size
= ARRAY_SIZE(rfgain_5413
);
473 ath5k_rfg
= rfgain_2425
;
474 size
= ARRAY_SIZE(rfgain_2425
);
481 case AR5K_INI_RFGAIN_2GHZ
:
482 case AR5K_INI_RFGAIN_5GHZ
:
488 for (i
= 0; i
< size
; i
++) {
490 ath5k_hw_reg_write(ah
, ath5k_rfg
[i
].rfg_value
[freq
],
491 (u32
)ath5k_rfg
[i
].rfg_register
);
499 /********************\
500 * RF Registers setup *
501 \********************/
505 * Setup RF registers by writing rf buffer on hw
507 int ath5k_hw_rfregs_init(struct ath5k_hw
*ah
, struct ieee80211_channel
*channel
,
510 const struct ath5k_rf_reg
*rf_regs
;
511 const struct ath5k_ini_rfbuffer
*ini_rfb
;
512 const struct ath5k_gain_opt
*go
= NULL
;
513 const struct ath5k_gain_opt_step
*g_step
;
514 struct ath5k_eeprom_info
*ee
= &ah
->ah_capabilities
.cap_eeprom
;
517 int i
, obdb
= -1, bank
= -1;
519 switch (ah
->ah_radio
) {
521 rf_regs
= rf_regs_5111
;
522 ah
->ah_rf_regs_count
= ARRAY_SIZE(rf_regs_5111
);
524 ah
->ah_rf_banks_size
= ARRAY_SIZE(rfb_5111
);
525 go
= &rfgain_opt_5111
;
528 if (ah
->ah_radio_5ghz_revision
>= AR5K_SREV_RAD_5112A
) {
529 rf_regs
= rf_regs_5112a
;
530 ah
->ah_rf_regs_count
= ARRAY_SIZE(rf_regs_5112a
);
532 ah
->ah_rf_banks_size
= ARRAY_SIZE(rfb_5112a
);
534 rf_regs
= rf_regs_5112
;
535 ah
->ah_rf_regs_count
= ARRAY_SIZE(rf_regs_5112
);
537 ah
->ah_rf_banks_size
= ARRAY_SIZE(rfb_5112
);
539 go
= &rfgain_opt_5112
;
542 rf_regs
= rf_regs_2413
;
543 ah
->ah_rf_regs_count
= ARRAY_SIZE(rf_regs_2413
);
545 ah
->ah_rf_banks_size
= ARRAY_SIZE(rfb_2413
);
548 rf_regs
= rf_regs_2316
;
549 ah
->ah_rf_regs_count
= ARRAY_SIZE(rf_regs_2316
);
551 ah
->ah_rf_banks_size
= ARRAY_SIZE(rfb_2316
);
554 rf_regs
= rf_regs_5413
;
555 ah
->ah_rf_regs_count
= ARRAY_SIZE(rf_regs_5413
);
557 ah
->ah_rf_banks_size
= ARRAY_SIZE(rfb_5413
);
560 rf_regs
= rf_regs_2425
;
561 ah
->ah_rf_regs_count
= ARRAY_SIZE(rf_regs_2425
);
563 ah
->ah_rf_banks_size
= ARRAY_SIZE(rfb_2317
);
566 rf_regs
= rf_regs_2425
;
567 ah
->ah_rf_regs_count
= ARRAY_SIZE(rf_regs_2425
);
568 if (ah
->ah_mac_srev
< AR5K_SREV_AR2417
) {
570 ah
->ah_rf_banks_size
= ARRAY_SIZE(rfb_2425
);
573 ah
->ah_rf_banks_size
= ARRAY_SIZE(rfb_2417
);
580 /* If it's the first time we set rf buffer, allocate
581 * ah->ah_rf_banks based on ah->ah_rf_banks_size
583 if (ah
->ah_rf_banks
== NULL
) {
584 ah
->ah_rf_banks
= kmalloc(sizeof(u32
) * ah
->ah_rf_banks_size
,
586 if (ah
->ah_rf_banks
== NULL
) {
587 ATH5K_ERR(ah
->ah_sc
, "out of memory\n");
592 /* Copy values to modify them */
593 rfb
= ah
->ah_rf_banks
;
595 for (i
= 0; i
< ah
->ah_rf_banks_size
; i
++) {
596 if (ini_rfb
[i
].rfb_bank
>= AR5K_MAX_RF_BANKS
) {
597 ATH5K_ERR(ah
->ah_sc
, "invalid bank\n");
601 /* Bank changed, write down the offset */
602 if (bank
!= ini_rfb
[i
].rfb_bank
) {
603 bank
= ini_rfb
[i
].rfb_bank
;
604 ah
->ah_offset
[bank
] = i
;
607 rfb
[i
] = ini_rfb
[i
].rfb_mode_data
[mode
];
610 /* Set Output and Driver bias current (OB/DB) */
611 if (channel
->hw_value
& CHANNEL_2GHZ
) {
613 if (channel
->hw_value
& CHANNEL_CCK
)
614 ee_mode
= AR5K_EEPROM_MODE_11B
;
616 ee_mode
= AR5K_EEPROM_MODE_11G
;
618 /* For RF511X/RF211X combination we
619 * use b_OB and b_DB parameters stored
620 * in eeprom on ee->ee_ob[ee_mode][0]
622 * For all other chips we use OB/DB for 2Ghz
623 * stored in the b/g modal section just like
624 * 802.11a on ee->ee_ob[ee_mode][1] */
625 if ((ah
->ah_radio
== AR5K_RF5111
) ||
626 (ah
->ah_radio
== AR5K_RF5112
))
631 ath5k_hw_rfb_op(ah
, rf_regs
, ee
->ee_ob
[ee_mode
][obdb
],
632 AR5K_RF_OB_2GHZ
, true);
634 ath5k_hw_rfb_op(ah
, rf_regs
, ee
->ee_db
[ee_mode
][obdb
],
635 AR5K_RF_DB_2GHZ
, true);
637 /* RF5111 always needs OB/DB for 5GHz, even if we use 2GHz */
638 } else if ((channel
->hw_value
& CHANNEL_5GHZ
) ||
639 (ah
->ah_radio
== AR5K_RF5111
)) {
641 /* For 11a, Turbo and XR we need to choose
642 * OB/DB based on frequency range */
643 ee_mode
= AR5K_EEPROM_MODE_11A
;
644 obdb
= channel
->center_freq
>= 5725 ? 3 :
645 (channel
->center_freq
>= 5500 ? 2 :
646 (channel
->center_freq
>= 5260 ? 1 :
647 (channel
->center_freq
> 4000 ? 0 : -1)));
652 ath5k_hw_rfb_op(ah
, rf_regs
, ee
->ee_ob
[ee_mode
][obdb
],
653 AR5K_RF_OB_5GHZ
, true);
655 ath5k_hw_rfb_op(ah
, rf_regs
, ee
->ee_db
[ee_mode
][obdb
],
656 AR5K_RF_DB_5GHZ
, true);
659 g_step
= &go
->go_step
[ah
->ah_gain
.g_step_idx
];
661 /* Bank Modifications (chip-specific) */
662 if (ah
->ah_radio
== AR5K_RF5111
) {
664 /* Set gain_F settings according to current step */
665 if (channel
->hw_value
& CHANNEL_OFDM
) {
667 AR5K_REG_WRITE_BITS(ah
, AR5K_PHY_FRAME_CTL
,
668 AR5K_PHY_FRAME_CTL_TX_CLIP
,
669 g_step
->gos_param
[0]);
671 ath5k_hw_rfb_op(ah
, rf_regs
, g_step
->gos_param
[1],
672 AR5K_RF_PWD_90
, true);
674 ath5k_hw_rfb_op(ah
, rf_regs
, g_step
->gos_param
[2],
675 AR5K_RF_PWD_84
, true);
677 ath5k_hw_rfb_op(ah
, rf_regs
, g_step
->gos_param
[3],
678 AR5K_RF_RFGAIN_SEL
, true);
680 /* We programmed gain_F parameters, switch back
682 ah
->ah_gain
.g_state
= AR5K_RFGAIN_ACTIVE
;
688 ath5k_hw_rfb_op(ah
, rf_regs
, !ee
->ee_xpd
[ee_mode
],
689 AR5K_RF_PWD_XPD
, true);
691 ath5k_hw_rfb_op(ah
, rf_regs
, ee
->ee_x_gain
[ee_mode
],
692 AR5K_RF_XPD_GAIN
, true);
694 ath5k_hw_rfb_op(ah
, rf_regs
, ee
->ee_i_gain
[ee_mode
],
695 AR5K_RF_GAIN_I
, true);
697 ath5k_hw_rfb_op(ah
, rf_regs
, ee
->ee_xpd
[ee_mode
],
698 AR5K_RF_PLO_SEL
, true);
700 /* TODO: Half/quarter channel support */
703 if (ah
->ah_radio
== AR5K_RF5112
) {
705 /* Set gain_F settings according to current step */
706 if (channel
->hw_value
& CHANNEL_OFDM
) {
708 ath5k_hw_rfb_op(ah
, rf_regs
, g_step
->gos_param
[0],
709 AR5K_RF_MIXGAIN_OVR
, true);
711 ath5k_hw_rfb_op(ah
, rf_regs
, g_step
->gos_param
[1],
712 AR5K_RF_PWD_138
, true);
714 ath5k_hw_rfb_op(ah
, rf_regs
, g_step
->gos_param
[2],
715 AR5K_RF_PWD_137
, true);
717 ath5k_hw_rfb_op(ah
, rf_regs
, g_step
->gos_param
[3],
718 AR5K_RF_PWD_136
, true);
720 ath5k_hw_rfb_op(ah
, rf_regs
, g_step
->gos_param
[4],
721 AR5K_RF_PWD_132
, true);
723 ath5k_hw_rfb_op(ah
, rf_regs
, g_step
->gos_param
[5],
724 AR5K_RF_PWD_131
, true);
726 ath5k_hw_rfb_op(ah
, rf_regs
, g_step
->gos_param
[6],
727 AR5K_RF_PWD_130
, true);
729 /* We programmed gain_F parameters, switch back
731 ah
->ah_gain
.g_state
= AR5K_RFGAIN_ACTIVE
;
736 ath5k_hw_rfb_op(ah
, rf_regs
, ee
->ee_xpd
[ee_mode
],
737 AR5K_RF_XPD_SEL
, true);
739 if (ah
->ah_radio_5ghz_revision
< AR5K_SREV_RAD_5112A
) {
740 /* Rev. 1 supports only one xpd */
741 ath5k_hw_rfb_op(ah
, rf_regs
,
742 ee
->ee_x_gain
[ee_mode
],
743 AR5K_RF_XPD_GAIN
, true);
746 /* TODO: Set high and low gain bits */
747 ath5k_hw_rfb_op(ah
, rf_regs
,
748 ee
->ee_x_gain
[ee_mode
],
749 AR5K_RF_PD_GAIN_LO
, true);
750 ath5k_hw_rfb_op(ah
, rf_regs
,
751 ee
->ee_x_gain
[ee_mode
],
752 AR5K_RF_PD_GAIN_HI
, true);
754 /* Lower synth voltage on Rev 2 */
755 ath5k_hw_rfb_op(ah
, rf_regs
, 2,
756 AR5K_RF_HIGH_VC_CP
, true);
758 ath5k_hw_rfb_op(ah
, rf_regs
, 2,
759 AR5K_RF_MID_VC_CP
, true);
761 ath5k_hw_rfb_op(ah
, rf_regs
, 2,
762 AR5K_RF_LOW_VC_CP
, true);
764 ath5k_hw_rfb_op(ah
, rf_regs
, 2,
765 AR5K_RF_PUSH_UP
, true);
767 /* Decrease power consumption on 5213+ BaseBand */
768 if (ah
->ah_phy_revision
>= AR5K_SREV_PHY_5212A
) {
769 ath5k_hw_rfb_op(ah
, rf_regs
, 1,
770 AR5K_RF_PAD2GND
, true);
772 ath5k_hw_rfb_op(ah
, rf_regs
, 1,
773 AR5K_RF_XB2_LVL
, true);
775 ath5k_hw_rfb_op(ah
, rf_regs
, 1,
776 AR5K_RF_XB5_LVL
, true);
778 ath5k_hw_rfb_op(ah
, rf_regs
, 1,
779 AR5K_RF_PWD_167
, true);
781 ath5k_hw_rfb_op(ah
, rf_regs
, 1,
782 AR5K_RF_PWD_166
, true);
786 ath5k_hw_rfb_op(ah
, rf_regs
, ee
->ee_i_gain
[ee_mode
],
787 AR5K_RF_GAIN_I
, true);
789 /* TODO: Half/quarter channel support */
793 if (ah
->ah_radio
== AR5K_RF5413
&&
794 channel
->hw_value
& CHANNEL_2GHZ
) {
796 ath5k_hw_rfb_op(ah
, rf_regs
, 1, AR5K_RF_DERBY_CHAN_SEL_MODE
,
799 /* Set optimum value for early revisions (on pci-e chips) */
800 if (ah
->ah_mac_srev
>= AR5K_SREV_AR5424
&&
801 ah
->ah_mac_srev
< AR5K_SREV_AR5413
)
802 ath5k_hw_rfb_op(ah
, rf_regs
, ath5k_hw_bitswap(6, 3),
803 AR5K_RF_PWD_ICLOBUF_2G
, true);
807 /* Write RF banks on hw */
808 for (i
= 0; i
< ah
->ah_rf_banks_size
; i
++) {
810 ath5k_hw_reg_write(ah
, rfb
[i
], ini_rfb
[i
].rfb_ctrl_register
);
817 /**************************\
818 PHY/RF channel functions
819 \**************************/
822 * Check if a channel is supported
824 bool ath5k_channel_ok(struct ath5k_hw
*ah
, u16 freq
, unsigned int flags
)
826 /* Check if the channel is in our supported range */
827 if (flags
& CHANNEL_2GHZ
) {
828 if ((freq
>= ah
->ah_capabilities
.cap_range
.range_2ghz_min
) &&
829 (freq
<= ah
->ah_capabilities
.cap_range
.range_2ghz_max
))
831 } else if (flags
& CHANNEL_5GHZ
)
832 if ((freq
>= ah
->ah_capabilities
.cap_range
.range_5ghz_min
) &&
833 (freq
<= ah
->ah_capabilities
.cap_range
.range_5ghz_max
))
840 * Convertion needed for RF5110
842 static u32
ath5k_hw_rf5110_chan2athchan(struct ieee80211_channel
*channel
)
847 * Convert IEEE channel/MHz to an internal channel value used
848 * by the AR5210 chipset. This has not been verified with
849 * newer chipsets like the AR5212A who have a completely
850 * different RF/PHY part.
852 athchan
= (ath5k_hw_bitswap(
853 (ieee80211_frequency_to_channel(
854 channel
->center_freq
) - 24) / 2, 5)
855 << 1) | (1 << 6) | 0x1;
860 * Set channel on RF5110
862 static int ath5k_hw_rf5110_channel(struct ath5k_hw
*ah
,
863 struct ieee80211_channel
*channel
)
868 * Set the channel and wait
870 data
= ath5k_hw_rf5110_chan2athchan(channel
);
871 ath5k_hw_reg_write(ah
, data
, AR5K_RF_BUFFER
);
872 ath5k_hw_reg_write(ah
, 0, AR5K_RF_BUFFER_CONTROL_0
);
879 * Convertion needed for 5111
881 static int ath5k_hw_rf5111_chan2athchan(unsigned int ieee
,
882 struct ath5k_athchan_2ghz
*athchan
)
886 /* Cast this value to catch negative channel numbers (>= -19) */
890 * Map 2GHz IEEE channel to 5GHz Atheros channel
893 athchan
->a2_athchan
= 115 + channel
;
894 athchan
->a2_flags
= 0x46;
895 } else if (channel
== 14) {
896 athchan
->a2_athchan
= 124;
897 athchan
->a2_flags
= 0x44;
898 } else if (channel
>= 15 && channel
<= 26) {
899 athchan
->a2_athchan
= ((channel
- 14) * 4) + 132;
900 athchan
->a2_flags
= 0x46;
908 * Set channel on 5111
910 static int ath5k_hw_rf5111_channel(struct ath5k_hw
*ah
,
911 struct ieee80211_channel
*channel
)
913 struct ath5k_athchan_2ghz ath5k_channel_2ghz
;
914 unsigned int ath5k_channel
=
915 ieee80211_frequency_to_channel(channel
->center_freq
);
916 u32 data0
, data1
, clock
;
920 * Set the channel on the RF5111 radio
924 if (channel
->hw_value
& CHANNEL_2GHZ
) {
925 /* Map 2GHz channel to 5GHz Atheros channel ID */
926 ret
= ath5k_hw_rf5111_chan2athchan(
927 ieee80211_frequency_to_channel(channel
->center_freq
),
928 &ath5k_channel_2ghz
);
932 ath5k_channel
= ath5k_channel_2ghz
.a2_athchan
;
933 data0
= ((ath5k_hw_bitswap(ath5k_channel_2ghz
.a2_flags
, 8) & 0xff)
937 if (ath5k_channel
< 145 || !(ath5k_channel
& 1)) {
939 data1
= ((ath5k_hw_bitswap(ath5k_channel
- 24, 8) & 0xff) << 2) |
940 (clock
<< 1) | (1 << 10) | 1;
943 data1
= ((ath5k_hw_bitswap((ath5k_channel
- 24) / 2, 8) & 0xff)
944 << 2) | (clock
<< 1) | (1 << 10) | 1;
947 ath5k_hw_reg_write(ah
, (data1
& 0xff) | ((data0
& 0xff) << 8),
949 ath5k_hw_reg_write(ah
, ((data1
>> 8) & 0xff) | (data0
& 0xff00),
950 AR5K_RF_BUFFER_CONTROL_3
);
956 * Set channel on 5112 and newer
958 static int ath5k_hw_rf5112_channel(struct ath5k_hw
*ah
,
959 struct ieee80211_channel
*channel
)
961 u32 data
, data0
, data1
, data2
;
964 data
= data0
= data1
= data2
= 0;
965 c
= channel
->center_freq
;
968 if (!((c
- 2224) % 5)) {
969 data0
= ((2 * (c
- 704)) - 3040) / 10;
971 } else if (!((c
- 2192) % 5)) {
972 data0
= ((2 * (c
- 672)) - 3040) / 10;
977 data0
= ath5k_hw_bitswap((data0
<< 2) & 0xff, 8);
978 } else if ((c
- (c
% 5)) != 2 || c
> 5435) {
979 if (!(c
% 20) && c
>= 5120) {
980 data0
= ath5k_hw_bitswap(((c
- 4800) / 20 << 2), 8);
981 data2
= ath5k_hw_bitswap(3, 2);
982 } else if (!(c
% 10)) {
983 data0
= ath5k_hw_bitswap(((c
- 4800) / 10 << 1), 8);
984 data2
= ath5k_hw_bitswap(2, 2);
985 } else if (!(c
% 5)) {
986 data0
= ath5k_hw_bitswap((c
- 4800) / 5, 8);
987 data2
= ath5k_hw_bitswap(1, 2);
991 data0
= ath5k_hw_bitswap((10 * (c
- 2) - 4800) / 25 + 1, 8);
992 data2
= ath5k_hw_bitswap(0, 2);
995 data
= (data0
<< 4) | (data1
<< 1) | (data2
<< 2) | 0x1001;
997 ath5k_hw_reg_write(ah
, data
& 0xff, AR5K_RF_BUFFER
);
998 ath5k_hw_reg_write(ah
, (data
>> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5
);
1004 * Set the channel on the RF2425
1006 static int ath5k_hw_rf2425_channel(struct ath5k_hw
*ah
,
1007 struct ieee80211_channel
*channel
)
1009 u32 data
, data0
, data2
;
1012 data
= data0
= data2
= 0;
1013 c
= channel
->center_freq
;
1016 data0
= ath5k_hw_bitswap((c
- 2272), 8);
1019 } else if ((c
- (c
% 5)) != 2 || c
> 5435) {
1020 if (!(c
% 20) && c
< 5120)
1021 data0
= ath5k_hw_bitswap(((c
- 4800) / 20 << 2), 8);
1023 data0
= ath5k_hw_bitswap(((c
- 4800) / 10 << 1), 8);
1025 data0
= ath5k_hw_bitswap((c
- 4800) / 5, 8);
1028 data2
= ath5k_hw_bitswap(1, 2);
1030 data0
= ath5k_hw_bitswap((10 * (c
- 2) - 4800) / 25 + 1, 8);
1031 data2
= ath5k_hw_bitswap(0, 2);
1034 data
= (data0
<< 4) | data2
<< 2 | 0x1001;
1036 ath5k_hw_reg_write(ah
, data
& 0xff, AR5K_RF_BUFFER
);
1037 ath5k_hw_reg_write(ah
, (data
>> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5
);
1043 * Set a channel on the radio chip
1045 int ath5k_hw_channel(struct ath5k_hw
*ah
, struct ieee80211_channel
*channel
)
1049 * Check bounds supported by the PHY (we don't care about regultory
1050 * restrictions at this point). Note: hw_value already has the band
1051 * (CHANNEL_2GHZ, or CHANNEL_5GHZ) so we inform ath5k_channel_ok()
1052 * of the band by that */
1053 if (!ath5k_channel_ok(ah
, channel
->center_freq
, channel
->hw_value
)) {
1054 ATH5K_ERR(ah
->ah_sc
,
1055 "channel frequency (%u MHz) out of supported "
1057 channel
->center_freq
);
1062 * Set the channel and wait
1064 switch (ah
->ah_radio
) {
1066 ret
= ath5k_hw_rf5110_channel(ah
, channel
);
1069 ret
= ath5k_hw_rf5111_channel(ah
, channel
);
1072 ret
= ath5k_hw_rf2425_channel(ah
, channel
);
1075 ret
= ath5k_hw_rf5112_channel(ah
, channel
);
1082 /* Set JAPAN setting for channel 14 */
1083 if (channel
->center_freq
== 2484) {
1084 AR5K_REG_ENABLE_BITS(ah
, AR5K_PHY_CCKTXCTL
,
1085 AR5K_PHY_CCKTXCTL_JAPAN
);
1087 AR5K_REG_ENABLE_BITS(ah
, AR5K_PHY_CCKTXCTL
,
1088 AR5K_PHY_CCKTXCTL_WORLD
);
1091 ah
->ah_current_channel
.center_freq
= channel
->center_freq
;
1092 ah
->ah_current_channel
.hw_value
= channel
->hw_value
;
1093 ah
->ah_turbo
= channel
->hw_value
== CHANNEL_T
? true : false;
1103 * ath5k_hw_noise_floor_calibration - perform PHY noise floor calibration
1105 * @ah: struct ath5k_hw pointer we are operating on
1106 * @freq: the channel frequency, just used for error logging
1108 * This function performs a noise floor calibration of the PHY and waits for
1109 * it to complete. Then the noise floor value is compared to some maximum
1110 * noise floor we consider valid.
1112 * Note that this is different from what the madwifi HAL does: it reads the
1113 * noise floor and afterwards initiates the calibration. Since the noise floor
1114 * calibration can take some time to finish, depending on the current channel
1115 * use, that avoids the occasional timeout warnings we are seeing now.
1117 * See the following link for an Atheros patent on noise floor calibration:
1118 * http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL \
1119 * &p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=7245893.PN.&OS=PN/7
1121 * XXX: Since during noise floor calibration antennas are detached according to
1122 * the patent, we should stop tx queues here.
1125 ath5k_hw_noise_floor_calibration(struct ath5k_hw
*ah
, short freq
)
1132 * Enable noise floor calibration
1134 AR5K_REG_ENABLE_BITS(ah
, AR5K_PHY_AGCCTL
,
1135 AR5K_PHY_AGCCTL_NF
);
1137 ret
= ath5k_hw_register_timeout(ah
, AR5K_PHY_AGCCTL
,
1138 AR5K_PHY_AGCCTL_NF
, 0, false);
1140 ATH5K_ERR(ah
->ah_sc
,
1141 "noise floor calibration timeout (%uMHz)\n", freq
);
1145 /* Wait until the noise floor is calibrated and read the value */
1146 for (i
= 20; i
> 0; i
--) {
1148 noise_floor
= ath5k_hw_reg_read(ah
, AR5K_PHY_NF
);
1149 noise_floor
= AR5K_PHY_NF_RVAL(noise_floor
);
1150 if (noise_floor
& AR5K_PHY_NF_ACTIVE
) {
1151 noise_floor
= AR5K_PHY_NF_AVAL(noise_floor
);
1153 if (noise_floor
<= AR5K_TUNE_NOISE_FLOOR
)
1158 ATH5K_DBG_UNLIMIT(ah
->ah_sc
, ATH5K_DEBUG_CALIBRATE
,
1159 "noise floor %d\n", noise_floor
);
1161 if (noise_floor
> AR5K_TUNE_NOISE_FLOOR
) {
1162 ATH5K_ERR(ah
->ah_sc
,
1163 "noise floor calibration failed (%uMHz)\n", freq
);
1167 ah
->ah_noise_floor
= noise_floor
;
1173 * Perform a PHY calibration on RF5110
1174 * -Fix BPSK/QAM Constellation (I/Q correction)
1175 * -Calculate Noise Floor
1177 static int ath5k_hw_rf5110_calibrate(struct ath5k_hw
*ah
,
1178 struct ieee80211_channel
*channel
)
1180 u32 phy_sig
, phy_agc
, phy_sat
, beacon
;
1184 * Disable beacons and RX/TX queues, wait
1186 AR5K_REG_ENABLE_BITS(ah
, AR5K_DIAG_SW_5210
,
1187 AR5K_DIAG_SW_DIS_TX
| AR5K_DIAG_SW_DIS_RX_5210
);
1188 beacon
= ath5k_hw_reg_read(ah
, AR5K_BEACON_5210
);
1189 ath5k_hw_reg_write(ah
, beacon
& ~AR5K_BEACON_ENABLE
, AR5K_BEACON_5210
);
1194 * Set the channel (with AGC turned off)
1196 AR5K_REG_ENABLE_BITS(ah
, AR5K_PHY_AGC
, AR5K_PHY_AGC_DISABLE
);
1198 ret
= ath5k_hw_channel(ah
, channel
);
1201 * Activate PHY and wait
1203 ath5k_hw_reg_write(ah
, AR5K_PHY_ACT_ENABLE
, AR5K_PHY_ACT
);
1206 AR5K_REG_DISABLE_BITS(ah
, AR5K_PHY_AGC
, AR5K_PHY_AGC_DISABLE
);
1212 * Calibrate the radio chip
1215 /* Remember normal state */
1216 phy_sig
= ath5k_hw_reg_read(ah
, AR5K_PHY_SIG
);
1217 phy_agc
= ath5k_hw_reg_read(ah
, AR5K_PHY_AGCCOARSE
);
1218 phy_sat
= ath5k_hw_reg_read(ah
, AR5K_PHY_ADCSAT
);
1220 /* Update radio registers */
1221 ath5k_hw_reg_write(ah
, (phy_sig
& ~(AR5K_PHY_SIG_FIRPWR
)) |
1222 AR5K_REG_SM(-1, AR5K_PHY_SIG_FIRPWR
), AR5K_PHY_SIG
);
1224 ath5k_hw_reg_write(ah
, (phy_agc
& ~(AR5K_PHY_AGCCOARSE_HI
|
1225 AR5K_PHY_AGCCOARSE_LO
)) |
1226 AR5K_REG_SM(-1, AR5K_PHY_AGCCOARSE_HI
) |
1227 AR5K_REG_SM(-127, AR5K_PHY_AGCCOARSE_LO
), AR5K_PHY_AGCCOARSE
);
1229 ath5k_hw_reg_write(ah
, (phy_sat
& ~(AR5K_PHY_ADCSAT_ICNT
|
1230 AR5K_PHY_ADCSAT_THR
)) |
1231 AR5K_REG_SM(2, AR5K_PHY_ADCSAT_ICNT
) |
1232 AR5K_REG_SM(12, AR5K_PHY_ADCSAT_THR
), AR5K_PHY_ADCSAT
);
1236 AR5K_REG_ENABLE_BITS(ah
, AR5K_PHY_AGC
, AR5K_PHY_AGC_DISABLE
);
1238 ath5k_hw_reg_write(ah
, AR5K_PHY_RFSTG_DISABLE
, AR5K_PHY_RFSTG
);
1239 AR5K_REG_DISABLE_BITS(ah
, AR5K_PHY_AGC
, AR5K_PHY_AGC_DISABLE
);
1244 * Enable calibration and wait until completion
1246 AR5K_REG_ENABLE_BITS(ah
, AR5K_PHY_AGCCTL
, AR5K_PHY_AGCCTL_CAL
);
1248 ret
= ath5k_hw_register_timeout(ah
, AR5K_PHY_AGCCTL
,
1249 AR5K_PHY_AGCCTL_CAL
, 0, false);
1251 /* Reset to normal state */
1252 ath5k_hw_reg_write(ah
, phy_sig
, AR5K_PHY_SIG
);
1253 ath5k_hw_reg_write(ah
, phy_agc
, AR5K_PHY_AGCCOARSE
);
1254 ath5k_hw_reg_write(ah
, phy_sat
, AR5K_PHY_ADCSAT
);
1257 ATH5K_ERR(ah
->ah_sc
, "calibration timeout (%uMHz)\n",
1258 channel
->center_freq
);
1262 ath5k_hw_noise_floor_calibration(ah
, channel
->center_freq
);
1265 * Re-enable RX/TX and beacons
1267 AR5K_REG_DISABLE_BITS(ah
, AR5K_DIAG_SW_5210
,
1268 AR5K_DIAG_SW_DIS_TX
| AR5K_DIAG_SW_DIS_RX_5210
);
1269 ath5k_hw_reg_write(ah
, beacon
, AR5K_BEACON_5210
);
1275 * Perform a PHY calibration on RF5111/5112 and newer chips
1277 static int ath5k_hw_rf511x_calibrate(struct ath5k_hw
*ah
,
1278 struct ieee80211_channel
*channel
)
1281 s32 iq_corr
, i_coff
, i_coffd
, q_coff
, q_coffd
;
1283 ATH5K_TRACE(ah
->ah_sc
);
1285 if (!ah
->ah_calibration
||
1286 ath5k_hw_reg_read(ah
, AR5K_PHY_IQ
) & AR5K_PHY_IQ_RUN
)
1289 /* Calibration has finished, get the results and re-run */
1290 for (i
= 0; i
<= 10; i
++) {
1291 iq_corr
= ath5k_hw_reg_read(ah
, AR5K_PHY_IQRES_CAL_CORR
);
1292 i_pwr
= ath5k_hw_reg_read(ah
, AR5K_PHY_IQRES_CAL_PWR_I
);
1293 q_pwr
= ath5k_hw_reg_read(ah
, AR5K_PHY_IQRES_CAL_PWR_Q
);
1296 i_coffd
= ((i_pwr
>> 1) + (q_pwr
>> 1)) >> 7;
1297 q_coffd
= q_pwr
>> 7;
1300 if (i_coffd
== 0 || q_coffd
== 0)
1303 i_coff
= ((-iq_corr
) / i_coffd
) & 0x3f;
1305 /* Boundary check */
1311 q_coff
= (((s32
)i_pwr
/ q_coffd
) - 128) & 0x1f;
1313 /* Boundary check */
1319 /* Commit new I/Q value */
1320 AR5K_REG_ENABLE_BITS(ah
, AR5K_PHY_IQ
, AR5K_PHY_IQ_CORR_ENABLE
|
1321 ((u32
)q_coff
) | ((u32
)i_coff
<< AR5K_PHY_IQ_CORR_Q_I_COFF_S
));
1323 /* Re-enable calibration -if we don't we'll commit
1324 * the same values again and again */
1325 AR5K_REG_WRITE_BITS(ah
, AR5K_PHY_IQ
,
1326 AR5K_PHY_IQ_CAL_NUM_LOG_MAX
, 15);
1327 AR5K_REG_ENABLE_BITS(ah
, AR5K_PHY_IQ
, AR5K_PHY_IQ_RUN
);
1331 /* TODO: Separate noise floor calibration from I/Q calibration
1332 * since noise floor calibration interrupts rx path while I/Q
1333 * calibration doesn't. We don't need to run noise floor calibration
1334 * as often as I/Q calibration.*/
1335 ath5k_hw_noise_floor_calibration(ah
, channel
->center_freq
);
1337 /* Initiate a gain_F calibration */
1338 ath5k_hw_request_rfgain_probe(ah
);
1344 * Perform a PHY calibration
1346 int ath5k_hw_phy_calibrate(struct ath5k_hw
*ah
,
1347 struct ieee80211_channel
*channel
)
1351 if (ah
->ah_radio
== AR5K_RF5110
)
1352 ret
= ath5k_hw_rf5110_calibrate(ah
, channel
);
1354 ret
= ath5k_hw_rf511x_calibrate(ah
, channel
);
1359 int ath5k_hw_phy_disable(struct ath5k_hw
*ah
)
1361 ATH5K_TRACE(ah
->ah_sc
);
1363 ath5k_hw_reg_write(ah
, AR5K_PHY_ACT_DISABLE
, AR5K_PHY_ACT
);
1368 /********************\
1370 \********************/
1373 * Get the PHY Chip revision
1375 u16
ath5k_hw_radio_revision(struct ath5k_hw
*ah
, unsigned int chan
)
1381 ATH5K_TRACE(ah
->ah_sc
);
1384 * Set the radio chip access register
1388 ath5k_hw_reg_write(ah
, AR5K_PHY_SHIFT_2GHZ
, AR5K_PHY(0));
1391 ath5k_hw_reg_write(ah
, AR5K_PHY_SHIFT_5GHZ
, AR5K_PHY(0));
1399 /* ...wait until PHY is ready and read the selected radio revision */
1400 ath5k_hw_reg_write(ah
, 0x00001c16, AR5K_PHY(0x34));
1402 for (i
= 0; i
< 8; i
++)
1403 ath5k_hw_reg_write(ah
, 0x00010000, AR5K_PHY(0x20));
1405 if (ah
->ah_version
== AR5K_AR5210
) {
1406 srev
= ath5k_hw_reg_read(ah
, AR5K_PHY(256) >> 28) & 0xf;
1407 ret
= (u16
)ath5k_hw_bitswap(srev
, 4) + 1;
1409 srev
= (ath5k_hw_reg_read(ah
, AR5K_PHY(0x100)) >> 24) & 0xff;
1410 ret
= (u16
)ath5k_hw_bitswap(((srev
& 0xf0) >> 4) |
1411 ((srev
& 0x0f) << 4), 8);
1414 /* Reset to the 5GHz mode */
1415 ath5k_hw_reg_write(ah
, AR5K_PHY_SHIFT_5GHZ
, AR5K_PHY(0));
1420 void /*TODO:Boundary check*/
1421 ath5k_hw_set_def_antenna(struct ath5k_hw
*ah
, unsigned int ant
)
1423 ATH5K_TRACE(ah
->ah_sc
);
1425 if (ah
->ah_version
!= AR5K_AR5210
)
1426 ath5k_hw_reg_write(ah
, ant
, AR5K_DEFAULT_ANTENNA
);
1429 unsigned int ath5k_hw_get_def_antenna(struct ath5k_hw
*ah
)
1431 ATH5K_TRACE(ah
->ah_sc
);
1433 if (ah
->ah_version
!= AR5K_AR5210
)
1434 return ath5k_hw_reg_read(ah
, AR5K_DEFAULT_ANTENNA
);
1436 return false; /*XXX: What do we return for 5210 ?*/
1449 * Do linear interpolation between two given (x, y) points
1452 ath5k_get_interpolated_value(s16 target
, s16 x_left
, s16 x_right
,
1453 s16 y_left
, s16 y_right
)
1457 /* Avoid divide by zero and skip interpolation
1458 * if we have the same point */
1459 if ((x_left
== x_right
) || (y_left
== y_right
))
1463 * Since we use ints and not fps, we need to scale up in
1464 * order to get a sane ratio value (or else we 'll eg. get
1465 * always 1 instead of 1.25, 1.75 etc). We scale up by 100
1466 * to have some accuracy both for 0.5 and 0.25 steps.
1468 ratio
= ((100 * y_right
- 100 * y_left
)/(x_right
- x_left
));
1470 /* Now scale down to be in range */
1471 result
= y_left
+ (ratio
* (target
- x_left
) / 100);
1477 * Find vertical boundary (min pwr) for the linear PCDAC curve.
1479 * Since we have the top of the curve and we draw the line below
1480 * until we reach 1 (1 pcdac step) we need to know which point
1481 * (x value) that is so that we don't go below y axis and have negative
1482 * pcdac values when creating the curve, or fill the table with zeroes.
1485 ath5k_get_linear_pcdac_min(const u8
*stepL
, const u8
*stepR
,
1486 const s16
*pwrL
, const s16
*pwrR
)
1489 s16 min_pwrL
, min_pwrR
;
1492 if (pwrL
[0] == pwrL
[1])
1498 tmp
= (s8
) ath5k_get_interpolated_value(pwr_i
,
1500 stepL
[0], stepL
[1]);
1506 if (pwrR
[0] == pwrR
[1])
1512 tmp
= (s8
) ath5k_get_interpolated_value(pwr_i
,
1514 stepR
[0], stepR
[1]);
1520 /* Keep the right boundary so that it works for both curves */
1521 return max(min_pwrL
, min_pwrR
);
1525 * Interpolate (pwr,vpd) points to create a Power to PDADC or a
1526 * Power to PCDAC curve.
1528 * Each curve has power on x axis (in 0.5dB units) and PCDAC/PDADC
1529 * steps (offsets) on y axis. Power can go up to 31.5dB and max
1530 * PCDAC/PDADC step for each curve is 64 but we can write more than
1531 * one curves on hw so we can go up to 128 (which is the max step we
1532 * can write on the final table).
1534 * We write y values (PCDAC/PDADC steps) on hw.
1537 ath5k_create_power_curve(s16 pmin
, s16 pmax
,
1538 const s16
*pwr
, const u8
*vpd
,
1540 u8
*vpd_table
, u8 type
)
1542 u8 idx
[2] = { 0, 1 };
1549 /* We want the whole line, so adjust boundaries
1550 * to cover the entire power range. Note that
1551 * power values are already 0.25dB so no need
1552 * to multiply pwr_i by 2 */
1553 if (type
== AR5K_PWRTABLE_LINEAR_PCDAC
) {
1559 /* Find surrounding turning points (TPs)
1560 * and interpolate between them */
1561 for (i
= 0; (i
<= (u16
) (pmax
- pmin
)) &&
1562 (i
< AR5K_EEPROM_POWER_TABLE_SIZE
); i
++) {
1564 /* We passed the right TP, move to the next set of TPs
1565 * if we pass the last TP, extrapolate above using the last
1566 * two TPs for ratio */
1567 if ((pwr_i
> pwr
[idx
[1]]) && (idx
[1] < num_points
- 1)) {
1572 vpd_table
[i
] = (u8
) ath5k_get_interpolated_value(pwr_i
,
1573 pwr
[idx
[0]], pwr
[idx
[1]],
1574 vpd
[idx
[0]], vpd
[idx
[1]]);
1576 /* Increase by 0.5dB
1577 * (0.25 dB units) */
1583 * Get the surrounding per-channel power calibration piers
1584 * for a given frequency so that we can interpolate between
1585 * them and come up with an apropriate dataset for our current
1589 ath5k_get_chan_pcal_surrounding_piers(struct ath5k_hw
*ah
,
1590 struct ieee80211_channel
*channel
,
1591 struct ath5k_chan_pcal_info
**pcinfo_l
,
1592 struct ath5k_chan_pcal_info
**pcinfo_r
)
1594 struct ath5k_eeprom_info
*ee
= &ah
->ah_capabilities
.cap_eeprom
;
1595 struct ath5k_chan_pcal_info
*pcinfo
;
1598 u32 target
= channel
->center_freq
;
1603 if (!(channel
->hw_value
& CHANNEL_OFDM
)) {
1604 pcinfo
= ee
->ee_pwr_cal_b
;
1605 mode
= AR5K_EEPROM_MODE_11B
;
1606 } else if (channel
->hw_value
& CHANNEL_2GHZ
) {
1607 pcinfo
= ee
->ee_pwr_cal_g
;
1608 mode
= AR5K_EEPROM_MODE_11G
;
1610 pcinfo
= ee
->ee_pwr_cal_a
;
1611 mode
= AR5K_EEPROM_MODE_11A
;
1613 max
= ee
->ee_n_piers
[mode
] - 1;
1615 /* Frequency is below our calibrated
1616 * range. Use the lowest power curve
1618 if (target
< pcinfo
[0].freq
) {
1623 /* Frequency is above our calibrated
1624 * range. Use the highest power curve
1626 if (target
> pcinfo
[max
].freq
) {
1627 idx_l
= idx_r
= max
;
1631 /* Frequency is inside our calibrated
1632 * channel range. Pick the surrounding
1633 * calibration piers so that we can
1635 for (i
= 0; i
<= max
; i
++) {
1637 /* Frequency matches one of our calibration
1638 * piers, no need to interpolate, just use
1639 * that calibration pier */
1640 if (pcinfo
[i
].freq
== target
) {
1645 /* We found a calibration pier that's above
1646 * frequency, use this pier and the previous
1647 * one to interpolate */
1648 if (target
< pcinfo
[i
].freq
) {
1656 *pcinfo_l
= &pcinfo
[idx_l
];
1657 *pcinfo_r
= &pcinfo
[idx_r
];
1663 * Get the surrounding per-rate power calibration data
1664 * for a given frequency and interpolate between power
1665 * values to set max target power supported by hw for
1669 ath5k_get_rate_pcal_data(struct ath5k_hw
*ah
,
1670 struct ieee80211_channel
*channel
,
1671 struct ath5k_rate_pcal_info
*rates
)
1673 struct ath5k_eeprom_info
*ee
= &ah
->ah_capabilities
.cap_eeprom
;
1674 struct ath5k_rate_pcal_info
*rpinfo
;
1677 u32 target
= channel
->center_freq
;
1682 if (!(channel
->hw_value
& CHANNEL_OFDM
)) {
1683 rpinfo
= ee
->ee_rate_tpwr_b
;
1684 mode
= AR5K_EEPROM_MODE_11B
;
1685 } else if (channel
->hw_value
& CHANNEL_2GHZ
) {
1686 rpinfo
= ee
->ee_rate_tpwr_g
;
1687 mode
= AR5K_EEPROM_MODE_11G
;
1689 rpinfo
= ee
->ee_rate_tpwr_a
;
1690 mode
= AR5K_EEPROM_MODE_11A
;
1692 max
= ee
->ee_rate_target_pwr_num
[mode
] - 1;
1694 /* Get the surrounding calibration
1695 * piers - same as above */
1696 if (target
< rpinfo
[0].freq
) {
1701 if (target
> rpinfo
[max
].freq
) {
1702 idx_l
= idx_r
= max
;
1706 for (i
= 0; i
<= max
; i
++) {
1708 if (rpinfo
[i
].freq
== target
) {
1713 if (target
< rpinfo
[i
].freq
) {
1721 /* Now interpolate power value, based on the frequency */
1722 rates
->freq
= target
;
1724 rates
->target_power_6to24
=
1725 ath5k_get_interpolated_value(target
, rpinfo
[idx_l
].freq
,
1727 rpinfo
[idx_l
].target_power_6to24
,
1728 rpinfo
[idx_r
].target_power_6to24
);
1730 rates
->target_power_36
=
1731 ath5k_get_interpolated_value(target
, rpinfo
[idx_l
].freq
,
1733 rpinfo
[idx_l
].target_power_36
,
1734 rpinfo
[idx_r
].target_power_36
);
1736 rates
->target_power_48
=
1737 ath5k_get_interpolated_value(target
, rpinfo
[idx_l
].freq
,
1739 rpinfo
[idx_l
].target_power_48
,
1740 rpinfo
[idx_r
].target_power_48
);
1742 rates
->target_power_54
=
1743 ath5k_get_interpolated_value(target
, rpinfo
[idx_l
].freq
,
1745 rpinfo
[idx_l
].target_power_54
,
1746 rpinfo
[idx_r
].target_power_54
);
1750 * Get the max edge power for this channel if
1751 * we have such data from EEPROM's Conformance Test
1752 * Limits (CTL), and limit max power if needed.
1754 * FIXME: Only works for world regulatory domains
1757 ath5k_get_max_ctl_power(struct ath5k_hw
*ah
,
1758 struct ieee80211_channel
*channel
)
1760 struct ath5k_eeprom_info
*ee
= &ah
->ah_capabilities
.cap_eeprom
;
1761 struct ath5k_edge_power
*rep
= ee
->ee_ctl_pwr
;
1762 u8
*ctl_val
= ee
->ee_ctl
;
1763 s16 max_chan_pwr
= ah
->ah_txpower
.txp_max_pwr
/ 4;
1768 u32 target
= channel
->center_freq
;
1770 /* Find out a CTL for our mode that's not mapped
1771 * on a specific reg domain.
1773 * TODO: Map our current reg domain to one of the 3 available
1774 * reg domain ids so that we can support more CTLs. */
1775 switch (channel
->hw_value
& CHANNEL_MODES
) {
1777 ctl_mode
= AR5K_CTL_11A
| AR5K_CTL_NO_REGDOMAIN
;
1780 ctl_mode
= AR5K_CTL_11G
| AR5K_CTL_NO_REGDOMAIN
;
1783 ctl_mode
= AR5K_CTL_11B
| AR5K_CTL_NO_REGDOMAIN
;
1786 ctl_mode
= AR5K_CTL_TURBO
| AR5K_CTL_NO_REGDOMAIN
;
1789 ctl_mode
= AR5K_CTL_TURBOG
| AR5K_CTL_NO_REGDOMAIN
;
1797 for (i
= 0; i
< ee
->ee_ctls
; i
++) {
1798 if (ctl_val
[i
] == ctl_mode
) {
1804 /* If we have a CTL dataset available grab it and find the
1805 * edge power for our frequency */
1806 if (ctl_idx
== 0xFF)
1809 /* Edge powers are sorted by frequency from lower
1810 * to higher. Each CTL corresponds to 8 edge power
1812 rep_idx
= ctl_idx
* AR5K_EEPROM_N_EDGES
;
1814 /* Don't do boundaries check because we
1815 * might have more that one bands defined
1818 /* Get the edge power that's closer to our
1820 for (i
= 0; i
< AR5K_EEPROM_N_EDGES
; i
++) {
1822 if (target
<= rep
[rep_idx
].freq
)
1823 edge_pwr
= (s16
) rep
[rep_idx
].edge
;
1827 ah
->ah_txpower
.txp_max_pwr
= 4*min(edge_pwr
, max_chan_pwr
);
1832 * Power to PCDAC table functions
1836 * Fill Power to PCDAC table on RF5111
1838 * No further processing is needed for RF5111, the only thing we have to
1839 * do is fill the values below and above calibration range since eeprom data
1840 * may not cover the entire PCDAC table.
1843 ath5k_fill_pwr_to_pcdac_table(struct ath5k_hw
*ah
, s16
* table_min
,
1846 u8
*pcdac_out
= ah
->ah_txpower
.txp_pd_table
;
1847 u8
*pcdac_tmp
= ah
->ah_txpower
.tmpL
[0];
1848 u8 pcdac_0
, pcdac_n
, pcdac_i
, pwr_idx
, i
;
1849 s16 min_pwr
, max_pwr
;
1851 /* Get table boundaries */
1852 min_pwr
= table_min
[0];
1853 pcdac_0
= pcdac_tmp
[0];
1855 max_pwr
= table_max
[0];
1856 pcdac_n
= pcdac_tmp
[table_max
[0] - table_min
[0]];
1858 /* Extrapolate below minimum using pcdac_0 */
1860 for (i
= 0; i
< min_pwr
; i
++)
1861 pcdac_out
[pcdac_i
++] = pcdac_0
;
1863 /* Copy values from pcdac_tmp */
1865 for (i
= 0 ; pwr_idx
<= max_pwr
&&
1866 pcdac_i
< AR5K_EEPROM_POWER_TABLE_SIZE
; i
++) {
1867 pcdac_out
[pcdac_i
++] = pcdac_tmp
[i
];
1871 /* Extrapolate above maximum */
1872 while (pcdac_i
< AR5K_EEPROM_POWER_TABLE_SIZE
)
1873 pcdac_out
[pcdac_i
++] = pcdac_n
;
1878 * Combine available XPD Curves and fill Linear Power to PCDAC table
1881 * RFX112 can have up to 2 curves (one for low txpower range and one for
1882 * higher txpower range). We need to put them both on pcdac_out and place
1883 * them in the correct location. In case we only have one curve available
1884 * just fit it on pcdac_out (it's supposed to cover the entire range of
1885 * available pwr levels since it's always the higher power curve). Extrapolate
1886 * below and above final table if needed.
1889 ath5k_combine_linear_pcdac_curves(struct ath5k_hw
*ah
, s16
* table_min
,
1890 s16
*table_max
, u8 pdcurves
)
1892 u8
*pcdac_out
= ah
->ah_txpower
.txp_pd_table
;
1899 s16 mid_pwr_idx
= 0;
1900 /* Edge flag turs on the 7nth bit on the PCDAC
1901 * to delcare the higher power curve (force values
1902 * to be greater than 64). If we only have one curve
1903 * we don't need to set this, if we have 2 curves and
1904 * fill the table backwards this can also be used to
1905 * switch from higher power curve to lower power curve */
1909 /* When we have only one curve available
1910 * that's the higher power curve. If we have
1911 * two curves the first is the high power curve
1912 * and the next is the low power curve. */
1914 pcdac_low_pwr
= ah
->ah_txpower
.tmpL
[1];
1915 pcdac_high_pwr
= ah
->ah_txpower
.tmpL
[0];
1916 mid_pwr_idx
= table_max
[1] - table_min
[1] - 1;
1917 max_pwr_idx
= (table_max
[0] - table_min
[0]) / 2;
1919 /* If table size goes beyond 31.5dB, keep the
1920 * upper 31.5dB range when setting tx power.
1921 * Note: 126 = 31.5 dB in quarter dB steps */
1922 if (table_max
[0] - table_min
[1] > 126)
1923 min_pwr_idx
= table_max
[0] - 126;
1925 min_pwr_idx
= table_min
[1];
1927 /* Since we fill table backwards
1928 * start from high power curve */
1929 pcdac_tmp
= pcdac_high_pwr
;
1933 /* If both min and max power limits are in lower
1934 * power curve's range, only use the low power curve.
1935 * TODO: min/max levels are related to target
1936 * power values requested from driver/user
1937 * XXX: Is this really needed ? */
1938 if (min_pwr
< table_max
[1] &&
1939 max_pwr
< table_max
[1]) {
1941 pcdac_tmp
= pcdac_low_pwr
;
1942 max_pwr_idx
= (table_max
[1] - table_min
[1])/2;
1946 pcdac_low_pwr
= ah
->ah_txpower
.tmpL
[1]; /* Zeroed */
1947 pcdac_high_pwr
= ah
->ah_txpower
.tmpL
[0];
1948 min_pwr_idx
= table_min
[0];
1949 max_pwr_idx
= (table_max
[0] - table_min
[0]) / 2;
1950 pcdac_tmp
= pcdac_high_pwr
;
1954 /* This is used when setting tx power*/
1955 ah
->ah_txpower
.txp_min_idx
= min_pwr_idx
/2;
1957 /* Fill Power to PCDAC table backwards */
1959 for (i
= 63; i
>= 0; i
--) {
1960 /* Entering lower power range, reset
1961 * edge flag and set pcdac_tmp to lower
1963 if (edge_flag
== 0x40 &&
1964 (2*pwr
<= (table_max
[1] - table_min
[0]) || pwr
== 0)) {
1966 pcdac_tmp
= pcdac_low_pwr
;
1967 pwr
= mid_pwr_idx
/2;
1970 /* Don't go below 1, extrapolate below if we have
1971 * already swithced to the lower power curve -or
1972 * we only have one curve and edge_flag is zero
1974 if (pcdac_tmp
[pwr
] < 1 && (edge_flag
== 0x00)) {
1976 pcdac_out
[i
] = pcdac_out
[i
+ 1];
1982 pcdac_out
[i
] = pcdac_tmp
[pwr
] | edge_flag
;
1984 /* Extrapolate above if pcdac is greater than
1985 * 126 -this can happen because we OR pcdac_out
1986 * value with edge_flag on high power curve */
1987 if (pcdac_out
[i
] > 126)
1990 /* Decrease by a 0.5dB step */
1995 /* Write PCDAC values on hw */
1997 ath5k_setup_pcdac_table(struct ath5k_hw
*ah
)
1999 u8
*pcdac_out
= ah
->ah_txpower
.txp_pd_table
;
2003 * Write TX power values
2005 for (i
= 0; i
< (AR5K_EEPROM_POWER_TABLE_SIZE
/ 2); i
++) {
2006 ath5k_hw_reg_write(ah
,
2007 (((pcdac_out
[2*i
+ 0] << 8 | 0xff) & 0xffff) << 0) |
2008 (((pcdac_out
[2*i
+ 1] << 8 | 0xff) & 0xffff) << 16),
2009 AR5K_PHY_PCDAC_TXPOWER(i
));
2015 * Power to PDADC table functions
2019 * Set the gain boundaries and create final Power to PDADC table
2021 * We can have up to 4 pd curves, we need to do a simmilar process
2022 * as we do for RF5112. This time we don't have an edge_flag but we
2023 * set the gain boundaries on a separate register.
2026 ath5k_combine_pwr_to_pdadc_curves(struct ath5k_hw
*ah
,
2027 s16
*pwr_min
, s16
*pwr_max
, u8 pdcurves
)
2029 u8 gain_boundaries
[AR5K_EEPROM_N_PD_GAINS
];
2030 u8
*pdadc_out
= ah
->ah_txpower
.txp_pd_table
;
2033 u8 pdadc_i
, pdadc_n
, pwr_step
, pdg
, max_idx
, table_size
;
2036 /* Note: Register value is initialized on initvals
2037 * there is no feedback from hw.
2038 * XXX: What about pd_gain_overlap from EEPROM ? */
2039 pd_gain_overlap
= (u8
) ath5k_hw_reg_read(ah
, AR5K_PHY_TPC_RG5
) &
2040 AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP
;
2042 /* Create final PDADC table */
2043 for (pdg
= 0, pdadc_i
= 0; pdg
< pdcurves
; pdg
++) {
2044 pdadc_tmp
= ah
->ah_txpower
.tmpL
[pdg
];
2046 if (pdg
== pdcurves
- 1)
2047 /* 2 dB boundary stretch for last
2048 * (higher power) curve */
2049 gain_boundaries
[pdg
] = pwr_max
[pdg
] + 4;
2051 /* Set gain boundary in the middle
2052 * between this curve and the next one */
2053 gain_boundaries
[pdg
] =
2054 (pwr_max
[pdg
] + pwr_min
[pdg
+ 1]) / 2;
2056 /* Sanity check in case our 2 db stretch got out of
2058 if (gain_boundaries
[pdg
] > AR5K_TUNE_MAX_TXPOWER
)
2059 gain_boundaries
[pdg
] = AR5K_TUNE_MAX_TXPOWER
;
2061 /* For the first curve (lower power)
2062 * start from 0 dB */
2066 /* For the other curves use the gain overlap */
2067 pdadc_0
= (gain_boundaries
[pdg
- 1] - pwr_min
[pdg
]) -
2070 /* Force each power step to be at least 0.5 dB */
2071 if ((pdadc_tmp
[1] - pdadc_tmp
[0]) > 1)
2072 pwr_step
= pdadc_tmp
[1] - pdadc_tmp
[0];
2076 /* If pdadc_0 is negative, we need to extrapolate
2077 * below this pdgain by a number of pwr_steps */
2078 while ((pdadc_0
< 0) && (pdadc_i
< 128)) {
2079 s16 tmp
= pdadc_tmp
[0] + pdadc_0
* pwr_step
;
2080 pdadc_out
[pdadc_i
++] = (tmp
< 0) ? 0 : (u8
) tmp
;
2084 /* Set last pwr level, using gain boundaries */
2085 pdadc_n
= gain_boundaries
[pdg
] + pd_gain_overlap
- pwr_min
[pdg
];
2086 /* Limit it to be inside pwr range */
2087 table_size
= pwr_max
[pdg
] - pwr_min
[pdg
];
2088 max_idx
= (pdadc_n
< table_size
) ? pdadc_n
: table_size
;
2090 /* Fill pdadc_out table */
2091 while (pdadc_0
< max_idx
)
2092 pdadc_out
[pdadc_i
++] = pdadc_tmp
[pdadc_0
++];
2094 /* Need to extrapolate above this pdgain? */
2095 if (pdadc_n
<= max_idx
)
2098 /* Force each power step to be at least 0.5 dB */
2099 if ((pdadc_tmp
[table_size
- 1] - pdadc_tmp
[table_size
- 2]) > 1)
2100 pwr_step
= pdadc_tmp
[table_size
- 1] -
2101 pdadc_tmp
[table_size
- 2];
2105 /* Extrapolate above */
2106 while ((pdadc_0
< (s16
) pdadc_n
) &&
2107 (pdadc_i
< AR5K_EEPROM_POWER_TABLE_SIZE
* 2)) {
2108 s16 tmp
= pdadc_tmp
[table_size
- 1] +
2109 (pdadc_0
- max_idx
) * pwr_step
;
2110 pdadc_out
[pdadc_i
++] = (tmp
> 127) ? 127 : (u8
) tmp
;
2115 while (pdg
< AR5K_EEPROM_N_PD_GAINS
) {
2116 gain_boundaries
[pdg
] = gain_boundaries
[pdg
- 1];
2120 while (pdadc_i
< AR5K_EEPROM_POWER_TABLE_SIZE
* 2) {
2121 pdadc_out
[pdadc_i
] = pdadc_out
[pdadc_i
- 1];
2125 /* Set gain boundaries */
2126 ath5k_hw_reg_write(ah
,
2127 AR5K_REG_SM(pd_gain_overlap
,
2128 AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP
) |
2129 AR5K_REG_SM(gain_boundaries
[0],
2130 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_1
) |
2131 AR5K_REG_SM(gain_boundaries
[1],
2132 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_2
) |
2133 AR5K_REG_SM(gain_boundaries
[2],
2134 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_3
) |
2135 AR5K_REG_SM(gain_boundaries
[3],
2136 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_4
),
2139 /* Used for setting rate power table */
2140 ah
->ah_txpower
.txp_min_idx
= pwr_min
[0];
2144 /* Write PDADC values on hw */
2146 ath5k_setup_pwr_to_pdadc_table(struct ath5k_hw
*ah
,
2147 u8 pdcurves
, u8
*pdg_to_idx
)
2149 u8
*pdadc_out
= ah
->ah_txpower
.txp_pd_table
;
2153 /* Select the right pdgain curves */
2155 /* Clear current settings */
2156 reg
= ath5k_hw_reg_read(ah
, AR5K_PHY_TPC_RG1
);
2157 reg
&= ~(AR5K_PHY_TPC_RG1_PDGAIN_1
|
2158 AR5K_PHY_TPC_RG1_PDGAIN_2
|
2159 AR5K_PHY_TPC_RG1_PDGAIN_3
|
2160 AR5K_PHY_TPC_RG1_NUM_PD_GAIN
);
2163 * Use pd_gains curve from eeprom
2165 * This overrides the default setting from initvals
2166 * in case some vendors (e.g. Zcomax) don't use the default
2167 * curves. If we don't honor their settings we 'll get a
2168 * 5dB (1 * gain overlap ?) drop.
2170 reg
|= AR5K_REG_SM(pdcurves
, AR5K_PHY_TPC_RG1_NUM_PD_GAIN
);
2174 reg
|= AR5K_REG_SM(pdg_to_idx
[2], AR5K_PHY_TPC_RG1_PDGAIN_3
);
2177 reg
|= AR5K_REG_SM(pdg_to_idx
[1], AR5K_PHY_TPC_RG1_PDGAIN_2
);
2180 reg
|= AR5K_REG_SM(pdg_to_idx
[0], AR5K_PHY_TPC_RG1_PDGAIN_1
);
2183 ath5k_hw_reg_write(ah
, reg
, AR5K_PHY_TPC_RG1
);
2186 * Write TX power values
2188 for (i
= 0; i
< (AR5K_EEPROM_POWER_TABLE_SIZE
/ 2); i
++) {
2189 ath5k_hw_reg_write(ah
,
2190 ((pdadc_out
[4*i
+ 0] & 0xff) << 0) |
2191 ((pdadc_out
[4*i
+ 1] & 0xff) << 8) |
2192 ((pdadc_out
[4*i
+ 2] & 0xff) << 16) |
2193 ((pdadc_out
[4*i
+ 3] & 0xff) << 24),
2194 AR5K_PHY_PDADC_TXPOWER(i
));
2200 * Common code for PCDAC/PDADC tables
2204 * This is the main function that uses all of the above
2205 * to set PCDAC/PDADC table on hw for the current channel.
2206 * This table is used for tx power calibration on the basband,
2207 * without it we get weird tx power levels and in some cases
2208 * distorted spectral mask
2211 ath5k_setup_channel_powertable(struct ath5k_hw
*ah
,
2212 struct ieee80211_channel
*channel
,
2213 u8 ee_mode
, u8 type
)
2215 struct ath5k_pdgain_info
*pdg_L
, *pdg_R
;
2216 struct ath5k_chan_pcal_info
*pcinfo_L
;
2217 struct ath5k_chan_pcal_info
*pcinfo_R
;
2218 struct ath5k_eeprom_info
*ee
= &ah
->ah_capabilities
.cap_eeprom
;
2219 u8
*pdg_curve_to_idx
= ee
->ee_pdc_to_idx
[ee_mode
];
2220 s16 table_min
[AR5K_EEPROM_N_PD_GAINS
];
2221 s16 table_max
[AR5K_EEPROM_N_PD_GAINS
];
2224 u32 target
= channel
->center_freq
;
2227 /* Get surounding freq piers for this channel */
2228 ath5k_get_chan_pcal_surrounding_piers(ah
, channel
,
2232 /* Loop over pd gain curves on
2233 * surounding freq piers by index */
2234 for (pdg
= 0; pdg
< ee
->ee_pd_gains
[ee_mode
]; pdg
++) {
2236 /* Fill curves in reverse order
2237 * from lower power (max gain)
2238 * to higher power. Use curve -> idx
2239 * backmaping we did on eeprom init */
2240 u8 idx
= pdg_curve_to_idx
[pdg
];
2242 /* Grab the needed curves by index */
2243 pdg_L
= &pcinfo_L
->pd_curves
[idx
];
2244 pdg_R
= &pcinfo_R
->pd_curves
[idx
];
2246 /* Initialize the temp tables */
2247 tmpL
= ah
->ah_txpower
.tmpL
[pdg
];
2248 tmpR
= ah
->ah_txpower
.tmpR
[pdg
];
2250 /* Set curve's x boundaries and create
2251 * curves so that they cover the same
2252 * range (if we don't do that one table
2253 * will have values on some range and the
2254 * other one won't have any so interpolation
2256 table_min
[pdg
] = min(pdg_L
->pd_pwr
[0],
2257 pdg_R
->pd_pwr
[0]) / 2;
2259 table_max
[pdg
] = max(pdg_L
->pd_pwr
[pdg_L
->pd_points
- 1],
2260 pdg_R
->pd_pwr
[pdg_R
->pd_points
- 1]) / 2;
2262 /* Now create the curves on surrounding channels
2263 * and interpolate if needed to get the final
2264 * curve for this gain on this channel */
2266 case AR5K_PWRTABLE_LINEAR_PCDAC
:
2267 /* Override min/max so that we don't loose
2268 * accuracy (don't divide by 2) */
2269 table_min
[pdg
] = min(pdg_L
->pd_pwr
[0],
2273 max(pdg_L
->pd_pwr
[pdg_L
->pd_points
- 1],
2274 pdg_R
->pd_pwr
[pdg_R
->pd_points
- 1]);
2276 /* Override minimum so that we don't get
2277 * out of bounds while extrapolating
2278 * below. Don't do this when we have 2
2279 * curves and we are on the high power curve
2280 * because table_min is ok in this case */
2281 if (!(ee
->ee_pd_gains
[ee_mode
] > 1 && pdg
== 0)) {
2284 ath5k_get_linear_pcdac_min(pdg_L
->pd_step
,
2289 /* Don't go too low because we will
2290 * miss the upper part of the curve.
2291 * Note: 126 = 31.5dB (max power supported)
2292 * in 0.25dB units */
2293 if (table_max
[pdg
] - table_min
[pdg
] > 126)
2294 table_min
[pdg
] = table_max
[pdg
] - 126;
2298 case AR5K_PWRTABLE_PWR_TO_PCDAC
:
2299 case AR5K_PWRTABLE_PWR_TO_PDADC
:
2301 ath5k_create_power_curve(table_min
[pdg
],
2305 pdg_L
->pd_points
, tmpL
, type
);
2307 /* We are in a calibration
2308 * pier, no need to interpolate
2309 * between freq piers */
2310 if (pcinfo_L
== pcinfo_R
)
2313 ath5k_create_power_curve(table_min
[pdg
],
2317 pdg_R
->pd_points
, tmpR
, type
);
2323 /* Interpolate between curves
2324 * of surounding freq piers to
2325 * get the final curve for this
2326 * pd gain. Re-use tmpL for interpolation
2328 for (i
= 0; (i
< (u16
) (table_max
[pdg
] - table_min
[pdg
])) &&
2329 (i
< AR5K_EEPROM_POWER_TABLE_SIZE
); i
++) {
2330 tmpL
[i
] = (u8
) ath5k_get_interpolated_value(target
,
2331 (s16
) pcinfo_L
->freq
,
2332 (s16
) pcinfo_R
->freq
,
2338 /* Now we have a set of curves for this
2339 * channel on tmpL (x range is table_max - table_min
2340 * and y values are tmpL[pdg][]) sorted in the same
2341 * order as EEPROM (because we've used the backmaping).
2342 * So for RF5112 it's from higher power to lower power
2343 * and for RF2413 it's from lower power to higher power.
2344 * For RF5111 we only have one curve. */
2346 /* Fill min and max power levels for this
2347 * channel by interpolating the values on
2348 * surounding channels to complete the dataset */
2349 ah
->ah_txpower
.txp_min_pwr
= ath5k_get_interpolated_value(target
,
2350 (s16
) pcinfo_L
->freq
,
2351 (s16
) pcinfo_R
->freq
,
2352 pcinfo_L
->min_pwr
, pcinfo_R
->min_pwr
);
2354 ah
->ah_txpower
.txp_max_pwr
= ath5k_get_interpolated_value(target
,
2355 (s16
) pcinfo_L
->freq
,
2356 (s16
) pcinfo_R
->freq
,
2357 pcinfo_L
->max_pwr
, pcinfo_R
->max_pwr
);
2359 /* We are ready to go, fill PCDAC/PDADC
2360 * table and write settings on hardware */
2362 case AR5K_PWRTABLE_LINEAR_PCDAC
:
2363 /* For RF5112 we can have one or two curves
2364 * and each curve covers a certain power lvl
2365 * range so we need to do some more processing */
2366 ath5k_combine_linear_pcdac_curves(ah
, table_min
, table_max
,
2367 ee
->ee_pd_gains
[ee_mode
]);
2369 /* Set txp.offset so that we can
2370 * match max power value with max
2372 ah
->ah_txpower
.txp_offset
= 64 - (table_max
[0] / 2);
2374 /* Write settings on hw */
2375 ath5k_setup_pcdac_table(ah
);
2377 case AR5K_PWRTABLE_PWR_TO_PCDAC
:
2378 /* We are done for RF5111 since it has only
2379 * one curve, just fit the curve on the table */
2380 ath5k_fill_pwr_to_pcdac_table(ah
, table_min
, table_max
);
2382 /* No rate powertable adjustment for RF5111 */
2383 ah
->ah_txpower
.txp_min_idx
= 0;
2384 ah
->ah_txpower
.txp_offset
= 0;
2386 /* Write settings on hw */
2387 ath5k_setup_pcdac_table(ah
);
2389 case AR5K_PWRTABLE_PWR_TO_PDADC
:
2390 /* Set PDADC boundaries and fill
2391 * final PDADC table */
2392 ath5k_combine_pwr_to_pdadc_curves(ah
, table_min
, table_max
,
2393 ee
->ee_pd_gains
[ee_mode
]);
2395 /* Write settings on hw */
2396 ath5k_setup_pwr_to_pdadc_table(ah
, pdg
, pdg_curve_to_idx
);
2398 /* Set txp.offset, note that table_min
2399 * can be negative */
2400 ah
->ah_txpower
.txp_offset
= table_min
[0];
2411 * Per-rate tx power setting
2413 * This is the code that sets the desired tx power (below
2414 * maximum) on hw for each rate (we also have TPC that sets
2415 * power per packet). We do that by providing an index on the
2416 * PCDAC/PDADC table we set up.
2420 * Set rate power table
2422 * For now we only limit txpower based on maximum tx power
2423 * supported by hw (what's inside rate_info). We need to limit
2424 * this even more, based on regulatory domain etc.
2426 * Rate power table contains indices to PCDAC/PDADC table (0.5dB steps)
2427 * and is indexed as follows:
2428 * rates[0] - rates[7] -> OFDM rates
2429 * rates[8] - rates[14] -> CCK rates
2430 * rates[15] -> XR rates (they all have the same power)
2433 ath5k_setup_rate_powertable(struct ath5k_hw
*ah
, u16 max_pwr
,
2434 struct ath5k_rate_pcal_info
*rate_info
,
2440 /* max_pwr is power level we got from driver/user in 0.5dB
2441 * units, switch to 0.25dB units so we can compare */
2443 max_pwr
= min(max_pwr
, (u16
) ah
->ah_txpower
.txp_max_pwr
) / 2;
2445 /* apply rate limits */
2446 rates
= ah
->ah_txpower
.txp_rates_power_table
;
2448 /* OFDM rates 6 to 24Mb/s */
2449 for (i
= 0; i
< 5; i
++)
2450 rates
[i
] = min(max_pwr
, rate_info
->target_power_6to24
);
2452 /* Rest OFDM rates */
2453 rates
[5] = min(rates
[0], rate_info
->target_power_36
);
2454 rates
[6] = min(rates
[0], rate_info
->target_power_48
);
2455 rates
[7] = min(rates
[0], rate_info
->target_power_54
);
2459 rates
[8] = min(rates
[0], rate_info
->target_power_6to24
);
2461 rates
[9] = min(rates
[0], rate_info
->target_power_36
);
2463 rates
[10] = min(rates
[0], rate_info
->target_power_36
);
2465 rates
[11] = min(rates
[0], rate_info
->target_power_48
);
2467 rates
[12] = min(rates
[0], rate_info
->target_power_48
);
2469 rates
[13] = min(rates
[0], rate_info
->target_power_54
);
2471 rates
[14] = min(rates
[0], rate_info
->target_power_54
);
2474 rates
[15] = min(rates
[0], rate_info
->target_power_6to24
);
2476 /* CCK rates have different peak to average ratio
2477 * so we have to tweak their power so that gainf
2478 * correction works ok. For this we use OFDM to
2479 * CCK delta from eeprom */
2480 if ((ee_mode
== AR5K_EEPROM_MODE_11G
) &&
2481 (ah
->ah_phy_revision
< AR5K_SREV_PHY_5212A
))
2482 for (i
= 8; i
<= 15; i
++)
2483 rates
[i
] -= ah
->ah_txpower
.txp_cck_ofdm_gainf_delta
;
2485 ah
->ah_txpower
.txp_min_pwr
= rates
[7];
2486 ah
->ah_txpower
.txp_max_pwr
= rates
[0];
2487 ah
->ah_txpower
.txp_ofdm
= rates
[7];
2492 * Set transmition power
2495 ath5k_hw_txpower(struct ath5k_hw
*ah
, struct ieee80211_channel
*channel
,
2496 u8 ee_mode
, u8 txpower
)
2498 struct ath5k_rate_pcal_info rate_info
;
2502 ATH5K_TRACE(ah
->ah_sc
);
2503 if (txpower
> AR5K_TUNE_MAX_TXPOWER
) {
2504 ATH5K_ERR(ah
->ah_sc
, "invalid tx power: %u\n", txpower
);
2508 txpower
= AR5K_TUNE_DEFAULT_TXPOWER
;
2510 /* Reset TX power values */
2511 memset(&ah
->ah_txpower
, 0, sizeof(ah
->ah_txpower
));
2512 ah
->ah_txpower
.txp_tpc
= AR5K_TUNE_TPC_TXPOWER
;
2513 ah
->ah_txpower
.txp_min_pwr
= 0;
2514 ah
->ah_txpower
.txp_max_pwr
= AR5K_TUNE_MAX_TXPOWER
;
2516 /* Initialize TX power table */
2517 switch (ah
->ah_radio
) {
2519 type
= AR5K_PWRTABLE_PWR_TO_PCDAC
;
2522 type
= AR5K_PWRTABLE_LINEAR_PCDAC
;
2529 type
= AR5K_PWRTABLE_PWR_TO_PDADC
;
2535 /* FIXME: Only on channel/mode change */
2536 ret
= ath5k_setup_channel_powertable(ah
, channel
, ee_mode
, type
);
2540 /* Limit max power if we have a CTL available */
2541 ath5k_get_max_ctl_power(ah
, channel
);
2543 /* FIXME: Tx power limit for this regdomain
2544 * XXX: Mac80211/CRDA will do that anyway ? */
2546 /* FIXME: Antenna reduction stuff */
2548 /* FIXME: Limit power on turbo modes */
2550 /* FIXME: TPC scale reduction */
2552 /* Get surounding channels for per-rate power table
2554 ath5k_get_rate_pcal_data(ah
, channel
, &rate_info
);
2556 /* Setup rate power table */
2557 ath5k_setup_rate_powertable(ah
, txpower
, &rate_info
, ee_mode
);
2559 /* Write rate power table on hw */
2560 ath5k_hw_reg_write(ah
, AR5K_TXPOWER_OFDM(3, 24) |
2561 AR5K_TXPOWER_OFDM(2, 16) | AR5K_TXPOWER_OFDM(1, 8) |
2562 AR5K_TXPOWER_OFDM(0, 0), AR5K_PHY_TXPOWER_RATE1
);
2564 ath5k_hw_reg_write(ah
, AR5K_TXPOWER_OFDM(7, 24) |
2565 AR5K_TXPOWER_OFDM(6, 16) | AR5K_TXPOWER_OFDM(5, 8) |
2566 AR5K_TXPOWER_OFDM(4, 0), AR5K_PHY_TXPOWER_RATE2
);
2568 ath5k_hw_reg_write(ah
, AR5K_TXPOWER_CCK(10, 24) |
2569 AR5K_TXPOWER_CCK(9, 16) | AR5K_TXPOWER_CCK(15, 8) |
2570 AR5K_TXPOWER_CCK(8, 0), AR5K_PHY_TXPOWER_RATE3
);
2572 ath5k_hw_reg_write(ah
, AR5K_TXPOWER_CCK(14, 24) |
2573 AR5K_TXPOWER_CCK(13, 16) | AR5K_TXPOWER_CCK(12, 8) |
2574 AR5K_TXPOWER_CCK(11, 0), AR5K_PHY_TXPOWER_RATE4
);
2576 /* FIXME: TPC support */
2577 if (ah
->ah_txpower
.txp_tpc
) {
2578 ath5k_hw_reg_write(ah
, AR5K_PHY_TXPOWER_RATE_MAX_TPC_ENABLE
|
2579 AR5K_TUNE_MAX_TXPOWER
, AR5K_PHY_TXPOWER_RATE_MAX
);
2581 ath5k_hw_reg_write(ah
,
2582 AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER
, AR5K_TPC_ACK
) |
2583 AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER
, AR5K_TPC_CTS
) |
2584 AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER
, AR5K_TPC_CHIRP
),
2587 ath5k_hw_reg_write(ah
, AR5K_PHY_TXPOWER_RATE_MAX
|
2588 AR5K_TUNE_MAX_TXPOWER
, AR5K_PHY_TXPOWER_RATE_MAX
);
2594 int ath5k_hw_set_txpower_limit(struct ath5k_hw
*ah
, u8 mode
, u8 txpower
)
2597 struct ieee80211_channel
*channel
= &ah
->ah_current_channel
;
2599 ATH5K_TRACE(ah
->ah_sc
);
2600 ATH5K_DBG(ah
->ah_sc
, ATH5K_DEBUG_TXPOWER
,
2601 "changing txpower to %d\n", txpower
);
2603 return ath5k_hw_txpower(ah
, channel
, mode
, txpower
);