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Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wirel...
[deliverable/linux.git] / drivers / net / wireless / ath9k / ath9k.h
1 /*
2 * Copyright (c) 2008 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #ifndef ATH9K_H
18 #define ATH9K_H
19
20 #include <linux/io.h>
21
22 #define ATHEROS_VENDOR_ID 0x168c
23
24 #define AR5416_DEVID_PCI 0x0023
25 #define AR5416_DEVID_PCIE 0x0024
26 #define AR9160_DEVID_PCI 0x0027
27 #define AR9280_DEVID_PCI 0x0029
28 #define AR9280_DEVID_PCIE 0x002a
29
30 #define AR5416_AR9100_DEVID 0x000b
31
32 #define AR_SUBVENDOR_ID_NOG 0x0e11
33 #define AR_SUBVENDOR_ID_NEW_A 0x7065
34
35 #define ATH9K_TXERR_XRETRY 0x01
36 #define ATH9K_TXERR_FILT 0x02
37 #define ATH9K_TXERR_FIFO 0x04
38 #define ATH9K_TXERR_XTXOP 0x08
39 #define ATH9K_TXERR_TIMER_EXPIRED 0x10
40
41 #define ATH9K_TX_BA 0x01
42 #define ATH9K_TX_PWRMGMT 0x02
43 #define ATH9K_TX_DESC_CFG_ERR 0x04
44 #define ATH9K_TX_DATA_UNDERRUN 0x08
45 #define ATH9K_TX_DELIM_UNDERRUN 0x10
46 #define ATH9K_TX_SW_ABORTED 0x40
47 #define ATH9K_TX_SW_FILTERED 0x80
48
49 #define NBBY 8
50
51 struct ath_tx_status {
52 u32 ts_tstamp;
53 u16 ts_seqnum;
54 u8 ts_status;
55 u8 ts_ratecode;
56 u8 ts_rateindex;
57 int8_t ts_rssi;
58 u8 ts_shortretry;
59 u8 ts_longretry;
60 u8 ts_virtcol;
61 u8 ts_antenna;
62 u8 ts_flags;
63 int8_t ts_rssi_ctl0;
64 int8_t ts_rssi_ctl1;
65 int8_t ts_rssi_ctl2;
66 int8_t ts_rssi_ext0;
67 int8_t ts_rssi_ext1;
68 int8_t ts_rssi_ext2;
69 u8 pad[3];
70 u32 ba_low;
71 u32 ba_high;
72 u32 evm0;
73 u32 evm1;
74 u32 evm2;
75 };
76
77 struct ath_rx_status {
78 u32 rs_tstamp;
79 u16 rs_datalen;
80 u8 rs_status;
81 u8 rs_phyerr;
82 int8_t rs_rssi;
83 u8 rs_keyix;
84 u8 rs_rate;
85 u8 rs_antenna;
86 u8 rs_more;
87 int8_t rs_rssi_ctl0;
88 int8_t rs_rssi_ctl1;
89 int8_t rs_rssi_ctl2;
90 int8_t rs_rssi_ext0;
91 int8_t rs_rssi_ext1;
92 int8_t rs_rssi_ext2;
93 u8 rs_isaggr;
94 u8 rs_moreaggr;
95 u8 rs_num_delims;
96 u8 rs_flags;
97 u32 evm0;
98 u32 evm1;
99 u32 evm2;
100 };
101
102 #define ATH9K_RXERR_CRC 0x01
103 #define ATH9K_RXERR_PHY 0x02
104 #define ATH9K_RXERR_FIFO 0x04
105 #define ATH9K_RXERR_DECRYPT 0x08
106 #define ATH9K_RXERR_MIC 0x10
107
108 #define ATH9K_RX_MORE 0x01
109 #define ATH9K_RX_MORE_AGGR 0x02
110 #define ATH9K_RX_GI 0x04
111 #define ATH9K_RX_2040 0x08
112 #define ATH9K_RX_DELIM_CRC_PRE 0x10
113 #define ATH9K_RX_DELIM_CRC_POST 0x20
114 #define ATH9K_RX_DECRYPT_BUSY 0x40
115
116 #define ATH9K_RXKEYIX_INVALID ((u8)-1)
117 #define ATH9K_TXKEYIX_INVALID ((u32)-1)
118
119 struct ath_desc {
120 u32 ds_link;
121 u32 ds_data;
122 u32 ds_ctl0;
123 u32 ds_ctl1;
124 u32 ds_hw[20];
125 union {
126 struct ath_tx_status tx;
127 struct ath_rx_status rx;
128 void *stats;
129 } ds_us;
130 void *ds_vdata;
131 } __packed;
132
133 #define ds_txstat ds_us.tx
134 #define ds_rxstat ds_us.rx
135 #define ds_stat ds_us.stats
136
137 #define ATH9K_TXDESC_CLRDMASK 0x0001
138 #define ATH9K_TXDESC_NOACK 0x0002
139 #define ATH9K_TXDESC_RTSENA 0x0004
140 #define ATH9K_TXDESC_CTSENA 0x0008
141 /* ATH9K_TXDESC_INTREQ forces a tx interrupt to be generated for
142 * the descriptor its marked on. We take a tx interrupt to reap
143 * descriptors when the h/w hits an EOL condition or
144 * when the descriptor is specifically marked to generate
145 * an interrupt with this flag. Descriptors should be
146 * marked periodically to insure timely replenishing of the
147 * supply needed for sending frames. Defering interrupts
148 * reduces system load and potentially allows more concurrent
149 * work to be done but if done to aggressively can cause
150 * senders to backup. When the hardware queue is left too
151 * large rate control information may also be too out of
152 * date. An Alternative for this is TX interrupt mitigation
153 * but this needs more testing. */
154 #define ATH9K_TXDESC_INTREQ 0x0010
155 #define ATH9K_TXDESC_VEOL 0x0020
156 #define ATH9K_TXDESC_EXT_ONLY 0x0040
157 #define ATH9K_TXDESC_EXT_AND_CTL 0x0080
158 #define ATH9K_TXDESC_VMF 0x0100
159 #define ATH9K_TXDESC_FRAG_IS_ON 0x0200
160 #define ATH9K_TXDESC_CAB 0x0400
161
162 #define ATH9K_RXDESC_INTREQ 0x0020
163
164 enum wireless_mode {
165 ATH9K_MODE_11A = 0,
166 ATH9K_MODE_11B = 2,
167 ATH9K_MODE_11G = 3,
168 ATH9K_MODE_11NA_HT20 = 6,
169 ATH9K_MODE_11NG_HT20 = 7,
170 ATH9K_MODE_11NA_HT40PLUS = 8,
171 ATH9K_MODE_11NA_HT40MINUS = 9,
172 ATH9K_MODE_11NG_HT40PLUS = 10,
173 ATH9K_MODE_11NG_HT40MINUS = 11,
174 ATH9K_MODE_MAX
175 };
176
177 enum ath9k_hw_caps {
178 ATH9K_HW_CAP_CHAN_SPREAD = BIT(0),
179 ATH9K_HW_CAP_MIC_AESCCM = BIT(1),
180 ATH9K_HW_CAP_MIC_CKIP = BIT(2),
181 ATH9K_HW_CAP_MIC_TKIP = BIT(3),
182 ATH9K_HW_CAP_CIPHER_AESCCM = BIT(4),
183 ATH9K_HW_CAP_CIPHER_CKIP = BIT(5),
184 ATH9K_HW_CAP_CIPHER_TKIP = BIT(6),
185 ATH9K_HW_CAP_VEOL = BIT(7),
186 ATH9K_HW_CAP_BSSIDMASK = BIT(8),
187 ATH9K_HW_CAP_MCAST_KEYSEARCH = BIT(9),
188 ATH9K_HW_CAP_CHAN_HALFRATE = BIT(10),
189 ATH9K_HW_CAP_CHAN_QUARTERRATE = BIT(11),
190 ATH9K_HW_CAP_HT = BIT(12),
191 ATH9K_HW_CAP_GTT = BIT(13),
192 ATH9K_HW_CAP_FASTCC = BIT(14),
193 ATH9K_HW_CAP_RFSILENT = BIT(15),
194 ATH9K_HW_CAP_WOW = BIT(16),
195 ATH9K_HW_CAP_CST = BIT(17),
196 ATH9K_HW_CAP_ENHANCEDPM = BIT(18),
197 ATH9K_HW_CAP_AUTOSLEEP = BIT(19),
198 ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(20),
199 ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT = BIT(21),
200 };
201
202 enum ath9k_capability_type {
203 ATH9K_CAP_CIPHER = 0,
204 ATH9K_CAP_TKIP_MIC,
205 ATH9K_CAP_TKIP_SPLIT,
206 ATH9K_CAP_PHYCOUNTERS,
207 ATH9K_CAP_DIVERSITY,
208 ATH9K_CAP_TXPOW,
209 ATH9K_CAP_PHYDIAG,
210 ATH9K_CAP_MCAST_KEYSRCH,
211 ATH9K_CAP_TSF_ADJUST,
212 ATH9K_CAP_WME_TKIPMIC,
213 ATH9K_CAP_RFSILENT,
214 ATH9K_CAP_ANT_CFG_2GHZ,
215 ATH9K_CAP_ANT_CFG_5GHZ
216 };
217
218 struct ath9k_hw_capabilities {
219 u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */
220 DECLARE_BITMAP(wireless_modes, ATH9K_MODE_MAX); /* ATH9K_MODE_* */
221 u16 total_queues;
222 u16 keycache_size;
223 u16 low_5ghz_chan, high_5ghz_chan;
224 u16 low_2ghz_chan, high_2ghz_chan;
225 u16 num_mr_retries;
226 u16 rts_aggr_limit;
227 u8 tx_chainmask;
228 u8 rx_chainmask;
229 u16 tx_triglevel_max;
230 u16 reg_cap;
231 u8 num_gpio_pins;
232 u8 num_antcfg_2ghz;
233 u8 num_antcfg_5ghz;
234 };
235
236 struct ath9k_ops_config {
237 int dma_beacon_response_time;
238 int sw_beacon_response_time;
239 int additional_swba_backoff;
240 int ack_6mb;
241 int cwm_ignore_extcca;
242 u8 pcie_powersave_enable;
243 u8 pcie_l1skp_enable;
244 u8 pcie_clock_req;
245 u32 pcie_waen;
246 int pcie_power_reset;
247 u8 pcie_restore;
248 u8 analog_shiftreg;
249 u8 ht_enable;
250 u32 ofdm_trig_low;
251 u32 ofdm_trig_high;
252 u32 cck_trig_high;
253 u32 cck_trig_low;
254 u32 enable_ani;
255 u8 noise_immunity_level;
256 u32 ofdm_weaksignal_det;
257 u32 cck_weaksignal_thr;
258 u8 spur_immunity_level;
259 u8 firstep_level;
260 int8_t rssi_thr_high;
261 int8_t rssi_thr_low;
262 u16 diversity_control;
263 u16 antenna_switch_swap;
264 int serialize_regmode;
265 int intr_mitigation;
266 #define SPUR_DISABLE 0
267 #define SPUR_ENABLE_IOCTL 1
268 #define SPUR_ENABLE_EEPROM 2
269 #define AR_EEPROM_MODAL_SPURS 5
270 #define AR_SPUR_5413_1 1640
271 #define AR_SPUR_5413_2 1200
272 #define AR_NO_SPUR 0x8000
273 #define AR_BASE_FREQ_2GHZ 2300
274 #define AR_BASE_FREQ_5GHZ 4900
275 #define AR_SPUR_FEEQ_BOUND_HT40 19
276 #define AR_SPUR_FEEQ_BOUND_HT20 10
277 int spurmode;
278 u16 spurchans[AR_EEPROM_MODAL_SPURS][2];
279 };
280
281 enum ath9k_tx_queue {
282 ATH9K_TX_QUEUE_INACTIVE = 0,
283 ATH9K_TX_QUEUE_DATA,
284 ATH9K_TX_QUEUE_BEACON,
285 ATH9K_TX_QUEUE_CAB,
286 ATH9K_TX_QUEUE_UAPSD,
287 ATH9K_TX_QUEUE_PSPOLL
288 };
289
290 #define ATH9K_NUM_TX_QUEUES 10
291
292 enum ath9k_tx_queue_subtype {
293 ATH9K_WME_AC_BK = 0,
294 ATH9K_WME_AC_BE,
295 ATH9K_WME_AC_VI,
296 ATH9K_WME_AC_VO,
297 ATH9K_WME_UPSD
298 };
299
300 enum ath9k_tx_queue_flags {
301 TXQ_FLAG_TXOKINT_ENABLE = 0x0001,
302 TXQ_FLAG_TXERRINT_ENABLE = 0x0001,
303 TXQ_FLAG_TXDESCINT_ENABLE = 0x0002,
304 TXQ_FLAG_TXEOLINT_ENABLE = 0x0004,
305 TXQ_FLAG_TXURNINT_ENABLE = 0x0008,
306 TXQ_FLAG_BACKOFF_DISABLE = 0x0010,
307 TXQ_FLAG_COMPRESSION_ENABLE = 0x0020,
308 TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE = 0x0040,
309 TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE = 0x0080,
310 };
311
312 #define ATH9K_TXQ_USEDEFAULT ((u32) -1)
313
314 #define ATH9K_DECOMP_MASK_SIZE 128
315 #define ATH9K_READY_TIME_LO_BOUND 50
316 #define ATH9K_READY_TIME_HI_BOUND 96
317
318 enum ath9k_pkt_type {
319 ATH9K_PKT_TYPE_NORMAL = 0,
320 ATH9K_PKT_TYPE_ATIM,
321 ATH9K_PKT_TYPE_PSPOLL,
322 ATH9K_PKT_TYPE_BEACON,
323 ATH9K_PKT_TYPE_PROBE_RESP,
324 ATH9K_PKT_TYPE_CHIRP,
325 ATH9K_PKT_TYPE_GRP_POLL,
326 };
327
328 struct ath9k_tx_queue_info {
329 u32 tqi_ver;
330 enum ath9k_tx_queue tqi_type;
331 enum ath9k_tx_queue_subtype tqi_subtype;
332 enum ath9k_tx_queue_flags tqi_qflags;
333 u32 tqi_priority;
334 u32 tqi_aifs;
335 u32 tqi_cwmin;
336 u32 tqi_cwmax;
337 u16 tqi_shretry;
338 u16 tqi_lgretry;
339 u32 tqi_cbrPeriod;
340 u32 tqi_cbrOverflowLimit;
341 u32 tqi_burstTime;
342 u32 tqi_readyTime;
343 u32 tqi_physCompBuf;
344 u32 tqi_intFlags;
345 };
346
347 enum ath9k_rx_filter {
348 ATH9K_RX_FILTER_UCAST = 0x00000001,
349 ATH9K_RX_FILTER_MCAST = 0x00000002,
350 ATH9K_RX_FILTER_BCAST = 0x00000004,
351 ATH9K_RX_FILTER_CONTROL = 0x00000008,
352 ATH9K_RX_FILTER_BEACON = 0x00000010,
353 ATH9K_RX_FILTER_PROM = 0x00000020,
354 ATH9K_RX_FILTER_PROBEREQ = 0x00000080,
355 ATH9K_RX_FILTER_PSPOLL = 0x00004000,
356 ATH9K_RX_FILTER_PHYERR = 0x00000100,
357 ATH9K_RX_FILTER_PHYRADAR = 0x00002000,
358 };
359
360 enum ath9k_int {
361 ATH9K_INT_RX = 0x00000001,
362 ATH9K_INT_RXDESC = 0x00000002,
363 ATH9K_INT_RXNOFRM = 0x00000008,
364 ATH9K_INT_RXEOL = 0x00000010,
365 ATH9K_INT_RXORN = 0x00000020,
366 ATH9K_INT_TX = 0x00000040,
367 ATH9K_INT_TXDESC = 0x00000080,
368 ATH9K_INT_TIM_TIMER = 0x00000100,
369 ATH9K_INT_TXURN = 0x00000800,
370 ATH9K_INT_MIB = 0x00001000,
371 ATH9K_INT_RXPHY = 0x00004000,
372 ATH9K_INT_RXKCM = 0x00008000,
373 ATH9K_INT_SWBA = 0x00010000,
374 ATH9K_INT_BMISS = 0x00040000,
375 ATH9K_INT_BNR = 0x00100000,
376 ATH9K_INT_TIM = 0x00200000,
377 ATH9K_INT_DTIM = 0x00400000,
378 ATH9K_INT_DTIMSYNC = 0x00800000,
379 ATH9K_INT_GPIO = 0x01000000,
380 ATH9K_INT_CABEND = 0x02000000,
381 ATH9K_INT_CST = 0x10000000,
382 ATH9K_INT_GTT = 0x20000000,
383 ATH9K_INT_FATAL = 0x40000000,
384 ATH9K_INT_GLOBAL = 0x80000000,
385 ATH9K_INT_BMISC = ATH9K_INT_TIM |
386 ATH9K_INT_DTIM |
387 ATH9K_INT_DTIMSYNC |
388 ATH9K_INT_CABEND,
389 ATH9K_INT_COMMON = ATH9K_INT_RXNOFRM |
390 ATH9K_INT_RXDESC |
391 ATH9K_INT_RXEOL |
392 ATH9K_INT_RXORN |
393 ATH9K_INT_TXURN |
394 ATH9K_INT_TXDESC |
395 ATH9K_INT_MIB |
396 ATH9K_INT_RXPHY |
397 ATH9K_INT_RXKCM |
398 ATH9K_INT_SWBA |
399 ATH9K_INT_BMISS |
400 ATH9K_INT_GPIO,
401 ATH9K_INT_NOCARD = 0xffffffff
402 };
403
404 #define ATH9K_RATESERIES_RTS_CTS 0x0001
405 #define ATH9K_RATESERIES_2040 0x0002
406 #define ATH9K_RATESERIES_HALFGI 0x0004
407
408 struct ath9k_11n_rate_series {
409 u32 Tries;
410 u32 Rate;
411 u32 PktDuration;
412 u32 ChSel;
413 u32 RateFlags;
414 };
415
416 #define CHANNEL_CW_INT 0x00002
417 #define CHANNEL_CCK 0x00020
418 #define CHANNEL_OFDM 0x00040
419 #define CHANNEL_2GHZ 0x00080
420 #define CHANNEL_5GHZ 0x00100
421 #define CHANNEL_PASSIVE 0x00200
422 #define CHANNEL_DYN 0x00400
423 #define CHANNEL_HALF 0x04000
424 #define CHANNEL_QUARTER 0x08000
425 #define CHANNEL_HT20 0x10000
426 #define CHANNEL_HT40PLUS 0x20000
427 #define CHANNEL_HT40MINUS 0x40000
428
429 #define CHANNEL_INTERFERENCE 0x01
430 #define CHANNEL_DFS 0x02
431 #define CHANNEL_4MS_LIMIT 0x04
432 #define CHANNEL_DFS_CLEAR 0x08
433 #define CHANNEL_DISALLOW_ADHOC 0x10
434 #define CHANNEL_PER_11D_ADHOC 0x20
435
436 #define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM)
437 #define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK)
438 #define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM)
439 #define CHANNEL_G_HT20 (CHANNEL_2GHZ|CHANNEL_HT20)
440 #define CHANNEL_A_HT20 (CHANNEL_5GHZ|CHANNEL_HT20)
441 #define CHANNEL_G_HT40PLUS (CHANNEL_2GHZ|CHANNEL_HT40PLUS)
442 #define CHANNEL_G_HT40MINUS (CHANNEL_2GHZ|CHANNEL_HT40MINUS)
443 #define CHANNEL_A_HT40PLUS (CHANNEL_5GHZ|CHANNEL_HT40PLUS)
444 #define CHANNEL_A_HT40MINUS (CHANNEL_5GHZ|CHANNEL_HT40MINUS)
445 #define CHANNEL_ALL \
446 (CHANNEL_OFDM| \
447 CHANNEL_CCK| \
448 CHANNEL_2GHZ | \
449 CHANNEL_5GHZ | \
450 CHANNEL_HT20 | \
451 CHANNEL_HT40PLUS | \
452 CHANNEL_HT40MINUS)
453
454 struct ath9k_channel {
455 u16 channel;
456 u32 channelFlags;
457 u8 privFlags;
458 int8_t maxRegTxPower;
459 int8_t maxTxPower;
460 int8_t minTxPower;
461 u32 chanmode;
462 int32_t CalValid;
463 bool oneTimeCalsDone;
464 int8_t iCoff;
465 int8_t qCoff;
466 int16_t rawNoiseFloor;
467 int8_t antennaMax;
468 u32 regDmnFlags;
469 u32 conformanceTestLimit[3]; /* 0:11a, 1: 11b, 2:11g */
470 #ifdef ATH_NF_PER_CHAN
471 struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
472 #endif
473 };
474
475 #define IS_CHAN_A(_c) ((((_c)->channelFlags & CHANNEL_A) == CHANNEL_A) || \
476 (((_c)->channelFlags & CHANNEL_A_HT20) == CHANNEL_A_HT20) || \
477 (((_c)->channelFlags & CHANNEL_A_HT40PLUS) == CHANNEL_A_HT40PLUS) || \
478 (((_c)->channelFlags & CHANNEL_A_HT40MINUS) == CHANNEL_A_HT40MINUS))
479 #define IS_CHAN_G(_c) ((((_c)->channelFlags & (CHANNEL_G)) == CHANNEL_G) || \
480 (((_c)->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20) || \
481 (((_c)->channelFlags & CHANNEL_G_HT40PLUS) == CHANNEL_G_HT40PLUS) || \
482 (((_c)->channelFlags & CHANNEL_G_HT40MINUS) == CHANNEL_G_HT40MINUS))
483 #define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0)
484 #define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0)
485 #define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0)
486 #define IS_CHAN_PASSIVE(_c) (((_c)->channelFlags & CHANNEL_PASSIVE) != 0)
487 #define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0)
488 #define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0)
489
490 /* These macros check chanmode and not channelFlags */
491 #define IS_CHAN_B(_c) ((_c)->chanmode == CHANNEL_B)
492 #define IS_CHAN_HT20(_c) (((_c)->chanmode == CHANNEL_A_HT20) || \
493 ((_c)->chanmode == CHANNEL_G_HT20))
494 #define IS_CHAN_HT40(_c) (((_c)->chanmode == CHANNEL_A_HT40PLUS) || \
495 ((_c)->chanmode == CHANNEL_A_HT40MINUS) || \
496 ((_c)->chanmode == CHANNEL_G_HT40PLUS) || \
497 ((_c)->chanmode == CHANNEL_G_HT40MINUS))
498 #define IS_CHAN_HT(_c) (IS_CHAN_HT20((_c)) || IS_CHAN_HT40((_c)))
499
500 #define IS_CHAN_IN_PUBLIC_SAFETY_BAND(_c) ((_c) > 4940 && (_c) < 4990)
501 #define IS_CHAN_A_5MHZ_SPACED(_c) \
502 ((((_c)->channelFlags & CHANNEL_5GHZ) != 0) && \
503 (((_c)->channel % 20) != 0) && \
504 (((_c)->channel % 10) != 0))
505
506 struct ath9k_keyval {
507 u8 kv_type;
508 u8 kv_pad;
509 u16 kv_len;
510 u8 kv_val[16];
511 u8 kv_mic[8];
512 u8 kv_txmic[8];
513 };
514
515 enum ath9k_key_type {
516 ATH9K_KEY_TYPE_CLEAR,
517 ATH9K_KEY_TYPE_WEP,
518 ATH9K_KEY_TYPE_AES,
519 ATH9K_KEY_TYPE_TKIP,
520 };
521
522 enum ath9k_cipher {
523 ATH9K_CIPHER_WEP = 0,
524 ATH9K_CIPHER_AES_OCB = 1,
525 ATH9K_CIPHER_AES_CCM = 2,
526 ATH9K_CIPHER_CKIP = 3,
527 ATH9K_CIPHER_TKIP = 4,
528 ATH9K_CIPHER_CLR = 5,
529 ATH9K_CIPHER_MIC = 127
530 };
531
532 #define AR_EEPROM_EEPCAP_COMPRESS_DIS 0x0001
533 #define AR_EEPROM_EEPCAP_AES_DIS 0x0002
534 #define AR_EEPROM_EEPCAP_FASTFRAME_DIS 0x0004
535 #define AR_EEPROM_EEPCAP_BURST_DIS 0x0008
536 #define AR_EEPROM_EEPCAP_MAXQCU 0x01F0
537 #define AR_EEPROM_EEPCAP_MAXQCU_S 4
538 #define AR_EEPROM_EEPCAP_HEAVY_CLIP_EN 0x0200
539 #define AR_EEPROM_EEPCAP_KC_ENTRIES 0xF000
540 #define AR_EEPROM_EEPCAP_KC_ENTRIES_S 12
541
542 #define AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND 0x0040
543 #define AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN 0x0080
544 #define AR_EEPROM_EEREGCAP_EN_KK_U2 0x0100
545 #define AR_EEPROM_EEREGCAP_EN_KK_MIDBAND 0x0200
546 #define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD 0x0400
547 #define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A 0x0800
548
549 #define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD_PRE4_0 0x4000
550 #define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A_PRE4_0 0x8000
551
552 #define SD_NO_CTL 0xE0
553 #define NO_CTL 0xff
554 #define CTL_MODE_M 7
555 #define CTL_11A 0
556 #define CTL_11B 1
557 #define CTL_11G 2
558 #define CTL_2GHT20 5
559 #define CTL_5GHT20 6
560 #define CTL_2GHT40 7
561 #define CTL_5GHT40 8
562
563 #define AR_EEPROM_MAC(i) (0x1d+(i))
564
565 #define AR_EEPROM_RFSILENT_GPIO_SEL 0x001c
566 #define AR_EEPROM_RFSILENT_GPIO_SEL_S 2
567 #define AR_EEPROM_RFSILENT_POLARITY 0x0002
568 #define AR_EEPROM_RFSILENT_POLARITY_S 1
569
570 #define CTRY_DEBUG 0x1ff
571 #define CTRY_DEFAULT 0
572
573 enum reg_ext_bitmap {
574 REG_EXT_JAPAN_MIDBAND = 1,
575 REG_EXT_FCC_DFS_HT40 = 2,
576 REG_EXT_JAPAN_NONDFS_HT40 = 3,
577 REG_EXT_JAPAN_DFS_HT40 = 4
578 };
579
580 struct ath9k_country_entry {
581 u16 countryCode;
582 u16 regDmnEnum;
583 u16 regDmn5G;
584 u16 regDmn2G;
585 u8 isMultidomain;
586 u8 iso[3];
587 };
588
589 #define REG_WRITE(_ah, _reg, _val) iowrite32(_val, _ah->ah_sh + _reg)
590 #define REG_READ(_ah, _reg) ioread32(_ah->ah_sh + _reg)
591
592 #define SM(_v, _f) (((_v) << _f##_S) & _f)
593 #define MS(_v, _f) (((_v) & _f) >> _f##_S)
594 #define REG_RMW(_a, _r, _set, _clr) \
595 REG_WRITE(_a, _r, (REG_READ(_a, _r) & ~(_clr)) | (_set))
596 #define REG_RMW_FIELD(_a, _r, _f, _v) \
597 REG_WRITE(_a, _r, \
598 (REG_READ(_a, _r) & ~_f) | (((_v) << _f##_S) & _f))
599 #define REG_SET_BIT(_a, _r, _f) \
600 REG_WRITE(_a, _r, REG_READ(_a, _r) | _f)
601 #define REG_CLR_BIT(_a, _r, _f) \
602 REG_WRITE(_a, _r, REG_READ(_a, _r) & ~_f)
603
604 #define ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS 0x00000001
605
606 #define INIT_AIFS 2
607 #define INIT_CWMIN 15
608 #define INIT_CWMIN_11B 31
609 #define INIT_CWMAX 1023
610 #define INIT_SH_RETRY 10
611 #define INIT_LG_RETRY 10
612 #define INIT_SSH_RETRY 32
613 #define INIT_SLG_RETRY 32
614
615 #define WLAN_CTRL_FRAME_SIZE (2+2+6+4)
616
617 #define ATH_AMPDU_LIMIT_MAX (64 * 1024 - 1)
618 #define ATH_AMPDU_LIMIT_DEFAULT ATH_AMPDU_LIMIT_MAX
619
620 #define IEEE80211_WEP_IVLEN 3
621 #define IEEE80211_WEP_KIDLEN 1
622 #define IEEE80211_WEP_CRCLEN 4
623 #define IEEE80211_MAX_MPDU_LEN (3840 + FCS_LEN + \
624 (IEEE80211_WEP_IVLEN + \
625 IEEE80211_WEP_KIDLEN + \
626 IEEE80211_WEP_CRCLEN))
627 #define MAX_RATE_POWER 63
628
629 enum ath9k_power_mode {
630 ATH9K_PM_AWAKE = 0,
631 ATH9K_PM_FULL_SLEEP,
632 ATH9K_PM_NETWORK_SLEEP,
633 ATH9K_PM_UNDEFINED
634 };
635
636 struct ath9k_mib_stats {
637 u32 ackrcv_bad;
638 u32 rts_bad;
639 u32 rts_good;
640 u32 fcs_bad;
641 u32 beacons;
642 };
643
644 enum ath9k_ant_setting {
645 ATH9K_ANT_VARIABLE = 0,
646 ATH9K_ANT_FIXED_A,
647 ATH9K_ANT_FIXED_B
648 };
649
650 #define ATH9K_SLOT_TIME_6 6
651 #define ATH9K_SLOT_TIME_9 9
652 #define ATH9K_SLOT_TIME_20 20
653
654 enum ath9k_ht_macmode {
655 ATH9K_HT_MACMODE_20 = 0,
656 ATH9K_HT_MACMODE_2040 = 1,
657 };
658
659 enum ath9k_ht_extprotspacing {
660 ATH9K_HT_EXTPROTSPACING_20 = 0,
661 ATH9K_HT_EXTPROTSPACING_25 = 1,
662 };
663
664 struct ath9k_ht_cwm {
665 enum ath9k_ht_macmode ht_macmode;
666 enum ath9k_ht_extprotspacing ht_extprotspacing;
667 };
668
669 enum ath9k_ani_cmd {
670 ATH9K_ANI_PRESENT = 0x1,
671 ATH9K_ANI_NOISE_IMMUNITY_LEVEL = 0x2,
672 ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION = 0x4,
673 ATH9K_ANI_CCK_WEAK_SIGNAL_THR = 0x8,
674 ATH9K_ANI_FIRSTEP_LEVEL = 0x10,
675 ATH9K_ANI_SPUR_IMMUNITY_LEVEL = 0x20,
676 ATH9K_ANI_MODE = 0x40,
677 ATH9K_ANI_PHYERR_RESET = 0x80,
678 ATH9K_ANI_ALL = 0xff
679 };
680
681 enum {
682 WLAN_RC_PHY_OFDM,
683 WLAN_RC_PHY_CCK,
684 WLAN_RC_PHY_HT_20_SS,
685 WLAN_RC_PHY_HT_20_DS,
686 WLAN_RC_PHY_HT_40_SS,
687 WLAN_RC_PHY_HT_40_DS,
688 WLAN_RC_PHY_HT_20_SS_HGI,
689 WLAN_RC_PHY_HT_20_DS_HGI,
690 WLAN_RC_PHY_HT_40_SS_HGI,
691 WLAN_RC_PHY_HT_40_DS_HGI,
692 WLAN_RC_PHY_MAX
693 };
694
695 enum ath9k_tp_scale {
696 ATH9K_TP_SCALE_MAX = 0,
697 ATH9K_TP_SCALE_50,
698 ATH9K_TP_SCALE_25,
699 ATH9K_TP_SCALE_12,
700 ATH9K_TP_SCALE_MIN
701 };
702
703 enum ser_reg_mode {
704 SER_REG_MODE_OFF = 0,
705 SER_REG_MODE_ON = 1,
706 SER_REG_MODE_AUTO = 2,
707 };
708
709 #define AR_PHY_CCA_MAX_GOOD_VALUE -85
710 #define AR_PHY_CCA_MAX_HIGH_VALUE -62
711 #define AR_PHY_CCA_MIN_BAD_VALUE -121
712 #define AR_PHY_CCA_FILTERWINDOW_LENGTH_INIT 3
713 #define AR_PHY_CCA_FILTERWINDOW_LENGTH 5
714
715 #define ATH9K_NF_CAL_HIST_MAX 5
716 #define NUM_NF_READINGS 6
717
718 struct ath9k_nfcal_hist {
719 int16_t nfCalBuffer[ATH9K_NF_CAL_HIST_MAX];
720 u8 currIndex;
721 int16_t privNF;
722 u8 invalidNFcount;
723 };
724
725 struct ath9k_beacon_state {
726 u32 bs_nexttbtt;
727 u32 bs_nextdtim;
728 u32 bs_intval;
729 #define ATH9K_BEACON_PERIOD 0x0000ffff
730 #define ATH9K_BEACON_ENA 0x00800000
731 #define ATH9K_BEACON_RESET_TSF 0x01000000
732 u32 bs_dtimperiod;
733 u16 bs_cfpperiod;
734 u16 bs_cfpmaxduration;
735 u32 bs_cfpnext;
736 u16 bs_timoffset;
737 u16 bs_bmissthreshold;
738 u32 bs_sleepduration;
739 };
740
741 struct ath9k_node_stats {
742 u32 ns_avgbrssi;
743 u32 ns_avgrssi;
744 u32 ns_avgtxrssi;
745 u32 ns_avgtxrate;
746 };
747
748 #define ATH9K_RSSI_EP_MULTIPLIER (1<<7)
749
750 #define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0
751 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1
752 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2
753 #define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5
754 #define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6
755
756 enum {
757 ATH9K_RESET_POWER_ON,
758 ATH9K_RESET_WARM,
759 ATH9K_RESET_COLD,
760 };
761
762 #define AH_USE_EEPROM 0x1
763
764 struct ath_hal {
765 u32 ah_magic;
766 u16 ah_devid;
767 u16 ah_subvendorid;
768 u32 ah_macVersion;
769 u16 ah_macRev;
770 u16 ah_phyRev;
771 u16 ah_analog5GhzRev;
772 u16 ah_analog2GhzRev;
773
774 void __iomem *ah_sh;
775 struct ath_softc *ah_sc;
776
777 enum nl80211_iftype ah_opmode;
778 struct ath9k_ops_config ah_config;
779 struct ath9k_hw_capabilities ah_caps;
780
781 u16 ah_countryCode;
782 u32 ah_flags;
783 int16_t ah_powerLimit;
784 u16 ah_maxPowerLevel;
785 u32 ah_tpScale;
786 u16 ah_currentRD;
787 u16 ah_currentRDExt;
788 u16 ah_currentRDInUse;
789 u16 ah_currentRD5G;
790 u16 ah_currentRD2G;
791 char ah_iso[4];
792
793 struct ath9k_channel ah_channels[150];
794 struct ath9k_channel *ah_curchan;
795 u32 ah_nchan;
796
797 bool ah_isPciExpress;
798 u16 ah_txTrigLevel;
799 u16 ah_rfsilent;
800 u32 ah_rfkill_gpio;
801 u32 ah_rfkill_polarity;
802
803 #ifndef ATH_NF_PER_CHAN
804 struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
805 #endif
806 };
807
808 struct chan_centers {
809 u16 synth_center;
810 u16 ctl_center;
811 u16 ext_center;
812 };
813
814 struct ath_rate_table;
815
816 /* Helpers */
817
818 enum wireless_mode ath9k_hw_chan2wmode(struct ath_hal *ah,
819 const struct ath9k_channel *chan);
820 bool ath9k_hw_wait(struct ath_hal *ah, u32 reg, u32 mask, u32 val);
821 u32 ath9k_hw_reverse_bits(u32 val, u32 n);
822 bool ath9k_get_channel_edges(struct ath_hal *ah,
823 u16 flags, u16 *low,
824 u16 *high);
825 u16 ath9k_hw_computetxtime(struct ath_hal *ah,
826 struct ath_rate_table *rates,
827 u32 frameLen, u16 rateix,
828 bool shortPreamble);
829 u32 ath9k_hw_mhz2ieee(struct ath_hal *ah, u32 freq, u32 flags);
830 void ath9k_hw_get_channel_centers(struct ath_hal *ah,
831 struct ath9k_channel *chan,
832 struct chan_centers *centers);
833
834 /* Attach, Detach */
835
836 const char *ath9k_hw_probe(u16 vendorid, u16 devid);
837 void ath9k_hw_detach(struct ath_hal *ah);
838 struct ath_hal *ath9k_hw_attach(u16 devid, struct ath_softc *sc,
839 void __iomem *mem, int *error);
840 void ath9k_hw_rfdetach(struct ath_hal *ah);
841
842
843 /* HW Reset */
844
845 bool ath9k_hw_reset(struct ath_hal *ah, struct ath9k_channel *chan,
846 enum ath9k_ht_macmode macmode,
847 u8 txchainmask, u8 rxchainmask,
848 enum ath9k_ht_extprotspacing extprotspacing,
849 bool bChannelChange, int *status);
850
851 /* Key Cache Management */
852
853 bool ath9k_hw_keyreset(struct ath_hal *ah, u16 entry);
854 bool ath9k_hw_keysetmac(struct ath_hal *ah, u16 entry, const u8 *mac);
855 bool ath9k_hw_set_keycache_entry(struct ath_hal *ah, u16 entry,
856 const struct ath9k_keyval *k,
857 const u8 *mac, int xorKey);
858 bool ath9k_hw_keyisvalid(struct ath_hal *ah, u16 entry);
859
860 /* Power Management */
861
862 bool ath9k_hw_setpower(struct ath_hal *ah,
863 enum ath9k_power_mode mode);
864 void ath9k_hw_configpcipowersave(struct ath_hal *ah, int restore);
865
866 /* Beacon timers */
867
868 void ath9k_hw_beaconinit(struct ath_hal *ah, u32 next_beacon, u32 beacon_period);
869 void ath9k_hw_set_sta_beacon_timers(struct ath_hal *ah,
870 const struct ath9k_beacon_state *bs);
871 /* HW Capabilities */
872
873 bool ath9k_hw_fill_cap_info(struct ath_hal *ah);
874 bool ath9k_hw_getcapability(struct ath_hal *ah, enum ath9k_capability_type type,
875 u32 capability, u32 *result);
876 bool ath9k_hw_setcapability(struct ath_hal *ah, enum ath9k_capability_type type,
877 u32 capability, u32 setting, int *status);
878
879 /* GPIO / RFKILL / Antennae */
880
881 void ath9k_hw_cfg_gpio_input(struct ath_hal *ah, u32 gpio);
882 u32 ath9k_hw_gpio_get(struct ath_hal *ah, u32 gpio);
883 void ath9k_hw_cfg_output(struct ath_hal *ah, u32 gpio,
884 u32 ah_signal_type);
885 void ath9k_hw_set_gpio(struct ath_hal *ah, u32 gpio, u32 val);
886 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
887 void ath9k_enable_rfkill(struct ath_hal *ah);
888 #endif
889 int ath9k_hw_select_antconfig(struct ath_hal *ah, u32 cfg);
890 u32 ath9k_hw_getdefantenna(struct ath_hal *ah);
891 void ath9k_hw_setantenna(struct ath_hal *ah, u32 antenna);
892 bool ath9k_hw_setantennaswitch(struct ath_hal *ah,
893 enum ath9k_ant_setting settings,
894 struct ath9k_channel *chan,
895 u8 *tx_chainmask,
896 u8 *rx_chainmask,
897 u8 *antenna_cfgd);
898
899 /* General Operation */
900
901 u32 ath9k_hw_getrxfilter(struct ath_hal *ah);
902 void ath9k_hw_setrxfilter(struct ath_hal *ah, u32 bits);
903 bool ath9k_hw_phy_disable(struct ath_hal *ah);
904 bool ath9k_hw_disable(struct ath_hal *ah);
905 bool ath9k_hw_set_txpowerlimit(struct ath_hal *ah, u32 limit);
906 void ath9k_hw_getmac(struct ath_hal *ah, u8 *mac);
907 bool ath9k_hw_setmac(struct ath_hal *ah, const u8 *mac);
908 void ath9k_hw_setopmode(struct ath_hal *ah);
909 void ath9k_hw_setmcastfilter(struct ath_hal *ah, u32 filter0, u32 filter1);
910 void ath9k_hw_getbssidmask(struct ath_hal *ah, u8 *mask);
911 bool ath9k_hw_setbssidmask(struct ath_hal *ah, const u8 *mask);
912 void ath9k_hw_write_associd(struct ath_hal *ah, const u8 *bssid, u16 assocId);
913 u64 ath9k_hw_gettsf64(struct ath_hal *ah);
914 void ath9k_hw_reset_tsf(struct ath_hal *ah);
915 bool ath9k_hw_set_tsfadjust(struct ath_hal *ah, u32 setting);
916 bool ath9k_hw_setslottime(struct ath_hal *ah, u32 us);
917 void ath9k_hw_set11nmac2040(struct ath_hal *ah, enum ath9k_ht_macmode mode);
918
919 /* Regulatory */
920
921 bool ath9k_regd_is_public_safety_sku(struct ath_hal *ah);
922 struct ath9k_channel* ath9k_regd_check_channel(struct ath_hal *ah,
923 const struct ath9k_channel *c);
924 u32 ath9k_regd_get_ctl(struct ath_hal *ah, struct ath9k_channel *chan);
925 u32 ath9k_regd_get_antenna_allowed(struct ath_hal *ah,
926 struct ath9k_channel *chan);
927 bool ath9k_regd_init_channels(struct ath_hal *ah,
928 u32 maxchans, u32 *nchans, u8 *regclassids,
929 u32 maxregids, u32 *nregids, u16 cc,
930 bool enableOutdoor, bool enableExtendedChannels);
931
932 /* ANI */
933
934 void ath9k_ani_reset(struct ath_hal *ah);
935 void ath9k_hw_ani_monitor(struct ath_hal *ah,
936 const struct ath9k_node_stats *stats,
937 struct ath9k_channel *chan);
938 bool ath9k_hw_phycounters(struct ath_hal *ah);
939 void ath9k_enable_mib_counters(struct ath_hal *ah);
940 void ath9k_hw_disable_mib_counters(struct ath_hal *ah);
941 u32 ath9k_hw_GetMibCycleCountsPct(struct ath_hal *ah,
942 u32 *rxc_pcnt,
943 u32 *rxf_pcnt,
944 u32 *txf_pcnt);
945 void ath9k_hw_procmibevent(struct ath_hal *ah,
946 const struct ath9k_node_stats *stats);
947 void ath9k_hw_ani_setup(struct ath_hal *ah);
948 void ath9k_hw_ani_attach(struct ath_hal *ah);
949 void ath9k_hw_ani_detach(struct ath_hal *ah);
950
951 /* Calibration */
952
953 void ath9k_hw_reset_calvalid(struct ath_hal *ah, struct ath9k_channel *chan,
954 bool *isCalDone);
955 void ath9k_hw_start_nfcal(struct ath_hal *ah);
956 void ath9k_hw_loadnf(struct ath_hal *ah, struct ath9k_channel *chan);
957 int16_t ath9k_hw_getnf(struct ath_hal *ah,
958 struct ath9k_channel *chan);
959 void ath9k_init_nfcal_hist_buffer(struct ath_hal *ah);
960 s16 ath9k_hw_getchan_noise(struct ath_hal *ah, struct ath9k_channel *chan);
961 bool ath9k_hw_calibrate(struct ath_hal *ah, struct ath9k_channel *chan,
962 u8 rxchainmask, bool longcal,
963 bool *isCalDone);
964 bool ath9k_hw_init_cal(struct ath_hal *ah,
965 struct ath9k_channel *chan);
966
967
968 /* EEPROM */
969
970 int ath9k_hw_set_txpower(struct ath_hal *ah,
971 struct ath9k_channel *chan,
972 u16 cfgCtl,
973 u8 twiceAntennaReduction,
974 u8 twiceMaxRegulatoryPower,
975 u8 powerLimit);
976 void ath9k_hw_set_addac(struct ath_hal *ah, struct ath9k_channel *chan);
977 bool ath9k_hw_set_power_per_rate_table(struct ath_hal *ah,
978 struct ath9k_channel *chan,
979 int16_t *ratesArray,
980 u16 cfgCtl,
981 u8 AntennaReduction,
982 u8 twiceMaxRegulatoryPower,
983 u8 powerLimit);
984 bool ath9k_hw_set_power_cal_table(struct ath_hal *ah,
985 struct ath9k_channel *chan,
986 int16_t *pTxPowerIndexOffset);
987 bool ath9k_hw_eeprom_set_board_values(struct ath_hal *ah,
988 struct ath9k_channel *chan);
989 int ath9k_hw_get_eeprom_antenna_cfg(struct ath_hal *ah,
990 struct ath9k_channel *chan,
991 u8 index, u16 *config);
992 u8 ath9k_hw_get_num_ant_config(struct ath_hal *ah,
993 enum ieee80211_band freq_band);
994 u16 ath9k_hw_eeprom_get_spur_chan(struct ath_hal *ah, u16 i, bool is2GHz);
995 int ath9k_hw_eeprom_attach(struct ath_hal *ah);
996
997 /* Interrupt Handling */
998
999 bool ath9k_hw_intrpend(struct ath_hal *ah);
1000 bool ath9k_hw_getisr(struct ath_hal *ah, enum ath9k_int *masked);
1001 enum ath9k_int ath9k_hw_intrget(struct ath_hal *ah);
1002 enum ath9k_int ath9k_hw_set_interrupts(struct ath_hal *ah, enum ath9k_int ints);
1003
1004 /* MAC (PCU/QCU) */
1005
1006 u32 ath9k_hw_gettxbuf(struct ath_hal *ah, u32 q);
1007 bool ath9k_hw_puttxbuf(struct ath_hal *ah, u32 q, u32 txdp);
1008 bool ath9k_hw_txstart(struct ath_hal *ah, u32 q);
1009 u32 ath9k_hw_numtxpending(struct ath_hal *ah, u32 q);
1010 bool ath9k_hw_updatetxtriglevel(struct ath_hal *ah, bool bIncTrigLevel);
1011 bool ath9k_hw_stoptxdma(struct ath_hal *ah, u32 q);
1012 bool ath9k_hw_filltxdesc(struct ath_hal *ah, struct ath_desc *ds,
1013 u32 segLen, bool firstSeg,
1014 bool lastSeg, const struct ath_desc *ds0);
1015 void ath9k_hw_cleartxdesc(struct ath_hal *ah, struct ath_desc *ds);
1016 int ath9k_hw_txprocdesc(struct ath_hal *ah, struct ath_desc *ds);
1017 void ath9k_hw_set11n_txdesc(struct ath_hal *ah, struct ath_desc *ds,
1018 u32 pktLen, enum ath9k_pkt_type type, u32 txPower,
1019 u32 keyIx, enum ath9k_key_type keyType, u32 flags);
1020 void ath9k_hw_set11n_ratescenario(struct ath_hal *ah, struct ath_desc *ds,
1021 struct ath_desc *lastds,
1022 u32 durUpdateEn, u32 rtsctsRate,
1023 u32 rtsctsDuration,
1024 struct ath9k_11n_rate_series series[],
1025 u32 nseries, u32 flags);
1026 void ath9k_hw_set11n_aggr_first(struct ath_hal *ah, struct ath_desc *ds,
1027 u32 aggrLen);
1028 void ath9k_hw_set11n_aggr_middle(struct ath_hal *ah, struct ath_desc *ds,
1029 u32 numDelims);
1030 void ath9k_hw_set11n_aggr_last(struct ath_hal *ah, struct ath_desc *ds);
1031 void ath9k_hw_clr11n_aggr(struct ath_hal *ah, struct ath_desc *ds);
1032 void ath9k_hw_set11n_burstduration(struct ath_hal *ah, struct ath_desc *ds,
1033 u32 burstDuration);
1034 void ath9k_hw_set11n_virtualmorefrag(struct ath_hal *ah, struct ath_desc *ds,
1035 u32 vmf);
1036 void ath9k_hw_gettxintrtxqs(struct ath_hal *ah, u32 *txqs);
1037 bool ath9k_hw_set_txq_props(struct ath_hal *ah, int q,
1038 const struct ath9k_tx_queue_info *qinfo);
1039 bool ath9k_hw_get_txq_props(struct ath_hal *ah, int q,
1040 struct ath9k_tx_queue_info *qinfo);
1041 int ath9k_hw_setuptxqueue(struct ath_hal *ah, enum ath9k_tx_queue type,
1042 const struct ath9k_tx_queue_info *qinfo);
1043 bool ath9k_hw_releasetxqueue(struct ath_hal *ah, u32 q);
1044 bool ath9k_hw_resettxqueue(struct ath_hal *ah, u32 q);
1045 int ath9k_hw_rxprocdesc(struct ath_hal *ah, struct ath_desc *ds,
1046 u32 pa, struct ath_desc *nds, u64 tsf);
1047 bool ath9k_hw_setuprxdesc(struct ath_hal *ah, struct ath_desc *ds,
1048 u32 size, u32 flags);
1049 bool ath9k_hw_setrxabort(struct ath_hal *ah, bool set);
1050 void ath9k_hw_putrxbuf(struct ath_hal *ah, u32 rxdp);
1051 void ath9k_hw_rxena(struct ath_hal *ah);
1052 void ath9k_hw_startpcureceive(struct ath_hal *ah);
1053 void ath9k_hw_stoppcurecv(struct ath_hal *ah);
1054 bool ath9k_hw_stopdmarecv(struct ath_hal *ah);
1055
1056 #endif
Linux kernel - Deliverables
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