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ath9k: Trim struct ath_softc
[deliverable/linux.git] / drivers / net / wireless / ath9k / core.c
1 /*
2 * Copyright (c) 2008, Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 /* Implementation of the main "ATH" layer. */
18
19 #include "core.h"
20 #include "regd.h"
21
22 static int ath_outdoor; /* enable outdoor use */
23
24 static u32 ath_chainmask_sel_up_rssi_thres =
25 ATH_CHAINMASK_SEL_UP_RSSI_THRES;
26 static u32 ath_chainmask_sel_down_rssi_thres =
27 ATH_CHAINMASK_SEL_DOWN_RSSI_THRES;
28 static u32 ath_chainmask_sel_period =
29 ATH_CHAINMASK_SEL_TIMEOUT;
30
31 /* return bus cachesize in 4B word units */
32
33 static void bus_read_cachesize(struct ath_softc *sc, int *csz)
34 {
35 u8 u8tmp;
36
37 pci_read_config_byte(sc->pdev, PCI_CACHE_LINE_SIZE, (u8 *)&u8tmp);
38 *csz = (int)u8tmp;
39
40 /*
41 * This check was put in to avoid "unplesant" consequences if
42 * the bootrom has not fully initialized all PCI devices.
43 * Sometimes the cache line size register is not set
44 */
45
46 if (*csz == 0)
47 *csz = DEFAULT_CACHELINE >> 2; /* Use the default size */
48 }
49
50 /*
51 * Set current operating mode
52 *
53 * This function initializes and fills the rate table in the ATH object based
54 * on the operating mode. The blink rates are also set up here, although
55 * they have been superceeded by the ath_led module.
56 */
57
58 static void ath_setcurmode(struct ath_softc *sc, enum wireless_mode mode)
59 {
60 const struct ath9k_rate_table *rt;
61 int i;
62
63 memset(sc->sc_rixmap, 0xff, sizeof(sc->sc_rixmap));
64 rt = ath9k_hw_getratetable(sc->sc_ah, mode);
65 BUG_ON(!rt);
66
67 for (i = 0; i < rt->rateCount; i++)
68 sc->sc_rixmap[rt->info[i].rateCode] = (u8) i;
69
70 memzero(sc->sc_hwmap, sizeof(sc->sc_hwmap));
71 for (i = 0; i < 256; i++) {
72 u8 ix = rt->rateCodeToIndex[i];
73
74 if (ix == 0xff)
75 continue;
76
77 sc->sc_hwmap[i].ieeerate =
78 rt->info[ix].dot11Rate & IEEE80211_RATE_VAL;
79 sc->sc_hwmap[i].rateKbps = rt->info[ix].rateKbps;
80
81 if (rt->info[ix].shortPreamble ||
82 rt->info[ix].phy == PHY_OFDM) {
83 /* XXX: Handle this */
84 }
85
86 /* NB: this uses the last entry if the rate isn't found */
87 /* XXX beware of overlow */
88 }
89 sc->sc_currates = rt;
90 sc->sc_curmode = mode;
91 /*
92 * All protection frames are transmited at 2Mb/s for
93 * 11g, otherwise at 1Mb/s.
94 * XXX select protection rate index from rate table.
95 */
96 sc->sc_protrix = (mode == ATH9K_MODE_11G ? 1 : 0);
97 }
98
99 /*
100 * Set up rate table (legacy rates)
101 */
102 static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
103 {
104 struct ath_hal *ah = sc->sc_ah;
105 const struct ath9k_rate_table *rt = NULL;
106 struct ieee80211_supported_band *sband;
107 struct ieee80211_rate *rate;
108 int i, maxrates;
109
110 switch (band) {
111 case IEEE80211_BAND_2GHZ:
112 rt = ath9k_hw_getratetable(ah, ATH9K_MODE_11G);
113 break;
114 case IEEE80211_BAND_5GHZ:
115 rt = ath9k_hw_getratetable(ah, ATH9K_MODE_11A);
116 break;
117 default:
118 break;
119 }
120
121 if (rt == NULL)
122 return;
123
124 sband = &sc->sbands[band];
125 rate = sc->rates[band];
126
127 if (rt->rateCount > ATH_RATE_MAX)
128 maxrates = ATH_RATE_MAX;
129 else
130 maxrates = rt->rateCount;
131
132 for (i = 0; i < maxrates; i++) {
133 rate[i].bitrate = rt->info[i].rateKbps / 100;
134 rate[i].hw_value = rt->info[i].rateCode;
135 sband->n_bitrates++;
136 DPRINTF(sc, ATH_DBG_CONFIG,
137 "%s: Rate: %2dMbps, ratecode: %2d\n",
138 __func__,
139 rate[i].bitrate / 10,
140 rate[i].hw_value);
141 }
142 }
143
144 /*
145 * Set up channel list
146 */
147 static int ath_setup_channels(struct ath_softc *sc)
148 {
149 struct ath_hal *ah = sc->sc_ah;
150 int nchan, i, a = 0, b = 0;
151 u8 regclassids[ATH_REGCLASSIDS_MAX];
152 u32 nregclass = 0;
153 struct ieee80211_supported_band *band_2ghz;
154 struct ieee80211_supported_band *band_5ghz;
155 struct ieee80211_channel *chan_2ghz;
156 struct ieee80211_channel *chan_5ghz;
157 struct ath9k_channel *c;
158
159 /* Fill in ah->ah_channels */
160 if (!ath9k_regd_init_channels(ah,
161 ATH_CHAN_MAX,
162 (u32 *)&nchan,
163 regclassids,
164 ATH_REGCLASSIDS_MAX,
165 &nregclass,
166 CTRY_DEFAULT,
167 false,
168 1)) {
169 u32 rd = ah->ah_currentRD;
170
171 DPRINTF(sc, ATH_DBG_FATAL,
172 "%s: unable to collect channel list; "
173 "regdomain likely %u country code %u\n",
174 __func__, rd, CTRY_DEFAULT);
175 return -EINVAL;
176 }
177
178 band_2ghz = &sc->sbands[IEEE80211_BAND_2GHZ];
179 band_5ghz = &sc->sbands[IEEE80211_BAND_5GHZ];
180 chan_2ghz = sc->channels[IEEE80211_BAND_2GHZ];
181 chan_5ghz = sc->channels[IEEE80211_BAND_5GHZ];
182
183 for (i = 0; i < nchan; i++) {
184 c = &ah->ah_channels[i];
185 if (IS_CHAN_2GHZ(c)) {
186 chan_2ghz[a].band = IEEE80211_BAND_2GHZ;
187 chan_2ghz[a].center_freq = c->channel;
188 chan_2ghz[a].max_power = c->maxTxPower;
189
190 if (c->privFlags & CHANNEL_DISALLOW_ADHOC)
191 chan_2ghz[a].flags |=
192 IEEE80211_CHAN_NO_IBSS;
193 if (c->channelFlags & CHANNEL_PASSIVE)
194 chan_2ghz[a].flags |=
195 IEEE80211_CHAN_PASSIVE_SCAN;
196
197 band_2ghz->n_channels = ++a;
198
199 DPRINTF(sc, ATH_DBG_CONFIG,
200 "%s: 2MHz channel: %d, "
201 "channelFlags: 0x%x\n",
202 __func__,
203 c->channel,
204 c->channelFlags);
205 } else if (IS_CHAN_5GHZ(c)) {
206 chan_5ghz[b].band = IEEE80211_BAND_5GHZ;
207 chan_5ghz[b].center_freq = c->channel;
208 chan_5ghz[b].max_power = c->maxTxPower;
209
210 if (c->privFlags & CHANNEL_DISALLOW_ADHOC)
211 chan_5ghz[b].flags |=
212 IEEE80211_CHAN_NO_IBSS;
213 if (c->channelFlags & CHANNEL_PASSIVE)
214 chan_5ghz[b].flags |=
215 IEEE80211_CHAN_PASSIVE_SCAN;
216
217 band_5ghz->n_channels = ++b;
218
219 DPRINTF(sc, ATH_DBG_CONFIG,
220 "%s: 5MHz channel: %d, "
221 "channelFlags: 0x%x\n",
222 __func__,
223 c->channel,
224 c->channelFlags);
225 }
226 }
227
228 return 0;
229 }
230
231 /*
232 * Determine mode from channel flags
233 *
234 * This routine will provide the enumerated WIRELESSS_MODE value based
235 * on the settings of the channel flags. If ho valid set of flags
236 * exist, the lowest mode (11b) is selected.
237 */
238
239 static enum wireless_mode ath_chan2mode(struct ath9k_channel *chan)
240 {
241 if (chan->chanmode == CHANNEL_A)
242 return ATH9K_MODE_11A;
243 else if (chan->chanmode == CHANNEL_G)
244 return ATH9K_MODE_11G;
245 else if (chan->chanmode == CHANNEL_B)
246 return ATH9K_MODE_11B;
247 else if (chan->chanmode == CHANNEL_A_HT20)
248 return ATH9K_MODE_11NA_HT20;
249 else if (chan->chanmode == CHANNEL_G_HT20)
250 return ATH9K_MODE_11NG_HT20;
251 else if (chan->chanmode == CHANNEL_A_HT40PLUS)
252 return ATH9K_MODE_11NA_HT40PLUS;
253 else if (chan->chanmode == CHANNEL_A_HT40MINUS)
254 return ATH9K_MODE_11NA_HT40MINUS;
255 else if (chan->chanmode == CHANNEL_G_HT40PLUS)
256 return ATH9K_MODE_11NG_HT40PLUS;
257 else if (chan->chanmode == CHANNEL_G_HT40MINUS)
258 return ATH9K_MODE_11NG_HT40MINUS;
259
260 /* NB: should not get here */
261 return ATH9K_MODE_11B;
262 }
263
264 /*
265 * Stop the device, grabbing the top-level lock to protect
266 * against concurrent entry through ath_init (which can happen
267 * if another thread does a system call and the thread doing the
268 * stop is preempted).
269 */
270
271 static int ath_stop(struct ath_softc *sc)
272 {
273 struct ath_hal *ah = sc->sc_ah;
274
275 DPRINTF(sc, ATH_DBG_CONFIG, "%s: invalid %ld\n",
276 __func__, sc->sc_flags & SC_OP_INVALID);
277
278 /*
279 * Shutdown the hardware and driver:
280 * stop output from above
281 * reset 802.11 state machine
282 * (sends station deassoc/deauth frames)
283 * turn off timers
284 * disable interrupts
285 * clear transmit machinery
286 * clear receive machinery
287 * turn off the radio
288 * reclaim beacon resources
289 *
290 * Note that some of this work is not possible if the
291 * hardware is gone (invalid).
292 */
293
294 if (!(sc->sc_flags & SC_OP_INVALID))
295 ath9k_hw_set_interrupts(ah, 0);
296 ath_draintxq(sc, false);
297 if (!(sc->sc_flags & SC_OP_INVALID)) {
298 ath_stoprecv(sc);
299 ath9k_hw_phy_disable(ah);
300 } else
301 sc->sc_rxlink = NULL;
302
303 return 0;
304 }
305
306 /*
307 * Set the current channel
308 *
309 * Set/change channels. If the channel is really being changed, it's done
310 * by reseting the chip. To accomplish this we must first cleanup any pending
311 * DMA, then restart stuff after a la ath_init.
312 */
313 int ath_set_channel(struct ath_softc *sc, struct ath9k_channel *hchan)
314 {
315 struct ath_hal *ah = sc->sc_ah;
316 bool fastcc = true, stopped;
317 enum ath9k_ht_macmode ht_macmode;
318
319 if (sc->sc_flags & SC_OP_INVALID) /* the device is invalid or removed */
320 return -EIO;
321
322 DPRINTF(sc, ATH_DBG_CONFIG,
323 "%s: %u (%u MHz) -> %u (%u MHz), cflags:%x\n",
324 __func__,
325 ath9k_hw_mhz2ieee(ah, sc->sc_ah->ah_curchan->channel,
326 sc->sc_ah->ah_curchan->channelFlags),
327 sc->sc_ah->ah_curchan->channel,
328 ath9k_hw_mhz2ieee(ah, hchan->channel, hchan->channelFlags),
329 hchan->channel, hchan->channelFlags);
330
331 ht_macmode = ath_cwm_macmode(sc);
332
333 if (hchan->channel != sc->sc_ah->ah_curchan->channel ||
334 hchan->channelFlags != sc->sc_ah->ah_curchan->channelFlags ||
335 (sc->sc_flags & SC_OP_CHAINMASK_UPDATE) ||
336 (sc->sc_flags & SC_OP_FULL_RESET)) {
337 int status;
338 /*
339 * This is only performed if the channel settings have
340 * actually changed.
341 *
342 * To switch channels clear any pending DMA operations;
343 * wait long enough for the RX fifo to drain, reset the
344 * hardware at the new frequency, and then re-enable
345 * the relevant bits of the h/w.
346 */
347 ath9k_hw_set_interrupts(ah, 0); /* disable interrupts */
348 ath_draintxq(sc, false); /* clear pending tx frames */
349 stopped = ath_stoprecv(sc); /* turn off frame recv */
350
351 /* XXX: do not flush receive queue here. We don't want
352 * to flush data frames already in queue because of
353 * changing channel. */
354
355 if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
356 fastcc = false;
357
358 spin_lock_bh(&sc->sc_resetlock);
359 if (!ath9k_hw_reset(ah, hchan,
360 ht_macmode, sc->sc_tx_chainmask,
361 sc->sc_rx_chainmask,
362 sc->sc_ht_extprotspacing,
363 fastcc, &status)) {
364 DPRINTF(sc, ATH_DBG_FATAL,
365 "%s: unable to reset channel %u (%uMhz) "
366 "flags 0x%x hal status %u\n", __func__,
367 ath9k_hw_mhz2ieee(ah, hchan->channel,
368 hchan->channelFlags),
369 hchan->channel, hchan->channelFlags, status);
370 spin_unlock_bh(&sc->sc_resetlock);
371 return -EIO;
372 }
373 spin_unlock_bh(&sc->sc_resetlock);
374
375 sc->sc_flags &= ~SC_OP_CHAINMASK_UPDATE;
376 sc->sc_flags &= ~SC_OP_FULL_RESET;
377
378 /* Re-enable rx framework */
379 if (ath_startrecv(sc) != 0) {
380 DPRINTF(sc, ATH_DBG_FATAL,
381 "%s: unable to restart recv logic\n", __func__);
382 return -EIO;
383 }
384 /*
385 * Change channels and update the h/w rate map
386 * if we're switching; e.g. 11a to 11b/g.
387 */
388 ath_setcurmode(sc, ath_chan2mode(hchan));
389
390 ath_update_txpow(sc); /* update tx power state */
391 /*
392 * Re-enable interrupts.
393 */
394 ath9k_hw_set_interrupts(ah, sc->sc_imask);
395 }
396 return 0;
397 }
398
399 /**********************/
400 /* Chainmask Handling */
401 /**********************/
402
403 static void ath_chainmask_sel_timertimeout(unsigned long data)
404 {
405 struct ath_chainmask_sel *cm = (struct ath_chainmask_sel *)data;
406 cm->switch_allowed = 1;
407 }
408
409 /* Start chainmask select timer */
410 static void ath_chainmask_sel_timerstart(struct ath_chainmask_sel *cm)
411 {
412 cm->switch_allowed = 0;
413 mod_timer(&cm->timer, ath_chainmask_sel_period);
414 }
415
416 /* Stop chainmask select timer */
417 static void ath_chainmask_sel_timerstop(struct ath_chainmask_sel *cm)
418 {
419 cm->switch_allowed = 0;
420 del_timer_sync(&cm->timer);
421 }
422
423 static void ath_chainmask_sel_init(struct ath_softc *sc, struct ath_node *an)
424 {
425 struct ath_chainmask_sel *cm = &an->an_chainmask_sel;
426
427 memzero(cm, sizeof(struct ath_chainmask_sel));
428
429 cm->cur_tx_mask = sc->sc_tx_chainmask;
430 cm->cur_rx_mask = sc->sc_rx_chainmask;
431 cm->tx_avgrssi = ATH_RSSI_DUMMY_MARKER;
432 setup_timer(&cm->timer,
433 ath_chainmask_sel_timertimeout, (unsigned long) cm);
434 }
435
436 int ath_chainmask_sel_logic(struct ath_softc *sc, struct ath_node *an)
437 {
438 struct ath_chainmask_sel *cm = &an->an_chainmask_sel;
439
440 /*
441 * Disable auto-swtiching in one of the following if conditions.
442 * sc_chainmask_auto_sel is used for internal global auto-switching
443 * enabled/disabled setting
444 */
445 if (sc->sc_ah->ah_caps.tx_chainmask != ATH_CHAINMASK_SEL_3X3) {
446 cm->cur_tx_mask = sc->sc_tx_chainmask;
447 return cm->cur_tx_mask;
448 }
449
450 if (cm->tx_avgrssi == ATH_RSSI_DUMMY_MARKER)
451 return cm->cur_tx_mask;
452
453 if (cm->switch_allowed) {
454 /* Switch down from tx 3 to tx 2. */
455 if (cm->cur_tx_mask == ATH_CHAINMASK_SEL_3X3 &&
456 ATH_RSSI_OUT(cm->tx_avgrssi) >=
457 ath_chainmask_sel_down_rssi_thres) {
458 cm->cur_tx_mask = sc->sc_tx_chainmask;
459
460 /* Don't let another switch happen until
461 * this timer expires */
462 ath_chainmask_sel_timerstart(cm);
463 }
464 /* Switch up from tx 2 to 3. */
465 else if (cm->cur_tx_mask == sc->sc_tx_chainmask &&
466 ATH_RSSI_OUT(cm->tx_avgrssi) <=
467 ath_chainmask_sel_up_rssi_thres) {
468 cm->cur_tx_mask = ATH_CHAINMASK_SEL_3X3;
469
470 /* Don't let another switch happen
471 * until this timer expires */
472 ath_chainmask_sel_timerstart(cm);
473 }
474 }
475
476 return cm->cur_tx_mask;
477 }
478
479 /*
480 * Update tx/rx chainmask. For legacy association,
481 * hard code chainmask to 1x1, for 11n association, use
482 * the chainmask configuration.
483 */
484
485 void ath_update_chainmask(struct ath_softc *sc, int is_ht)
486 {
487 sc->sc_flags |= SC_OP_CHAINMASK_UPDATE;
488 if (is_ht) {
489 sc->sc_tx_chainmask = sc->sc_ah->ah_caps.tx_chainmask;
490 sc->sc_rx_chainmask = sc->sc_ah->ah_caps.rx_chainmask;
491 } else {
492 sc->sc_tx_chainmask = 1;
493 sc->sc_rx_chainmask = 1;
494 }
495
496 DPRINTF(sc, ATH_DBG_CONFIG, "%s: tx chmask: %d, rx chmask: %d\n",
497 __func__, sc->sc_tx_chainmask, sc->sc_rx_chainmask);
498 }
499
500 /******************/
501 /* VAP management */
502 /******************/
503
504 /*
505 * VAP in Listen mode
506 *
507 * This routine brings the VAP out of the down state into a "listen" state
508 * where it waits for association requests. This is used in AP and AdHoc
509 * modes.
510 */
511
512 int ath_vap_listen(struct ath_softc *sc, int if_id)
513 {
514 struct ath_hal *ah = sc->sc_ah;
515 struct ath_vap *avp;
516 u32 rfilt = 0;
517 DECLARE_MAC_BUF(mac);
518
519 avp = sc->sc_vaps[if_id];
520 if (avp == NULL) {
521 DPRINTF(sc, ATH_DBG_FATAL, "%s: invalid interface id %u\n",
522 __func__, if_id);
523 return -EINVAL;
524 }
525
526 #ifdef CONFIG_SLOW_ANT_DIV
527 ath_slow_ant_div_stop(&sc->sc_antdiv);
528 #endif
529
530 /* update ratectrl about the new state */
531 ath_rate_newstate(sc, avp);
532
533 rfilt = ath_calcrxfilter(sc);
534 ath9k_hw_setrxfilter(ah, rfilt);
535
536 if (sc->sc_ah->ah_opmode == ATH9K_M_STA ||
537 sc->sc_ah->ah_opmode == ATH9K_M_IBSS) {
538 memcpy(sc->sc_curbssid, ath_bcast_mac, ETH_ALEN);
539 ath9k_hw_write_associd(ah, sc->sc_curbssid, sc->sc_curaid);
540 } else
541 sc->sc_curaid = 0;
542
543 DPRINTF(sc, ATH_DBG_CONFIG,
544 "%s: RX filter 0x%x bssid %s aid 0x%x\n",
545 __func__, rfilt, print_mac(mac,
546 sc->sc_curbssid), sc->sc_curaid);
547
548 /*
549 * XXXX
550 * Disable BMISS interrupt when we're not associated
551 */
552 ath9k_hw_set_interrupts(ah,
553 sc->sc_imask & ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS));
554 sc->sc_imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
555 /* need to reconfigure the beacons when it moves to RUN */
556 sc->sc_flags &= ~SC_OP_BEACONS;
557
558 return 0;
559 }
560
561 int ath_vap_attach(struct ath_softc *sc,
562 int if_id,
563 struct ieee80211_vif *if_data,
564 enum ath9k_opmode opmode)
565 {
566 struct ath_vap *avp;
567
568 if (if_id >= ATH_BCBUF || sc->sc_vaps[if_id] != NULL) {
569 DPRINTF(sc, ATH_DBG_FATAL,
570 "%s: Invalid interface id = %u\n", __func__, if_id);
571 return -EINVAL;
572 }
573
574 switch (opmode) {
575 case ATH9K_M_STA:
576 case ATH9K_M_IBSS:
577 case ATH9K_M_MONITOR:
578 break;
579 case ATH9K_M_HOSTAP:
580 /* XXX not right, beacon buffer is allocated on RUN trans */
581 if (list_empty(&sc->sc_bbuf))
582 return -ENOMEM;
583 break;
584 default:
585 return -EINVAL;
586 }
587
588 /* create ath_vap */
589 avp = kmalloc(sizeof(struct ath_vap), GFP_KERNEL);
590 if (avp == NULL)
591 return -ENOMEM;
592
593 memzero(avp, sizeof(struct ath_vap));
594 avp->av_if_data = if_data;
595 /* Set the VAP opmode */
596 avp->av_opmode = opmode;
597 avp->av_bslot = -1;
598 INIT_LIST_HEAD(&avp->av_mcastq.axq_q);
599 INIT_LIST_HEAD(&avp->av_mcastq.axq_acq);
600 spin_lock_init(&avp->av_mcastq.axq_lock);
601
602 ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
603
604 sc->sc_vaps[if_id] = avp;
605 sc->sc_nvaps++;
606 /* Set the device opmode */
607 sc->sc_ah->ah_opmode = opmode;
608
609 /* default VAP configuration */
610 avp->av_config.av_fixed_rateset = IEEE80211_FIXED_RATE_NONE;
611 avp->av_config.av_fixed_retryset = 0x03030303;
612
613 return 0;
614 }
615
616 int ath_vap_detach(struct ath_softc *sc, int if_id)
617 {
618 struct ath_hal *ah = sc->sc_ah;
619 struct ath_vap *avp;
620
621 avp = sc->sc_vaps[if_id];
622 if (avp == NULL) {
623 DPRINTF(sc, ATH_DBG_FATAL, "%s: invalid interface id %u\n",
624 __func__, if_id);
625 return -EINVAL;
626 }
627
628 /*
629 * Quiesce the hardware while we remove the vap. In
630 * particular we need to reclaim all references to the
631 * vap state by any frames pending on the tx queues.
632 *
633 * XXX can we do this w/o affecting other vap's?
634 */
635 ath9k_hw_set_interrupts(ah, 0); /* disable interrupts */
636 ath_draintxq(sc, false); /* stop xmit side */
637 ath_stoprecv(sc); /* stop recv side */
638 ath_flushrecv(sc); /* flush recv queue */
639
640 /* Reclaim any pending mcast bufs on the vap. */
641 ath_tx_draintxq(sc, &avp->av_mcastq, false);
642
643 kfree(avp);
644 sc->sc_vaps[if_id] = NULL;
645 sc->sc_nvaps--;
646
647 return 0;
648 }
649
650 int ath_vap_config(struct ath_softc *sc,
651 int if_id, struct ath_vap_config *if_config)
652 {
653 struct ath_vap *avp;
654
655 if (if_id >= ATH_BCBUF) {
656 DPRINTF(sc, ATH_DBG_FATAL,
657 "%s: Invalid interface id = %u\n", __func__, if_id);
658 return -EINVAL;
659 }
660
661 avp = sc->sc_vaps[if_id];
662 ASSERT(avp != NULL);
663
664 if (avp)
665 memcpy(&avp->av_config, if_config, sizeof(avp->av_config));
666
667 return 0;
668 }
669
670 /********/
671 /* Core */
672 /********/
673
674 int ath_open(struct ath_softc *sc, struct ath9k_channel *initial_chan)
675 {
676 struct ath_hal *ah = sc->sc_ah;
677 int status;
678 int error = 0;
679 enum ath9k_ht_macmode ht_macmode = ath_cwm_macmode(sc);
680
681 DPRINTF(sc, ATH_DBG_CONFIG, "%s: mode %d\n",
682 __func__, sc->sc_ah->ah_opmode);
683
684 /*
685 * Stop anything previously setup. This is safe
686 * whether this is the first time through or not.
687 */
688 ath_stop(sc);
689
690 /* Initialize chanmask selection */
691 sc->sc_tx_chainmask = ah->ah_caps.tx_chainmask;
692 sc->sc_rx_chainmask = ah->ah_caps.rx_chainmask;
693
694 /* Reset SERDES registers */
695 ath9k_hw_configpcipowersave(ah, 0);
696
697 /*
698 * The basic interface to setting the hardware in a good
699 * state is ``reset''. On return the hardware is known to
700 * be powered up and with interrupts disabled. This must
701 * be followed by initialization of the appropriate bits
702 * and then setup of the interrupt mask.
703 */
704
705 spin_lock_bh(&sc->sc_resetlock);
706 if (!ath9k_hw_reset(ah, initial_chan, ht_macmode,
707 sc->sc_tx_chainmask, sc->sc_rx_chainmask,
708 sc->sc_ht_extprotspacing, false, &status)) {
709 DPRINTF(sc, ATH_DBG_FATAL,
710 "%s: unable to reset hardware; hal status %u "
711 "(freq %u flags 0x%x)\n", __func__, status,
712 initial_chan->channel, initial_chan->channelFlags);
713 error = -EIO;
714 spin_unlock_bh(&sc->sc_resetlock);
715 goto done;
716 }
717 spin_unlock_bh(&sc->sc_resetlock);
718 /*
719 * This is needed only to setup initial state
720 * but it's best done after a reset.
721 */
722 ath_update_txpow(sc);
723
724 /*
725 * Setup the hardware after reset:
726 * The receive engine is set going.
727 * Frame transmit is handled entirely
728 * in the frame output path; there's nothing to do
729 * here except setup the interrupt mask.
730 */
731 if (ath_startrecv(sc) != 0) {
732 DPRINTF(sc, ATH_DBG_FATAL,
733 "%s: unable to start recv logic\n", __func__);
734 error = -EIO;
735 goto done;
736 }
737 /* Setup our intr mask. */
738 sc->sc_imask = ATH9K_INT_RX | ATH9K_INT_TX
739 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
740 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
741
742 if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_GTT)
743 sc->sc_imask |= ATH9K_INT_GTT;
744
745 if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT)
746 sc->sc_imask |= ATH9K_INT_CST;
747
748 /*
749 * Enable MIB interrupts when there are hardware phy counters.
750 * Note we only do this (at the moment) for station mode.
751 */
752 if (ath9k_hw_phycounters(ah) &&
753 ((sc->sc_ah->ah_opmode == ATH9K_M_STA) ||
754 (sc->sc_ah->ah_opmode == ATH9K_M_IBSS)))
755 sc->sc_imask |= ATH9K_INT_MIB;
756 /*
757 * Some hardware processes the TIM IE and fires an
758 * interrupt when the TIM bit is set. For hardware
759 * that does, if not overridden by configuration,
760 * enable the TIM interrupt when operating as station.
761 */
762 if ((ah->ah_caps.hw_caps & ATH9K_HW_CAP_ENHANCEDPM) &&
763 (sc->sc_ah->ah_opmode == ATH9K_M_STA) &&
764 !sc->sc_config.swBeaconProcess)
765 sc->sc_imask |= ATH9K_INT_TIM;
766 /*
767 * Don't enable interrupts here as we've not yet built our
768 * vap and node data structures, which will be needed as soon
769 * as we start receiving.
770 */
771 ath_setcurmode(sc, ath_chan2mode(initial_chan));
772
773 /* XXX: we must make sure h/w is ready and clear invalid flag
774 * before turning on interrupt. */
775 sc->sc_flags &= ~SC_OP_INVALID;
776 done:
777 return error;
778 }
779
780 int ath_reset(struct ath_softc *sc, bool retry_tx)
781 {
782 struct ath_hal *ah = sc->sc_ah;
783 int status;
784 int error = 0;
785 enum ath9k_ht_macmode ht_macmode = ath_cwm_macmode(sc);
786
787 ath9k_hw_set_interrupts(ah, 0); /* disable interrupts */
788 ath_draintxq(sc, retry_tx); /* stop xmit */
789 ath_stoprecv(sc); /* stop recv */
790 ath_flushrecv(sc); /* flush recv queue */
791
792 /* Reset chip */
793 spin_lock_bh(&sc->sc_resetlock);
794 if (!ath9k_hw_reset(ah, sc->sc_ah->ah_curchan,
795 ht_macmode,
796 sc->sc_tx_chainmask, sc->sc_rx_chainmask,
797 sc->sc_ht_extprotspacing, false, &status)) {
798 DPRINTF(sc, ATH_DBG_FATAL,
799 "%s: unable to reset hardware; hal status %u\n",
800 __func__, status);
801 error = -EIO;
802 }
803 spin_unlock_bh(&sc->sc_resetlock);
804
805 if (ath_startrecv(sc) != 0) /* restart recv */
806 DPRINTF(sc, ATH_DBG_FATAL,
807 "%s: unable to start recv logic\n", __func__);
808
809 /*
810 * We may be doing a reset in response to a request
811 * that changes the channel so update any state that
812 * might change as a result.
813 */
814 ath_setcurmode(sc, ath_chan2mode(sc->sc_ah->ah_curchan));
815
816 ath_update_txpow(sc);
817
818 if (sc->sc_flags & SC_OP_BEACONS)
819 ath_beacon_config(sc, ATH_IF_ID_ANY); /* restart beacons */
820
821 ath9k_hw_set_interrupts(ah, sc->sc_imask);
822
823 /* Restart the txq */
824 if (retry_tx) {
825 int i;
826 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
827 if (ATH_TXQ_SETUP(sc, i)) {
828 spin_lock_bh(&sc->sc_txq[i].axq_lock);
829 ath_txq_schedule(sc, &sc->sc_txq[i]);
830 spin_unlock_bh(&sc->sc_txq[i].axq_lock);
831 }
832 }
833 }
834
835 return error;
836 }
837
838 int ath_suspend(struct ath_softc *sc)
839 {
840 struct ath_hal *ah = sc->sc_ah;
841
842 /* No I/O if device has been surprise removed */
843 if (sc->sc_flags & SC_OP_INVALID)
844 return -EIO;
845
846 /* Shut off the interrupt before setting sc->sc_invalid to '1' */
847 ath9k_hw_set_interrupts(ah, 0);
848
849 /* XXX: we must make sure h/w will not generate any interrupt
850 * before setting the invalid flag. */
851 sc->sc_flags |= SC_OP_INVALID;
852
853 /* disable HAL and put h/w to sleep */
854 ath9k_hw_disable(sc->sc_ah);
855
856 ath9k_hw_configpcipowersave(sc->sc_ah, 1);
857
858 return 0;
859 }
860
861 /* Interrupt handler. Most of the actual processing is deferred.
862 * It's the caller's responsibility to ensure the chip is awake. */
863
864 irqreturn_t ath_isr(int irq, void *dev)
865 {
866 struct ath_softc *sc = dev;
867 struct ath_hal *ah = sc->sc_ah;
868 enum ath9k_int status;
869 bool sched = false;
870
871 do {
872 if (sc->sc_flags & SC_OP_INVALID) {
873 /*
874 * The hardware is not ready/present, don't
875 * touch anything. Note this can happen early
876 * on if the IRQ is shared.
877 */
878 return IRQ_NONE;
879 }
880 if (!ath9k_hw_intrpend(ah)) { /* shared irq, not for us */
881 return IRQ_NONE;
882 }
883
884 /*
885 * Figure out the reason(s) for the interrupt. Note
886 * that the hal returns a pseudo-ISR that may include
887 * bits we haven't explicitly enabled so we mask the
888 * value to insure we only process bits we requested.
889 */
890 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
891
892 status &= sc->sc_imask; /* discard unasked-for bits */
893
894 /*
895 * If there are no status bits set, then this interrupt was not
896 * for me (should have been caught above).
897 */
898
899 if (!status)
900 return IRQ_NONE;
901
902 sc->sc_intrstatus = status;
903
904 if (status & ATH9K_INT_FATAL) {
905 /* need a chip reset */
906 sched = true;
907 } else if (status & ATH9K_INT_RXORN) {
908 /* need a chip reset */
909 sched = true;
910 } else {
911 if (status & ATH9K_INT_SWBA) {
912 /* schedule a tasklet for beacon handling */
913 tasklet_schedule(&sc->bcon_tasklet);
914 }
915 if (status & ATH9K_INT_RXEOL) {
916 /*
917 * NB: the hardware should re-read the link when
918 * RXE bit is written, but it doesn't work
919 * at least on older hardware revs.
920 */
921 sched = true;
922 }
923
924 if (status & ATH9K_INT_TXURN)
925 /* bump tx trigger level */
926 ath9k_hw_updatetxtriglevel(ah, true);
927 /* XXX: optimize this */
928 if (status & ATH9K_INT_RX)
929 sched = true;
930 if (status & ATH9K_INT_TX)
931 sched = true;
932 if (status & ATH9K_INT_BMISS)
933 sched = true;
934 /* carrier sense timeout */
935 if (status & ATH9K_INT_CST)
936 sched = true;
937 if (status & ATH9K_INT_MIB) {
938 /*
939 * Disable interrupts until we service the MIB
940 * interrupt; otherwise it will continue to
941 * fire.
942 */
943 ath9k_hw_set_interrupts(ah, 0);
944 /*
945 * Let the hal handle the event. We assume
946 * it will clear whatever condition caused
947 * the interrupt.
948 */
949 ath9k_hw_procmibevent(ah, &sc->sc_halstats);
950 ath9k_hw_set_interrupts(ah, sc->sc_imask);
951 }
952 if (status & ATH9K_INT_TIM_TIMER) {
953 if (!(ah->ah_caps.hw_caps &
954 ATH9K_HW_CAP_AUTOSLEEP)) {
955 /* Clear RxAbort bit so that we can
956 * receive frames */
957 ath9k_hw_setrxabort(ah, 0);
958 sched = true;
959 }
960 }
961 }
962 } while (0);
963
964 if (sched) {
965 /* turn off every interrupt except SWBA */
966 ath9k_hw_set_interrupts(ah, (sc->sc_imask & ATH9K_INT_SWBA));
967 tasklet_schedule(&sc->intr_tq);
968 }
969
970 return IRQ_HANDLED;
971 }
972
973 /* Deferred interrupt processing */
974
975 static void ath9k_tasklet(unsigned long data)
976 {
977 struct ath_softc *sc = (struct ath_softc *)data;
978 u32 status = sc->sc_intrstatus;
979
980 if (status & ATH9K_INT_FATAL) {
981 /* need a chip reset */
982 ath_reset(sc, false);
983 return;
984 } else {
985
986 if (status &
987 (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
988 /* XXX: fill me in */
989 /*
990 if (status & ATH9K_INT_RXORN) {
991 }
992 if (status & ATH9K_INT_RXEOL) {
993 }
994 */
995 spin_lock_bh(&sc->sc_rxflushlock);
996 ath_rx_tasklet(sc, 0);
997 spin_unlock_bh(&sc->sc_rxflushlock);
998 }
999 /* XXX: optimize this */
1000 if (status & ATH9K_INT_TX)
1001 ath_tx_tasklet(sc);
1002 /* XXX: fill me in */
1003 /*
1004 if (status & ATH9K_INT_BMISS) {
1005 }
1006 if (status & (ATH9K_INT_TIM | ATH9K_INT_DTIMSYNC)) {
1007 if (status & ATH9K_INT_TIM) {
1008 }
1009 if (status & ATH9K_INT_DTIMSYNC) {
1010 }
1011 }
1012 */
1013 }
1014
1015 /* re-enable hardware interrupt */
1016 ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_imask);
1017 }
1018
1019 int ath_init(u16 devid, struct ath_softc *sc)
1020 {
1021 struct ath_hal *ah = NULL;
1022 int status;
1023 int error = 0, i;
1024 int csz = 0;
1025 u32 rd;
1026
1027 /* XXX: hardware will not be ready until ath_open() being called */
1028 sc->sc_flags |= SC_OP_INVALID;
1029
1030 sc->sc_debug = DBG_DEFAULT;
1031 DPRINTF(sc, ATH_DBG_CONFIG, "%s: devid 0x%x\n", __func__, devid);
1032
1033 /* Initialize tasklet */
1034 tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
1035 tasklet_init(&sc->bcon_tasklet, ath9k_beacon_tasklet,
1036 (unsigned long)sc);
1037
1038 /*
1039 * Cache line size is used to size and align various
1040 * structures used to communicate with the hardware.
1041 */
1042 bus_read_cachesize(sc, &csz);
1043 /* XXX assert csz is non-zero */
1044 sc->sc_cachelsz = csz << 2; /* convert to bytes */
1045
1046 spin_lock_init(&sc->sc_resetlock);
1047
1048 ah = ath9k_hw_attach(devid, sc, sc->mem, &status);
1049 if (ah == NULL) {
1050 DPRINTF(sc, ATH_DBG_FATAL,
1051 "%s: unable to attach hardware; HAL status %u\n",
1052 __func__, status);
1053 error = -ENXIO;
1054 goto bad;
1055 }
1056 sc->sc_ah = ah;
1057
1058 /* Get the hardware key cache size. */
1059 sc->sc_keymax = ah->ah_caps.keycache_size;
1060 if (sc->sc_keymax > ATH_KEYMAX) {
1061 DPRINTF(sc, ATH_DBG_KEYCACHE,
1062 "%s: Warning, using only %u entries in %u key cache\n",
1063 __func__, ATH_KEYMAX, sc->sc_keymax);
1064 sc->sc_keymax = ATH_KEYMAX;
1065 }
1066
1067 /*
1068 * Reset the key cache since some parts do not
1069 * reset the contents on initial power up.
1070 */
1071 for (i = 0; i < sc->sc_keymax; i++)
1072 ath9k_hw_keyreset(ah, (u16) i);
1073 /*
1074 * Mark key cache slots associated with global keys
1075 * as in use. If we knew TKIP was not to be used we
1076 * could leave the +32, +64, and +32+64 slots free.
1077 * XXX only for splitmic.
1078 */
1079 for (i = 0; i < IEEE80211_WEP_NKID; i++) {
1080 set_bit(i, sc->sc_keymap);
1081 set_bit(i + 32, sc->sc_keymap);
1082 set_bit(i + 64, sc->sc_keymap);
1083 set_bit(i + 32 + 64, sc->sc_keymap);
1084 }
1085 /*
1086 * Collect the channel list using the default country
1087 * code and including outdoor channels. The 802.11 layer
1088 * is resposible for filtering this list based on settings
1089 * like the phy mode.
1090 */
1091 rd = ah->ah_currentRD;
1092
1093 error = ath_setup_channels(sc);
1094 if (error)
1095 goto bad;
1096
1097 /* default to STA mode */
1098 sc->sc_ah->ah_opmode = ATH9K_M_MONITOR;
1099
1100 /* Setup rate tables */
1101
1102 ath_setup_rates(sc, IEEE80211_BAND_2GHZ);
1103 ath_setup_rates(sc, IEEE80211_BAND_5GHZ);
1104
1105 /* NB: setup here so ath_rate_update is happy */
1106 ath_setcurmode(sc, ATH9K_MODE_11A);
1107
1108 /*
1109 * Allocate hardware transmit queues: one queue for
1110 * beacon frames and one data queue for each QoS
1111 * priority. Note that the hal handles reseting
1112 * these queues at the needed time.
1113 */
1114 sc->sc_bhalq = ath_beaconq_setup(ah);
1115 if (sc->sc_bhalq == -1) {
1116 DPRINTF(sc, ATH_DBG_FATAL,
1117 "%s: unable to setup a beacon xmit queue\n", __func__);
1118 error = -EIO;
1119 goto bad2;
1120 }
1121 sc->sc_cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1122 if (sc->sc_cabq == NULL) {
1123 DPRINTF(sc, ATH_DBG_FATAL,
1124 "%s: unable to setup CAB xmit queue\n", __func__);
1125 error = -EIO;
1126 goto bad2;
1127 }
1128
1129 sc->sc_config.cabqReadytime = ATH_CABQ_READY_TIME;
1130 ath_cabq_update(sc);
1131
1132 for (i = 0; i < ARRAY_SIZE(sc->sc_haltype2q); i++)
1133 sc->sc_haltype2q[i] = -1;
1134
1135 /* Setup data queues */
1136 /* NB: ensure BK queue is the lowest priority h/w queue */
1137 if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
1138 DPRINTF(sc, ATH_DBG_FATAL,
1139 "%s: unable to setup xmit queue for BK traffic\n",
1140 __func__);
1141 error = -EIO;
1142 goto bad2;
1143 }
1144
1145 if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
1146 DPRINTF(sc, ATH_DBG_FATAL,
1147 "%s: unable to setup xmit queue for BE traffic\n",
1148 __func__);
1149 error = -EIO;
1150 goto bad2;
1151 }
1152 if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
1153 DPRINTF(sc, ATH_DBG_FATAL,
1154 "%s: unable to setup xmit queue for VI traffic\n",
1155 __func__);
1156 error = -EIO;
1157 goto bad2;
1158 }
1159 if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
1160 DPRINTF(sc, ATH_DBG_FATAL,
1161 "%s: unable to setup xmit queue for VO traffic\n",
1162 __func__);
1163 error = -EIO;
1164 goto bad2;
1165 }
1166
1167 sc->sc_rc = ath_rate_attach(ah);
1168 if (sc->sc_rc == NULL) {
1169 error = EIO;
1170 goto bad2;
1171 }
1172
1173 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1174 ATH9K_CIPHER_TKIP, NULL)) {
1175 /*
1176 * Whether we should enable h/w TKIP MIC.
1177 * XXX: if we don't support WME TKIP MIC, then we wouldn't
1178 * report WMM capable, so it's always safe to turn on
1179 * TKIP MIC in this case.
1180 */
1181 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
1182 0, 1, NULL);
1183 }
1184
1185 /*
1186 * Check whether the separate key cache entries
1187 * are required to handle both tx+rx MIC keys.
1188 * With split mic keys the number of stations is limited
1189 * to 27 otherwise 59.
1190 */
1191 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1192 ATH9K_CIPHER_TKIP, NULL)
1193 && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1194 ATH9K_CIPHER_MIC, NULL)
1195 && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
1196 0, NULL))
1197 sc->sc_splitmic = 1;
1198
1199 /* turn on mcast key search if possible */
1200 if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
1201 (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
1202 1, NULL);
1203
1204 sc->sc_config.txpowlimit = ATH_TXPOWER_MAX;
1205 sc->sc_config.txpowlimit_override = 0;
1206
1207 /* 11n Capabilities */
1208 if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) {
1209 sc->sc_flags |= SC_OP_TXAGGR;
1210 sc->sc_flags |= SC_OP_RXAGGR;
1211 }
1212
1213 sc->sc_tx_chainmask = ah->ah_caps.tx_chainmask;
1214 sc->sc_rx_chainmask = ah->ah_caps.rx_chainmask;
1215
1216 ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
1217 sc->sc_defant = ath9k_hw_getdefantenna(ah);
1218
1219 ath9k_hw_getmac(ah, sc->sc_myaddr);
1220 if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) {
1221 ath9k_hw_getbssidmask(ah, sc->sc_bssidmask);
1222 ATH_SET_VAP_BSSID_MASK(sc->sc_bssidmask);
1223 ath9k_hw_setbssidmask(ah, sc->sc_bssidmask);
1224 }
1225 sc->sc_slottime = ATH9K_SLOT_TIME_9; /* default to short slot time */
1226
1227 /* initialize beacon slots */
1228 for (i = 0; i < ARRAY_SIZE(sc->sc_bslot); i++)
1229 sc->sc_bslot[i] = ATH_IF_ID_ANY;
1230
1231 /* save MISC configurations */
1232 sc->sc_config.swBeaconProcess = 1;
1233
1234 #ifdef CONFIG_SLOW_ANT_DIV
1235 /* range is 40 - 255, we use something in the middle */
1236 ath_slow_ant_div_init(&sc->sc_antdiv, sc, 0x127);
1237 #endif
1238
1239 return 0;
1240 bad2:
1241 /* cleanup tx queues */
1242 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1243 if (ATH_TXQ_SETUP(sc, i))
1244 ath_tx_cleanupq(sc, &sc->sc_txq[i]);
1245 bad:
1246 if (ah)
1247 ath9k_hw_detach(ah);
1248 return error;
1249 }
1250
1251 void ath_deinit(struct ath_softc *sc)
1252 {
1253 struct ath_hal *ah = sc->sc_ah;
1254 int i;
1255
1256 DPRINTF(sc, ATH_DBG_CONFIG, "%s\n", __func__);
1257
1258 ath_stop(sc);
1259 if (!(sc->sc_flags & SC_OP_INVALID))
1260 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
1261 ath_rate_detach(sc->sc_rc);
1262 /* cleanup tx queues */
1263 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1264 if (ATH_TXQ_SETUP(sc, i))
1265 ath_tx_cleanupq(sc, &sc->sc_txq[i]);
1266 ath9k_hw_detach(ah);
1267 }
1268
1269 /*******************/
1270 /* Node Management */
1271 /*******************/
1272
1273 struct ath_node *ath_node_attach(struct ath_softc *sc, u8 *addr, int if_id)
1274 {
1275 struct ath_vap *avp;
1276 struct ath_node *an;
1277 DECLARE_MAC_BUF(mac);
1278
1279 avp = sc->sc_vaps[if_id];
1280 ASSERT(avp != NULL);
1281
1282 /* mac80211 sta_notify callback is from an IRQ context, so no sleep */
1283 an = kmalloc(sizeof(struct ath_node), GFP_ATOMIC);
1284 if (an == NULL)
1285 return NULL;
1286 memzero(an, sizeof(*an));
1287
1288 an->an_sc = sc;
1289 memcpy(an->an_addr, addr, ETH_ALEN);
1290 atomic_set(&an->an_refcnt, 1);
1291
1292 /* set up per-node tx/rx state */
1293 ath_tx_node_init(sc, an);
1294 ath_rx_node_init(sc, an);
1295
1296 ath_chainmask_sel_init(sc, an);
1297 ath_chainmask_sel_timerstart(&an->an_chainmask_sel);
1298 list_add(&an->list, &sc->node_list);
1299
1300 return an;
1301 }
1302
1303 void ath_node_detach(struct ath_softc *sc, struct ath_node *an, bool bh_flag)
1304 {
1305 unsigned long flags;
1306
1307 DECLARE_MAC_BUF(mac);
1308
1309 ath_chainmask_sel_timerstop(&an->an_chainmask_sel);
1310 an->an_flags |= ATH_NODE_CLEAN;
1311 ath_tx_node_cleanup(sc, an, bh_flag);
1312 ath_rx_node_cleanup(sc, an);
1313
1314 ath_tx_node_free(sc, an);
1315 ath_rx_node_free(sc, an);
1316
1317 spin_lock_irqsave(&sc->node_lock, flags);
1318
1319 list_del(&an->list);
1320
1321 spin_unlock_irqrestore(&sc->node_lock, flags);
1322
1323 kfree(an);
1324 }
1325
1326 /* Finds a node and increases the refcnt if found */
1327
1328 struct ath_node *ath_node_get(struct ath_softc *sc, u8 *addr)
1329 {
1330 struct ath_node *an = NULL, *an_found = NULL;
1331
1332 if (list_empty(&sc->node_list)) /* FIXME */
1333 goto out;
1334 list_for_each_entry(an, &sc->node_list, list) {
1335 if (!compare_ether_addr(an->an_addr, addr)) {
1336 atomic_inc(&an->an_refcnt);
1337 an_found = an;
1338 break;
1339 }
1340 }
1341 out:
1342 return an_found;
1343 }
1344
1345 /* Decrements the refcnt and if it drops to zero, detach the node */
1346
1347 void ath_node_put(struct ath_softc *sc, struct ath_node *an, bool bh_flag)
1348 {
1349 if (atomic_dec_and_test(&an->an_refcnt))
1350 ath_node_detach(sc, an, bh_flag);
1351 }
1352
1353 /* Finds a node, doesn't increment refcnt. Caller must hold sc->node_lock */
1354 struct ath_node *ath_node_find(struct ath_softc *sc, u8 *addr)
1355 {
1356 struct ath_node *an = NULL, *an_found = NULL;
1357
1358 if (list_empty(&sc->node_list))
1359 return NULL;
1360
1361 list_for_each_entry(an, &sc->node_list, list)
1362 if (!compare_ether_addr(an->an_addr, addr)) {
1363 an_found = an;
1364 break;
1365 }
1366
1367 return an_found;
1368 }
1369
1370 /*
1371 * Set up New Node
1372 *
1373 * Setup driver-specific state for a newly associated node. This routine
1374 * really only applies if compression or XR are enabled, there is no code
1375 * covering any other cases.
1376 */
1377
1378 void ath_newassoc(struct ath_softc *sc,
1379 struct ath_node *an, int isnew, int isuapsd)
1380 {
1381 int tidno;
1382
1383 /* if station reassociates, tear down the aggregation state. */
1384 if (!isnew) {
1385 for (tidno = 0; tidno < WME_NUM_TID; tidno++) {
1386 if (sc->sc_flags & SC_OP_TXAGGR)
1387 ath_tx_aggr_teardown(sc, an, tidno);
1388 if (sc->sc_flags & SC_OP_RXAGGR)
1389 ath_rx_aggr_teardown(sc, an, tidno);
1390 }
1391 }
1392 an->an_flags = 0;
1393 }
1394
1395 /**************/
1396 /* Encryption */
1397 /**************/
1398
1399 void ath_key_reset(struct ath_softc *sc, u16 keyix, int freeslot)
1400 {
1401 ath9k_hw_keyreset(sc->sc_ah, keyix);
1402 if (freeslot)
1403 clear_bit(keyix, sc->sc_keymap);
1404 }
1405
1406 int ath_keyset(struct ath_softc *sc,
1407 u16 keyix,
1408 struct ath9k_keyval *hk,
1409 const u8 mac[ETH_ALEN])
1410 {
1411 bool status;
1412
1413 status = ath9k_hw_set_keycache_entry(sc->sc_ah,
1414 keyix, hk, mac, false);
1415
1416 return status != false;
1417 }
1418
1419 /***********************/
1420 /* TX Power/Regulatory */
1421 /***********************/
1422
1423 /*
1424 * Set Transmit power in HAL
1425 *
1426 * This routine makes the actual HAL calls to set the new transmit power
1427 * limit.
1428 */
1429
1430 void ath_update_txpow(struct ath_softc *sc)
1431 {
1432 struct ath_hal *ah = sc->sc_ah;
1433 u32 txpow;
1434
1435 if (sc->sc_curtxpow != sc->sc_config.txpowlimit) {
1436 ath9k_hw_set_txpowerlimit(ah, sc->sc_config.txpowlimit);
1437 /* read back in case value is clamped */
1438 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
1439 sc->sc_curtxpow = txpow;
1440 }
1441 }
1442
1443 /* Return the current country and domain information */
1444 void ath_get_currentCountry(struct ath_softc *sc,
1445 struct ath9k_country_entry *ctry)
1446 {
1447 ath9k_regd_get_current_country(sc->sc_ah, ctry);
1448
1449 /* If HAL not specific yet, since it is band dependent,
1450 * use the one we passed in. */
1451 if (ctry->countryCode == CTRY_DEFAULT) {
1452 ctry->iso[0] = 0;
1453 ctry->iso[1] = 0;
1454 } else if (ctry->iso[0] && ctry->iso[1]) {
1455 if (!ctry->iso[2]) {
1456 if (ath_outdoor)
1457 ctry->iso[2] = 'O';
1458 else
1459 ctry->iso[2] = 'I';
1460 }
1461 }
1462 }
1463
1464 /**************************/
1465 /* Slow Antenna Diversity */
1466 /**************************/
1467
1468 void ath_slow_ant_div_init(struct ath_antdiv *antdiv,
1469 struct ath_softc *sc,
1470 int32_t rssitrig)
1471 {
1472 int trig;
1473
1474 /* antdivf_rssitrig can range from 40 - 0xff */
1475 trig = (rssitrig > 0xff) ? 0xff : rssitrig;
1476 trig = (rssitrig < 40) ? 40 : rssitrig;
1477
1478 antdiv->antdiv_sc = sc;
1479 antdiv->antdivf_rssitrig = trig;
1480 }
1481
1482 void ath_slow_ant_div_start(struct ath_antdiv *antdiv,
1483 u8 num_antcfg,
1484 const u8 *bssid)
1485 {
1486 antdiv->antdiv_num_antcfg =
1487 num_antcfg < ATH_ANT_DIV_MAX_CFG ?
1488 num_antcfg : ATH_ANT_DIV_MAX_CFG;
1489 antdiv->antdiv_state = ATH_ANT_DIV_IDLE;
1490 antdiv->antdiv_curcfg = 0;
1491 antdiv->antdiv_bestcfg = 0;
1492 antdiv->antdiv_laststatetsf = 0;
1493
1494 memcpy(antdiv->antdiv_bssid, bssid, sizeof(antdiv->antdiv_bssid));
1495
1496 antdiv->antdiv_start = 1;
1497 }
1498
1499 void ath_slow_ant_div_stop(struct ath_antdiv *antdiv)
1500 {
1501 antdiv->antdiv_start = 0;
1502 }
1503
1504 static int32_t ath_find_max_val(int32_t *val,
1505 u8 num_val, u8 *max_index)
1506 {
1507 u32 MaxVal = *val++;
1508 u32 cur_index = 0;
1509
1510 *max_index = 0;
1511 while (++cur_index < num_val) {
1512 if (*val > MaxVal) {
1513 MaxVal = *val;
1514 *max_index = cur_index;
1515 }
1516
1517 val++;
1518 }
1519
1520 return MaxVal;
1521 }
1522
1523 void ath_slow_ant_div(struct ath_antdiv *antdiv,
1524 struct ieee80211_hdr *hdr,
1525 struct ath_rx_status *rx_stats)
1526 {
1527 struct ath_softc *sc = antdiv->antdiv_sc;
1528 struct ath_hal *ah = sc->sc_ah;
1529 u64 curtsf = 0;
1530 u8 bestcfg, curcfg = antdiv->antdiv_curcfg;
1531 __le16 fc = hdr->frame_control;
1532
1533 if (antdiv->antdiv_start && ieee80211_is_beacon(fc)
1534 && !compare_ether_addr(hdr->addr3, antdiv->antdiv_bssid)) {
1535 antdiv->antdiv_lastbrssi[curcfg] = rx_stats->rs_rssi;
1536 antdiv->antdiv_lastbtsf[curcfg] = ath9k_hw_gettsf64(sc->sc_ah);
1537 curtsf = antdiv->antdiv_lastbtsf[curcfg];
1538 } else {
1539 return;
1540 }
1541
1542 switch (antdiv->antdiv_state) {
1543 case ATH_ANT_DIV_IDLE:
1544 if ((antdiv->antdiv_lastbrssi[curcfg] <
1545 antdiv->antdivf_rssitrig)
1546 && ((curtsf - antdiv->antdiv_laststatetsf) >
1547 ATH_ANT_DIV_MIN_IDLE_US)) {
1548
1549 curcfg++;
1550 if (curcfg == antdiv->antdiv_num_antcfg)
1551 curcfg = 0;
1552
1553 if (!ath9k_hw_select_antconfig(ah, curcfg)) {
1554 antdiv->antdiv_bestcfg = antdiv->antdiv_curcfg;
1555 antdiv->antdiv_curcfg = curcfg;
1556 antdiv->antdiv_laststatetsf = curtsf;
1557 antdiv->antdiv_state = ATH_ANT_DIV_SCAN;
1558 }
1559 }
1560 break;
1561
1562 case ATH_ANT_DIV_SCAN:
1563 if ((curtsf - antdiv->antdiv_laststatetsf) <
1564 ATH_ANT_DIV_MIN_SCAN_US)
1565 break;
1566
1567 curcfg++;
1568 if (curcfg == antdiv->antdiv_num_antcfg)
1569 curcfg = 0;
1570
1571 if (curcfg == antdiv->antdiv_bestcfg) {
1572 ath_find_max_val(antdiv->antdiv_lastbrssi,
1573 antdiv->antdiv_num_antcfg, &bestcfg);
1574 if (!ath9k_hw_select_antconfig(ah, bestcfg)) {
1575 antdiv->antdiv_bestcfg = bestcfg;
1576 antdiv->antdiv_curcfg = bestcfg;
1577 antdiv->antdiv_laststatetsf = curtsf;
1578 antdiv->antdiv_state = ATH_ANT_DIV_IDLE;
1579 }
1580 } else {
1581 if (!ath9k_hw_select_antconfig(ah, curcfg)) {
1582 antdiv->antdiv_curcfg = curcfg;
1583 antdiv->antdiv_laststatetsf = curtsf;
1584 antdiv->antdiv_state = ATH_ANT_DIV_SCAN;
1585 }
1586 }
1587
1588 break;
1589 }
1590 }
1591
1592 /***********************/
1593 /* Descriptor Handling */
1594 /***********************/
1595
1596 /*
1597 * Set up DMA descriptors
1598 *
1599 * This function will allocate both the DMA descriptor structure, and the
1600 * buffers it contains. These are used to contain the descriptors used
1601 * by the system.
1602 */
1603
1604 int ath_descdma_setup(struct ath_softc *sc,
1605 struct ath_descdma *dd,
1606 struct list_head *head,
1607 const char *name,
1608 int nbuf,
1609 int ndesc)
1610 {
1611 #define DS2PHYS(_dd, _ds) \
1612 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
1613 #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
1614 #define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
1615
1616 struct ath_desc *ds;
1617 struct ath_buf *bf;
1618 int i, bsize, error;
1619
1620 DPRINTF(sc, ATH_DBG_CONFIG, "%s: %s DMA: %u buffers %u desc/buf\n",
1621 __func__, name, nbuf, ndesc);
1622
1623 /* ath_desc must be a multiple of DWORDs */
1624 if ((sizeof(struct ath_desc) % 4) != 0) {
1625 DPRINTF(sc, ATH_DBG_FATAL, "%s: ath_desc not DWORD aligned\n",
1626 __func__);
1627 ASSERT((sizeof(struct ath_desc) % 4) == 0);
1628 error = -ENOMEM;
1629 goto fail;
1630 }
1631
1632 dd->dd_name = name;
1633 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
1634
1635 /*
1636 * Need additional DMA memory because we can't use
1637 * descriptors that cross the 4K page boundary. Assume
1638 * one skipped descriptor per 4K page.
1639 */
1640 if (!(sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1641 u32 ndesc_skipped =
1642 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
1643 u32 dma_len;
1644
1645 while (ndesc_skipped) {
1646 dma_len = ndesc_skipped * sizeof(struct ath_desc);
1647 dd->dd_desc_len += dma_len;
1648
1649 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
1650 };
1651 }
1652
1653 /* allocate descriptors */
1654 dd->dd_desc = pci_alloc_consistent(sc->pdev,
1655 dd->dd_desc_len,
1656 &dd->dd_desc_paddr);
1657 if (dd->dd_desc == NULL) {
1658 error = -ENOMEM;
1659 goto fail;
1660 }
1661 ds = dd->dd_desc;
1662 DPRINTF(sc, ATH_DBG_CONFIG, "%s: %s DMA map: %p (%u) -> %llx (%u)\n",
1663 __func__, dd->dd_name, ds, (u32) dd->dd_desc_len,
1664 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
1665
1666 /* allocate buffers */
1667 bsize = sizeof(struct ath_buf) * nbuf;
1668 bf = kmalloc(bsize, GFP_KERNEL);
1669 if (bf == NULL) {
1670 error = -ENOMEM;
1671 goto fail2;
1672 }
1673 memzero(bf, bsize);
1674 dd->dd_bufptr = bf;
1675
1676 INIT_LIST_HEAD(head);
1677 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
1678 bf->bf_desc = ds;
1679 bf->bf_daddr = DS2PHYS(dd, ds);
1680
1681 if (!(sc->sc_ah->ah_caps.hw_caps &
1682 ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1683 /*
1684 * Skip descriptor addresses which can cause 4KB
1685 * boundary crossing (addr + length) with a 32 dword
1686 * descriptor fetch.
1687 */
1688 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
1689 ASSERT((caddr_t) bf->bf_desc <
1690 ((caddr_t) dd->dd_desc +
1691 dd->dd_desc_len));
1692
1693 ds += ndesc;
1694 bf->bf_desc = ds;
1695 bf->bf_daddr = DS2PHYS(dd, ds);
1696 }
1697 }
1698 list_add_tail(&bf->list, head);
1699 }
1700 return 0;
1701 fail2:
1702 pci_free_consistent(sc->pdev,
1703 dd->dd_desc_len, dd->dd_desc, dd->dd_desc_paddr);
1704 fail:
1705 memzero(dd, sizeof(*dd));
1706 return error;
1707 #undef ATH_DESC_4KB_BOUND_CHECK
1708 #undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
1709 #undef DS2PHYS
1710 }
1711
1712 /*
1713 * Cleanup DMA descriptors
1714 *
1715 * This function will free the DMA block that was allocated for the descriptor
1716 * pool. Since this was allocated as one "chunk", it is freed in the same
1717 * manner.
1718 */
1719
1720 void ath_descdma_cleanup(struct ath_softc *sc,
1721 struct ath_descdma *dd,
1722 struct list_head *head)
1723 {
1724 /* Free memory associated with descriptors */
1725 pci_free_consistent(sc->pdev,
1726 dd->dd_desc_len, dd->dd_desc, dd->dd_desc_paddr);
1727
1728 INIT_LIST_HEAD(head);
1729 kfree(dd->dd_bufptr);
1730 memzero(dd, sizeof(*dd));
1731 }
1732
1733 /*************/
1734 /* Utilities */
1735 /*************/
1736
1737 int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
1738 {
1739 int qnum;
1740
1741 switch (queue) {
1742 case 0:
1743 qnum = sc->sc_haltype2q[ATH9K_WME_AC_VO];
1744 break;
1745 case 1:
1746 qnum = sc->sc_haltype2q[ATH9K_WME_AC_VI];
1747 break;
1748 case 2:
1749 qnum = sc->sc_haltype2q[ATH9K_WME_AC_BE];
1750 break;
1751 case 3:
1752 qnum = sc->sc_haltype2q[ATH9K_WME_AC_BK];
1753 break;
1754 default:
1755 qnum = sc->sc_haltype2q[ATH9K_WME_AC_BE];
1756 break;
1757 }
1758
1759 return qnum;
1760 }
1761
1762 int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
1763 {
1764 int qnum;
1765
1766 switch (queue) {
1767 case ATH9K_WME_AC_VO:
1768 qnum = 0;
1769 break;
1770 case ATH9K_WME_AC_VI:
1771 qnum = 1;
1772 break;
1773 case ATH9K_WME_AC_BE:
1774 qnum = 2;
1775 break;
1776 case ATH9K_WME_AC_BK:
1777 qnum = 3;
1778 break;
1779 default:
1780 qnum = -1;
1781 break;
1782 }
1783
1784 return qnum;
1785 }
1786
1787
1788 /*
1789 * Expand time stamp to TSF
1790 *
1791 * Extend 15-bit time stamp from rx descriptor to
1792 * a full 64-bit TSF using the current h/w TSF.
1793 */
1794
1795 u64 ath_extend_tsf(struct ath_softc *sc, u32 rstamp)
1796 {
1797 u64 tsf;
1798
1799 tsf = ath9k_hw_gettsf64(sc->sc_ah);
1800 if ((tsf & 0x7fff) < rstamp)
1801 tsf -= 0x8000;
1802 return (tsf & ~0x7fff) | rstamp;
1803 }
1804
1805 /*
1806 * Set Default Antenna
1807 *
1808 * Call into the HAL to set the default antenna to use. Not really valid for
1809 * MIMO technology.
1810 */
1811
1812 void ath_setdefantenna(void *context, u32 antenna)
1813 {
1814 struct ath_softc *sc = (struct ath_softc *)context;
1815 struct ath_hal *ah = sc->sc_ah;
1816
1817 /* XXX block beacon interrupts */
1818 ath9k_hw_setantenna(ah, antenna);
1819 sc->sc_defant = antenna;
1820 sc->sc_rxotherant = 0;
1821 }
1822
1823 /*
1824 * Set Slot Time
1825 *
1826 * This will wake up the chip if required, and set the slot time for the
1827 * frame (maximum transmit time). Slot time is assumed to be already set
1828 * in the ATH object member sc_slottime
1829 */
1830
1831 void ath_setslottime(struct ath_softc *sc)
1832 {
1833 ath9k_hw_setslottime(sc->sc_ah, sc->sc_slottime);
1834 sc->sc_updateslot = OK;
1835 }
Linux kernel - Deliverables
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