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ath9k: Add new Atheros IEEE 802.11n driver
[deliverable/linux.git] / drivers / net / wireless / ath9k / core.c
1 /*
2 * Copyright (c) 2008, Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 /* Implementation of the main "ATH" layer. */
18
19 #include "core.h"
20 #include "regd.h"
21
22 static int ath_outdoor; /* enable outdoor use */
23
24 static const u8 ath_bcast_mac[ETH_ALEN] =
25 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
26
27 static u32 ath_chainmask_sel_up_rssi_thres =
28 ATH_CHAINMASK_SEL_UP_RSSI_THRES;
29 static u32 ath_chainmask_sel_down_rssi_thres =
30 ATH_CHAINMASK_SEL_DOWN_RSSI_THRES;
31 static u32 ath_chainmask_sel_period =
32 ATH_CHAINMASK_SEL_TIMEOUT;
33
34 /* return bus cachesize in 4B word units */
35
36 static void bus_read_cachesize(struct ath_softc *sc, int *csz)
37 {
38 u8 u8tmp;
39
40 pci_read_config_byte(sc->pdev, PCI_CACHE_LINE_SIZE, (u8 *)&u8tmp);
41 *csz = (int)u8tmp;
42
43 /*
44 * This check was put in to avoid "unplesant" consequences if
45 * the bootrom has not fully initialized all PCI devices.
46 * Sometimes the cache line size register is not set
47 */
48
49 if (*csz == 0)
50 *csz = DEFAULT_CACHELINE >> 2; /* Use the default size */
51 }
52
53 /*
54 * Set current operating mode
55 *
56 * This function initializes and fills the rate table in the ATH object based
57 * on the operating mode. The blink rates are also set up here, although
58 * they have been superceeded by the ath_led module.
59 */
60
61 static void ath_setcurmode(struct ath_softc *sc, enum wireless_mode mode)
62 {
63 const struct ath9k_rate_table *rt;
64 int i;
65
66 memset(sc->sc_rixmap, 0xff, sizeof(sc->sc_rixmap));
67 rt = sc->sc_rates[mode];
68 BUG_ON(!rt);
69
70 for (i = 0; i < rt->rateCount; i++)
71 sc->sc_rixmap[rt->info[i].rateCode] = (u8) i;
72
73 memzero(sc->sc_hwmap, sizeof(sc->sc_hwmap));
74 for (i = 0; i < 256; i++) {
75 u8 ix = rt->rateCodeToIndex[i];
76
77 if (ix == 0xff)
78 continue;
79
80 sc->sc_hwmap[i].ieeerate =
81 rt->info[ix].dot11Rate & IEEE80211_RATE_VAL;
82 sc->sc_hwmap[i].rateKbps = rt->info[ix].rateKbps;
83
84 if (rt->info[ix].shortPreamble ||
85 rt->info[ix].phy == PHY_OFDM) {
86 /* XXX: Handle this */
87 }
88
89 /* NB: this uses the last entry if the rate isn't found */
90 /* XXX beware of overlow */
91 }
92 sc->sc_currates = rt;
93 sc->sc_curmode = mode;
94 /*
95 * All protection frames are transmited at 2Mb/s for
96 * 11g, otherwise at 1Mb/s.
97 * XXX select protection rate index from rate table.
98 */
99 sc->sc_protrix = (mode == WIRELESS_MODE_11g ? 1 : 0);
100 /* rate index used to send mgt frames */
101 sc->sc_minrateix = 0;
102 }
103
104 /*
105 * Select Rate Table
106 *
107 * Based on the wireless mode passed in, the rate table in the ATH object
108 * is set to the mode specific rate table. This also calls the callback
109 * function to set the rate in the protocol layer object.
110 */
111
112 static int ath_rate_setup(struct ath_softc *sc, enum wireless_mode mode)
113 {
114 struct ath_hal *ah = sc->sc_ah;
115 const struct ath9k_rate_table *rt;
116
117 switch (mode) {
118 case WIRELESS_MODE_11a:
119 sc->sc_rates[mode] =
120 ath9k_hw_getratetable(ah, ATH9K_MODE_SEL_11A);
121 break;
122 case WIRELESS_MODE_11b:
123 sc->sc_rates[mode] =
124 ath9k_hw_getratetable(ah, ATH9K_MODE_SEL_11B);
125 break;
126 case WIRELESS_MODE_11g:
127 sc->sc_rates[mode] =
128 ath9k_hw_getratetable(ah, ATH9K_MODE_SEL_11G);
129 break;
130 case WIRELESS_MODE_11NA_HT20:
131 sc->sc_rates[mode] =
132 ath9k_hw_getratetable(ah, ATH9K_MODE_SEL_11NA_HT20);
133 break;
134 case WIRELESS_MODE_11NG_HT20:
135 sc->sc_rates[mode] =
136 ath9k_hw_getratetable(ah, ATH9K_MODE_SEL_11NG_HT20);
137 break;
138 case WIRELESS_MODE_11NA_HT40PLUS:
139 sc->sc_rates[mode] =
140 ath9k_hw_getratetable(ah, ATH9K_MODE_SEL_11NA_HT40PLUS);
141 break;
142 case WIRELESS_MODE_11NA_HT40MINUS:
143 sc->sc_rates[mode] =
144 ath9k_hw_getratetable(ah,
145 ATH9K_MODE_SEL_11NA_HT40MINUS);
146 break;
147 case WIRELESS_MODE_11NG_HT40PLUS:
148 sc->sc_rates[mode] =
149 ath9k_hw_getratetable(ah, ATH9K_MODE_SEL_11NG_HT40PLUS);
150 break;
151 case WIRELESS_MODE_11NG_HT40MINUS:
152 sc->sc_rates[mode] =
153 ath9k_hw_getratetable(ah,
154 ATH9K_MODE_SEL_11NG_HT40MINUS);
155 break;
156 default:
157 DPRINTF(sc, ATH_DBG_FATAL, "%s: invalid mode %u\n",
158 __func__, mode);
159 return 0;
160 }
161 rt = sc->sc_rates[mode];
162 if (rt == NULL)
163 return 0;
164
165 /* setup rate set in 802.11 protocol layer */
166 ath_setup_rate(sc, mode, NORMAL_RATE, rt);
167
168 return 1;
169 }
170
171 /*
172 * Set up channel list
173 */
174 static int ath_setup_channels(struct ath_softc *sc)
175 {
176 struct ath_hal *ah = sc->sc_ah;
177 int nchan, i, a = 0, b = 0;
178 u8 regclassids[ATH_REGCLASSIDS_MAX];
179 u32 nregclass = 0;
180 struct ieee80211_supported_band *band_2ghz;
181 struct ieee80211_supported_band *band_5ghz;
182 struct ieee80211_channel *chan_2ghz;
183 struct ieee80211_channel *chan_5ghz;
184 struct ath9k_channel *c;
185
186 /* Fill in ah->ah_channels */
187 if (!ath9k_regd_init_channels(ah,
188 ATH_CHAN_MAX,
189 (u32 *)&nchan,
190 regclassids,
191 ATH_REGCLASSIDS_MAX,
192 &nregclass,
193 CTRY_DEFAULT,
194 ATH9K_MODE_SEL_ALL,
195 false,
196 1)) {
197 u32 rd = ah->ah_currentRD;
198
199 DPRINTF(sc, ATH_DBG_FATAL,
200 "%s: unable to collect channel list; "
201 "regdomain likely %u country code %u\n",
202 __func__, rd, CTRY_DEFAULT);
203 return -EINVAL;
204 }
205
206 band_2ghz = &sc->sbands[IEEE80211_BAND_2GHZ];
207 band_5ghz = &sc->sbands[IEEE80211_BAND_5GHZ];
208 chan_2ghz = sc->channels[IEEE80211_BAND_2GHZ];
209 chan_5ghz = sc->channels[IEEE80211_BAND_5GHZ];
210
211 for (i = 0; i < nchan; i++) {
212 c = &ah->ah_channels[i];
213 if (IS_CHAN_2GHZ(c)) {
214 chan_2ghz[a].band = IEEE80211_BAND_2GHZ;
215 chan_2ghz[a].center_freq = c->channel;
216 chan_2ghz[a].max_power = c->maxTxPower;
217
218 if (c->privFlags & CHANNEL_DISALLOW_ADHOC)
219 chan_2ghz[a].flags |=
220 IEEE80211_CHAN_NO_IBSS;
221 if (c->channelFlags & CHANNEL_PASSIVE)
222 chan_2ghz[a].flags |=
223 IEEE80211_CHAN_PASSIVE_SCAN;
224
225 band_2ghz->n_channels = ++a;
226
227 DPRINTF(sc, ATH_DBG_CONFIG,
228 "%s: 2MHz channel: %d, "
229 "channelFlags: 0x%x\n",
230 __func__,
231 c->channel,
232 c->channelFlags);
233 } else if (IS_CHAN_5GHZ(c)) {
234 chan_5ghz[b].band = IEEE80211_BAND_5GHZ;
235 chan_5ghz[b].center_freq = c->channel;
236 chan_5ghz[b].max_power = c->maxTxPower;
237
238 if (c->privFlags & CHANNEL_DISALLOW_ADHOC)
239 chan_5ghz[b].flags |=
240 IEEE80211_CHAN_NO_IBSS;
241 if (c->channelFlags & CHANNEL_PASSIVE)
242 chan_5ghz[b].flags |=
243 IEEE80211_CHAN_PASSIVE_SCAN;
244
245 band_5ghz->n_channels = ++b;
246
247 DPRINTF(sc, ATH_DBG_CONFIG,
248 "%s: 5MHz channel: %d, "
249 "channelFlags: 0x%x\n",
250 __func__,
251 c->channel,
252 c->channelFlags);
253 }
254 }
255
256 return 0;
257 }
258
259 /*
260 * Determine mode from channel flags
261 *
262 * This routine will provide the enumerated WIRELESSS_MODE value based
263 * on the settings of the channel flags. If ho valid set of flags
264 * exist, the lowest mode (11b) is selected.
265 */
266
267 static enum wireless_mode ath_chan2mode(struct ath9k_channel *chan)
268 {
269 if (chan->chanmode == CHANNEL_A)
270 return WIRELESS_MODE_11a;
271 else if (chan->chanmode == CHANNEL_G)
272 return WIRELESS_MODE_11g;
273 else if (chan->chanmode == CHANNEL_B)
274 return WIRELESS_MODE_11b;
275 else if (chan->chanmode == CHANNEL_A_HT20)
276 return WIRELESS_MODE_11NA_HT20;
277 else if (chan->chanmode == CHANNEL_G_HT20)
278 return WIRELESS_MODE_11NG_HT20;
279 else if (chan->chanmode == CHANNEL_A_HT40PLUS)
280 return WIRELESS_MODE_11NA_HT40PLUS;
281 else if (chan->chanmode == CHANNEL_A_HT40MINUS)
282 return WIRELESS_MODE_11NA_HT40MINUS;
283 else if (chan->chanmode == CHANNEL_G_HT40PLUS)
284 return WIRELESS_MODE_11NG_HT40PLUS;
285 else if (chan->chanmode == CHANNEL_G_HT40MINUS)
286 return WIRELESS_MODE_11NG_HT40MINUS;
287
288 /* NB: should not get here */
289 return WIRELESS_MODE_11b;
290 }
291
292 /*
293 * Change Channels
294 *
295 * Performs the actions to change the channel in the hardware, and set up
296 * the current operating mode for the new channel.
297 */
298
299 static void ath_chan_change(struct ath_softc *sc, struct ath9k_channel *chan)
300 {
301 enum wireless_mode mode;
302
303 mode = ath_chan2mode(chan);
304
305 ath_rate_setup(sc, mode);
306 ath_setcurmode(sc, mode);
307 }
308
309 /*
310 * Stop the device, grabbing the top-level lock to protect
311 * against concurrent entry through ath_init (which can happen
312 * if another thread does a system call and the thread doing the
313 * stop is preempted).
314 */
315
316 static int ath_stop(struct ath_softc *sc)
317 {
318 struct ath_hal *ah = sc->sc_ah;
319
320 DPRINTF(sc, ATH_DBG_CONFIG, "%s: invalid %u\n",
321 __func__, sc->sc_invalid);
322
323 /*
324 * Shutdown the hardware and driver:
325 * stop output from above
326 * reset 802.11 state machine
327 * (sends station deassoc/deauth frames)
328 * turn off timers
329 * disable interrupts
330 * clear transmit machinery
331 * clear receive machinery
332 * turn off the radio
333 * reclaim beacon resources
334 *
335 * Note that some of this work is not possible if the
336 * hardware is gone (invalid).
337 */
338
339 if (!sc->sc_invalid)
340 ath9k_hw_set_interrupts(ah, 0);
341 ath_draintxq(sc, false);
342 if (!sc->sc_invalid) {
343 ath_stoprecv(sc);
344 ath9k_hw_phy_disable(ah);
345 } else
346 sc->sc_rxlink = NULL;
347
348 return 0;
349 }
350
351 /*
352 * Start Scan
353 *
354 * This function is called when starting a channel scan. It will perform
355 * power save wakeup processing, set the filter for the scan, and get the
356 * chip ready to send broadcast packets out during the scan.
357 */
358
359 void ath_scan_start(struct ath_softc *sc)
360 {
361 struct ath_hal *ah = sc->sc_ah;
362 u32 rfilt;
363 u32 now = (u32) jiffies_to_msecs(get_timestamp());
364
365 sc->sc_scanning = 1;
366 rfilt = ath_calcrxfilter(sc);
367 ath9k_hw_setrxfilter(ah, rfilt);
368 ath9k_hw_write_associd(ah, ath_bcast_mac, 0);
369
370 /* Restore previous power management state. */
371
372 DPRINTF(sc, ATH_DBG_CONFIG, "%d.%03d | %s: RX filter 0x%x aid 0\n",
373 now / 1000, now % 1000, __func__, rfilt);
374 }
375
376 /*
377 * Scan End
378 *
379 * This routine is called by the upper layer when the scan is completed. This
380 * will set the filters back to normal operating mode, set the BSSID to the
381 * correct value, and restore the power save state.
382 */
383
384 void ath_scan_end(struct ath_softc *sc)
385 {
386 struct ath_hal *ah = sc->sc_ah;
387 u32 rfilt;
388 u32 now = (u32) jiffies_to_msecs(get_timestamp());
389
390 sc->sc_scanning = 0;
391 /* Request for a full reset due to rx packet filter changes */
392 sc->sc_full_reset = 1;
393 rfilt = ath_calcrxfilter(sc);
394 ath9k_hw_setrxfilter(ah, rfilt);
395 ath9k_hw_write_associd(ah, sc->sc_curbssid, sc->sc_curaid);
396
397 DPRINTF(sc, ATH_DBG_CONFIG, "%d.%03d | %s: RX filter 0x%x aid 0x%x\n",
398 now / 1000, now % 1000, __func__, rfilt, sc->sc_curaid);
399 }
400
401 /*
402 * Set the current channel
403 *
404 * Set/change channels. If the channel is really being changed, it's done
405 * by reseting the chip. To accomplish this we must first cleanup any pending
406 * DMA, then restart stuff after a la ath_init.
407 */
408 int ath_set_channel(struct ath_softc *sc, struct ath9k_channel *hchan)
409 {
410 struct ath_hal *ah = sc->sc_ah;
411 bool fastcc = true, stopped;
412 enum ath9k_ht_macmode ht_macmode;
413
414 if (sc->sc_invalid) /* if the device is invalid or removed */
415 return -EIO;
416
417 DPRINTF(sc, ATH_DBG_CONFIG,
418 "%s: %u (%u MHz) -> %u (%u MHz), cflags:%x\n",
419 __func__,
420 ath9k_hw_mhz2ieee(ah, sc->sc_curchan.channel,
421 sc->sc_curchan.channelFlags),
422 sc->sc_curchan.channel,
423 ath9k_hw_mhz2ieee(ah, hchan->channel, hchan->channelFlags),
424 hchan->channel, hchan->channelFlags);
425
426 ht_macmode = ath_cwm_macmode(sc);
427
428 if (hchan->channel != sc->sc_curchan.channel ||
429 hchan->channelFlags != sc->sc_curchan.channelFlags ||
430 sc->sc_update_chainmask || sc->sc_full_reset) {
431 int status;
432 /*
433 * This is only performed if the channel settings have
434 * actually changed.
435 *
436 * To switch channels clear any pending DMA operations;
437 * wait long enough for the RX fifo to drain, reset the
438 * hardware at the new frequency, and then re-enable
439 * the relevant bits of the h/w.
440 */
441 ath9k_hw_set_interrupts(ah, 0); /* disable interrupts */
442 ath_draintxq(sc, false); /* clear pending tx frames */
443 stopped = ath_stoprecv(sc); /* turn off frame recv */
444
445 /* XXX: do not flush receive queue here. We don't want
446 * to flush data frames already in queue because of
447 * changing channel. */
448
449 if (!stopped || sc->sc_full_reset)
450 fastcc = false;
451
452 spin_lock_bh(&sc->sc_resetlock);
453 if (!ath9k_hw_reset(ah, sc->sc_opmode, hchan,
454 ht_macmode, sc->sc_tx_chainmask,
455 sc->sc_rx_chainmask,
456 sc->sc_ht_extprotspacing,
457 fastcc, &status)) {
458 DPRINTF(sc, ATH_DBG_FATAL,
459 "%s: unable to reset channel %u (%uMhz) "
460 "flags 0x%x hal status %u\n", __func__,
461 ath9k_hw_mhz2ieee(ah, hchan->channel,
462 hchan->channelFlags),
463 hchan->channel, hchan->channelFlags, status);
464 spin_unlock_bh(&sc->sc_resetlock);
465 return -EIO;
466 }
467 spin_unlock_bh(&sc->sc_resetlock);
468
469 sc->sc_curchan = *hchan;
470 sc->sc_update_chainmask = 0;
471 sc->sc_full_reset = 0;
472
473 /* Re-enable rx framework */
474 if (ath_startrecv(sc) != 0) {
475 DPRINTF(sc, ATH_DBG_FATAL,
476 "%s: unable to restart recv logic\n", __func__);
477 return -EIO;
478 }
479 /*
480 * Change channels and update the h/w rate map
481 * if we're switching; e.g. 11a to 11b/g.
482 */
483 ath_chan_change(sc, hchan);
484 ath_update_txpow(sc); /* update tx power state */
485 /*
486 * Re-enable interrupts.
487 */
488 ath9k_hw_set_interrupts(ah, sc->sc_imask);
489 }
490 return 0;
491 }
492
493 /**********************/
494 /* Chainmask Handling */
495 /**********************/
496
497 static void ath_chainmask_sel_timertimeout(unsigned long data)
498 {
499 struct ath_chainmask_sel *cm = (struct ath_chainmask_sel *)data;
500 cm->switch_allowed = 1;
501 }
502
503 /* Start chainmask select timer */
504 static void ath_chainmask_sel_timerstart(struct ath_chainmask_sel *cm)
505 {
506 cm->switch_allowed = 0;
507 mod_timer(&cm->timer, ath_chainmask_sel_period);
508 }
509
510 /* Stop chainmask select timer */
511 static void ath_chainmask_sel_timerstop(struct ath_chainmask_sel *cm)
512 {
513 cm->switch_allowed = 0;
514 del_timer_sync(&cm->timer);
515 }
516
517 static void ath_chainmask_sel_init(struct ath_softc *sc, struct ath_node *an)
518 {
519 struct ath_chainmask_sel *cm = &an->an_chainmask_sel;
520
521 memzero(cm, sizeof(struct ath_chainmask_sel));
522
523 cm->cur_tx_mask = sc->sc_tx_chainmask;
524 cm->cur_rx_mask = sc->sc_rx_chainmask;
525 cm->tx_avgrssi = ATH_RSSI_DUMMY_MARKER;
526 setup_timer(&cm->timer,
527 ath_chainmask_sel_timertimeout, (unsigned long) cm);
528 }
529
530 int ath_chainmask_sel_logic(struct ath_softc *sc, struct ath_node *an)
531 {
532 struct ath_chainmask_sel *cm = &an->an_chainmask_sel;
533
534 /*
535 * Disable auto-swtiching in one of the following if conditions.
536 * sc_chainmask_auto_sel is used for internal global auto-switching
537 * enabled/disabled setting
538 */
539 if (sc->sc_ah->ah_caps.halTxChainMask != ATH_CHAINMASK_SEL_3X3) {
540 cm->cur_tx_mask = sc->sc_tx_chainmask;
541 return cm->cur_tx_mask;
542 }
543
544 if (cm->tx_avgrssi == ATH_RSSI_DUMMY_MARKER)
545 return cm->cur_tx_mask;
546
547 if (cm->switch_allowed) {
548 /* Switch down from tx 3 to tx 2. */
549 if (cm->cur_tx_mask == ATH_CHAINMASK_SEL_3X3 &&
550 ATH_RSSI_OUT(cm->tx_avgrssi) >=
551 ath_chainmask_sel_down_rssi_thres) {
552 cm->cur_tx_mask = sc->sc_tx_chainmask;
553
554 /* Don't let another switch happen until
555 * this timer expires */
556 ath_chainmask_sel_timerstart(cm);
557 }
558 /* Switch up from tx 2 to 3. */
559 else if (cm->cur_tx_mask == sc->sc_tx_chainmask &&
560 ATH_RSSI_OUT(cm->tx_avgrssi) <=
561 ath_chainmask_sel_up_rssi_thres) {
562 cm->cur_tx_mask = ATH_CHAINMASK_SEL_3X3;
563
564 /* Don't let another switch happen
565 * until this timer expires */
566 ath_chainmask_sel_timerstart(cm);
567 }
568 }
569
570 return cm->cur_tx_mask;
571 }
572
573 /*
574 * Update tx/rx chainmask. For legacy association,
575 * hard code chainmask to 1x1, for 11n association, use
576 * the chainmask configuration.
577 */
578
579 void ath_update_chainmask(struct ath_softc *sc, int is_ht)
580 {
581 sc->sc_update_chainmask = 1;
582 if (is_ht) {
583 sc->sc_tx_chainmask = sc->sc_ah->ah_caps.halTxChainMask;
584 sc->sc_rx_chainmask = sc->sc_ah->ah_caps.halRxChainMask;
585 } else {
586 sc->sc_tx_chainmask = 1;
587 sc->sc_rx_chainmask = 1;
588 }
589
590 DPRINTF(sc, ATH_DBG_CONFIG, "%s: tx chmask: %d, rx chmask: %d\n",
591 __func__, sc->sc_tx_chainmask, sc->sc_rx_chainmask);
592 }
593
594 /******************/
595 /* VAP management */
596 /******************/
597
598 /*
599 * VAP in Listen mode
600 *
601 * This routine brings the VAP out of the down state into a "listen" state
602 * where it waits for association requests. This is used in AP and AdHoc
603 * modes.
604 */
605
606 int ath_vap_listen(struct ath_softc *sc, int if_id)
607 {
608 struct ath_hal *ah = sc->sc_ah;
609 struct ath_vap *avp;
610 u32 rfilt = 0;
611 DECLARE_MAC_BUF(mac);
612
613 avp = sc->sc_vaps[if_id];
614 if (avp == NULL) {
615 DPRINTF(sc, ATH_DBG_FATAL, "%s: invalid interface id %u\n",
616 __func__, if_id);
617 return -EINVAL;
618 }
619
620 #ifdef CONFIG_SLOW_ANT_DIV
621 ath_slow_ant_div_stop(&sc->sc_antdiv);
622 #endif
623
624 /* update ratectrl about the new state */
625 ath_rate_newstate(sc, avp);
626
627 rfilt = ath_calcrxfilter(sc);
628 ath9k_hw_setrxfilter(ah, rfilt);
629
630 if (sc->sc_opmode == ATH9K_M_STA || sc->sc_opmode == ATH9K_M_IBSS) {
631 memcpy(sc->sc_curbssid, ath_bcast_mac, ETH_ALEN);
632 ath9k_hw_write_associd(ah, sc->sc_curbssid, sc->sc_curaid);
633 } else
634 sc->sc_curaid = 0;
635
636 DPRINTF(sc, ATH_DBG_CONFIG,
637 "%s: RX filter 0x%x bssid %s aid 0x%x\n",
638 __func__, rfilt, print_mac(mac,
639 sc->sc_curbssid), sc->sc_curaid);
640
641 /*
642 * XXXX
643 * Disable BMISS interrupt when we're not associated
644 */
645 ath9k_hw_set_interrupts(ah,
646 sc->sc_imask & ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS));
647 sc->sc_imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
648 /* need to reconfigure the beacons when it moves to RUN */
649 sc->sc_beacons = 0;
650
651 return 0;
652 }
653
654 int ath_vap_attach(struct ath_softc *sc,
655 int if_id,
656 struct ieee80211_vif *if_data,
657 enum ath9k_opmode opmode)
658 {
659 struct ath_vap *avp;
660
661 if (if_id >= ATH_BCBUF || sc->sc_vaps[if_id] != NULL) {
662 DPRINTF(sc, ATH_DBG_FATAL,
663 "%s: Invalid interface id = %u\n", __func__, if_id);
664 return -EINVAL;
665 }
666
667 switch (opmode) {
668 case ATH9K_M_STA:
669 case ATH9K_M_IBSS:
670 case ATH9K_M_MONITOR:
671 break;
672 case ATH9K_M_HOSTAP:
673 /* XXX not right, beacon buffer is allocated on RUN trans */
674 if (list_empty(&sc->sc_bbuf))
675 return -ENOMEM;
676 break;
677 default:
678 return -EINVAL;
679 }
680
681 /* create ath_vap */
682 avp = kmalloc(sizeof(struct ath_vap), GFP_KERNEL);
683 if (avp == NULL)
684 return -ENOMEM;
685
686 memzero(avp, sizeof(struct ath_vap));
687 avp->av_if_data = if_data;
688 /* Set the VAP opmode */
689 avp->av_opmode = opmode;
690 avp->av_bslot = -1;
691 INIT_LIST_HEAD(&avp->av_mcastq.axq_q);
692 INIT_LIST_HEAD(&avp->av_mcastq.axq_acq);
693 spin_lock_init(&avp->av_mcastq.axq_lock);
694
695 ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
696
697 sc->sc_vaps[if_id] = avp;
698 sc->sc_nvaps++;
699 /* Set the device opmode */
700 sc->sc_opmode = opmode;
701
702 /* default VAP configuration */
703 avp->av_config.av_fixed_rateset = IEEE80211_FIXED_RATE_NONE;
704 avp->av_config.av_fixed_retryset = 0x03030303;
705
706 return 0;
707 }
708
709 int ath_vap_detach(struct ath_softc *sc, int if_id)
710 {
711 struct ath_hal *ah = sc->sc_ah;
712 struct ath_vap *avp;
713
714 avp = sc->sc_vaps[if_id];
715 if (avp == NULL) {
716 DPRINTF(sc, ATH_DBG_FATAL, "%s: invalid interface id %u\n",
717 __func__, if_id);
718 return -EINVAL;
719 }
720
721 /*
722 * Quiesce the hardware while we remove the vap. In
723 * particular we need to reclaim all references to the
724 * vap state by any frames pending on the tx queues.
725 *
726 * XXX can we do this w/o affecting other vap's?
727 */
728 ath9k_hw_set_interrupts(ah, 0); /* disable interrupts */
729 ath_draintxq(sc, false); /* stop xmit side */
730 ath_stoprecv(sc); /* stop recv side */
731 ath_flushrecv(sc); /* flush recv queue */
732
733 /* Reclaim any pending mcast bufs on the vap. */
734 ath_tx_draintxq(sc, &avp->av_mcastq, false);
735
736 kfree(avp);
737 sc->sc_vaps[if_id] = NULL;
738 sc->sc_nvaps--;
739
740 return 0;
741 }
742
743 int ath_vap_config(struct ath_softc *sc,
744 int if_id, struct ath_vap_config *if_config)
745 {
746 struct ath_vap *avp;
747
748 if (if_id >= ATH_BCBUF) {
749 DPRINTF(sc, ATH_DBG_FATAL,
750 "%s: Invalid interface id = %u\n", __func__, if_id);
751 return -EINVAL;
752 }
753
754 avp = sc->sc_vaps[if_id];
755 ASSERT(avp != NULL);
756
757 if (avp)
758 memcpy(&avp->av_config, if_config, sizeof(avp->av_config));
759
760 return 0;
761 }
762
763 /********/
764 /* Core */
765 /********/
766
767 int ath_open(struct ath_softc *sc, struct ath9k_channel *initial_chan)
768 {
769 struct ath_hal *ah = sc->sc_ah;
770 int status;
771 int error = 0;
772 enum ath9k_ht_macmode ht_macmode = ath_cwm_macmode(sc);
773
774 DPRINTF(sc, ATH_DBG_CONFIG, "%s: mode %d\n", __func__, sc->sc_opmode);
775
776 /*
777 * Stop anything previously setup. This is safe
778 * whether this is the first time through or not.
779 */
780 ath_stop(sc);
781
782 /* Initialize chanmask selection */
783 sc->sc_tx_chainmask = ah->ah_caps.halTxChainMask;
784 sc->sc_rx_chainmask = ah->ah_caps.halRxChainMask;
785
786 /* Reset SERDES registers */
787 ath9k_hw_configpcipowersave(ah, 0);
788
789 /*
790 * The basic interface to setting the hardware in a good
791 * state is ``reset''. On return the hardware is known to
792 * be powered up and with interrupts disabled. This must
793 * be followed by initialization of the appropriate bits
794 * and then setup of the interrupt mask.
795 */
796 sc->sc_curchan = *initial_chan;
797
798 spin_lock_bh(&sc->sc_resetlock);
799 if (!ath9k_hw_reset(ah, sc->sc_opmode, &sc->sc_curchan, ht_macmode,
800 sc->sc_tx_chainmask, sc->sc_rx_chainmask,
801 sc->sc_ht_extprotspacing, false, &status)) {
802 DPRINTF(sc, ATH_DBG_FATAL,
803 "%s: unable to reset hardware; hal status %u "
804 "(freq %u flags 0x%x)\n", __func__, status,
805 sc->sc_curchan.channel, sc->sc_curchan.channelFlags);
806 error = -EIO;
807 spin_unlock_bh(&sc->sc_resetlock);
808 goto done;
809 }
810 spin_unlock_bh(&sc->sc_resetlock);
811 /*
812 * This is needed only to setup initial state
813 * but it's best done after a reset.
814 */
815 ath_update_txpow(sc);
816
817 /*
818 * Setup the hardware after reset:
819 * The receive engine is set going.
820 * Frame transmit is handled entirely
821 * in the frame output path; there's nothing to do
822 * here except setup the interrupt mask.
823 */
824 if (ath_startrecv(sc) != 0) {
825 DPRINTF(sc, ATH_DBG_FATAL,
826 "%s: unable to start recv logic\n", __func__);
827 error = -EIO;
828 goto done;
829 }
830 /* Setup our intr mask. */
831 sc->sc_imask = ATH9K_INT_RX | ATH9K_INT_TX
832 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
833 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
834
835 if (ah->ah_caps.halGTTSupport)
836 sc->sc_imask |= ATH9K_INT_GTT;
837
838 if (ah->ah_caps.halHTSupport)
839 sc->sc_imask |= ATH9K_INT_CST;
840
841 /*
842 * Enable MIB interrupts when there are hardware phy counters.
843 * Note we only do this (at the moment) for station mode.
844 */
845 if (ath9k_hw_phycounters(ah) &&
846 ((sc->sc_opmode == ATH9K_M_STA) || (sc->sc_opmode == ATH9K_M_IBSS)))
847 sc->sc_imask |= ATH9K_INT_MIB;
848 /*
849 * Some hardware processes the TIM IE and fires an
850 * interrupt when the TIM bit is set. For hardware
851 * that does, if not overridden by configuration,
852 * enable the TIM interrupt when operating as station.
853 */
854 if (ah->ah_caps.halEnhancedPmSupport && sc->sc_opmode == ATH9K_M_STA &&
855 !sc->sc_config.swBeaconProcess)
856 sc->sc_imask |= ATH9K_INT_TIM;
857 /*
858 * Don't enable interrupts here as we've not yet built our
859 * vap and node data structures, which will be needed as soon
860 * as we start receiving.
861 */
862 ath_chan_change(sc, initial_chan);
863
864 /* XXX: we must make sure h/w is ready and clear invalid flag
865 * before turning on interrupt. */
866 sc->sc_invalid = 0;
867 done:
868 return error;
869 }
870
871 /*
872 * Reset the hardware w/o losing operational state. This is
873 * basically a more efficient way of doing ath_stop, ath_init,
874 * followed by state transitions to the current 802.11
875 * operational state. Used to recover from errors rx overrun
876 * and to reset the hardware when rf gain settings must be reset.
877 */
878
879 static int ath_reset_start(struct ath_softc *sc, u32 flag)
880 {
881 struct ath_hal *ah = sc->sc_ah;
882
883 ath9k_hw_set_interrupts(ah, 0); /* disable interrupts */
884 ath_draintxq(sc, flag & RESET_RETRY_TXQ); /* stop xmit side */
885 ath_stoprecv(sc); /* stop recv side */
886 ath_flushrecv(sc); /* flush recv queue */
887
888 return 0;
889 }
890
891 static int ath_reset_end(struct ath_softc *sc, u32 flag)
892 {
893 struct ath_hal *ah = sc->sc_ah;
894
895 if (ath_startrecv(sc) != 0) /* restart recv */
896 DPRINTF(sc, ATH_DBG_FATAL,
897 "%s: unable to start recv logic\n", __func__);
898
899 /*
900 * We may be doing a reset in response to a request
901 * that changes the channel so update any state that
902 * might change as a result.
903 */
904 ath_chan_change(sc, &sc->sc_curchan);
905
906 ath_update_txpow(sc); /* update tx power state */
907
908 if (sc->sc_beacons)
909 ath_beacon_config(sc, ATH_IF_ID_ANY); /* restart beacons */
910 ath9k_hw_set_interrupts(ah, sc->sc_imask);
911
912 /* Restart the txq */
913 if (flag & RESET_RETRY_TXQ) {
914 int i;
915 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
916 if (ATH_TXQ_SETUP(sc, i)) {
917 spin_lock_bh(&sc->sc_txq[i].axq_lock);
918 ath_txq_schedule(sc, &sc->sc_txq[i]);
919 spin_unlock_bh(&sc->sc_txq[i].axq_lock);
920 }
921 }
922 }
923 return 0;
924 }
925
926 int ath_reset(struct ath_softc *sc)
927 {
928 struct ath_hal *ah = sc->sc_ah;
929 int status;
930 int error = 0;
931 enum ath9k_ht_macmode ht_macmode = ath_cwm_macmode(sc);
932
933 /* NB: indicate channel change so we do a full reset */
934 spin_lock_bh(&sc->sc_resetlock);
935 if (!ath9k_hw_reset(ah, sc->sc_opmode, &sc->sc_curchan,
936 ht_macmode,
937 sc->sc_tx_chainmask, sc->sc_rx_chainmask,
938 sc->sc_ht_extprotspacing, false, &status)) {
939 DPRINTF(sc, ATH_DBG_FATAL,
940 "%s: unable to reset hardware; hal status %u\n",
941 __func__, status);
942 error = -EIO;
943 }
944 spin_unlock_bh(&sc->sc_resetlock);
945
946 return error;
947 }
948
949 int ath_suspend(struct ath_softc *sc)
950 {
951 struct ath_hal *ah = sc->sc_ah;
952
953 /* No I/O if device has been surprise removed */
954 if (sc->sc_invalid)
955 return -EIO;
956
957 /* Shut off the interrupt before setting sc->sc_invalid to '1' */
958 ath9k_hw_set_interrupts(ah, 0);
959
960 /* XXX: we must make sure h/w will not generate any interrupt
961 * before setting the invalid flag. */
962 sc->sc_invalid = 1;
963
964 /* disable HAL and put h/w to sleep */
965 ath9k_hw_disable(sc->sc_ah);
966
967 ath9k_hw_configpcipowersave(sc->sc_ah, 1);
968
969 return 0;
970 }
971
972 /* Interrupt handler. Most of the actual processing is deferred.
973 * It's the caller's responsibility to ensure the chip is awake. */
974
975 irqreturn_t ath_isr(int irq, void *dev)
976 {
977 struct ath_softc *sc = dev;
978 struct ath_hal *ah = sc->sc_ah;
979 enum ath9k_int status;
980 bool sched = false;
981
982 do {
983 if (sc->sc_invalid) {
984 /*
985 * The hardware is not ready/present, don't
986 * touch anything. Note this can happen early
987 * on if the IRQ is shared.
988 */
989 return IRQ_NONE;
990 }
991 if (!ath9k_hw_intrpend(ah)) { /* shared irq, not for us */
992 return IRQ_NONE;
993 }
994
995 /*
996 * Figure out the reason(s) for the interrupt. Note
997 * that the hal returns a pseudo-ISR that may include
998 * bits we haven't explicitly enabled so we mask the
999 * value to insure we only process bits we requested.
1000 */
1001 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
1002
1003 status &= sc->sc_imask; /* discard unasked-for bits */
1004
1005 /*
1006 * If there are no status bits set, then this interrupt was not
1007 * for me (should have been caught above).
1008 */
1009
1010 if (!status)
1011 return IRQ_NONE;
1012
1013 sc->sc_intrstatus = status;
1014
1015 if (status & ATH9K_INT_FATAL) {
1016 /* need a chip reset */
1017 sched = true;
1018 } else if (status & ATH9K_INT_RXORN) {
1019 /* need a chip reset */
1020 sched = true;
1021 } else {
1022 if (status & ATH9K_INT_SWBA) {
1023 /* schedule a tasklet for beacon handling */
1024 tasklet_schedule(&sc->bcon_tasklet);
1025 }
1026 if (status & ATH9K_INT_RXEOL) {
1027 /*
1028 * NB: the hardware should re-read the link when
1029 * RXE bit is written, but it doesn't work
1030 * at least on older hardware revs.
1031 */
1032 sched = true;
1033 }
1034
1035 if (status & ATH9K_INT_TXURN)
1036 /* bump tx trigger level */
1037 ath9k_hw_updatetxtriglevel(ah, true);
1038 /* XXX: optimize this */
1039 if (status & ATH9K_INT_RX)
1040 sched = true;
1041 if (status & ATH9K_INT_TX)
1042 sched = true;
1043 if (status & ATH9K_INT_BMISS)
1044 sched = true;
1045 /* carrier sense timeout */
1046 if (status & ATH9K_INT_CST)
1047 sched = true;
1048 if (status & ATH9K_INT_MIB) {
1049 /*
1050 * Disable interrupts until we service the MIB
1051 * interrupt; otherwise it will continue to
1052 * fire.
1053 */
1054 ath9k_hw_set_interrupts(ah, 0);
1055 /*
1056 * Let the hal handle the event. We assume
1057 * it will clear whatever condition caused
1058 * the interrupt.
1059 */
1060 ath9k_hw_procmibevent(ah, &sc->sc_halstats);
1061 ath9k_hw_set_interrupts(ah, sc->sc_imask);
1062 }
1063 if (status & ATH9K_INT_TIM_TIMER) {
1064 if (!ah->ah_caps.halAutoSleepSupport) {
1065 /* Clear RxAbort bit so that we can
1066 * receive frames */
1067 ath9k_hw_setrxabort(ah, 0);
1068 sched = true;
1069 }
1070 }
1071 }
1072 } while (0);
1073
1074 if (sched) {
1075 /* turn off every interrupt except SWBA */
1076 ath9k_hw_set_interrupts(ah, (sc->sc_imask & ATH9K_INT_SWBA));
1077 tasklet_schedule(&sc->intr_tq);
1078 }
1079
1080 return IRQ_HANDLED;
1081 }
1082
1083 /* Deferred interrupt processing */
1084
1085 static void ath9k_tasklet(unsigned long data)
1086 {
1087 struct ath_softc *sc = (struct ath_softc *)data;
1088 u32 status = sc->sc_intrstatus;
1089
1090 if (status & ATH9K_INT_FATAL) {
1091 /* need a chip reset */
1092 ath_internal_reset(sc);
1093 return;
1094 } else {
1095
1096 if (status &
1097 (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
1098 /* XXX: fill me in */
1099 /*
1100 if (status & ATH9K_INT_RXORN) {
1101 }
1102 if (status & ATH9K_INT_RXEOL) {
1103 }
1104 */
1105 spin_lock_bh(&sc->sc_rxflushlock);
1106 ath_rx_tasklet(sc, 0);
1107 spin_unlock_bh(&sc->sc_rxflushlock);
1108 }
1109 /* XXX: optimize this */
1110 if (status & ATH9K_INT_TX)
1111 ath_tx_tasklet(sc);
1112 /* XXX: fill me in */
1113 /*
1114 if (status & ATH9K_INT_BMISS) {
1115 }
1116 if (status & (ATH9K_INT_TIM | ATH9K_INT_DTIMSYNC)) {
1117 if (status & ATH9K_INT_TIM) {
1118 }
1119 if (status & ATH9K_INT_DTIMSYNC) {
1120 }
1121 }
1122 */
1123 }
1124
1125 /* re-enable hardware interrupt */
1126 ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_imask);
1127 }
1128
1129 int ath_init(u16 devid, struct ath_softc *sc)
1130 {
1131 struct ath_hal *ah = NULL;
1132 int status;
1133 int error = 0, i;
1134 int csz = 0;
1135 u32 rd;
1136
1137 /* XXX: hardware will not be ready until ath_open() being called */
1138 sc->sc_invalid = 1;
1139
1140 sc->sc_debug = DBG_DEFAULT;
1141 DPRINTF(sc, ATH_DBG_CONFIG, "%s: devid 0x%x\n", __func__, devid);
1142
1143 /* Initialize tasklet */
1144 tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
1145 tasklet_init(&sc->bcon_tasklet, ath9k_beacon_tasklet,
1146 (unsigned long)sc);
1147
1148 /*
1149 * Cache line size is used to size and align various
1150 * structures used to communicate with the hardware.
1151 */
1152 bus_read_cachesize(sc, &csz);
1153 /* XXX assert csz is non-zero */
1154 sc->sc_cachelsz = csz << 2; /* convert to bytes */
1155
1156 spin_lock_init(&sc->sc_resetlock);
1157
1158 ah = ath9k_hw_attach(devid, sc, sc->mem, &status);
1159 if (ah == NULL) {
1160 DPRINTF(sc, ATH_DBG_FATAL,
1161 "%s: unable to attach hardware; HAL status %u\n",
1162 __func__, status);
1163 error = -ENXIO;
1164 goto bad;
1165 }
1166 sc->sc_ah = ah;
1167
1168 /* Get the chipset-specific aggr limit. */
1169 sc->sc_rtsaggrlimit = ah->ah_caps.halRtsAggrLimit;
1170
1171 /* Get the hardware key cache size. */
1172 sc->sc_keymax = ah->ah_caps.halKeyCacheSize;
1173 if (sc->sc_keymax > ATH_KEYMAX) {
1174 DPRINTF(sc, ATH_DBG_KEYCACHE,
1175 "%s: Warning, using only %u entries in %u key cache\n",
1176 __func__, ATH_KEYMAX, sc->sc_keymax);
1177 sc->sc_keymax = ATH_KEYMAX;
1178 }
1179
1180 /*
1181 * Reset the key cache since some parts do not
1182 * reset the contents on initial power up.
1183 */
1184 for (i = 0; i < sc->sc_keymax; i++)
1185 ath9k_hw_keyreset(ah, (u16) i);
1186 /*
1187 * Mark key cache slots associated with global keys
1188 * as in use. If we knew TKIP was not to be used we
1189 * could leave the +32, +64, and +32+64 slots free.
1190 * XXX only for splitmic.
1191 */
1192 for (i = 0; i < IEEE80211_WEP_NKID; i++) {
1193 set_bit(i, sc->sc_keymap);
1194 set_bit(i + 32, sc->sc_keymap);
1195 set_bit(i + 64, sc->sc_keymap);
1196 set_bit(i + 32 + 64, sc->sc_keymap);
1197 }
1198 /*
1199 * Collect the channel list using the default country
1200 * code and including outdoor channels. The 802.11 layer
1201 * is resposible for filtering this list based on settings
1202 * like the phy mode.
1203 */
1204 rd = ah->ah_currentRD;
1205
1206 error = ath_setup_channels(sc);
1207 if (error)
1208 goto bad;
1209
1210 /* default to STA mode */
1211 sc->sc_opmode = ATH9K_M_MONITOR;
1212
1213 /* Setup rate tables for all potential media types. */
1214 /* 11g encompasses b,g */
1215
1216 ath_rate_setup(sc, WIRELESS_MODE_11a);
1217 ath_rate_setup(sc, WIRELESS_MODE_11g);
1218
1219 /* NB: setup here so ath_rate_update is happy */
1220 ath_setcurmode(sc, WIRELESS_MODE_11a);
1221
1222 /*
1223 * Allocate hardware transmit queues: one queue for
1224 * beacon frames and one data queue for each QoS
1225 * priority. Note that the hal handles reseting
1226 * these queues at the needed time.
1227 */
1228 sc->sc_bhalq = ath_beaconq_setup(ah);
1229 if (sc->sc_bhalq == -1) {
1230 DPRINTF(sc, ATH_DBG_FATAL,
1231 "%s: unable to setup a beacon xmit queue\n", __func__);
1232 error = -EIO;
1233 goto bad2;
1234 }
1235 sc->sc_cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1236 if (sc->sc_cabq == NULL) {
1237 DPRINTF(sc, ATH_DBG_FATAL,
1238 "%s: unable to setup CAB xmit queue\n", __func__);
1239 error = -EIO;
1240 goto bad2;
1241 }
1242
1243 sc->sc_config.cabqReadytime = ATH_CABQ_READY_TIME;
1244 ath_cabq_update(sc);
1245
1246 for (i = 0; i < ARRAY_SIZE(sc->sc_haltype2q); i++)
1247 sc->sc_haltype2q[i] = -1;
1248
1249 /* Setup data queues */
1250 /* NB: ensure BK queue is the lowest priority h/w queue */
1251 if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
1252 DPRINTF(sc, ATH_DBG_FATAL,
1253 "%s: unable to setup xmit queue for BK traffic\n",
1254 __func__);
1255 error = -EIO;
1256 goto bad2;
1257 }
1258
1259 if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
1260 DPRINTF(sc, ATH_DBG_FATAL,
1261 "%s: unable to setup xmit queue for BE traffic\n",
1262 __func__);
1263 error = -EIO;
1264 goto bad2;
1265 }
1266 if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
1267 DPRINTF(sc, ATH_DBG_FATAL,
1268 "%s: unable to setup xmit queue for VI traffic\n",
1269 __func__);
1270 error = -EIO;
1271 goto bad2;
1272 }
1273 if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
1274 DPRINTF(sc, ATH_DBG_FATAL,
1275 "%s: unable to setup xmit queue for VO traffic\n",
1276 __func__);
1277 error = -EIO;
1278 goto bad2;
1279 }
1280
1281 sc->sc_rc = ath_rate_attach(ah);
1282 if (sc->sc_rc == NULL) {
1283 error = EIO;
1284 goto bad2;
1285 }
1286
1287 if (ath9k_hw_getcapability(ah, HAL_CAP_CIPHER,
1288 ATH9K_CIPHER_TKIP, NULL)) {
1289 /*
1290 * Whether we should enable h/w TKIP MIC.
1291 * XXX: if we don't support WME TKIP MIC, then we wouldn't
1292 * report WMM capable, so it's always safe to turn on
1293 * TKIP MIC in this case.
1294 */
1295 ath9k_hw_setcapability(sc->sc_ah, HAL_CAP_TKIP_MIC, 0, 1, NULL);
1296 }
1297
1298 /*
1299 * Check whether the separate key cache entries
1300 * are required to handle both tx+rx MIC keys.
1301 * With split mic keys the number of stations is limited
1302 * to 27 otherwise 59.
1303 */
1304 if (ath9k_hw_getcapability(ah, HAL_CAP_CIPHER,
1305 ATH9K_CIPHER_TKIP, NULL)
1306 && ath9k_hw_getcapability(ah, HAL_CAP_CIPHER,
1307 ATH9K_CIPHER_MIC, NULL)
1308 && ath9k_hw_getcapability(ah, HAL_CAP_TKIP_SPLIT,
1309 0, NULL))
1310 sc->sc_splitmic = 1;
1311
1312 /* turn on mcast key search if possible */
1313 if (!ath9k_hw_getcapability(ah, HAL_CAP_MCAST_KEYSRCH, 0, NULL))
1314 (void)ath9k_hw_setcapability(ah, HAL_CAP_MCAST_KEYSRCH, 1,
1315 1, NULL);
1316
1317 sc->sc_config.txpowlimit = ATH_TXPOWER_MAX;
1318 sc->sc_config.txpowlimit_override = 0;
1319
1320 /* 11n Capabilities */
1321 if (ah->ah_caps.halHTSupport) {
1322 sc->sc_txaggr = 1;
1323 sc->sc_rxaggr = 1;
1324 }
1325
1326 sc->sc_tx_chainmask = ah->ah_caps.halTxChainMask;
1327 sc->sc_rx_chainmask = ah->ah_caps.halRxChainMask;
1328
1329 /* Configuration for rx chain detection */
1330 sc->sc_rxchaindetect_ref = 0;
1331 sc->sc_rxchaindetect_thresh5GHz = 35;
1332 sc->sc_rxchaindetect_thresh2GHz = 35;
1333 sc->sc_rxchaindetect_delta5GHz = 30;
1334 sc->sc_rxchaindetect_delta2GHz = 30;
1335
1336 ath9k_hw_setcapability(ah, HAL_CAP_DIVERSITY, 1, true, NULL);
1337 sc->sc_defant = ath9k_hw_getdefantenna(ah);
1338
1339 ath9k_hw_getmac(ah, sc->sc_myaddr);
1340 if (ah->ah_caps.halBssIdMaskSupport) {
1341 ath9k_hw_getbssidmask(ah, sc->sc_bssidmask);
1342 ATH_SET_VAP_BSSID_MASK(sc->sc_bssidmask);
1343 ath9k_hw_setbssidmask(ah, sc->sc_bssidmask);
1344 }
1345 sc->sc_slottime = ATH9K_SLOT_TIME_9; /* default to short slot time */
1346
1347 /* initialize beacon slots */
1348 for (i = 0; i < ARRAY_SIZE(sc->sc_bslot); i++)
1349 sc->sc_bslot[i] = ATH_IF_ID_ANY;
1350
1351 /* save MISC configurations */
1352 sc->sc_config.swBeaconProcess = 1;
1353
1354 #ifdef CONFIG_SLOW_ANT_DIV
1355 /* range is 40 - 255, we use something in the middle */
1356 ath_slow_ant_div_init(&sc->sc_antdiv, sc, 0x127);
1357 #endif
1358
1359 return 0;
1360 bad2:
1361 /* cleanup tx queues */
1362 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1363 if (ATH_TXQ_SETUP(sc, i))
1364 ath_tx_cleanupq(sc, &sc->sc_txq[i]);
1365 bad:
1366 if (ah)
1367 ath9k_hw_detach(ah);
1368 return error;
1369 }
1370
1371 void ath_deinit(struct ath_softc *sc)
1372 {
1373 struct ath_hal *ah = sc->sc_ah;
1374 int i;
1375
1376 DPRINTF(sc, ATH_DBG_CONFIG, "%s\n", __func__);
1377
1378 ath_stop(sc);
1379 if (!sc->sc_invalid)
1380 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
1381 ath_rate_detach(sc->sc_rc);
1382 /* cleanup tx queues */
1383 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1384 if (ATH_TXQ_SETUP(sc, i))
1385 ath_tx_cleanupq(sc, &sc->sc_txq[i]);
1386 ath9k_hw_detach(ah);
1387 }
1388
1389 /*******************/
1390 /* Node Management */
1391 /*******************/
1392
1393 struct ath_node *ath_node_attach(struct ath_softc *sc, u8 *addr, int if_id)
1394 {
1395 struct ath_vap *avp;
1396 struct ath_node *an;
1397 DECLARE_MAC_BUF(mac);
1398
1399 avp = sc->sc_vaps[if_id];
1400 ASSERT(avp != NULL);
1401
1402 /* mac80211 sta_notify callback is from an IRQ context, so no sleep */
1403 an = kmalloc(sizeof(struct ath_node), GFP_ATOMIC);
1404 if (an == NULL)
1405 return NULL;
1406 memzero(an, sizeof(*an));
1407
1408 an->an_sc = sc;
1409 memcpy(an->an_addr, addr, ETH_ALEN);
1410 atomic_set(&an->an_refcnt, 1);
1411
1412 /* set up per-node tx/rx state */
1413 ath_tx_node_init(sc, an);
1414 ath_rx_node_init(sc, an);
1415
1416 ath_chainmask_sel_init(sc, an);
1417 ath_chainmask_sel_timerstart(&an->an_chainmask_sel);
1418 list_add(&an->list, &sc->node_list);
1419
1420 return an;
1421 }
1422
1423 void ath_node_detach(struct ath_softc *sc, struct ath_node *an, bool bh_flag)
1424 {
1425 unsigned long flags;
1426
1427 DECLARE_MAC_BUF(mac);
1428
1429 ath_chainmask_sel_timerstop(&an->an_chainmask_sel);
1430 an->an_flags |= ATH_NODE_CLEAN;
1431 ath_tx_node_cleanup(sc, an, bh_flag);
1432 ath_rx_node_cleanup(sc, an);
1433
1434 ath_tx_node_free(sc, an);
1435 ath_rx_node_free(sc, an);
1436
1437 spin_lock_irqsave(&sc->node_lock, flags);
1438
1439 list_del(&an->list);
1440
1441 spin_unlock_irqrestore(&sc->node_lock, flags);
1442
1443 kfree(an);
1444 }
1445
1446 /* Finds a node and increases the refcnt if found */
1447
1448 struct ath_node *ath_node_get(struct ath_softc *sc, u8 *addr)
1449 {
1450 struct ath_node *an = NULL, *an_found = NULL;
1451
1452 if (list_empty(&sc->node_list)) /* FIXME */
1453 goto out;
1454 list_for_each_entry(an, &sc->node_list, list) {
1455 if (!compare_ether_addr(an->an_addr, addr)) {
1456 atomic_inc(&an->an_refcnt);
1457 an_found = an;
1458 break;
1459 }
1460 }
1461 out:
1462 return an_found;
1463 }
1464
1465 /* Decrements the refcnt and if it drops to zero, detach the node */
1466
1467 void ath_node_put(struct ath_softc *sc, struct ath_node *an, bool bh_flag)
1468 {
1469 if (atomic_dec_and_test(&an->an_refcnt))
1470 ath_node_detach(sc, an, bh_flag);
1471 }
1472
1473 /* Finds a node, doesn't increment refcnt. Caller must hold sc->node_lock */
1474 struct ath_node *ath_node_find(struct ath_softc *sc, u8 *addr)
1475 {
1476 struct ath_node *an = NULL, *an_found = NULL;
1477
1478 if (list_empty(&sc->node_list))
1479 return NULL;
1480
1481 list_for_each_entry(an, &sc->node_list, list)
1482 if (!compare_ether_addr(an->an_addr, addr)) {
1483 an_found = an;
1484 break;
1485 }
1486
1487 return an_found;
1488 }
1489
1490 /*
1491 * Set up New Node
1492 *
1493 * Setup driver-specific state for a newly associated node. This routine
1494 * really only applies if compression or XR are enabled, there is no code
1495 * covering any other cases.
1496 */
1497
1498 void ath_newassoc(struct ath_softc *sc,
1499 struct ath_node *an, int isnew, int isuapsd)
1500 {
1501 int tidno;
1502
1503 /* if station reassociates, tear down the aggregation state. */
1504 if (!isnew) {
1505 for (tidno = 0; tidno < WME_NUM_TID; tidno++) {
1506 if (sc->sc_txaggr)
1507 ath_tx_aggr_teardown(sc, an, tidno);
1508 if (sc->sc_rxaggr)
1509 ath_rx_aggr_teardown(sc, an, tidno);
1510 }
1511 }
1512 an->an_flags = 0;
1513 }
1514
1515 /**************/
1516 /* Encryption */
1517 /**************/
1518
1519 void ath_key_reset(struct ath_softc *sc, u16 keyix, int freeslot)
1520 {
1521 ath9k_hw_keyreset(sc->sc_ah, keyix);
1522 if (freeslot)
1523 clear_bit(keyix, sc->sc_keymap);
1524 }
1525
1526 int ath_keyset(struct ath_softc *sc,
1527 u16 keyix,
1528 struct ath9k_keyval *hk,
1529 const u8 mac[ETH_ALEN])
1530 {
1531 bool status;
1532
1533 status = ath9k_hw_set_keycache_entry(sc->sc_ah,
1534 keyix, hk, mac, false);
1535
1536 return status != false;
1537 }
1538
1539 /***********************/
1540 /* TX Power/Regulatory */
1541 /***********************/
1542
1543 /*
1544 * Set Transmit power in HAL
1545 *
1546 * This routine makes the actual HAL calls to set the new transmit power
1547 * limit.
1548 */
1549
1550 void ath_update_txpow(struct ath_softc *sc)
1551 {
1552 struct ath_hal *ah = sc->sc_ah;
1553 u32 txpow;
1554
1555 if (sc->sc_curtxpow != sc->sc_config.txpowlimit) {
1556 ath9k_hw_set_txpowerlimit(ah, sc->sc_config.txpowlimit);
1557 /* read back in case value is clamped */
1558 ath9k_hw_getcapability(ah, HAL_CAP_TXPOW, 1, &txpow);
1559 sc->sc_curtxpow = txpow;
1560 }
1561 }
1562
1563 /* Return the current country and domain information */
1564 void ath_get_currentCountry(struct ath_softc *sc,
1565 struct ath9k_country_entry *ctry)
1566 {
1567 ath9k_regd_get_current_country(sc->sc_ah, ctry);
1568
1569 /* If HAL not specific yet, since it is band dependent,
1570 * use the one we passed in. */
1571 if (ctry->countryCode == CTRY_DEFAULT) {
1572 ctry->iso[0] = 0;
1573 ctry->iso[1] = 0;
1574 } else if (ctry->iso[0] && ctry->iso[1]) {
1575 if (!ctry->iso[2]) {
1576 if (ath_outdoor)
1577 ctry->iso[2] = 'O';
1578 else
1579 ctry->iso[2] = 'I';
1580 }
1581 }
1582 }
1583
1584 /**************************/
1585 /* Slow Antenna Diversity */
1586 /**************************/
1587
1588 void ath_slow_ant_div_init(struct ath_antdiv *antdiv,
1589 struct ath_softc *sc,
1590 int32_t rssitrig)
1591 {
1592 int trig;
1593
1594 /* antdivf_rssitrig can range from 40 - 0xff */
1595 trig = (rssitrig > 0xff) ? 0xff : rssitrig;
1596 trig = (rssitrig < 40) ? 40 : rssitrig;
1597
1598 antdiv->antdiv_sc = sc;
1599 antdiv->antdivf_rssitrig = trig;
1600 }
1601
1602 void ath_slow_ant_div_start(struct ath_antdiv *antdiv,
1603 u8 num_antcfg,
1604 const u8 *bssid)
1605 {
1606 antdiv->antdiv_num_antcfg =
1607 num_antcfg < ATH_ANT_DIV_MAX_CFG ?
1608 num_antcfg : ATH_ANT_DIV_MAX_CFG;
1609 antdiv->antdiv_state = ATH_ANT_DIV_IDLE;
1610 antdiv->antdiv_curcfg = 0;
1611 antdiv->antdiv_bestcfg = 0;
1612 antdiv->antdiv_laststatetsf = 0;
1613
1614 memcpy(antdiv->antdiv_bssid, bssid, sizeof(antdiv->antdiv_bssid));
1615
1616 antdiv->antdiv_start = 1;
1617 }
1618
1619 void ath_slow_ant_div_stop(struct ath_antdiv *antdiv)
1620 {
1621 antdiv->antdiv_start = 0;
1622 }
1623
1624 static int32_t ath_find_max_val(int32_t *val,
1625 u8 num_val, u8 *max_index)
1626 {
1627 u32 MaxVal = *val++;
1628 u32 cur_index = 0;
1629
1630 *max_index = 0;
1631 while (++cur_index < num_val) {
1632 if (*val > MaxVal) {
1633 MaxVal = *val;
1634 *max_index = cur_index;
1635 }
1636
1637 val++;
1638 }
1639
1640 return MaxVal;
1641 }
1642
1643 void ath_slow_ant_div(struct ath_antdiv *antdiv,
1644 struct ieee80211_hdr *hdr,
1645 struct ath_rx_status *rx_stats)
1646 {
1647 struct ath_softc *sc = antdiv->antdiv_sc;
1648 struct ath_hal *ah = sc->sc_ah;
1649 u64 curtsf = 0;
1650 u8 bestcfg, curcfg = antdiv->antdiv_curcfg;
1651 __le16 fc = hdr->frame_control;
1652
1653 if (antdiv->antdiv_start && ieee80211_is_beacon(fc)
1654 && !compare_ether_addr(hdr->addr3, antdiv->antdiv_bssid)) {
1655 antdiv->antdiv_lastbrssi[curcfg] = rx_stats->rs_rssi;
1656 antdiv->antdiv_lastbtsf[curcfg] = ath9k_hw_gettsf64(sc->sc_ah);
1657 curtsf = antdiv->antdiv_lastbtsf[curcfg];
1658 } else {
1659 return;
1660 }
1661
1662 switch (antdiv->antdiv_state) {
1663 case ATH_ANT_DIV_IDLE:
1664 if ((antdiv->antdiv_lastbrssi[curcfg] <
1665 antdiv->antdivf_rssitrig)
1666 && ((curtsf - antdiv->antdiv_laststatetsf) >
1667 ATH_ANT_DIV_MIN_IDLE_US)) {
1668
1669 curcfg++;
1670 if (curcfg == antdiv->antdiv_num_antcfg)
1671 curcfg = 0;
1672
1673 if (!ath9k_hw_select_antconfig(ah, curcfg)) {
1674 antdiv->antdiv_bestcfg = antdiv->antdiv_curcfg;
1675 antdiv->antdiv_curcfg = curcfg;
1676 antdiv->antdiv_laststatetsf = curtsf;
1677 antdiv->antdiv_state = ATH_ANT_DIV_SCAN;
1678 }
1679 }
1680 break;
1681
1682 case ATH_ANT_DIV_SCAN:
1683 if ((curtsf - antdiv->antdiv_laststatetsf) <
1684 ATH_ANT_DIV_MIN_SCAN_US)
1685 break;
1686
1687 curcfg++;
1688 if (curcfg == antdiv->antdiv_num_antcfg)
1689 curcfg = 0;
1690
1691 if (curcfg == antdiv->antdiv_bestcfg) {
1692 ath_find_max_val(antdiv->antdiv_lastbrssi,
1693 antdiv->antdiv_num_antcfg, &bestcfg);
1694 if (!ath9k_hw_select_antconfig(ah, bestcfg)) {
1695 antdiv->antdiv_bestcfg = bestcfg;
1696 antdiv->antdiv_curcfg = bestcfg;
1697 antdiv->antdiv_laststatetsf = curtsf;
1698 antdiv->antdiv_state = ATH_ANT_DIV_IDLE;
1699 }
1700 } else {
1701 if (!ath9k_hw_select_antconfig(ah, curcfg)) {
1702 antdiv->antdiv_curcfg = curcfg;
1703 antdiv->antdiv_laststatetsf = curtsf;
1704 antdiv->antdiv_state = ATH_ANT_DIV_SCAN;
1705 }
1706 }
1707
1708 break;
1709 }
1710 }
1711
1712 /***********************/
1713 /* Descriptor Handling */
1714 /***********************/
1715
1716 /*
1717 * Set up DMA descriptors
1718 *
1719 * This function will allocate both the DMA descriptor structure, and the
1720 * buffers it contains. These are used to contain the descriptors used
1721 * by the system.
1722 */
1723
1724 int ath_descdma_setup(struct ath_softc *sc,
1725 struct ath_descdma *dd,
1726 struct list_head *head,
1727 const char *name,
1728 int nbuf,
1729 int ndesc)
1730 {
1731 #define DS2PHYS(_dd, _ds) \
1732 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
1733 #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
1734 #define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
1735
1736 struct ath_desc *ds;
1737 struct ath_buf *bf;
1738 int i, bsize, error;
1739
1740 DPRINTF(sc, ATH_DBG_CONFIG, "%s: %s DMA: %u buffers %u desc/buf\n",
1741 __func__, name, nbuf, ndesc);
1742
1743 /* ath_desc must be a multiple of DWORDs */
1744 if ((sizeof(struct ath_desc) % 4) != 0) {
1745 DPRINTF(sc, ATH_DBG_FATAL, "%s: ath_desc not DWORD aligned\n",
1746 __func__);
1747 ASSERT((sizeof(struct ath_desc) % 4) == 0);
1748 error = -ENOMEM;
1749 goto fail;
1750 }
1751
1752 dd->dd_name = name;
1753 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
1754
1755 /*
1756 * Need additional DMA memory because we can't use
1757 * descriptors that cross the 4K page boundary. Assume
1758 * one skipped descriptor per 4K page.
1759 */
1760 if (!(sc->sc_ah->ah_caps.hal4kbSplitTransSupport)) {
1761 u32 ndesc_skipped =
1762 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
1763 u32 dma_len;
1764
1765 while (ndesc_skipped) {
1766 dma_len = ndesc_skipped * sizeof(struct ath_desc);
1767 dd->dd_desc_len += dma_len;
1768
1769 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
1770 };
1771 }
1772
1773 /* allocate descriptors */
1774 dd->dd_desc = pci_alloc_consistent(sc->pdev,
1775 dd->dd_desc_len,
1776 &dd->dd_desc_paddr);
1777 if (dd->dd_desc == NULL) {
1778 error = -ENOMEM;
1779 goto fail;
1780 }
1781 ds = dd->dd_desc;
1782 DPRINTF(sc, ATH_DBG_CONFIG, "%s: %s DMA map: %p (%u) -> %llx (%u)\n",
1783 __func__, dd->dd_name, ds, (u32) dd->dd_desc_len,
1784 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
1785
1786 /* allocate buffers */
1787 bsize = sizeof(struct ath_buf) * nbuf;
1788 bf = kmalloc(bsize, GFP_KERNEL);
1789 if (bf == NULL) {
1790 error = -ENOMEM;
1791 goto fail2;
1792 }
1793 memzero(bf, bsize);
1794 dd->dd_bufptr = bf;
1795
1796 INIT_LIST_HEAD(head);
1797 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
1798 bf->bf_desc = ds;
1799 bf->bf_daddr = DS2PHYS(dd, ds);
1800
1801 if (!(sc->sc_ah->ah_caps.hal4kbSplitTransSupport)) {
1802 /*
1803 * Skip descriptor addresses which can cause 4KB
1804 * boundary crossing (addr + length) with a 32 dword
1805 * descriptor fetch.
1806 */
1807 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
1808 ASSERT((caddr_t) bf->bf_desc <
1809 ((caddr_t) dd->dd_desc +
1810 dd->dd_desc_len));
1811
1812 ds += ndesc;
1813 bf->bf_desc = ds;
1814 bf->bf_daddr = DS2PHYS(dd, ds);
1815 }
1816 }
1817 list_add_tail(&bf->list, head);
1818 }
1819 return 0;
1820 fail2:
1821 pci_free_consistent(sc->pdev,
1822 dd->dd_desc_len, dd->dd_desc, dd->dd_desc_paddr);
1823 fail:
1824 memzero(dd, sizeof(*dd));
1825 return error;
1826 #undef ATH_DESC_4KB_BOUND_CHECK
1827 #undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
1828 #undef DS2PHYS
1829 }
1830
1831 /*
1832 * Cleanup DMA descriptors
1833 *
1834 * This function will free the DMA block that was allocated for the descriptor
1835 * pool. Since this was allocated as one "chunk", it is freed in the same
1836 * manner.
1837 */
1838
1839 void ath_descdma_cleanup(struct ath_softc *sc,
1840 struct ath_descdma *dd,
1841 struct list_head *head)
1842 {
1843 /* Free memory associated with descriptors */
1844 pci_free_consistent(sc->pdev,
1845 dd->dd_desc_len, dd->dd_desc, dd->dd_desc_paddr);
1846
1847 INIT_LIST_HEAD(head);
1848 kfree(dd->dd_bufptr);
1849 memzero(dd, sizeof(*dd));
1850 }
1851
1852 /*************/
1853 /* Utilities */
1854 /*************/
1855
1856 void ath_internal_reset(struct ath_softc *sc)
1857 {
1858 ath_reset_start(sc, 0);
1859 ath_reset(sc);
1860 ath_reset_end(sc, 0);
1861 }
1862
1863 int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
1864 {
1865 int qnum;
1866
1867 switch (queue) {
1868 case 0:
1869 qnum = sc->sc_haltype2q[ATH9K_WME_AC_VO];
1870 break;
1871 case 1:
1872 qnum = sc->sc_haltype2q[ATH9K_WME_AC_VI];
1873 break;
1874 case 2:
1875 qnum = sc->sc_haltype2q[ATH9K_WME_AC_BE];
1876 break;
1877 case 3:
1878 qnum = sc->sc_haltype2q[ATH9K_WME_AC_BK];
1879 break;
1880 default:
1881 qnum = sc->sc_haltype2q[ATH9K_WME_AC_BE];
1882 break;
1883 }
1884
1885 return qnum;
1886 }
1887
1888 int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
1889 {
1890 int qnum;
1891
1892 switch (queue) {
1893 case ATH9K_WME_AC_VO:
1894 qnum = 0;
1895 break;
1896 case ATH9K_WME_AC_VI:
1897 qnum = 1;
1898 break;
1899 case ATH9K_WME_AC_BE:
1900 qnum = 2;
1901 break;
1902 case ATH9K_WME_AC_BK:
1903 qnum = 3;
1904 break;
1905 default:
1906 qnum = -1;
1907 break;
1908 }
1909
1910 return qnum;
1911 }
1912
1913
1914 /*
1915 * Expand time stamp to TSF
1916 *
1917 * Extend 15-bit time stamp from rx descriptor to
1918 * a full 64-bit TSF using the current h/w TSF.
1919 */
1920
1921 u64 ath_extend_tsf(struct ath_softc *sc, u32 rstamp)
1922 {
1923 u64 tsf;
1924
1925 tsf = ath9k_hw_gettsf64(sc->sc_ah);
1926 if ((tsf & 0x7fff) < rstamp)
1927 tsf -= 0x8000;
1928 return (tsf & ~0x7fff) | rstamp;
1929 }
1930
1931 /*
1932 * Set Default Antenna
1933 *
1934 * Call into the HAL to set the default antenna to use. Not really valid for
1935 * MIMO technology.
1936 */
1937
1938 void ath_setdefantenna(void *context, u32 antenna)
1939 {
1940 struct ath_softc *sc = (struct ath_softc *)context;
1941 struct ath_hal *ah = sc->sc_ah;
1942
1943 /* XXX block beacon interrupts */
1944 ath9k_hw_setantenna(ah, antenna);
1945 sc->sc_defant = antenna;
1946 sc->sc_rxotherant = 0;
1947 }
1948
1949 /*
1950 * Set Slot Time
1951 *
1952 * This will wake up the chip if required, and set the slot time for the
1953 * frame (maximum transmit time). Slot time is assumed to be already set
1954 * in the ATH object member sc_slottime
1955 */
1956
1957 void ath_setslottime(struct ath_softc *sc)
1958 {
1959 ath9k_hw_setslottime(sc->sc_ah, sc->sc_slottime);
1960 sc->sc_updateslot = OK;
1961 }
Linux kernel - Deliverables
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