2 * Copyright (c) 2008-2009 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #define AH_USE_EEPROM 0x1
23 #define AR5416_EEPROM_MAGIC 0x5aa5
25 #define AR5416_EEPROM_MAGIC 0xa55a
28 #define CTRY_DEBUG 0x1ff
29 #define CTRY_DEFAULT 0
31 #define AR_EEPROM_EEPCAP_COMPRESS_DIS 0x0001
32 #define AR_EEPROM_EEPCAP_AES_DIS 0x0002
33 #define AR_EEPROM_EEPCAP_FASTFRAME_DIS 0x0004
34 #define AR_EEPROM_EEPCAP_BURST_DIS 0x0008
35 #define AR_EEPROM_EEPCAP_MAXQCU 0x01F0
36 #define AR_EEPROM_EEPCAP_MAXQCU_S 4
37 #define AR_EEPROM_EEPCAP_HEAVY_CLIP_EN 0x0200
38 #define AR_EEPROM_EEPCAP_KC_ENTRIES 0xF000
39 #define AR_EEPROM_EEPCAP_KC_ENTRIES_S 12
41 #define AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND 0x0040
42 #define AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN 0x0080
43 #define AR_EEPROM_EEREGCAP_EN_KK_U2 0x0100
44 #define AR_EEPROM_EEREGCAP_EN_KK_MIDBAND 0x0200
45 #define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD 0x0400
46 #define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A 0x0800
48 #define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD_PRE4_0 0x4000
49 #define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A_PRE4_0 0x8000
51 #define AR5416_EEPROM_MAGIC_OFFSET 0x0
52 #define AR5416_EEPROM_S 2
53 #define AR5416_EEPROM_OFFSET 0x2000
54 #define AR5416_EEPROM_MAX 0xae0
56 #define AR5416_EEPROM_START_ADDR \
57 (AR_SREV_9100(ah)) ? 0x1fff1000 : 0x503f1200
59 #define SD_NO_CTL 0xE0
70 #define EXT_ADDITIVE (0x8000)
71 #define CTL_11A_EXT (CTL_11A | EXT_ADDITIVE)
72 #define CTL_11G_EXT (CTL_11G | EXT_ADDITIVE)
73 #define CTL_11B_EXT (CTL_11B | EXT_ADDITIVE)
75 #define SUB_NUM_CTL_MODES_AT_5G_40 2
76 #define SUB_NUM_CTL_MODES_AT_2G_40 3
78 #define INCREASE_MAXPOW_BY_TWO_CHAIN 6 /* 10*log10(2)*2 */
79 #define INCREASE_MAXPOW_BY_THREE_CHAIN 10 /* 10*log10(3)*2 */
82 * For AR9285 and later chipsets, the following bits are not being programmed
83 * in EEPROM and so need to be enabled always.
87 * Bit 2: en_fcc_dfs_ht40
89 * Bit 4: en_jap_dfs_ht40
91 #define AR9285_RDEXT_DEFAULT 0x1F
93 #define AR_EEPROM_MAC(i) (0x1d+(i))
94 #define ATH9K_POW_SM(_r, _s) (((_r) & 0x3f) << (_s))
95 #define FREQ2FBIN(x, y) ((y) ? ((x) - 2300) : (((x) - 4800) / 5))
96 #define ath9k_hw_use_flash(_ah) (!(_ah->ah_flags & AH_USE_EEPROM))
98 #define AR5416_VER_MASK (eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK)
99 #define OLC_FOR_AR9280_20_LATER (AR_SREV_9280_20_OR_LATER(ah) && \
100 ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
102 #define AR_EEPROM_RFSILENT_GPIO_SEL 0x001c
103 #define AR_EEPROM_RFSILENT_GPIO_SEL_S 2
104 #define AR_EEPROM_RFSILENT_POLARITY 0x0002
105 #define AR_EEPROM_RFSILENT_POLARITY_S 1
107 #define EEP_RFSILENT_ENABLED 0x0001
108 #define EEP_RFSILENT_ENABLED_S 0
109 #define EEP_RFSILENT_POLARITY 0x0002
110 #define EEP_RFSILENT_POLARITY_S 1
111 #define EEP_RFSILENT_GPIO_SEL 0x001c
112 #define EEP_RFSILENT_GPIO_SEL_S 2
114 #define AR5416_OPFLAGS_11A 0x01
115 #define AR5416_OPFLAGS_11G 0x02
116 #define AR5416_OPFLAGS_N_5G_HT40 0x04
117 #define AR5416_OPFLAGS_N_2G_HT40 0x08
118 #define AR5416_OPFLAGS_N_5G_HT20 0x10
119 #define AR5416_OPFLAGS_N_2G_HT20 0x20
121 #define AR5416_EEP_NO_BACK_VER 0x1
122 #define AR5416_EEP_VER 0xE
123 #define AR5416_EEP_VER_MINOR_MASK 0x0FFF
124 #define AR5416_EEP_MINOR_VER_2 0x2
125 #define AR5416_EEP_MINOR_VER_3 0x3
126 #define AR5416_EEP_MINOR_VER_7 0x7
127 #define AR5416_EEP_MINOR_VER_9 0x9
128 #define AR5416_EEP_MINOR_VER_16 0x10
129 #define AR5416_EEP_MINOR_VER_17 0x11
130 #define AR5416_EEP_MINOR_VER_19 0x13
131 #define AR5416_EEP_MINOR_VER_20 0x14
132 #define AR5416_EEP_MINOR_VER_22 0x16
134 #define AR5416_NUM_5G_CAL_PIERS 8
135 #define AR5416_NUM_2G_CAL_PIERS 4
136 #define AR5416_NUM_5G_20_TARGET_POWERS 8
137 #define AR5416_NUM_5G_40_TARGET_POWERS 8
138 #define AR5416_NUM_2G_CCK_TARGET_POWERS 3
139 #define AR5416_NUM_2G_20_TARGET_POWERS 4
140 #define AR5416_NUM_2G_40_TARGET_POWERS 4
141 #define AR5416_NUM_CTLS 24
142 #define AR5416_NUM_BAND_EDGES 8
143 #define AR5416_NUM_PD_GAINS 4
144 #define AR5416_PD_GAINS_IN_MASK 4
145 #define AR5416_PD_GAIN_ICEPTS 5
146 #define AR5416_EEPROM_MODAL_SPURS 5
147 #define AR5416_MAX_RATE_POWER 63
148 #define AR5416_NUM_PDADC_VALUES 128
149 #define AR5416_BCHAN_UNUSED 0xFF
150 #define AR5416_MAX_PWR_RANGE_IN_HALF_DB 64
151 #define AR5416_MAX_CHAINS 3
152 #define AR5416_PWR_TABLE_OFFSET -5
154 /* Rx gain type values */
155 #define AR5416_EEP_RXGAIN_23DB_BACKOFF 0
156 #define AR5416_EEP_RXGAIN_13DB_BACKOFF 1
157 #define AR5416_EEP_RXGAIN_ORIG 2
159 /* Tx gain type values */
160 #define AR5416_EEP_TXGAIN_ORIGINAL 0
161 #define AR5416_EEP_TXGAIN_HIGH_POWER 1
163 #define AR5416_EEP4K_START_LOC 64
164 #define AR5416_EEP4K_NUM_2G_CAL_PIERS 3
165 #define AR5416_EEP4K_NUM_2G_CCK_TARGET_POWERS 3
166 #define AR5416_EEP4K_NUM_2G_20_TARGET_POWERS 3
167 #define AR5416_EEP4K_NUM_2G_40_TARGET_POWERS 3
168 #define AR5416_EEP4K_NUM_CTLS 12
169 #define AR5416_EEP4K_NUM_BAND_EDGES 4
170 #define AR5416_EEP4K_NUM_PD_GAINS 2
171 #define AR5416_EEP4K_PD_GAINS_IN_MASK 4
172 #define AR5416_EEP4K_PD_GAIN_ICEPTS 5
173 #define AR5416_EEP4K_MAX_CHAINS 1
175 #define AR9280_TX_GAIN_TABLE_SIZE 22
204 rate6mb
, rate9mb
, rate12mb
, rate18mb
,
205 rate24mb
, rate36mb
, rate48mb
, rate54mb
,
206 rate1l
, rate2l
, rate2s
, rate5_5l
,
207 rate5_5s
, rate11l
, rate11s
, rateXr
,
208 rateHt20_0
, rateHt20_1
, rateHt20_2
, rateHt20_3
,
209 rateHt20_4
, rateHt20_5
, rateHt20_6
, rateHt20_7
,
210 rateHt40_0
, rateHt40_1
, rateHt40_2
, rateHt40_3
,
211 rateHt40_4
, rateHt40_5
, rateHt40_6
, rateHt40_7
,
212 rateDupCck
, rateDupOfdm
, rateExtCck
, rateExtOfdm
,
216 enum ath9k_hal_freq_band
{
217 ATH9K_HAL_FREQ_BAND_5GHZ
= 0,
218 ATH9K_HAL_FREQ_BAND_2GHZ
= 1
221 struct base_eep_header
{
232 u16 blueToothOptions
;
245 u8 power_table_offset
;
250 struct base_eep_header_4k
{
261 u16 blueToothOptions
;
275 struct modal_eep_header
{
276 u32 antCtrlChain
[AR5416_MAX_CHAINS
];
278 u8 antennaGainCh
[AR5416_MAX_CHAINS
];
280 u8 txRxAttenCh
[AR5416_MAX_CHAINS
];
281 u8 rxTxMarginCh
[AR5416_MAX_CHAINS
];
284 u8 xlnaGainCh
[AR5416_MAX_CHAINS
];
289 u8 noiseFloorThreshCh
[AR5416_MAX_CHAINS
];
292 u8 iqCalICh
[AR5416_MAX_CHAINS
];
293 u8 iqCalQCh
[AR5416_MAX_CHAINS
];
298 u8 pwrDecreaseFor2Chain
;
299 u8 pwrDecreaseFor3Chain
;
300 u8 txFrameToDataStart
;
302 u8 ht40PowerIncForPdadc
;
303 u8 bswAtten
[AR5416_MAX_CHAINS
];
304 u8 bswMargin
[AR5416_MAX_CHAINS
];
306 u8 xatten2Db
[AR5416_MAX_CHAINS
];
307 u8 xatten2Margin
[AR5416_MAX_CHAINS
];
313 femBandSelectUsed
:1, xlnabufin
:1, xlnaisel
:2, xlnabufmode
:1;
315 u16 xpaBiasLvlFreq
[3];
318 struct spur_chan spurChans
[AR5416_EEPROM_MODAL_SPURS
];
321 struct calDataPerFreqOpLoop
{
328 struct modal_eep_4k_header
{
329 u32 antCtrlChain
[AR5416_EEP4K_MAX_CHAINS
];
331 u8 antennaGainCh
[AR5416_EEP4K_MAX_CHAINS
];
333 u8 txRxAttenCh
[AR5416_EEP4K_MAX_CHAINS
];
334 u8 rxTxMarginCh
[AR5416_EEP4K_MAX_CHAINS
];
337 u8 xlnaGainCh
[AR5416_EEP4K_MAX_CHAINS
];
342 u8 noiseFloorThreshCh
[AR5416_EEP4K_MAX_CHAINS
];
345 u8 iqCalICh
[AR5416_EEP4K_MAX_CHAINS
];
346 u8 iqCalQCh
[AR5416_EEP4K_MAX_CHAINS
];
351 u8 txFrameToDataStart
;
353 u8 ht40PowerIncForPdadc
;
354 u8 bswAtten
[AR5416_EEP4K_MAX_CHAINS
];
355 u8 bswMargin
[AR5416_EEP4K_MAX_CHAINS
];
357 u8 xatten2Db
[AR5416_EEP4K_MAX_CHAINS
];
358 u8 xatten2Margin
[AR5416_EEP4K_MAX_CHAINS
];
366 struct spur_chan spurChans
[AR5416_EEPROM_MODAL_SPURS
];
370 struct cal_data_per_freq
{
371 u8 pwrPdg
[AR5416_NUM_PD_GAINS
][AR5416_PD_GAIN_ICEPTS
];
372 u8 vpdPdg
[AR5416_NUM_PD_GAINS
][AR5416_PD_GAIN_ICEPTS
];
375 struct cal_data_per_freq_4k
{
376 u8 pwrPdg
[AR5416_EEP4K_NUM_PD_GAINS
][AR5416_EEP4K_PD_GAIN_ICEPTS
];
377 u8 vpdPdg
[AR5416_EEP4K_NUM_PD_GAINS
][AR5416_EEP4K_PD_GAIN_ICEPTS
];
380 struct cal_target_power_leg
{
385 struct cal_target_power_ht
{
391 #ifdef __BIG_ENDIAN_BITFIELD
392 struct cal_ctl_edges
{
397 struct cal_ctl_edges
{
403 struct cal_ctl_data
{
405 ctlEdges
[AR5416_MAX_CHAINS
][AR5416_NUM_BAND_EDGES
];
408 struct cal_ctl_data_4k
{
410 ctlEdges
[AR5416_EEP4K_MAX_CHAINS
][AR5416_EEP4K_NUM_BAND_EDGES
];
413 struct ar5416_eeprom_def
{
414 struct base_eep_header baseEepHeader
;
416 struct modal_eep_header modalHeader
[2];
417 u8 calFreqPier5G
[AR5416_NUM_5G_CAL_PIERS
];
418 u8 calFreqPier2G
[AR5416_NUM_2G_CAL_PIERS
];
419 struct cal_data_per_freq
420 calPierData5G
[AR5416_MAX_CHAINS
][AR5416_NUM_5G_CAL_PIERS
];
421 struct cal_data_per_freq
422 calPierData2G
[AR5416_MAX_CHAINS
][AR5416_NUM_2G_CAL_PIERS
];
423 struct cal_target_power_leg
424 calTargetPower5G
[AR5416_NUM_5G_20_TARGET_POWERS
];
425 struct cal_target_power_ht
426 calTargetPower5GHT20
[AR5416_NUM_5G_20_TARGET_POWERS
];
427 struct cal_target_power_ht
428 calTargetPower5GHT40
[AR5416_NUM_5G_40_TARGET_POWERS
];
429 struct cal_target_power_leg
430 calTargetPowerCck
[AR5416_NUM_2G_CCK_TARGET_POWERS
];
431 struct cal_target_power_leg
432 calTargetPower2G
[AR5416_NUM_2G_20_TARGET_POWERS
];
433 struct cal_target_power_ht
434 calTargetPower2GHT20
[AR5416_NUM_2G_20_TARGET_POWERS
];
435 struct cal_target_power_ht
436 calTargetPower2GHT40
[AR5416_NUM_2G_40_TARGET_POWERS
];
437 u8 ctlIndex
[AR5416_NUM_CTLS
];
438 struct cal_ctl_data ctlData
[AR5416_NUM_CTLS
];
442 struct ar5416_eeprom_4k
{
443 struct base_eep_header_4k baseEepHeader
;
445 struct modal_eep_4k_header modalHeader
;
446 u8 calFreqPier2G
[AR5416_EEP4K_NUM_2G_CAL_PIERS
];
447 struct cal_data_per_freq_4k
448 calPierData2G
[AR5416_EEP4K_MAX_CHAINS
][AR5416_EEP4K_NUM_2G_CAL_PIERS
];
449 struct cal_target_power_leg
450 calTargetPowerCck
[AR5416_EEP4K_NUM_2G_CCK_TARGET_POWERS
];
451 struct cal_target_power_leg
452 calTargetPower2G
[AR5416_EEP4K_NUM_2G_20_TARGET_POWERS
];
453 struct cal_target_power_ht
454 calTargetPower2GHT20
[AR5416_EEP4K_NUM_2G_20_TARGET_POWERS
];
455 struct cal_target_power_ht
456 calTargetPower2GHT40
[AR5416_EEP4K_NUM_2G_40_TARGET_POWERS
];
457 u8 ctlIndex
[AR5416_EEP4K_NUM_CTLS
];
458 struct cal_ctl_data_4k ctlData
[AR5416_EEP4K_NUM_CTLS
];
462 enum reg_ext_bitmap
{
463 REG_EXT_JAPAN_MIDBAND
= 1,
464 REG_EXT_FCC_DFS_HT40
= 2,
465 REG_EXT_JAPAN_NONDFS_HT40
= 3,
466 REG_EXT_JAPAN_DFS_HT40
= 4
469 struct ath9k_country_entry
{
479 EEP_MAP_DEFAULT
= 0x0,
485 int (*check_eeprom
)(struct ath_hw
*hw
);
486 u32 (*get_eeprom
)(struct ath_hw
*hw
, enum eeprom_param param
);
487 bool (*fill_eeprom
)(struct ath_hw
*hw
);
488 int (*get_eeprom_ver
)(struct ath_hw
*hw
);
489 int (*get_eeprom_rev
)(struct ath_hw
*hw
);
490 u8 (*get_num_ant_config
)(struct ath_hw
*hw
, enum ieee80211_band band
);
491 u16 (*get_eeprom_antenna_cfg
)(struct ath_hw
*hw
,
492 struct ath9k_channel
*chan
);
493 void (*set_board_values
)(struct ath_hw
*hw
, struct ath9k_channel
*chan
);
494 void (*set_addac
)(struct ath_hw
*hw
, struct ath9k_channel
*chan
);
495 int (*set_txpower
)(struct ath_hw
*hw
, struct ath9k_channel
*chan
,
496 u16 cfgCtl
, u8 twiceAntennaReduction
,
497 u8 twiceMaxRegulatoryPower
, u8 powerLimit
);
498 u16 (*get_spur_channel
)(struct ath_hw
*ah
, u16 i
, bool is2GHz
);
501 #define ar5416_get_ntxchains(_txchainmask) \
502 (((_txchainmask >> 2) & 1) + \
503 ((_txchainmask >> 1) & 1) + (_txchainmask & 1))
505 int ath9k_hw_eeprom_attach(struct ath_hw
*ah
);
507 #endif /* EEPROM_H */