2 * Copyright (c) 2008 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include <linux/if_ether.h>
21 #include <linux/delay.h>
65 #define AR5416DESC(_ds) ((struct ar5416_desc *)(_ds))
66 #define AR5416DESC_CONST(_ds) ((const struct ar5416_desc *)(_ds))
68 #define ds_ctl2 u.tx.ctl2
69 #define ds_ctl3 u.tx.ctl3
70 #define ds_ctl4 u.tx.ctl4
71 #define ds_ctl5 u.tx.ctl5
72 #define ds_ctl6 u.tx.ctl6
73 #define ds_ctl7 u.tx.ctl7
74 #define ds_ctl8 u.tx.ctl8
75 #define ds_ctl9 u.tx.ctl9
76 #define ds_ctl10 u.tx.ctl10
77 #define ds_ctl11 u.tx.ctl11
79 #define ds_txstatus0 u.tx.status0
80 #define ds_txstatus1 u.tx.status1
81 #define ds_txstatus2 u.tx.status2
82 #define ds_txstatus3 u.tx.status3
83 #define ds_txstatus4 u.tx.status4
84 #define ds_txstatus5 u.tx.status5
85 #define ds_txstatus6 u.tx.status6
86 #define ds_txstatus7 u.tx.status7
87 #define ds_txstatus8 u.tx.status8
88 #define ds_txstatus9 u.tx.status9
90 #define ds_rxstatus0 u.rx.status0
91 #define ds_rxstatus1 u.rx.status1
92 #define ds_rxstatus2 u.rx.status2
93 #define ds_rxstatus3 u.rx.status3
94 #define ds_rxstatus4 u.rx.status4
95 #define ds_rxstatus5 u.rx.status5
96 #define ds_rxstatus6 u.rx.status6
97 #define ds_rxstatus7 u.rx.status7
98 #define ds_rxstatus8 u.rx.status8
100 #define AR_FrameLen 0x00000fff
101 #define AR_VirtMoreFrag 0x00001000
102 #define AR_TxCtlRsvd00 0x0000e000
103 #define AR_XmitPower 0x003f0000
104 #define AR_XmitPower_S 16
105 #define AR_RTSEnable 0x00400000
106 #define AR_VEOL 0x00800000
107 #define AR_ClrDestMask 0x01000000
108 #define AR_TxCtlRsvd01 0x1e000000
109 #define AR_TxIntrReq 0x20000000
110 #define AR_DestIdxValid 0x40000000
111 #define AR_CTSEnable 0x80000000
113 #define AR_BufLen 0x00000fff
114 #define AR_TxMore 0x00001000
115 #define AR_DestIdx 0x000fe000
116 #define AR_DestIdx_S 13
117 #define AR_FrameType 0x00f00000
118 #define AR_FrameType_S 20
119 #define AR_NoAck 0x01000000
120 #define AR_InsertTS 0x02000000
121 #define AR_CorruptFCS 0x04000000
122 #define AR_ExtOnly 0x08000000
123 #define AR_ExtAndCtl 0x10000000
124 #define AR_MoreAggr 0x20000000
125 #define AR_IsAggr 0x40000000
127 #define AR_BurstDur 0x00007fff
128 #define AR_BurstDur_S 0
129 #define AR_DurUpdateEna 0x00008000
130 #define AR_XmitDataTries0 0x000f0000
131 #define AR_XmitDataTries0_S 16
132 #define AR_XmitDataTries1 0x00f00000
133 #define AR_XmitDataTries1_S 20
134 #define AR_XmitDataTries2 0x0f000000
135 #define AR_XmitDataTries2_S 24
136 #define AR_XmitDataTries3 0xf0000000
137 #define AR_XmitDataTries3_S 28
139 #define AR_XmitRate0 0x000000ff
140 #define AR_XmitRate0_S 0
141 #define AR_XmitRate1 0x0000ff00
142 #define AR_XmitRate1_S 8
143 #define AR_XmitRate2 0x00ff0000
144 #define AR_XmitRate2_S 16
145 #define AR_XmitRate3 0xff000000
146 #define AR_XmitRate3_S 24
148 #define AR_PacketDur0 0x00007fff
149 #define AR_PacketDur0_S 0
150 #define AR_RTSCTSQual0 0x00008000
151 #define AR_PacketDur1 0x7fff0000
152 #define AR_PacketDur1_S 16
153 #define AR_RTSCTSQual1 0x80000000
155 #define AR_PacketDur2 0x00007fff
156 #define AR_PacketDur2_S 0
157 #define AR_RTSCTSQual2 0x00008000
158 #define AR_PacketDur3 0x7fff0000
159 #define AR_PacketDur3_S 16
160 #define AR_RTSCTSQual3 0x80000000
162 #define AR_AggrLen 0x0000ffff
163 #define AR_AggrLen_S 0
164 #define AR_TxCtlRsvd60 0x00030000
165 #define AR_PadDelim 0x03fc0000
166 #define AR_PadDelim_S 18
167 #define AR_EncrType 0x0c000000
168 #define AR_EncrType_S 26
169 #define AR_TxCtlRsvd61 0xf0000000
171 #define AR_2040_0 0x00000001
172 #define AR_GI0 0x00000002
173 #define AR_ChainSel0 0x0000001c
174 #define AR_ChainSel0_S 2
175 #define AR_2040_1 0x00000020
176 #define AR_GI1 0x00000040
177 #define AR_ChainSel1 0x00000380
178 #define AR_ChainSel1_S 7
179 #define AR_2040_2 0x00000400
180 #define AR_GI2 0x00000800
181 #define AR_ChainSel2 0x00007000
182 #define AR_ChainSel2_S 12
183 #define AR_2040_3 0x00008000
184 #define AR_GI3 0x00010000
185 #define AR_ChainSel3 0x000e0000
186 #define AR_ChainSel3_S 17
187 #define AR_RTSCTSRate 0x0ff00000
188 #define AR_RTSCTSRate_S 20
189 #define AR_TxCtlRsvd70 0xf0000000
191 #define AR_TxRSSIAnt00 0x000000ff
192 #define AR_TxRSSIAnt00_S 0
193 #define AR_TxRSSIAnt01 0x0000ff00
194 #define AR_TxRSSIAnt01_S 8
195 #define AR_TxRSSIAnt02 0x00ff0000
196 #define AR_TxRSSIAnt02_S 16
197 #define AR_TxStatusRsvd00 0x3f000000
198 #define AR_TxBaStatus 0x40000000
199 #define AR_TxStatusRsvd01 0x80000000
201 #define AR_FrmXmitOK 0x00000001
202 #define AR_ExcessiveRetries 0x00000002
203 #define AR_FIFOUnderrun 0x00000004
204 #define AR_Filtered 0x00000008
205 #define AR_RTSFailCnt 0x000000f0
206 #define AR_RTSFailCnt_S 4
207 #define AR_DataFailCnt 0x00000f00
208 #define AR_DataFailCnt_S 8
209 #define AR_VirtRetryCnt 0x0000f000
210 #define AR_VirtRetryCnt_S 12
211 #define AR_TxDelimUnderrun 0x00010000
212 #define AR_TxDataUnderrun 0x00020000
213 #define AR_DescCfgErr 0x00040000
214 #define AR_TxTimerExpired 0x00080000
215 #define AR_TxStatusRsvd10 0xfff00000
217 #define AR_SendTimestamp ds_txstatus2
218 #define AR_BaBitmapLow ds_txstatus3
219 #define AR_BaBitmapHigh ds_txstatus4
221 #define AR_TxRSSIAnt10 0x000000ff
222 #define AR_TxRSSIAnt10_S 0
223 #define AR_TxRSSIAnt11 0x0000ff00
224 #define AR_TxRSSIAnt11_S 8
225 #define AR_TxRSSIAnt12 0x00ff0000
226 #define AR_TxRSSIAnt12_S 16
227 #define AR_TxRSSICombined 0xff000000
228 #define AR_TxRSSICombined_S 24
230 #define AR_TxEVM0 ds_txstatus5
231 #define AR_TxEVM1 ds_txstatus6
232 #define AR_TxEVM2 ds_txstatus7
234 #define AR_TxDone 0x00000001
235 #define AR_SeqNum 0x00001ffe
236 #define AR_SeqNum_S 1
237 #define AR_TxStatusRsvd80 0x0001e000
238 #define AR_TxOpExceeded 0x00020000
239 #define AR_TxStatusRsvd81 0x001c0000
240 #define AR_FinalTxIdx 0x00600000
241 #define AR_FinalTxIdx_S 21
242 #define AR_TxStatusRsvd82 0x01800000
243 #define AR_PowerMgmt 0x02000000
244 #define AR_TxStatusRsvd83 0xfc000000
246 #define AR_RxCTLRsvd00 0xffffffff
248 #define AR_BufLen 0x00000fff
249 #define AR_RxCtlRsvd00 0x00001000
250 #define AR_RxIntrReq 0x00002000
251 #define AR_RxCtlRsvd01 0xffffc000
253 #define AR_RxRSSIAnt00 0x000000ff
254 #define AR_RxRSSIAnt00_S 0
255 #define AR_RxRSSIAnt01 0x0000ff00
256 #define AR_RxRSSIAnt01_S 8
257 #define AR_RxRSSIAnt02 0x00ff0000
258 #define AR_RxRSSIAnt02_S 16
259 #define AR_RxRate 0xff000000
260 #define AR_RxRate_S 24
261 #define AR_RxStatusRsvd00 0xff000000
263 #define AR_DataLen 0x00000fff
264 #define AR_RxMore 0x00001000
265 #define AR_NumDelim 0x003fc000
266 #define AR_NumDelim_S 14
267 #define AR_RxStatusRsvd10 0xff800000
269 #define AR_RcvTimestamp ds_rxstatus2
271 #define AR_GI 0x00000001
272 #define AR_2040 0x00000002
273 #define AR_Parallel40 0x00000004
274 #define AR_Parallel40_S 2
275 #define AR_RxStatusRsvd30 0x000000f8
276 #define AR_RxAntenna 0xffffff00
277 #define AR_RxAntenna_S 8
279 #define AR_RxRSSIAnt10 0x000000ff
280 #define AR_RxRSSIAnt10_S 0
281 #define AR_RxRSSIAnt11 0x0000ff00
282 #define AR_RxRSSIAnt11_S 8
283 #define AR_RxRSSIAnt12 0x00ff0000
284 #define AR_RxRSSIAnt12_S 16
285 #define AR_RxRSSICombined 0xff000000
286 #define AR_RxRSSICombined_S 24
288 #define AR_RxEVM0 ds_rxstatus4
289 #define AR_RxEVM1 ds_rxstatus5
290 #define AR_RxEVM2 ds_rxstatus6
292 #define AR_RxDone 0x00000001
293 #define AR_RxFrameOK 0x00000002
294 #define AR_CRCErr 0x00000004
295 #define AR_DecryptCRCErr 0x00000008
296 #define AR_PHYErr 0x00000010
297 #define AR_MichaelErr 0x00000020
298 #define AR_PreDelimCRCErr 0x00000040
299 #define AR_RxStatusRsvd70 0x00000080
300 #define AR_RxKeyIdxValid 0x00000100
301 #define AR_KeyIdx 0x0000fe00
302 #define AR_KeyIdx_S 9
303 #define AR_PHYErrCode 0x0000ff00
304 #define AR_PHYErrCode_S 8
305 #define AR_RxMoreAggr 0x00010000
306 #define AR_RxAggr 0x00020000
307 #define AR_PostDelimCRCErr 0x00040000
308 #define AR_RxStatusRsvd71 0x3ff80000
309 #define AR_DecryptBusyErr 0x40000000
310 #define AR_KeyMiss 0x80000000
312 #define AR5416_MAGIC 0x19641014
314 #define RXSTATUS_RATE(ah, ads) (AR_SREV_5416_V20_OR_LATER(ah) ? \
315 MS(ads->ds_rxstatus0, AR_RxRate) : \
316 (ads->ds_rxstatus3 >> 2) & 0xFF)
318 #define set11nTries(_series, _index) \
319 (SM((_series)[_index].Tries, AR_XmitDataTries##_index))
321 #define set11nRate(_series, _index) \
322 (SM((_series)[_index].Rate, AR_XmitRate##_index))
324 #define set11nPktDurRTSCTS(_series, _index) \
325 (SM((_series)[_index].PktDuration, AR_PacketDur##_index) | \
326 ((_series)[_index].RateFlags & ATH9K_RATESERIES_RTS_CTS ? \
327 AR_RTSCTSQual##_index : 0))
329 #define set11nRateFlags(_series, _index) \
330 (((_series)[_index].RateFlags & ATH9K_RATESERIES_2040 ? \
331 AR_2040_##_index : 0) \
332 |((_series)[_index].RateFlags & ATH9K_RATESERIES_HALFGI ? \
334 |SM((_series)[_index].ChSel, AR_ChainSel##_index))
336 #define AR_SREV_9100(ah) ((ah->ah_macVersion) == AR_SREV_VERSION_9100)
338 #define INIT_CONFIG_STATUS 0x00000000
339 #define INIT_RSSI_THR 0x00000700
340 #define INIT_BCON_CNTRL_REG 0x00000000
342 #define MIN_TX_FIFO_THRESHOLD 0x1
343 #define MAX_TX_FIFO_THRESHOLD ((4096 / 64) - 1)
344 #define INIT_TX_FIFO_THRESHOLD MIN_TX_FIFO_THRESHOLD
346 struct ar5416AniState
{
347 struct ath9k_channel c
;
348 u8 noiseImmunityLevel
;
349 u8 spurImmunityLevel
;
351 u8 ofdmWeakSigDetectOff
;
352 u8 cckWeakSigThreshold
;
369 int16_t ofdmErrRssi
[2];
370 int16_t cckErrRssi
[2];
373 #define HAL_PROCESS_ANI 0x00000001
375 ((AH5416(ah)->ah_procPhyErr & HAL_PROCESS_ANI))
381 u32 ast_ani_spurdown
;
387 u32 ast_ani_stepdown
;
388 u32 ast_ani_ofdmerrs
;
393 struct ath9k_mib_stats ast_mibstats
;
394 struct ath9k_node_stats ast_nodestats
;
397 #define AR5416_OPFLAGS_11A 0x01
398 #define AR5416_OPFLAGS_11G 0x02
399 #define AR5416_OPFLAGS_N_5G_HT40 0x04
400 #define AR5416_OPFLAGS_N_2G_HT40 0x08
401 #define AR5416_OPFLAGS_N_5G_HT20 0x10
402 #define AR5416_OPFLAGS_N_2G_HT20 0x20
404 #define EEP_RFSILENT_ENABLED 0x0001
405 #define EEP_RFSILENT_ENABLED_S 0
406 #define EEP_RFSILENT_POLARITY 0x0002
407 #define EEP_RFSILENT_POLARITY_S 1
408 #define EEP_RFSILENT_GPIO_SEL 0x001c
409 #define EEP_RFSILENT_GPIO_SEL_S 2
411 #define AR5416_EEP_NO_BACK_VER 0x1
412 #define AR5416_EEP_VER 0xE
413 #define AR5416_EEP_VER_MINOR_MASK 0x0FFF
414 #define AR5416_EEP_MINOR_VER_2 0x2
415 #define AR5416_EEP_MINOR_VER_3 0x3
416 #define AR5416_EEP_MINOR_VER_7 0x7
417 #define AR5416_EEP_MINOR_VER_9 0x9
418 #define AR5416_EEP_MINOR_VER_16 0x10
419 #define AR5416_EEP_MINOR_VER_17 0x11
420 #define AR5416_EEP_MINOR_VER_19 0x13
422 #define AR5416_NUM_5G_CAL_PIERS 8
423 #define AR5416_NUM_2G_CAL_PIERS 4
424 #define AR5416_NUM_5G_20_TARGET_POWERS 8
425 #define AR5416_NUM_5G_40_TARGET_POWERS 8
426 #define AR5416_NUM_2G_CCK_TARGET_POWERS 3
427 #define AR5416_NUM_2G_20_TARGET_POWERS 4
428 #define AR5416_NUM_2G_40_TARGET_POWERS 4
429 #define AR5416_NUM_CTLS 24
430 #define AR5416_NUM_BAND_EDGES 8
431 #define AR5416_NUM_PD_GAINS 4
432 #define AR5416_PD_GAINS_IN_MASK 4
433 #define AR5416_PD_GAIN_ICEPTS 5
434 #define AR5416_EEPROM_MODAL_SPURS 5
435 #define AR5416_MAX_RATE_POWER 63
436 #define AR5416_NUM_PDADC_VALUES 128
437 #define AR5416_BCHAN_UNUSED 0xFF
438 #define AR5416_MAX_PWR_RANGE_IN_HALF_DB 64
439 #define AR5416_MAX_CHAINS 3
440 #define AR5416_PWR_TABLE_OFFSET -5
442 /* Rx gain type values */
443 #define AR5416_EEP_RXGAIN_23DB_BACKOFF 0
444 #define AR5416_EEP_RXGAIN_13DB_BACKOFF 1
445 #define AR5416_EEP_RXGAIN_ORIG 2
447 /* Tx gain type values */
448 #define AR5416_EEP_TXGAIN_ORIGINAL 0
449 #define AR5416_EEP_TXGAIN_HIGH_POWER 1
451 #define AR5416_EEP4K_START_LOC 64
452 #define AR5416_EEP4K_NUM_2G_CAL_PIERS 3
453 #define AR5416_EEP4K_NUM_2G_CCK_TARGET_POWERS 3
454 #define AR5416_EEP4K_NUM_2G_20_TARGET_POWERS 3
455 #define AR5416_EEP4K_NUM_2G_40_TARGET_POWERS 3
456 #define AR5416_EEP4K_NUM_CTLS 12
457 #define AR5416_EEP4K_NUM_BAND_EDGES 4
458 #define AR5416_EEP4K_NUM_PD_GAINS 2
459 #define AR5416_EEP4K_PD_GAINS_IN_MASK 4
460 #define AR5416_EEP4K_PD_GAIN_ICEPTS 5
461 #define AR5416_EEP4K_MAX_CHAINS 1
486 rate6mb
, rate9mb
, rate12mb
, rate18mb
,
487 rate24mb
, rate36mb
, rate48mb
, rate54mb
,
488 rate1l
, rate2l
, rate2s
, rate5_5l
,
489 rate5_5s
, rate11l
, rate11s
, rateXr
,
490 rateHt20_0
, rateHt20_1
, rateHt20_2
, rateHt20_3
,
491 rateHt20_4
, rateHt20_5
, rateHt20_6
, rateHt20_7
,
492 rateHt40_0
, rateHt40_1
, rateHt40_2
, rateHt40_3
,
493 rateHt40_4
, rateHt40_5
, rateHt40_6
, rateHt40_7
,
494 rateDupCck
, rateDupOfdm
, rateExtCck
, rateExtOfdm
,
498 enum ath9k_hal_freq_band
{
499 ATH9K_HAL_FREQ_BAND_5GHZ
= 0,
500 ATH9K_HAL_FREQ_BAND_2GHZ
= 1
503 struct base_eep_header
{
514 u16 blueToothOptions
;
526 struct base_eep_header_4k
{
537 u16 blueToothOptions
;
551 struct modal_eep_header
{
552 u32 antCtrlChain
[AR5416_MAX_CHAINS
];
554 u8 antennaGainCh
[AR5416_MAX_CHAINS
];
556 u8 txRxAttenCh
[AR5416_MAX_CHAINS
];
557 u8 rxTxMarginCh
[AR5416_MAX_CHAINS
];
560 u8 xlnaGainCh
[AR5416_MAX_CHAINS
];
565 u8 noiseFloorThreshCh
[AR5416_MAX_CHAINS
];
568 u8 iqCalICh
[AR5416_MAX_CHAINS
];
569 u8 iqCalQCh
[AR5416_MAX_CHAINS
];
574 u8 pwrDecreaseFor2Chain
;
575 u8 pwrDecreaseFor3Chain
;
576 u8 txFrameToDataStart
;
578 u8 ht40PowerIncForPdadc
;
579 u8 bswAtten
[AR5416_MAX_CHAINS
];
580 u8 bswMargin
[AR5416_MAX_CHAINS
];
582 u8 xatten2Db
[AR5416_MAX_CHAINS
];
583 u8 xatten2Margin
[AR5416_MAX_CHAINS
];
589 femBandSelectUsed
:1, xlnabufin
:1, xlnaisel
:2, xlnabufmode
:1;
590 u8 futureModalar9280
;
591 u16 xpaBiasLvlFreq
[3];
594 struct spur_chan spurChans
[AR5416_EEPROM_MODAL_SPURS
];
597 struct modal_eep_4k_header
{
598 u32 antCtrlChain
[AR5416_EEP4K_MAX_CHAINS
];
600 u8 antennaGainCh
[AR5416_EEP4K_MAX_CHAINS
];
602 u8 txRxAttenCh
[AR5416_EEP4K_MAX_CHAINS
];
603 u8 rxTxMarginCh
[AR5416_EEP4K_MAX_CHAINS
];
606 u8 xlnaGainCh
[AR5416_EEP4K_MAX_CHAINS
];
611 u8 noiseFloorThreshCh
[AR5416_EEP4K_MAX_CHAINS
];
614 u8 iqCalICh
[AR5416_EEP4K_MAX_CHAINS
];
615 u8 iqCalQCh
[AR5416_EEP4K_MAX_CHAINS
];
620 u8 txFrameToDataStart
;
622 u8 ht40PowerIncForPdadc
;
623 u8 bswAtten
[AR5416_EEP4K_MAX_CHAINS
];
624 u8 bswMargin
[AR5416_EEP4K_MAX_CHAINS
];
626 u8 xatten2Db
[AR5416_EEP4K_MAX_CHAINS
];
627 u8 xatten2Margin
[AR5416_EEP4K_MAX_CHAINS
];
635 struct spur_chan spurChans
[AR5416_EEPROM_MODAL_SPURS
];
639 struct cal_data_per_freq
{
640 u8 pwrPdg
[AR5416_NUM_PD_GAINS
][AR5416_PD_GAIN_ICEPTS
];
641 u8 vpdPdg
[AR5416_NUM_PD_GAINS
][AR5416_PD_GAIN_ICEPTS
];
644 struct cal_data_per_freq_4k
{
645 u8 pwrPdg
[AR5416_EEP4K_NUM_PD_GAINS
][AR5416_EEP4K_PD_GAIN_ICEPTS
];
646 u8 vpdPdg
[AR5416_EEP4K_NUM_PD_GAINS
][AR5416_EEP4K_PD_GAIN_ICEPTS
];
649 struct cal_target_power_leg
{
654 struct cal_target_power_ht
{
660 #ifdef __BIG_ENDIAN_BITFIELD
661 struct cal_ctl_edges
{
666 struct cal_ctl_edges
{
672 struct cal_ctl_data
{
674 ctlEdges
[AR5416_MAX_CHAINS
][AR5416_NUM_BAND_EDGES
];
677 struct cal_ctl_data_4k
{
679 ctlEdges
[AR5416_EEP4K_MAX_CHAINS
][AR5416_EEP4K_NUM_BAND_EDGES
];
682 struct ar5416_eeprom_def
{
683 struct base_eep_header baseEepHeader
;
685 struct modal_eep_header modalHeader
[2];
686 u8 calFreqPier5G
[AR5416_NUM_5G_CAL_PIERS
];
687 u8 calFreqPier2G
[AR5416_NUM_2G_CAL_PIERS
];
688 struct cal_data_per_freq
689 calPierData5G
[AR5416_MAX_CHAINS
][AR5416_NUM_5G_CAL_PIERS
];
690 struct cal_data_per_freq
691 calPierData2G
[AR5416_MAX_CHAINS
][AR5416_NUM_2G_CAL_PIERS
];
692 struct cal_target_power_leg
693 calTargetPower5G
[AR5416_NUM_5G_20_TARGET_POWERS
];
694 struct cal_target_power_ht
695 calTargetPower5GHT20
[AR5416_NUM_5G_20_TARGET_POWERS
];
696 struct cal_target_power_ht
697 calTargetPower5GHT40
[AR5416_NUM_5G_40_TARGET_POWERS
];
698 struct cal_target_power_leg
699 calTargetPowerCck
[AR5416_NUM_2G_CCK_TARGET_POWERS
];
700 struct cal_target_power_leg
701 calTargetPower2G
[AR5416_NUM_2G_20_TARGET_POWERS
];
702 struct cal_target_power_ht
703 calTargetPower2GHT20
[AR5416_NUM_2G_20_TARGET_POWERS
];
704 struct cal_target_power_ht
705 calTargetPower2GHT40
[AR5416_NUM_2G_40_TARGET_POWERS
];
706 u8 ctlIndex
[AR5416_NUM_CTLS
];
707 struct cal_ctl_data ctlData
[AR5416_NUM_CTLS
];
711 struct ar5416_eeprom_4k
{
712 struct base_eep_header_4k baseEepHeader
;
714 struct modal_eep_4k_header modalHeader
;
715 u8 calFreqPier2G
[AR5416_EEP4K_NUM_2G_CAL_PIERS
];
716 struct cal_data_per_freq_4k
717 calPierData2G
[AR5416_EEP4K_MAX_CHAINS
][AR5416_EEP4K_NUM_2G_CAL_PIERS
];
718 struct cal_target_power_leg
719 calTargetPowerCck
[AR5416_EEP4K_NUM_2G_CCK_TARGET_POWERS
];
720 struct cal_target_power_leg
721 calTargetPower2G
[AR5416_EEP4K_NUM_2G_20_TARGET_POWERS
];
722 struct cal_target_power_ht
723 calTargetPower2GHT20
[AR5416_EEP4K_NUM_2G_20_TARGET_POWERS
];
724 struct cal_target_power_ht
725 calTargetPower2GHT40
[AR5416_EEP4K_NUM_2G_40_TARGET_POWERS
];
726 u8 ctlIndex
[AR5416_EEP4K_NUM_CTLS
];
727 struct cal_ctl_data_4k ctlData
[AR5416_EEP4K_NUM_CTLS
];
731 struct ar5416IniArray
{
737 #define INIT_INI_ARRAY(iniarray, array, rows, columns) do { \
738 (iniarray)->ia_array = (u32 *)(array); \
739 (iniarray)->ia_rows = (rows); \
740 (iniarray)->ia_columns = (columns); \
743 #define INI_RA(iniarray, row, column) \
744 (((iniarray)->ia_array)[(row) * ((iniarray)->ia_columns) + (column)])
746 #define INIT_CAL(_perCal) do { \
747 (_perCal)->calState = CAL_WAITING; \
748 (_perCal)->calNext = NULL; \
751 #define INSERT_CAL(_ahp, _perCal) \
753 if ((_ahp)->ah_cal_list_last == NULL) { \
754 (_ahp)->ah_cal_list = \
755 (_ahp)->ah_cal_list_last = (_perCal); \
756 ((_ahp)->ah_cal_list_last)->calNext = (_perCal); \
758 ((_ahp)->ah_cal_list_last)->calNext = (_perCal); \
759 (_ahp)->ah_cal_list_last = (_perCal); \
760 (_perCal)->calNext = (_ahp)->ah_cal_list; \
765 ADC_DC_INIT_CAL
= 0x1,
768 IQ_MISMATCH_CAL
= 0x8
778 #define MIN_CAL_SAMPLES 1
779 #define MAX_CAL_SAMPLES 64
780 #define INIT_LOG_COUNT 5
781 #define PER_MIN_LOG_COUNT 2
782 #define PER_MAX_LOG_COUNT 10
784 struct hal_percal_data
{
785 enum hal_cal_types calType
;
788 void (*calCollect
) (struct ath_hal
*);
789 void (*calPostProc
) (struct ath_hal
*, u8
);
792 struct hal_cal_list
{
793 const struct hal_percal_data
*calData
;
794 enum hal_cal_state calState
;
795 struct hal_cal_list
*calNext
;
799 * Enum to indentify the eeprom mappings
802 EEP_MAP_DEFAULT
= 0x0,
808 struct ath_hal_5416
{
811 struct ar5416_eeprom_def def
;
812 struct ar5416_eeprom_4k map4k
;
814 struct ar5416Stats ah_stats
;
815 struct ath9k_tx_queue_info ah_txq
[ATH9K_NUM_TX_QUEUES
];
816 void __iomem
*ah_cal_mem
;
818 u8 ah_macaddr
[ETH_ALEN
];
819 u8 ah_bssid
[ETH_ALEN
];
820 u8 ah_bssidmask
[ETH_ALEN
];
823 int16_t ah_curchanRadIndex
;
825 u32 ah_txOkInterruptMask
;
826 u32 ah_txErrInterruptMask
;
827 u32 ah_txDescInterruptMask
;
828 u32 ah_txEolInterruptMask
;
829 u32 ah_txUrnInterruptMask
;
830 bool ah_chipFullSleep
;
832 u16 ah_antennaSwitchSwap
;
833 enum ath9k_power_mode ah_powerMode
;
834 enum ath9k_ant_setting ah_diversityControl
;
837 enum hal_cal_types ah_suppCals
;
838 struct hal_cal_list ah_iqCalData
;
839 struct hal_cal_list ah_adcGainCalData
;
840 struct hal_cal_list ah_adcDcCalInitData
;
841 struct hal_cal_list ah_adcDcCalData
;
842 struct hal_cal_list
*ah_cal_list
;
843 struct hal_cal_list
*ah_cal_list_last
;
844 struct hal_cal_list
*ah_cal_list_curr
;
845 #define ah_totalPowerMeasI ah_Meas0.unsign
846 #define ah_totalPowerMeasQ ah_Meas1.unsign
847 #define ah_totalIqCorrMeas ah_Meas2.sign
848 #define ah_totalAdcIOddPhase ah_Meas0.unsign
849 #define ah_totalAdcIEvenPhase ah_Meas1.unsign
850 #define ah_totalAdcQOddPhase ah_Meas2.unsign
851 #define ah_totalAdcQEvenPhase ah_Meas3.unsign
852 #define ah_totalAdcDcOffsetIOddPhase ah_Meas0.sign
853 #define ah_totalAdcDcOffsetIEvenPhase ah_Meas1.sign
854 #define ah_totalAdcDcOffsetQOddPhase ah_Meas2.sign
855 #define ah_totalAdcDcOffsetQEvenPhase ah_Meas3.sign
857 u32 unsign
[AR5416_MAX_CHAINS
];
858 int32_t sign
[AR5416_MAX_CHAINS
];
861 u32 unsign
[AR5416_MAX_CHAINS
];
862 int32_t sign
[AR5416_MAX_CHAINS
];
865 u32 unsign
[AR5416_MAX_CHAINS
];
866 int32_t sign
[AR5416_MAX_CHAINS
];
869 u32 unsign
[AR5416_MAX_CHAINS
];
870 int32_t sign
[AR5416_MAX_CHAINS
];
874 u32 ah_staId1Defaults
;
880 } ah_enable32kHzClock
;
883 u32
*ah_analogBank0Data
;
884 u32
*ah_analogBank1Data
;
885 u32
*ah_analogBank2Data
;
886 u32
*ah_analogBank3Data
;
887 u32
*ah_analogBank6Data
;
888 u32
*ah_analogBank6TPCData
;
889 u32
*ah_analogBank7Data
;
890 u32
*ah_addac5416_21
;
893 int16_t ah_txPowerIndexOffset
;
894 u32 ah_beaconInterval
;
898 u32 ah_globaltxtimeout
;
906 bool ah_hasHwPhyCounters
;
908 struct ar5416AniState
*ah_curani
;
909 struct ar5416AniState ah_ani
[255];
910 int ah_totalSizeDesired
[5];
911 int ah_coarseHigh
[5];
914 enum ath9k_ani_cmd ah_ani_function
;
917 bool ah_intrMitigation
;
918 enum ath9k_ht_extprotspacing ah_extprotspacing
;
922 struct ar5416IniArray ah_iniModes
;
923 struct ar5416IniArray ah_iniCommon
;
924 struct ar5416IniArray ah_iniBank0
;
925 struct ar5416IniArray ah_iniBB_RfGain
;
926 struct ar5416IniArray ah_iniBank1
;
927 struct ar5416IniArray ah_iniBank2
;
928 struct ar5416IniArray ah_iniBank3
;
929 struct ar5416IniArray ah_iniBank6
;
930 struct ar5416IniArray ah_iniBank6TPC
;
931 struct ar5416IniArray ah_iniBank7
;
932 struct ar5416IniArray ah_iniAddac
;
933 struct ar5416IniArray ah_iniPcieSerdes
;
934 struct ar5416IniArray ah_iniModesAdditional
;
935 struct ar5416IniArray ah_iniModesRxGain
;
936 struct ar5416IniArray ah_iniModesTxGain
;
937 /* To indicate EEPROM mapping used */
938 enum hal_eep_map ah_eep_map
;
940 #define AH5416(_ah) ((struct ath_hal_5416 *)(_ah))
942 #define FREQ2FBIN(x, y) ((y) ? ((x) - 2300) : (((x) - 4800) / 5))
944 #define ar5416RfDetach(ah) do { \
945 if (AH5416(ah)->ah_rfHal.rfDetach != NULL) \
946 AH5416(ah)->ah_rfHal.rfDetach(ah); \
949 #define ath9k_hw_use_flash(_ah) \
950 (!(_ah->ah_flags & AH_USE_EEPROM))
953 #define DO_DELAY(x) do { \
954 if ((++(x) % 64) == 0) \
958 #define REG_WRITE_ARRAY(iniarray, column, regWr) do { \
960 for (r = 0; r < ((iniarray)->ia_rows); r++) { \
961 REG_WRITE(ah, INI_RA((iniarray), (r), 0), \
962 INI_RA((iniarray), r, (column))); \
967 #define BASE_ACTIVATE_DELAY 100
968 #define RTC_PLL_SETTLE_DELAY 1000
969 #define COEF_SCALE_S 24
970 #define HT40_CHANNEL_CENTER_SHIFT 10
972 #define AR5416_EEPROM_MAGIC_OFFSET 0x0
974 #define AR5416_EEPROM_S 2
975 #define AR5416_EEPROM_OFFSET 0x2000
976 #define AR5416_EEPROM_START_ADDR \
977 (AR_SREV_9100(ah)) ? 0x1fff1000 : 0x503f1200
978 #define AR5416_EEPROM_MAX 0xae0
979 #define ar5416_get_eep_ver(_ahp) \
980 (((_ahp)->ah_eeprom.def.baseEepHeader.version >> 12) & 0xF)
981 #define ar5416_get_eep_rev(_ahp) \
982 (((_ahp)->ah_eeprom.def.baseEepHeader.version) & 0xFFF)
983 #define ar5416_get_ntxchains(_txchainmask) \
984 (((_txchainmask >> 2) & 1) + \
985 ((_txchainmask >> 1) & 1) + (_txchainmask & 1))
987 /* EEPROM 4K bit map definations */
988 #define ar5416_get_eep4k_ver(_ahp) \
989 (((_ahp)->ah_eeprom.map4k.baseEepHeader.version >> 12) & 0xF)
990 #define ar5416_get_eep4k_rev(_ahp) \
991 (((_ahp)->ah_eeprom.map4k.baseEepHeader.version) & 0xFFF)
995 #define AR5416_EEPROM_MAGIC 0x5aa5
997 #define AR5416_EEPROM_MAGIC 0xa55a
1000 #define ATH9K_POW_SM(_r, _s) (((_r) & 0x3f) << (_s))
1002 #define ATH9K_ANTENNA0_CHAINMASK 0x1
1003 #define ATH9K_ANTENNA1_CHAINMASK 0x2
1005 #define ATH9K_NUM_DMA_DEBUG_REGS 8
1006 #define ATH9K_NUM_QUEUES 10
1008 #define HAL_NOISE_IMMUNE_MAX 4
1009 #define HAL_SPUR_IMMUNE_MAX 7
1010 #define HAL_FIRST_STEP_MAX 2
1012 #define ATH9K_ANI_OFDM_TRIG_HIGH 500
1013 #define ATH9K_ANI_OFDM_TRIG_LOW 200
1014 #define ATH9K_ANI_CCK_TRIG_HIGH 200
1015 #define ATH9K_ANI_CCK_TRIG_LOW 100
1016 #define ATH9K_ANI_NOISE_IMMUNE_LVL 4
1017 #define ATH9K_ANI_USE_OFDM_WEAK_SIG true
1018 #define ATH9K_ANI_CCK_WEAK_SIG_THR false
1019 #define ATH9K_ANI_SPUR_IMMUNE_LVL 7
1020 #define ATH9K_ANI_FIRSTEP_LVL 0
1021 #define ATH9K_ANI_RSSI_THR_HIGH 40
1022 #define ATH9K_ANI_RSSI_THR_LOW 7
1023 #define ATH9K_ANI_PERIOD 100
1025 #define AR_GPIOD_MASK 0x00001FFF
1026 #define AR_GPIO_BIT(_gpio) (1 << (_gpio))
1028 #define HAL_EP_RND(x, mul) \
1029 ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul))
1030 #define BEACON_RSSI(ahp) \
1031 HAL_EP_RND(ahp->ah_stats.ast_nodestats.ns_avgbrssi, \
1032 ATH9K_RSSI_EP_MULTIPLIER)
1034 #define ah_mibStats ah_stats.ast_mibstats
1036 #define AH_TIMEOUT 100000
1037 #define AH_TIME_QUANTUM 10
1039 #define AR_KEYTABLE_SIZE 128
1040 #define POWER_UP_TIME 200000
1042 #define EXT_ADDITIVE (0x8000)
1043 #define CTL_11A_EXT (CTL_11A | EXT_ADDITIVE)
1044 #define CTL_11G_EXT (CTL_11G | EXT_ADDITIVE)
1045 #define CTL_11B_EXT (CTL_11B | EXT_ADDITIVE)
1047 #define SUB_NUM_CTL_MODES_AT_5G_40 2
1048 #define SUB_NUM_CTL_MODES_AT_2G_40 3
1049 #define SPUR_RSSI_THRESH 40
1051 #define TU_TO_USEC(_tu) ((_tu) << 10)
1053 #define CAB_TIMEOUT_VAL 10
1054 #define BEACON_TIMEOUT_VAL 10
1055 #define MIN_BEACON_TIMEOUT_VAL 1
1056 #define SLEEP_SLOP 3
1058 #define CCK_SIFS_TIME 10
1059 #define CCK_PREAMBLE_BITS 144
1060 #define CCK_PLCP_BITS 48
1062 #define OFDM_SIFS_TIME 16
1063 #define OFDM_PREAMBLE_TIME 20
1064 #define OFDM_PLCP_BITS 22
1065 #define OFDM_SYMBOL_TIME 4
1067 #define OFDM_SIFS_TIME_HALF 32
1068 #define OFDM_PREAMBLE_TIME_HALF 40
1069 #define OFDM_PLCP_BITS_HALF 22
1070 #define OFDM_SYMBOL_TIME_HALF 8
1072 #define OFDM_SIFS_TIME_QUARTER 64
1073 #define OFDM_PREAMBLE_TIME_QUARTER 80
1074 #define OFDM_PLCP_BITS_QUARTER 22
1075 #define OFDM_SYMBOL_TIME_QUARTER 16
1077 u32
ath9k_hw_get_eeprom(struct ath_hal
*ah
,
1078 enum eeprom_param param
);