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ath9k: fix sparse warnings
[deliverable/linux.git] / drivers / net / wireless / ath9k / hw.h
1 /*
2 * Copyright (c) 2008 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #ifndef HW_H
18 #define HW_H
19
20 #include <linux/if_ether.h>
21 #include <linux/delay.h>
22
23 extern const struct hal_percal_data iq_cal_multi_sample;
24 extern const struct hal_percal_data iq_cal_single_sample;
25 extern const struct hal_percal_data adc_gain_cal_multi_sample;
26 extern const struct hal_percal_data adc_gain_cal_single_sample;
27 extern const struct hal_percal_data adc_dc_cal_multi_sample;
28 extern const struct hal_percal_data adc_dc_cal_single_sample;
29 extern const struct hal_percal_data adc_init_dc_cal;
30
31 struct ar5416_desc {
32 u32 ds_link;
33 u32 ds_data;
34 u32 ds_ctl0;
35 u32 ds_ctl1;
36 union {
37 struct {
38 u32 ctl2;
39 u32 ctl3;
40 u32 ctl4;
41 u32 ctl5;
42 u32 ctl6;
43 u32 ctl7;
44 u32 ctl8;
45 u32 ctl9;
46 u32 ctl10;
47 u32 ctl11;
48 u32 status0;
49 u32 status1;
50 u32 status2;
51 u32 status3;
52 u32 status4;
53 u32 status5;
54 u32 status6;
55 u32 status7;
56 u32 status8;
57 u32 status9;
58 } tx;
59 struct {
60 u32 status0;
61 u32 status1;
62 u32 status2;
63 u32 status3;
64 u32 status4;
65 u32 status5;
66 u32 status6;
67 u32 status7;
68 u32 status8;
69 } rx;
70 } u;
71 } __packed;
72
73 #define AR5416DESC(_ds) ((struct ar5416_desc *)(_ds))
74 #define AR5416DESC_CONST(_ds) ((const struct ar5416_desc *)(_ds))
75
76 #define ds_ctl2 u.tx.ctl2
77 #define ds_ctl3 u.tx.ctl3
78 #define ds_ctl4 u.tx.ctl4
79 #define ds_ctl5 u.tx.ctl5
80 #define ds_ctl6 u.tx.ctl6
81 #define ds_ctl7 u.tx.ctl7
82 #define ds_ctl8 u.tx.ctl8
83 #define ds_ctl9 u.tx.ctl9
84 #define ds_ctl10 u.tx.ctl10
85 #define ds_ctl11 u.tx.ctl11
86
87 #define ds_txstatus0 u.tx.status0
88 #define ds_txstatus1 u.tx.status1
89 #define ds_txstatus2 u.tx.status2
90 #define ds_txstatus3 u.tx.status3
91 #define ds_txstatus4 u.tx.status4
92 #define ds_txstatus5 u.tx.status5
93 #define ds_txstatus6 u.tx.status6
94 #define ds_txstatus7 u.tx.status7
95 #define ds_txstatus8 u.tx.status8
96 #define ds_txstatus9 u.tx.status9
97
98 #define ds_rxstatus0 u.rx.status0
99 #define ds_rxstatus1 u.rx.status1
100 #define ds_rxstatus2 u.rx.status2
101 #define ds_rxstatus3 u.rx.status3
102 #define ds_rxstatus4 u.rx.status4
103 #define ds_rxstatus5 u.rx.status5
104 #define ds_rxstatus6 u.rx.status6
105 #define ds_rxstatus7 u.rx.status7
106 #define ds_rxstatus8 u.rx.status8
107
108 #define AR_FrameLen 0x00000fff
109 #define AR_VirtMoreFrag 0x00001000
110 #define AR_TxCtlRsvd00 0x0000e000
111 #define AR_XmitPower 0x003f0000
112 #define AR_XmitPower_S 16
113 #define AR_RTSEnable 0x00400000
114 #define AR_VEOL 0x00800000
115 #define AR_ClrDestMask 0x01000000
116 #define AR_TxCtlRsvd01 0x1e000000
117 #define AR_TxIntrReq 0x20000000
118 #define AR_DestIdxValid 0x40000000
119 #define AR_CTSEnable 0x80000000
120
121 #define AR_BufLen 0x00000fff
122 #define AR_TxMore 0x00001000
123 #define AR_DestIdx 0x000fe000
124 #define AR_DestIdx_S 13
125 #define AR_FrameType 0x00f00000
126 #define AR_FrameType_S 20
127 #define AR_NoAck 0x01000000
128 #define AR_InsertTS 0x02000000
129 #define AR_CorruptFCS 0x04000000
130 #define AR_ExtOnly 0x08000000
131 #define AR_ExtAndCtl 0x10000000
132 #define AR_MoreAggr 0x20000000
133 #define AR_IsAggr 0x40000000
134
135 #define AR_BurstDur 0x00007fff
136 #define AR_BurstDur_S 0
137 #define AR_DurUpdateEna 0x00008000
138 #define AR_XmitDataTries0 0x000f0000
139 #define AR_XmitDataTries0_S 16
140 #define AR_XmitDataTries1 0x00f00000
141 #define AR_XmitDataTries1_S 20
142 #define AR_XmitDataTries2 0x0f000000
143 #define AR_XmitDataTries2_S 24
144 #define AR_XmitDataTries3 0xf0000000
145 #define AR_XmitDataTries3_S 28
146
147 #define AR_XmitRate0 0x000000ff
148 #define AR_XmitRate0_S 0
149 #define AR_XmitRate1 0x0000ff00
150 #define AR_XmitRate1_S 8
151 #define AR_XmitRate2 0x00ff0000
152 #define AR_XmitRate2_S 16
153 #define AR_XmitRate3 0xff000000
154 #define AR_XmitRate3_S 24
155
156 #define AR_PacketDur0 0x00007fff
157 #define AR_PacketDur0_S 0
158 #define AR_RTSCTSQual0 0x00008000
159 #define AR_PacketDur1 0x7fff0000
160 #define AR_PacketDur1_S 16
161 #define AR_RTSCTSQual1 0x80000000
162
163 #define AR_PacketDur2 0x00007fff
164 #define AR_PacketDur2_S 0
165 #define AR_RTSCTSQual2 0x00008000
166 #define AR_PacketDur3 0x7fff0000
167 #define AR_PacketDur3_S 16
168 #define AR_RTSCTSQual3 0x80000000
169
170 #define AR_AggrLen 0x0000ffff
171 #define AR_AggrLen_S 0
172 #define AR_TxCtlRsvd60 0x00030000
173 #define AR_PadDelim 0x03fc0000
174 #define AR_PadDelim_S 18
175 #define AR_EncrType 0x0c000000
176 #define AR_EncrType_S 26
177 #define AR_TxCtlRsvd61 0xf0000000
178
179 #define AR_2040_0 0x00000001
180 #define AR_GI0 0x00000002
181 #define AR_ChainSel0 0x0000001c
182 #define AR_ChainSel0_S 2
183 #define AR_2040_1 0x00000020
184 #define AR_GI1 0x00000040
185 #define AR_ChainSel1 0x00000380
186 #define AR_ChainSel1_S 7
187 #define AR_2040_2 0x00000400
188 #define AR_GI2 0x00000800
189 #define AR_ChainSel2 0x00007000
190 #define AR_ChainSel2_S 12
191 #define AR_2040_3 0x00008000
192 #define AR_GI3 0x00010000
193 #define AR_ChainSel3 0x000e0000
194 #define AR_ChainSel3_S 17
195 #define AR_RTSCTSRate 0x0ff00000
196 #define AR_RTSCTSRate_S 20
197 #define AR_TxCtlRsvd70 0xf0000000
198
199 #define AR_TxRSSIAnt00 0x000000ff
200 #define AR_TxRSSIAnt00_S 0
201 #define AR_TxRSSIAnt01 0x0000ff00
202 #define AR_TxRSSIAnt01_S 8
203 #define AR_TxRSSIAnt02 0x00ff0000
204 #define AR_TxRSSIAnt02_S 16
205 #define AR_TxStatusRsvd00 0x3f000000
206 #define AR_TxBaStatus 0x40000000
207 #define AR_TxStatusRsvd01 0x80000000
208
209 #define AR_FrmXmitOK 0x00000001
210 #define AR_ExcessiveRetries 0x00000002
211 #define AR_FIFOUnderrun 0x00000004
212 #define AR_Filtered 0x00000008
213 #define AR_RTSFailCnt 0x000000f0
214 #define AR_RTSFailCnt_S 4
215 #define AR_DataFailCnt 0x00000f00
216 #define AR_DataFailCnt_S 8
217 #define AR_VirtRetryCnt 0x0000f000
218 #define AR_VirtRetryCnt_S 12
219 #define AR_TxDelimUnderrun 0x00010000
220 #define AR_TxDataUnderrun 0x00020000
221 #define AR_DescCfgErr 0x00040000
222 #define AR_TxTimerExpired 0x00080000
223 #define AR_TxStatusRsvd10 0xfff00000
224
225 #define AR_SendTimestamp ds_txstatus2
226 #define AR_BaBitmapLow ds_txstatus3
227 #define AR_BaBitmapHigh ds_txstatus4
228
229 #define AR_TxRSSIAnt10 0x000000ff
230 #define AR_TxRSSIAnt10_S 0
231 #define AR_TxRSSIAnt11 0x0000ff00
232 #define AR_TxRSSIAnt11_S 8
233 #define AR_TxRSSIAnt12 0x00ff0000
234 #define AR_TxRSSIAnt12_S 16
235 #define AR_TxRSSICombined 0xff000000
236 #define AR_TxRSSICombined_S 24
237
238 #define AR_TxEVM0 ds_txstatus5
239 #define AR_TxEVM1 ds_txstatus6
240 #define AR_TxEVM2 ds_txstatus7
241
242 #define AR_TxDone 0x00000001
243 #define AR_SeqNum 0x00001ffe
244 #define AR_SeqNum_S 1
245 #define AR_TxStatusRsvd80 0x0001e000
246 #define AR_TxOpExceeded 0x00020000
247 #define AR_TxStatusRsvd81 0x001c0000
248 #define AR_FinalTxIdx 0x00600000
249 #define AR_FinalTxIdx_S 21
250 #define AR_TxStatusRsvd82 0x01800000
251 #define AR_PowerMgmt 0x02000000
252 #define AR_TxStatusRsvd83 0xfc000000
253
254 #define AR_RxCTLRsvd00 0xffffffff
255
256 #define AR_BufLen 0x00000fff
257 #define AR_RxCtlRsvd00 0x00001000
258 #define AR_RxIntrReq 0x00002000
259 #define AR_RxCtlRsvd01 0xffffc000
260
261 #define AR_RxRSSIAnt00 0x000000ff
262 #define AR_RxRSSIAnt00_S 0
263 #define AR_RxRSSIAnt01 0x0000ff00
264 #define AR_RxRSSIAnt01_S 8
265 #define AR_RxRSSIAnt02 0x00ff0000
266 #define AR_RxRSSIAnt02_S 16
267 #define AR_RxRate 0xff000000
268 #define AR_RxRate_S 24
269 #define AR_RxStatusRsvd00 0xff000000
270
271 #define AR_DataLen 0x00000fff
272 #define AR_RxMore 0x00001000
273 #define AR_NumDelim 0x003fc000
274 #define AR_NumDelim_S 14
275 #define AR_RxStatusRsvd10 0xff800000
276
277 #define AR_RcvTimestamp ds_rxstatus2
278
279 #define AR_GI 0x00000001
280 #define AR_2040 0x00000002
281 #define AR_Parallel40 0x00000004
282 #define AR_Parallel40_S 2
283 #define AR_RxStatusRsvd30 0x000000f8
284 #define AR_RxAntenna 0xffffff00
285 #define AR_RxAntenna_S 8
286
287 #define AR_RxRSSIAnt10 0x000000ff
288 #define AR_RxRSSIAnt10_S 0
289 #define AR_RxRSSIAnt11 0x0000ff00
290 #define AR_RxRSSIAnt11_S 8
291 #define AR_RxRSSIAnt12 0x00ff0000
292 #define AR_RxRSSIAnt12_S 16
293 #define AR_RxRSSICombined 0xff000000
294 #define AR_RxRSSICombined_S 24
295
296 #define AR_RxEVM0 ds_rxstatus4
297 #define AR_RxEVM1 ds_rxstatus5
298 #define AR_RxEVM2 ds_rxstatus6
299
300 #define AR_RxDone 0x00000001
301 #define AR_RxFrameOK 0x00000002
302 #define AR_CRCErr 0x00000004
303 #define AR_DecryptCRCErr 0x00000008
304 #define AR_PHYErr 0x00000010
305 #define AR_MichaelErr 0x00000020
306 #define AR_PreDelimCRCErr 0x00000040
307 #define AR_RxStatusRsvd70 0x00000080
308 #define AR_RxKeyIdxValid 0x00000100
309 #define AR_KeyIdx 0x0000fe00
310 #define AR_KeyIdx_S 9
311 #define AR_PHYErrCode 0x0000ff00
312 #define AR_PHYErrCode_S 8
313 #define AR_RxMoreAggr 0x00010000
314 #define AR_RxAggr 0x00020000
315 #define AR_PostDelimCRCErr 0x00040000
316 #define AR_RxStatusRsvd71 0x3ff80000
317 #define AR_DecryptBusyErr 0x40000000
318 #define AR_KeyMiss 0x80000000
319
320 #define AR5416_MAGIC 0x19641014
321
322 #define RXSTATUS_RATE(ah, ads) (AR_SREV_5416_V20_OR_LATER(ah) ? \
323 MS(ads->ds_rxstatus0, AR_RxRate) : \
324 (ads->ds_rxstatus3 >> 2) & 0xFF)
325
326 #define set11nTries(_series, _index) \
327 (SM((_series)[_index].Tries, AR_XmitDataTries##_index))
328
329 #define set11nRate(_series, _index) \
330 (SM((_series)[_index].Rate, AR_XmitRate##_index))
331
332 #define set11nPktDurRTSCTS(_series, _index) \
333 (SM((_series)[_index].PktDuration, AR_PacketDur##_index) | \
334 ((_series)[_index].RateFlags & ATH9K_RATESERIES_RTS_CTS ? \
335 AR_RTSCTSQual##_index : 0))
336
337 #define set11nRateFlags(_series, _index) \
338 (((_series)[_index].RateFlags & ATH9K_RATESERIES_2040 ? \
339 AR_2040_##_index : 0) \
340 |((_series)[_index].RateFlags & ATH9K_RATESERIES_HALFGI ? \
341 AR_GI##_index : 0) \
342 |SM((_series)[_index].ChSel, AR_ChainSel##_index))
343
344 #define AR_SREV_9100(ah) ((ah->ah_macVersion) == AR_SREV_VERSION_9100)
345
346 #define INIT_CONFIG_STATUS 0x00000000
347 #define INIT_RSSI_THR 0x00000700
348 #define INIT_BCON_CNTRL_REG 0x00000000
349
350 #define MIN_TX_FIFO_THRESHOLD 0x1
351 #define MAX_TX_FIFO_THRESHOLD ((4096 / 64) - 1)
352 #define INIT_TX_FIFO_THRESHOLD MIN_TX_FIFO_THRESHOLD
353
354 struct ar5416AniState {
355 struct ath9k_channel c;
356 u8 noiseImmunityLevel;
357 u8 spurImmunityLevel;
358 u8 firstepLevel;
359 u8 ofdmWeakSigDetectOff;
360 u8 cckWeakSigThreshold;
361 u32 listenTime;
362 u32 ofdmTrigHigh;
363 u32 ofdmTrigLow;
364 int32_t cckTrigHigh;
365 int32_t cckTrigLow;
366 int32_t rssiThrLow;
367 int32_t rssiThrHigh;
368 u32 noiseFloor;
369 u32 txFrameCount;
370 u32 rxFrameCount;
371 u32 cycleCount;
372 u32 ofdmPhyErrCount;
373 u32 cckPhyErrCount;
374 u32 ofdmPhyErrBase;
375 u32 cckPhyErrBase;
376 int16_t pktRssi[2];
377 int16_t ofdmErrRssi[2];
378 int16_t cckErrRssi[2];
379 };
380
381 #define HAL_PROCESS_ANI 0x00000001
382 #define DO_ANI(ah) \
383 ((AH5416(ah)->ah_procPhyErr & HAL_PROCESS_ANI))
384
385 struct ar5416Stats {
386 u32 ast_ani_niup;
387 u32 ast_ani_nidown;
388 u32 ast_ani_spurup;
389 u32 ast_ani_spurdown;
390 u32 ast_ani_ofdmon;
391 u32 ast_ani_ofdmoff;
392 u32 ast_ani_cckhigh;
393 u32 ast_ani_ccklow;
394 u32 ast_ani_stepup;
395 u32 ast_ani_stepdown;
396 u32 ast_ani_ofdmerrs;
397 u32 ast_ani_cckerrs;
398 u32 ast_ani_reset;
399 u32 ast_ani_lzero;
400 u32 ast_ani_lneg;
401 struct ath9k_mib_stats ast_mibstats;
402 struct ath9k_node_stats ast_nodestats;
403 };
404
405 #define AR5416_OPFLAGS_11A 0x01
406 #define AR5416_OPFLAGS_11G 0x02
407 #define AR5416_OPFLAGS_N_5G_HT40 0x04
408 #define AR5416_OPFLAGS_N_2G_HT40 0x08
409 #define AR5416_OPFLAGS_N_5G_HT20 0x10
410 #define AR5416_OPFLAGS_N_2G_HT20 0x20
411
412 #define EEP_RFSILENT_ENABLED 0x0001
413 #define EEP_RFSILENT_ENABLED_S 0
414 #define EEP_RFSILENT_POLARITY 0x0002
415 #define EEP_RFSILENT_POLARITY_S 1
416 #define EEP_RFSILENT_GPIO_SEL 0x001c
417 #define EEP_RFSILENT_GPIO_SEL_S 2
418
419 #define AR5416_EEP_NO_BACK_VER 0x1
420 #define AR5416_EEP_VER 0xE
421 #define AR5416_EEP_VER_MINOR_MASK 0x0FFF
422 #define AR5416_EEP_MINOR_VER_2 0x2
423 #define AR5416_EEP_MINOR_VER_3 0x3
424 #define AR5416_EEP_MINOR_VER_7 0x7
425 #define AR5416_EEP_MINOR_VER_9 0x9
426 #define AR5416_EEP_MINOR_VER_16 0x10
427 #define AR5416_EEP_MINOR_VER_17 0x11
428 #define AR5416_EEP_MINOR_VER_19 0x13
429
430 #define AR5416_NUM_5G_CAL_PIERS 8
431 #define AR5416_NUM_2G_CAL_PIERS 4
432 #define AR5416_NUM_5G_20_TARGET_POWERS 8
433 #define AR5416_NUM_5G_40_TARGET_POWERS 8
434 #define AR5416_NUM_2G_CCK_TARGET_POWERS 3
435 #define AR5416_NUM_2G_20_TARGET_POWERS 4
436 #define AR5416_NUM_2G_40_TARGET_POWERS 4
437 #define AR5416_NUM_CTLS 24
438 #define AR5416_NUM_BAND_EDGES 8
439 #define AR5416_NUM_PD_GAINS 4
440 #define AR5416_PD_GAINS_IN_MASK 4
441 #define AR5416_PD_GAIN_ICEPTS 5
442 #define AR5416_EEPROM_MODAL_SPURS 5
443 #define AR5416_MAX_RATE_POWER 63
444 #define AR5416_NUM_PDADC_VALUES 128
445 #define AR5416_BCHAN_UNUSED 0xFF
446 #define AR5416_MAX_PWR_RANGE_IN_HALF_DB 64
447 #define AR5416_MAX_CHAINS 3
448 #define AR5416_PWR_TABLE_OFFSET -5
449
450 /* Rx gain type values */
451 #define AR5416_EEP_RXGAIN_23DB_BACKOFF 0
452 #define AR5416_EEP_RXGAIN_13DB_BACKOFF 1
453 #define AR5416_EEP_RXGAIN_ORIG 2
454
455 /* Tx gain type values */
456 #define AR5416_EEP_TXGAIN_ORIGINAL 0
457 #define AR5416_EEP_TXGAIN_HIGH_POWER 1
458
459 #define AR5416_EEP4K_START_LOC 64
460 #define AR5416_EEP4K_NUM_2G_CAL_PIERS 3
461 #define AR5416_EEP4K_NUM_2G_CCK_TARGET_POWERS 3
462 #define AR5416_EEP4K_NUM_2G_20_TARGET_POWERS 3
463 #define AR5416_EEP4K_NUM_2G_40_TARGET_POWERS 3
464 #define AR5416_EEP4K_NUM_CTLS 12
465 #define AR5416_EEP4K_NUM_BAND_EDGES 4
466 #define AR5416_EEP4K_NUM_PD_GAINS 2
467 #define AR5416_EEP4K_PD_GAINS_IN_MASK 4
468 #define AR5416_EEP4K_PD_GAIN_ICEPTS 5
469 #define AR5416_EEP4K_MAX_CHAINS 1
470
471 enum eeprom_param {
472 EEP_NFTHRESH_5,
473 EEP_NFTHRESH_2,
474 EEP_MAC_MSW,
475 EEP_MAC_MID,
476 EEP_MAC_LSW,
477 EEP_REG_0,
478 EEP_REG_1,
479 EEP_OP_CAP,
480 EEP_OP_MODE,
481 EEP_RF_SILENT,
482 EEP_OB_5,
483 EEP_DB_5,
484 EEP_OB_2,
485 EEP_DB_2,
486 EEP_MINOR_REV,
487 EEP_TX_MASK,
488 EEP_RX_MASK,
489 EEP_RXGAIN_TYPE,
490 EEP_TXGAIN_TYPE,
491 };
492
493 enum ar5416_rates {
494 rate6mb, rate9mb, rate12mb, rate18mb,
495 rate24mb, rate36mb, rate48mb, rate54mb,
496 rate1l, rate2l, rate2s, rate5_5l,
497 rate5_5s, rate11l, rate11s, rateXr,
498 rateHt20_0, rateHt20_1, rateHt20_2, rateHt20_3,
499 rateHt20_4, rateHt20_5, rateHt20_6, rateHt20_7,
500 rateHt40_0, rateHt40_1, rateHt40_2, rateHt40_3,
501 rateHt40_4, rateHt40_5, rateHt40_6, rateHt40_7,
502 rateDupCck, rateDupOfdm, rateExtCck, rateExtOfdm,
503 Ar5416RateSize
504 };
505
506 enum ath9k_hal_freq_band {
507 ATH9K_HAL_FREQ_BAND_5GHZ = 0,
508 ATH9K_HAL_FREQ_BAND_2GHZ = 1
509 };
510
511 struct base_eep_header {
512 u16 length;
513 u16 checksum;
514 u16 version;
515 u8 opCapFlags;
516 u8 eepMisc;
517 u16 regDmn[2];
518 u8 macAddr[6];
519 u8 rxMask;
520 u8 txMask;
521 u16 rfSilent;
522 u16 blueToothOptions;
523 u16 deviceCap;
524 u32 binBuildNumber;
525 u8 deviceType;
526 u8 pwdclkind;
527 u8 futureBase_1[2];
528 u8 rxGainType;
529 u8 futureBase_2[3];
530 u8 txGainType;
531 u8 futureBase_3[25];
532 } __packed;
533
534 struct base_eep_header_4k {
535 u16 length;
536 u16 checksum;
537 u16 version;
538 u8 opCapFlags;
539 u8 eepMisc;
540 u16 regDmn[2];
541 u8 macAddr[6];
542 u8 rxMask;
543 u8 txMask;
544 u16 rfSilent;
545 u16 blueToothOptions;
546 u16 deviceCap;
547 u32 binBuildNumber;
548 u8 deviceType;
549 u8 futureBase[1];
550 } __packed;
551
552
553 struct spur_chan {
554 u16 spurChan;
555 u8 spurRangeLow;
556 u8 spurRangeHigh;
557 } __packed;
558
559 struct modal_eep_header {
560 u32 antCtrlChain[AR5416_MAX_CHAINS];
561 u32 antCtrlCommon;
562 u8 antennaGainCh[AR5416_MAX_CHAINS];
563 u8 switchSettling;
564 u8 txRxAttenCh[AR5416_MAX_CHAINS];
565 u8 rxTxMarginCh[AR5416_MAX_CHAINS];
566 u8 adcDesiredSize;
567 u8 pgaDesiredSize;
568 u8 xlnaGainCh[AR5416_MAX_CHAINS];
569 u8 txEndToXpaOff;
570 u8 txEndToRxOn;
571 u8 txFrameToXpaOn;
572 u8 thresh62;
573 u8 noiseFloorThreshCh[AR5416_MAX_CHAINS];
574 u8 xpdGain;
575 u8 xpd;
576 u8 iqCalICh[AR5416_MAX_CHAINS];
577 u8 iqCalQCh[AR5416_MAX_CHAINS];
578 u8 pdGainOverlap;
579 u8 ob;
580 u8 db;
581 u8 xpaBiasLvl;
582 u8 pwrDecreaseFor2Chain;
583 u8 pwrDecreaseFor3Chain;
584 u8 txFrameToDataStart;
585 u8 txFrameToPaOn;
586 u8 ht40PowerIncForPdadc;
587 u8 bswAtten[AR5416_MAX_CHAINS];
588 u8 bswMargin[AR5416_MAX_CHAINS];
589 u8 swSettleHt40;
590 u8 xatten2Db[AR5416_MAX_CHAINS];
591 u8 xatten2Margin[AR5416_MAX_CHAINS];
592 u8 ob_ch1;
593 u8 db_ch1;
594 u8 useAnt1:1,
595 force_xpaon:1,
596 local_bias:1,
597 femBandSelectUsed:1, xlnabufin:1, xlnaisel:2, xlnabufmode:1;
598 u8 futureModalar9280;
599 u16 xpaBiasLvlFreq[3];
600 u8 futureModal[6];
601
602 struct spur_chan spurChans[AR5416_EEPROM_MODAL_SPURS];
603 } __packed;
604
605 struct modal_eep_4k_header {
606 u32 antCtrlChain[AR5416_EEP4K_MAX_CHAINS];
607 u32 antCtrlCommon;
608 u8 antennaGainCh[AR5416_EEP4K_MAX_CHAINS];
609 u8 switchSettling;
610 u8 txRxAttenCh[AR5416_EEP4K_MAX_CHAINS];
611 u8 rxTxMarginCh[AR5416_EEP4K_MAX_CHAINS];
612 u8 adcDesiredSize;
613 u8 pgaDesiredSize;
614 u8 xlnaGainCh[AR5416_EEP4K_MAX_CHAINS];
615 u8 txEndToXpaOff;
616 u8 txEndToRxOn;
617 u8 txFrameToXpaOn;
618 u8 thresh62;
619 u8 noiseFloorThreshCh[AR5416_EEP4K_MAX_CHAINS];
620 u8 xpdGain;
621 u8 xpd;
622 u8 iqCalICh[AR5416_EEP4K_MAX_CHAINS];
623 u8 iqCalQCh[AR5416_EEP4K_MAX_CHAINS];
624 u8 pdGainOverlap;
625 u8 ob_01;
626 u8 db1_01;
627 u8 xpaBiasLvl;
628 u8 txFrameToDataStart;
629 u8 txFrameToPaOn;
630 u8 ht40PowerIncForPdadc;
631 u8 bswAtten[AR5416_EEP4K_MAX_CHAINS];
632 u8 bswMargin[AR5416_EEP4K_MAX_CHAINS];
633 u8 swSettleHt40;
634 u8 xatten2Db[AR5416_EEP4K_MAX_CHAINS];
635 u8 xatten2Margin[AR5416_EEP4K_MAX_CHAINS];
636 u8 db2_01;
637 u8 version;
638 u16 ob_234;
639 u16 db1_234;
640 u16 db2_234;
641 u8 futureModal[4];
642
643 struct spur_chan spurChans[AR5416_EEPROM_MODAL_SPURS];
644 } __packed;
645
646
647 struct cal_data_per_freq {
648 u8 pwrPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
649 u8 vpdPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
650 } __packed;
651
652 struct cal_data_per_freq_4k {
653 u8 pwrPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_EEP4K_PD_GAIN_ICEPTS];
654 u8 vpdPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_EEP4K_PD_GAIN_ICEPTS];
655 } __packed;
656
657 struct cal_target_power_leg {
658 u8 bChannel;
659 u8 tPow2x[4];
660 } __packed;
661
662 struct cal_target_power_ht {
663 u8 bChannel;
664 u8 tPow2x[8];
665 } __packed;
666
667
668 #ifdef __BIG_ENDIAN_BITFIELD
669 struct cal_ctl_edges {
670 u8 bChannel;
671 u8 flag:2, tPower:6;
672 } __packed;
673 #else
674 struct cal_ctl_edges {
675 u8 bChannel;
676 u8 tPower:6, flag:2;
677 } __packed;
678 #endif
679
680 struct cal_ctl_data {
681 struct cal_ctl_edges
682 ctlEdges[AR5416_MAX_CHAINS][AR5416_NUM_BAND_EDGES];
683 } __packed;
684
685 struct cal_ctl_data_4k {
686 struct cal_ctl_edges
687 ctlEdges[AR5416_EEP4K_MAX_CHAINS][AR5416_EEP4K_NUM_BAND_EDGES];
688 } __packed;
689
690 struct ar5416_eeprom_def {
691 struct base_eep_header baseEepHeader;
692 u8 custData[64];
693 struct modal_eep_header modalHeader[2];
694 u8 calFreqPier5G[AR5416_NUM_5G_CAL_PIERS];
695 u8 calFreqPier2G[AR5416_NUM_2G_CAL_PIERS];
696 struct cal_data_per_freq
697 calPierData5G[AR5416_MAX_CHAINS][AR5416_NUM_5G_CAL_PIERS];
698 struct cal_data_per_freq
699 calPierData2G[AR5416_MAX_CHAINS][AR5416_NUM_2G_CAL_PIERS];
700 struct cal_target_power_leg
701 calTargetPower5G[AR5416_NUM_5G_20_TARGET_POWERS];
702 struct cal_target_power_ht
703 calTargetPower5GHT20[AR5416_NUM_5G_20_TARGET_POWERS];
704 struct cal_target_power_ht
705 calTargetPower5GHT40[AR5416_NUM_5G_40_TARGET_POWERS];
706 struct cal_target_power_leg
707 calTargetPowerCck[AR5416_NUM_2G_CCK_TARGET_POWERS];
708 struct cal_target_power_leg
709 calTargetPower2G[AR5416_NUM_2G_20_TARGET_POWERS];
710 struct cal_target_power_ht
711 calTargetPower2GHT20[AR5416_NUM_2G_20_TARGET_POWERS];
712 struct cal_target_power_ht
713 calTargetPower2GHT40[AR5416_NUM_2G_40_TARGET_POWERS];
714 u8 ctlIndex[AR5416_NUM_CTLS];
715 struct cal_ctl_data ctlData[AR5416_NUM_CTLS];
716 u8 padding;
717 } __packed;
718
719 struct ar5416_eeprom_4k {
720 struct base_eep_header_4k baseEepHeader;
721 u8 custData[20];
722 struct modal_eep_4k_header modalHeader;
723 u8 calFreqPier2G[AR5416_EEP4K_NUM_2G_CAL_PIERS];
724 struct cal_data_per_freq_4k
725 calPierData2G[AR5416_EEP4K_MAX_CHAINS][AR5416_EEP4K_NUM_2G_CAL_PIERS];
726 struct cal_target_power_leg
727 calTargetPowerCck[AR5416_EEP4K_NUM_2G_CCK_TARGET_POWERS];
728 struct cal_target_power_leg
729 calTargetPower2G[AR5416_EEP4K_NUM_2G_20_TARGET_POWERS];
730 struct cal_target_power_ht
731 calTargetPower2GHT20[AR5416_EEP4K_NUM_2G_20_TARGET_POWERS];
732 struct cal_target_power_ht
733 calTargetPower2GHT40[AR5416_EEP4K_NUM_2G_40_TARGET_POWERS];
734 u8 ctlIndex[AR5416_EEP4K_NUM_CTLS];
735 struct cal_ctl_data_4k ctlData[AR5416_EEP4K_NUM_CTLS];
736 u8 padding;
737 } __packed;
738
739 struct ar5416IniArray {
740 u32 *ia_array;
741 u32 ia_rows;
742 u32 ia_columns;
743 };
744
745 #define INIT_INI_ARRAY(iniarray, array, rows, columns) do { \
746 (iniarray)->ia_array = (u32 *)(array); \
747 (iniarray)->ia_rows = (rows); \
748 (iniarray)->ia_columns = (columns); \
749 } while (0)
750
751 #define INI_RA(iniarray, row, column) \
752 (((iniarray)->ia_array)[(row) * ((iniarray)->ia_columns) + (column)])
753
754 #define INIT_CAL(_perCal) do { \
755 (_perCal)->calState = CAL_WAITING; \
756 (_perCal)->calNext = NULL; \
757 } while (0)
758
759 #define INSERT_CAL(_ahp, _perCal) \
760 do { \
761 if ((_ahp)->ah_cal_list_last == NULL) { \
762 (_ahp)->ah_cal_list = \
763 (_ahp)->ah_cal_list_last = (_perCal); \
764 ((_ahp)->ah_cal_list_last)->calNext = (_perCal); \
765 } else { \
766 ((_ahp)->ah_cal_list_last)->calNext = (_perCal); \
767 (_ahp)->ah_cal_list_last = (_perCal); \
768 (_perCal)->calNext = (_ahp)->ah_cal_list; \
769 } \
770 } while (0)
771
772 enum hal_cal_types {
773 ADC_DC_INIT_CAL = 0x1,
774 ADC_GAIN_CAL = 0x2,
775 ADC_DC_CAL = 0x4,
776 IQ_MISMATCH_CAL = 0x8
777 };
778
779 enum hal_cal_state {
780 CAL_INACTIVE,
781 CAL_WAITING,
782 CAL_RUNNING,
783 CAL_DONE
784 };
785
786 #define MIN_CAL_SAMPLES 1
787 #define MAX_CAL_SAMPLES 64
788 #define INIT_LOG_COUNT 5
789 #define PER_MIN_LOG_COUNT 2
790 #define PER_MAX_LOG_COUNT 10
791
792 struct hal_percal_data {
793 enum hal_cal_types calType;
794 u32 calNumSamples;
795 u32 calCountMax;
796 void (*calCollect) (struct ath_hal *);
797 void (*calPostProc) (struct ath_hal *, u8);
798 };
799
800 struct hal_cal_list {
801 const struct hal_percal_data *calData;
802 enum hal_cal_state calState;
803 struct hal_cal_list *calNext;
804 };
805
806 /*
807 * Enum to indentify the eeprom mappings
808 */
809 enum hal_eep_map {
810 EEP_MAP_DEFAULT = 0x0,
811 EEP_MAP_4KBITS,
812 EEP_MAP_MAX
813 };
814
815
816 struct ath_hal_5416 {
817 struct ath_hal ah;
818 union {
819 struct ar5416_eeprom_def def;
820 struct ar5416_eeprom_4k map4k;
821 } ah_eeprom;
822 struct ar5416Stats ah_stats;
823 struct ath9k_tx_queue_info ah_txq[ATH9K_NUM_TX_QUEUES];
824 void __iomem *ah_cal_mem;
825
826 u8 ah_macaddr[ETH_ALEN];
827 u8 ah_bssid[ETH_ALEN];
828 u8 ah_bssidmask[ETH_ALEN];
829 u16 ah_assocId;
830
831 int16_t ah_curchanRadIndex;
832 u32 ah_maskReg;
833 u32 ah_txOkInterruptMask;
834 u32 ah_txErrInterruptMask;
835 u32 ah_txDescInterruptMask;
836 u32 ah_txEolInterruptMask;
837 u32 ah_txUrnInterruptMask;
838 bool ah_chipFullSleep;
839 u32 ah_atimWindow;
840 u16 ah_antennaSwitchSwap;
841 enum ath9k_power_mode ah_powerMode;
842 enum ath9k_ant_setting ah_diversityControl;
843
844 /* Calibration */
845 enum hal_cal_types ah_suppCals;
846 struct hal_cal_list ah_iqCalData;
847 struct hal_cal_list ah_adcGainCalData;
848 struct hal_cal_list ah_adcDcCalInitData;
849 struct hal_cal_list ah_adcDcCalData;
850 struct hal_cal_list *ah_cal_list;
851 struct hal_cal_list *ah_cal_list_last;
852 struct hal_cal_list *ah_cal_list_curr;
853 #define ah_totalPowerMeasI ah_Meas0.unsign
854 #define ah_totalPowerMeasQ ah_Meas1.unsign
855 #define ah_totalIqCorrMeas ah_Meas2.sign
856 #define ah_totalAdcIOddPhase ah_Meas0.unsign
857 #define ah_totalAdcIEvenPhase ah_Meas1.unsign
858 #define ah_totalAdcQOddPhase ah_Meas2.unsign
859 #define ah_totalAdcQEvenPhase ah_Meas3.unsign
860 #define ah_totalAdcDcOffsetIOddPhase ah_Meas0.sign
861 #define ah_totalAdcDcOffsetIEvenPhase ah_Meas1.sign
862 #define ah_totalAdcDcOffsetQOddPhase ah_Meas2.sign
863 #define ah_totalAdcDcOffsetQEvenPhase ah_Meas3.sign
864 union {
865 u32 unsign[AR5416_MAX_CHAINS];
866 int32_t sign[AR5416_MAX_CHAINS];
867 } ah_Meas0;
868 union {
869 u32 unsign[AR5416_MAX_CHAINS];
870 int32_t sign[AR5416_MAX_CHAINS];
871 } ah_Meas1;
872 union {
873 u32 unsign[AR5416_MAX_CHAINS];
874 int32_t sign[AR5416_MAX_CHAINS];
875 } ah_Meas2;
876 union {
877 u32 unsign[AR5416_MAX_CHAINS];
878 int32_t sign[AR5416_MAX_CHAINS];
879 } ah_Meas3;
880 u16 ah_CalSamples;
881
882 u32 ah_staId1Defaults;
883 u32 ah_miscMode;
884 enum {
885 AUTO_32KHZ,
886 USE_32KHZ,
887 DONT_USE_32KHZ,
888 } ah_enable32kHzClock;
889
890 /* RF */
891 u32 *ah_analogBank0Data;
892 u32 *ah_analogBank1Data;
893 u32 *ah_analogBank2Data;
894 u32 *ah_analogBank3Data;
895 u32 *ah_analogBank6Data;
896 u32 *ah_analogBank6TPCData;
897 u32 *ah_analogBank7Data;
898 u32 *ah_addac5416_21;
899 u32 *ah_bank6Temp;
900
901 int16_t ah_txPowerIndexOffset;
902 u32 ah_beaconInterval;
903 u32 ah_slottime;
904 u32 ah_acktimeout;
905 u32 ah_ctstimeout;
906 u32 ah_globaltxtimeout;
907 u8 ah_gBeaconRate;
908 u32 ah_gpioSelect;
909 u32 ah_polarity;
910 u32 ah_gpioBit;
911
912 /* ANI */
913 u32 ah_procPhyErr;
914 bool ah_hasHwPhyCounters;
915 u32 ah_aniPeriod;
916 struct ar5416AniState *ah_curani;
917 struct ar5416AniState ah_ani[255];
918 int ah_totalSizeDesired[5];
919 int ah_coarseHigh[5];
920 int ah_coarseLow[5];
921 int ah_firpwr[5];
922 enum ath9k_ani_cmd ah_ani_function;
923
924 u32 ah_intrTxqs;
925 bool ah_intrMitigation;
926 enum ath9k_ht_extprotspacing ah_extprotspacing;
927 u8 ah_txchainmask;
928 u8 ah_rxchainmask;
929
930 struct ar5416IniArray ah_iniModes;
931 struct ar5416IniArray ah_iniCommon;
932 struct ar5416IniArray ah_iniBank0;
933 struct ar5416IniArray ah_iniBB_RfGain;
934 struct ar5416IniArray ah_iniBank1;
935 struct ar5416IniArray ah_iniBank2;
936 struct ar5416IniArray ah_iniBank3;
937 struct ar5416IniArray ah_iniBank6;
938 struct ar5416IniArray ah_iniBank6TPC;
939 struct ar5416IniArray ah_iniBank7;
940 struct ar5416IniArray ah_iniAddac;
941 struct ar5416IniArray ah_iniPcieSerdes;
942 struct ar5416IniArray ah_iniModesAdditional;
943 struct ar5416IniArray ah_iniModesRxGain;
944 struct ar5416IniArray ah_iniModesTxGain;
945 /* To indicate EEPROM mapping used */
946 enum hal_eep_map ah_eep_map;
947 };
948 #define AH5416(_ah) ((struct ath_hal_5416 *)(_ah))
949
950 #define FREQ2FBIN(x, y) ((y) ? ((x) - 2300) : (((x) - 4800) / 5))
951
952 #define ar5416RfDetach(ah) do { \
953 if (AH5416(ah)->ah_rfHal.rfDetach != NULL) \
954 AH5416(ah)->ah_rfHal.rfDetach(ah); \
955 } while (0)
956
957 #define ath9k_hw_use_flash(_ah) \
958 (!(_ah->ah_flags & AH_USE_EEPROM))
959
960
961 #define DO_DELAY(x) do { \
962 if ((++(x) % 64) == 0) \
963 udelay(1); \
964 } while (0)
965
966 #define REG_WRITE_ARRAY(iniarray, column, regWr) do { \
967 int r; \
968 for (r = 0; r < ((iniarray)->ia_rows); r++) { \
969 REG_WRITE(ah, INI_RA((iniarray), (r), 0), \
970 INI_RA((iniarray), r, (column))); \
971 DO_DELAY(regWr); \
972 } \
973 } while (0)
974
975 #define BASE_ACTIVATE_DELAY 100
976 #define RTC_PLL_SETTLE_DELAY 1000
977 #define COEF_SCALE_S 24
978 #define HT40_CHANNEL_CENTER_SHIFT 10
979
980 #define AR5416_EEPROM_MAGIC_OFFSET 0x0
981
982 #define AR5416_EEPROM_S 2
983 #define AR5416_EEPROM_OFFSET 0x2000
984 #define AR5416_EEPROM_START_ADDR \
985 (AR_SREV_9100(ah)) ? 0x1fff1000 : 0x503f1200
986 #define AR5416_EEPROM_MAX 0xae0
987 #define ar5416_get_eep_ver(_ahp) \
988 (((_ahp)->ah_eeprom.def.baseEepHeader.version >> 12) & 0xF)
989 #define ar5416_get_eep_rev(_ahp) \
990 (((_ahp)->ah_eeprom.def.baseEepHeader.version) & 0xFFF)
991 #define ar5416_get_ntxchains(_txchainmask) \
992 (((_txchainmask >> 2) & 1) + \
993 ((_txchainmask >> 1) & 1) + (_txchainmask & 1))
994
995 /* EEPROM 4K bit map definations */
996 #define ar5416_get_eep4k_ver(_ahp) \
997 (((_ahp)->ah_eeprom.map4k.baseEepHeader.version >> 12) & 0xF)
998 #define ar5416_get_eep4k_rev(_ahp) \
999 (((_ahp)->ah_eeprom.map4k.baseEepHeader.version) & 0xFFF)
1000
1001
1002 #ifdef __BIG_ENDIAN
1003 #define AR5416_EEPROM_MAGIC 0x5aa5
1004 #else
1005 #define AR5416_EEPROM_MAGIC 0xa55a
1006 #endif
1007
1008 #define ATH9K_POW_SM(_r, _s) (((_r) & 0x3f) << (_s))
1009
1010 #define ATH9K_ANTENNA0_CHAINMASK 0x1
1011 #define ATH9K_ANTENNA1_CHAINMASK 0x2
1012
1013 #define ATH9K_NUM_DMA_DEBUG_REGS 8
1014 #define ATH9K_NUM_QUEUES 10
1015
1016 #define HAL_NOISE_IMMUNE_MAX 4
1017 #define HAL_SPUR_IMMUNE_MAX 7
1018 #define HAL_FIRST_STEP_MAX 2
1019
1020 #define ATH9K_ANI_OFDM_TRIG_HIGH 500
1021 #define ATH9K_ANI_OFDM_TRIG_LOW 200
1022 #define ATH9K_ANI_CCK_TRIG_HIGH 200
1023 #define ATH9K_ANI_CCK_TRIG_LOW 100
1024 #define ATH9K_ANI_NOISE_IMMUNE_LVL 4
1025 #define ATH9K_ANI_USE_OFDM_WEAK_SIG true
1026 #define ATH9K_ANI_CCK_WEAK_SIG_THR false
1027 #define ATH9K_ANI_SPUR_IMMUNE_LVL 7
1028 #define ATH9K_ANI_FIRSTEP_LVL 0
1029 #define ATH9K_ANI_RSSI_THR_HIGH 40
1030 #define ATH9K_ANI_RSSI_THR_LOW 7
1031 #define ATH9K_ANI_PERIOD 100
1032
1033 #define AR_GPIOD_MASK 0x00001FFF
1034 #define AR_GPIO_BIT(_gpio) (1 << (_gpio))
1035
1036 #define HAL_EP_RND(x, mul) \
1037 ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul))
1038 #define BEACON_RSSI(ahp) \
1039 HAL_EP_RND(ahp->ah_stats.ast_nodestats.ns_avgbrssi, \
1040 ATH9K_RSSI_EP_MULTIPLIER)
1041
1042 #define ah_mibStats ah_stats.ast_mibstats
1043
1044 #define AH_TIMEOUT 100000
1045 #define AH_TIME_QUANTUM 10
1046
1047 #define AR_KEYTABLE_SIZE 128
1048 #define POWER_UP_TIME 200000
1049
1050 #define EXT_ADDITIVE (0x8000)
1051 #define CTL_11A_EXT (CTL_11A | EXT_ADDITIVE)
1052 #define CTL_11G_EXT (CTL_11G | EXT_ADDITIVE)
1053 #define CTL_11B_EXT (CTL_11B | EXT_ADDITIVE)
1054
1055 #define SUB_NUM_CTL_MODES_AT_5G_40 2
1056 #define SUB_NUM_CTL_MODES_AT_2G_40 3
1057 #define SPUR_RSSI_THRESH 40
1058
1059 #define TU_TO_USEC(_tu) ((_tu) << 10)
1060
1061 #define CAB_TIMEOUT_VAL 10
1062 #define BEACON_TIMEOUT_VAL 10
1063 #define MIN_BEACON_TIMEOUT_VAL 1
1064 #define SLEEP_SLOP 3
1065
1066 #define CCK_SIFS_TIME 10
1067 #define CCK_PREAMBLE_BITS 144
1068 #define CCK_PLCP_BITS 48
1069
1070 #define OFDM_SIFS_TIME 16
1071 #define OFDM_PREAMBLE_TIME 20
1072 #define OFDM_PLCP_BITS 22
1073 #define OFDM_SYMBOL_TIME 4
1074
1075 #define OFDM_SIFS_TIME_HALF 32
1076 #define OFDM_PREAMBLE_TIME_HALF 40
1077 #define OFDM_PLCP_BITS_HALF 22
1078 #define OFDM_SYMBOL_TIME_HALF 8
1079
1080 #define OFDM_SIFS_TIME_QUARTER 64
1081 #define OFDM_PREAMBLE_TIME_QUARTER 80
1082 #define OFDM_PLCP_BITS_QUARTER 22
1083 #define OFDM_SYMBOL_TIME_QUARTER 16
1084
1085 u32 ath9k_hw_get_eeprom(struct ath_hal *ah,
1086 enum eeprom_param param);
1087
1088 #endif
Linux kernel - Deliverables
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