2 * Copyright (c) 2008 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/nl80211.h>
22 #define ATH_PCI_VERSION "0.1"
24 static char *dev_info
= "ath9k";
26 MODULE_AUTHOR("Atheros Communications");
27 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
28 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
29 MODULE_LICENSE("Dual BSD/GPL");
31 static struct pci_device_id ath_pci_id_table
[] __devinitdata
= {
32 { PCI_VDEVICE(ATHEROS
, 0x0023) }, /* PCI */
33 { PCI_VDEVICE(ATHEROS
, 0x0024) }, /* PCI-E */
34 { PCI_VDEVICE(ATHEROS
, 0x0027) }, /* PCI */
35 { PCI_VDEVICE(ATHEROS
, 0x0029) }, /* PCI */
36 { PCI_VDEVICE(ATHEROS
, 0x002A) }, /* PCI-E */
37 { PCI_VDEVICE(ATHEROS
, 0x002B) }, /* PCI-E */
41 static void ath_detach(struct ath_softc
*sc
);
43 /* return bus cachesize in 4B word units */
45 static void bus_read_cachesize(struct ath_softc
*sc
, int *csz
)
49 pci_read_config_byte(sc
->pdev
, PCI_CACHE_LINE_SIZE
, (u8
*)&u8tmp
);
53 * This check was put in to avoid "unplesant" consequences if
54 * the bootrom has not fully initialized all PCI devices.
55 * Sometimes the cache line size register is not set
59 *csz
= DEFAULT_CACHELINE
>> 2; /* Use the default size */
62 static void ath_setcurmode(struct ath_softc
*sc
, enum wireless_mode mode
)
64 sc
->cur_rate_table
= sc
->hw_rate_table
[mode
];
66 * All protection frames are transmited at 2Mb/s for
67 * 11g, otherwise at 1Mb/s.
68 * XXX select protection rate index from rate table.
70 sc
->sc_protrix
= (mode
== ATH9K_MODE_11G
? 1 : 0);
73 static enum wireless_mode
ath_chan2mode(struct ath9k_channel
*chan
)
75 if (chan
->chanmode
== CHANNEL_A
)
76 return ATH9K_MODE_11A
;
77 else if (chan
->chanmode
== CHANNEL_G
)
78 return ATH9K_MODE_11G
;
79 else if (chan
->chanmode
== CHANNEL_B
)
80 return ATH9K_MODE_11B
;
81 else if (chan
->chanmode
== CHANNEL_A_HT20
)
82 return ATH9K_MODE_11NA_HT20
;
83 else if (chan
->chanmode
== CHANNEL_G_HT20
)
84 return ATH9K_MODE_11NG_HT20
;
85 else if (chan
->chanmode
== CHANNEL_A_HT40PLUS
)
86 return ATH9K_MODE_11NA_HT40PLUS
;
87 else if (chan
->chanmode
== CHANNEL_A_HT40MINUS
)
88 return ATH9K_MODE_11NA_HT40MINUS
;
89 else if (chan
->chanmode
== CHANNEL_G_HT40PLUS
)
90 return ATH9K_MODE_11NG_HT40PLUS
;
91 else if (chan
->chanmode
== CHANNEL_G_HT40MINUS
)
92 return ATH9K_MODE_11NG_HT40MINUS
;
94 WARN_ON(1); /* should not get here */
96 return ATH9K_MODE_11B
;
99 static void ath_update_txpow(struct ath_softc
*sc
)
101 struct ath_hal
*ah
= sc
->sc_ah
;
104 if (sc
->sc_curtxpow
!= sc
->sc_config
.txpowlimit
) {
105 ath9k_hw_set_txpowerlimit(ah
, sc
->sc_config
.txpowlimit
);
106 /* read back in case value is clamped */
107 ath9k_hw_getcapability(ah
, ATH9K_CAP_TXPOW
, 1, &txpow
);
108 sc
->sc_curtxpow
= txpow
;
112 static u8
parse_mpdudensity(u8 mpdudensity
)
115 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
116 * 0 for no restriction
125 switch (mpdudensity
) {
131 /* Our lower layer calculations limit our precision to
147 static void ath_setup_rates(struct ath_softc
*sc
, enum ieee80211_band band
)
149 struct ath_rate_table
*rate_table
= NULL
;
150 struct ieee80211_supported_band
*sband
;
151 struct ieee80211_rate
*rate
;
155 case IEEE80211_BAND_2GHZ
:
156 rate_table
= sc
->hw_rate_table
[ATH9K_MODE_11G
];
158 case IEEE80211_BAND_5GHZ
:
159 rate_table
= sc
->hw_rate_table
[ATH9K_MODE_11A
];
165 if (rate_table
== NULL
)
168 sband
= &sc
->sbands
[band
];
169 rate
= sc
->rates
[band
];
171 if (rate_table
->rate_cnt
> ATH_RATE_MAX
)
172 maxrates
= ATH_RATE_MAX
;
174 maxrates
= rate_table
->rate_cnt
;
176 for (i
= 0; i
< maxrates
; i
++) {
177 rate
[i
].bitrate
= rate_table
->info
[i
].ratekbps
/ 100;
178 rate
[i
].hw_value
= rate_table
->info
[i
].ratecode
;
180 DPRINTF(sc
, ATH_DBG_CONFIG
, "Rate: %2dMbps, ratecode: %2d\n",
181 rate
[i
].bitrate
/ 10, rate
[i
].hw_value
);
185 static int ath_setup_channels(struct ath_softc
*sc
)
187 struct ath_hal
*ah
= sc
->sc_ah
;
188 int nchan
, i
, a
= 0, b
= 0;
189 u8 regclassids
[ATH_REGCLASSIDS_MAX
];
191 struct ieee80211_supported_band
*band_2ghz
;
192 struct ieee80211_supported_band
*band_5ghz
;
193 struct ieee80211_channel
*chan_2ghz
;
194 struct ieee80211_channel
*chan_5ghz
;
195 struct ath9k_channel
*c
;
197 /* Fill in ah->ah_channels */
198 if (!ath9k_regd_init_channels(ah
, ATH_CHAN_MAX
, (u32
*)&nchan
,
199 regclassids
, ATH_REGCLASSIDS_MAX
,
200 &nregclass
, CTRY_DEFAULT
, false, 1)) {
201 u32 rd
= ah
->ah_currentRD
;
202 DPRINTF(sc
, ATH_DBG_FATAL
,
203 "Unable to collect channel list; "
204 "regdomain likely %u country code %u\n",
209 band_2ghz
= &sc
->sbands
[IEEE80211_BAND_2GHZ
];
210 band_5ghz
= &sc
->sbands
[IEEE80211_BAND_5GHZ
];
211 chan_2ghz
= sc
->channels
[IEEE80211_BAND_2GHZ
];
212 chan_5ghz
= sc
->channels
[IEEE80211_BAND_5GHZ
];
214 for (i
= 0; i
< nchan
; i
++) {
215 c
= &ah
->ah_channels
[i
];
216 if (IS_CHAN_2GHZ(c
)) {
217 chan_2ghz
[a
].band
= IEEE80211_BAND_2GHZ
;
218 chan_2ghz
[a
].center_freq
= c
->channel
;
219 chan_2ghz
[a
].max_power
= c
->maxTxPower
;
221 if (c
->privFlags
& CHANNEL_DISALLOW_ADHOC
)
222 chan_2ghz
[a
].flags
|= IEEE80211_CHAN_NO_IBSS
;
223 if (c
->channelFlags
& CHANNEL_PASSIVE
)
224 chan_2ghz
[a
].flags
|= IEEE80211_CHAN_PASSIVE_SCAN
;
226 band_2ghz
->n_channels
= ++a
;
228 DPRINTF(sc
, ATH_DBG_CONFIG
, "2MHz channel: %d, "
229 "channelFlags: 0x%x\n",
230 c
->channel
, c
->channelFlags
);
231 } else if (IS_CHAN_5GHZ(c
)) {
232 chan_5ghz
[b
].band
= IEEE80211_BAND_5GHZ
;
233 chan_5ghz
[b
].center_freq
= c
->channel
;
234 chan_5ghz
[b
].max_power
= c
->maxTxPower
;
236 if (c
->privFlags
& CHANNEL_DISALLOW_ADHOC
)
237 chan_5ghz
[b
].flags
|= IEEE80211_CHAN_NO_IBSS
;
238 if (c
->channelFlags
& CHANNEL_PASSIVE
)
239 chan_5ghz
[b
].flags
|= IEEE80211_CHAN_PASSIVE_SCAN
;
241 band_5ghz
->n_channels
= ++b
;
243 DPRINTF(sc
, ATH_DBG_CONFIG
, "5MHz channel: %d, "
244 "channelFlags: 0x%x\n",
245 c
->channel
, c
->channelFlags
);
253 * Set/change channels. If the channel is really being changed, it's done
254 * by reseting the chip. To accomplish this we must first cleanup any pending
255 * DMA, then restart stuff.
257 static int ath_set_channel(struct ath_softc
*sc
, struct ath9k_channel
*hchan
)
259 struct ath_hal
*ah
= sc
->sc_ah
;
260 bool fastcc
= true, stopped
;
262 if (sc
->sc_flags
& SC_OP_INVALID
)
265 if (hchan
->channel
!= sc
->sc_ah
->ah_curchan
->channel
||
266 hchan
->channelFlags
!= sc
->sc_ah
->ah_curchan
->channelFlags
||
267 (sc
->sc_flags
& SC_OP_CHAINMASK_UPDATE
) ||
268 (sc
->sc_flags
& SC_OP_FULL_RESET
)) {
271 * This is only performed if the channel settings have
274 * To switch channels clear any pending DMA operations;
275 * wait long enough for the RX fifo to drain, reset the
276 * hardware at the new frequency, and then re-enable
277 * the relevant bits of the h/w.
279 ath9k_hw_set_interrupts(ah
, 0);
280 ath_draintxq(sc
, false);
281 stopped
= ath_stoprecv(sc
);
283 /* XXX: do not flush receive queue here. We don't want
284 * to flush data frames already in queue because of
285 * changing channel. */
287 if (!stopped
|| (sc
->sc_flags
& SC_OP_FULL_RESET
))
290 DPRINTF(sc
, ATH_DBG_CONFIG
,
291 "(%u MHz) -> (%u MHz), cflags:%x, chanwidth: %d\n",
292 sc
->sc_ah
->ah_curchan
->channel
,
293 hchan
->channel
, hchan
->channelFlags
, sc
->tx_chan_width
);
295 spin_lock_bh(&sc
->sc_resetlock
);
296 if (!ath9k_hw_reset(ah
, hchan
, sc
->tx_chan_width
,
297 sc
->sc_tx_chainmask
, sc
->sc_rx_chainmask
,
298 sc
->sc_ht_extprotspacing
, fastcc
, &status
)) {
299 DPRINTF(sc
, ATH_DBG_FATAL
,
300 "Unable to reset channel %u (%uMhz) "
301 "flags 0x%x hal status %u\n",
302 ath9k_hw_mhz2ieee(ah
, hchan
->channel
,
303 hchan
->channelFlags
),
304 hchan
->channel
, hchan
->channelFlags
, status
);
305 spin_unlock_bh(&sc
->sc_resetlock
);
308 spin_unlock_bh(&sc
->sc_resetlock
);
310 sc
->sc_flags
&= ~SC_OP_CHAINMASK_UPDATE
;
311 sc
->sc_flags
&= ~SC_OP_FULL_RESET
;
313 if (ath_startrecv(sc
) != 0) {
314 DPRINTF(sc
, ATH_DBG_FATAL
,
315 "Unable to restart recv logic\n");
319 ath_setcurmode(sc
, ath_chan2mode(hchan
));
320 ath_update_txpow(sc
);
321 ath9k_hw_set_interrupts(ah
, sc
->sc_imask
);
327 * This routine performs the periodic noise floor calibration function
328 * that is used to adjust and optimize the chip performance. This
329 * takes environmental changes (location, temperature) into account.
330 * When the task is complete, it reschedules itself depending on the
331 * appropriate interval that was calculated.
333 static void ath_ani_calibrate(unsigned long data
)
335 struct ath_softc
*sc
;
337 bool longcal
= false;
338 bool shortcal
= false;
339 bool aniflag
= false;
340 unsigned int timestamp
= jiffies_to_msecs(jiffies
);
343 sc
= (struct ath_softc
*)data
;
347 * don't calibrate when we're scanning.
348 * we are most likely not on our home channel.
350 if (sc
->rx
.rxfilter
& FIF_BCN_PRBRESP_PROMISC
)
353 /* Long calibration runs independently of short calibration. */
354 if ((timestamp
- sc
->sc_ani
.sc_longcal_timer
) >= ATH_LONG_CALINTERVAL
) {
356 DPRINTF(sc
, ATH_DBG_ANI
, "longcal @%lu\n", jiffies
);
357 sc
->sc_ani
.sc_longcal_timer
= timestamp
;
360 /* Short calibration applies only while sc_caldone is false */
361 if (!sc
->sc_ani
.sc_caldone
) {
362 if ((timestamp
- sc
->sc_ani
.sc_shortcal_timer
) >=
363 ATH_SHORT_CALINTERVAL
) {
365 DPRINTF(sc
, ATH_DBG_ANI
, "shortcal @%lu\n", jiffies
);
366 sc
->sc_ani
.sc_shortcal_timer
= timestamp
;
367 sc
->sc_ani
.sc_resetcal_timer
= timestamp
;
370 if ((timestamp
- sc
->sc_ani
.sc_resetcal_timer
) >=
371 ATH_RESTART_CALINTERVAL
) {
372 ath9k_hw_reset_calvalid(ah
, ah
->ah_curchan
,
373 &sc
->sc_ani
.sc_caldone
);
374 if (sc
->sc_ani
.sc_caldone
)
375 sc
->sc_ani
.sc_resetcal_timer
= timestamp
;
379 /* Verify whether we must check ANI */
380 if ((timestamp
- sc
->sc_ani
.sc_checkani_timer
) >=
381 ATH_ANI_POLLINTERVAL
) {
383 sc
->sc_ani
.sc_checkani_timer
= timestamp
;
386 /* Skip all processing if there's nothing to do. */
387 if (longcal
|| shortcal
|| aniflag
) {
388 /* Call ANI routine if necessary */
390 ath9k_hw_ani_monitor(ah
, &sc
->sc_halstats
,
393 /* Perform calibration if necessary */
394 if (longcal
|| shortcal
) {
395 bool iscaldone
= false;
397 if (ath9k_hw_calibrate(ah
, ah
->ah_curchan
,
398 sc
->sc_rx_chainmask
, longcal
,
401 sc
->sc_ani
.sc_noise_floor
=
402 ath9k_hw_getchan_noise(ah
,
405 DPRINTF(sc
, ATH_DBG_ANI
,
406 "calibrate chan %u/%x nf: %d\n",
407 ah
->ah_curchan
->channel
,
408 ah
->ah_curchan
->channelFlags
,
409 sc
->sc_ani
.sc_noise_floor
);
411 DPRINTF(sc
, ATH_DBG_ANY
,
412 "calibrate chan %u/%x failed\n",
413 ah
->ah_curchan
->channel
,
414 ah
->ah_curchan
->channelFlags
);
416 sc
->sc_ani
.sc_caldone
= iscaldone
;
421 * Set timer interval based on previous results.
422 * The interval must be the shortest necessary to satisfy ANI,
423 * short calibration and long calibration.
425 cal_interval
= ATH_LONG_CALINTERVAL
;
426 if (sc
->sc_ah
->ah_config
.enable_ani
)
427 cal_interval
= min(cal_interval
, (u32
)ATH_ANI_POLLINTERVAL
);
428 if (!sc
->sc_ani
.sc_caldone
)
429 cal_interval
= min(cal_interval
, (u32
)ATH_SHORT_CALINTERVAL
);
431 mod_timer(&sc
->sc_ani
.timer
, jiffies
+ msecs_to_jiffies(cal_interval
));
435 * Update tx/rx chainmask. For legacy association,
436 * hard code chainmask to 1x1, for 11n association, use
437 * the chainmask configuration.
439 static void ath_update_chainmask(struct ath_softc
*sc
, int is_ht
)
441 sc
->sc_flags
|= SC_OP_CHAINMASK_UPDATE
;
443 sc
->sc_tx_chainmask
= sc
->sc_ah
->ah_caps
.tx_chainmask
;
444 sc
->sc_rx_chainmask
= sc
->sc_ah
->ah_caps
.rx_chainmask
;
446 sc
->sc_tx_chainmask
= 1;
447 sc
->sc_rx_chainmask
= 1;
450 DPRINTF(sc
, ATH_DBG_CONFIG
, "tx chmask: %d, rx chmask: %d\n",
451 sc
->sc_tx_chainmask
, sc
->sc_rx_chainmask
);
454 static void ath_node_attach(struct ath_softc
*sc
, struct ieee80211_sta
*sta
)
458 an
= (struct ath_node
*)sta
->drv_priv
;
460 if (sc
->sc_flags
& SC_OP_TXAGGR
)
461 ath_tx_node_init(sc
, an
);
463 an
->maxampdu
= 1 << (IEEE80211_HTCAP_MAXRXAMPDU_FACTOR
+
464 sta
->ht_cap
.ampdu_factor
);
465 an
->mpdudensity
= parse_mpdudensity(sta
->ht_cap
.ampdu_density
);
468 static void ath_node_detach(struct ath_softc
*sc
, struct ieee80211_sta
*sta
)
470 struct ath_node
*an
= (struct ath_node
*)sta
->drv_priv
;
472 if (sc
->sc_flags
& SC_OP_TXAGGR
)
473 ath_tx_node_cleanup(sc
, an
);
476 static void ath9k_tasklet(unsigned long data
)
478 struct ath_softc
*sc
= (struct ath_softc
*)data
;
479 u32 status
= sc
->sc_intrstatus
;
481 if (status
& ATH9K_INT_FATAL
) {
482 /* need a chip reset */
483 ath_reset(sc
, false);
488 (ATH9K_INT_RX
| ATH9K_INT_RXEOL
| ATH9K_INT_RXORN
)) {
489 spin_lock_bh(&sc
->rx
.rxflushlock
);
490 ath_rx_tasklet(sc
, 0);
491 spin_unlock_bh(&sc
->rx
.rxflushlock
);
493 /* XXX: optimize this */
494 if (status
& ATH9K_INT_TX
)
498 /* re-enable hardware interrupt */
499 ath9k_hw_set_interrupts(sc
->sc_ah
, sc
->sc_imask
);
502 static irqreturn_t
ath_isr(int irq
, void *dev
)
504 struct ath_softc
*sc
= dev
;
505 struct ath_hal
*ah
= sc
->sc_ah
;
506 enum ath9k_int status
;
510 if (sc
->sc_flags
& SC_OP_INVALID
) {
512 * The hardware is not ready/present, don't
513 * touch anything. Note this can happen early
514 * on if the IRQ is shared.
518 if (!ath9k_hw_intrpend(ah
)) { /* shared irq, not for us */
523 * Figure out the reason(s) for the interrupt. Note
524 * that the hal returns a pseudo-ISR that may include
525 * bits we haven't explicitly enabled so we mask the
526 * value to insure we only process bits we requested.
528 ath9k_hw_getisr(ah
, &status
); /* NB: clears ISR too */
530 status
&= sc
->sc_imask
; /* discard unasked-for bits */
533 * If there are no status bits set, then this interrupt was not
534 * for me (should have been caught above).
539 sc
->sc_intrstatus
= status
;
541 if (status
& ATH9K_INT_FATAL
) {
542 /* need a chip reset */
544 } else if (status
& ATH9K_INT_RXORN
) {
545 /* need a chip reset */
548 if (status
& ATH9K_INT_SWBA
) {
549 /* schedule a tasklet for beacon handling */
550 tasklet_schedule(&sc
->bcon_tasklet
);
552 if (status
& ATH9K_INT_RXEOL
) {
554 * NB: the hardware should re-read the link when
555 * RXE bit is written, but it doesn't work
556 * at least on older hardware revs.
561 if (status
& ATH9K_INT_TXURN
)
562 /* bump tx trigger level */
563 ath9k_hw_updatetxtriglevel(ah
, true);
564 /* XXX: optimize this */
565 if (status
& ATH9K_INT_RX
)
567 if (status
& ATH9K_INT_TX
)
569 if (status
& ATH9K_INT_BMISS
)
571 /* carrier sense timeout */
572 if (status
& ATH9K_INT_CST
)
574 if (status
& ATH9K_INT_MIB
) {
576 * Disable interrupts until we service the MIB
577 * interrupt; otherwise it will continue to
580 ath9k_hw_set_interrupts(ah
, 0);
582 * Let the hal handle the event. We assume
583 * it will clear whatever condition caused
586 ath9k_hw_procmibevent(ah
, &sc
->sc_halstats
);
587 ath9k_hw_set_interrupts(ah
, sc
->sc_imask
);
589 if (status
& ATH9K_INT_TIM_TIMER
) {
590 if (!(ah
->ah_caps
.hw_caps
&
591 ATH9K_HW_CAP_AUTOSLEEP
)) {
592 /* Clear RxAbort bit so that we can
594 ath9k_hw_setrxabort(ah
, 0);
601 ath_debug_stat_interrupt(sc
, status
);
604 /* turn off every interrupt except SWBA */
605 ath9k_hw_set_interrupts(ah
, (sc
->sc_imask
& ATH9K_INT_SWBA
));
606 tasklet_schedule(&sc
->intr_tq
);
612 static int ath_get_channel(struct ath_softc
*sc
,
613 struct ieee80211_channel
*chan
)
617 for (i
= 0; i
< sc
->sc_ah
->ah_nchan
; i
++) {
618 if (sc
->sc_ah
->ah_channels
[i
].channel
== chan
->center_freq
)
625 static u32
ath_get_extchanmode(struct ath_softc
*sc
,
626 struct ieee80211_channel
*chan
,
627 enum nl80211_channel_type channel_type
)
631 switch (chan
->band
) {
632 case IEEE80211_BAND_2GHZ
:
633 switch(channel_type
) {
634 case NL80211_CHAN_NO_HT
:
635 case NL80211_CHAN_HT20
:
636 chanmode
= CHANNEL_G_HT20
;
638 case NL80211_CHAN_HT40PLUS
:
639 chanmode
= CHANNEL_G_HT40PLUS
;
641 case NL80211_CHAN_HT40MINUS
:
642 chanmode
= CHANNEL_G_HT40MINUS
;
646 case IEEE80211_BAND_5GHZ
:
647 switch(channel_type
) {
648 case NL80211_CHAN_NO_HT
:
649 case NL80211_CHAN_HT20
:
650 chanmode
= CHANNEL_A_HT20
;
652 case NL80211_CHAN_HT40PLUS
:
653 chanmode
= CHANNEL_A_HT40PLUS
;
655 case NL80211_CHAN_HT40MINUS
:
656 chanmode
= CHANNEL_A_HT40MINUS
;
667 static int ath_keyset(struct ath_softc
*sc
, u16 keyix
,
668 struct ath9k_keyval
*hk
, const u8 mac
[ETH_ALEN
])
672 status
= ath9k_hw_set_keycache_entry(sc
->sc_ah
,
673 keyix
, hk
, mac
, false);
675 return status
!= false;
678 static int ath_setkey_tkip(struct ath_softc
*sc
, u16 keyix
, const u8
*key
,
679 struct ath9k_keyval
*hk
,
685 key_txmic
= key
+ NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY
;
686 key_rxmic
= key
+ NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY
;
689 /* Group key installation */
690 memcpy(hk
->kv_mic
, key_rxmic
, sizeof(hk
->kv_mic
));
691 return ath_keyset(sc
, keyix
, hk
, addr
);
693 if (!sc
->sc_splitmic
) {
695 * data key goes at first index,
696 * the hal handles the MIC keys at index+64.
698 memcpy(hk
->kv_mic
, key_rxmic
, sizeof(hk
->kv_mic
));
699 memcpy(hk
->kv_txmic
, key_txmic
, sizeof(hk
->kv_txmic
));
700 return ath_keyset(sc
, keyix
, hk
, addr
);
703 * TX key goes at first index, RX key at +32.
704 * The hal handles the MIC keys at index+64.
706 memcpy(hk
->kv_mic
, key_txmic
, sizeof(hk
->kv_mic
));
707 if (!ath_keyset(sc
, keyix
, hk
, NULL
)) {
708 /* Txmic entry failed. No need to proceed further */
709 DPRINTF(sc
, ATH_DBG_KEYCACHE
,
710 "Setting TX MIC Key Failed\n");
714 memcpy(hk
->kv_mic
, key_rxmic
, sizeof(hk
->kv_mic
));
715 /* XXX delete tx key on failure? */
716 return ath_keyset(sc
, keyix
+ 32, hk
, addr
);
719 static int ath_reserve_key_cache_slot_tkip(struct ath_softc
*sc
)
723 for (i
= IEEE80211_WEP_NKID
; i
< sc
->sc_keymax
/ 2; i
++) {
724 if (test_bit(i
, sc
->sc_keymap
) ||
725 test_bit(i
+ 64, sc
->sc_keymap
))
726 continue; /* At least one part of TKIP key allocated */
727 if (sc
->sc_splitmic
&&
728 (test_bit(i
+ 32, sc
->sc_keymap
) ||
729 test_bit(i
+ 64 + 32, sc
->sc_keymap
)))
730 continue; /* At least one part of TKIP key allocated */
732 /* Found a free slot for a TKIP key */
738 static int ath_reserve_key_cache_slot(struct ath_softc
*sc
)
742 /* First, try to find slots that would not be available for TKIP. */
743 if (sc
->sc_splitmic
) {
744 for (i
= IEEE80211_WEP_NKID
; i
< sc
->sc_keymax
/ 4; i
++) {
745 if (!test_bit(i
, sc
->sc_keymap
) &&
746 (test_bit(i
+ 32, sc
->sc_keymap
) ||
747 test_bit(i
+ 64, sc
->sc_keymap
) ||
748 test_bit(i
+ 64 + 32, sc
->sc_keymap
)))
750 if (!test_bit(i
+ 32, sc
->sc_keymap
) &&
751 (test_bit(i
, sc
->sc_keymap
) ||
752 test_bit(i
+ 64, sc
->sc_keymap
) ||
753 test_bit(i
+ 64 + 32, sc
->sc_keymap
)))
755 if (!test_bit(i
+ 64, sc
->sc_keymap
) &&
756 (test_bit(i
, sc
->sc_keymap
) ||
757 test_bit(i
+ 32, sc
->sc_keymap
) ||
758 test_bit(i
+ 64 + 32, sc
->sc_keymap
)))
760 if (!test_bit(i
+ 64 + 32, sc
->sc_keymap
) &&
761 (test_bit(i
, sc
->sc_keymap
) ||
762 test_bit(i
+ 32, sc
->sc_keymap
) ||
763 test_bit(i
+ 64, sc
->sc_keymap
)))
767 for (i
= IEEE80211_WEP_NKID
; i
< sc
->sc_keymax
/ 2; i
++) {
768 if (!test_bit(i
, sc
->sc_keymap
) &&
769 test_bit(i
+ 64, sc
->sc_keymap
))
771 if (test_bit(i
, sc
->sc_keymap
) &&
772 !test_bit(i
+ 64, sc
->sc_keymap
))
777 /* No partially used TKIP slots, pick any available slot */
778 for (i
= IEEE80211_WEP_NKID
; i
< sc
->sc_keymax
; i
++) {
779 /* Do not allow slots that could be needed for TKIP group keys
780 * to be used. This limitation could be removed if we know that
781 * TKIP will not be used. */
782 if (i
>= 64 && i
< 64 + IEEE80211_WEP_NKID
)
784 if (sc
->sc_splitmic
) {
785 if (i
>= 32 && i
< 32 + IEEE80211_WEP_NKID
)
787 if (i
>= 64 + 32 && i
< 64 + 32 + IEEE80211_WEP_NKID
)
791 if (!test_bit(i
, sc
->sc_keymap
))
792 return i
; /* Found a free slot for a key */
795 /* No free slot found */
799 static int ath_key_config(struct ath_softc
*sc
,
801 struct ieee80211_key_conf
*key
)
803 struct ath9k_keyval hk
;
804 const u8
*mac
= NULL
;
808 memset(&hk
, 0, sizeof(hk
));
812 hk
.kv_type
= ATH9K_CIPHER_WEP
;
815 hk
.kv_type
= ATH9K_CIPHER_TKIP
;
818 hk
.kv_type
= ATH9K_CIPHER_AES_CCM
;
824 hk
.kv_len
= key
->keylen
;
825 memcpy(hk
.kv_val
, key
->key
, key
->keylen
);
827 if (!(key
->flags
& IEEE80211_KEY_FLAG_PAIRWISE
)) {
828 /* For now, use the default keys for broadcast keys. This may
829 * need to change with virtual interfaces. */
831 } else if (key
->keyidx
) {
832 struct ieee80211_vif
*vif
;
835 vif
= sc
->sc_vaps
[0];
836 if (vif
->type
!= NL80211_IFTYPE_AP
) {
837 /* Only keyidx 0 should be used with unicast key, but
838 * allow this for client mode for now. */
844 if (key
->alg
== ALG_TKIP
)
845 idx
= ath_reserve_key_cache_slot_tkip(sc
);
847 idx
= ath_reserve_key_cache_slot(sc
);
849 return -EIO
; /* no free key cache entries */
852 if (key
->alg
== ALG_TKIP
)
853 ret
= ath_setkey_tkip(sc
, idx
, key
->key
, &hk
, mac
);
855 ret
= ath_keyset(sc
, idx
, &hk
, mac
);
860 set_bit(idx
, sc
->sc_keymap
);
861 if (key
->alg
== ALG_TKIP
) {
862 set_bit(idx
+ 64, sc
->sc_keymap
);
863 if (sc
->sc_splitmic
) {
864 set_bit(idx
+ 32, sc
->sc_keymap
);
865 set_bit(idx
+ 64 + 32, sc
->sc_keymap
);
872 static void ath_key_delete(struct ath_softc
*sc
, struct ieee80211_key_conf
*key
)
874 ath9k_hw_keyreset(sc
->sc_ah
, key
->hw_key_idx
);
875 if (key
->hw_key_idx
< IEEE80211_WEP_NKID
)
878 clear_bit(key
->hw_key_idx
, sc
->sc_keymap
);
879 if (key
->alg
!= ALG_TKIP
)
882 clear_bit(key
->hw_key_idx
+ 64, sc
->sc_keymap
);
883 if (sc
->sc_splitmic
) {
884 clear_bit(key
->hw_key_idx
+ 32, sc
->sc_keymap
);
885 clear_bit(key
->hw_key_idx
+ 64 + 32, sc
->sc_keymap
);
889 static void setup_ht_cap(struct ieee80211_sta_ht_cap
*ht_info
)
891 #define ATH9K_HT_CAP_MAXRXAMPDU_65536 0x3 /* 2 ^ 16 */
892 #define ATH9K_HT_CAP_MPDUDENSITY_8 0x6 /* 8 usec */
894 ht_info
->ht_supported
= true;
895 ht_info
->cap
= IEEE80211_HT_CAP_SUP_WIDTH_20_40
|
896 IEEE80211_HT_CAP_SM_PS
|
897 IEEE80211_HT_CAP_SGI_40
|
898 IEEE80211_HT_CAP_DSSSCCK40
;
900 ht_info
->ampdu_factor
= ATH9K_HT_CAP_MAXRXAMPDU_65536
;
901 ht_info
->ampdu_density
= ATH9K_HT_CAP_MPDUDENSITY_8
;
902 /* set up supported mcs set */
903 memset(&ht_info
->mcs
, 0, sizeof(ht_info
->mcs
));
904 ht_info
->mcs
.rx_mask
[0] = 0xff;
905 ht_info
->mcs
.rx_mask
[1] = 0xff;
906 ht_info
->mcs
.tx_params
= IEEE80211_HT_MCS_TX_DEFINED
;
909 static void ath9k_bss_assoc_info(struct ath_softc
*sc
,
910 struct ieee80211_vif
*vif
,
911 struct ieee80211_bss_conf
*bss_conf
)
913 struct ath_vap
*avp
= (void *)vif
->drv_priv
;
915 if (bss_conf
->assoc
) {
916 DPRINTF(sc
, ATH_DBG_CONFIG
, "Bss Info ASSOC %d, bssid: %pM\n",
917 bss_conf
->aid
, sc
->sc_curbssid
);
919 /* New association, store aid */
920 if (avp
->av_opmode
== NL80211_IFTYPE_STATION
) {
921 sc
->sc_curaid
= bss_conf
->aid
;
922 ath9k_hw_write_associd(sc
->sc_ah
, sc
->sc_curbssid
,
926 /* Configure the beacon */
927 ath_beacon_config(sc
, 0);
928 sc
->sc_flags
|= SC_OP_BEACONS
;
930 /* Reset rssi stats */
931 sc
->sc_halstats
.ns_avgbrssi
= ATH_RSSI_DUMMY_MARKER
;
932 sc
->sc_halstats
.ns_avgrssi
= ATH_RSSI_DUMMY_MARKER
;
933 sc
->sc_halstats
.ns_avgtxrssi
= ATH_RSSI_DUMMY_MARKER
;
934 sc
->sc_halstats
.ns_avgtxrate
= ATH_RATE_DUMMY_MARKER
;
937 mod_timer(&sc
->sc_ani
.timer
,
938 jiffies
+ msecs_to_jiffies(ATH_ANI_POLLINTERVAL
));
941 DPRINTF(sc
, ATH_DBG_CONFIG
, "Bss Info DISSOC\n");
946 /********************************/
948 /********************************/
950 static void ath_led_brightness(struct led_classdev
*led_cdev
,
951 enum led_brightness brightness
)
953 struct ath_led
*led
= container_of(led_cdev
, struct ath_led
, led_cdev
);
954 struct ath_softc
*sc
= led
->sc
;
956 switch (brightness
) {
958 if (led
->led_type
== ATH_LED_ASSOC
||
959 led
->led_type
== ATH_LED_RADIO
)
960 sc
->sc_flags
&= ~SC_OP_LED_ASSOCIATED
;
961 ath9k_hw_set_gpio(sc
->sc_ah
, ATH_LED_PIN
,
962 (led
->led_type
== ATH_LED_RADIO
) ? 1 :
963 !!(sc
->sc_flags
& SC_OP_LED_ASSOCIATED
));
966 if (led
->led_type
== ATH_LED_ASSOC
)
967 sc
->sc_flags
|= SC_OP_LED_ASSOCIATED
;
968 ath9k_hw_set_gpio(sc
->sc_ah
, ATH_LED_PIN
, 0);
975 static int ath_register_led(struct ath_softc
*sc
, struct ath_led
*led
,
981 led
->led_cdev
.name
= led
->name
;
982 led
->led_cdev
.default_trigger
= trigger
;
983 led
->led_cdev
.brightness_set
= ath_led_brightness
;
985 ret
= led_classdev_register(wiphy_dev(sc
->hw
->wiphy
), &led
->led_cdev
);
987 DPRINTF(sc
, ATH_DBG_FATAL
,
988 "Failed to register led:%s", led
->name
);
994 static void ath_unregister_led(struct ath_led
*led
)
996 if (led
->registered
) {
997 led_classdev_unregister(&led
->led_cdev
);
1002 static void ath_deinit_leds(struct ath_softc
*sc
)
1004 ath_unregister_led(&sc
->assoc_led
);
1005 sc
->sc_flags
&= ~SC_OP_LED_ASSOCIATED
;
1006 ath_unregister_led(&sc
->tx_led
);
1007 ath_unregister_led(&sc
->rx_led
);
1008 ath_unregister_led(&sc
->radio_led
);
1009 ath9k_hw_set_gpio(sc
->sc_ah
, ATH_LED_PIN
, 1);
1012 static void ath_init_leds(struct ath_softc
*sc
)
1017 /* Configure gpio 1 for output */
1018 ath9k_hw_cfg_output(sc
->sc_ah
, ATH_LED_PIN
,
1019 AR_GPIO_OUTPUT_MUX_AS_OUTPUT
);
1020 /* LED off, active low */
1021 ath9k_hw_set_gpio(sc
->sc_ah
, ATH_LED_PIN
, 1);
1023 trigger
= ieee80211_get_radio_led_name(sc
->hw
);
1024 snprintf(sc
->radio_led
.name
, sizeof(sc
->radio_led
.name
),
1025 "ath9k-%s:radio", wiphy_name(sc
->hw
->wiphy
));
1026 ret
= ath_register_led(sc
, &sc
->radio_led
, trigger
);
1027 sc
->radio_led
.led_type
= ATH_LED_RADIO
;
1031 trigger
= ieee80211_get_assoc_led_name(sc
->hw
);
1032 snprintf(sc
->assoc_led
.name
, sizeof(sc
->assoc_led
.name
),
1033 "ath9k-%s:assoc", wiphy_name(sc
->hw
->wiphy
));
1034 ret
= ath_register_led(sc
, &sc
->assoc_led
, trigger
);
1035 sc
->assoc_led
.led_type
= ATH_LED_ASSOC
;
1039 trigger
= ieee80211_get_tx_led_name(sc
->hw
);
1040 snprintf(sc
->tx_led
.name
, sizeof(sc
->tx_led
.name
),
1041 "ath9k-%s:tx", wiphy_name(sc
->hw
->wiphy
));
1042 ret
= ath_register_led(sc
, &sc
->tx_led
, trigger
);
1043 sc
->tx_led
.led_type
= ATH_LED_TX
;
1047 trigger
= ieee80211_get_rx_led_name(sc
->hw
);
1048 snprintf(sc
->rx_led
.name
, sizeof(sc
->rx_led
.name
),
1049 "ath9k-%s:rx", wiphy_name(sc
->hw
->wiphy
));
1050 ret
= ath_register_led(sc
, &sc
->rx_led
, trigger
);
1051 sc
->rx_led
.led_type
= ATH_LED_RX
;
1058 ath_deinit_leds(sc
);
1061 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1063 /*******************/
1065 /*******************/
1067 static void ath_radio_enable(struct ath_softc
*sc
)
1069 struct ath_hal
*ah
= sc
->sc_ah
;
1072 spin_lock_bh(&sc
->sc_resetlock
);
1073 if (!ath9k_hw_reset(ah
, ah
->ah_curchan
,
1075 sc
->sc_tx_chainmask
,
1076 sc
->sc_rx_chainmask
,
1077 sc
->sc_ht_extprotspacing
,
1079 DPRINTF(sc
, ATH_DBG_FATAL
,
1080 "Unable to reset channel %u (%uMhz) "
1081 "flags 0x%x hal status %u\n",
1082 ath9k_hw_mhz2ieee(ah
,
1083 ah
->ah_curchan
->channel
,
1084 ah
->ah_curchan
->channelFlags
),
1085 ah
->ah_curchan
->channel
,
1086 ah
->ah_curchan
->channelFlags
, status
);
1088 spin_unlock_bh(&sc
->sc_resetlock
);
1090 ath_update_txpow(sc
);
1091 if (ath_startrecv(sc
) != 0) {
1092 DPRINTF(sc
, ATH_DBG_FATAL
,
1093 "Unable to restart recv logic\n");
1097 if (sc
->sc_flags
& SC_OP_BEACONS
)
1098 ath_beacon_config(sc
, ATH_IF_ID_ANY
); /* restart beacons */
1100 /* Re-Enable interrupts */
1101 ath9k_hw_set_interrupts(ah
, sc
->sc_imask
);
1104 ath9k_hw_cfg_output(ah
, ATH_LED_PIN
,
1105 AR_GPIO_OUTPUT_MUX_AS_OUTPUT
);
1106 ath9k_hw_set_gpio(ah
, ATH_LED_PIN
, 0);
1108 ieee80211_wake_queues(sc
->hw
);
1111 static void ath_radio_disable(struct ath_softc
*sc
)
1113 struct ath_hal
*ah
= sc
->sc_ah
;
1117 ieee80211_stop_queues(sc
->hw
);
1120 ath9k_hw_set_gpio(ah
, ATH_LED_PIN
, 1);
1121 ath9k_hw_cfg_gpio_input(ah
, ATH_LED_PIN
);
1123 /* Disable interrupts */
1124 ath9k_hw_set_interrupts(ah
, 0);
1126 ath_draintxq(sc
, false); /* clear pending tx frames */
1127 ath_stoprecv(sc
); /* turn off frame recv */
1128 ath_flushrecv(sc
); /* flush recv queue */
1130 spin_lock_bh(&sc
->sc_resetlock
);
1131 if (!ath9k_hw_reset(ah
, ah
->ah_curchan
,
1133 sc
->sc_tx_chainmask
,
1134 sc
->sc_rx_chainmask
,
1135 sc
->sc_ht_extprotspacing
,
1137 DPRINTF(sc
, ATH_DBG_FATAL
,
1138 "Unable to reset channel %u (%uMhz) "
1139 "flags 0x%x hal status %u\n",
1140 ath9k_hw_mhz2ieee(ah
,
1141 ah
->ah_curchan
->channel
,
1142 ah
->ah_curchan
->channelFlags
),
1143 ah
->ah_curchan
->channel
,
1144 ah
->ah_curchan
->channelFlags
, status
);
1146 spin_unlock_bh(&sc
->sc_resetlock
);
1148 ath9k_hw_phy_disable(ah
);
1149 ath9k_hw_setpower(ah
, ATH9K_PM_FULL_SLEEP
);
1152 static bool ath_is_rfkill_set(struct ath_softc
*sc
)
1154 struct ath_hal
*ah
= sc
->sc_ah
;
1156 return ath9k_hw_gpio_get(ah
, ah
->ah_rfkill_gpio
) ==
1157 ah
->ah_rfkill_polarity
;
1160 /* h/w rfkill poll function */
1161 static void ath_rfkill_poll(struct work_struct
*work
)
1163 struct ath_softc
*sc
= container_of(work
, struct ath_softc
,
1164 rf_kill
.rfkill_poll
.work
);
1167 if (sc
->sc_flags
& SC_OP_INVALID
)
1170 radio_on
= !ath_is_rfkill_set(sc
);
1173 * enable/disable radio only when there is a
1174 * state change in RF switch
1176 if (radio_on
== !!(sc
->sc_flags
& SC_OP_RFKILL_HW_BLOCKED
)) {
1177 enum rfkill_state state
;
1179 if (sc
->sc_flags
& SC_OP_RFKILL_SW_BLOCKED
) {
1180 state
= radio_on
? RFKILL_STATE_SOFT_BLOCKED
1181 : RFKILL_STATE_HARD_BLOCKED
;
1182 } else if (radio_on
) {
1183 ath_radio_enable(sc
);
1184 state
= RFKILL_STATE_UNBLOCKED
;
1186 ath_radio_disable(sc
);
1187 state
= RFKILL_STATE_HARD_BLOCKED
;
1190 if (state
== RFKILL_STATE_HARD_BLOCKED
)
1191 sc
->sc_flags
|= SC_OP_RFKILL_HW_BLOCKED
;
1193 sc
->sc_flags
&= ~SC_OP_RFKILL_HW_BLOCKED
;
1195 rfkill_force_state(sc
->rf_kill
.rfkill
, state
);
1198 queue_delayed_work(sc
->hw
->workqueue
, &sc
->rf_kill
.rfkill_poll
,
1199 msecs_to_jiffies(ATH_RFKILL_POLL_INTERVAL
));
1202 /* s/w rfkill handler */
1203 static int ath_sw_toggle_radio(void *data
, enum rfkill_state state
)
1205 struct ath_softc
*sc
= data
;
1208 case RFKILL_STATE_SOFT_BLOCKED
:
1209 if (!(sc
->sc_flags
& (SC_OP_RFKILL_HW_BLOCKED
|
1210 SC_OP_RFKILL_SW_BLOCKED
)))
1211 ath_radio_disable(sc
);
1212 sc
->sc_flags
|= SC_OP_RFKILL_SW_BLOCKED
;
1214 case RFKILL_STATE_UNBLOCKED
:
1215 if ((sc
->sc_flags
& SC_OP_RFKILL_SW_BLOCKED
)) {
1216 sc
->sc_flags
&= ~SC_OP_RFKILL_SW_BLOCKED
;
1217 if (sc
->sc_flags
& SC_OP_RFKILL_HW_BLOCKED
) {
1218 DPRINTF(sc
, ATH_DBG_FATAL
, "Can't turn on the"
1219 "radio as it is disabled by h/w\n");
1222 ath_radio_enable(sc
);
1230 /* Init s/w rfkill */
1231 static int ath_init_sw_rfkill(struct ath_softc
*sc
)
1233 sc
->rf_kill
.rfkill
= rfkill_allocate(wiphy_dev(sc
->hw
->wiphy
),
1235 if (!sc
->rf_kill
.rfkill
) {
1236 DPRINTF(sc
, ATH_DBG_FATAL
, "Failed to allocate rfkill\n");
1240 snprintf(sc
->rf_kill
.rfkill_name
, sizeof(sc
->rf_kill
.rfkill_name
),
1241 "ath9k-%s:rfkill", wiphy_name(sc
->hw
->wiphy
));
1242 sc
->rf_kill
.rfkill
->name
= sc
->rf_kill
.rfkill_name
;
1243 sc
->rf_kill
.rfkill
->data
= sc
;
1244 sc
->rf_kill
.rfkill
->toggle_radio
= ath_sw_toggle_radio
;
1245 sc
->rf_kill
.rfkill
->state
= RFKILL_STATE_UNBLOCKED
;
1246 sc
->rf_kill
.rfkill
->user_claim_unsupported
= 1;
1251 /* Deinitialize rfkill */
1252 static void ath_deinit_rfkill(struct ath_softc
*sc
)
1254 if (sc
->sc_ah
->ah_caps
.hw_caps
& ATH9K_HW_CAP_RFSILENT
)
1255 cancel_delayed_work_sync(&sc
->rf_kill
.rfkill_poll
);
1257 if (sc
->sc_flags
& SC_OP_RFKILL_REGISTERED
) {
1258 rfkill_unregister(sc
->rf_kill
.rfkill
);
1259 sc
->sc_flags
&= ~SC_OP_RFKILL_REGISTERED
;
1260 sc
->rf_kill
.rfkill
= NULL
;
1264 static int ath_start_rfkill_poll(struct ath_softc
*sc
)
1266 if (sc
->sc_ah
->ah_caps
.hw_caps
& ATH9K_HW_CAP_RFSILENT
)
1267 queue_delayed_work(sc
->hw
->workqueue
,
1268 &sc
->rf_kill
.rfkill_poll
, 0);
1270 if (!(sc
->sc_flags
& SC_OP_RFKILL_REGISTERED
)) {
1271 if (rfkill_register(sc
->rf_kill
.rfkill
)) {
1272 DPRINTF(sc
, ATH_DBG_FATAL
,
1273 "Unable to register rfkill\n");
1274 rfkill_free(sc
->rf_kill
.rfkill
);
1276 /* Deinitialize the device */
1279 free_irq(sc
->pdev
->irq
, sc
);
1280 pci_iounmap(sc
->pdev
, sc
->mem
);
1281 pci_release_region(sc
->pdev
, 0);
1282 pci_disable_device(sc
->pdev
);
1283 ieee80211_free_hw(sc
->hw
);
1286 sc
->sc_flags
|= SC_OP_RFKILL_REGISTERED
;
1292 #endif /* CONFIG_RFKILL */
1294 static void ath_detach(struct ath_softc
*sc
)
1296 struct ieee80211_hw
*hw
= sc
->hw
;
1299 DPRINTF(sc
, ATH_DBG_CONFIG
, "Detach ATH hw\n");
1301 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1302 ath_deinit_rfkill(sc
);
1304 ath_deinit_leds(sc
);
1306 ieee80211_unregister_hw(hw
);
1310 tasklet_kill(&sc
->intr_tq
);
1311 tasklet_kill(&sc
->bcon_tasklet
);
1313 if (!(sc
->sc_flags
& SC_OP_INVALID
))
1314 ath9k_hw_setpower(sc
->sc_ah
, ATH9K_PM_AWAKE
);
1316 /* cleanup tx queues */
1317 for (i
= 0; i
< ATH9K_NUM_TX_QUEUES
; i
++)
1318 if (ATH_TXQ_SETUP(sc
, i
))
1319 ath_tx_cleanupq(sc
, &sc
->tx
.txq
[i
]);
1321 ath9k_hw_detach(sc
->sc_ah
);
1322 ath9k_exit_debug(sc
);
1325 static int ath_init(u16 devid
, struct ath_softc
*sc
)
1327 struct ath_hal
*ah
= NULL
;
1332 /* XXX: hardware will not be ready until ath_open() being called */
1333 sc
->sc_flags
|= SC_OP_INVALID
;
1335 if (ath9k_init_debug(sc
) < 0)
1336 printk(KERN_ERR
"Unable to create debugfs files\n");
1338 spin_lock_init(&sc
->sc_resetlock
);
1339 mutex_init(&sc
->mutex
);
1340 tasklet_init(&sc
->intr_tq
, ath9k_tasklet
, (unsigned long)sc
);
1341 tasklet_init(&sc
->bcon_tasklet
, ath9k_beacon_tasklet
,
1345 * Cache line size is used to size and align various
1346 * structures used to communicate with the hardware.
1348 bus_read_cachesize(sc
, &csz
);
1349 /* XXX assert csz is non-zero */
1350 sc
->sc_cachelsz
= csz
<< 2; /* convert to bytes */
1352 ah
= ath9k_hw_attach(devid
, sc
, sc
->mem
, &status
);
1354 DPRINTF(sc
, ATH_DBG_FATAL
,
1355 "Unable to attach hardware; HAL status %u\n", status
);
1361 /* Get the hardware key cache size. */
1362 sc
->sc_keymax
= ah
->ah_caps
.keycache_size
;
1363 if (sc
->sc_keymax
> ATH_KEYMAX
) {
1364 DPRINTF(sc
, ATH_DBG_KEYCACHE
,
1365 "Warning, using only %u entries in %u key cache\n",
1366 ATH_KEYMAX
, sc
->sc_keymax
);
1367 sc
->sc_keymax
= ATH_KEYMAX
;
1371 * Reset the key cache since some parts do not
1372 * reset the contents on initial power up.
1374 for (i
= 0; i
< sc
->sc_keymax
; i
++)
1375 ath9k_hw_keyreset(ah
, (u16
) i
);
1377 /* Collect the channel list using the default country code */
1379 error
= ath_setup_channels(sc
);
1383 /* default to MONITOR mode */
1384 sc
->sc_ah
->ah_opmode
= NL80211_IFTYPE_MONITOR
;
1387 /* Setup rate tables */
1389 ath_rate_attach(sc
);
1390 ath_setup_rates(sc
, IEEE80211_BAND_2GHZ
);
1391 ath_setup_rates(sc
, IEEE80211_BAND_5GHZ
);
1394 * Allocate hardware transmit queues: one queue for
1395 * beacon frames and one data queue for each QoS
1396 * priority. Note that the hal handles reseting
1397 * these queues at the needed time.
1399 sc
->beacon
.beaconq
= ath_beaconq_setup(ah
);
1400 if (sc
->beacon
.beaconq
== -1) {
1401 DPRINTF(sc
, ATH_DBG_FATAL
,
1402 "Unable to setup a beacon xmit queue\n");
1406 sc
->beacon
.cabq
= ath_txq_setup(sc
, ATH9K_TX_QUEUE_CAB
, 0);
1407 if (sc
->beacon
.cabq
== NULL
) {
1408 DPRINTF(sc
, ATH_DBG_FATAL
,
1409 "Unable to setup CAB xmit queue\n");
1414 sc
->sc_config
.cabqReadytime
= ATH_CABQ_READY_TIME
;
1415 ath_cabq_update(sc
);
1417 for (i
= 0; i
< ARRAY_SIZE(sc
->tx
.hwq_map
); i
++)
1418 sc
->tx
.hwq_map
[i
] = -1;
1420 /* Setup data queues */
1421 /* NB: ensure BK queue is the lowest priority h/w queue */
1422 if (!ath_tx_setup(sc
, ATH9K_WME_AC_BK
)) {
1423 DPRINTF(sc
, ATH_DBG_FATAL
,
1424 "Unable to setup xmit queue for BK traffic\n");
1429 if (!ath_tx_setup(sc
, ATH9K_WME_AC_BE
)) {
1430 DPRINTF(sc
, ATH_DBG_FATAL
,
1431 "Unable to setup xmit queue for BE traffic\n");
1435 if (!ath_tx_setup(sc
, ATH9K_WME_AC_VI
)) {
1436 DPRINTF(sc
, ATH_DBG_FATAL
,
1437 "Unable to setup xmit queue for VI traffic\n");
1441 if (!ath_tx_setup(sc
, ATH9K_WME_AC_VO
)) {
1442 DPRINTF(sc
, ATH_DBG_FATAL
,
1443 "Unable to setup xmit queue for VO traffic\n");
1448 /* Initializes the noise floor to a reasonable default value.
1449 * Later on this will be updated during ANI processing. */
1451 sc
->sc_ani
.sc_noise_floor
= ATH_DEFAULT_NOISE_FLOOR
;
1452 setup_timer(&sc
->sc_ani
.timer
, ath_ani_calibrate
, (unsigned long)sc
);
1454 if (ath9k_hw_getcapability(ah
, ATH9K_CAP_CIPHER
,
1455 ATH9K_CIPHER_TKIP
, NULL
)) {
1457 * Whether we should enable h/w TKIP MIC.
1458 * XXX: if we don't support WME TKIP MIC, then we wouldn't
1459 * report WMM capable, so it's always safe to turn on
1460 * TKIP MIC in this case.
1462 ath9k_hw_setcapability(sc
->sc_ah
, ATH9K_CAP_TKIP_MIC
,
1467 * Check whether the separate key cache entries
1468 * are required to handle both tx+rx MIC keys.
1469 * With split mic keys the number of stations is limited
1470 * to 27 otherwise 59.
1472 if (ath9k_hw_getcapability(ah
, ATH9K_CAP_CIPHER
,
1473 ATH9K_CIPHER_TKIP
, NULL
)
1474 && ath9k_hw_getcapability(ah
, ATH9K_CAP_CIPHER
,
1475 ATH9K_CIPHER_MIC
, NULL
)
1476 && ath9k_hw_getcapability(ah
, ATH9K_CAP_TKIP_SPLIT
,
1478 sc
->sc_splitmic
= 1;
1480 /* turn on mcast key search if possible */
1481 if (!ath9k_hw_getcapability(ah
, ATH9K_CAP_MCAST_KEYSRCH
, 0, NULL
))
1482 (void)ath9k_hw_setcapability(ah
, ATH9K_CAP_MCAST_KEYSRCH
, 1,
1485 sc
->sc_config
.txpowlimit
= ATH_TXPOWER_MAX
;
1486 sc
->sc_config
.txpowlimit_override
= 0;
1488 /* 11n Capabilities */
1489 if (ah
->ah_caps
.hw_caps
& ATH9K_HW_CAP_HT
) {
1490 sc
->sc_flags
|= SC_OP_TXAGGR
;
1491 sc
->sc_flags
|= SC_OP_RXAGGR
;
1494 sc
->sc_tx_chainmask
= ah
->ah_caps
.tx_chainmask
;
1495 sc
->sc_rx_chainmask
= ah
->ah_caps
.rx_chainmask
;
1497 ath9k_hw_setcapability(ah
, ATH9K_CAP_DIVERSITY
, 1, true, NULL
);
1498 sc
->rx
.defant
= ath9k_hw_getdefantenna(ah
);
1500 ath9k_hw_getmac(ah
, sc
->sc_myaddr
);
1501 if (ah
->ah_caps
.hw_caps
& ATH9K_HW_CAP_BSSIDMASK
) {
1502 ath9k_hw_getbssidmask(ah
, sc
->sc_bssidmask
);
1503 ATH_SET_VAP_BSSID_MASK(sc
->sc_bssidmask
);
1504 ath9k_hw_setbssidmask(ah
, sc
->sc_bssidmask
);
1507 sc
->beacon
.slottime
= ATH9K_SLOT_TIME_9
; /* default to short slot time */
1509 /* initialize beacon slots */
1510 for (i
= 0; i
< ARRAY_SIZE(sc
->beacon
.bslot
); i
++)
1511 sc
->beacon
.bslot
[i
] = ATH_IF_ID_ANY
;
1513 /* save MISC configurations */
1514 sc
->sc_config
.swBeaconProcess
= 1;
1516 /* setup channels and rates */
1518 sc
->sbands
[IEEE80211_BAND_2GHZ
].channels
=
1519 sc
->channels
[IEEE80211_BAND_2GHZ
];
1520 sc
->sbands
[IEEE80211_BAND_2GHZ
].bitrates
=
1521 sc
->rates
[IEEE80211_BAND_2GHZ
];
1522 sc
->sbands
[IEEE80211_BAND_2GHZ
].band
= IEEE80211_BAND_2GHZ
;
1524 if (test_bit(ATH9K_MODE_11A
, sc
->sc_ah
->ah_caps
.wireless_modes
)) {
1525 sc
->sbands
[IEEE80211_BAND_5GHZ
].channels
=
1526 sc
->channels
[IEEE80211_BAND_5GHZ
];
1527 sc
->sbands
[IEEE80211_BAND_5GHZ
].bitrates
=
1528 sc
->rates
[IEEE80211_BAND_5GHZ
];
1529 sc
->sbands
[IEEE80211_BAND_5GHZ
].band
= IEEE80211_BAND_5GHZ
;
1534 /* cleanup tx queues */
1535 for (i
= 0; i
< ATH9K_NUM_TX_QUEUES
; i
++)
1536 if (ATH_TXQ_SETUP(sc
, i
))
1537 ath_tx_cleanupq(sc
, &sc
->tx
.txq
[i
]);
1540 ath9k_hw_detach(ah
);
1545 static int ath_attach(u16 devid
, struct ath_softc
*sc
)
1547 struct ieee80211_hw
*hw
= sc
->hw
;
1550 DPRINTF(sc
, ATH_DBG_CONFIG
, "Attach ATH hw\n");
1552 error
= ath_init(devid
, sc
);
1556 /* get mac address from hardware and set in mac80211 */
1558 SET_IEEE80211_PERM_ADDR(hw
, sc
->sc_myaddr
);
1560 hw
->flags
= IEEE80211_HW_RX_INCLUDES_FCS
|
1561 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING
|
1562 IEEE80211_HW_SIGNAL_DBM
|
1563 IEEE80211_HW_AMPDU_AGGREGATION
;
1565 hw
->wiphy
->interface_modes
=
1566 BIT(NL80211_IFTYPE_AP
) |
1567 BIT(NL80211_IFTYPE_STATION
) |
1568 BIT(NL80211_IFTYPE_ADHOC
);
1572 hw
->max_rate_tries
= ATH_11N_TXMAXTRY
;
1573 hw
->sta_data_size
= sizeof(struct ath_node
);
1574 hw
->vif_data_size
= sizeof(struct ath_vap
);
1576 hw
->rate_control_algorithm
= "ath9k_rate_control";
1578 if (sc
->sc_ah
->ah_caps
.hw_caps
& ATH9K_HW_CAP_HT
) {
1579 setup_ht_cap(&sc
->sbands
[IEEE80211_BAND_2GHZ
].ht_cap
);
1580 if (test_bit(ATH9K_MODE_11A
, sc
->sc_ah
->ah_caps
.wireless_modes
))
1581 setup_ht_cap(&sc
->sbands
[IEEE80211_BAND_5GHZ
].ht_cap
);
1584 hw
->wiphy
->bands
[IEEE80211_BAND_2GHZ
] = &sc
->sbands
[IEEE80211_BAND_2GHZ
];
1585 if (test_bit(ATH9K_MODE_11A
, sc
->sc_ah
->ah_caps
.wireless_modes
))
1586 hw
->wiphy
->bands
[IEEE80211_BAND_5GHZ
] =
1587 &sc
->sbands
[IEEE80211_BAND_5GHZ
];
1589 /* initialize tx/rx engine */
1590 error
= ath_tx_init(sc
, ATH_TXBUF
);
1594 error
= ath_rx_init(sc
, ATH_RXBUF
);
1598 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1599 /* Initialze h/w Rfkill */
1600 if (sc
->sc_ah
->ah_caps
.hw_caps
& ATH9K_HW_CAP_RFSILENT
)
1601 INIT_DELAYED_WORK(&sc
->rf_kill
.rfkill_poll
, ath_rfkill_poll
);
1603 /* Initialize s/w rfkill */
1604 if (ath_init_sw_rfkill(sc
))
1608 error
= ieee80211_register_hw(hw
);
1610 /* Initialize LED control */
1619 int ath_reset(struct ath_softc
*sc
, bool retry_tx
)
1621 struct ath_hal
*ah
= sc
->sc_ah
;
1625 ath9k_hw_set_interrupts(ah
, 0);
1626 ath_draintxq(sc
, retry_tx
);
1630 spin_lock_bh(&sc
->sc_resetlock
);
1631 if (!ath9k_hw_reset(ah
, sc
->sc_ah
->ah_curchan
,
1633 sc
->sc_tx_chainmask
, sc
->sc_rx_chainmask
,
1634 sc
->sc_ht_extprotspacing
, false, &status
)) {
1635 DPRINTF(sc
, ATH_DBG_FATAL
,
1636 "Unable to reset hardware; hal status %u\n", status
);
1639 spin_unlock_bh(&sc
->sc_resetlock
);
1641 if (ath_startrecv(sc
) != 0)
1642 DPRINTF(sc
, ATH_DBG_FATAL
, "Unable to start recv logic\n");
1645 * We may be doing a reset in response to a request
1646 * that changes the channel so update any state that
1647 * might change as a result.
1649 ath_setcurmode(sc
, ath_chan2mode(sc
->sc_ah
->ah_curchan
));
1651 ath_update_txpow(sc
);
1653 if (sc
->sc_flags
& SC_OP_BEACONS
)
1654 ath_beacon_config(sc
, ATH_IF_ID_ANY
); /* restart beacons */
1656 ath9k_hw_set_interrupts(ah
, sc
->sc_imask
);
1660 for (i
= 0; i
< ATH9K_NUM_TX_QUEUES
; i
++) {
1661 if (ATH_TXQ_SETUP(sc
, i
)) {
1662 spin_lock_bh(&sc
->tx
.txq
[i
].axq_lock
);
1663 ath_txq_schedule(sc
, &sc
->tx
.txq
[i
]);
1664 spin_unlock_bh(&sc
->tx
.txq
[i
].axq_lock
);
1673 * This function will allocate both the DMA descriptor structure, and the
1674 * buffers it contains. These are used to contain the descriptors used
1677 int ath_descdma_setup(struct ath_softc
*sc
, struct ath_descdma
*dd
,
1678 struct list_head
*head
, const char *name
,
1679 int nbuf
, int ndesc
)
1681 #define DS2PHYS(_dd, _ds) \
1682 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
1683 #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
1684 #define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
1686 struct ath_desc
*ds
;
1688 int i
, bsize
, error
;
1690 DPRINTF(sc
, ATH_DBG_CONFIG
, "%s DMA: %u buffers %u desc/buf\n",
1693 /* ath_desc must be a multiple of DWORDs */
1694 if ((sizeof(struct ath_desc
) % 4) != 0) {
1695 DPRINTF(sc
, ATH_DBG_FATAL
, "ath_desc not DWORD aligned\n");
1696 ASSERT((sizeof(struct ath_desc
) % 4) == 0);
1702 dd
->dd_desc_len
= sizeof(struct ath_desc
) * nbuf
* ndesc
;
1705 * Need additional DMA memory because we can't use
1706 * descriptors that cross the 4K page boundary. Assume
1707 * one skipped descriptor per 4K page.
1709 if (!(sc
->sc_ah
->ah_caps
.hw_caps
& ATH9K_HW_CAP_4KB_SPLITTRANS
)) {
1711 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd
->dd_desc_len
);
1714 while (ndesc_skipped
) {
1715 dma_len
= ndesc_skipped
* sizeof(struct ath_desc
);
1716 dd
->dd_desc_len
+= dma_len
;
1718 ndesc_skipped
= ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len
);
1722 /* allocate descriptors */
1723 dd
->dd_desc
= pci_alloc_consistent(sc
->pdev
,
1725 &dd
->dd_desc_paddr
);
1726 if (dd
->dd_desc
== NULL
) {
1731 DPRINTF(sc
, ATH_DBG_CONFIG
, "%s DMA map: %p (%u) -> %llx (%u)\n",
1732 dd
->dd_name
, ds
, (u32
) dd
->dd_desc_len
,
1733 ito64(dd
->dd_desc_paddr
), /*XXX*/(u32
) dd
->dd_desc_len
);
1735 /* allocate buffers */
1736 bsize
= sizeof(struct ath_buf
) * nbuf
;
1737 bf
= kmalloc(bsize
, GFP_KERNEL
);
1742 memset(bf
, 0, bsize
);
1745 INIT_LIST_HEAD(head
);
1746 for (i
= 0; i
< nbuf
; i
++, bf
++, ds
+= ndesc
) {
1748 bf
->bf_daddr
= DS2PHYS(dd
, ds
);
1750 if (!(sc
->sc_ah
->ah_caps
.hw_caps
&
1751 ATH9K_HW_CAP_4KB_SPLITTRANS
)) {
1753 * Skip descriptor addresses which can cause 4KB
1754 * boundary crossing (addr + length) with a 32 dword
1757 while (ATH_DESC_4KB_BOUND_CHECK(bf
->bf_daddr
)) {
1758 ASSERT((caddr_t
) bf
->bf_desc
<
1759 ((caddr_t
) dd
->dd_desc
+
1764 bf
->bf_daddr
= DS2PHYS(dd
, ds
);
1767 list_add_tail(&bf
->list
, head
);
1771 pci_free_consistent(sc
->pdev
,
1772 dd
->dd_desc_len
, dd
->dd_desc
, dd
->dd_desc_paddr
);
1774 memset(dd
, 0, sizeof(*dd
));
1776 #undef ATH_DESC_4KB_BOUND_CHECK
1777 #undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
1781 void ath_descdma_cleanup(struct ath_softc
*sc
,
1782 struct ath_descdma
*dd
,
1783 struct list_head
*head
)
1785 pci_free_consistent(sc
->pdev
,
1786 dd
->dd_desc_len
, dd
->dd_desc
, dd
->dd_desc_paddr
);
1788 INIT_LIST_HEAD(head
);
1789 kfree(dd
->dd_bufptr
);
1790 memset(dd
, 0, sizeof(*dd
));
1793 int ath_get_hal_qnum(u16 queue
, struct ath_softc
*sc
)
1799 qnum
= sc
->tx
.hwq_map
[ATH9K_WME_AC_VO
];
1802 qnum
= sc
->tx
.hwq_map
[ATH9K_WME_AC_VI
];
1805 qnum
= sc
->tx
.hwq_map
[ATH9K_WME_AC_BE
];
1808 qnum
= sc
->tx
.hwq_map
[ATH9K_WME_AC_BK
];
1811 qnum
= sc
->tx
.hwq_map
[ATH9K_WME_AC_BE
];
1818 int ath_get_mac80211_qnum(u32 queue
, struct ath_softc
*sc
)
1823 case ATH9K_WME_AC_VO
:
1826 case ATH9K_WME_AC_VI
:
1829 case ATH9K_WME_AC_BE
:
1832 case ATH9K_WME_AC_BK
:
1843 /**********************/
1844 /* mac80211 callbacks */
1845 /**********************/
1847 static int ath9k_start(struct ieee80211_hw
*hw
)
1849 struct ath_softc
*sc
= hw
->priv
;
1850 struct ieee80211_channel
*curchan
= hw
->conf
.channel
;
1851 struct ath9k_channel
*init_channel
;
1852 int error
= 0, pos
, status
;
1854 DPRINTF(sc
, ATH_DBG_CONFIG
, "Starting driver with "
1855 "initial channel: %d MHz\n", curchan
->center_freq
);
1857 /* setup initial channel */
1859 pos
= ath_get_channel(sc
, curchan
);
1861 DPRINTF(sc
, ATH_DBG_FATAL
, "Invalid channel: %d\n", curchan
->center_freq
);
1866 sc
->tx_chan_width
= ATH9K_HT_MACMODE_20
;
1867 sc
->sc_ah
->ah_channels
[pos
].chanmode
=
1868 (curchan
->band
== IEEE80211_BAND_2GHZ
) ? CHANNEL_G
: CHANNEL_A
;
1869 init_channel
= &sc
->sc_ah
->ah_channels
[pos
];
1871 /* Reset SERDES registers */
1872 ath9k_hw_configpcipowersave(sc
->sc_ah
, 0);
1875 * The basic interface to setting the hardware in a good
1876 * state is ``reset''. On return the hardware is known to
1877 * be powered up and with interrupts disabled. This must
1878 * be followed by initialization of the appropriate bits
1879 * and then setup of the interrupt mask.
1881 spin_lock_bh(&sc
->sc_resetlock
);
1882 if (!ath9k_hw_reset(sc
->sc_ah
, init_channel
,
1884 sc
->sc_tx_chainmask
, sc
->sc_rx_chainmask
,
1885 sc
->sc_ht_extprotspacing
, false, &status
)) {
1886 DPRINTF(sc
, ATH_DBG_FATAL
,
1887 "Unable to reset hardware; hal status %u "
1888 "(freq %u flags 0x%x)\n", status
,
1889 init_channel
->channel
, init_channel
->channelFlags
);
1891 spin_unlock_bh(&sc
->sc_resetlock
);
1894 spin_unlock_bh(&sc
->sc_resetlock
);
1897 * This is needed only to setup initial state
1898 * but it's best done after a reset.
1900 ath_update_txpow(sc
);
1903 * Setup the hardware after reset:
1904 * The receive engine is set going.
1905 * Frame transmit is handled entirely
1906 * in the frame output path; there's nothing to do
1907 * here except setup the interrupt mask.
1909 if (ath_startrecv(sc
) != 0) {
1910 DPRINTF(sc
, ATH_DBG_FATAL
,
1911 "Unable to start recv logic\n");
1916 /* Setup our intr mask. */
1917 sc
->sc_imask
= ATH9K_INT_RX
| ATH9K_INT_TX
1918 | ATH9K_INT_RXEOL
| ATH9K_INT_RXORN
1919 | ATH9K_INT_FATAL
| ATH9K_INT_GLOBAL
;
1921 if (sc
->sc_ah
->ah_caps
.hw_caps
& ATH9K_HW_CAP_GTT
)
1922 sc
->sc_imask
|= ATH9K_INT_GTT
;
1924 if (sc
->sc_ah
->ah_caps
.hw_caps
& ATH9K_HW_CAP_HT
)
1925 sc
->sc_imask
|= ATH9K_INT_CST
;
1928 * Enable MIB interrupts when there are hardware phy counters.
1929 * Note we only do this (at the moment) for station mode.
1931 if (ath9k_hw_phycounters(sc
->sc_ah
) &&
1932 ((sc
->sc_ah
->ah_opmode
== NL80211_IFTYPE_STATION
) ||
1933 (sc
->sc_ah
->ah_opmode
== NL80211_IFTYPE_ADHOC
)))
1934 sc
->sc_imask
|= ATH9K_INT_MIB
;
1936 * Some hardware processes the TIM IE and fires an
1937 * interrupt when the TIM bit is set. For hardware
1938 * that does, if not overridden by configuration,
1939 * enable the TIM interrupt when operating as station.
1941 if ((sc
->sc_ah
->ah_caps
.hw_caps
& ATH9K_HW_CAP_ENHANCEDPM
) &&
1942 (sc
->sc_ah
->ah_opmode
== NL80211_IFTYPE_STATION
) &&
1943 !sc
->sc_config
.swBeaconProcess
)
1944 sc
->sc_imask
|= ATH9K_INT_TIM
;
1946 ath_setcurmode(sc
, ath_chan2mode(init_channel
));
1948 sc
->sc_flags
&= ~SC_OP_INVALID
;
1950 /* Disable BMISS interrupt when we're not associated */
1951 sc
->sc_imask
&= ~(ATH9K_INT_SWBA
| ATH9K_INT_BMISS
);
1952 ath9k_hw_set_interrupts(sc
->sc_ah
, sc
->sc_imask
);
1954 ieee80211_wake_queues(sc
->hw
);
1956 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1957 error
= ath_start_rfkill_poll(sc
);
1964 static int ath9k_tx(struct ieee80211_hw
*hw
,
1965 struct sk_buff
*skb
)
1967 struct ieee80211_tx_info
*info
= IEEE80211_SKB_CB(skb
);
1968 struct ath_softc
*sc
= hw
->priv
;
1969 struct ath_tx_control txctl
;
1970 int hdrlen
, padsize
;
1972 memset(&txctl
, 0, sizeof(struct ath_tx_control
));
1975 * As a temporary workaround, assign seq# here; this will likely need
1976 * to be cleaned up to work better with Beacon transmission and virtual
1979 if (info
->flags
& IEEE80211_TX_CTL_ASSIGN_SEQ
) {
1980 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*) skb
->data
;
1981 if (info
->flags
& IEEE80211_TX_CTL_FIRST_FRAGMENT
)
1982 sc
->tx
.seq_no
+= 0x10;
1983 hdr
->seq_ctrl
&= cpu_to_le16(IEEE80211_SCTL_FRAG
);
1984 hdr
->seq_ctrl
|= cpu_to_le16(sc
->tx
.seq_no
);
1987 /* Add the padding after the header if this is not already done */
1988 hdrlen
= ieee80211_get_hdrlen_from_skb(skb
);
1990 padsize
= hdrlen
% 4;
1991 if (skb_headroom(skb
) < padsize
)
1993 skb_push(skb
, padsize
);
1994 memmove(skb
->data
, skb
->data
+ padsize
, hdrlen
);
1997 /* Check if a tx queue is available */
1999 txctl
.txq
= ath_test_get_txq(sc
, skb
);
2003 DPRINTF(sc
, ATH_DBG_XMIT
, "transmitting packet, skb: %p\n", skb
);
2005 if (ath_tx_start(sc
, skb
, &txctl
) != 0) {
2006 DPRINTF(sc
, ATH_DBG_XMIT
, "TX failed\n");
2012 dev_kfree_skb_any(skb
);
2016 static void ath9k_stop(struct ieee80211_hw
*hw
)
2018 struct ath_softc
*sc
= hw
->priv
;
2020 if (sc
->sc_flags
& SC_OP_INVALID
) {
2021 DPRINTF(sc
, ATH_DBG_ANY
, "Device not present\n");
2025 DPRINTF(sc
, ATH_DBG_CONFIG
, "Cleaning up\n");
2027 ieee80211_stop_queues(sc
->hw
);
2029 /* make sure h/w will not generate any interrupt
2030 * before setting the invalid flag. */
2031 ath9k_hw_set_interrupts(sc
->sc_ah
, 0);
2033 if (!(sc
->sc_flags
& SC_OP_INVALID
)) {
2034 ath_draintxq(sc
, false);
2036 ath9k_hw_phy_disable(sc
->sc_ah
);
2038 sc
->rx
.rxlink
= NULL
;
2040 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2041 if (sc
->sc_ah
->ah_caps
.hw_caps
& ATH9K_HW_CAP_RFSILENT
)
2042 cancel_delayed_work_sync(&sc
->rf_kill
.rfkill_poll
);
2044 /* disable HAL and put h/w to sleep */
2045 ath9k_hw_disable(sc
->sc_ah
);
2046 ath9k_hw_configpcipowersave(sc
->sc_ah
, 1);
2048 sc
->sc_flags
|= SC_OP_INVALID
;
2050 DPRINTF(sc
, ATH_DBG_CONFIG
, "Driver halt\n");
2053 static int ath9k_add_interface(struct ieee80211_hw
*hw
,
2054 struct ieee80211_if_init_conf
*conf
)
2056 struct ath_softc
*sc
= hw
->priv
;
2057 struct ath_vap
*avp
= (void *)conf
->vif
->drv_priv
;
2058 enum nl80211_iftype ic_opmode
= NL80211_IFTYPE_UNSPECIFIED
;
2060 /* Support only vap for now */
2065 switch (conf
->type
) {
2066 case NL80211_IFTYPE_STATION
:
2067 ic_opmode
= NL80211_IFTYPE_STATION
;
2069 case NL80211_IFTYPE_ADHOC
:
2070 ic_opmode
= NL80211_IFTYPE_ADHOC
;
2072 case NL80211_IFTYPE_AP
:
2073 ic_opmode
= NL80211_IFTYPE_AP
;
2076 DPRINTF(sc
, ATH_DBG_FATAL
,
2077 "Interface type %d not yet supported\n", conf
->type
);
2081 DPRINTF(sc
, ATH_DBG_CONFIG
, "Attach a VAP of type: %d\n", ic_opmode
);
2083 /* Set the VAP opmode */
2084 avp
->av_opmode
= ic_opmode
;
2087 if (ic_opmode
== NL80211_IFTYPE_AP
)
2088 ath9k_hw_set_tsfadjust(sc
->sc_ah
, 1);
2090 sc
->sc_vaps
[0] = conf
->vif
;
2093 /* Set the device opmode */
2094 sc
->sc_ah
->ah_opmode
= ic_opmode
;
2096 if (conf
->type
== NL80211_IFTYPE_AP
) {
2097 /* TODO: is this a suitable place to start ANI for AP mode? */
2099 mod_timer(&sc
->sc_ani
.timer
,
2100 jiffies
+ msecs_to_jiffies(ATH_ANI_POLLINTERVAL
));
2106 static void ath9k_remove_interface(struct ieee80211_hw
*hw
,
2107 struct ieee80211_if_init_conf
*conf
)
2109 struct ath_softc
*sc
= hw
->priv
;
2110 struct ath_vap
*avp
= (void *)conf
->vif
->drv_priv
;
2112 DPRINTF(sc
, ATH_DBG_CONFIG
, "Detach Interface\n");
2115 del_timer_sync(&sc
->sc_ani
.timer
);
2117 /* Reclaim beacon resources */
2118 if (sc
->sc_ah
->ah_opmode
== NL80211_IFTYPE_AP
||
2119 sc
->sc_ah
->ah_opmode
== NL80211_IFTYPE_ADHOC
) {
2120 ath9k_hw_stoptxdma(sc
->sc_ah
, sc
->beacon
.beaconq
);
2121 ath_beacon_return(sc
, avp
);
2124 sc
->sc_flags
&= ~SC_OP_BEACONS
;
2126 sc
->sc_vaps
[0] = NULL
;
2130 static int ath9k_config(struct ieee80211_hw
*hw
, u32 changed
)
2132 struct ath_softc
*sc
= hw
->priv
;
2133 struct ieee80211_conf
*conf
= &hw
->conf
;
2135 mutex_lock(&sc
->mutex
);
2136 if (changed
& (IEEE80211_CONF_CHANGE_CHANNEL
|
2137 IEEE80211_CONF_CHANGE_HT
)) {
2138 struct ieee80211_channel
*curchan
= hw
->conf
.channel
;
2141 DPRINTF(sc
, ATH_DBG_CONFIG
, "Set channel: %d MHz\n",
2142 curchan
->center_freq
);
2144 pos
= ath_get_channel(sc
, curchan
);
2146 DPRINTF(sc
, ATH_DBG_FATAL
, "Invalid channel: %d\n",
2147 curchan
->center_freq
);
2148 mutex_unlock(&sc
->mutex
);
2152 sc
->tx_chan_width
= ATH9K_HT_MACMODE_20
;
2153 sc
->sc_ah
->ah_channels
[pos
].chanmode
=
2154 (curchan
->band
== IEEE80211_BAND_2GHZ
) ?
2155 CHANNEL_G
: CHANNEL_A
;
2157 if (conf
->ht
.enabled
) {
2158 if (conf
->ht
.channel_type
== NL80211_CHAN_HT40PLUS
||
2159 conf
->ht
.channel_type
== NL80211_CHAN_HT40MINUS
)
2160 sc
->tx_chan_width
= ATH9K_HT_MACMODE_2040
;
2162 sc
->sc_ah
->ah_channels
[pos
].chanmode
=
2163 ath_get_extchanmode(sc
, curchan
,
2164 conf
->ht
.channel_type
);
2167 ath_update_chainmask(sc
, conf
->ht
.enabled
);
2169 if (ath_set_channel(sc
, &sc
->sc_ah
->ah_channels
[pos
]) < 0) {
2170 DPRINTF(sc
, ATH_DBG_FATAL
, "Unable to set channel\n");
2171 mutex_unlock(&sc
->mutex
);
2176 if (changed
& IEEE80211_CONF_CHANGE_POWER
)
2177 sc
->sc_config
.txpowlimit
= 2 * conf
->power_level
;
2179 mutex_unlock(&sc
->mutex
);
2183 static int ath9k_config_interface(struct ieee80211_hw
*hw
,
2184 struct ieee80211_vif
*vif
,
2185 struct ieee80211_if_conf
*conf
)
2187 struct ath_softc
*sc
= hw
->priv
;
2188 struct ath_hal
*ah
= sc
->sc_ah
;
2189 struct ath_vap
*avp
= (void *)vif
->drv_priv
;
2193 /* TODO: Need to decide which hw opmode to use for multi-interface
2195 if (vif
->type
== NL80211_IFTYPE_AP
&&
2196 ah
->ah_opmode
!= NL80211_IFTYPE_AP
) {
2197 ah
->ah_opmode
= NL80211_IFTYPE_STATION
;
2198 ath9k_hw_setopmode(ah
);
2199 ath9k_hw_write_associd(ah
, sc
->sc_myaddr
, 0);
2200 /* Request full reset to get hw opmode changed properly */
2201 sc
->sc_flags
|= SC_OP_FULL_RESET
;
2204 if ((conf
->changed
& IEEE80211_IFCC_BSSID
) &&
2205 !is_zero_ether_addr(conf
->bssid
)) {
2206 switch (vif
->type
) {
2207 case NL80211_IFTYPE_STATION
:
2208 case NL80211_IFTYPE_ADHOC
:
2210 memcpy(sc
->sc_curbssid
, conf
->bssid
, ETH_ALEN
);
2212 ath9k_hw_write_associd(sc
->sc_ah
, sc
->sc_curbssid
,
2215 /* Set aggregation protection mode parameters */
2216 sc
->sc_config
.ath_aggr_prot
= 0;
2218 DPRINTF(sc
, ATH_DBG_CONFIG
,
2219 "RX filter 0x%x bssid %pM aid 0x%x\n",
2220 rfilt
, sc
->sc_curbssid
, sc
->sc_curaid
);
2222 /* need to reconfigure the beacon */
2223 sc
->sc_flags
&= ~SC_OP_BEACONS
;
2231 if ((conf
->changed
& IEEE80211_IFCC_BEACON
) &&
2232 ((vif
->type
== NL80211_IFTYPE_ADHOC
) ||
2233 (vif
->type
== NL80211_IFTYPE_AP
))) {
2235 * Allocate and setup the beacon frame.
2237 * Stop any previous beacon DMA. This may be
2238 * necessary, for example, when an ibss merge
2239 * causes reconfiguration; we may be called
2240 * with beacon transmission active.
2242 ath9k_hw_stoptxdma(sc
->sc_ah
, sc
->beacon
.beaconq
);
2244 error
= ath_beacon_alloc(sc
, 0);
2248 ath_beacon_sync(sc
, 0);
2251 /* Check for WLAN_CAPABILITY_PRIVACY ? */
2252 if ((avp
->av_opmode
!= NL80211_IFTYPE_STATION
)) {
2253 for (i
= 0; i
< IEEE80211_WEP_NKID
; i
++)
2254 if (ath9k_hw_keyisvalid(sc
->sc_ah
, (u16
)i
))
2255 ath9k_hw_keysetmac(sc
->sc_ah
,
2260 /* Only legacy IBSS for now */
2261 if (vif
->type
== NL80211_IFTYPE_ADHOC
)
2262 ath_update_chainmask(sc
, 0);
2267 #define SUPPORTED_FILTERS \
2268 (FIF_PROMISC_IN_BSS | \
2272 FIF_BCN_PRBRESP_PROMISC | \
2275 /* FIXME: sc->sc_full_reset ? */
2276 static void ath9k_configure_filter(struct ieee80211_hw
*hw
,
2277 unsigned int changed_flags
,
2278 unsigned int *total_flags
,
2280 struct dev_mc_list
*mclist
)
2282 struct ath_softc
*sc
= hw
->priv
;
2285 changed_flags
&= SUPPORTED_FILTERS
;
2286 *total_flags
&= SUPPORTED_FILTERS
;
2288 sc
->rx
.rxfilter
= *total_flags
;
2289 rfilt
= ath_calcrxfilter(sc
);
2290 ath9k_hw_setrxfilter(sc
->sc_ah
, rfilt
);
2292 if (changed_flags
& FIF_BCN_PRBRESP_PROMISC
) {
2293 if (*total_flags
& FIF_BCN_PRBRESP_PROMISC
)
2294 ath9k_hw_write_associd(sc
->sc_ah
, ath_bcast_mac
, 0);
2297 DPRINTF(sc
, ATH_DBG_CONFIG
, "Set HW RX filter: 0x%x\n", sc
->rx
.rxfilter
);
2300 static void ath9k_sta_notify(struct ieee80211_hw
*hw
,
2301 struct ieee80211_vif
*vif
,
2302 enum sta_notify_cmd cmd
,
2303 struct ieee80211_sta
*sta
)
2305 struct ath_softc
*sc
= hw
->priv
;
2308 case STA_NOTIFY_ADD
:
2309 ath_node_attach(sc
, sta
);
2311 case STA_NOTIFY_REMOVE
:
2312 ath_node_detach(sc
, sta
);
2319 static int ath9k_conf_tx(struct ieee80211_hw
*hw
,
2321 const struct ieee80211_tx_queue_params
*params
)
2323 struct ath_softc
*sc
= hw
->priv
;
2324 struct ath9k_tx_queue_info qi
;
2327 if (queue
>= WME_NUM_AC
)
2330 qi
.tqi_aifs
= params
->aifs
;
2331 qi
.tqi_cwmin
= params
->cw_min
;
2332 qi
.tqi_cwmax
= params
->cw_max
;
2333 qi
.tqi_burstTime
= params
->txop
;
2334 qnum
= ath_get_hal_qnum(queue
, sc
);
2336 DPRINTF(sc
, ATH_DBG_CONFIG
,
2337 "Configure tx [queue/halq] [%d/%d], "
2338 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
2339 queue
, qnum
, params
->aifs
, params
->cw_min
,
2340 params
->cw_max
, params
->txop
);
2342 ret
= ath_txq_update(sc
, qnum
, &qi
);
2344 DPRINTF(sc
, ATH_DBG_FATAL
, "TXQ Update failed\n");
2349 static int ath9k_set_key(struct ieee80211_hw
*hw
,
2350 enum set_key_cmd cmd
,
2351 const u8
*local_addr
,
2353 struct ieee80211_key_conf
*key
)
2355 struct ath_softc
*sc
= hw
->priv
;
2358 DPRINTF(sc
, ATH_DBG_KEYCACHE
, "Set HW Key\n");
2362 ret
= ath_key_config(sc
, addr
, key
);
2364 key
->hw_key_idx
= ret
;
2365 /* push IV and Michael MIC generation to stack */
2366 key
->flags
|= IEEE80211_KEY_FLAG_GENERATE_IV
;
2367 if (key
->alg
== ALG_TKIP
)
2368 key
->flags
|= IEEE80211_KEY_FLAG_GENERATE_MMIC
;
2373 ath_key_delete(sc
, key
);
2382 static void ath9k_bss_info_changed(struct ieee80211_hw
*hw
,
2383 struct ieee80211_vif
*vif
,
2384 struct ieee80211_bss_conf
*bss_conf
,
2387 struct ath_softc
*sc
= hw
->priv
;
2389 if (changed
& BSS_CHANGED_ERP_PREAMBLE
) {
2390 DPRINTF(sc
, ATH_DBG_CONFIG
, "BSS Changed PREAMBLE %d\n",
2391 bss_conf
->use_short_preamble
);
2392 if (bss_conf
->use_short_preamble
)
2393 sc
->sc_flags
|= SC_OP_PREAMBLE_SHORT
;
2395 sc
->sc_flags
&= ~SC_OP_PREAMBLE_SHORT
;
2398 if (changed
& BSS_CHANGED_ERP_CTS_PROT
) {
2399 DPRINTF(sc
, ATH_DBG_CONFIG
, "BSS Changed CTS PROT %d\n",
2400 bss_conf
->use_cts_prot
);
2401 if (bss_conf
->use_cts_prot
&&
2402 hw
->conf
.channel
->band
!= IEEE80211_BAND_5GHZ
)
2403 sc
->sc_flags
|= SC_OP_PROTECT_ENABLE
;
2405 sc
->sc_flags
&= ~SC_OP_PROTECT_ENABLE
;
2408 if (changed
& BSS_CHANGED_ASSOC
) {
2409 DPRINTF(sc
, ATH_DBG_CONFIG
, "BSS Changed ASSOC %d\n",
2411 ath9k_bss_assoc_info(sc
, vif
, bss_conf
);
2415 static u64
ath9k_get_tsf(struct ieee80211_hw
*hw
)
2418 struct ath_softc
*sc
= hw
->priv
;
2419 struct ath_hal
*ah
= sc
->sc_ah
;
2421 tsf
= ath9k_hw_gettsf64(ah
);
2426 static void ath9k_reset_tsf(struct ieee80211_hw
*hw
)
2428 struct ath_softc
*sc
= hw
->priv
;
2429 struct ath_hal
*ah
= sc
->sc_ah
;
2431 ath9k_hw_reset_tsf(ah
);
2434 static int ath9k_ampdu_action(struct ieee80211_hw
*hw
,
2435 enum ieee80211_ampdu_mlme_action action
,
2436 struct ieee80211_sta
*sta
,
2439 struct ath_softc
*sc
= hw
->priv
;
2443 case IEEE80211_AMPDU_RX_START
:
2444 if (!(sc
->sc_flags
& SC_OP_RXAGGR
))
2447 case IEEE80211_AMPDU_RX_STOP
:
2449 case IEEE80211_AMPDU_TX_START
:
2450 ret
= ath_tx_aggr_start(sc
, sta
, tid
, ssn
);
2452 DPRINTF(sc
, ATH_DBG_FATAL
,
2453 "Unable to start TX aggregation\n");
2455 ieee80211_start_tx_ba_cb_irqsafe(hw
, sta
->addr
, tid
);
2457 case IEEE80211_AMPDU_TX_STOP
:
2458 ret
= ath_tx_aggr_stop(sc
, sta
, tid
);
2460 DPRINTF(sc
, ATH_DBG_FATAL
,
2461 "Unable to stop TX aggregation\n");
2463 ieee80211_stop_tx_ba_cb_irqsafe(hw
, sta
->addr
, tid
);
2465 case IEEE80211_AMPDU_TX_RESUME
:
2466 ath_tx_aggr_resume(sc
, sta
, tid
);
2469 DPRINTF(sc
, ATH_DBG_FATAL
, "Unknown AMPDU action\n");
2475 static struct ieee80211_ops ath9k_ops
= {
2477 .start
= ath9k_start
,
2479 .add_interface
= ath9k_add_interface
,
2480 .remove_interface
= ath9k_remove_interface
,
2481 .config
= ath9k_config
,
2482 .config_interface
= ath9k_config_interface
,
2483 .configure_filter
= ath9k_configure_filter
,
2484 .sta_notify
= ath9k_sta_notify
,
2485 .conf_tx
= ath9k_conf_tx
,
2486 .bss_info_changed
= ath9k_bss_info_changed
,
2487 .set_key
= ath9k_set_key
,
2488 .get_tsf
= ath9k_get_tsf
,
2489 .reset_tsf
= ath9k_reset_tsf
,
2490 .ampdu_action
= ath9k_ampdu_action
,
2496 } ath_mac_bb_names
[] = {
2497 { AR_SREV_VERSION_5416_PCI
, "5416" },
2498 { AR_SREV_VERSION_5416_PCIE
, "5418" },
2499 { AR_SREV_VERSION_9100
, "9100" },
2500 { AR_SREV_VERSION_9160
, "9160" },
2501 { AR_SREV_VERSION_9280
, "9280" },
2502 { AR_SREV_VERSION_9285
, "9285" }
2508 } ath_rf_names
[] = {
2510 { AR_RAD5133_SREV_MAJOR
, "5133" },
2511 { AR_RAD5122_SREV_MAJOR
, "5122" },
2512 { AR_RAD2133_SREV_MAJOR
, "2133" },
2513 { AR_RAD2122_SREV_MAJOR
, "2122" }
2517 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2520 ath_mac_bb_name(u32 mac_bb_version
)
2524 for (i
=0; i
<ARRAY_SIZE(ath_mac_bb_names
); i
++) {
2525 if (ath_mac_bb_names
[i
].version
== mac_bb_version
) {
2526 return ath_mac_bb_names
[i
].name
;
2534 * Return the RF name. "????" is returned if the RF is unknown.
2537 ath_rf_name(u16 rf_version
)
2541 for (i
=0; i
<ARRAY_SIZE(ath_rf_names
); i
++) {
2542 if (ath_rf_names
[i
].version
== rf_version
) {
2543 return ath_rf_names
[i
].name
;
2550 static int ath_pci_probe(struct pci_dev
*pdev
, const struct pci_device_id
*id
)
2553 struct ath_softc
*sc
;
2554 struct ieee80211_hw
*hw
;
2560 if (pci_enable_device(pdev
))
2563 ret
= pci_set_dma_mask(pdev
, DMA_32BIT_MASK
);
2566 printk(KERN_ERR
"ath9k: 32-bit DMA not available\n");
2570 ret
= pci_set_consistent_dma_mask(pdev
, DMA_32BIT_MASK
);
2573 printk(KERN_ERR
"ath9k: 32-bit DMA consistent "
2574 "DMA enable failed\n");
2579 * Cache line size is used to size and align various
2580 * structures used to communicate with the hardware.
2582 pci_read_config_byte(pdev
, PCI_CACHE_LINE_SIZE
, &csz
);
2585 * Linux 2.4.18 (at least) writes the cache line size
2586 * register as a 16-bit wide register which is wrong.
2587 * We must have this setup properly for rx buffer
2588 * DMA to work so force a reasonable value here if it
2591 csz
= L1_CACHE_BYTES
/ sizeof(u32
);
2592 pci_write_config_byte(pdev
, PCI_CACHE_LINE_SIZE
, csz
);
2595 * The default setting of latency timer yields poor results,
2596 * set it to the value used by other systems. It may be worth
2597 * tweaking this setting more.
2599 pci_write_config_byte(pdev
, PCI_LATENCY_TIMER
, 0xa8);
2601 pci_set_master(pdev
);
2604 * Disable the RETRY_TIMEOUT register (0x41) to keep
2605 * PCI Tx retries from interfering with C3 CPU state.
2607 pci_read_config_dword(pdev
, 0x40, &val
);
2608 if ((val
& 0x0000ff00) != 0)
2609 pci_write_config_dword(pdev
, 0x40, val
& 0xffff00ff);
2611 ret
= pci_request_region(pdev
, 0, "ath9k");
2613 dev_err(&pdev
->dev
, "PCI memory region reserve error\n");
2618 mem
= pci_iomap(pdev
, 0, 0);
2620 printk(KERN_ERR
"PCI memory map error\n") ;
2625 hw
= ieee80211_alloc_hw(sizeof(struct ath_softc
), &ath9k_ops
);
2627 printk(KERN_ERR
"ath_pci: no memory for ieee80211_hw\n");
2631 SET_IEEE80211_DEV(hw
, &pdev
->dev
);
2632 pci_set_drvdata(pdev
, hw
);
2639 if (ath_attach(id
->device
, sc
) != 0) {
2644 /* setup interrupt service routine */
2646 if (request_irq(pdev
->irq
, ath_isr
, IRQF_SHARED
, "ath", sc
)) {
2647 printk(KERN_ERR
"%s: request_irq failed\n",
2648 wiphy_name(hw
->wiphy
));
2655 "%s: Atheros AR%s MAC/BB Rev:%x "
2656 "AR%s RF Rev:%x: mem=0x%lx, irq=%d\n",
2657 wiphy_name(hw
->wiphy
),
2658 ath_mac_bb_name(ah
->ah_macVersion
),
2660 ath_rf_name((ah
->ah_analog5GhzRev
& AR_RADIO_SREV_MAJOR
)),
2662 (unsigned long)mem
, pdev
->irq
);
2668 ieee80211_free_hw(hw
);
2670 pci_iounmap(pdev
, mem
);
2672 pci_release_region(pdev
, 0);
2674 pci_disable_device(pdev
);
2678 static void ath_pci_remove(struct pci_dev
*pdev
)
2680 struct ieee80211_hw
*hw
= pci_get_drvdata(pdev
);
2681 struct ath_softc
*sc
= hw
->priv
;
2685 free_irq(pdev
->irq
, sc
);
2686 pci_iounmap(pdev
, sc
->mem
);
2687 pci_release_region(pdev
, 0);
2688 pci_disable_device(pdev
);
2689 ieee80211_free_hw(hw
);
2694 static int ath_pci_suspend(struct pci_dev
*pdev
, pm_message_t state
)
2696 struct ieee80211_hw
*hw
= pci_get_drvdata(pdev
);
2697 struct ath_softc
*sc
= hw
->priv
;
2699 ath9k_hw_set_gpio(sc
->sc_ah
, ATH_LED_PIN
, 1);
2701 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2702 if (sc
->sc_ah
->ah_caps
.hw_caps
& ATH9K_HW_CAP_RFSILENT
)
2703 cancel_delayed_work_sync(&sc
->rf_kill
.rfkill_poll
);
2706 pci_save_state(pdev
);
2707 pci_disable_device(pdev
);
2708 pci_set_power_state(pdev
, 3);
2713 static int ath_pci_resume(struct pci_dev
*pdev
)
2715 struct ieee80211_hw
*hw
= pci_get_drvdata(pdev
);
2716 struct ath_softc
*sc
= hw
->priv
;
2720 err
= pci_enable_device(pdev
);
2723 pci_restore_state(pdev
);
2725 * Suspend/Resume resets the PCI configuration space, so we have to
2726 * re-disable the RETRY_TIMEOUT register (0x41) to keep
2727 * PCI Tx retries from interfering with C3 CPU state
2729 pci_read_config_dword(pdev
, 0x40, &val
);
2730 if ((val
& 0x0000ff00) != 0)
2731 pci_write_config_dword(pdev
, 0x40, val
& 0xffff00ff);
2734 ath9k_hw_cfg_output(sc
->sc_ah
, ATH_LED_PIN
,
2735 AR_GPIO_OUTPUT_MUX_AS_OUTPUT
);
2736 ath9k_hw_set_gpio(sc
->sc_ah
, ATH_LED_PIN
, 1);
2738 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2740 * check the h/w rfkill state on resume
2741 * and start the rfkill poll timer
2743 if (sc
->sc_ah
->ah_caps
.hw_caps
& ATH9K_HW_CAP_RFSILENT
)
2744 queue_delayed_work(sc
->hw
->workqueue
,
2745 &sc
->rf_kill
.rfkill_poll
, 0);
2751 #endif /* CONFIG_PM */
2753 MODULE_DEVICE_TABLE(pci
, ath_pci_id_table
);
2755 static struct pci_driver ath_pci_driver
= {
2757 .id_table
= ath_pci_id_table
,
2758 .probe
= ath_pci_probe
,
2759 .remove
= ath_pci_remove
,
2761 .suspend
= ath_pci_suspend
,
2762 .resume
= ath_pci_resume
,
2763 #endif /* CONFIG_PM */
2766 static int __init
init_ath_pci(void)
2770 printk(KERN_INFO
"%s: %s\n", dev_info
, ATH_PCI_VERSION
);
2772 /* Register rate control algorithm */
2773 error
= ath_rate_control_register();
2776 "Unable to register rate control algorithm: %d\n",
2778 ath_rate_control_unregister();
2782 if (pci_register_driver(&ath_pci_driver
) < 0) {
2784 "ath_pci: No devices found, driver not installed.\n");
2785 ath_rate_control_unregister();
2786 pci_unregister_driver(&ath_pci_driver
);
2792 module_init(init_ath_pci
);
2794 static void __exit
exit_ath_pci(void)
2796 ath_rate_control_unregister();
2797 pci_unregister_driver(&ath_pci_driver
);
2798 printk(KERN_INFO
"%s: Driver unloaded\n", dev_info
);
2800 module_exit(exit_ath_pci
);