drivers/net/wireless/ath9k/pci.c

   1 /*
   2  * Copyright (c) 2008-2009 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/nl80211.h>
  18 #include <linux/pci.h>
  19 #include "ath9k.h"
  20
  21 static struct pci_device_id ath_pci_id_table[] __devinitdata = {
  22         { PCI_VDEVICE(ATHEROS, 0x0023) }, /* PCI   */
  23         { PCI_VDEVICE(ATHEROS, 0x0024) }, /* PCI-E */
  24         { PCI_VDEVICE(ATHEROS, 0x0027) }, /* PCI   */
  25         { PCI_VDEVICE(ATHEROS, 0x0029) }, /* PCI   */
  26         { PCI_VDEVICE(ATHEROS, 0x002A) }, /* PCI-E */
  27         { PCI_VDEVICE(ATHEROS, 0x002B) }, /* PCI-E */
  28         { 0 }
  29 };
  30
  31 /* return bus cachesize in 4B word units */
  32 static void ath_pci_read_cachesize(struct ath_softc *sc, int *csz)
  33 {
  34         u8 u8tmp;
  35
  36         pci_read_config_byte(to_pci_dev(sc->dev), PCI_CACHE_LINE_SIZE,
  37                              (u8 *)&u8tmp);
  38         *csz = (int)u8tmp;
  39
  40         /*
  41          * This check was put in to avoid "unplesant" consequences if
  42          * the bootrom has not fully initialized all PCI devices.
  43          * Sometimes the cache line size register is not set
  44          */
  45
  46         if (*csz == 0)
  47                 *csz = DEFAULT_CACHELINE >> 2;   /* Use the default size */
  48 }
  49
  50 static void ath_pci_cleanup(struct ath_softc *sc)
  51 {
  52         struct pci_dev *pdev = to_pci_dev(sc->dev);
  53
  54         pci_iounmap(pdev, sc->mem);
  55         pci_disable_device(pdev);
  56         pci_release_region(pdev, 0);
  57 }
  58
  59 static bool ath_pci_eeprom_read(struct ath_hw *ah, u32 off, u16 *data)
  60 {
  61         (void)REG_READ(ah, AR5416_EEPROM_OFFSET + (off << AR5416_EEPROM_S));
  62
  63         if (!ath9k_hw_wait(ah,
  64                            AR_EEPROM_STATUS_DATA,
  65                            AR_EEPROM_STATUS_DATA_BUSY |
  66                            AR_EEPROM_STATUS_DATA_PROT_ACCESS, 0,
  67                            AH_WAIT_TIMEOUT)) {
  68                 return false;
  69         }
  70
  71         *data = MS(REG_READ(ah, AR_EEPROM_STATUS_DATA),
  72                    AR_EEPROM_STATUS_DATA_VAL);
  73
  74         return true;
  75 }
  76
  77 static struct ath_bus_ops ath_pci_bus_ops = {
  78         .read_cachesize = ath_pci_read_cachesize,
  79         .cleanup = ath_pci_cleanup,
  80         .eeprom_read = ath_pci_eeprom_read,
  81 };
  82
  83 static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
  84 {
  85         void __iomem *mem;
  86         struct ath_wiphy *aphy;
  87         struct ath_softc *sc;
  88         struct ieee80211_hw *hw;
  89         u8 csz;
  90         int ret = 0;
  91         struct ath_hw *ah;
  92
  93         if (pci_enable_device(pdev))
  94                 return -EIO;
  95
  96         ret =  pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
  97
  98         if (ret) {
  99                 printk(KERN_ERR "ath9k: 32-bit DMA not available\n");
 100                 goto bad;
 101         }
 102
 103         ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
 104
 105         if (ret) {
 106                 printk(KERN_ERR "ath9k: 32-bit DMA consistent "
 107                         "DMA enable failed\n");
 108                 goto bad;
 109         }
 110
 111         /*
 112          * Cache line size is used to size and align various
 113          * structures used to communicate with the hardware.
 114          */
 115         pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
 116         if (csz == 0) {
 117                 /*
 118                  * Linux 2.4.18 (at least) writes the cache line size
 119                  * register as a 16-bit wide register which is wrong.
 120                  * We must have this setup properly for rx buffer
 121                  * DMA to work so force a reasonable value here if it
 122                  * comes up zero.
 123                  */
 124                 csz = L1_CACHE_BYTES / sizeof(u32);
 125                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
 126         }
 127         /*
 128          * The default setting of latency timer yields poor results,
 129          * set it to the value used by other systems. It may be worth
 130          * tweaking this setting more.
 131          */
 132         pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
 133
 134         pci_set_master(pdev);
 135
 136         ret = pci_request_region(pdev, 0, "ath9k");
 137         if (ret) {
 138                 dev_err(&pdev->dev, "PCI memory region reserve error\n");
 139                 ret = -ENODEV;
 140                 goto bad;
 141         }
 142
 143         mem = pci_iomap(pdev, 0, 0);
 144         if (!mem) {
 145                 printk(KERN_ERR "PCI memory map error\n") ;
 146                 ret = -EIO;
 147                 goto bad1;
 148         }
 149
 150         hw = ieee80211_alloc_hw(sizeof(struct ath_wiphy) +
 151                                 sizeof(struct ath_softc), &ath9k_ops);
 152         if (hw == NULL) {
 153                 printk(KERN_ERR "ath_pci: no memory for ieee80211_hw\n");
 154                 goto bad2;
 155         }
 156
 157         SET_IEEE80211_DEV(hw, &pdev->dev);
 158         pci_set_drvdata(pdev, hw);
 159
 160         aphy = hw->priv;
 161         sc = (struct ath_softc *) (aphy + 1);
 162         aphy->sc = sc;
 163         aphy->hw = hw;
 164         sc->pri_wiphy = aphy;
 165         sc->hw = hw;
 166         sc->dev = &pdev->dev;
 167         sc->mem = mem;
 168         sc->bus_ops = &ath_pci_bus_ops;
 169
 170         if (ath_attach(id->device, sc) != 0) {
 171                 ret = -ENODEV;
 172                 goto bad3;
 173         }
 174
 175         /* setup interrupt service routine */
 176
 177         if (request_irq(pdev->irq, ath_isr, IRQF_SHARED, "ath", sc)) {
 178                 printk(KERN_ERR "%s: request_irq failed\n",
 179                         wiphy_name(hw->wiphy));
 180                 ret = -EIO;
 181                 goto bad4;
 182         }
 183
 184         sc->irq = pdev->irq;
 185
 186         ah = sc->sc_ah;
 187         printk(KERN_INFO
 188                "%s: Atheros AR%s MAC/BB Rev:%x "
 189                "AR%s RF Rev:%x: mem=0x%lx, irq=%d\n",
 190                wiphy_name(hw->wiphy),
 191                ath_mac_bb_name(ah->hw_version.macVersion),
 192                ah->hw_version.macRev,
 193                ath_rf_name((ah->hw_version.analog5GhzRev & AR_RADIO_SREV_MAJOR)),
 194                ah->hw_version.phyRev,
 195                (unsigned long)mem, pdev->irq);
 196
 197         return 0;
 198 bad4:
 199         ath_detach(sc);
 200 bad3:
 201         ieee80211_free_hw(hw);
 202 bad2:
 203         pci_iounmap(pdev, mem);
 204 bad1:
 205         pci_release_region(pdev, 0);
 206 bad:
 207         pci_disable_device(pdev);
 208         return ret;
 209 }
 210
 211 static void ath_pci_remove(struct pci_dev *pdev)
 212 {
 213         struct ieee80211_hw *hw = pci_get_drvdata(pdev);
 214         struct ath_wiphy *aphy = hw->priv;
 215         struct ath_softc *sc = aphy->sc;
 216
 217         ath_cleanup(sc);
 218 }
 219
 220 #ifdef CONFIG_PM
 221
 222 static int ath_pci_suspend(struct pci_dev *pdev, pm_message_t state)
 223 {
 224         struct ieee80211_hw *hw = pci_get_drvdata(pdev);
 225         struct ath_wiphy *aphy = hw->priv;
 226         struct ath_softc *sc = aphy->sc;
 227
 228         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
 229
 230 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
 231         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
 232                 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
 233 #endif
 234
 235         pci_save_state(pdev);
 236         pci_disable_device(pdev);
 237         pci_set_power_state(pdev, PCI_D3hot);
 238
 239         return 0;
 240 }
 241
 242 static int ath_pci_resume(struct pci_dev *pdev)
 243 {
 244         struct ieee80211_hw *hw = pci_get_drvdata(pdev);
 245         struct ath_wiphy *aphy = hw->priv;
 246         struct ath_softc *sc = aphy->sc;
 247         int err;
 248
 249         err = pci_enable_device(pdev);
 250         if (err)
 251                 return err;
 252         pci_restore_state(pdev);
 253
 254         /* Enable LED */
 255         ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
 256                             AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
 257         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
 258
 259 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
 260         /*
 261          * check the h/w rfkill state on resume
 262          * and start the rfkill poll timer
 263          */
 264         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
 265                 queue_delayed_work(sc->hw->workqueue,
 266                                    &sc->rf_kill.rfkill_poll, 0);
 267 #endif
 268
 269         return 0;
 270 }
 271
 272 #endif /* CONFIG_PM */
 273
 274 MODULE_DEVICE_TABLE(pci, ath_pci_id_table);
 275
 276 static struct pci_driver ath_pci_driver = {
 277         .name       = "ath9k",
 278         .id_table   = ath_pci_id_table,
 279         .probe      = ath_pci_probe,
 280         .remove     = ath_pci_remove,
 281 #ifdef CONFIG_PM
 282         .suspend    = ath_pci_suspend,
 283         .resume     = ath_pci_resume,
 284 #endif /* CONFIG_PM */
 285 };
 286
 287 int ath_pci_init(void)
 288 {
 289         return pci_register_driver(&ath_pci_driver);
 290 }
 291
 292 void ath_pci_exit(void)
 293 {
 294         pci_unregister_driver(&ath_pci_driver);
 295 }