drivers/net/wireless/ath9k/recv.c

   1 /*
   2  * Copyright (c) 2008 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include "ath9k.h"
  18
  19 static struct ieee80211_hw * ath_get_virt_hw(struct ath_softc *sc,
  20                                              struct ieee80211_hdr *hdr)
  21 {
  22         struct ieee80211_hw *hw = sc->pri_wiphy->hw;
  23         int i;
  24
  25         spin_lock_bh(&sc->wiphy_lock);
  26         for (i = 0; i < sc->num_sec_wiphy; i++) {
  27                 struct ath_wiphy *aphy = sc->sec_wiphy[i];
  28                 if (aphy == NULL)
  29                         continue;
  30                 if (compare_ether_addr(hdr->addr1, aphy->hw->wiphy->perm_addr)
  31                     == 0) {
  32                         hw = aphy->hw;
  33                         break;
  34                 }
  35         }
  36         spin_unlock_bh(&sc->wiphy_lock);
  37         return hw;
  38 }
  39
  40 /*
  41  * Setup and link descriptors.
  42  *
  43  * 11N: we can no longer afford to self link the last descriptor.
  44  * MAC acknowledges BA status as long as it copies frames to host
  45  * buffer (or rx fifo). This can incorrectly acknowledge packets
  46  * to a sender if last desc is self-linked.
  47  */
  48 static void ath_rx_buf_link(struct ath_softc *sc, struct ath_buf *bf)
  49 {
  50         struct ath_hw *ah = sc->sc_ah;
  51         struct ath_desc *ds;
  52         struct sk_buff *skb;
  53
  54         ATH_RXBUF_RESET(bf);
  55
  56         ds = bf->bf_desc;
  57         ds->ds_link = 0; /* link to null */
  58         ds->ds_data = bf->bf_buf_addr;
  59
  60         /* virtual addr of the beginning of the buffer. */
  61         skb = bf->bf_mpdu;
  62         ASSERT(skb != NULL);
  63         ds->ds_vdata = skb->data;
  64
  65         /* setup rx descriptors. The rx.bufsize here tells the harware
  66          * how much data it can DMA to us and that we are prepared
  67          * to process */
  68         ath9k_hw_setuprxdesc(ah, ds,
  69                              sc->rx.bufsize,
  70                              0);
  71
  72         if (sc->rx.rxlink == NULL)
  73                 ath9k_hw_putrxbuf(ah, bf->bf_daddr);
  74         else
  75                 *sc->rx.rxlink = bf->bf_daddr;
  76
  77         sc->rx.rxlink = &ds->ds_link;
  78         ath9k_hw_rxena(ah);
  79 }
  80
  81 static void ath_setdefantenna(struct ath_softc *sc, u32 antenna)
  82 {
  83         /* XXX block beacon interrupts */
  84         ath9k_hw_setantenna(sc->sc_ah, antenna);
  85         sc->rx.defant = antenna;
  86         sc->rx.rxotherant = 0;
  87 }
  88
  89 /*
  90  *  Extend 15-bit time stamp from rx descriptor to
  91  *  a full 64-bit TSF using the current h/w TSF.
  92 */
  93 static u64 ath_extend_tsf(struct ath_softc *sc, u32 rstamp)
  94 {
  95         u64 tsf;
  96
  97         tsf = ath9k_hw_gettsf64(sc->sc_ah);
  98         if ((tsf & 0x7fff) < rstamp)
  99                 tsf -= 0x8000;
 100         return (tsf & ~0x7fff) | rstamp;
 101 }
 102
 103 static struct sk_buff *ath_rxbuf_alloc(struct ath_softc *sc, u32 len)
 104 {
 105         struct sk_buff *skb;
 106         u32 off;
 107
 108         /*
 109          * Cache-line-align.  This is important (for the
 110          * 5210 at least) as not doing so causes bogus data
 111          * in rx'd frames.
 112          */
 113
 114         /* Note: the kernel can allocate a value greater than
 115          * what we ask it to give us. We really only need 4 KB as that
 116          * is this hardware supports and in fact we need at least 3849
 117          * as that is the MAX AMSDU size this hardware supports.
 118          * Unfortunately this means we may get 8 KB here from the
 119          * kernel... and that is actually what is observed on some
 120          * systems :( */
 121         skb = dev_alloc_skb(len + sc->cachelsz - 1);
 122         if (skb != NULL) {
 123                 off = ((unsigned long) skb->data) % sc->cachelsz;
 124                 if (off != 0)
 125                         skb_reserve(skb, sc->cachelsz - off);
 126         } else {
 127                 DPRINTF(sc, ATH_DBG_FATAL,
 128                         "skbuff alloc of size %u failed\n", len);
 129                 return NULL;
 130         }
 131
 132         return skb;
 133 }
 134
 135 /*
 136  * For Decrypt or Demic errors, we only mark packet status here and always push
 137  * up the frame up to let mac80211 handle the actual error case, be it no
 138  * decryption key or real decryption error. This let us keep statistics there.
 139  */
 140 static int ath_rx_prepare(struct sk_buff *skb, struct ath_desc *ds,
 141                           struct ieee80211_rx_status *rx_status, bool *decrypt_error,
 142                           struct ath_softc *sc)
 143 {
 144         struct ieee80211_hdr *hdr;
 145         u8 ratecode;
 146         __le16 fc;
 147         struct ieee80211_hw *hw;
 148
 149         hdr = (struct ieee80211_hdr *)skb->data;
 150         fc = hdr->frame_control;
 151         memset(rx_status, 0, sizeof(struct ieee80211_rx_status));
 152         hw = ath_get_virt_hw(sc, hdr);
 153
 154         if (ds->ds_rxstat.rs_more) {
 155                 /*
 156                  * Frame spans multiple descriptors; this cannot happen yet
 157                  * as we don't support jumbograms. If not in monitor mode,
 158                  * discard the frame. Enable this if you want to see
 159                  * error frames in Monitor mode.
 160                  */
 161                 if (sc->sc_ah->opmode != NL80211_IFTYPE_MONITOR)
 162                         goto rx_next;
 163         } else if (ds->ds_rxstat.rs_status != 0) {
 164                 if (ds->ds_rxstat.rs_status & ATH9K_RXERR_CRC)
 165                         rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
 166                 if (ds->ds_rxstat.rs_status & ATH9K_RXERR_PHY)
 167                         goto rx_next;
 168
 169                 if (ds->ds_rxstat.rs_status & ATH9K_RXERR_DECRYPT) {
 170                         *decrypt_error = true;
 171                 } else if (ds->ds_rxstat.rs_status & ATH9K_RXERR_MIC) {
 172                         if (ieee80211_is_ctl(fc))
 173                                 /*
 174                                  * Sometimes, we get invalid
 175                                  * MIC failures on valid control frames.
 176                                  * Remove these mic errors.
 177                                  */
 178                                 ds->ds_rxstat.rs_status &= ~ATH9K_RXERR_MIC;
 179                         else
 180                                 rx_status->flag |= RX_FLAG_MMIC_ERROR;
 181                 }
 182                 /*
 183                  * Reject error frames with the exception of
 184                  * decryption and MIC failures. For monitor mode,
 185                  * we also ignore the CRC error.
 186                  */
 187                 if (sc->sc_ah->opmode == NL80211_IFTYPE_MONITOR) {
 188                         if (ds->ds_rxstat.rs_status &
 189                             ~(ATH9K_RXERR_DECRYPT | ATH9K_RXERR_MIC |
 190                               ATH9K_RXERR_CRC))
 191                                 goto rx_next;
 192                 } else {
 193                         if (ds->ds_rxstat.rs_status &
 194                             ~(ATH9K_RXERR_DECRYPT | ATH9K_RXERR_MIC)) {
 195                                 goto rx_next;
 196                         }
 197                 }
 198         }
 199
 200         ratecode = ds->ds_rxstat.rs_rate;
 201
 202         if (ratecode & 0x80) {
 203                 /* HT rate */
 204                 rx_status->flag |= RX_FLAG_HT;
 205                 if (ds->ds_rxstat.rs_flags & ATH9K_RX_2040)
 206                         rx_status->flag |= RX_FLAG_40MHZ;
 207                 if (ds->ds_rxstat.rs_flags & ATH9K_RX_GI)
 208                         rx_status->flag |= RX_FLAG_SHORT_GI;
 209                 rx_status->rate_idx = ratecode & 0x7f;
 210         } else {
 211                 int i = 0, cur_band, n_rates;
 212
 213                 cur_band = hw->conf.channel->band;
 214                 n_rates = sc->sbands[cur_band].n_bitrates;
 215
 216                 for (i = 0; i < n_rates; i++) {
 217                         if (sc->sbands[cur_band].bitrates[i].hw_value ==
 218                             ratecode) {
 219                                 rx_status->rate_idx = i;
 220                                 break;
 221                         }
 222
 223                         if (sc->sbands[cur_band].bitrates[i].hw_value_short ==
 224                             ratecode) {
 225                                 rx_status->rate_idx = i;
 226                                 rx_status->flag |= RX_FLAG_SHORTPRE;
 227                                 break;
 228                         }
 229                 }
 230         }
 231
 232         rx_status->mactime = ath_extend_tsf(sc, ds->ds_rxstat.rs_tstamp);
 233         rx_status->band = hw->conf.channel->band;
 234         rx_status->freq = hw->conf.channel->center_freq;
 235         rx_status->noise = sc->ani.noise_floor;
 236         rx_status->signal = rx_status->noise + ds->ds_rxstat.rs_rssi;
 237         rx_status->antenna = ds->ds_rxstat.rs_antenna;
 238
 239         /* at 45 you will be able to use MCS 15 reliably. A more elaborate
 240          * scheme can be used here but it requires tables of SNR/throughput for
 241          * each possible mode used. */
 242         rx_status->qual =  ds->ds_rxstat.rs_rssi * 100 / 45;
 243
 244         /* rssi can be more than 45 though, anything above that
 245          * should be considered at 100% */
 246         if (rx_status->qual > 100)
 247                 rx_status->qual = 100;
 248
 249         rx_status->flag |= RX_FLAG_TSFT;
 250
 251         return 1;
 252 rx_next:
 253         return 0;
 254 }
 255
 256 static void ath_opmode_init(struct ath_softc *sc)
 257 {
 258         struct ath_hw *ah = sc->sc_ah;
 259         u32 rfilt, mfilt[2];
 260
 261         /* configure rx filter */
 262         rfilt = ath_calcrxfilter(sc);
 263         ath9k_hw_setrxfilter(ah, rfilt);
 264
 265         /* configure bssid mask */
 266         if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
 267                 ath9k_hw_setbssidmask(sc);
 268
 269         /* configure operational mode */
 270         ath9k_hw_setopmode(ah);
 271
 272         /* Handle any link-level address change. */
 273         ath9k_hw_setmac(ah, sc->sc_ah->macaddr);
 274
 275         /* calculate and install multicast filter */
 276         mfilt[0] = mfilt[1] = ~0;
 277         ath9k_hw_setmcastfilter(ah, mfilt[0], mfilt[1]);
 278 }
 279
 280 int ath_rx_init(struct ath_softc *sc, int nbufs)
 281 {
 282         struct sk_buff *skb;
 283         struct ath_buf *bf;
 284         int error = 0;
 285
 286         do {
 287                 spin_lock_init(&sc->rx.rxflushlock);
 288                 sc->sc_flags &= ~SC_OP_RXFLUSH;
 289                 spin_lock_init(&sc->rx.rxbuflock);
 290
 291                 sc->rx.bufsize = roundup(IEEE80211_MAX_MPDU_LEN,
 292                                            min(sc->cachelsz,
 293                                                (u16)64));
 294
 295                 DPRINTF(sc, ATH_DBG_CONFIG, "cachelsz %u rxbufsize %u\n",
 296                         sc->cachelsz, sc->rx.bufsize);
 297
 298                 /* Initialize rx descriptors */
 299
 300                 error = ath_descdma_setup(sc, &sc->rx.rxdma, &sc->rx.rxbuf,
 301                                           "rx", nbufs, 1);
 302                 if (error != 0) {
 303                         DPRINTF(sc, ATH_DBG_FATAL,
 304                                 "failed to allocate rx descriptors: %d\n", error);
 305                         break;
 306                 }
 307
 308                 list_for_each_entry(bf, &sc->rx.rxbuf, list) {
 309                         skb = ath_rxbuf_alloc(sc, sc->rx.bufsize);
 310                         if (skb == NULL) {
 311                                 error = -ENOMEM;
 312                                 break;
 313                         }
 314
 315                         bf->bf_mpdu = skb;
 316                         bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
 317                                                          sc->rx.bufsize,
 318                                                          DMA_FROM_DEVICE);
 319                         if (unlikely(dma_mapping_error(sc->dev,
 320                                   bf->bf_buf_addr))) {
 321                                 dev_kfree_skb_any(skb);
 322                                 bf->bf_mpdu = NULL;
 323                                 DPRINTF(sc, ATH_DBG_CONFIG,
 324                                         "dma_mapping_error() on RX init\n");
 325                                 error = -ENOMEM;
 326                                 break;
 327                         }
 328                         bf->bf_dmacontext = bf->bf_buf_addr;
 329                 }
 330                 sc->rx.rxlink = NULL;
 331
 332         } while (0);
 333
 334         if (error)
 335                 ath_rx_cleanup(sc);
 336
 337         return error;
 338 }
 339
 340 void ath_rx_cleanup(struct ath_softc *sc)
 341 {
 342         struct sk_buff *skb;
 343         struct ath_buf *bf;
 344
 345         list_for_each_entry(bf, &sc->rx.rxbuf, list) {
 346                 skb = bf->bf_mpdu;
 347                 if (skb)
 348                         dev_kfree_skb(skb);
 349         }
 350
 351         if (sc->rx.rxdma.dd_desc_len != 0)
 352                 ath_descdma_cleanup(sc, &sc->rx.rxdma, &sc->rx.rxbuf);
 353 }
 354
 355 /*
 356  * Calculate the receive filter according to the
 357  * operating mode and state:
 358  *
 359  * o always accept unicast, broadcast, and multicast traffic
 360  * o maintain current state of phy error reception (the hal
 361  *   may enable phy error frames for noise immunity work)
 362  * o probe request frames are accepted only when operating in
 363  *   hostap, adhoc, or monitor modes
 364  * o enable promiscuous mode according to the interface state
 365  * o accept beacons:
 366  *   - when operating in adhoc mode so the 802.11 layer creates
 367  *     node table entries for peers,
 368  *   - when operating in station mode for collecting rssi data when
 369  *     the station is otherwise quiet, or
 370  *   - when operating as a repeater so we see repeater-sta beacons
 371  *   - when scanning
 372  */
 373
 374 u32 ath_calcrxfilter(struct ath_softc *sc)
 375 {
 376 #define RX_FILTER_PRESERVE (ATH9K_RX_FILTER_PHYERR | ATH9K_RX_FILTER_PHYRADAR)
 377
 378         u32 rfilt;
 379
 380         rfilt = (ath9k_hw_getrxfilter(sc->sc_ah) & RX_FILTER_PRESERVE)
 381                 | ATH9K_RX_FILTER_UCAST | ATH9K_RX_FILTER_BCAST
 382                 | ATH9K_RX_FILTER_MCAST;
 383
 384         /* If not a STA, enable processing of Probe Requests */
 385         if (sc->sc_ah->opmode != NL80211_IFTYPE_STATION)
 386                 rfilt |= ATH9K_RX_FILTER_PROBEREQ;
 387
 388         /* Can't set HOSTAP into promiscous mode */
 389         if (((sc->sc_ah->opmode != NL80211_IFTYPE_AP) &&
 390              (sc->rx.rxfilter & FIF_PROMISC_IN_BSS)) ||
 391             (sc->sc_ah->opmode == NL80211_IFTYPE_MONITOR)) {
 392                 rfilt |= ATH9K_RX_FILTER_PROM;
 393                 /* ??? To prevent from sending ACK */
 394                 rfilt &= ~ATH9K_RX_FILTER_UCAST;
 395         }
 396
 397         if (sc->rx.rxfilter & FIF_CONTROL)
 398                 rfilt |= ATH9K_RX_FILTER_CONTROL;
 399
 400         if ((sc->sc_ah->opmode == NL80211_IFTYPE_STATION) &&
 401             !(sc->rx.rxfilter & FIF_BCN_PRBRESP_PROMISC))
 402                 rfilt |= ATH9K_RX_FILTER_MYBEACON;
 403         else
 404                 rfilt |= ATH9K_RX_FILTER_BEACON;
 405
 406         /* If in HOSTAP mode, want to enable reception of PSPOLL frames */
 407         if (sc->sc_ah->opmode == NL80211_IFTYPE_AP)
 408                 rfilt |= ATH9K_RX_FILTER_PSPOLL;
 409
 410         return rfilt;
 411
 412 #undef RX_FILTER_PRESERVE
 413 }
 414
 415 int ath_startrecv(struct ath_softc *sc)
 416 {
 417         struct ath_hw *ah = sc->sc_ah;
 418         struct ath_buf *bf, *tbf;
 419
 420         spin_lock_bh(&sc->rx.rxbuflock);
 421         if (list_empty(&sc->rx.rxbuf))
 422                 goto start_recv;
 423
 424         sc->rx.rxlink = NULL;
 425         list_for_each_entry_safe(bf, tbf, &sc->rx.rxbuf, list) {
 426                 ath_rx_buf_link(sc, bf);
 427         }
 428
 429         /* We could have deleted elements so the list may be empty now */
 430         if (list_empty(&sc->rx.rxbuf))
 431                 goto start_recv;
 432
 433         bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list);
 434         ath9k_hw_putrxbuf(ah, bf->bf_daddr);
 435         ath9k_hw_rxena(ah);
 436
 437 start_recv:
 438         spin_unlock_bh(&sc->rx.rxbuflock);
 439         ath_opmode_init(sc);
 440         ath9k_hw_startpcureceive(ah);
 441
 442         return 0;
 443 }
 444
 445 bool ath_stoprecv(struct ath_softc *sc)
 446 {
 447         struct ath_hw *ah = sc->sc_ah;
 448         bool stopped;
 449
 450         ath9k_hw_stoppcurecv(ah);
 451         ath9k_hw_setrxfilter(ah, 0);
 452         stopped = ath9k_hw_stopdmarecv(ah);
 453         sc->rx.rxlink = NULL;
 454
 455         return stopped;
 456 }
 457
 458 void ath_flushrecv(struct ath_softc *sc)
 459 {
 460         spin_lock_bh(&sc->rx.rxflushlock);
 461         sc->sc_flags |= SC_OP_RXFLUSH;
 462         ath_rx_tasklet(sc, 1);
 463         sc->sc_flags &= ~SC_OP_RXFLUSH;
 464         spin_unlock_bh(&sc->rx.rxflushlock);
 465 }
 466
 467 int ath_rx_tasklet(struct ath_softc *sc, int flush)
 468 {
 469 #define PA2DESC(_sc, _pa)                                               \
 470         ((struct ath_desc *)((caddr_t)(_sc)->rx.rxdma.dd_desc +         \
 471                              ((_pa) - (_sc)->rx.rxdma.dd_desc_paddr)))
 472
 473         struct ath_buf *bf;
 474         struct ath_desc *ds;
 475         struct sk_buff *skb = NULL, *requeue_skb;
 476         struct ieee80211_rx_status rx_status;
 477         struct ath_hw *ah = sc->sc_ah;
 478         struct ieee80211_hdr *hdr;
 479         int hdrlen, padsize, retval;
 480         bool decrypt_error = false;
 481         u8 keyix;
 482
 483         spin_lock_bh(&sc->rx.rxbuflock);
 484
 485         do {
 486                 /* If handling rx interrupt and flush is in progress => exit */
 487                 if ((sc->sc_flags & SC_OP_RXFLUSH) && (flush == 0))
 488                         break;
 489
 490                 if (list_empty(&sc->rx.rxbuf)) {
 491                         sc->rx.rxlink = NULL;
 492                         break;
 493                 }
 494
 495                 bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list);
 496                 ds = bf->bf_desc;
 497
 498                 /*
 499                  * Must provide the virtual address of the current
 500                  * descriptor, the physical address, and the virtual
 501                  * address of the next descriptor in the h/w chain.
 502                  * This allows the HAL to look ahead to see if the
 503                  * hardware is done with a descriptor by checking the
 504                  * done bit in the following descriptor and the address
 505                  * of the current descriptor the DMA engine is working
 506                  * on.  All this is necessary because of our use of
 507                  * a self-linked list to avoid rx overruns.
 508                  */
 509                 retval = ath9k_hw_rxprocdesc(ah, ds,
 510                                              bf->bf_daddr,
 511                                              PA2DESC(sc, ds->ds_link),
 512                                              0);
 513                 if (retval == -EINPROGRESS) {
 514                         struct ath_buf *tbf;
 515                         struct ath_desc *tds;
 516
 517                         if (list_is_last(&bf->list, &sc->rx.rxbuf)) {
 518                                 sc->rx.rxlink = NULL;
 519                                 break;
 520                         }
 521
 522                         tbf = list_entry(bf->list.next, struct ath_buf, list);
 523
 524                         /*
 525                          * On some hardware the descriptor status words could
 526                          * get corrupted, including the done bit. Because of
 527                          * this, check if the next descriptor's done bit is
 528                          * set or not.
 529                          *
 530                          * If the next descriptor's done bit is set, the current
 531                          * descriptor has been corrupted. Force s/w to discard
 532                          * this descriptor and continue...
 533                          */
 534
 535                         tds = tbf->bf_desc;
 536                         retval = ath9k_hw_rxprocdesc(ah, tds, tbf->bf_daddr,
 537                                              PA2DESC(sc, tds->ds_link), 0);
 538                         if (retval == -EINPROGRESS) {
 539                                 break;
 540                         }
 541                 }
 542
 543                 skb = bf->bf_mpdu;
 544                 if (!skb)
 545                         continue;
 546
 547                 /*
 548                  * Synchronize the DMA transfer with CPU before
 549                  * 1. accessing the frame
 550                  * 2. requeueing the same buffer to h/w
 551                  */
 552                 dma_sync_single_for_cpu(sc->dev, bf->bf_buf_addr,
 553                                 sc->rx.bufsize,
 554                                 DMA_FROM_DEVICE);
 555
 556                 /*
 557                  * If we're asked to flush receive queue, directly
 558                  * chain it back at the queue without processing it.
 559                  */
 560                 if (flush)
 561                         goto requeue;
 562
 563                 if (!ds->ds_rxstat.rs_datalen)
 564                         goto requeue;
 565
 566                 /* The status portion of the descriptor could get corrupted. */
 567                 if (sc->rx.bufsize < ds->ds_rxstat.rs_datalen)
 568                         goto requeue;
 569
 570                 if (!ath_rx_prepare(skb, ds, &rx_status, &decrypt_error, sc))
 571                         goto requeue;
 572
 573                 /* Ensure we always have an skb to requeue once we are done
 574                  * processing the current buffer's skb */
 575                 requeue_skb = ath_rxbuf_alloc(sc, sc->rx.bufsize);
 576
 577                 /* If there is no memory we ignore the current RX'd frame,
 578                  * tell hardware it can give us a new frame using the old
 579                  * skb and put it at the tail of the sc->rx.rxbuf list for
 580                  * processing. */
 581                 if (!requeue_skb)
 582                         goto requeue;
 583
 584                 /* Unmap the frame */
 585                 dma_unmap_single(sc->dev, bf->bf_buf_addr,
 586                                  sc->rx.bufsize,
 587                                  DMA_FROM_DEVICE);
 588
 589                 skb_put(skb, ds->ds_rxstat.rs_datalen);
 590                 skb->protocol = cpu_to_be16(ETH_P_CONTROL);
 591
 592                 /* see if any padding is done by the hw and remove it */
 593                 hdr = (struct ieee80211_hdr *)skb->data;
 594                 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
 595
 596                 /* The MAC header is padded to have 32-bit boundary if the
 597                  * packet payload is non-zero. The general calculation for
 598                  * padsize would take into account odd header lengths:
 599                  * padsize = (4 - hdrlen % 4) % 4; However, since only
 600                  * even-length headers are used, padding can only be 0 or 2
 601                  * bytes and we can optimize this a bit. In addition, we must
 602                  * not try to remove padding from short control frames that do
 603                  * not have payload. */
 604                 padsize = hdrlen & 3;
 605                 if (padsize && hdrlen >= 24) {
 606                         memmove(skb->data + padsize, skb->data, hdrlen);
 607                         skb_pull(skb, padsize);
 608                 }
 609
 610                 keyix = ds->ds_rxstat.rs_keyix;
 611
 612                 if (!(keyix == ATH9K_RXKEYIX_INVALID) && !decrypt_error) {
 613                         rx_status.flag |= RX_FLAG_DECRYPTED;
 614                 } else if ((le16_to_cpu(hdr->frame_control) & IEEE80211_FCTL_PROTECTED)
 615                            && !decrypt_error && skb->len >= hdrlen + 4) {
 616                         keyix = skb->data[hdrlen + 3] >> 6;
 617
 618                         if (test_bit(keyix, sc->keymap))
 619                                 rx_status.flag |= RX_FLAG_DECRYPTED;
 620                 }
 621                 if (ah->sw_mgmt_crypto &&
 622                     (rx_status.flag & RX_FLAG_DECRYPTED) &&
 623                     ieee80211_is_mgmt(hdr->frame_control)) {
 624                         /* Use software decrypt for management frames. */
 625                         rx_status.flag &= ~RX_FLAG_DECRYPTED;
 626                 }
 627
 628                 /* Send the frame to mac80211 */
 629                 if (hdr->addr1[5] & 0x01) {
 630                         int i;
 631                         /*
 632                          * Deliver broadcast/multicast frames to all suitable
 633                          * virtual wiphys.
 634                          */
 635                         /* TODO: filter based on channel configuration */
 636                         for (i = 0; i < sc->num_sec_wiphy; i++) {
 637                                 struct ath_wiphy *aphy = sc->sec_wiphy[i];
 638                                 struct sk_buff *nskb;
 639                                 if (aphy == NULL)
 640                                         continue;
 641                                 nskb = skb_copy(skb, GFP_ATOMIC);
 642                                 if (nskb)
 643                                         __ieee80211_rx(aphy->hw, nskb,
 644                                                        &rx_status);
 645                         }
 646                         __ieee80211_rx(sc->hw, skb, &rx_status);
 647                 } else {
 648                         /* Deliver unicast frames based on receiver address */
 649                         __ieee80211_rx(ath_get_virt_hw(sc, hdr), skb,
 650                                        &rx_status);
 651                 }
 652
 653                 /* We will now give hardware our shiny new allocated skb */
 654                 bf->bf_mpdu = requeue_skb;
 655                 bf->bf_buf_addr = dma_map_single(sc->dev, requeue_skb->data,
 656                                          sc->rx.bufsize,
 657                                          DMA_FROM_DEVICE);
 658                 if (unlikely(dma_mapping_error(sc->dev,
 659                           bf->bf_buf_addr))) {
 660                         dev_kfree_skb_any(requeue_skb);
 661                         bf->bf_mpdu = NULL;
 662                         DPRINTF(sc, ATH_DBG_CONFIG,
 663                                 "dma_mapping_error() on RX\n");
 664                         break;
 665                 }
 666                 bf->bf_dmacontext = bf->bf_buf_addr;
 667
 668                 /*
 669                  * change the default rx antenna if rx diversity chooses the
 670                  * other antenna 3 times in a row.
 671                  */
 672                 if (sc->rx.defant != ds->ds_rxstat.rs_antenna) {
 673                         if (++sc->rx.rxotherant >= 3)
 674                                 ath_setdefantenna(sc, ds->ds_rxstat.rs_antenna);
 675                 } else {
 676                         sc->rx.rxotherant = 0;
 677                 }
 678
 679                 if (ieee80211_is_beacon(hdr->frame_control) &&
 680                                 (sc->sc_flags & SC_OP_WAIT_FOR_BEACON)) {
 681                         sc->sc_flags &= ~SC_OP_WAIT_FOR_BEACON;
 682                         ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
 683                 }
 684 requeue:
 685                 list_move_tail(&bf->list, &sc->rx.rxbuf);
 686                 ath_rx_buf_link(sc, bf);
 687         } while (1);
 688
 689         spin_unlock_bh(&sc->rx.rxbuflock);
 690
 691         return 0;
 692 #undef PA2DESC
 693 }