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hwmon: (max6650) Add support for alarms
[deliverable/linux.git] / drivers / net / wireless / ath9k / xmit.c
1 /*
2 * Copyright (c) 2008-2009 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include "ath9k.h"
18
19 #define BITS_PER_BYTE 8
20 #define OFDM_PLCP_BITS 22
21 #define HT_RC_2_MCS(_rc) ((_rc) & 0x0f)
22 #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
23 #define L_STF 8
24 #define L_LTF 8
25 #define L_SIG 4
26 #define HT_SIG 8
27 #define HT_STF 4
28 #define HT_LTF(_ns) (4 * (_ns))
29 #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */
30 #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */
31 #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
32 #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
33
34 #define OFDM_SIFS_TIME 16
35
36 static u32 bits_per_symbol[][2] = {
37 /* 20MHz 40MHz */
38 { 26, 54 }, /* 0: BPSK */
39 { 52, 108 }, /* 1: QPSK 1/2 */
40 { 78, 162 }, /* 2: QPSK 3/4 */
41 { 104, 216 }, /* 3: 16-QAM 1/2 */
42 { 156, 324 }, /* 4: 16-QAM 3/4 */
43 { 208, 432 }, /* 5: 64-QAM 2/3 */
44 { 234, 486 }, /* 6: 64-QAM 3/4 */
45 { 260, 540 }, /* 7: 64-QAM 5/6 */
46 { 52, 108 }, /* 8: BPSK */
47 { 104, 216 }, /* 9: QPSK 1/2 */
48 { 156, 324 }, /* 10: QPSK 3/4 */
49 { 208, 432 }, /* 11: 16-QAM 1/2 */
50 { 312, 648 }, /* 12: 16-QAM 3/4 */
51 { 416, 864 }, /* 13: 64-QAM 2/3 */
52 { 468, 972 }, /* 14: 64-QAM 3/4 */
53 { 520, 1080 }, /* 15: 64-QAM 5/6 */
54 };
55
56 #define IS_HT_RATE(_rate) ((_rate) & 0x80)
57
58 static void ath_tx_send_ht_normal(struct ath_softc *sc, struct ath_txq *txq,
59 struct ath_atx_tid *tid,
60 struct list_head *bf_head);
61 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
62 struct list_head *bf_q,
63 int txok, int sendbar);
64 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
65 struct list_head *head);
66 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf);
67 static int ath_tx_num_badfrms(struct ath_softc *sc, struct ath_buf *bf,
68 int txok);
69 static void ath_tx_rc_status(struct ath_buf *bf, struct ath_desc *ds,
70 int nbad, int txok, bool update_rc);
71
72 /*********************/
73 /* Aggregation logic */
74 /*********************/
75
76 static int ath_aggr_query(struct ath_softc *sc, struct ath_node *an, u8 tidno)
77 {
78 struct ath_atx_tid *tid;
79 tid = ATH_AN_2_TID(an, tidno);
80
81 if (tid->state & AGGR_ADDBA_COMPLETE ||
82 tid->state & AGGR_ADDBA_PROGRESS)
83 return 1;
84 else
85 return 0;
86 }
87
88 static void ath_tx_queue_tid(struct ath_txq *txq, struct ath_atx_tid *tid)
89 {
90 struct ath_atx_ac *ac = tid->ac;
91
92 if (tid->paused)
93 return;
94
95 if (tid->sched)
96 return;
97
98 tid->sched = true;
99 list_add_tail(&tid->list, &ac->tid_q);
100
101 if (ac->sched)
102 return;
103
104 ac->sched = true;
105 list_add_tail(&ac->list, &txq->axq_acq);
106 }
107
108 static void ath_tx_pause_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
109 {
110 struct ath_txq *txq = &sc->tx.txq[tid->ac->qnum];
111
112 spin_lock_bh(&txq->axq_lock);
113 tid->paused++;
114 spin_unlock_bh(&txq->axq_lock);
115 }
116
117 static void ath_tx_resume_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
118 {
119 struct ath_txq *txq = &sc->tx.txq[tid->ac->qnum];
120
121 ASSERT(tid->paused > 0);
122 spin_lock_bh(&txq->axq_lock);
123
124 tid->paused--;
125
126 if (tid->paused > 0)
127 goto unlock;
128
129 if (list_empty(&tid->buf_q))
130 goto unlock;
131
132 ath_tx_queue_tid(txq, tid);
133 ath_txq_schedule(sc, txq);
134 unlock:
135 spin_unlock_bh(&txq->axq_lock);
136 }
137
138 static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
139 {
140 struct ath_txq *txq = &sc->tx.txq[tid->ac->qnum];
141 struct ath_buf *bf;
142 struct list_head bf_head;
143 INIT_LIST_HEAD(&bf_head);
144
145 ASSERT(tid->paused > 0);
146 spin_lock_bh(&txq->axq_lock);
147
148 tid->paused--;
149
150 if (tid->paused > 0) {
151 spin_unlock_bh(&txq->axq_lock);
152 return;
153 }
154
155 while (!list_empty(&tid->buf_q)) {
156 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
157 ASSERT(!bf_isretried(bf));
158 list_move_tail(&bf->list, &bf_head);
159 ath_tx_send_ht_normal(sc, txq, tid, &bf_head);
160 }
161
162 spin_unlock_bh(&txq->axq_lock);
163 }
164
165 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
166 int seqno)
167 {
168 int index, cindex;
169
170 index = ATH_BA_INDEX(tid->seq_start, seqno);
171 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
172
173 tid->tx_buf[cindex] = NULL;
174
175 while (tid->baw_head != tid->baw_tail && !tid->tx_buf[tid->baw_head]) {
176 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
177 INCR(tid->baw_head, ATH_TID_MAX_BUFS);
178 }
179 }
180
181 static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
182 struct ath_buf *bf)
183 {
184 int index, cindex;
185
186 if (bf_isretried(bf))
187 return;
188
189 index = ATH_BA_INDEX(tid->seq_start, bf->bf_seqno);
190 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
191
192 ASSERT(tid->tx_buf[cindex] == NULL);
193 tid->tx_buf[cindex] = bf;
194
195 if (index >= ((tid->baw_tail - tid->baw_head) &
196 (ATH_TID_MAX_BUFS - 1))) {
197 tid->baw_tail = cindex;
198 INCR(tid->baw_tail, ATH_TID_MAX_BUFS);
199 }
200 }
201
202 /*
203 * TODO: For frame(s) that are in the retry state, we will reuse the
204 * sequence number(s) without setting the retry bit. The
205 * alternative is to give up on these and BAR the receiver's window
206 * forward.
207 */
208 static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq,
209 struct ath_atx_tid *tid)
210
211 {
212 struct ath_buf *bf;
213 struct list_head bf_head;
214 INIT_LIST_HEAD(&bf_head);
215
216 for (;;) {
217 if (list_empty(&tid->buf_q))
218 break;
219
220 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
221 list_move_tail(&bf->list, &bf_head);
222
223 if (bf_isretried(bf))
224 ath_tx_update_baw(sc, tid, bf->bf_seqno);
225
226 spin_unlock(&txq->axq_lock);
227 ath_tx_complete_buf(sc, bf, &bf_head, 0, 0);
228 spin_lock(&txq->axq_lock);
229 }
230
231 tid->seq_next = tid->seq_start;
232 tid->baw_tail = tid->baw_head;
233 }
234
235 static void ath_tx_set_retry(struct ath_softc *sc, struct ath_buf *bf)
236 {
237 struct sk_buff *skb;
238 struct ieee80211_hdr *hdr;
239
240 bf->bf_state.bf_type |= BUF_RETRY;
241 bf->bf_retries++;
242
243 skb = bf->bf_mpdu;
244 hdr = (struct ieee80211_hdr *)skb->data;
245 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY);
246 }
247
248 static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf)
249 {
250 struct ath_buf *tbf;
251
252 spin_lock_bh(&sc->tx.txbuflock);
253 ASSERT(!list_empty((&sc->tx.txbuf)));
254 tbf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list);
255 list_del(&tbf->list);
256 spin_unlock_bh(&sc->tx.txbuflock);
257
258 ATH_TXBUF_RESET(tbf);
259
260 tbf->bf_mpdu = bf->bf_mpdu;
261 tbf->bf_buf_addr = bf->bf_buf_addr;
262 *(tbf->bf_desc) = *(bf->bf_desc);
263 tbf->bf_state = bf->bf_state;
264 tbf->bf_dmacontext = bf->bf_dmacontext;
265
266 return tbf;
267 }
268
269 static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
270 struct ath_buf *bf, struct list_head *bf_q,
271 int txok)
272 {
273 struct ath_node *an = NULL;
274 struct sk_buff *skb;
275 struct ieee80211_sta *sta;
276 struct ieee80211_hdr *hdr;
277 struct ath_atx_tid *tid = NULL;
278 struct ath_buf *bf_next, *bf_last = bf->bf_lastbf;
279 struct ath_desc *ds = bf_last->bf_desc;
280 struct list_head bf_head, bf_pending;
281 u16 seq_st = 0, acked_cnt = 0, txfail_cnt = 0;
282 u32 ba[WME_BA_BMP_SIZE >> 5];
283 int isaggr, txfail, txpending, sendbar = 0, needreset = 0, nbad = 0;
284 bool rc_update = true;
285
286 skb = (struct sk_buff *)bf->bf_mpdu;
287 hdr = (struct ieee80211_hdr *)skb->data;
288
289 rcu_read_lock();
290
291 sta = ieee80211_find_sta(sc->hw, hdr->addr1);
292 if (!sta) {
293 rcu_read_unlock();
294 return;
295 }
296
297 an = (struct ath_node *)sta->drv_priv;
298 tid = ATH_AN_2_TID(an, bf->bf_tidno);
299
300 isaggr = bf_isaggr(bf);
301 memset(ba, 0, WME_BA_BMP_SIZE >> 3);
302
303 if (isaggr && txok) {
304 if (ATH_DS_TX_BA(ds)) {
305 seq_st = ATH_DS_BA_SEQ(ds);
306 memcpy(ba, ATH_DS_BA_BITMAP(ds),
307 WME_BA_BMP_SIZE >> 3);
308 } else {
309 /*
310 * AR5416 can become deaf/mute when BA
311 * issue happens. Chip needs to be reset.
312 * But AP code may have sychronization issues
313 * when perform internal reset in this routine.
314 * Only enable reset in STA mode for now.
315 */
316 if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION)
317 needreset = 1;
318 }
319 }
320
321 INIT_LIST_HEAD(&bf_pending);
322 INIT_LIST_HEAD(&bf_head);
323
324 nbad = ath_tx_num_badfrms(sc, bf, txok);
325 while (bf) {
326 txfail = txpending = 0;
327 bf_next = bf->bf_next;
328
329 if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, bf->bf_seqno))) {
330 /* transmit completion, subframe is
331 * acked by block ack */
332 acked_cnt++;
333 } else if (!isaggr && txok) {
334 /* transmit completion */
335 acked_cnt++;
336 } else {
337 if (!(tid->state & AGGR_CLEANUP) &&
338 ds->ds_txstat.ts_flags != ATH9K_TX_SW_ABORTED) {
339 if (bf->bf_retries < ATH_MAX_SW_RETRIES) {
340 ath_tx_set_retry(sc, bf);
341 txpending = 1;
342 } else {
343 bf->bf_state.bf_type |= BUF_XRETRY;
344 txfail = 1;
345 sendbar = 1;
346 txfail_cnt++;
347 }
348 } else {
349 /*
350 * cleanup in progress, just fail
351 * the un-acked sub-frames
352 */
353 txfail = 1;
354 }
355 }
356
357 if (bf_next == NULL) {
358 INIT_LIST_HEAD(&bf_head);
359 } else {
360 ASSERT(!list_empty(bf_q));
361 list_move_tail(&bf->list, &bf_head);
362 }
363
364 if (!txpending) {
365 /*
366 * complete the acked-ones/xretried ones; update
367 * block-ack window
368 */
369 spin_lock_bh(&txq->axq_lock);
370 ath_tx_update_baw(sc, tid, bf->bf_seqno);
371 spin_unlock_bh(&txq->axq_lock);
372
373 if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) {
374 ath_tx_rc_status(bf, ds, nbad, txok, true);
375 rc_update = false;
376 } else {
377 ath_tx_rc_status(bf, ds, nbad, txok, false);
378 }
379
380 ath_tx_complete_buf(sc, bf, &bf_head, !txfail, sendbar);
381 } else {
382 /* retry the un-acked ones */
383 if (bf->bf_next == NULL &&
384 bf_last->bf_status & ATH_BUFSTATUS_STALE) {
385 struct ath_buf *tbf;
386
387 tbf = ath_clone_txbuf(sc, bf_last);
388 ath9k_hw_cleartxdesc(sc->sc_ah, tbf->bf_desc);
389 list_add_tail(&tbf->list, &bf_head);
390 } else {
391 /*
392 * Clear descriptor status words for
393 * software retry
394 */
395 ath9k_hw_cleartxdesc(sc->sc_ah, bf->bf_desc);
396 }
397
398 /*
399 * Put this buffer to the temporary pending
400 * queue to retain ordering
401 */
402 list_splice_tail_init(&bf_head, &bf_pending);
403 }
404
405 bf = bf_next;
406 }
407
408 if (tid->state & AGGR_CLEANUP) {
409 if (tid->baw_head == tid->baw_tail) {
410 tid->state &= ~AGGR_ADDBA_COMPLETE;
411 tid->addba_exchangeattempts = 0;
412 tid->state &= ~AGGR_CLEANUP;
413
414 /* send buffered frames as singles */
415 ath_tx_flush_tid(sc, tid);
416 }
417 rcu_read_unlock();
418 return;
419 }
420
421 /* prepend un-acked frames to the beginning of the pending frame queue */
422 if (!list_empty(&bf_pending)) {
423 spin_lock_bh(&txq->axq_lock);
424 list_splice(&bf_pending, &tid->buf_q);
425 ath_tx_queue_tid(txq, tid);
426 spin_unlock_bh(&txq->axq_lock);
427 }
428
429 rcu_read_unlock();
430
431 if (needreset)
432 ath_reset(sc, false);
433 }
434
435 static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf,
436 struct ath_atx_tid *tid)
437 {
438 struct ath_rate_table *rate_table = sc->cur_rate_table;
439 struct sk_buff *skb;
440 struct ieee80211_tx_info *tx_info;
441 struct ieee80211_tx_rate *rates;
442 struct ath_tx_info_priv *tx_info_priv;
443 u32 max_4ms_framelen, frmlen;
444 u16 aggr_limit, legacy = 0, maxampdu;
445 int i;
446
447 skb = (struct sk_buff *)bf->bf_mpdu;
448 tx_info = IEEE80211_SKB_CB(skb);
449 rates = tx_info->control.rates;
450 tx_info_priv = (struct ath_tx_info_priv *)tx_info->rate_driver_data[0];
451
452 /*
453 * Find the lowest frame length among the rate series that will have a
454 * 4ms transmit duration.
455 * TODO - TXOP limit needs to be considered.
456 */
457 max_4ms_framelen = ATH_AMPDU_LIMIT_MAX;
458
459 for (i = 0; i < 4; i++) {
460 if (rates[i].count) {
461 if (!WLAN_RC_PHY_HT(rate_table->info[rates[i].idx].phy)) {
462 legacy = 1;
463 break;
464 }
465
466 frmlen = rate_table->info[rates[i].idx].max_4ms_framelen;
467 max_4ms_framelen = min(max_4ms_framelen, frmlen);
468 }
469 }
470
471 /*
472 * limit aggregate size by the minimum rate if rate selected is
473 * not a probe rate, if rate selected is a probe rate then
474 * avoid aggregation of this packet.
475 */
476 if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy)
477 return 0;
478
479 aggr_limit = min(max_4ms_framelen, (u32)ATH_AMPDU_LIMIT_DEFAULT);
480
481 /*
482 * h/w can accept aggregates upto 16 bit lengths (65535).
483 * The IE, however can hold upto 65536, which shows up here
484 * as zero. Ignore 65536 since we are constrained by hw.
485 */
486 maxampdu = tid->an->maxampdu;
487 if (maxampdu)
488 aggr_limit = min(aggr_limit, maxampdu);
489
490 return aggr_limit;
491 }
492
493 /*
494 * Returns the number of delimiters to be added to
495 * meet the minimum required mpdudensity.
496 * caller should make sure that the rate is HT rate .
497 */
498 static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid,
499 struct ath_buf *bf, u16 frmlen)
500 {
501 struct ath_rate_table *rt = sc->cur_rate_table;
502 struct sk_buff *skb = bf->bf_mpdu;
503 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
504 u32 nsymbits, nsymbols, mpdudensity;
505 u16 minlen;
506 u8 rc, flags, rix;
507 int width, half_gi, ndelim, mindelim;
508
509 /* Select standard number of delimiters based on frame length alone */
510 ndelim = ATH_AGGR_GET_NDELIM(frmlen);
511
512 /*
513 * If encryption enabled, hardware requires some more padding between
514 * subframes.
515 * TODO - this could be improved to be dependent on the rate.
516 * The hardware can keep up at lower rates, but not higher rates
517 */
518 if (bf->bf_keytype != ATH9K_KEY_TYPE_CLEAR)
519 ndelim += ATH_AGGR_ENCRYPTDELIM;
520
521 /*
522 * Convert desired mpdu density from microeconds to bytes based
523 * on highest rate in rate series (i.e. first rate) to determine
524 * required minimum length for subframe. Take into account
525 * whether high rate is 20 or 40Mhz and half or full GI.
526 */
527 mpdudensity = tid->an->mpdudensity;
528
529 /*
530 * If there is no mpdu density restriction, no further calculation
531 * is needed.
532 */
533 if (mpdudensity == 0)
534 return ndelim;
535
536 rix = tx_info->control.rates[0].idx;
537 flags = tx_info->control.rates[0].flags;
538 rc = rt->info[rix].ratecode;
539 width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0;
540 half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0;
541
542 if (half_gi)
543 nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(mpdudensity);
544 else
545 nsymbols = NUM_SYMBOLS_PER_USEC(mpdudensity);
546
547 if (nsymbols == 0)
548 nsymbols = 1;
549
550 nsymbits = bits_per_symbol[HT_RC_2_MCS(rc)][width];
551 minlen = (nsymbols * nsymbits) / BITS_PER_BYTE;
552
553 if (frmlen < minlen) {
554 mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ;
555 ndelim = max(mindelim, ndelim);
556 }
557
558 return ndelim;
559 }
560
561 static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc,
562 struct ath_atx_tid *tid,
563 struct list_head *bf_q)
564 {
565 #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
566 struct ath_buf *bf, *bf_first, *bf_prev = NULL;
567 int rl = 0, nframes = 0, ndelim, prev_al = 0;
568 u16 aggr_limit = 0, al = 0, bpad = 0,
569 al_delta, h_baw = tid->baw_size / 2;
570 enum ATH_AGGR_STATUS status = ATH_AGGR_DONE;
571
572 bf_first = list_first_entry(&tid->buf_q, struct ath_buf, list);
573
574 do {
575 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
576
577 /* do not step over block-ack window */
578 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, bf->bf_seqno)) {
579 status = ATH_AGGR_BAW_CLOSED;
580 break;
581 }
582
583 if (!rl) {
584 aggr_limit = ath_lookup_rate(sc, bf, tid);
585 rl = 1;
586 }
587
588 /* do not exceed aggregation limit */
589 al_delta = ATH_AGGR_DELIM_SZ + bf->bf_frmlen;
590
591 if (nframes &&
592 (aggr_limit < (al + bpad + al_delta + prev_al))) {
593 status = ATH_AGGR_LIMITED;
594 break;
595 }
596
597 /* do not exceed subframe limit */
598 if (nframes >= min((int)h_baw, ATH_AMPDU_SUBFRAME_DEFAULT)) {
599 status = ATH_AGGR_LIMITED;
600 break;
601 }
602 nframes++;
603
604 /* add padding for previous frame to aggregation length */
605 al += bpad + al_delta;
606
607 /*
608 * Get the delimiters needed to meet the MPDU
609 * density for this node.
610 */
611 ndelim = ath_compute_num_delims(sc, tid, bf_first, bf->bf_frmlen);
612 bpad = PADBYTES(al_delta) + (ndelim << 2);
613
614 bf->bf_next = NULL;
615 bf->bf_desc->ds_link = 0;
616
617 /* link buffers of this frame to the aggregate */
618 ath_tx_addto_baw(sc, tid, bf);
619 ath9k_hw_set11n_aggr_middle(sc->sc_ah, bf->bf_desc, ndelim);
620 list_move_tail(&bf->list, bf_q);
621 if (bf_prev) {
622 bf_prev->bf_next = bf;
623 bf_prev->bf_desc->ds_link = bf->bf_daddr;
624 }
625 bf_prev = bf;
626 } while (!list_empty(&tid->buf_q));
627
628 bf_first->bf_al = al;
629 bf_first->bf_nframes = nframes;
630
631 return status;
632 #undef PADBYTES
633 }
634
635 static void ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq,
636 struct ath_atx_tid *tid)
637 {
638 struct ath_buf *bf;
639 enum ATH_AGGR_STATUS status;
640 struct list_head bf_q;
641
642 do {
643 if (list_empty(&tid->buf_q))
644 return;
645
646 INIT_LIST_HEAD(&bf_q);
647
648 status = ath_tx_form_aggr(sc, tid, &bf_q);
649
650 /*
651 * no frames picked up to be aggregated;
652 * block-ack window is not open.
653 */
654 if (list_empty(&bf_q))
655 break;
656
657 bf = list_first_entry(&bf_q, struct ath_buf, list);
658 bf->bf_lastbf = list_entry(bf_q.prev, struct ath_buf, list);
659
660 /* if only one frame, send as non-aggregate */
661 if (bf->bf_nframes == 1) {
662 bf->bf_state.bf_type &= ~BUF_AGGR;
663 ath9k_hw_clr11n_aggr(sc->sc_ah, bf->bf_desc);
664 ath_buf_set_rate(sc, bf);
665 ath_tx_txqaddbuf(sc, txq, &bf_q);
666 continue;
667 }
668
669 /* setup first desc of aggregate */
670 bf->bf_state.bf_type |= BUF_AGGR;
671 ath_buf_set_rate(sc, bf);
672 ath9k_hw_set11n_aggr_first(sc->sc_ah, bf->bf_desc, bf->bf_al);
673
674 /* anchor last desc of aggregate */
675 ath9k_hw_set11n_aggr_last(sc->sc_ah, bf->bf_lastbf->bf_desc);
676
677 txq->axq_aggr_depth++;
678 ath_tx_txqaddbuf(sc, txq, &bf_q);
679
680 } while (txq->axq_depth < ATH_AGGR_MIN_QDEPTH &&
681 status != ATH_AGGR_BAW_CLOSED);
682 }
683
684 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
685 u16 tid, u16 *ssn)
686 {
687 struct ath_atx_tid *txtid;
688 struct ath_node *an;
689
690 an = (struct ath_node *)sta->drv_priv;
691
692 if (sc->sc_flags & SC_OP_TXAGGR) {
693 txtid = ATH_AN_2_TID(an, tid);
694 txtid->state |= AGGR_ADDBA_PROGRESS;
695 ath_tx_pause_tid(sc, txtid);
696 *ssn = txtid->seq_start;
697 }
698
699 return 0;
700 }
701
702 int ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
703 {
704 struct ath_node *an = (struct ath_node *)sta->drv_priv;
705 struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid);
706 struct ath_txq *txq = &sc->tx.txq[txtid->ac->qnum];
707 struct ath_buf *bf;
708 struct list_head bf_head;
709 INIT_LIST_HEAD(&bf_head);
710
711 if (txtid->state & AGGR_CLEANUP)
712 return 0;
713
714 if (!(txtid->state & AGGR_ADDBA_COMPLETE)) {
715 txtid->addba_exchangeattempts = 0;
716 return 0;
717 }
718
719 ath_tx_pause_tid(sc, txtid);
720
721 /* drop all software retried frames and mark this TID */
722 spin_lock_bh(&txq->axq_lock);
723 while (!list_empty(&txtid->buf_q)) {
724 bf = list_first_entry(&txtid->buf_q, struct ath_buf, list);
725 if (!bf_isretried(bf)) {
726 /*
727 * NB: it's based on the assumption that
728 * software retried frame will always stay
729 * at the head of software queue.
730 */
731 break;
732 }
733 list_move_tail(&bf->list, &bf_head);
734 ath_tx_update_baw(sc, txtid, bf->bf_seqno);
735 ath_tx_complete_buf(sc, bf, &bf_head, 0, 0);
736 }
737 spin_unlock_bh(&txq->axq_lock);
738
739 if (txtid->baw_head != txtid->baw_tail) {
740 txtid->state |= AGGR_CLEANUP;
741 } else {
742 txtid->state &= ~AGGR_ADDBA_COMPLETE;
743 txtid->addba_exchangeattempts = 0;
744 ath_tx_flush_tid(sc, txtid);
745 }
746
747 return 0;
748 }
749
750 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
751 {
752 struct ath_atx_tid *txtid;
753 struct ath_node *an;
754
755 an = (struct ath_node *)sta->drv_priv;
756
757 if (sc->sc_flags & SC_OP_TXAGGR) {
758 txtid = ATH_AN_2_TID(an, tid);
759 txtid->baw_size =
760 IEEE80211_MIN_AMPDU_BUF << sta->ht_cap.ampdu_factor;
761 txtid->state |= AGGR_ADDBA_COMPLETE;
762 txtid->state &= ~AGGR_ADDBA_PROGRESS;
763 ath_tx_resume_tid(sc, txtid);
764 }
765 }
766
767 bool ath_tx_aggr_check(struct ath_softc *sc, struct ath_node *an, u8 tidno)
768 {
769 struct ath_atx_tid *txtid;
770
771 if (!(sc->sc_flags & SC_OP_TXAGGR))
772 return false;
773
774 txtid = ATH_AN_2_TID(an, tidno);
775
776 if (!(txtid->state & AGGR_ADDBA_COMPLETE)) {
777 if (!(txtid->state & AGGR_ADDBA_PROGRESS) &&
778 (txtid->addba_exchangeattempts < ADDBA_EXCHANGE_ATTEMPTS)) {
779 txtid->addba_exchangeattempts++;
780 return true;
781 }
782 }
783
784 return false;
785 }
786
787 /********************/
788 /* Queue Management */
789 /********************/
790
791 static void ath_txq_drain_pending_buffers(struct ath_softc *sc,
792 struct ath_txq *txq)
793 {
794 struct ath_atx_ac *ac, *ac_tmp;
795 struct ath_atx_tid *tid, *tid_tmp;
796
797 list_for_each_entry_safe(ac, ac_tmp, &txq->axq_acq, list) {
798 list_del(&ac->list);
799 ac->sched = false;
800 list_for_each_entry_safe(tid, tid_tmp, &ac->tid_q, list) {
801 list_del(&tid->list);
802 tid->sched = false;
803 ath_tid_drain(sc, txq, tid);
804 }
805 }
806 }
807
808 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
809 {
810 struct ath_hw *ah = sc->sc_ah;
811 struct ath9k_tx_queue_info qi;
812 int qnum;
813
814 memset(&qi, 0, sizeof(qi));
815 qi.tqi_subtype = subtype;
816 qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT;
817 qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
818 qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT;
819 qi.tqi_physCompBuf = 0;
820
821 /*
822 * Enable interrupts only for EOL and DESC conditions.
823 * We mark tx descriptors to receive a DESC interrupt
824 * when a tx queue gets deep; otherwise waiting for the
825 * EOL to reap descriptors. Note that this is done to
826 * reduce interrupt load and this only defers reaping
827 * descriptors, never transmitting frames. Aside from
828 * reducing interrupts this also permits more concurrency.
829 * The only potential downside is if the tx queue backs
830 * up in which case the top half of the kernel may backup
831 * due to a lack of tx descriptors.
832 *
833 * The UAPSD queue is an exception, since we take a desc-
834 * based intr on the EOSP frames.
835 */
836 if (qtype == ATH9K_TX_QUEUE_UAPSD)
837 qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE;
838 else
839 qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE |
840 TXQ_FLAG_TXDESCINT_ENABLE;
841 qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi);
842 if (qnum == -1) {
843 /*
844 * NB: don't print a message, this happens
845 * normally on parts with too few tx queues
846 */
847 return NULL;
848 }
849 if (qnum >= ARRAY_SIZE(sc->tx.txq)) {
850 DPRINTF(sc, ATH_DBG_FATAL,
851 "qnum %u out of range, max %u!\n",
852 qnum, (unsigned int)ARRAY_SIZE(sc->tx.txq));
853 ath9k_hw_releasetxqueue(ah, qnum);
854 return NULL;
855 }
856 if (!ATH_TXQ_SETUP(sc, qnum)) {
857 struct ath_txq *txq = &sc->tx.txq[qnum];
858
859 txq->axq_qnum = qnum;
860 txq->axq_link = NULL;
861 INIT_LIST_HEAD(&txq->axq_q);
862 INIT_LIST_HEAD(&txq->axq_acq);
863 spin_lock_init(&txq->axq_lock);
864 txq->axq_depth = 0;
865 txq->axq_aggr_depth = 0;
866 txq->axq_totalqueued = 0;
867 txq->axq_linkbuf = NULL;
868 sc->tx.txqsetup |= 1<<qnum;
869 }
870 return &sc->tx.txq[qnum];
871 }
872
873 static int ath_tx_get_qnum(struct ath_softc *sc, int qtype, int haltype)
874 {
875 int qnum;
876
877 switch (qtype) {
878 case ATH9K_TX_QUEUE_DATA:
879 if (haltype >= ARRAY_SIZE(sc->tx.hwq_map)) {
880 DPRINTF(sc, ATH_DBG_FATAL,
881 "HAL AC %u out of range, max %zu!\n",
882 haltype, ARRAY_SIZE(sc->tx.hwq_map));
883 return -1;
884 }
885 qnum = sc->tx.hwq_map[haltype];
886 break;
887 case ATH9K_TX_QUEUE_BEACON:
888 qnum = sc->beacon.beaconq;
889 break;
890 case ATH9K_TX_QUEUE_CAB:
891 qnum = sc->beacon.cabq->axq_qnum;
892 break;
893 default:
894 qnum = -1;
895 }
896 return qnum;
897 }
898
899 struct ath_txq *ath_test_get_txq(struct ath_softc *sc, struct sk_buff *skb)
900 {
901 struct ath_txq *txq = NULL;
902 int qnum;
903
904 qnum = ath_get_hal_qnum(skb_get_queue_mapping(skb), sc);
905 txq = &sc->tx.txq[qnum];
906
907 spin_lock_bh(&txq->axq_lock);
908
909 if (txq->axq_depth >= (ATH_TXBUF - 20)) {
910 DPRINTF(sc, ATH_DBG_XMIT,
911 "TX queue: %d is full, depth: %d\n",
912 qnum, txq->axq_depth);
913 ieee80211_stop_queue(sc->hw, skb_get_queue_mapping(skb));
914 txq->stopped = 1;
915 spin_unlock_bh(&txq->axq_lock);
916 return NULL;
917 }
918
919 spin_unlock_bh(&txq->axq_lock);
920
921 return txq;
922 }
923
924 int ath_txq_update(struct ath_softc *sc, int qnum,
925 struct ath9k_tx_queue_info *qinfo)
926 {
927 struct ath_hw *ah = sc->sc_ah;
928 int error = 0;
929 struct ath9k_tx_queue_info qi;
930
931 if (qnum == sc->beacon.beaconq) {
932 /*
933 * XXX: for beacon queue, we just save the parameter.
934 * It will be picked up by ath_beaconq_config when
935 * it's necessary.
936 */
937 sc->beacon.beacon_qi = *qinfo;
938 return 0;
939 }
940
941 ASSERT(sc->tx.txq[qnum].axq_qnum == qnum);
942
943 ath9k_hw_get_txq_props(ah, qnum, &qi);
944 qi.tqi_aifs = qinfo->tqi_aifs;
945 qi.tqi_cwmin = qinfo->tqi_cwmin;
946 qi.tqi_cwmax = qinfo->tqi_cwmax;
947 qi.tqi_burstTime = qinfo->tqi_burstTime;
948 qi.tqi_readyTime = qinfo->tqi_readyTime;
949
950 if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) {
951 DPRINTF(sc, ATH_DBG_FATAL,
952 "Unable to update hardware queue %u!\n", qnum);
953 error = -EIO;
954 } else {
955 ath9k_hw_resettxqueue(ah, qnum);
956 }
957
958 return error;
959 }
960
961 int ath_cabq_update(struct ath_softc *sc)
962 {
963 struct ath9k_tx_queue_info qi;
964 int qnum = sc->beacon.cabq->axq_qnum;
965
966 ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi);
967 /*
968 * Ensure the readytime % is within the bounds.
969 */
970 if (sc->config.cabqReadytime < ATH9K_READY_TIME_LO_BOUND)
971 sc->config.cabqReadytime = ATH9K_READY_TIME_LO_BOUND;
972 else if (sc->config.cabqReadytime > ATH9K_READY_TIME_HI_BOUND)
973 sc->config.cabqReadytime = ATH9K_READY_TIME_HI_BOUND;
974
975 qi.tqi_readyTime = (sc->hw->conf.beacon_int *
976 sc->config.cabqReadytime) / 100;
977 ath_txq_update(sc, qnum, &qi);
978
979 return 0;
980 }
981
982 /*
983 * Drain a given TX queue (could be Beacon or Data)
984 *
985 * This assumes output has been stopped and
986 * we do not need to block ath_tx_tasklet.
987 */
988 void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq, bool retry_tx)
989 {
990 struct ath_buf *bf, *lastbf;
991 struct list_head bf_head;
992
993 INIT_LIST_HEAD(&bf_head);
994
995 for (;;) {
996 spin_lock_bh(&txq->axq_lock);
997
998 if (list_empty(&txq->axq_q)) {
999 txq->axq_link = NULL;
1000 txq->axq_linkbuf = NULL;
1001 spin_unlock_bh(&txq->axq_lock);
1002 break;
1003 }
1004
1005 bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
1006
1007 if (bf->bf_status & ATH_BUFSTATUS_STALE) {
1008 list_del(&bf->list);
1009 spin_unlock_bh(&txq->axq_lock);
1010
1011 spin_lock_bh(&sc->tx.txbuflock);
1012 list_add_tail(&bf->list, &sc->tx.txbuf);
1013 spin_unlock_bh(&sc->tx.txbuflock);
1014 continue;
1015 }
1016
1017 lastbf = bf->bf_lastbf;
1018 if (!retry_tx)
1019 lastbf->bf_desc->ds_txstat.ts_flags =
1020 ATH9K_TX_SW_ABORTED;
1021
1022 /* remove ath_buf's of the same mpdu from txq */
1023 list_cut_position(&bf_head, &txq->axq_q, &lastbf->list);
1024 txq->axq_depth--;
1025
1026 spin_unlock_bh(&txq->axq_lock);
1027
1028 if (bf_isampdu(bf))
1029 ath_tx_complete_aggr(sc, txq, bf, &bf_head, 0);
1030 else
1031 ath_tx_complete_buf(sc, bf, &bf_head, 0, 0);
1032 }
1033
1034 /* flush any pending frames if aggregation is enabled */
1035 if (sc->sc_flags & SC_OP_TXAGGR) {
1036 if (!retry_tx) {
1037 spin_lock_bh(&txq->axq_lock);
1038 ath_txq_drain_pending_buffers(sc, txq);
1039 spin_unlock_bh(&txq->axq_lock);
1040 }
1041 }
1042 }
1043
1044 void ath_drain_all_txq(struct ath_softc *sc, bool retry_tx)
1045 {
1046 struct ath_hw *ah = sc->sc_ah;
1047 struct ath_txq *txq;
1048 int i, npend = 0;
1049
1050 if (sc->sc_flags & SC_OP_INVALID)
1051 return;
1052
1053 /* Stop beacon queue */
1054 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
1055
1056 /* Stop data queues */
1057 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1058 if (ATH_TXQ_SETUP(sc, i)) {
1059 txq = &sc->tx.txq[i];
1060 ath9k_hw_stoptxdma(ah, txq->axq_qnum);
1061 npend += ath9k_hw_numtxpending(ah, txq->axq_qnum);
1062 }
1063 }
1064
1065 if (npend) {
1066 int r;
1067
1068 DPRINTF(sc, ATH_DBG_XMIT, "Unable to stop TxDMA. Reset HAL!\n");
1069
1070 spin_lock_bh(&sc->sc_resetlock);
1071 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, true);
1072 if (r)
1073 DPRINTF(sc, ATH_DBG_FATAL,
1074 "Unable to reset hardware; reset status %u\n",
1075 r);
1076 spin_unlock_bh(&sc->sc_resetlock);
1077 }
1078
1079 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1080 if (ATH_TXQ_SETUP(sc, i))
1081 ath_draintxq(sc, &sc->tx.txq[i], retry_tx);
1082 }
1083 }
1084
1085 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
1086 {
1087 ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum);
1088 sc->tx.txqsetup &= ~(1<<txq->axq_qnum);
1089 }
1090
1091 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq)
1092 {
1093 struct ath_atx_ac *ac;
1094 struct ath_atx_tid *tid;
1095
1096 if (list_empty(&txq->axq_acq))
1097 return;
1098
1099 ac = list_first_entry(&txq->axq_acq, struct ath_atx_ac, list);
1100 list_del(&ac->list);
1101 ac->sched = false;
1102
1103 do {
1104 if (list_empty(&ac->tid_q))
1105 return;
1106
1107 tid = list_first_entry(&ac->tid_q, struct ath_atx_tid, list);
1108 list_del(&tid->list);
1109 tid->sched = false;
1110
1111 if (tid->paused)
1112 continue;
1113
1114 if ((txq->axq_depth % 2) == 0)
1115 ath_tx_sched_aggr(sc, txq, tid);
1116
1117 /*
1118 * add tid to round-robin queue if more frames
1119 * are pending for the tid
1120 */
1121 if (!list_empty(&tid->buf_q))
1122 ath_tx_queue_tid(txq, tid);
1123
1124 break;
1125 } while (!list_empty(&ac->tid_q));
1126
1127 if (!list_empty(&ac->tid_q)) {
1128 if (!ac->sched) {
1129 ac->sched = true;
1130 list_add_tail(&ac->list, &txq->axq_acq);
1131 }
1132 }
1133 }
1134
1135 int ath_tx_setup(struct ath_softc *sc, int haltype)
1136 {
1137 struct ath_txq *txq;
1138
1139 if (haltype >= ARRAY_SIZE(sc->tx.hwq_map)) {
1140 DPRINTF(sc, ATH_DBG_FATAL,
1141 "HAL AC %u out of range, max %zu!\n",
1142 haltype, ARRAY_SIZE(sc->tx.hwq_map));
1143 return 0;
1144 }
1145 txq = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, haltype);
1146 if (txq != NULL) {
1147 sc->tx.hwq_map[haltype] = txq->axq_qnum;
1148 return 1;
1149 } else
1150 return 0;
1151 }
1152
1153 /***********/
1154 /* TX, DMA */
1155 /***********/
1156
1157 /*
1158 * Insert a chain of ath_buf (descriptors) on a txq and
1159 * assume the descriptors are already chained together by caller.
1160 */
1161 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
1162 struct list_head *head)
1163 {
1164 struct ath_hw *ah = sc->sc_ah;
1165 struct ath_buf *bf;
1166
1167 /*
1168 * Insert the frame on the outbound list and
1169 * pass it on to the hardware.
1170 */
1171
1172 if (list_empty(head))
1173 return;
1174
1175 bf = list_first_entry(head, struct ath_buf, list);
1176
1177 list_splice_tail_init(head, &txq->axq_q);
1178 txq->axq_depth++;
1179 txq->axq_totalqueued++;
1180 txq->axq_linkbuf = list_entry(txq->axq_q.prev, struct ath_buf, list);
1181
1182 DPRINTF(sc, ATH_DBG_QUEUE,
1183 "qnum: %d, txq depth: %d\n", txq->axq_qnum, txq->axq_depth);
1184
1185 if (txq->axq_link == NULL) {
1186 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
1187 DPRINTF(sc, ATH_DBG_XMIT,
1188 "TXDP[%u] = %llx (%p)\n",
1189 txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc);
1190 } else {
1191 *txq->axq_link = bf->bf_daddr;
1192 DPRINTF(sc, ATH_DBG_XMIT, "link[%u] (%p)=%llx (%p)\n",
1193 txq->axq_qnum, txq->axq_link,
1194 ito64(bf->bf_daddr), bf->bf_desc);
1195 }
1196 txq->axq_link = &(bf->bf_lastbf->bf_desc->ds_link);
1197 ath9k_hw_txstart(ah, txq->axq_qnum);
1198 }
1199
1200 static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc)
1201 {
1202 struct ath_buf *bf = NULL;
1203
1204 spin_lock_bh(&sc->tx.txbuflock);
1205
1206 if (unlikely(list_empty(&sc->tx.txbuf))) {
1207 spin_unlock_bh(&sc->tx.txbuflock);
1208 return NULL;
1209 }
1210
1211 bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list);
1212 list_del(&bf->list);
1213
1214 spin_unlock_bh(&sc->tx.txbuflock);
1215
1216 return bf;
1217 }
1218
1219 static void ath_tx_send_ampdu(struct ath_softc *sc, struct ath_atx_tid *tid,
1220 struct list_head *bf_head,
1221 struct ath_tx_control *txctl)
1222 {
1223 struct ath_buf *bf;
1224
1225 bf = list_first_entry(bf_head, struct ath_buf, list);
1226 bf->bf_state.bf_type |= BUF_AMPDU;
1227
1228 /*
1229 * Do not queue to h/w when any of the following conditions is true:
1230 * - there are pending frames in software queue
1231 * - the TID is currently paused for ADDBA/BAR request
1232 * - seqno is not within block-ack window
1233 * - h/w queue depth exceeds low water mark
1234 */
1235 if (!list_empty(&tid->buf_q) || tid->paused ||
1236 !BAW_WITHIN(tid->seq_start, tid->baw_size, bf->bf_seqno) ||
1237 txctl->txq->axq_depth >= ATH_AGGR_MIN_QDEPTH) {
1238 /*
1239 * Add this frame to software queue for scheduling later
1240 * for aggregation.
1241 */
1242 list_move_tail(&bf->list, &tid->buf_q);
1243 ath_tx_queue_tid(txctl->txq, tid);
1244 return;
1245 }
1246
1247 /* Add sub-frame to BAW */
1248 ath_tx_addto_baw(sc, tid, bf);
1249
1250 /* Queue to h/w without aggregation */
1251 bf->bf_nframes = 1;
1252 bf->bf_lastbf = bf;
1253 ath_buf_set_rate(sc, bf);
1254 ath_tx_txqaddbuf(sc, txctl->txq, bf_head);
1255 }
1256
1257 static void ath_tx_send_ht_normal(struct ath_softc *sc, struct ath_txq *txq,
1258 struct ath_atx_tid *tid,
1259 struct list_head *bf_head)
1260 {
1261 struct ath_buf *bf;
1262
1263 bf = list_first_entry(bf_head, struct ath_buf, list);
1264 bf->bf_state.bf_type &= ~BUF_AMPDU;
1265
1266 /* update starting sequence number for subsequent ADDBA request */
1267 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
1268
1269 bf->bf_nframes = 1;
1270 bf->bf_lastbf = bf;
1271 ath_buf_set_rate(sc, bf);
1272 ath_tx_txqaddbuf(sc, txq, bf_head);
1273 }
1274
1275 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
1276 struct list_head *bf_head)
1277 {
1278 struct ath_buf *bf;
1279
1280 bf = list_first_entry(bf_head, struct ath_buf, list);
1281
1282 bf->bf_lastbf = bf;
1283 bf->bf_nframes = 1;
1284 ath_buf_set_rate(sc, bf);
1285 ath_tx_txqaddbuf(sc, txq, bf_head);
1286 }
1287
1288 static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb)
1289 {
1290 struct ieee80211_hdr *hdr;
1291 enum ath9k_pkt_type htype;
1292 __le16 fc;
1293
1294 hdr = (struct ieee80211_hdr *)skb->data;
1295 fc = hdr->frame_control;
1296
1297 if (ieee80211_is_beacon(fc))
1298 htype = ATH9K_PKT_TYPE_BEACON;
1299 else if (ieee80211_is_probe_resp(fc))
1300 htype = ATH9K_PKT_TYPE_PROBE_RESP;
1301 else if (ieee80211_is_atim(fc))
1302 htype = ATH9K_PKT_TYPE_ATIM;
1303 else if (ieee80211_is_pspoll(fc))
1304 htype = ATH9K_PKT_TYPE_PSPOLL;
1305 else
1306 htype = ATH9K_PKT_TYPE_NORMAL;
1307
1308 return htype;
1309 }
1310
1311 static bool is_pae(struct sk_buff *skb)
1312 {
1313 struct ieee80211_hdr *hdr;
1314 __le16 fc;
1315
1316 hdr = (struct ieee80211_hdr *)skb->data;
1317 fc = hdr->frame_control;
1318
1319 if (ieee80211_is_data(fc)) {
1320 if (ieee80211_is_nullfunc(fc) ||
1321 /* Port Access Entity (IEEE 802.1X) */
1322 (skb->protocol == cpu_to_be16(ETH_P_PAE))) {
1323 return true;
1324 }
1325 }
1326
1327 return false;
1328 }
1329
1330 static int get_hw_crypto_keytype(struct sk_buff *skb)
1331 {
1332 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1333
1334 if (tx_info->control.hw_key) {
1335 if (tx_info->control.hw_key->alg == ALG_WEP)
1336 return ATH9K_KEY_TYPE_WEP;
1337 else if (tx_info->control.hw_key->alg == ALG_TKIP)
1338 return ATH9K_KEY_TYPE_TKIP;
1339 else if (tx_info->control.hw_key->alg == ALG_CCMP)
1340 return ATH9K_KEY_TYPE_AES;
1341 }
1342
1343 return ATH9K_KEY_TYPE_CLEAR;
1344 }
1345
1346 static void assign_aggr_tid_seqno(struct sk_buff *skb,
1347 struct ath_buf *bf)
1348 {
1349 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1350 struct ieee80211_hdr *hdr;
1351 struct ath_node *an;
1352 struct ath_atx_tid *tid;
1353 __le16 fc;
1354 u8 *qc;
1355
1356 if (!tx_info->control.sta)
1357 return;
1358
1359 an = (struct ath_node *)tx_info->control.sta->drv_priv;
1360 hdr = (struct ieee80211_hdr *)skb->data;
1361 fc = hdr->frame_control;
1362
1363 if (ieee80211_is_data_qos(fc)) {
1364 qc = ieee80211_get_qos_ctl(hdr);
1365 bf->bf_tidno = qc[0] & 0xf;
1366 }
1367
1368 /*
1369 * For HT capable stations, we save tidno for later use.
1370 * We also override seqno set by upper layer with the one
1371 * in tx aggregation state.
1372 *
1373 * If fragmentation is on, the sequence number is
1374 * not overridden, since it has been
1375 * incremented by the fragmentation routine.
1376 *
1377 * FIXME: check if the fragmentation threshold exceeds
1378 * IEEE80211 max.
1379 */
1380 tid = ATH_AN_2_TID(an, bf->bf_tidno);
1381 hdr->seq_ctrl = cpu_to_le16(tid->seq_next <<
1382 IEEE80211_SEQ_SEQ_SHIFT);
1383 bf->bf_seqno = tid->seq_next;
1384 INCR(tid->seq_next, IEEE80211_SEQ_MAX);
1385 }
1386
1387 static int setup_tx_flags(struct ath_softc *sc, struct sk_buff *skb,
1388 struct ath_txq *txq)
1389 {
1390 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1391 int flags = 0;
1392
1393 flags |= ATH9K_TXDESC_CLRDMASK; /* needed for crypto errors */
1394 flags |= ATH9K_TXDESC_INTREQ;
1395
1396 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
1397 flags |= ATH9K_TXDESC_NOACK;
1398
1399 return flags;
1400 }
1401
1402 /*
1403 * rix - rate index
1404 * pktlen - total bytes (delims + data + fcs + pads + pad delims)
1405 * width - 0 for 20 MHz, 1 for 40 MHz
1406 * half_gi - to use 4us v/s 3.6 us for symbol time
1407 */
1408 static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, struct ath_buf *bf,
1409 int width, int half_gi, bool shortPreamble)
1410 {
1411 struct ath_rate_table *rate_table = sc->cur_rate_table;
1412 u32 nbits, nsymbits, duration, nsymbols;
1413 u8 rc;
1414 int streams, pktlen;
1415
1416 pktlen = bf_isaggr(bf) ? bf->bf_al : bf->bf_frmlen;
1417 rc = rate_table->info[rix].ratecode;
1418
1419 /* for legacy rates, use old function to compute packet duration */
1420 if (!IS_HT_RATE(rc))
1421 return ath9k_hw_computetxtime(sc->sc_ah, rate_table, pktlen,
1422 rix, shortPreamble);
1423
1424 /* find number of symbols: PLCP + data */
1425 nbits = (pktlen << 3) + OFDM_PLCP_BITS;
1426 nsymbits = bits_per_symbol[HT_RC_2_MCS(rc)][width];
1427 nsymbols = (nbits + nsymbits - 1) / nsymbits;
1428
1429 if (!half_gi)
1430 duration = SYMBOL_TIME(nsymbols);
1431 else
1432 duration = SYMBOL_TIME_HALFGI(nsymbols);
1433
1434 /* addup duration for legacy/ht training and signal fields */
1435 streams = HT_RC_2_STREAMS(rc);
1436 duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
1437
1438 return duration;
1439 }
1440
1441 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf)
1442 {
1443 struct ath_rate_table *rt = sc->cur_rate_table;
1444 struct ath9k_11n_rate_series series[4];
1445 struct sk_buff *skb;
1446 struct ieee80211_tx_info *tx_info;
1447 struct ieee80211_tx_rate *rates;
1448 struct ieee80211_hdr *hdr;
1449 int i, flags = 0;
1450 u8 rix = 0, ctsrate = 0;
1451 bool is_pspoll;
1452
1453 memset(series, 0, sizeof(struct ath9k_11n_rate_series) * 4);
1454
1455 skb = (struct sk_buff *)bf->bf_mpdu;
1456 tx_info = IEEE80211_SKB_CB(skb);
1457 rates = tx_info->control.rates;
1458 hdr = (struct ieee80211_hdr *)skb->data;
1459 is_pspoll = ieee80211_is_pspoll(hdr->frame_control);
1460
1461 /*
1462 * We check if Short Preamble is needed for the CTS rate by
1463 * checking the BSS's global flag.
1464 * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used.
1465 */
1466 if (sc->sc_flags & SC_OP_PREAMBLE_SHORT)
1467 ctsrate = rt->info[tx_info->control.rts_cts_rate_idx].ratecode |
1468 rt->info[tx_info->control.rts_cts_rate_idx].short_preamble;
1469 else
1470 ctsrate = rt->info[tx_info->control.rts_cts_rate_idx].ratecode;
1471
1472 /*
1473 * ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive.
1474 * Check the first rate in the series to decide whether RTS/CTS
1475 * or CTS-to-self has to be used.
1476 */
1477 if (rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT)
1478 flags = ATH9K_TXDESC_CTSENA;
1479 else if (rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS)
1480 flags = ATH9K_TXDESC_RTSENA;
1481
1482 /* FIXME: Handle aggregation protection */
1483 if (sc->config.ath_aggr_prot &&
1484 (!bf_isaggr(bf) || (bf_isaggr(bf) && bf->bf_al < 8192))) {
1485 flags = ATH9K_TXDESC_RTSENA;
1486 }
1487
1488 /* For AR5416 - RTS cannot be followed by a frame larger than 8K */
1489 if (bf_isaggr(bf) && (bf->bf_al > sc->sc_ah->caps.rts_aggr_limit))
1490 flags &= ~(ATH9K_TXDESC_RTSENA);
1491
1492 for (i = 0; i < 4; i++) {
1493 if (!rates[i].count || (rates[i].idx < 0))
1494 continue;
1495
1496 rix = rates[i].idx;
1497 series[i].Tries = rates[i].count;
1498 series[i].ChSel = sc->tx_chainmask;
1499
1500 if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
1501 series[i].Rate = rt->info[rix].ratecode |
1502 rt->info[rix].short_preamble;
1503 else
1504 series[i].Rate = rt->info[rix].ratecode;
1505
1506 if (rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS)
1507 series[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1508 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
1509 series[i].RateFlags |= ATH9K_RATESERIES_2040;
1510 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
1511 series[i].RateFlags |= ATH9K_RATESERIES_HALFGI;
1512
1513 series[i].PktDuration = ath_pkt_duration(sc, rix, bf,
1514 (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH) != 0,
1515 (rates[i].flags & IEEE80211_TX_RC_SHORT_GI),
1516 (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE));
1517 }
1518
1519 /* set dur_update_en for l-sig computation except for PS-Poll frames */
1520 ath9k_hw_set11n_ratescenario(sc->sc_ah, bf->bf_desc,
1521 bf->bf_lastbf->bf_desc,
1522 !is_pspoll, ctsrate,
1523 0, series, 4, flags);
1524
1525 if (sc->config.ath_aggr_prot && flags)
1526 ath9k_hw_set11n_burstduration(sc->sc_ah, bf->bf_desc, 8192);
1527 }
1528
1529 static int ath_tx_setup_buffer(struct ieee80211_hw *hw, struct ath_buf *bf,
1530 struct sk_buff *skb,
1531 struct ath_tx_control *txctl)
1532 {
1533 struct ath_wiphy *aphy = hw->priv;
1534 struct ath_softc *sc = aphy->sc;
1535 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1536 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1537 struct ath_tx_info_priv *tx_info_priv;
1538 int hdrlen;
1539 __le16 fc;
1540
1541 tx_info_priv = kzalloc(sizeof(*tx_info_priv), GFP_ATOMIC);
1542 if (unlikely(!tx_info_priv))
1543 return -ENOMEM;
1544 tx_info->rate_driver_data[0] = tx_info_priv;
1545 tx_info_priv->aphy = aphy;
1546 tx_info_priv->frame_type = txctl->frame_type;
1547 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1548 fc = hdr->frame_control;
1549
1550 ATH_TXBUF_RESET(bf);
1551
1552 bf->bf_frmlen = skb->len + FCS_LEN - (hdrlen & 3);
1553
1554 if (conf_is_ht(&sc->hw->conf) && !is_pae(skb))
1555 bf->bf_state.bf_type |= BUF_HT;
1556
1557 bf->bf_flags = setup_tx_flags(sc, skb, txctl->txq);
1558
1559 bf->bf_keytype = get_hw_crypto_keytype(skb);
1560 if (bf->bf_keytype != ATH9K_KEY_TYPE_CLEAR) {
1561 bf->bf_frmlen += tx_info->control.hw_key->icv_len;
1562 bf->bf_keyix = tx_info->control.hw_key->hw_key_idx;
1563 } else {
1564 bf->bf_keyix = ATH9K_TXKEYIX_INVALID;
1565 }
1566
1567 if (ieee80211_is_data_qos(fc) && (sc->sc_flags & SC_OP_TXAGGR))
1568 assign_aggr_tid_seqno(skb, bf);
1569
1570 bf->bf_mpdu = skb;
1571
1572 bf->bf_dmacontext = dma_map_single(sc->dev, skb->data,
1573 skb->len, DMA_TO_DEVICE);
1574 if (unlikely(dma_mapping_error(sc->dev, bf->bf_dmacontext))) {
1575 bf->bf_mpdu = NULL;
1576 DPRINTF(sc, ATH_DBG_CONFIG,
1577 "dma_mapping_error() on TX\n");
1578 return -ENOMEM;
1579 }
1580
1581 bf->bf_buf_addr = bf->bf_dmacontext;
1582 return 0;
1583 }
1584
1585 /* FIXME: tx power */
1586 static void ath_tx_start_dma(struct ath_softc *sc, struct ath_buf *bf,
1587 struct ath_tx_control *txctl)
1588 {
1589 struct sk_buff *skb = (struct sk_buff *)bf->bf_mpdu;
1590 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1591 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1592 struct ath_node *an = NULL;
1593 struct list_head bf_head;
1594 struct ath_desc *ds;
1595 struct ath_atx_tid *tid;
1596 struct ath_hw *ah = sc->sc_ah;
1597 int frm_type;
1598 __le16 fc;
1599
1600 frm_type = get_hw_packet_type(skb);
1601 fc = hdr->frame_control;
1602
1603 INIT_LIST_HEAD(&bf_head);
1604 list_add_tail(&bf->list, &bf_head);
1605
1606 ds = bf->bf_desc;
1607 ds->ds_link = 0;
1608 ds->ds_data = bf->bf_buf_addr;
1609
1610 ath9k_hw_set11n_txdesc(ah, ds, bf->bf_frmlen, frm_type, MAX_RATE_POWER,
1611 bf->bf_keyix, bf->bf_keytype, bf->bf_flags);
1612
1613 ath9k_hw_filltxdesc(ah, ds,
1614 skb->len, /* segment length */
1615 true, /* first segment */
1616 true, /* last segment */
1617 ds); /* first descriptor */
1618
1619 spin_lock_bh(&txctl->txq->axq_lock);
1620
1621 if (bf_isht(bf) && (sc->sc_flags & SC_OP_TXAGGR) &&
1622 tx_info->control.sta) {
1623 an = (struct ath_node *)tx_info->control.sta->drv_priv;
1624 tid = ATH_AN_2_TID(an, bf->bf_tidno);
1625
1626 if (!ieee80211_is_data_qos(fc)) {
1627 ath_tx_send_normal(sc, txctl->txq, &bf_head);
1628 goto tx_done;
1629 }
1630
1631 if (ath_aggr_query(sc, an, bf->bf_tidno)) {
1632 /*
1633 * Try aggregation if it's a unicast data frame
1634 * and the destination is HT capable.
1635 */
1636 ath_tx_send_ampdu(sc, tid, &bf_head, txctl);
1637 } else {
1638 /*
1639 * Send this frame as regular when ADDBA
1640 * exchange is neither complete nor pending.
1641 */
1642 ath_tx_send_ht_normal(sc, txctl->txq,
1643 tid, &bf_head);
1644 }
1645 } else {
1646 ath_tx_send_normal(sc, txctl->txq, &bf_head);
1647 }
1648
1649 tx_done:
1650 spin_unlock_bh(&txctl->txq->axq_lock);
1651 }
1652
1653 /* Upon failure caller should free skb */
1654 int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
1655 struct ath_tx_control *txctl)
1656 {
1657 struct ath_wiphy *aphy = hw->priv;
1658 struct ath_softc *sc = aphy->sc;
1659 struct ath_buf *bf;
1660 int r;
1661
1662 bf = ath_tx_get_buffer(sc);
1663 if (!bf) {
1664 DPRINTF(sc, ATH_DBG_XMIT, "TX buffers are full\n");
1665 return -1;
1666 }
1667
1668 r = ath_tx_setup_buffer(hw, bf, skb, txctl);
1669 if (unlikely(r)) {
1670 struct ath_txq *txq = txctl->txq;
1671
1672 DPRINTF(sc, ATH_DBG_FATAL, "TX mem alloc failure\n");
1673
1674 /* upon ath_tx_processq() this TX queue will be resumed, we
1675 * guarantee this will happen by knowing beforehand that
1676 * we will at least have to run TX completionon one buffer
1677 * on the queue */
1678 spin_lock_bh(&txq->axq_lock);
1679 if (sc->tx.txq[txq->axq_qnum].axq_depth > 1) {
1680 ieee80211_stop_queue(sc->hw,
1681 skb_get_queue_mapping(skb));
1682 txq->stopped = 1;
1683 }
1684 spin_unlock_bh(&txq->axq_lock);
1685
1686 spin_lock_bh(&sc->tx.txbuflock);
1687 list_add_tail(&bf->list, &sc->tx.txbuf);
1688 spin_unlock_bh(&sc->tx.txbuflock);
1689
1690 return r;
1691 }
1692
1693 ath_tx_start_dma(sc, bf, txctl);
1694
1695 return 0;
1696 }
1697
1698 void ath_tx_cabq(struct ieee80211_hw *hw, struct sk_buff *skb)
1699 {
1700 struct ath_wiphy *aphy = hw->priv;
1701 struct ath_softc *sc = aphy->sc;
1702 int hdrlen, padsize;
1703 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1704 struct ath_tx_control txctl;
1705
1706 memset(&txctl, 0, sizeof(struct ath_tx_control));
1707
1708 /*
1709 * As a temporary workaround, assign seq# here; this will likely need
1710 * to be cleaned up to work better with Beacon transmission and virtual
1711 * BSSes.
1712 */
1713 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1714 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
1715 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
1716 sc->tx.seq_no += 0x10;
1717 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
1718 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
1719 }
1720
1721 /* Add the padding after the header if this is not already done */
1722 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1723 if (hdrlen & 3) {
1724 padsize = hdrlen % 4;
1725 if (skb_headroom(skb) < padsize) {
1726 DPRINTF(sc, ATH_DBG_XMIT, "TX CABQ padding failed\n");
1727 dev_kfree_skb_any(skb);
1728 return;
1729 }
1730 skb_push(skb, padsize);
1731 memmove(skb->data, skb->data + padsize, hdrlen);
1732 }
1733
1734 txctl.txq = sc->beacon.cabq;
1735
1736 DPRINTF(sc, ATH_DBG_XMIT, "transmitting CABQ packet, skb: %p\n", skb);
1737
1738 if (ath_tx_start(hw, skb, &txctl) != 0) {
1739 DPRINTF(sc, ATH_DBG_XMIT, "CABQ TX failed\n");
1740 goto exit;
1741 }
1742
1743 return;
1744 exit:
1745 dev_kfree_skb_any(skb);
1746 }
1747
1748 /*****************/
1749 /* TX Completion */
1750 /*****************/
1751
1752 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
1753 int tx_flags)
1754 {
1755 struct ieee80211_hw *hw = sc->hw;
1756 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1757 struct ath_tx_info_priv *tx_info_priv = ATH_TX_INFO_PRIV(tx_info);
1758 int hdrlen, padsize;
1759 int frame_type = ATH9K_NOT_INTERNAL;
1760
1761 DPRINTF(sc, ATH_DBG_XMIT, "TX complete: skb: %p\n", skb);
1762
1763 if (tx_info_priv) {
1764 hw = tx_info_priv->aphy->hw;
1765 frame_type = tx_info_priv->frame_type;
1766 }
1767
1768 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK ||
1769 tx_info->flags & IEEE80211_TX_STAT_TX_FILTERED) {
1770 kfree(tx_info_priv);
1771 tx_info->rate_driver_data[0] = NULL;
1772 }
1773
1774 if (tx_flags & ATH_TX_BAR)
1775 tx_info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
1776
1777 if (!(tx_flags & (ATH_TX_ERROR | ATH_TX_XRETRY))) {
1778 /* Frame was ACKed */
1779 tx_info->flags |= IEEE80211_TX_STAT_ACK;
1780 }
1781
1782 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1783 padsize = hdrlen & 3;
1784 if (padsize && hdrlen >= 24) {
1785 /*
1786 * Remove MAC header padding before giving the frame back to
1787 * mac80211.
1788 */
1789 memmove(skb->data + padsize, skb->data, hdrlen);
1790 skb_pull(skb, padsize);
1791 }
1792
1793 if (frame_type == ATH9K_NOT_INTERNAL)
1794 ieee80211_tx_status(hw, skb);
1795 else
1796 ath9k_tx_status(hw, skb);
1797 }
1798
1799 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
1800 struct list_head *bf_q,
1801 int txok, int sendbar)
1802 {
1803 struct sk_buff *skb = bf->bf_mpdu;
1804 unsigned long flags;
1805 int tx_flags = 0;
1806
1807
1808 if (sendbar)
1809 tx_flags = ATH_TX_BAR;
1810
1811 if (!txok) {
1812 tx_flags |= ATH_TX_ERROR;
1813
1814 if (bf_isxretried(bf))
1815 tx_flags |= ATH_TX_XRETRY;
1816 }
1817
1818 dma_unmap_single(sc->dev, bf->bf_dmacontext, skb->len, DMA_TO_DEVICE);
1819 ath_tx_complete(sc, skb, tx_flags);
1820
1821 /*
1822 * Return the list of ath_buf of this mpdu to free queue
1823 */
1824 spin_lock_irqsave(&sc->tx.txbuflock, flags);
1825 list_splice_tail_init(bf_q, &sc->tx.txbuf);
1826 spin_unlock_irqrestore(&sc->tx.txbuflock, flags);
1827 }
1828
1829 static int ath_tx_num_badfrms(struct ath_softc *sc, struct ath_buf *bf,
1830 int txok)
1831 {
1832 struct ath_buf *bf_last = bf->bf_lastbf;
1833 struct ath_desc *ds = bf_last->bf_desc;
1834 u16 seq_st = 0;
1835 u32 ba[WME_BA_BMP_SIZE >> 5];
1836 int ba_index;
1837 int nbad = 0;
1838 int isaggr = 0;
1839
1840 if (ds->ds_txstat.ts_flags == ATH9K_TX_SW_ABORTED)
1841 return 0;
1842
1843 isaggr = bf_isaggr(bf);
1844 if (isaggr) {
1845 seq_st = ATH_DS_BA_SEQ(ds);
1846 memcpy(ba, ATH_DS_BA_BITMAP(ds), WME_BA_BMP_SIZE >> 3);
1847 }
1848
1849 while (bf) {
1850 ba_index = ATH_BA_INDEX(seq_st, bf->bf_seqno);
1851 if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index)))
1852 nbad++;
1853
1854 bf = bf->bf_next;
1855 }
1856
1857 return nbad;
1858 }
1859
1860 static void ath_tx_rc_status(struct ath_buf *bf, struct ath_desc *ds,
1861 int nbad, int txok, bool update_rc)
1862 {
1863 struct sk_buff *skb = (struct sk_buff *)bf->bf_mpdu;
1864 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1865 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1866 struct ath_tx_info_priv *tx_info_priv = ATH_TX_INFO_PRIV(tx_info);
1867 struct ieee80211_hw *hw = tx_info_priv->aphy->hw;
1868 u8 i, tx_rateindex;
1869
1870 if (txok)
1871 tx_info->status.ack_signal = ds->ds_txstat.ts_rssi;
1872
1873 tx_rateindex = ds->ds_txstat.ts_rateindex;
1874 WARN_ON(tx_rateindex >= hw->max_rates);
1875
1876 tx_info_priv->update_rc = update_rc;
1877 if (ds->ds_txstat.ts_status & ATH9K_TXERR_FILT)
1878 tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
1879
1880 if ((ds->ds_txstat.ts_status & ATH9K_TXERR_FILT) == 0 &&
1881 (bf->bf_flags & ATH9K_TXDESC_NOACK) == 0 && update_rc) {
1882 if (ieee80211_is_data(hdr->frame_control)) {
1883 memcpy(&tx_info_priv->tx, &ds->ds_txstat,
1884 sizeof(tx_info_priv->tx));
1885 tx_info_priv->n_frames = bf->bf_nframes;
1886 tx_info_priv->n_bad_frames = nbad;
1887 }
1888 }
1889
1890 for (i = tx_rateindex + 1; i < hw->max_rates; i++)
1891 tx_info->status.rates[i].count = 0;
1892
1893 tx_info->status.rates[tx_rateindex].count = bf->bf_retries + 1;
1894 }
1895
1896 static void ath_wake_mac80211_queue(struct ath_softc *sc, struct ath_txq *txq)
1897 {
1898 int qnum;
1899
1900 spin_lock_bh(&txq->axq_lock);
1901 if (txq->stopped &&
1902 sc->tx.txq[txq->axq_qnum].axq_depth <= (ATH_TXBUF - 20)) {
1903 qnum = ath_get_mac80211_qnum(txq->axq_qnum, sc);
1904 if (qnum != -1) {
1905 ieee80211_wake_queue(sc->hw, qnum);
1906 txq->stopped = 0;
1907 }
1908 }
1909 spin_unlock_bh(&txq->axq_lock);
1910 }
1911
1912 static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
1913 {
1914 struct ath_hw *ah = sc->sc_ah;
1915 struct ath_buf *bf, *lastbf, *bf_held = NULL;
1916 struct list_head bf_head;
1917 struct ath_desc *ds;
1918 int txok;
1919 int status;
1920
1921 DPRINTF(sc, ATH_DBG_QUEUE, "tx queue %d (%x), link %p\n",
1922 txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum),
1923 txq->axq_link);
1924
1925 for (;;) {
1926 spin_lock_bh(&txq->axq_lock);
1927 if (list_empty(&txq->axq_q)) {
1928 txq->axq_link = NULL;
1929 txq->axq_linkbuf = NULL;
1930 spin_unlock_bh(&txq->axq_lock);
1931 break;
1932 }
1933 bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
1934
1935 /*
1936 * There is a race condition that a BH gets scheduled
1937 * after sw writes TxE and before hw re-load the last
1938 * descriptor to get the newly chained one.
1939 * Software must keep the last DONE descriptor as a
1940 * holding descriptor - software does so by marking
1941 * it with the STALE flag.
1942 */
1943 bf_held = NULL;
1944 if (bf->bf_status & ATH_BUFSTATUS_STALE) {
1945 bf_held = bf;
1946 if (list_is_last(&bf_held->list, &txq->axq_q)) {
1947 txq->axq_link = NULL;
1948 txq->axq_linkbuf = NULL;
1949 spin_unlock_bh(&txq->axq_lock);
1950
1951 /*
1952 * The holding descriptor is the last
1953 * descriptor in queue. It's safe to remove
1954 * the last holding descriptor in BH context.
1955 */
1956 spin_lock_bh(&sc->tx.txbuflock);
1957 list_move_tail(&bf_held->list, &sc->tx.txbuf);
1958 spin_unlock_bh(&sc->tx.txbuflock);
1959
1960 break;
1961 } else {
1962 bf = list_entry(bf_held->list.next,
1963 struct ath_buf, list);
1964 }
1965 }
1966
1967 lastbf = bf->bf_lastbf;
1968 ds = lastbf->bf_desc;
1969
1970 status = ath9k_hw_txprocdesc(ah, ds);
1971 if (status == -EINPROGRESS) {
1972 spin_unlock_bh(&txq->axq_lock);
1973 break;
1974 }
1975 if (bf->bf_desc == txq->axq_lastdsWithCTS)
1976 txq->axq_lastdsWithCTS = NULL;
1977 if (ds == txq->axq_gatingds)
1978 txq->axq_gatingds = NULL;
1979
1980 /*
1981 * Remove ath_buf's of the same transmit unit from txq,
1982 * however leave the last descriptor back as the holding
1983 * descriptor for hw.
1984 */
1985 lastbf->bf_status |= ATH_BUFSTATUS_STALE;
1986 INIT_LIST_HEAD(&bf_head);
1987 if (!list_is_singular(&lastbf->list))
1988 list_cut_position(&bf_head,
1989 &txq->axq_q, lastbf->list.prev);
1990
1991 txq->axq_depth--;
1992 if (bf_isaggr(bf))
1993 txq->axq_aggr_depth--;
1994
1995 txok = (ds->ds_txstat.ts_status == 0);
1996 spin_unlock_bh(&txq->axq_lock);
1997
1998 if (bf_held) {
1999 spin_lock_bh(&sc->tx.txbuflock);
2000 list_move_tail(&bf_held->list, &sc->tx.txbuf);
2001 spin_unlock_bh(&sc->tx.txbuflock);
2002 }
2003
2004 if (!bf_isampdu(bf)) {
2005 /*
2006 * This frame is sent out as a single frame.
2007 * Use hardware retry status for this frame.
2008 */
2009 bf->bf_retries = ds->ds_txstat.ts_longretry;
2010 if (ds->ds_txstat.ts_status & ATH9K_TXERR_XRETRY)
2011 bf->bf_state.bf_type |= BUF_XRETRY;
2012 ath_tx_rc_status(bf, ds, 0, txok, true);
2013 }
2014
2015 if (bf_isampdu(bf))
2016 ath_tx_complete_aggr(sc, txq, bf, &bf_head, txok);
2017 else
2018 ath_tx_complete_buf(sc, bf, &bf_head, txok, 0);
2019
2020 ath_wake_mac80211_queue(sc, txq);
2021
2022 spin_lock_bh(&txq->axq_lock);
2023 if (sc->sc_flags & SC_OP_TXAGGR)
2024 ath_txq_schedule(sc, txq);
2025 spin_unlock_bh(&txq->axq_lock);
2026 }
2027 }
2028
2029
2030 void ath_tx_tasklet(struct ath_softc *sc)
2031 {
2032 int i;
2033 u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1);
2034
2035 ath9k_hw_gettxintrtxqs(sc->sc_ah, &qcumask);
2036
2037 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2038 if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i)))
2039 ath_tx_processq(sc, &sc->tx.txq[i]);
2040 }
2041 }
2042
2043 /*****************/
2044 /* Init, Cleanup */
2045 /*****************/
2046
2047 int ath_tx_init(struct ath_softc *sc, int nbufs)
2048 {
2049 int error = 0;
2050
2051 do {
2052 spin_lock_init(&sc->tx.txbuflock);
2053
2054 error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf,
2055 "tx", nbufs, 1);
2056 if (error != 0) {
2057 DPRINTF(sc, ATH_DBG_FATAL,
2058 "Failed to allocate tx descriptors: %d\n",
2059 error);
2060 break;
2061 }
2062
2063 error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf,
2064 "beacon", ATH_BCBUF, 1);
2065 if (error != 0) {
2066 DPRINTF(sc, ATH_DBG_FATAL,
2067 "Failed to allocate beacon descriptors: %d\n",
2068 error);
2069 break;
2070 }
2071
2072 } while (0);
2073
2074 if (error != 0)
2075 ath_tx_cleanup(sc);
2076
2077 return error;
2078 }
2079
2080 int ath_tx_cleanup(struct ath_softc *sc)
2081 {
2082 if (sc->beacon.bdma.dd_desc_len != 0)
2083 ath_descdma_cleanup(sc, &sc->beacon.bdma, &sc->beacon.bbuf);
2084
2085 if (sc->tx.txdma.dd_desc_len != 0)
2086 ath_descdma_cleanup(sc, &sc->tx.txdma, &sc->tx.txbuf);
2087
2088 return 0;
2089 }
2090
2091 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an)
2092 {
2093 struct ath_atx_tid *tid;
2094 struct ath_atx_ac *ac;
2095 int tidno, acno;
2096
2097 for (tidno = 0, tid = &an->tid[tidno];
2098 tidno < WME_NUM_TID;
2099 tidno++, tid++) {
2100 tid->an = an;
2101 tid->tidno = tidno;
2102 tid->seq_start = tid->seq_next = 0;
2103 tid->baw_size = WME_MAX_BA;
2104 tid->baw_head = tid->baw_tail = 0;
2105 tid->sched = false;
2106 tid->paused = false;
2107 tid->state &= ~AGGR_CLEANUP;
2108 INIT_LIST_HEAD(&tid->buf_q);
2109 acno = TID_TO_WME_AC(tidno);
2110 tid->ac = &an->ac[acno];
2111 tid->state &= ~AGGR_ADDBA_COMPLETE;
2112 tid->state &= ~AGGR_ADDBA_PROGRESS;
2113 tid->addba_exchangeattempts = 0;
2114 }
2115
2116 for (acno = 0, ac = &an->ac[acno];
2117 acno < WME_NUM_AC; acno++, ac++) {
2118 ac->sched = false;
2119 INIT_LIST_HEAD(&ac->tid_q);
2120
2121 switch (acno) {
2122 case WME_AC_BE:
2123 ac->qnum = ath_tx_get_qnum(sc,
2124 ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BE);
2125 break;
2126 case WME_AC_BK:
2127 ac->qnum = ath_tx_get_qnum(sc,
2128 ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BK);
2129 break;
2130 case WME_AC_VI:
2131 ac->qnum = ath_tx_get_qnum(sc,
2132 ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_VI);
2133 break;
2134 case WME_AC_VO:
2135 ac->qnum = ath_tx_get_qnum(sc,
2136 ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_VO);
2137 break;
2138 }
2139 }
2140 }
2141
2142 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an)
2143 {
2144 int i;
2145 struct ath_atx_ac *ac, *ac_tmp;
2146 struct ath_atx_tid *tid, *tid_tmp;
2147 struct ath_txq *txq;
2148
2149 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2150 if (ATH_TXQ_SETUP(sc, i)) {
2151 txq = &sc->tx.txq[i];
2152
2153 spin_lock(&txq->axq_lock);
2154
2155 list_for_each_entry_safe(ac,
2156 ac_tmp, &txq->axq_acq, list) {
2157 tid = list_first_entry(&ac->tid_q,
2158 struct ath_atx_tid, list);
2159 if (tid && tid->an != an)
2160 continue;
2161 list_del(&ac->list);
2162 ac->sched = false;
2163
2164 list_for_each_entry_safe(tid,
2165 tid_tmp, &ac->tid_q, list) {
2166 list_del(&tid->list);
2167 tid->sched = false;
2168 ath_tid_drain(sc, txq, tid);
2169 tid->state &= ~AGGR_ADDBA_COMPLETE;
2170 tid->addba_exchangeattempts = 0;
2171 tid->state &= ~AGGR_CLEANUP;
2172 }
2173 }
2174
2175 spin_unlock(&txq->axq_lock);
2176 }
2177 }
2178 }
Linux kernel - Deliverables
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