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ath9k: Use mac80211 for multicast power save buffering
[deliverable/linux.git] / drivers / net / wireless / ath9k / xmit.c
1 /*
2 * Copyright (c) 2008 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 /*
18 * Implementation of transmit path.
19 */
20
21 #include "core.h"
22
23 #define BITS_PER_BYTE 8
24 #define OFDM_PLCP_BITS 22
25 #define HT_RC_2_MCS(_rc) ((_rc) & 0x0f)
26 #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
27 #define L_STF 8
28 #define L_LTF 8
29 #define L_SIG 4
30 #define HT_SIG 8
31 #define HT_STF 4
32 #define HT_LTF(_ns) (4 * (_ns))
33 #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */
34 #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */
35 #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
36 #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
37
38 #define OFDM_SIFS_TIME 16
39
40 static u32 bits_per_symbol[][2] = {
41 /* 20MHz 40MHz */
42 { 26, 54 }, /* 0: BPSK */
43 { 52, 108 }, /* 1: QPSK 1/2 */
44 { 78, 162 }, /* 2: QPSK 3/4 */
45 { 104, 216 }, /* 3: 16-QAM 1/2 */
46 { 156, 324 }, /* 4: 16-QAM 3/4 */
47 { 208, 432 }, /* 5: 64-QAM 2/3 */
48 { 234, 486 }, /* 6: 64-QAM 3/4 */
49 { 260, 540 }, /* 7: 64-QAM 5/6 */
50 { 52, 108 }, /* 8: BPSK */
51 { 104, 216 }, /* 9: QPSK 1/2 */
52 { 156, 324 }, /* 10: QPSK 3/4 */
53 { 208, 432 }, /* 11: 16-QAM 1/2 */
54 { 312, 648 }, /* 12: 16-QAM 3/4 */
55 { 416, 864 }, /* 13: 64-QAM 2/3 */
56 { 468, 972 }, /* 14: 64-QAM 3/4 */
57 { 520, 1080 }, /* 15: 64-QAM 5/6 */
58 };
59
60 #define IS_HT_RATE(_rate) ((_rate) & 0x80)
61
62 /*
63 * Insert a chain of ath_buf (descriptors) on a txq and
64 * assume the descriptors are already chained together by caller.
65 * NB: must be called with txq lock held
66 */
67
68 static void ath_tx_txqaddbuf(struct ath_softc *sc,
69 struct ath_txq *txq, struct list_head *head)
70 {
71 struct ath_hal *ah = sc->sc_ah;
72 struct ath_buf *bf;
73 /*
74 * Insert the frame on the outbound list and
75 * pass it on to the hardware.
76 */
77
78 if (list_empty(head))
79 return;
80
81 bf = list_first_entry(head, struct ath_buf, list);
82
83 list_splice_tail_init(head, &txq->axq_q);
84 txq->axq_depth++;
85 txq->axq_totalqueued++;
86 txq->axq_linkbuf = list_entry(txq->axq_q.prev, struct ath_buf, list);
87
88 DPRINTF(sc, ATH_DBG_QUEUE,
89 "%s: txq depth = %d\n", __func__, txq->axq_depth);
90
91 if (txq->axq_link == NULL) {
92 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
93 DPRINTF(sc, ATH_DBG_XMIT,
94 "%s: TXDP[%u] = %llx (%p)\n",
95 __func__, txq->axq_qnum,
96 ito64(bf->bf_daddr), bf->bf_desc);
97 } else {
98 *txq->axq_link = bf->bf_daddr;
99 DPRINTF(sc, ATH_DBG_XMIT, "%s: link[%u] (%p)=%llx (%p)\n",
100 __func__,
101 txq->axq_qnum, txq->axq_link,
102 ito64(bf->bf_daddr), bf->bf_desc);
103 }
104 txq->axq_link = &(bf->bf_lastbf->bf_desc->ds_link);
105 ath9k_hw_txstart(ah, txq->axq_qnum);
106 }
107
108 /* Get transmit rate index using rate in Kbps */
109
110 static int ath_tx_findindex(const struct ath9k_rate_table *rt, int rate)
111 {
112 int i;
113 int ndx = 0;
114
115 for (i = 0; i < rt->rateCount; i++) {
116 if (rt->info[i].rateKbps == rate) {
117 ndx = i;
118 break;
119 }
120 }
121
122 return ndx;
123 }
124
125 /* Check if it's okay to send out aggregates */
126
127 static int ath_aggr_query(struct ath_softc *sc,
128 struct ath_node *an, u8 tidno)
129 {
130 struct ath_atx_tid *tid;
131 tid = ATH_AN_2_TID(an, tidno);
132
133 if (tid->addba_exchangecomplete || tid->addba_exchangeinprogress)
134 return 1;
135 else
136 return 0;
137 }
138
139 static enum ath9k_pkt_type get_hal_packet_type(struct ieee80211_hdr *hdr)
140 {
141 enum ath9k_pkt_type htype;
142 __le16 fc;
143
144 fc = hdr->frame_control;
145
146 /* Calculate Atheros packet type from IEEE80211 packet header */
147
148 if (ieee80211_is_beacon(fc))
149 htype = ATH9K_PKT_TYPE_BEACON;
150 else if (ieee80211_is_probe_resp(fc))
151 htype = ATH9K_PKT_TYPE_PROBE_RESP;
152 else if (ieee80211_is_atim(fc))
153 htype = ATH9K_PKT_TYPE_ATIM;
154 else if (ieee80211_is_pspoll(fc))
155 htype = ATH9K_PKT_TYPE_PSPOLL;
156 else
157 htype = ATH9K_PKT_TYPE_NORMAL;
158
159 return htype;
160 }
161
162 static void fill_min_rates(struct sk_buff *skb, struct ath_tx_control *txctl)
163 {
164 struct ieee80211_hdr *hdr;
165 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
166 struct ath_tx_info_priv *tx_info_priv;
167 __le16 fc;
168
169 hdr = (struct ieee80211_hdr *)skb->data;
170 fc = hdr->frame_control;
171 tx_info_priv = (struct ath_tx_info_priv *)tx_info->driver_data[0];
172
173 if (ieee80211_is_mgmt(fc) || ieee80211_is_ctl(fc)) {
174 txctl->use_minrate = 1;
175 txctl->min_rate = tx_info_priv->min_rate;
176 } else if (ieee80211_is_data(fc)) {
177 if (ieee80211_is_nullfunc(fc) ||
178 /* Port Access Entity (IEEE 802.1X) */
179 (skb->protocol == cpu_to_be16(0x888E))) {
180 txctl->use_minrate = 1;
181 txctl->min_rate = tx_info_priv->min_rate;
182 }
183 if (is_multicast_ether_addr(hdr->addr1))
184 txctl->mcast_rate = tx_info_priv->min_rate;
185 }
186
187 }
188
189 /* This function will setup additional txctl information, mostly rate stuff */
190 /* FIXME: seqno, ps */
191 static int ath_tx_prepare(struct ath_softc *sc,
192 struct sk_buff *skb,
193 struct ath_tx_control *txctl)
194 {
195 struct ieee80211_hw *hw = sc->hw;
196 struct ieee80211_hdr *hdr;
197 struct ath_rc_series *rcs;
198 struct ath_txq *txq = NULL;
199 const struct ath9k_rate_table *rt;
200 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
201 struct ath_tx_info_priv *tx_info_priv;
202 int hdrlen;
203 u8 rix, antenna;
204 __le16 fc;
205 u8 *qc;
206
207 txctl->dev = sc;
208 hdr = (struct ieee80211_hdr *)skb->data;
209 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
210 fc = hdr->frame_control;
211
212 rt = sc->sc_currates;
213 BUG_ON(!rt);
214
215 /* Fill misc fields */
216
217 spin_lock_bh(&sc->node_lock);
218 txctl->an = ath_node_get(sc, hdr->addr1);
219 /* create a temp node, if the node is not there already */
220 if (!txctl->an)
221 txctl->an = ath_node_attach(sc, hdr->addr1, 0);
222 spin_unlock_bh(&sc->node_lock);
223
224 if (ieee80211_is_data_qos(fc)) {
225 qc = ieee80211_get_qos_ctl(hdr);
226 txctl->tidno = qc[0] & 0xf;
227 }
228
229 txctl->if_id = 0;
230 txctl->nextfraglen = 0;
231 txctl->frmlen = skb->len + FCS_LEN - (hdrlen & 3);
232 txctl->txpower = MAX_RATE_POWER; /* FIXME */
233
234 /* Fill Key related fields */
235
236 txctl->keytype = ATH9K_KEY_TYPE_CLEAR;
237 txctl->keyix = ATH9K_TXKEYIX_INVALID;
238
239 if (tx_info->control.hw_key) {
240 txctl->keyix = tx_info->control.hw_key->hw_key_idx;
241 txctl->frmlen += tx_info->control.icv_len;
242
243 if (sc->sc_keytype == ATH9K_CIPHER_WEP)
244 txctl->keytype = ATH9K_KEY_TYPE_WEP;
245 else if (sc->sc_keytype == ATH9K_CIPHER_TKIP)
246 txctl->keytype = ATH9K_KEY_TYPE_TKIP;
247 else if (sc->sc_keytype == ATH9K_CIPHER_AES_CCM)
248 txctl->keytype = ATH9K_KEY_TYPE_AES;
249 }
250
251 /* Fill packet type */
252
253 txctl->atype = get_hal_packet_type(hdr);
254
255 /* Fill qnum */
256
257 if (unlikely(txctl->flags & ATH9K_TXDESC_CAB)) {
258 txctl->qnum = 0;
259 txq = sc->sc_cabq;
260 } else {
261 txctl->qnum = ath_get_hal_qnum(skb_get_queue_mapping(skb), sc);
262 txq = &sc->sc_txq[txctl->qnum];
263 }
264 spin_lock_bh(&txq->axq_lock);
265
266 /* Try to avoid running out of descriptors */
267 if (txq->axq_depth >= (ATH_TXBUF - 20) &&
268 !(txctl->flags & ATH9K_TXDESC_CAB)) {
269 DPRINTF(sc, ATH_DBG_FATAL,
270 "%s: TX queue: %d is full, depth: %d\n",
271 __func__,
272 txctl->qnum,
273 txq->axq_depth);
274 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
275 txq->stopped = 1;
276 spin_unlock_bh(&txq->axq_lock);
277 return -1;
278 }
279
280 spin_unlock_bh(&txq->axq_lock);
281
282 /* Fill rate */
283
284 fill_min_rates(skb, txctl);
285
286 /* Fill flags */
287
288 txctl->flags |= ATH9K_TXDESC_CLRDMASK; /* needed for crypto errors */
289
290 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
291 txctl->flags |= ATH9K_TXDESC_NOACK;
292 if (tx_info->flags & IEEE80211_TX_CTL_USE_RTS_CTS)
293 txctl->flags |= ATH9K_TXDESC_RTSENA;
294
295 /*
296 * Setup for rate calculations.
297 */
298 tx_info_priv = (struct ath_tx_info_priv *)tx_info->driver_data[0];
299 rcs = tx_info_priv->rcs;
300
301 if (ieee80211_is_data(fc) && !txctl->use_minrate) {
302
303 /* Enable HT only for DATA frames and not for EAPOL */
304 txctl->ht = (hw->conf.ht_conf.ht_supported &&
305 (tx_info->flags & IEEE80211_TX_CTL_AMPDU));
306
307 if (is_multicast_ether_addr(hdr->addr1)) {
308 rcs[0].rix = (u8)
309 ath_tx_findindex(rt, txctl->mcast_rate);
310
311 /*
312 * mcast packets are not re-tried.
313 */
314 rcs[0].tries = 1;
315 }
316 /* For HT capable stations, we save tidno for later use.
317 * We also override seqno set by upper layer with the one
318 * in tx aggregation state.
319 *
320 * First, the fragmentation stat is determined.
321 * If fragmentation is on, the sequence number is
322 * not overridden, since it has been
323 * incremented by the fragmentation routine.
324 */
325 if (likely(!(txctl->flags & ATH9K_TXDESC_FRAG_IS_ON)) &&
326 txctl->ht && (sc->sc_flags & SC_OP_TXAGGR)) {
327 struct ath_atx_tid *tid;
328
329 tid = ATH_AN_2_TID(txctl->an, txctl->tidno);
330
331 hdr->seq_ctrl = cpu_to_le16(tid->seq_next <<
332 IEEE80211_SEQ_SEQ_SHIFT);
333 txctl->seqno = tid->seq_next;
334 INCR(tid->seq_next, IEEE80211_SEQ_MAX);
335 }
336 } else {
337 /* for management and control frames,
338 * or for NULL and EAPOL frames */
339 if (txctl->min_rate)
340 rcs[0].rix = ath_rate_findrateix(sc, txctl->min_rate);
341 else
342 rcs[0].rix = 0;
343 rcs[0].tries = ATH_MGT_TXMAXTRY;
344 }
345 rix = rcs[0].rix;
346
347 /*
348 * Calculate duration. This logically belongs in the 802.11
349 * layer but it lacks sufficient information to calculate it.
350 */
351 if ((txctl->flags & ATH9K_TXDESC_NOACK) == 0 && !ieee80211_is_ctl(fc)) {
352 u16 dur;
353 /*
354 * XXX not right with fragmentation.
355 */
356 if (sc->sc_flags & SC_OP_PREAMBLE_SHORT)
357 dur = rt->info[rix].spAckDuration;
358 else
359 dur = rt->info[rix].lpAckDuration;
360
361 if (le16_to_cpu(hdr->frame_control) &
362 IEEE80211_FCTL_MOREFRAGS) {
363 dur += dur; /* Add additional 'SIFS + ACK' */
364
365 /*
366 ** Compute size of next fragment in order to compute
367 ** durations needed to update NAV.
368 ** The last fragment uses the ACK duration only.
369 ** Add time for next fragment.
370 */
371 dur += ath9k_hw_computetxtime(sc->sc_ah, rt,
372 txctl->nextfraglen,
373 rix,
374 (sc->sc_flags & SC_OP_PREAMBLE_SHORT));
375 }
376
377 if (ieee80211_has_morefrags(fc) ||
378 (le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG)) {
379 /*
380 ** Force hardware to use computed duration for next
381 ** fragment by disabling multi-rate retry, which
382 ** updates duration based on the multi-rate
383 ** duration table.
384 */
385 rcs[1].tries = rcs[2].tries = rcs[3].tries = 0;
386 rcs[1].rix = rcs[2].rix = rcs[3].rix = 0;
387 /* reset tries but keep rate index */
388 rcs[0].tries = ATH_TXMAXTRY;
389 }
390
391 hdr->duration_id = cpu_to_le16(dur);
392 }
393
394 /*
395 * Determine if a tx interrupt should be generated for
396 * this descriptor. We take a tx interrupt to reap
397 * descriptors when the h/w hits an EOL condition or
398 * when the descriptor is specifically marked to generate
399 * an interrupt. We periodically mark descriptors in this
400 * way to insure timely replenishing of the supply needed
401 * for sending frames. Defering interrupts reduces system
402 * load and potentially allows more concurrent work to be
403 * done but if done to aggressively can cause senders to
404 * backup.
405 *
406 * NB: use >= to deal with sc_txintrperiod changing
407 * dynamically through sysctl.
408 */
409 spin_lock_bh(&txq->axq_lock);
410 if ((++txq->axq_intrcnt >= sc->sc_txintrperiod)) {
411 txctl->flags |= ATH9K_TXDESC_INTREQ;
412 txq->axq_intrcnt = 0;
413 }
414 spin_unlock_bh(&txq->axq_lock);
415
416 if (is_multicast_ether_addr(hdr->addr1)) {
417 antenna = sc->sc_mcastantenna + 1;
418 sc->sc_mcastantenna = (sc->sc_mcastantenna + 1) & 0x1;
419 }
420
421 return 0;
422 }
423
424 /* To complete a chain of buffers associated a frame */
425
426 static void ath_tx_complete_buf(struct ath_softc *sc,
427 struct ath_buf *bf,
428 struct list_head *bf_q,
429 int txok, int sendbar)
430 {
431 struct sk_buff *skb = bf->bf_mpdu;
432 struct ath_xmit_status tx_status;
433
434 /*
435 * Set retry information.
436 * NB: Don't use the information in the descriptor, because the frame
437 * could be software retried.
438 */
439 tx_status.retries = bf->bf_retries;
440 tx_status.flags = 0;
441
442 if (sendbar)
443 tx_status.flags = ATH_TX_BAR;
444
445 if (!txok) {
446 tx_status.flags |= ATH_TX_ERROR;
447
448 if (bf_isxretried(bf))
449 tx_status.flags |= ATH_TX_XRETRY;
450 }
451 /* Unmap this frame */
452 pci_unmap_single(sc->pdev,
453 bf->bf_dmacontext,
454 skb->len,
455 PCI_DMA_TODEVICE);
456 /* complete this frame */
457 ath_tx_complete(sc, skb, &tx_status, bf->bf_node);
458
459 /*
460 * Return the list of ath_buf of this mpdu to free queue
461 */
462 spin_lock_bh(&sc->sc_txbuflock);
463 list_splice_tail_init(bf_q, &sc->sc_txbuf);
464 spin_unlock_bh(&sc->sc_txbuflock);
465 }
466
467 /*
468 * queue up a dest/ac pair for tx scheduling
469 * NB: must be called with txq lock held
470 */
471
472 static void ath_tx_queue_tid(struct ath_txq *txq, struct ath_atx_tid *tid)
473 {
474 struct ath_atx_ac *ac = tid->ac;
475
476 /*
477 * if tid is paused, hold off
478 */
479 if (tid->paused)
480 return;
481
482 /*
483 * add tid to ac atmost once
484 */
485 if (tid->sched)
486 return;
487
488 tid->sched = true;
489 list_add_tail(&tid->list, &ac->tid_q);
490
491 /*
492 * add node ac to txq atmost once
493 */
494 if (ac->sched)
495 return;
496
497 ac->sched = true;
498 list_add_tail(&ac->list, &txq->axq_acq);
499 }
500
501 /* pause a tid */
502
503 static void ath_tx_pause_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
504 {
505 struct ath_txq *txq = &sc->sc_txq[tid->ac->qnum];
506
507 spin_lock_bh(&txq->axq_lock);
508
509 tid->paused++;
510
511 spin_unlock_bh(&txq->axq_lock);
512 }
513
514 /* resume a tid and schedule aggregate */
515
516 void ath_tx_resume_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
517 {
518 struct ath_txq *txq = &sc->sc_txq[tid->ac->qnum];
519
520 ASSERT(tid->paused > 0);
521 spin_lock_bh(&txq->axq_lock);
522
523 tid->paused--;
524
525 if (tid->paused > 0)
526 goto unlock;
527
528 if (list_empty(&tid->buf_q))
529 goto unlock;
530
531 /*
532 * Add this TID to scheduler and try to send out aggregates
533 */
534 ath_tx_queue_tid(txq, tid);
535 ath_txq_schedule(sc, txq);
536 unlock:
537 spin_unlock_bh(&txq->axq_lock);
538 }
539
540 /* Compute the number of bad frames */
541
542 static int ath_tx_num_badfrms(struct ath_softc *sc,
543 struct ath_buf *bf, int txok)
544 {
545 struct ath_node *an = bf->bf_node;
546 int isnodegone = (an->an_flags & ATH_NODE_CLEAN);
547 struct ath_buf *bf_last = bf->bf_lastbf;
548 struct ath_desc *ds = bf_last->bf_desc;
549 u16 seq_st = 0;
550 u32 ba[WME_BA_BMP_SIZE >> 5];
551 int ba_index;
552 int nbad = 0;
553 int isaggr = 0;
554
555 if (isnodegone || ds->ds_txstat.ts_flags == ATH9K_TX_SW_ABORTED)
556 return 0;
557
558 isaggr = bf_isaggr(bf);
559 if (isaggr) {
560 seq_st = ATH_DS_BA_SEQ(ds);
561 memcpy(ba, ATH_DS_BA_BITMAP(ds), WME_BA_BMP_SIZE >> 3);
562 }
563
564 while (bf) {
565 ba_index = ATH_BA_INDEX(seq_st, bf->bf_seqno);
566 if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index)))
567 nbad++;
568
569 bf = bf->bf_next;
570 }
571
572 return nbad;
573 }
574
575 static void ath_tx_set_retry(struct ath_softc *sc, struct ath_buf *bf)
576 {
577 struct sk_buff *skb;
578 struct ieee80211_hdr *hdr;
579
580 bf->bf_state.bf_type |= BUF_RETRY;
581 bf->bf_retries++;
582
583 skb = bf->bf_mpdu;
584 hdr = (struct ieee80211_hdr *)skb->data;
585 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY);
586 }
587
588 /* Update block ack window */
589
590 static void ath_tx_update_baw(struct ath_softc *sc,
591 struct ath_atx_tid *tid, int seqno)
592 {
593 int index, cindex;
594
595 index = ATH_BA_INDEX(tid->seq_start, seqno);
596 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
597
598 tid->tx_buf[cindex] = NULL;
599
600 while (tid->baw_head != tid->baw_tail && !tid->tx_buf[tid->baw_head]) {
601 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
602 INCR(tid->baw_head, ATH_TID_MAX_BUFS);
603 }
604 }
605
606 /*
607 * ath_pkt_dur - compute packet duration (NB: not NAV)
608 *
609 * rix - rate index
610 * pktlen - total bytes (delims + data + fcs + pads + pad delims)
611 * width - 0 for 20 MHz, 1 for 40 MHz
612 * half_gi - to use 4us v/s 3.6 us for symbol time
613 */
614
615 static u32 ath_pkt_duration(struct ath_softc *sc,
616 u8 rix,
617 struct ath_buf *bf,
618 int width,
619 int half_gi,
620 bool shortPreamble)
621 {
622 const struct ath9k_rate_table *rt = sc->sc_currates;
623 u32 nbits, nsymbits, duration, nsymbols;
624 u8 rc;
625 int streams, pktlen;
626
627 pktlen = bf_isaggr(bf) ? bf->bf_al : bf->bf_frmlen;
628 rc = rt->info[rix].rateCode;
629
630 /*
631 * for legacy rates, use old function to compute packet duration
632 */
633 if (!IS_HT_RATE(rc))
634 return ath9k_hw_computetxtime(sc->sc_ah,
635 rt,
636 pktlen,
637 rix,
638 shortPreamble);
639 /*
640 * find number of symbols: PLCP + data
641 */
642 nbits = (pktlen << 3) + OFDM_PLCP_BITS;
643 nsymbits = bits_per_symbol[HT_RC_2_MCS(rc)][width];
644 nsymbols = (nbits + nsymbits - 1) / nsymbits;
645
646 if (!half_gi)
647 duration = SYMBOL_TIME(nsymbols);
648 else
649 duration = SYMBOL_TIME_HALFGI(nsymbols);
650
651 /*
652 * addup duration for legacy/ht training and signal fields
653 */
654 streams = HT_RC_2_STREAMS(rc);
655 duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
656 return duration;
657 }
658
659 /* Rate module function to set rate related fields in tx descriptor */
660
661 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf)
662 {
663 struct ath_hal *ah = sc->sc_ah;
664 const struct ath9k_rate_table *rt;
665 struct ath_desc *ds = bf->bf_desc;
666 struct ath_desc *lastds = bf->bf_lastbf->bf_desc;
667 struct ath9k_11n_rate_series series[4];
668 int i, flags, rtsctsena = 0, dynamic_mimops = 0;
669 u32 ctsduration = 0;
670 u8 rix = 0, cix, ctsrate = 0;
671 u32 aggr_limit_with_rts = ah->ah_caps.rts_aggr_limit;
672 struct ath_node *an = (struct ath_node *) bf->bf_node;
673
674 /*
675 * get the cix for the lowest valid rix.
676 */
677 rt = sc->sc_currates;
678 for (i = 4; i--;) {
679 if (bf->bf_rcs[i].tries) {
680 rix = bf->bf_rcs[i].rix;
681 break;
682 }
683 }
684 flags = (bf->bf_flags & (ATH9K_TXDESC_RTSENA | ATH9K_TXDESC_CTSENA));
685 cix = rt->info[rix].controlRate;
686
687 /*
688 * If 802.11g protection is enabled, determine whether
689 * to use RTS/CTS or just CTS. Note that this is only
690 * done for OFDM/HT unicast frames.
691 */
692 if (sc->sc_protmode != PROT_M_NONE &&
693 (rt->info[rix].phy == PHY_OFDM ||
694 rt->info[rix].phy == PHY_HT) &&
695 (bf->bf_flags & ATH9K_TXDESC_NOACK) == 0) {
696 if (sc->sc_protmode == PROT_M_RTSCTS)
697 flags = ATH9K_TXDESC_RTSENA;
698 else if (sc->sc_protmode == PROT_M_CTSONLY)
699 flags = ATH9K_TXDESC_CTSENA;
700
701 cix = rt->info[sc->sc_protrix].controlRate;
702 rtsctsena = 1;
703 }
704
705 /* For 11n, the default behavior is to enable RTS for
706 * hw retried frames. We enable the global flag here and
707 * let rate series flags determine which rates will actually
708 * use RTS.
709 */
710 if ((ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) && bf_isdata(bf)) {
711 BUG_ON(!an);
712 /*
713 * 802.11g protection not needed, use our default behavior
714 */
715 if (!rtsctsena)
716 flags = ATH9K_TXDESC_RTSENA;
717 /*
718 * For dynamic MIMO PS, RTS needs to precede the first aggregate
719 * and the second aggregate should have any protection at all.
720 */
721 if (an->an_smmode == ATH_SM_PWRSAV_DYNAMIC) {
722 if (!bf_isaggrburst(bf)) {
723 flags = ATH9K_TXDESC_RTSENA;
724 dynamic_mimops = 1;
725 } else {
726 flags = 0;
727 }
728 }
729 }
730
731 /*
732 * Set protection if aggregate protection on
733 */
734 if (sc->sc_config.ath_aggr_prot &&
735 (!bf_isaggr(bf) || (bf_isaggr(bf) && bf->bf_al < 8192))) {
736 flags = ATH9K_TXDESC_RTSENA;
737 cix = rt->info[sc->sc_protrix].controlRate;
738 rtsctsena = 1;
739 }
740
741 /*
742 * For AR5416 - RTS cannot be followed by a frame larger than 8K.
743 */
744 if (bf_isaggr(bf) && (bf->bf_al > aggr_limit_with_rts)) {
745 /*
746 * Ensure that in the case of SM Dynamic power save
747 * while we are bursting the second aggregate the
748 * RTS is cleared.
749 */
750 flags &= ~(ATH9K_TXDESC_RTSENA);
751 }
752
753 /*
754 * CTS transmit rate is derived from the transmit rate
755 * by looking in the h/w rate table. We must also factor
756 * in whether or not a short preamble is to be used.
757 */
758 /* NB: cix is set above where RTS/CTS is enabled */
759 BUG_ON(cix == 0xff);
760 ctsrate = rt->info[cix].rateCode |
761 (bf_isshpreamble(bf) ? rt->info[cix].shortPreamble : 0);
762
763 /*
764 * Setup HAL rate series
765 */
766 memzero(series, sizeof(struct ath9k_11n_rate_series) * 4);
767
768 for (i = 0; i < 4; i++) {
769 if (!bf->bf_rcs[i].tries)
770 continue;
771
772 rix = bf->bf_rcs[i].rix;
773
774 series[i].Rate = rt->info[rix].rateCode |
775 (bf_isshpreamble(bf) ? rt->info[rix].shortPreamble : 0);
776
777 series[i].Tries = bf->bf_rcs[i].tries;
778
779 series[i].RateFlags = (
780 (bf->bf_rcs[i].flags & ATH_RC_RTSCTS_FLAG) ?
781 ATH9K_RATESERIES_RTS_CTS : 0) |
782 ((bf->bf_rcs[i].flags & ATH_RC_CW40_FLAG) ?
783 ATH9K_RATESERIES_2040 : 0) |
784 ((bf->bf_rcs[i].flags & ATH_RC_SGI_FLAG) ?
785 ATH9K_RATESERIES_HALFGI : 0);
786
787 series[i].PktDuration = ath_pkt_duration(
788 sc, rix, bf,
789 (bf->bf_rcs[i].flags & ATH_RC_CW40_FLAG) != 0,
790 (bf->bf_rcs[i].flags & ATH_RC_SGI_FLAG),
791 bf_isshpreamble(bf));
792
793 if ((an->an_smmode == ATH_SM_PWRSAV_STATIC) &&
794 (bf->bf_rcs[i].flags & ATH_RC_DS_FLAG) == 0) {
795 /*
796 * When sending to an HT node that has enabled static
797 * SM/MIMO power save, send at single stream rates but
798 * use maximum allowed transmit chains per user,
799 * hardware, regulatory, or country limits for
800 * better range.
801 */
802 series[i].ChSel = sc->sc_tx_chainmask;
803 } else {
804 if (bf_isht(bf))
805 series[i].ChSel =
806 ath_chainmask_sel_logic(sc, an);
807 else
808 series[i].ChSel = sc->sc_tx_chainmask;
809 }
810
811 if (rtsctsena)
812 series[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
813
814 /*
815 * Set RTS for all rates if node is in dynamic powersave
816 * mode and we are using dual stream rates.
817 */
818 if (dynamic_mimops && (bf->bf_rcs[i].flags & ATH_RC_DS_FLAG))
819 series[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
820 }
821
822 /*
823 * For non-HT devices, calculate RTS/CTS duration in software
824 * and disable multi-rate retry.
825 */
826 if (flags && !(ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT)) {
827 /*
828 * Compute the transmit duration based on the frame
829 * size and the size of an ACK frame. We call into the
830 * HAL to do the computation since it depends on the
831 * characteristics of the actual PHY being used.
832 *
833 * NB: CTS is assumed the same size as an ACK so we can
834 * use the precalculated ACK durations.
835 */
836 if (flags & ATH9K_TXDESC_RTSENA) { /* SIFS + CTS */
837 ctsduration += bf_isshpreamble(bf) ?
838 rt->info[cix].spAckDuration :
839 rt->info[cix].lpAckDuration;
840 }
841
842 ctsduration += series[0].PktDuration;
843
844 if ((bf->bf_flags & ATH9K_TXDESC_NOACK) == 0) { /* SIFS + ACK */
845 ctsduration += bf_isshpreamble(bf) ?
846 rt->info[rix].spAckDuration :
847 rt->info[rix].lpAckDuration;
848 }
849
850 /*
851 * Disable multi-rate retry when using RTS/CTS by clearing
852 * series 1, 2 and 3.
853 */
854 memzero(&series[1], sizeof(struct ath9k_11n_rate_series) * 3);
855 }
856
857 /*
858 * set dur_update_en for l-sig computation except for PS-Poll frames
859 */
860 ath9k_hw_set11n_ratescenario(ah, ds, lastds,
861 !bf_ispspoll(bf),
862 ctsrate,
863 ctsduration,
864 series, 4, flags);
865 if (sc->sc_config.ath_aggr_prot && flags)
866 ath9k_hw_set11n_burstduration(ah, ds, 8192);
867 }
868
869 /*
870 * Function to send a normal HT (non-AMPDU) frame
871 * NB: must be called with txq lock held
872 */
873
874 static int ath_tx_send_normal(struct ath_softc *sc,
875 struct ath_txq *txq,
876 struct ath_atx_tid *tid,
877 struct list_head *bf_head)
878 {
879 struct ath_buf *bf;
880 struct sk_buff *skb;
881 struct ieee80211_tx_info *tx_info;
882 struct ath_tx_info_priv *tx_info_priv;
883
884 BUG_ON(list_empty(bf_head));
885
886 bf = list_first_entry(bf_head, struct ath_buf, list);
887 bf->bf_state.bf_type &= ~BUF_AMPDU; /* regular HT frame */
888
889 skb = (struct sk_buff *)bf->bf_mpdu;
890 tx_info = IEEE80211_SKB_CB(skb);
891 tx_info_priv = (struct ath_tx_info_priv *)tx_info->driver_data[0];
892 memcpy(bf->bf_rcs, tx_info_priv->rcs, 4 * sizeof(tx_info_priv->rcs[0]));
893
894 /* update starting sequence number for subsequent ADDBA request */
895 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
896
897 /* Queue to h/w without aggregation */
898 bf->bf_nframes = 1;
899 bf->bf_lastbf = bf->bf_lastfrm; /* one single frame */
900 ath_buf_set_rate(sc, bf);
901 ath_tx_txqaddbuf(sc, txq, bf_head);
902
903 return 0;
904 }
905
906 /* flush tid's software queue and send frames as non-ampdu's */
907
908 static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
909 {
910 struct ath_txq *txq = &sc->sc_txq[tid->ac->qnum];
911 struct ath_buf *bf;
912 struct list_head bf_head;
913 INIT_LIST_HEAD(&bf_head);
914
915 ASSERT(tid->paused > 0);
916 spin_lock_bh(&txq->axq_lock);
917
918 tid->paused--;
919
920 if (tid->paused > 0) {
921 spin_unlock_bh(&txq->axq_lock);
922 return;
923 }
924
925 while (!list_empty(&tid->buf_q)) {
926 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
927 ASSERT(!bf_isretried(bf));
928 list_cut_position(&bf_head, &tid->buf_q, &bf->bf_lastfrm->list);
929 ath_tx_send_normal(sc, txq, tid, &bf_head);
930 }
931
932 spin_unlock_bh(&txq->axq_lock);
933 }
934
935 /* Completion routine of an aggregate */
936
937 static void ath_tx_complete_aggr_rifs(struct ath_softc *sc,
938 struct ath_txq *txq,
939 struct ath_buf *bf,
940 struct list_head *bf_q,
941 int txok)
942 {
943 struct ath_node *an = bf->bf_node;
944 struct ath_atx_tid *tid = ATH_AN_2_TID(an, bf->bf_tidno);
945 struct ath_buf *bf_last = bf->bf_lastbf;
946 struct ath_desc *ds = bf_last->bf_desc;
947 struct ath_buf *bf_next, *bf_lastq = NULL;
948 struct list_head bf_head, bf_pending;
949 u16 seq_st = 0;
950 u32 ba[WME_BA_BMP_SIZE >> 5];
951 int isaggr, txfail, txpending, sendbar = 0, needreset = 0;
952 int isnodegone = (an->an_flags & ATH_NODE_CLEAN);
953
954 isaggr = bf_isaggr(bf);
955 if (isaggr) {
956 if (txok) {
957 if (ATH_DS_TX_BA(ds)) {
958 /*
959 * extract starting sequence and
960 * block-ack bitmap
961 */
962 seq_st = ATH_DS_BA_SEQ(ds);
963 memcpy(ba,
964 ATH_DS_BA_BITMAP(ds),
965 WME_BA_BMP_SIZE >> 3);
966 } else {
967 memzero(ba, WME_BA_BMP_SIZE >> 3);
968
969 /*
970 * AR5416 can become deaf/mute when BA
971 * issue happens. Chip needs to be reset.
972 * But AP code may have sychronization issues
973 * when perform internal reset in this routine.
974 * Only enable reset in STA mode for now.
975 */
976 if (sc->sc_ah->ah_opmode == ATH9K_M_STA)
977 needreset = 1;
978 }
979 } else {
980 memzero(ba, WME_BA_BMP_SIZE >> 3);
981 }
982 }
983
984 INIT_LIST_HEAD(&bf_pending);
985 INIT_LIST_HEAD(&bf_head);
986
987 while (bf) {
988 txfail = txpending = 0;
989 bf_next = bf->bf_next;
990
991 if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, bf->bf_seqno))) {
992 /* transmit completion, subframe is
993 * acked by block ack */
994 } else if (!isaggr && txok) {
995 /* transmit completion */
996 } else {
997
998 if (!tid->cleanup_inprogress && !isnodegone &&
999 ds->ds_txstat.ts_flags != ATH9K_TX_SW_ABORTED) {
1000 if (bf->bf_retries < ATH_MAX_SW_RETRIES) {
1001 ath_tx_set_retry(sc, bf);
1002 txpending = 1;
1003 } else {
1004 bf->bf_state.bf_type |= BUF_XRETRY;
1005 txfail = 1;
1006 sendbar = 1;
1007 }
1008 } else {
1009 /*
1010 * cleanup in progress, just fail
1011 * the un-acked sub-frames
1012 */
1013 txfail = 1;
1014 }
1015 }
1016 /*
1017 * Remove ath_buf's of this sub-frame from aggregate queue.
1018 */
1019 if (bf_next == NULL) { /* last subframe in the aggregate */
1020 ASSERT(bf->bf_lastfrm == bf_last);
1021
1022 /*
1023 * The last descriptor of the last sub frame could be
1024 * a holding descriptor for h/w. If that's the case,
1025 * bf->bf_lastfrm won't be in the bf_q.
1026 * Make sure we handle bf_q properly here.
1027 */
1028
1029 if (!list_empty(bf_q)) {
1030 bf_lastq = list_entry(bf_q->prev,
1031 struct ath_buf, list);
1032 list_cut_position(&bf_head,
1033 bf_q, &bf_lastq->list);
1034 } else {
1035 /*
1036 * XXX: if the last subframe only has one
1037 * descriptor which is also being used as
1038 * a holding descriptor. Then the ath_buf
1039 * is not in the bf_q at all.
1040 */
1041 INIT_LIST_HEAD(&bf_head);
1042 }
1043 } else {
1044 ASSERT(!list_empty(bf_q));
1045 list_cut_position(&bf_head,
1046 bf_q, &bf->bf_lastfrm->list);
1047 }
1048
1049 if (!txpending) {
1050 /*
1051 * complete the acked-ones/xretried ones; update
1052 * block-ack window
1053 */
1054 spin_lock_bh(&txq->axq_lock);
1055 ath_tx_update_baw(sc, tid, bf->bf_seqno);
1056 spin_unlock_bh(&txq->axq_lock);
1057
1058 /* complete this sub-frame */
1059 ath_tx_complete_buf(sc, bf, &bf_head, !txfail, sendbar);
1060 } else {
1061 /*
1062 * retry the un-acked ones
1063 */
1064 /*
1065 * XXX: if the last descriptor is holding descriptor,
1066 * in order to requeue the frame to software queue, we
1067 * need to allocate a new descriptor and
1068 * copy the content of holding descriptor to it.
1069 */
1070 if (bf->bf_next == NULL &&
1071 bf_last->bf_status & ATH_BUFSTATUS_STALE) {
1072 struct ath_buf *tbf;
1073
1074 /* allocate new descriptor */
1075 spin_lock_bh(&sc->sc_txbuflock);
1076 ASSERT(!list_empty((&sc->sc_txbuf)));
1077 tbf = list_first_entry(&sc->sc_txbuf,
1078 struct ath_buf, list);
1079 list_del(&tbf->list);
1080 spin_unlock_bh(&sc->sc_txbuflock);
1081
1082 ATH_TXBUF_RESET(tbf);
1083
1084 /* copy descriptor content */
1085 tbf->bf_mpdu = bf_last->bf_mpdu;
1086 tbf->bf_node = bf_last->bf_node;
1087 tbf->bf_buf_addr = bf_last->bf_buf_addr;
1088 *(tbf->bf_desc) = *(bf_last->bf_desc);
1089
1090 /* link it to the frame */
1091 if (bf_lastq) {
1092 bf_lastq->bf_desc->ds_link =
1093 tbf->bf_daddr;
1094 bf->bf_lastfrm = tbf;
1095 ath9k_hw_cleartxdesc(sc->sc_ah,
1096 bf->bf_lastfrm->bf_desc);
1097 } else {
1098 tbf->bf_state = bf_last->bf_state;
1099 tbf->bf_lastfrm = tbf;
1100 ath9k_hw_cleartxdesc(sc->sc_ah,
1101 tbf->bf_lastfrm->bf_desc);
1102
1103 /* copy the DMA context */
1104 tbf->bf_dmacontext =
1105 bf_last->bf_dmacontext;
1106 }
1107 list_add_tail(&tbf->list, &bf_head);
1108 } else {
1109 /*
1110 * Clear descriptor status words for
1111 * software retry
1112 */
1113 ath9k_hw_cleartxdesc(sc->sc_ah,
1114 bf->bf_lastfrm->bf_desc);
1115 }
1116
1117 /*
1118 * Put this buffer to the temporary pending
1119 * queue to retain ordering
1120 */
1121 list_splice_tail_init(&bf_head, &bf_pending);
1122 }
1123
1124 bf = bf_next;
1125 }
1126
1127 /*
1128 * node is already gone. no more assocication
1129 * with the node. the node might have been freed
1130 * any node acces can result in panic.note tid
1131 * is part of the node.
1132 */
1133 if (isnodegone)
1134 return;
1135
1136 if (tid->cleanup_inprogress) {
1137 /* check to see if we're done with cleaning the h/w queue */
1138 spin_lock_bh(&txq->axq_lock);
1139
1140 if (tid->baw_head == tid->baw_tail) {
1141 tid->addba_exchangecomplete = 0;
1142 tid->addba_exchangeattempts = 0;
1143 spin_unlock_bh(&txq->axq_lock);
1144
1145 tid->cleanup_inprogress = false;
1146
1147 /* send buffered frames as singles */
1148 ath_tx_flush_tid(sc, tid);
1149 } else
1150 spin_unlock_bh(&txq->axq_lock);
1151
1152 return;
1153 }
1154
1155 /*
1156 * prepend un-acked frames to the beginning of the pending frame queue
1157 */
1158 if (!list_empty(&bf_pending)) {
1159 spin_lock_bh(&txq->axq_lock);
1160 /* Note: we _prepend_, we _do_not_ at to
1161 * the end of the queue ! */
1162 list_splice(&bf_pending, &tid->buf_q);
1163 ath_tx_queue_tid(txq, tid);
1164 spin_unlock_bh(&txq->axq_lock);
1165 }
1166
1167 if (needreset)
1168 ath_reset(sc, false);
1169
1170 return;
1171 }
1172
1173 /* Process completed xmit descriptors from the specified queue */
1174
1175 static int ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
1176 {
1177 struct ath_hal *ah = sc->sc_ah;
1178 struct ath_buf *bf, *lastbf, *bf_held = NULL;
1179 struct list_head bf_head;
1180 struct ath_desc *ds, *tmp_ds;
1181 struct sk_buff *skb;
1182 struct ieee80211_tx_info *tx_info;
1183 struct ath_tx_info_priv *tx_info_priv;
1184 int nacked, txok, nbad = 0, isrifs = 0;
1185 int status;
1186
1187 DPRINTF(sc, ATH_DBG_QUEUE,
1188 "%s: tx queue %d (%x), link %p\n", __func__,
1189 txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum),
1190 txq->axq_link);
1191
1192 nacked = 0;
1193 for (;;) {
1194 spin_lock_bh(&txq->axq_lock);
1195 txq->axq_intrcnt = 0; /* reset periodic desc intr count */
1196 if (list_empty(&txq->axq_q)) {
1197 txq->axq_link = NULL;
1198 txq->axq_linkbuf = NULL;
1199 spin_unlock_bh(&txq->axq_lock);
1200 break;
1201 }
1202 bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
1203
1204 /*
1205 * There is a race condition that a BH gets scheduled
1206 * after sw writes TxE and before hw re-load the last
1207 * descriptor to get the newly chained one.
1208 * Software must keep the last DONE descriptor as a
1209 * holding descriptor - software does so by marking
1210 * it with the STALE flag.
1211 */
1212 bf_held = NULL;
1213 if (bf->bf_status & ATH_BUFSTATUS_STALE) {
1214 bf_held = bf;
1215 if (list_is_last(&bf_held->list, &txq->axq_q)) {
1216 /* FIXME:
1217 * The holding descriptor is the last
1218 * descriptor in queue. It's safe to remove
1219 * the last holding descriptor in BH context.
1220 */
1221 spin_unlock_bh(&txq->axq_lock);
1222 break;
1223 } else {
1224 /* Lets work with the next buffer now */
1225 bf = list_entry(bf_held->list.next,
1226 struct ath_buf, list);
1227 }
1228 }
1229
1230 lastbf = bf->bf_lastbf;
1231 ds = lastbf->bf_desc; /* NB: last decriptor */
1232
1233 status = ath9k_hw_txprocdesc(ah, ds);
1234 if (status == -EINPROGRESS) {
1235 spin_unlock_bh(&txq->axq_lock);
1236 break;
1237 }
1238 if (bf->bf_desc == txq->axq_lastdsWithCTS)
1239 txq->axq_lastdsWithCTS = NULL;
1240 if (ds == txq->axq_gatingds)
1241 txq->axq_gatingds = NULL;
1242
1243 /*
1244 * Remove ath_buf's of the same transmit unit from txq,
1245 * however leave the last descriptor back as the holding
1246 * descriptor for hw.
1247 */
1248 lastbf->bf_status |= ATH_BUFSTATUS_STALE;
1249 INIT_LIST_HEAD(&bf_head);
1250
1251 if (!list_is_singular(&lastbf->list))
1252 list_cut_position(&bf_head,
1253 &txq->axq_q, lastbf->list.prev);
1254
1255 txq->axq_depth--;
1256
1257 if (bf_isaggr(bf))
1258 txq->axq_aggr_depth--;
1259
1260 txok = (ds->ds_txstat.ts_status == 0);
1261
1262 spin_unlock_bh(&txq->axq_lock);
1263
1264 if (bf_held) {
1265 list_del(&bf_held->list);
1266 spin_lock_bh(&sc->sc_txbuflock);
1267 list_add_tail(&bf_held->list, &sc->sc_txbuf);
1268 spin_unlock_bh(&sc->sc_txbuflock);
1269 }
1270
1271 if (!bf_isampdu(bf)) {
1272 /*
1273 * This frame is sent out as a single frame.
1274 * Use hardware retry status for this frame.
1275 */
1276 bf->bf_retries = ds->ds_txstat.ts_longretry;
1277 if (ds->ds_txstat.ts_status & ATH9K_TXERR_XRETRY)
1278 bf->bf_state.bf_type |= BUF_XRETRY;
1279 nbad = 0;
1280 } else {
1281 nbad = ath_tx_num_badfrms(sc, bf, txok);
1282 }
1283 skb = bf->bf_mpdu;
1284 tx_info = IEEE80211_SKB_CB(skb);
1285 tx_info_priv = (struct ath_tx_info_priv *)
1286 tx_info->driver_data[0];
1287 if (ds->ds_txstat.ts_status & ATH9K_TXERR_FILT)
1288 tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
1289 if ((ds->ds_txstat.ts_status & ATH9K_TXERR_FILT) == 0 &&
1290 (bf->bf_flags & ATH9K_TXDESC_NOACK) == 0) {
1291 if (ds->ds_txstat.ts_status == 0)
1292 nacked++;
1293
1294 if (bf_isdata(bf)) {
1295 if (isrifs)
1296 tmp_ds = bf->bf_rifslast->bf_desc;
1297 else
1298 tmp_ds = ds;
1299 memcpy(&tx_info_priv->tx,
1300 &tmp_ds->ds_txstat,
1301 sizeof(tx_info_priv->tx));
1302 tx_info_priv->n_frames = bf->bf_nframes;
1303 tx_info_priv->n_bad_frames = nbad;
1304 }
1305 }
1306
1307 /*
1308 * Complete this transmit unit
1309 */
1310 if (bf_isampdu(bf))
1311 ath_tx_complete_aggr_rifs(sc, txq, bf, &bf_head, txok);
1312 else
1313 ath_tx_complete_buf(sc, bf, &bf_head, txok, 0);
1314
1315 /* Wake up mac80211 queue */
1316
1317 spin_lock_bh(&txq->axq_lock);
1318 if (txq->stopped && ath_txq_depth(sc, txq->axq_qnum) <=
1319 (ATH_TXBUF - 20)) {
1320 int qnum;
1321 qnum = ath_get_mac80211_qnum(txq->axq_qnum, sc);
1322 if (qnum != -1) {
1323 ieee80211_wake_queue(sc->hw, qnum);
1324 txq->stopped = 0;
1325 }
1326
1327 }
1328
1329 /*
1330 * schedule any pending packets if aggregation is enabled
1331 */
1332 if (sc->sc_flags & SC_OP_TXAGGR)
1333 ath_txq_schedule(sc, txq);
1334 spin_unlock_bh(&txq->axq_lock);
1335 }
1336 return nacked;
1337 }
1338
1339 static void ath_tx_stopdma(struct ath_softc *sc, struct ath_txq *txq)
1340 {
1341 struct ath_hal *ah = sc->sc_ah;
1342
1343 (void) ath9k_hw_stoptxdma(ah, txq->axq_qnum);
1344 DPRINTF(sc, ATH_DBG_XMIT, "%s: tx queue [%u] %x, link %p\n",
1345 __func__, txq->axq_qnum,
1346 ath9k_hw_gettxbuf(ah, txq->axq_qnum), txq->axq_link);
1347 }
1348
1349 /* Drain only the data queues */
1350
1351 static void ath_drain_txdataq(struct ath_softc *sc, bool retry_tx)
1352 {
1353 struct ath_hal *ah = sc->sc_ah;
1354 int i;
1355 int npend = 0;
1356
1357 /* XXX return value */
1358 if (!(sc->sc_flags & SC_OP_INVALID)) {
1359 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1360 if (ATH_TXQ_SETUP(sc, i)) {
1361 ath_tx_stopdma(sc, &sc->sc_txq[i]);
1362
1363 /* The TxDMA may not really be stopped.
1364 * Double check the hal tx pending count */
1365 npend += ath9k_hw_numtxpending(ah,
1366 sc->sc_txq[i].axq_qnum);
1367 }
1368 }
1369 }
1370
1371 if (npend) {
1372 int status;
1373
1374 /* TxDMA not stopped, reset the hal */
1375 DPRINTF(sc, ATH_DBG_XMIT,
1376 "%s: Unable to stop TxDMA. Reset HAL!\n", __func__);
1377
1378 spin_lock_bh(&sc->sc_resetlock);
1379 if (!ath9k_hw_reset(ah,
1380 sc->sc_ah->ah_curchan,
1381 sc->sc_ht_info.tx_chan_width,
1382 sc->sc_tx_chainmask, sc->sc_rx_chainmask,
1383 sc->sc_ht_extprotspacing, true, &status)) {
1384
1385 DPRINTF(sc, ATH_DBG_FATAL,
1386 "%s: unable to reset hardware; hal status %u\n",
1387 __func__,
1388 status);
1389 }
1390 spin_unlock_bh(&sc->sc_resetlock);
1391 }
1392
1393 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1394 if (ATH_TXQ_SETUP(sc, i))
1395 ath_tx_draintxq(sc, &sc->sc_txq[i], retry_tx);
1396 }
1397 }
1398
1399 /* Add a sub-frame to block ack window */
1400
1401 static void ath_tx_addto_baw(struct ath_softc *sc,
1402 struct ath_atx_tid *tid,
1403 struct ath_buf *bf)
1404 {
1405 int index, cindex;
1406
1407 if (bf_isretried(bf))
1408 return;
1409
1410 index = ATH_BA_INDEX(tid->seq_start, bf->bf_seqno);
1411 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
1412
1413 ASSERT(tid->tx_buf[cindex] == NULL);
1414 tid->tx_buf[cindex] = bf;
1415
1416 if (index >= ((tid->baw_tail - tid->baw_head) &
1417 (ATH_TID_MAX_BUFS - 1))) {
1418 tid->baw_tail = cindex;
1419 INCR(tid->baw_tail, ATH_TID_MAX_BUFS);
1420 }
1421 }
1422
1423 /*
1424 * Function to send an A-MPDU
1425 * NB: must be called with txq lock held
1426 */
1427
1428 static int ath_tx_send_ampdu(struct ath_softc *sc,
1429 struct ath_txq *txq,
1430 struct ath_atx_tid *tid,
1431 struct list_head *bf_head,
1432 struct ath_tx_control *txctl)
1433 {
1434 struct ath_buf *bf;
1435 struct sk_buff *skb;
1436 struct ieee80211_tx_info *tx_info;
1437 struct ath_tx_info_priv *tx_info_priv;
1438
1439 BUG_ON(list_empty(bf_head));
1440
1441 bf = list_first_entry(bf_head, struct ath_buf, list);
1442 bf->bf_state.bf_type |= BUF_AMPDU;
1443 bf->bf_seqno = txctl->seqno; /* save seqno and tidno in buffer */
1444 bf->bf_tidno = txctl->tidno;
1445
1446 /*
1447 * Do not queue to h/w when any of the following conditions is true:
1448 * - there are pending frames in software queue
1449 * - the TID is currently paused for ADDBA/BAR request
1450 * - seqno is not within block-ack window
1451 * - h/w queue depth exceeds low water mark
1452 */
1453 if (!list_empty(&tid->buf_q) || tid->paused ||
1454 !BAW_WITHIN(tid->seq_start, tid->baw_size, bf->bf_seqno) ||
1455 txq->axq_depth >= ATH_AGGR_MIN_QDEPTH) {
1456 /*
1457 * Add this frame to software queue for scheduling later
1458 * for aggregation.
1459 */
1460 list_splice_tail_init(bf_head, &tid->buf_q);
1461 ath_tx_queue_tid(txq, tid);
1462 return 0;
1463 }
1464
1465 skb = (struct sk_buff *)bf->bf_mpdu;
1466 tx_info = IEEE80211_SKB_CB(skb);
1467 tx_info_priv = (struct ath_tx_info_priv *)tx_info->driver_data[0];
1468 memcpy(bf->bf_rcs, tx_info_priv->rcs, 4 * sizeof(tx_info_priv->rcs[0]));
1469
1470 /* Add sub-frame to BAW */
1471 ath_tx_addto_baw(sc, tid, bf);
1472
1473 /* Queue to h/w without aggregation */
1474 bf->bf_nframes = 1;
1475 bf->bf_lastbf = bf->bf_lastfrm; /* one single frame */
1476 ath_buf_set_rate(sc, bf);
1477 ath_tx_txqaddbuf(sc, txq, bf_head);
1478 return 0;
1479 }
1480
1481 /*
1482 * looks up the rate
1483 * returns aggr limit based on lowest of the rates
1484 */
1485
1486 static u32 ath_lookup_rate(struct ath_softc *sc,
1487 struct ath_buf *bf)
1488 {
1489 const struct ath9k_rate_table *rt = sc->sc_currates;
1490 struct sk_buff *skb;
1491 struct ieee80211_tx_info *tx_info;
1492 struct ath_tx_info_priv *tx_info_priv;
1493 u32 max_4ms_framelen, frame_length;
1494 u16 aggr_limit, legacy = 0, maxampdu;
1495 int i;
1496
1497
1498 skb = (struct sk_buff *)bf->bf_mpdu;
1499 tx_info = IEEE80211_SKB_CB(skb);
1500 tx_info_priv = (struct ath_tx_info_priv *)
1501 tx_info->driver_data[0];
1502 memcpy(bf->bf_rcs,
1503 tx_info_priv->rcs, 4 * sizeof(tx_info_priv->rcs[0]));
1504
1505 /*
1506 * Find the lowest frame length among the rate series that will have a
1507 * 4ms transmit duration.
1508 * TODO - TXOP limit needs to be considered.
1509 */
1510 max_4ms_framelen = ATH_AMPDU_LIMIT_MAX;
1511
1512 for (i = 0; i < 4; i++) {
1513 if (bf->bf_rcs[i].tries) {
1514 frame_length = bf->bf_rcs[i].max_4ms_framelen;
1515
1516 if (rt->info[bf->bf_rcs[i].rix].phy != PHY_HT) {
1517 legacy = 1;
1518 break;
1519 }
1520
1521 max_4ms_framelen = min(max_4ms_framelen, frame_length);
1522 }
1523 }
1524
1525 /*
1526 * limit aggregate size by the minimum rate if rate selected is
1527 * not a probe rate, if rate selected is a probe rate then
1528 * avoid aggregation of this packet.
1529 */
1530 if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy)
1531 return 0;
1532
1533 aggr_limit = min(max_4ms_framelen,
1534 (u32)ATH_AMPDU_LIMIT_DEFAULT);
1535
1536 /*
1537 * h/w can accept aggregates upto 16 bit lengths (65535).
1538 * The IE, however can hold upto 65536, which shows up here
1539 * as zero. Ignore 65536 since we are constrained by hw.
1540 */
1541 maxampdu = sc->sc_ht_info.maxampdu;
1542 if (maxampdu)
1543 aggr_limit = min(aggr_limit, maxampdu);
1544
1545 return aggr_limit;
1546 }
1547
1548 /*
1549 * returns the number of delimiters to be added to
1550 * meet the minimum required mpdudensity.
1551 * caller should make sure that the rate is HT rate .
1552 */
1553
1554 static int ath_compute_num_delims(struct ath_softc *sc,
1555 struct ath_buf *bf,
1556 u16 frmlen)
1557 {
1558 const struct ath9k_rate_table *rt = sc->sc_currates;
1559 u32 nsymbits, nsymbols, mpdudensity;
1560 u16 minlen;
1561 u8 rc, flags, rix;
1562 int width, half_gi, ndelim, mindelim;
1563
1564 /* Select standard number of delimiters based on frame length alone */
1565 ndelim = ATH_AGGR_GET_NDELIM(frmlen);
1566
1567 /*
1568 * If encryption enabled, hardware requires some more padding between
1569 * subframes.
1570 * TODO - this could be improved to be dependent on the rate.
1571 * The hardware can keep up at lower rates, but not higher rates
1572 */
1573 if (bf->bf_keytype != ATH9K_KEY_TYPE_CLEAR)
1574 ndelim += ATH_AGGR_ENCRYPTDELIM;
1575
1576 /*
1577 * Convert desired mpdu density from microeconds to bytes based
1578 * on highest rate in rate series (i.e. first rate) to determine
1579 * required minimum length for subframe. Take into account
1580 * whether high rate is 20 or 40Mhz and half or full GI.
1581 */
1582 mpdudensity = sc->sc_ht_info.mpdudensity;
1583
1584 /*
1585 * If there is no mpdu density restriction, no further calculation
1586 * is needed.
1587 */
1588 if (mpdudensity == 0)
1589 return ndelim;
1590
1591 rix = bf->bf_rcs[0].rix;
1592 flags = bf->bf_rcs[0].flags;
1593 rc = rt->info[rix].rateCode;
1594 width = (flags & ATH_RC_CW40_FLAG) ? 1 : 0;
1595 half_gi = (flags & ATH_RC_SGI_FLAG) ? 1 : 0;
1596
1597 if (half_gi)
1598 nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(mpdudensity);
1599 else
1600 nsymbols = NUM_SYMBOLS_PER_USEC(mpdudensity);
1601
1602 if (nsymbols == 0)
1603 nsymbols = 1;
1604
1605 nsymbits = bits_per_symbol[HT_RC_2_MCS(rc)][width];
1606 minlen = (nsymbols * nsymbits) / BITS_PER_BYTE;
1607
1608 /* Is frame shorter than required minimum length? */
1609 if (frmlen < minlen) {
1610 /* Get the minimum number of delimiters required. */
1611 mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ;
1612 ndelim = max(mindelim, ndelim);
1613 }
1614
1615 return ndelim;
1616 }
1617
1618 /*
1619 * For aggregation from software buffer queue.
1620 * NB: must be called with txq lock held
1621 */
1622
1623 static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc,
1624 struct ath_atx_tid *tid,
1625 struct list_head *bf_q,
1626 struct ath_buf **bf_last,
1627 struct aggr_rifs_param *param,
1628 int *prev_frames)
1629 {
1630 #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
1631 struct ath_buf *bf, *tbf, *bf_first, *bf_prev = NULL;
1632 struct list_head bf_head;
1633 int rl = 0, nframes = 0, ndelim;
1634 u16 aggr_limit = 0, al = 0, bpad = 0,
1635 al_delta, h_baw = tid->baw_size / 2;
1636 enum ATH_AGGR_STATUS status = ATH_AGGR_DONE;
1637 int prev_al = 0, is_ds_rate = 0;
1638 INIT_LIST_HEAD(&bf_head);
1639
1640 BUG_ON(list_empty(&tid->buf_q));
1641
1642 bf_first = list_first_entry(&tid->buf_q, struct ath_buf, list);
1643
1644 do {
1645 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
1646
1647 /*
1648 * do not step over block-ack window
1649 */
1650 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, bf->bf_seqno)) {
1651 status = ATH_AGGR_BAW_CLOSED;
1652 break;
1653 }
1654
1655 if (!rl) {
1656 aggr_limit = ath_lookup_rate(sc, bf);
1657 rl = 1;
1658 /*
1659 * Is rate dual stream
1660 */
1661 is_ds_rate =
1662 (bf->bf_rcs[0].flags & ATH_RC_DS_FLAG) ? 1 : 0;
1663 }
1664
1665 /*
1666 * do not exceed aggregation limit
1667 */
1668 al_delta = ATH_AGGR_DELIM_SZ + bf->bf_frmlen;
1669
1670 if (nframes && (aggr_limit <
1671 (al + bpad + al_delta + prev_al))) {
1672 status = ATH_AGGR_LIMITED;
1673 break;
1674 }
1675
1676 /*
1677 * do not exceed subframe limit
1678 */
1679 if ((nframes + *prev_frames) >=
1680 min((int)h_baw, ATH_AMPDU_SUBFRAME_DEFAULT)) {
1681 status = ATH_AGGR_LIMITED;
1682 break;
1683 }
1684
1685 /*
1686 * add padding for previous frame to aggregation length
1687 */
1688 al += bpad + al_delta;
1689
1690 /*
1691 * Get the delimiters needed to meet the MPDU
1692 * density for this node.
1693 */
1694 ndelim = ath_compute_num_delims(sc, bf_first, bf->bf_frmlen);
1695
1696 bpad = PADBYTES(al_delta) + (ndelim << 2);
1697
1698 bf->bf_next = NULL;
1699 bf->bf_lastfrm->bf_desc->ds_link = 0;
1700
1701 /*
1702 * this packet is part of an aggregate
1703 * - remove all descriptors belonging to this frame from
1704 * software queue
1705 * - add it to block ack window
1706 * - set up descriptors for aggregation
1707 */
1708 list_cut_position(&bf_head, &tid->buf_q, &bf->bf_lastfrm->list);
1709 ath_tx_addto_baw(sc, tid, bf);
1710
1711 list_for_each_entry(tbf, &bf_head, list) {
1712 ath9k_hw_set11n_aggr_middle(sc->sc_ah,
1713 tbf->bf_desc, ndelim);
1714 }
1715
1716 /*
1717 * link buffers of this frame to the aggregate
1718 */
1719 list_splice_tail_init(&bf_head, bf_q);
1720 nframes++;
1721
1722 if (bf_prev) {
1723 bf_prev->bf_next = bf;
1724 bf_prev->bf_lastfrm->bf_desc->ds_link = bf->bf_daddr;
1725 }
1726 bf_prev = bf;
1727
1728 #ifdef AGGR_NOSHORT
1729 /*
1730 * terminate aggregation on a small packet boundary
1731 */
1732 if (bf->bf_frmlen < ATH_AGGR_MINPLEN) {
1733 status = ATH_AGGR_SHORTPKT;
1734 break;
1735 }
1736 #endif
1737 } while (!list_empty(&tid->buf_q));
1738
1739 bf_first->bf_al = al;
1740 bf_first->bf_nframes = nframes;
1741 *bf_last = bf_prev;
1742 return status;
1743 #undef PADBYTES
1744 }
1745
1746 /*
1747 * process pending frames possibly doing a-mpdu aggregation
1748 * NB: must be called with txq lock held
1749 */
1750
1751 static void ath_tx_sched_aggr(struct ath_softc *sc,
1752 struct ath_txq *txq, struct ath_atx_tid *tid)
1753 {
1754 struct ath_buf *bf, *tbf, *bf_last, *bf_lastaggr = NULL;
1755 enum ATH_AGGR_STATUS status;
1756 struct list_head bf_q;
1757 struct aggr_rifs_param param = {0, 0, 0, 0, NULL};
1758 int prev_frames = 0;
1759
1760 do {
1761 if (list_empty(&tid->buf_q))
1762 return;
1763
1764 INIT_LIST_HEAD(&bf_q);
1765
1766 status = ath_tx_form_aggr(sc, tid, &bf_q, &bf_lastaggr, &param,
1767 &prev_frames);
1768
1769 /*
1770 * no frames picked up to be aggregated; block-ack
1771 * window is not open
1772 */
1773 if (list_empty(&bf_q))
1774 break;
1775
1776 bf = list_first_entry(&bf_q, struct ath_buf, list);
1777 bf_last = list_entry(bf_q.prev, struct ath_buf, list);
1778 bf->bf_lastbf = bf_last;
1779
1780 /*
1781 * if only one frame, send as non-aggregate
1782 */
1783 if (bf->bf_nframes == 1) {
1784 ASSERT(bf->bf_lastfrm == bf_last);
1785
1786 bf->bf_state.bf_type &= ~BUF_AGGR;
1787 /*
1788 * clear aggr bits for every descriptor
1789 * XXX TODO: is there a way to optimize it?
1790 */
1791 list_for_each_entry(tbf, &bf_q, list) {
1792 ath9k_hw_clr11n_aggr(sc->sc_ah, tbf->bf_desc);
1793 }
1794
1795 ath_buf_set_rate(sc, bf);
1796 ath_tx_txqaddbuf(sc, txq, &bf_q);
1797 continue;
1798 }
1799
1800 /*
1801 * setup first desc with rate and aggr info
1802 */
1803 bf->bf_state.bf_type |= BUF_AGGR;
1804 ath_buf_set_rate(sc, bf);
1805 ath9k_hw_set11n_aggr_first(sc->sc_ah, bf->bf_desc, bf->bf_al);
1806
1807 /*
1808 * anchor last frame of aggregate correctly
1809 */
1810 ASSERT(bf_lastaggr);
1811 ASSERT(bf_lastaggr->bf_lastfrm == bf_last);
1812 tbf = bf_lastaggr;
1813 ath9k_hw_set11n_aggr_last(sc->sc_ah, tbf->bf_desc);
1814
1815 /* XXX: We don't enter into this loop, consider removing this */
1816 while (!list_empty(&bf_q) && !list_is_last(&tbf->list, &bf_q)) {
1817 tbf = list_entry(tbf->list.next, struct ath_buf, list);
1818 ath9k_hw_set11n_aggr_last(sc->sc_ah, tbf->bf_desc);
1819 }
1820
1821 txq->axq_aggr_depth++;
1822
1823 /*
1824 * Normal aggregate, queue to hardware
1825 */
1826 ath_tx_txqaddbuf(sc, txq, &bf_q);
1827
1828 } while (txq->axq_depth < ATH_AGGR_MIN_QDEPTH &&
1829 status != ATH_AGGR_BAW_CLOSED);
1830 }
1831
1832 /* Called with txq lock held */
1833
1834 static void ath_tid_drain(struct ath_softc *sc,
1835 struct ath_txq *txq,
1836 struct ath_atx_tid *tid,
1837 bool bh_flag)
1838 {
1839 struct ath_buf *bf;
1840 struct list_head bf_head;
1841 INIT_LIST_HEAD(&bf_head);
1842
1843 for (;;) {
1844 if (list_empty(&tid->buf_q))
1845 break;
1846 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
1847
1848 list_cut_position(&bf_head, &tid->buf_q, &bf->bf_lastfrm->list);
1849
1850 /* update baw for software retried frame */
1851 if (bf_isretried(bf))
1852 ath_tx_update_baw(sc, tid, bf->bf_seqno);
1853
1854 /*
1855 * do not indicate packets while holding txq spinlock.
1856 * unlock is intentional here
1857 */
1858 if (likely(bh_flag))
1859 spin_unlock_bh(&txq->axq_lock);
1860 else
1861 spin_unlock(&txq->axq_lock);
1862
1863 /* complete this sub-frame */
1864 ath_tx_complete_buf(sc, bf, &bf_head, 0, 0);
1865
1866 if (likely(bh_flag))
1867 spin_lock_bh(&txq->axq_lock);
1868 else
1869 spin_lock(&txq->axq_lock);
1870 }
1871
1872 /*
1873 * TODO: For frame(s) that are in the retry state, we will reuse the
1874 * sequence number(s) without setting the retry bit. The
1875 * alternative is to give up on these and BAR the receiver's window
1876 * forward.
1877 */
1878 tid->seq_next = tid->seq_start;
1879 tid->baw_tail = tid->baw_head;
1880 }
1881
1882 /*
1883 * Drain all pending buffers
1884 * NB: must be called with txq lock held
1885 */
1886
1887 static void ath_txq_drain_pending_buffers(struct ath_softc *sc,
1888 struct ath_txq *txq,
1889 bool bh_flag)
1890 {
1891 struct ath_atx_ac *ac, *ac_tmp;
1892 struct ath_atx_tid *tid, *tid_tmp;
1893
1894 list_for_each_entry_safe(ac, ac_tmp, &txq->axq_acq, list) {
1895 list_del(&ac->list);
1896 ac->sched = false;
1897 list_for_each_entry_safe(tid, tid_tmp, &ac->tid_q, list) {
1898 list_del(&tid->list);
1899 tid->sched = false;
1900 ath_tid_drain(sc, txq, tid, bh_flag);
1901 }
1902 }
1903 }
1904
1905 static int ath_tx_start_dma(struct ath_softc *sc,
1906 struct sk_buff *skb,
1907 struct scatterlist *sg,
1908 u32 n_sg,
1909 struct ath_tx_control *txctl)
1910 {
1911 struct ath_node *an = txctl->an;
1912 struct ath_buf *bf = NULL;
1913 struct list_head bf_head;
1914 struct ath_desc *ds;
1915 struct ath_hal *ah = sc->sc_ah;
1916 struct ath_txq *txq;
1917 struct ath_tx_info_priv *tx_info_priv;
1918 struct ath_rc_series *rcs;
1919 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1920 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1921 __le16 fc = hdr->frame_control;
1922
1923 if (unlikely(txctl->flags & ATH9K_TXDESC_CAB))
1924 txq = sc->sc_cabq;
1925 else
1926 txq = &sc->sc_txq[txctl->qnum];
1927
1928 /* For each sglist entry, allocate an ath_buf for DMA */
1929 INIT_LIST_HEAD(&bf_head);
1930 spin_lock_bh(&sc->sc_txbuflock);
1931 if (unlikely(list_empty(&sc->sc_txbuf))) {
1932 spin_unlock_bh(&sc->sc_txbuflock);
1933 return -ENOMEM;
1934 }
1935
1936 bf = list_first_entry(&sc->sc_txbuf, struct ath_buf, list);
1937 list_del(&bf->list);
1938 spin_unlock_bh(&sc->sc_txbuflock);
1939
1940 list_add_tail(&bf->list, &bf_head);
1941
1942 /* set up this buffer */
1943 ATH_TXBUF_RESET(bf);
1944 bf->bf_frmlen = txctl->frmlen;
1945
1946 ieee80211_is_data(fc) ?
1947 (bf->bf_state.bf_type |= BUF_DATA) :
1948 (bf->bf_state.bf_type &= ~BUF_DATA);
1949 ieee80211_is_back_req(fc) ?
1950 (bf->bf_state.bf_type |= BUF_BAR) :
1951 (bf->bf_state.bf_type &= ~BUF_BAR);
1952 ieee80211_is_pspoll(fc) ?
1953 (bf->bf_state.bf_type |= BUF_PSPOLL) :
1954 (bf->bf_state.bf_type &= ~BUF_PSPOLL);
1955 (sc->sc_flags & SC_OP_PREAMBLE_SHORT) ?
1956 (bf->bf_state.bf_type |= BUF_SHORT_PREAMBLE) :
1957 (bf->bf_state.bf_type &= ~BUF_SHORT_PREAMBLE);
1958
1959 bf->bf_flags = txctl->flags;
1960 bf->bf_keytype = txctl->keytype;
1961 tx_info_priv = (struct ath_tx_info_priv *)tx_info->driver_data[0];
1962 rcs = tx_info_priv->rcs;
1963 bf->bf_rcs[0] = rcs[0];
1964 bf->bf_rcs[1] = rcs[1];
1965 bf->bf_rcs[2] = rcs[2];
1966 bf->bf_rcs[3] = rcs[3];
1967 bf->bf_node = an;
1968 bf->bf_mpdu = skb;
1969 bf->bf_buf_addr = sg_dma_address(sg);
1970
1971 /* setup descriptor */
1972 ds = bf->bf_desc;
1973 ds->ds_link = 0;
1974 ds->ds_data = bf->bf_buf_addr;
1975
1976 /*
1977 * Save the DMA context in the first ath_buf
1978 */
1979 bf->bf_dmacontext = txctl->dmacontext;
1980
1981 /*
1982 * Formulate first tx descriptor with tx controls.
1983 */
1984 ath9k_hw_set11n_txdesc(ah,
1985 ds,
1986 bf->bf_frmlen, /* frame length */
1987 txctl->atype, /* Atheros packet type */
1988 min(txctl->txpower, (u16)60), /* txpower */
1989 txctl->keyix, /* key cache index */
1990 txctl->keytype, /* key type */
1991 txctl->flags); /* flags */
1992 ath9k_hw_filltxdesc(ah,
1993 ds,
1994 sg_dma_len(sg), /* segment length */
1995 true, /* first segment */
1996 (n_sg == 1) ? true : false, /* last segment */
1997 ds); /* first descriptor */
1998
1999 bf->bf_lastfrm = bf;
2000 (txctl->ht) ?
2001 (bf->bf_state.bf_type |= BUF_HT) :
2002 (bf->bf_state.bf_type &= ~BUF_HT);
2003
2004 spin_lock_bh(&txq->axq_lock);
2005
2006 if (txctl->ht && (sc->sc_flags & SC_OP_TXAGGR)) {
2007 struct ath_atx_tid *tid = ATH_AN_2_TID(an, txctl->tidno);
2008 if (ath_aggr_query(sc, an, txctl->tidno)) {
2009 /*
2010 * Try aggregation if it's a unicast data frame
2011 * and the destination is HT capable.
2012 */
2013 ath_tx_send_ampdu(sc, txq, tid, &bf_head, txctl);
2014 } else {
2015 /*
2016 * Send this frame as regular when ADDBA exchange
2017 * is neither complete nor pending.
2018 */
2019 ath_tx_send_normal(sc, txq, tid, &bf_head);
2020 }
2021 } else {
2022 bf->bf_lastbf = bf;
2023 bf->bf_nframes = 1;
2024 ath_buf_set_rate(sc, bf);
2025
2026 if (ieee80211_is_back_req(fc)) {
2027 /* This is required for resuming tid
2028 * during BAR completion */
2029 bf->bf_tidno = txctl->tidno;
2030 }
2031
2032 ath_tx_txqaddbuf(sc, txq, &bf_head);
2033 }
2034 spin_unlock_bh(&txq->axq_lock);
2035 return 0;
2036 }
2037
2038 static void xmit_map_sg(struct ath_softc *sc,
2039 struct sk_buff *skb,
2040 struct ath_tx_control *txctl)
2041 {
2042 struct ath_xmit_status tx_status;
2043 struct ath_atx_tid *tid;
2044 struct scatterlist sg;
2045
2046 txctl->dmacontext = pci_map_single(sc->pdev, skb->data,
2047 skb->len, PCI_DMA_TODEVICE);
2048
2049 /* setup S/G list */
2050 memset(&sg, 0, sizeof(struct scatterlist));
2051 sg_dma_address(&sg) = txctl->dmacontext;
2052 sg_dma_len(&sg) = skb->len;
2053
2054 if (ath_tx_start_dma(sc, skb, &sg, 1, txctl) != 0) {
2055 /*
2056 * We have to do drop frame here.
2057 */
2058 pci_unmap_single(sc->pdev, txctl->dmacontext,
2059 skb->len, PCI_DMA_TODEVICE);
2060
2061 tx_status.retries = 0;
2062 tx_status.flags = ATH_TX_ERROR;
2063
2064 if (txctl->ht && (sc->sc_flags & SC_OP_TXAGGR)) {
2065 /* Reclaim the seqno. */
2066 tid = ATH_AN_2_TID((struct ath_node *)
2067 txctl->an, txctl->tidno);
2068 DECR(tid->seq_next, IEEE80211_SEQ_MAX);
2069 }
2070 ath_tx_complete(sc, skb, &tx_status, txctl->an);
2071 }
2072 }
2073
2074 /* Initialize TX queue and h/w */
2075
2076 int ath_tx_init(struct ath_softc *sc, int nbufs)
2077 {
2078 int error = 0;
2079
2080 do {
2081 spin_lock_init(&sc->sc_txbuflock);
2082
2083 /* Setup tx descriptors */
2084 error = ath_descdma_setup(sc, &sc->sc_txdma, &sc->sc_txbuf,
2085 "tx", nbufs, 1);
2086 if (error != 0) {
2087 DPRINTF(sc, ATH_DBG_FATAL,
2088 "%s: failed to allocate tx descriptors: %d\n",
2089 __func__, error);
2090 break;
2091 }
2092
2093 /* XXX allocate beacon state together with vap */
2094 error = ath_descdma_setup(sc, &sc->sc_bdma, &sc->sc_bbuf,
2095 "beacon", ATH_BCBUF, 1);
2096 if (error != 0) {
2097 DPRINTF(sc, ATH_DBG_FATAL,
2098 "%s: failed to allocate "
2099 "beacon descripotrs: %d\n",
2100 __func__, error);
2101 break;
2102 }
2103
2104 } while (0);
2105
2106 if (error != 0)
2107 ath_tx_cleanup(sc);
2108
2109 return error;
2110 }
2111
2112 /* Reclaim all tx queue resources */
2113
2114 int ath_tx_cleanup(struct ath_softc *sc)
2115 {
2116 /* cleanup beacon descriptors */
2117 if (sc->sc_bdma.dd_desc_len != 0)
2118 ath_descdma_cleanup(sc, &sc->sc_bdma, &sc->sc_bbuf);
2119
2120 /* cleanup tx descriptors */
2121 if (sc->sc_txdma.dd_desc_len != 0)
2122 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf);
2123
2124 return 0;
2125 }
2126
2127 /* Setup a h/w transmit queue */
2128
2129 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
2130 {
2131 struct ath_hal *ah = sc->sc_ah;
2132 struct ath9k_tx_queue_info qi;
2133 int qnum;
2134
2135 memzero(&qi, sizeof(qi));
2136 qi.tqi_subtype = subtype;
2137 qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT;
2138 qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
2139 qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT;
2140 qi.tqi_physCompBuf = 0;
2141
2142 /*
2143 * Enable interrupts only for EOL and DESC conditions.
2144 * We mark tx descriptors to receive a DESC interrupt
2145 * when a tx queue gets deep; otherwise waiting for the
2146 * EOL to reap descriptors. Note that this is done to
2147 * reduce interrupt load and this only defers reaping
2148 * descriptors, never transmitting frames. Aside from
2149 * reducing interrupts this also permits more concurrency.
2150 * The only potential downside is if the tx queue backs
2151 * up in which case the top half of the kernel may backup
2152 * due to a lack of tx descriptors.
2153 *
2154 * The UAPSD queue is an exception, since we take a desc-
2155 * based intr on the EOSP frames.
2156 */
2157 if (qtype == ATH9K_TX_QUEUE_UAPSD)
2158 qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE;
2159 else
2160 qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE |
2161 TXQ_FLAG_TXDESCINT_ENABLE;
2162 qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi);
2163 if (qnum == -1) {
2164 /*
2165 * NB: don't print a message, this happens
2166 * normally on parts with too few tx queues
2167 */
2168 return NULL;
2169 }
2170 if (qnum >= ARRAY_SIZE(sc->sc_txq)) {
2171 DPRINTF(sc, ATH_DBG_FATAL,
2172 "%s: hal qnum %u out of range, max %u!\n",
2173 __func__, qnum, (unsigned int)ARRAY_SIZE(sc->sc_txq));
2174 ath9k_hw_releasetxqueue(ah, qnum);
2175 return NULL;
2176 }
2177 if (!ATH_TXQ_SETUP(sc, qnum)) {
2178 struct ath_txq *txq = &sc->sc_txq[qnum];
2179
2180 txq->axq_qnum = qnum;
2181 txq->axq_link = NULL;
2182 INIT_LIST_HEAD(&txq->axq_q);
2183 INIT_LIST_HEAD(&txq->axq_acq);
2184 spin_lock_init(&txq->axq_lock);
2185 txq->axq_depth = 0;
2186 txq->axq_aggr_depth = 0;
2187 txq->axq_totalqueued = 0;
2188 txq->axq_intrcnt = 0;
2189 txq->axq_linkbuf = NULL;
2190 sc->sc_txqsetup |= 1<<qnum;
2191 }
2192 return &sc->sc_txq[qnum];
2193 }
2194
2195 /* Reclaim resources for a setup queue */
2196
2197 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
2198 {
2199 ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum);
2200 sc->sc_txqsetup &= ~(1<<txq->axq_qnum);
2201 }
2202
2203 /*
2204 * Setup a hardware data transmit queue for the specified
2205 * access control. The hal may not support all requested
2206 * queues in which case it will return a reference to a
2207 * previously setup queue. We record the mapping from ac's
2208 * to h/w queues for use by ath_tx_start and also track
2209 * the set of h/w queues being used to optimize work in the
2210 * transmit interrupt handler and related routines.
2211 */
2212
2213 int ath_tx_setup(struct ath_softc *sc, int haltype)
2214 {
2215 struct ath_txq *txq;
2216
2217 if (haltype >= ARRAY_SIZE(sc->sc_haltype2q)) {
2218 DPRINTF(sc, ATH_DBG_FATAL,
2219 "%s: HAL AC %u out of range, max %zu!\n",
2220 __func__, haltype, ARRAY_SIZE(sc->sc_haltype2q));
2221 return 0;
2222 }
2223 txq = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, haltype);
2224 if (txq != NULL) {
2225 sc->sc_haltype2q[haltype] = txq->axq_qnum;
2226 return 1;
2227 } else
2228 return 0;
2229 }
2230
2231 int ath_tx_get_qnum(struct ath_softc *sc, int qtype, int haltype)
2232 {
2233 int qnum;
2234
2235 switch (qtype) {
2236 case ATH9K_TX_QUEUE_DATA:
2237 if (haltype >= ARRAY_SIZE(sc->sc_haltype2q)) {
2238 DPRINTF(sc, ATH_DBG_FATAL,
2239 "%s: HAL AC %u out of range, max %zu!\n",
2240 __func__,
2241 haltype, ARRAY_SIZE(sc->sc_haltype2q));
2242 return -1;
2243 }
2244 qnum = sc->sc_haltype2q[haltype];
2245 break;
2246 case ATH9K_TX_QUEUE_BEACON:
2247 qnum = sc->sc_bhalq;
2248 break;
2249 case ATH9K_TX_QUEUE_CAB:
2250 qnum = sc->sc_cabq->axq_qnum;
2251 break;
2252 default:
2253 qnum = -1;
2254 }
2255 return qnum;
2256 }
2257
2258 /* Update parameters for a transmit queue */
2259
2260 int ath_txq_update(struct ath_softc *sc, int qnum,
2261 struct ath9k_tx_queue_info *qinfo)
2262 {
2263 struct ath_hal *ah = sc->sc_ah;
2264 int error = 0;
2265 struct ath9k_tx_queue_info qi;
2266
2267 if (qnum == sc->sc_bhalq) {
2268 /*
2269 * XXX: for beacon queue, we just save the parameter.
2270 * It will be picked up by ath_beaconq_config when
2271 * it's necessary.
2272 */
2273 sc->sc_beacon_qi = *qinfo;
2274 return 0;
2275 }
2276
2277 ASSERT(sc->sc_txq[qnum].axq_qnum == qnum);
2278
2279 ath9k_hw_get_txq_props(ah, qnum, &qi);
2280 qi.tqi_aifs = qinfo->tqi_aifs;
2281 qi.tqi_cwmin = qinfo->tqi_cwmin;
2282 qi.tqi_cwmax = qinfo->tqi_cwmax;
2283 qi.tqi_burstTime = qinfo->tqi_burstTime;
2284 qi.tqi_readyTime = qinfo->tqi_readyTime;
2285
2286 if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) {
2287 DPRINTF(sc, ATH_DBG_FATAL,
2288 "%s: unable to update hardware queue %u!\n",
2289 __func__, qnum);
2290 error = -EIO;
2291 } else {
2292 ath9k_hw_resettxqueue(ah, qnum); /* push to h/w */
2293 }
2294
2295 return error;
2296 }
2297
2298 int ath_cabq_update(struct ath_softc *sc)
2299 {
2300 struct ath9k_tx_queue_info qi;
2301 int qnum = sc->sc_cabq->axq_qnum;
2302 struct ath_beacon_config conf;
2303
2304 ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi);
2305 /*
2306 * Ensure the readytime % is within the bounds.
2307 */
2308 if (sc->sc_config.cabqReadytime < ATH9K_READY_TIME_LO_BOUND)
2309 sc->sc_config.cabqReadytime = ATH9K_READY_TIME_LO_BOUND;
2310 else if (sc->sc_config.cabqReadytime > ATH9K_READY_TIME_HI_BOUND)
2311 sc->sc_config.cabqReadytime = ATH9K_READY_TIME_HI_BOUND;
2312
2313 ath_get_beaconconfig(sc, ATH_IF_ID_ANY, &conf);
2314 qi.tqi_readyTime =
2315 (conf.beacon_interval * sc->sc_config.cabqReadytime) / 100;
2316 ath_txq_update(sc, qnum, &qi);
2317
2318 return 0;
2319 }
2320
2321 int ath_tx_start(struct ath_softc *sc, struct sk_buff *skb)
2322 {
2323 struct ath_tx_control txctl;
2324 int error = 0;
2325
2326 memset(&txctl, 0, sizeof(struct ath_tx_control));
2327 error = ath_tx_prepare(sc, skb, &txctl);
2328 if (error == 0)
2329 /*
2330 * Start DMA mapping.
2331 * ath_tx_start_dma() will be called either synchronously
2332 * or asynchrounsly once DMA is complete.
2333 */
2334 xmit_map_sg(sc, skb, &txctl);
2335 else
2336 ath_node_put(sc, txctl.an, ATH9K_BH_STATUS_CHANGE);
2337
2338 /* failed packets will be dropped by the caller */
2339 return error;
2340 }
2341
2342 /* Deferred processing of transmit interrupt */
2343
2344 void ath_tx_tasklet(struct ath_softc *sc)
2345 {
2346 u64 tsf = ath9k_hw_gettsf64(sc->sc_ah);
2347 int i, nacked = 0;
2348 u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1);
2349
2350 ath9k_hw_gettxintrtxqs(sc->sc_ah, &qcumask);
2351
2352 /*
2353 * Process each active queue.
2354 */
2355 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2356 if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i)))
2357 nacked += ath_tx_processq(sc, &sc->sc_txq[i]);
2358 }
2359 if (nacked)
2360 sc->sc_lastrx = tsf;
2361 }
2362
2363 void ath_tx_draintxq(struct ath_softc *sc,
2364 struct ath_txq *txq, bool retry_tx)
2365 {
2366 struct ath_buf *bf, *lastbf;
2367 struct list_head bf_head;
2368
2369 INIT_LIST_HEAD(&bf_head);
2370
2371 /*
2372 * NB: this assumes output has been stopped and
2373 * we do not need to block ath_tx_tasklet
2374 */
2375 for (;;) {
2376 spin_lock_bh(&txq->axq_lock);
2377
2378 if (list_empty(&txq->axq_q)) {
2379 txq->axq_link = NULL;
2380 txq->axq_linkbuf = NULL;
2381 spin_unlock_bh(&txq->axq_lock);
2382 break;
2383 }
2384
2385 bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
2386
2387 if (bf->bf_status & ATH_BUFSTATUS_STALE) {
2388 list_del(&bf->list);
2389 spin_unlock_bh(&txq->axq_lock);
2390
2391 spin_lock_bh(&sc->sc_txbuflock);
2392 list_add_tail(&bf->list, &sc->sc_txbuf);
2393 spin_unlock_bh(&sc->sc_txbuflock);
2394 continue;
2395 }
2396
2397 lastbf = bf->bf_lastbf;
2398 if (!retry_tx)
2399 lastbf->bf_desc->ds_txstat.ts_flags =
2400 ATH9K_TX_SW_ABORTED;
2401
2402 /* remove ath_buf's of the same mpdu from txq */
2403 list_cut_position(&bf_head, &txq->axq_q, &lastbf->list);
2404 txq->axq_depth--;
2405
2406 spin_unlock_bh(&txq->axq_lock);
2407
2408 if (bf_isampdu(bf))
2409 ath_tx_complete_aggr_rifs(sc, txq, bf, &bf_head, 0);
2410 else
2411 ath_tx_complete_buf(sc, bf, &bf_head, 0, 0);
2412 }
2413
2414 /* flush any pending frames if aggregation is enabled */
2415 if (sc->sc_flags & SC_OP_TXAGGR) {
2416 if (!retry_tx) {
2417 spin_lock_bh(&txq->axq_lock);
2418 ath_txq_drain_pending_buffers(sc, txq,
2419 ATH9K_BH_STATUS_CHANGE);
2420 spin_unlock_bh(&txq->axq_lock);
2421 }
2422 }
2423 }
2424
2425 /* Drain the transmit queues and reclaim resources */
2426
2427 void ath_draintxq(struct ath_softc *sc, bool retry_tx)
2428 {
2429 /* stop beacon queue. The beacon will be freed when
2430 * we go to INIT state */
2431 if (!(sc->sc_flags & SC_OP_INVALID)) {
2432 (void) ath9k_hw_stoptxdma(sc->sc_ah, sc->sc_bhalq);
2433 DPRINTF(sc, ATH_DBG_XMIT, "%s: beacon queue %x\n", __func__,
2434 ath9k_hw_gettxbuf(sc->sc_ah, sc->sc_bhalq));
2435 }
2436
2437 ath_drain_txdataq(sc, retry_tx);
2438 }
2439
2440 u32 ath_txq_depth(struct ath_softc *sc, int qnum)
2441 {
2442 return sc->sc_txq[qnum].axq_depth;
2443 }
2444
2445 u32 ath_txq_aggr_depth(struct ath_softc *sc, int qnum)
2446 {
2447 return sc->sc_txq[qnum].axq_aggr_depth;
2448 }
2449
2450 /* Check if an ADDBA is required. A valid node must be passed. */
2451 enum ATH_AGGR_CHECK ath_tx_aggr_check(struct ath_softc *sc,
2452 struct ath_node *an,
2453 u8 tidno)
2454 {
2455 struct ath_atx_tid *txtid;
2456 DECLARE_MAC_BUF(mac);
2457
2458 if (!(sc->sc_flags & SC_OP_TXAGGR))
2459 return AGGR_NOT_REQUIRED;
2460
2461 /* ADDBA exchange must be completed before sending aggregates */
2462 txtid = ATH_AN_2_TID(an, tidno);
2463
2464 if (txtid->addba_exchangecomplete)
2465 return AGGR_EXCHANGE_DONE;
2466
2467 if (txtid->cleanup_inprogress)
2468 return AGGR_CLEANUP_PROGRESS;
2469
2470 if (txtid->addba_exchangeinprogress)
2471 return AGGR_EXCHANGE_PROGRESS;
2472
2473 if (!txtid->addba_exchangecomplete) {
2474 if (!txtid->addba_exchangeinprogress &&
2475 (txtid->addba_exchangeattempts < ADDBA_EXCHANGE_ATTEMPTS)) {
2476 txtid->addba_exchangeattempts++;
2477 return AGGR_REQUIRED;
2478 }
2479 }
2480
2481 return AGGR_NOT_REQUIRED;
2482 }
2483
2484 /* Start TX aggregation */
2485
2486 int ath_tx_aggr_start(struct ath_softc *sc,
2487 const u8 *addr,
2488 u16 tid,
2489 u16 *ssn)
2490 {
2491 struct ath_atx_tid *txtid;
2492 struct ath_node *an;
2493
2494 spin_lock_bh(&sc->node_lock);
2495 an = ath_node_find(sc, (u8 *) addr);
2496 spin_unlock_bh(&sc->node_lock);
2497
2498 if (!an) {
2499 DPRINTF(sc, ATH_DBG_AGGR,
2500 "%s: Node not found to initialize "
2501 "TX aggregation\n", __func__);
2502 return -1;
2503 }
2504
2505 if (sc->sc_flags & SC_OP_TXAGGR) {
2506 txtid = ATH_AN_2_TID(an, tid);
2507 txtid->addba_exchangeinprogress = 1;
2508 ath_tx_pause_tid(sc, txtid);
2509 }
2510
2511 return 0;
2512 }
2513
2514 /* Stop tx aggregation */
2515
2516 int ath_tx_aggr_stop(struct ath_softc *sc,
2517 const u8 *addr,
2518 u16 tid)
2519 {
2520 struct ath_node *an;
2521
2522 spin_lock_bh(&sc->node_lock);
2523 an = ath_node_find(sc, (u8 *) addr);
2524 spin_unlock_bh(&sc->node_lock);
2525
2526 if (!an) {
2527 DPRINTF(sc, ATH_DBG_AGGR,
2528 "%s: TX aggr stop for non-existent node\n", __func__);
2529 return -1;
2530 }
2531
2532 ath_tx_aggr_teardown(sc, an, tid);
2533 return 0;
2534 }
2535
2536 /*
2537 * Performs transmit side cleanup when TID changes from aggregated to
2538 * unaggregated.
2539 * - Pause the TID and mark cleanup in progress
2540 * - Discard all retry frames from the s/w queue.
2541 */
2542
2543 void ath_tx_aggr_teardown(struct ath_softc *sc,
2544 struct ath_node *an, u8 tid)
2545 {
2546 struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid);
2547 struct ath_txq *txq = &sc->sc_txq[txtid->ac->qnum];
2548 struct ath_buf *bf;
2549 struct list_head bf_head;
2550 INIT_LIST_HEAD(&bf_head);
2551
2552 DPRINTF(sc, ATH_DBG_AGGR, "%s: teardown TX aggregation\n", __func__);
2553
2554 if (txtid->cleanup_inprogress) /* cleanup is in progress */
2555 return;
2556
2557 if (!txtid->addba_exchangecomplete) {
2558 txtid->addba_exchangeattempts = 0;
2559 return;
2560 }
2561
2562 /* TID must be paused first */
2563 ath_tx_pause_tid(sc, txtid);
2564
2565 /* drop all software retried frames and mark this TID */
2566 spin_lock_bh(&txq->axq_lock);
2567 while (!list_empty(&txtid->buf_q)) {
2568 bf = list_first_entry(&txtid->buf_q, struct ath_buf, list);
2569 if (!bf_isretried(bf)) {
2570 /*
2571 * NB: it's based on the assumption that
2572 * software retried frame will always stay
2573 * at the head of software queue.
2574 */
2575 break;
2576 }
2577 list_cut_position(&bf_head,
2578 &txtid->buf_q, &bf->bf_lastfrm->list);
2579 ath_tx_update_baw(sc, txtid, bf->bf_seqno);
2580
2581 /* complete this sub-frame */
2582 ath_tx_complete_buf(sc, bf, &bf_head, 0, 0);
2583 }
2584
2585 if (txtid->baw_head != txtid->baw_tail) {
2586 spin_unlock_bh(&txq->axq_lock);
2587 txtid->cleanup_inprogress = true;
2588 } else {
2589 txtid->addba_exchangecomplete = 0;
2590 txtid->addba_exchangeattempts = 0;
2591 spin_unlock_bh(&txq->axq_lock);
2592 ath_tx_flush_tid(sc, txtid);
2593 }
2594 }
2595
2596 /*
2597 * Tx scheduling logic
2598 * NB: must be called with txq lock held
2599 */
2600
2601 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq)
2602 {
2603 struct ath_atx_ac *ac;
2604 struct ath_atx_tid *tid;
2605
2606 /* nothing to schedule */
2607 if (list_empty(&txq->axq_acq))
2608 return;
2609 /*
2610 * get the first node/ac pair on the queue
2611 */
2612 ac = list_first_entry(&txq->axq_acq, struct ath_atx_ac, list);
2613 list_del(&ac->list);
2614 ac->sched = false;
2615
2616 /*
2617 * process a single tid per destination
2618 */
2619 do {
2620 /* nothing to schedule */
2621 if (list_empty(&ac->tid_q))
2622 return;
2623
2624 tid = list_first_entry(&ac->tid_q, struct ath_atx_tid, list);
2625 list_del(&tid->list);
2626 tid->sched = false;
2627
2628 if (tid->paused) /* check next tid to keep h/w busy */
2629 continue;
2630
2631 if (!(tid->an->an_smmode == ATH_SM_PWRSAV_DYNAMIC) ||
2632 ((txq->axq_depth % 2) == 0)) {
2633 ath_tx_sched_aggr(sc, txq, tid);
2634 }
2635
2636 /*
2637 * add tid to round-robin queue if more frames
2638 * are pending for the tid
2639 */
2640 if (!list_empty(&tid->buf_q))
2641 ath_tx_queue_tid(txq, tid);
2642
2643 /* only schedule one TID at a time */
2644 break;
2645 } while (!list_empty(&ac->tid_q));
2646
2647 /*
2648 * schedule AC if more TIDs need processing
2649 */
2650 if (!list_empty(&ac->tid_q)) {
2651 /*
2652 * add dest ac to txq if not already added
2653 */
2654 if (!ac->sched) {
2655 ac->sched = true;
2656 list_add_tail(&ac->list, &txq->axq_acq);
2657 }
2658 }
2659 }
2660
2661 /* Initialize per-node transmit state */
2662
2663 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an)
2664 {
2665 if (sc->sc_flags & SC_OP_TXAGGR) {
2666 struct ath_atx_tid *tid;
2667 struct ath_atx_ac *ac;
2668 int tidno, acno;
2669
2670 sc->sc_ht_info.maxampdu = ATH_AMPDU_LIMIT_DEFAULT;
2671
2672 /*
2673 * Init per tid tx state
2674 */
2675 for (tidno = 0, tid = &an->an_aggr.tx.tid[tidno];
2676 tidno < WME_NUM_TID;
2677 tidno++, tid++) {
2678 tid->an = an;
2679 tid->tidno = tidno;
2680 tid->seq_start = tid->seq_next = 0;
2681 tid->baw_size = WME_MAX_BA;
2682 tid->baw_head = tid->baw_tail = 0;
2683 tid->sched = false;
2684 tid->paused = false;
2685 tid->cleanup_inprogress = false;
2686 INIT_LIST_HEAD(&tid->buf_q);
2687
2688 acno = TID_TO_WME_AC(tidno);
2689 tid->ac = &an->an_aggr.tx.ac[acno];
2690
2691 /* ADDBA state */
2692 tid->addba_exchangecomplete = 0;
2693 tid->addba_exchangeinprogress = 0;
2694 tid->addba_exchangeattempts = 0;
2695 }
2696
2697 /*
2698 * Init per ac tx state
2699 */
2700 for (acno = 0, ac = &an->an_aggr.tx.ac[acno];
2701 acno < WME_NUM_AC; acno++, ac++) {
2702 ac->sched = false;
2703 INIT_LIST_HEAD(&ac->tid_q);
2704
2705 switch (acno) {
2706 case WME_AC_BE:
2707 ac->qnum = ath_tx_get_qnum(sc,
2708 ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BE);
2709 break;
2710 case WME_AC_BK:
2711 ac->qnum = ath_tx_get_qnum(sc,
2712 ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BK);
2713 break;
2714 case WME_AC_VI:
2715 ac->qnum = ath_tx_get_qnum(sc,
2716 ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_VI);
2717 break;
2718 case WME_AC_VO:
2719 ac->qnum = ath_tx_get_qnum(sc,
2720 ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_VO);
2721 break;
2722 }
2723 }
2724 }
2725 }
2726
2727 /* Cleanupthe pending buffers for the node. */
2728
2729 void ath_tx_node_cleanup(struct ath_softc *sc,
2730 struct ath_node *an, bool bh_flag)
2731 {
2732 int i;
2733 struct ath_atx_ac *ac, *ac_tmp;
2734 struct ath_atx_tid *tid, *tid_tmp;
2735 struct ath_txq *txq;
2736 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2737 if (ATH_TXQ_SETUP(sc, i)) {
2738 txq = &sc->sc_txq[i];
2739
2740 if (likely(bh_flag))
2741 spin_lock_bh(&txq->axq_lock);
2742 else
2743 spin_lock(&txq->axq_lock);
2744
2745 list_for_each_entry_safe(ac,
2746 ac_tmp, &txq->axq_acq, list) {
2747 tid = list_first_entry(&ac->tid_q,
2748 struct ath_atx_tid, list);
2749 if (tid && tid->an != an)
2750 continue;
2751 list_del(&ac->list);
2752 ac->sched = false;
2753
2754 list_for_each_entry_safe(tid,
2755 tid_tmp, &ac->tid_q, list) {
2756 list_del(&tid->list);
2757 tid->sched = false;
2758 ath_tid_drain(sc, txq, tid, bh_flag);
2759 tid->addba_exchangecomplete = 0;
2760 tid->addba_exchangeattempts = 0;
2761 tid->cleanup_inprogress = false;
2762 }
2763 }
2764
2765 if (likely(bh_flag))
2766 spin_unlock_bh(&txq->axq_lock);
2767 else
2768 spin_unlock(&txq->axq_lock);
2769 }
2770 }
2771 }
2772
2773 /* Cleanup per node transmit state */
2774
2775 void ath_tx_node_free(struct ath_softc *sc, struct ath_node *an)
2776 {
2777 if (sc->sc_flags & SC_OP_TXAGGR) {
2778 struct ath_atx_tid *tid;
2779 int tidno, i;
2780
2781 /* Init per tid rx state */
2782 for (tidno = 0, tid = &an->an_aggr.tx.tid[tidno];
2783 tidno < WME_NUM_TID;
2784 tidno++, tid++) {
2785
2786 for (i = 0; i < ATH_TID_MAX_BUFS; i++)
2787 ASSERT(tid->tx_buf[i] == NULL);
2788 }
2789 }
2790 }
2791
2792 void ath_tx_cabq(struct ath_softc *sc, struct sk_buff *skb)
2793 {
2794 int hdrlen, padsize;
2795 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2796 struct ath_tx_control txctl;
2797
2798 /*
2799 * As a temporary workaround, assign seq# here; this will likely need
2800 * to be cleaned up to work better with Beacon transmission and virtual
2801 * BSSes.
2802 */
2803 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
2804 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2805 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
2806 sc->seq_no += 0x10;
2807 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
2808 hdr->seq_ctrl |= cpu_to_le16(sc->seq_no);
2809 }
2810
2811 /* Add the padding after the header if this is not already done */
2812 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2813 if (hdrlen & 3) {
2814 padsize = hdrlen % 4;
2815 if (skb_headroom(skb) < padsize) {
2816 DPRINTF(sc, ATH_DBG_XMIT, "%s: TX CABQ padding "
2817 "failed\n", __func__);
2818 dev_kfree_skb_any(skb);
2819 return;
2820 }
2821 skb_push(skb, padsize);
2822 memmove(skb->data, skb->data + padsize, hdrlen);
2823 }
2824
2825 DPRINTF(sc, ATH_DBG_XMIT, "%s: transmitting CABQ packet, skb: %p\n",
2826 __func__,
2827 skb);
2828
2829 memset(&txctl, 0, sizeof(struct ath_tx_control));
2830 txctl.flags = ATH9K_TXDESC_CAB;
2831 if (ath_tx_prepare(sc, skb, &txctl) == 0) {
2832 /*
2833 * Start DMA mapping.
2834 * ath_tx_start_dma() will be called either synchronously
2835 * or asynchrounsly once DMA is complete.
2836 */
2837 xmit_map_sg(sc, skb, &txctl);
2838 } else {
2839 ath_node_put(sc, txctl.an, ATH9K_BH_STATUS_CHANGE);
2840 DPRINTF(sc, ATH_DBG_XMIT, "%s: TX CABQ failed\n", __func__);
2841 dev_kfree_skb_any(skb);
2842 }
2843 }
2844
Linux kernel - Deliverables
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