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ath9k: Virtual wiphy pause/unpause functionality
[deliverable/linux.git] / drivers / net / wireless / ath9k / xmit.c
1 /*
2 * Copyright (c) 2008 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include "ath9k.h"
18
19 #define BITS_PER_BYTE 8
20 #define OFDM_PLCP_BITS 22
21 #define HT_RC_2_MCS(_rc) ((_rc) & 0x0f)
22 #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
23 #define L_STF 8
24 #define L_LTF 8
25 #define L_SIG 4
26 #define HT_SIG 8
27 #define HT_STF 4
28 #define HT_LTF(_ns) (4 * (_ns))
29 #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */
30 #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */
31 #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
32 #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
33
34 #define OFDM_SIFS_TIME 16
35
36 static u32 bits_per_symbol[][2] = {
37 /* 20MHz 40MHz */
38 { 26, 54 }, /* 0: BPSK */
39 { 52, 108 }, /* 1: QPSK 1/2 */
40 { 78, 162 }, /* 2: QPSK 3/4 */
41 { 104, 216 }, /* 3: 16-QAM 1/2 */
42 { 156, 324 }, /* 4: 16-QAM 3/4 */
43 { 208, 432 }, /* 5: 64-QAM 2/3 */
44 { 234, 486 }, /* 6: 64-QAM 3/4 */
45 { 260, 540 }, /* 7: 64-QAM 5/6 */
46 { 52, 108 }, /* 8: BPSK */
47 { 104, 216 }, /* 9: QPSK 1/2 */
48 { 156, 324 }, /* 10: QPSK 3/4 */
49 { 208, 432 }, /* 11: 16-QAM 1/2 */
50 { 312, 648 }, /* 12: 16-QAM 3/4 */
51 { 416, 864 }, /* 13: 64-QAM 2/3 */
52 { 468, 972 }, /* 14: 64-QAM 3/4 */
53 { 520, 1080 }, /* 15: 64-QAM 5/6 */
54 };
55
56 #define IS_HT_RATE(_rate) ((_rate) & 0x80)
57
58 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
59 struct ath_atx_tid *tid,
60 struct list_head *bf_head);
61 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
62 struct list_head *bf_q,
63 int txok, int sendbar);
64 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
65 struct list_head *head);
66 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf);
67
68 /*********************/
69 /* Aggregation logic */
70 /*********************/
71
72 static int ath_aggr_query(struct ath_softc *sc, struct ath_node *an, u8 tidno)
73 {
74 struct ath_atx_tid *tid;
75 tid = ATH_AN_2_TID(an, tidno);
76
77 if (tid->state & AGGR_ADDBA_COMPLETE ||
78 tid->state & AGGR_ADDBA_PROGRESS)
79 return 1;
80 else
81 return 0;
82 }
83
84 static void ath_tx_queue_tid(struct ath_txq *txq, struct ath_atx_tid *tid)
85 {
86 struct ath_atx_ac *ac = tid->ac;
87
88 if (tid->paused)
89 return;
90
91 if (tid->sched)
92 return;
93
94 tid->sched = true;
95 list_add_tail(&tid->list, &ac->tid_q);
96
97 if (ac->sched)
98 return;
99
100 ac->sched = true;
101 list_add_tail(&ac->list, &txq->axq_acq);
102 }
103
104 static void ath_tx_pause_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
105 {
106 struct ath_txq *txq = &sc->tx.txq[tid->ac->qnum];
107
108 spin_lock_bh(&txq->axq_lock);
109 tid->paused++;
110 spin_unlock_bh(&txq->axq_lock);
111 }
112
113 static void ath_tx_resume_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
114 {
115 struct ath_txq *txq = &sc->tx.txq[tid->ac->qnum];
116
117 ASSERT(tid->paused > 0);
118 spin_lock_bh(&txq->axq_lock);
119
120 tid->paused--;
121
122 if (tid->paused > 0)
123 goto unlock;
124
125 if (list_empty(&tid->buf_q))
126 goto unlock;
127
128 ath_tx_queue_tid(txq, tid);
129 ath_txq_schedule(sc, txq);
130 unlock:
131 spin_unlock_bh(&txq->axq_lock);
132 }
133
134 static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
135 {
136 struct ath_txq *txq = &sc->tx.txq[tid->ac->qnum];
137 struct ath_buf *bf;
138 struct list_head bf_head;
139 INIT_LIST_HEAD(&bf_head);
140
141 ASSERT(tid->paused > 0);
142 spin_lock_bh(&txq->axq_lock);
143
144 tid->paused--;
145
146 if (tid->paused > 0) {
147 spin_unlock_bh(&txq->axq_lock);
148 return;
149 }
150
151 while (!list_empty(&tid->buf_q)) {
152 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
153 ASSERT(!bf_isretried(bf));
154 list_move_tail(&bf->list, &bf_head);
155 ath_tx_send_normal(sc, txq, tid, &bf_head);
156 }
157
158 spin_unlock_bh(&txq->axq_lock);
159 }
160
161 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
162 int seqno)
163 {
164 int index, cindex;
165
166 index = ATH_BA_INDEX(tid->seq_start, seqno);
167 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
168
169 tid->tx_buf[cindex] = NULL;
170
171 while (tid->baw_head != tid->baw_tail && !tid->tx_buf[tid->baw_head]) {
172 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
173 INCR(tid->baw_head, ATH_TID_MAX_BUFS);
174 }
175 }
176
177 static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
178 struct ath_buf *bf)
179 {
180 int index, cindex;
181
182 if (bf_isretried(bf))
183 return;
184
185 index = ATH_BA_INDEX(tid->seq_start, bf->bf_seqno);
186 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
187
188 ASSERT(tid->tx_buf[cindex] == NULL);
189 tid->tx_buf[cindex] = bf;
190
191 if (index >= ((tid->baw_tail - tid->baw_head) &
192 (ATH_TID_MAX_BUFS - 1))) {
193 tid->baw_tail = cindex;
194 INCR(tid->baw_tail, ATH_TID_MAX_BUFS);
195 }
196 }
197
198 /*
199 * TODO: For frame(s) that are in the retry state, we will reuse the
200 * sequence number(s) without setting the retry bit. The
201 * alternative is to give up on these and BAR the receiver's window
202 * forward.
203 */
204 static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq,
205 struct ath_atx_tid *tid)
206
207 {
208 struct ath_buf *bf;
209 struct list_head bf_head;
210 INIT_LIST_HEAD(&bf_head);
211
212 for (;;) {
213 if (list_empty(&tid->buf_q))
214 break;
215
216 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
217 list_move_tail(&bf->list, &bf_head);
218
219 if (bf_isretried(bf))
220 ath_tx_update_baw(sc, tid, bf->bf_seqno);
221
222 spin_unlock(&txq->axq_lock);
223 ath_tx_complete_buf(sc, bf, &bf_head, 0, 0);
224 spin_lock(&txq->axq_lock);
225 }
226
227 tid->seq_next = tid->seq_start;
228 tid->baw_tail = tid->baw_head;
229 }
230
231 static void ath_tx_set_retry(struct ath_softc *sc, struct ath_buf *bf)
232 {
233 struct sk_buff *skb;
234 struct ieee80211_hdr *hdr;
235
236 bf->bf_state.bf_type |= BUF_RETRY;
237 bf->bf_retries++;
238
239 skb = bf->bf_mpdu;
240 hdr = (struct ieee80211_hdr *)skb->data;
241 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY);
242 }
243
244 static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf)
245 {
246 struct ath_buf *tbf;
247
248 spin_lock_bh(&sc->tx.txbuflock);
249 ASSERT(!list_empty((&sc->tx.txbuf)));
250 tbf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list);
251 list_del(&tbf->list);
252 spin_unlock_bh(&sc->tx.txbuflock);
253
254 ATH_TXBUF_RESET(tbf);
255
256 tbf->bf_mpdu = bf->bf_mpdu;
257 tbf->bf_buf_addr = bf->bf_buf_addr;
258 *(tbf->bf_desc) = *(bf->bf_desc);
259 tbf->bf_state = bf->bf_state;
260 tbf->bf_dmacontext = bf->bf_dmacontext;
261
262 return tbf;
263 }
264
265 static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
266 struct ath_buf *bf, struct list_head *bf_q,
267 int txok)
268 {
269 struct ath_node *an = NULL;
270 struct sk_buff *skb;
271 struct ieee80211_sta *sta;
272 struct ieee80211_hdr *hdr;
273 struct ath_atx_tid *tid = NULL;
274 struct ath_buf *bf_next, *bf_last = bf->bf_lastbf;
275 struct ath_desc *ds = bf_last->bf_desc;
276 struct list_head bf_head, bf_pending;
277 u16 seq_st = 0;
278 u32 ba[WME_BA_BMP_SIZE >> 5];
279 int isaggr, txfail, txpending, sendbar = 0, needreset = 0;
280
281 skb = (struct sk_buff *)bf->bf_mpdu;
282 hdr = (struct ieee80211_hdr *)skb->data;
283
284 rcu_read_lock();
285
286 sta = ieee80211_find_sta(sc->hw, hdr->addr1);
287 if (!sta) {
288 rcu_read_unlock();
289 return;
290 }
291
292 an = (struct ath_node *)sta->drv_priv;
293 tid = ATH_AN_2_TID(an, bf->bf_tidno);
294
295 isaggr = bf_isaggr(bf);
296 memset(ba, 0, WME_BA_BMP_SIZE >> 3);
297
298 if (isaggr && txok) {
299 if (ATH_DS_TX_BA(ds)) {
300 seq_st = ATH_DS_BA_SEQ(ds);
301 memcpy(ba, ATH_DS_BA_BITMAP(ds),
302 WME_BA_BMP_SIZE >> 3);
303 } else {
304 /*
305 * AR5416 can become deaf/mute when BA
306 * issue happens. Chip needs to be reset.
307 * But AP code may have sychronization issues
308 * when perform internal reset in this routine.
309 * Only enable reset in STA mode for now.
310 */
311 if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION)
312 needreset = 1;
313 }
314 }
315
316 INIT_LIST_HEAD(&bf_pending);
317 INIT_LIST_HEAD(&bf_head);
318
319 while (bf) {
320 txfail = txpending = 0;
321 bf_next = bf->bf_next;
322
323 if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, bf->bf_seqno))) {
324 /* transmit completion, subframe is
325 * acked by block ack */
326 } else if (!isaggr && txok) {
327 /* transmit completion */
328 } else {
329 if (!(tid->state & AGGR_CLEANUP) &&
330 ds->ds_txstat.ts_flags != ATH9K_TX_SW_ABORTED) {
331 if (bf->bf_retries < ATH_MAX_SW_RETRIES) {
332 ath_tx_set_retry(sc, bf);
333 txpending = 1;
334 } else {
335 bf->bf_state.bf_type |= BUF_XRETRY;
336 txfail = 1;
337 sendbar = 1;
338 }
339 } else {
340 /*
341 * cleanup in progress, just fail
342 * the un-acked sub-frames
343 */
344 txfail = 1;
345 }
346 }
347
348 if (bf_next == NULL) {
349 INIT_LIST_HEAD(&bf_head);
350 } else {
351 ASSERT(!list_empty(bf_q));
352 list_move_tail(&bf->list, &bf_head);
353 }
354
355 if (!txpending) {
356 /*
357 * complete the acked-ones/xretried ones; update
358 * block-ack window
359 */
360 spin_lock_bh(&txq->axq_lock);
361 ath_tx_update_baw(sc, tid, bf->bf_seqno);
362 spin_unlock_bh(&txq->axq_lock);
363
364 ath_tx_complete_buf(sc, bf, &bf_head, !txfail, sendbar);
365 } else {
366 /* retry the un-acked ones */
367 if (bf->bf_next == NULL &&
368 bf_last->bf_status & ATH_BUFSTATUS_STALE) {
369 struct ath_buf *tbf;
370
371 tbf = ath_clone_txbuf(sc, bf_last);
372 ath9k_hw_cleartxdesc(sc->sc_ah, tbf->bf_desc);
373 list_add_tail(&tbf->list, &bf_head);
374 } else {
375 /*
376 * Clear descriptor status words for
377 * software retry
378 */
379 ath9k_hw_cleartxdesc(sc->sc_ah, bf->bf_desc);
380 }
381
382 /*
383 * Put this buffer to the temporary pending
384 * queue to retain ordering
385 */
386 list_splice_tail_init(&bf_head, &bf_pending);
387 }
388
389 bf = bf_next;
390 }
391
392 if (tid->state & AGGR_CLEANUP) {
393 if (tid->baw_head == tid->baw_tail) {
394 tid->state &= ~AGGR_ADDBA_COMPLETE;
395 tid->addba_exchangeattempts = 0;
396 tid->state &= ~AGGR_CLEANUP;
397
398 /* send buffered frames as singles */
399 ath_tx_flush_tid(sc, tid);
400 }
401 rcu_read_unlock();
402 return;
403 }
404
405 /* prepend un-acked frames to the beginning of the pending frame queue */
406 if (!list_empty(&bf_pending)) {
407 spin_lock_bh(&txq->axq_lock);
408 list_splice(&bf_pending, &tid->buf_q);
409 ath_tx_queue_tid(txq, tid);
410 spin_unlock_bh(&txq->axq_lock);
411 }
412
413 rcu_read_unlock();
414
415 if (needreset)
416 ath_reset(sc, false);
417 }
418
419 static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf,
420 struct ath_atx_tid *tid)
421 {
422 struct ath_rate_table *rate_table = sc->cur_rate_table;
423 struct sk_buff *skb;
424 struct ieee80211_tx_info *tx_info;
425 struct ieee80211_tx_rate *rates;
426 struct ath_tx_info_priv *tx_info_priv;
427 u32 max_4ms_framelen, frmlen;
428 u16 aggr_limit, legacy = 0, maxampdu;
429 int i;
430
431 skb = (struct sk_buff *)bf->bf_mpdu;
432 tx_info = IEEE80211_SKB_CB(skb);
433 rates = tx_info->control.rates;
434 tx_info_priv = (struct ath_tx_info_priv *)tx_info->rate_driver_data[0];
435
436 /*
437 * Find the lowest frame length among the rate series that will have a
438 * 4ms transmit duration.
439 * TODO - TXOP limit needs to be considered.
440 */
441 max_4ms_framelen = ATH_AMPDU_LIMIT_MAX;
442
443 for (i = 0; i < 4; i++) {
444 if (rates[i].count) {
445 if (!WLAN_RC_PHY_HT(rate_table->info[rates[i].idx].phy)) {
446 legacy = 1;
447 break;
448 }
449
450 frmlen = rate_table->info[rates[i].idx].max_4ms_framelen;
451 max_4ms_framelen = min(max_4ms_framelen, frmlen);
452 }
453 }
454
455 /*
456 * limit aggregate size by the minimum rate if rate selected is
457 * not a probe rate, if rate selected is a probe rate then
458 * avoid aggregation of this packet.
459 */
460 if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy)
461 return 0;
462
463 aggr_limit = min(max_4ms_framelen, (u32)ATH_AMPDU_LIMIT_DEFAULT);
464
465 /*
466 * h/w can accept aggregates upto 16 bit lengths (65535).
467 * The IE, however can hold upto 65536, which shows up here
468 * as zero. Ignore 65536 since we are constrained by hw.
469 */
470 maxampdu = tid->an->maxampdu;
471 if (maxampdu)
472 aggr_limit = min(aggr_limit, maxampdu);
473
474 return aggr_limit;
475 }
476
477 /*
478 * Returns the number of delimiters to be added to
479 * meet the minimum required mpdudensity.
480 * caller should make sure that the rate is HT rate .
481 */
482 static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid,
483 struct ath_buf *bf, u16 frmlen)
484 {
485 struct ath_rate_table *rt = sc->cur_rate_table;
486 struct sk_buff *skb = bf->bf_mpdu;
487 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
488 u32 nsymbits, nsymbols, mpdudensity;
489 u16 minlen;
490 u8 rc, flags, rix;
491 int width, half_gi, ndelim, mindelim;
492
493 /* Select standard number of delimiters based on frame length alone */
494 ndelim = ATH_AGGR_GET_NDELIM(frmlen);
495
496 /*
497 * If encryption enabled, hardware requires some more padding between
498 * subframes.
499 * TODO - this could be improved to be dependent on the rate.
500 * The hardware can keep up at lower rates, but not higher rates
501 */
502 if (bf->bf_keytype != ATH9K_KEY_TYPE_CLEAR)
503 ndelim += ATH_AGGR_ENCRYPTDELIM;
504
505 /*
506 * Convert desired mpdu density from microeconds to bytes based
507 * on highest rate in rate series (i.e. first rate) to determine
508 * required minimum length for subframe. Take into account
509 * whether high rate is 20 or 40Mhz and half or full GI.
510 */
511 mpdudensity = tid->an->mpdudensity;
512
513 /*
514 * If there is no mpdu density restriction, no further calculation
515 * is needed.
516 */
517 if (mpdudensity == 0)
518 return ndelim;
519
520 rix = tx_info->control.rates[0].idx;
521 flags = tx_info->control.rates[0].flags;
522 rc = rt->info[rix].ratecode;
523 width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0;
524 half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0;
525
526 if (half_gi)
527 nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(mpdudensity);
528 else
529 nsymbols = NUM_SYMBOLS_PER_USEC(mpdudensity);
530
531 if (nsymbols == 0)
532 nsymbols = 1;
533
534 nsymbits = bits_per_symbol[HT_RC_2_MCS(rc)][width];
535 minlen = (nsymbols * nsymbits) / BITS_PER_BYTE;
536
537 if (frmlen < minlen) {
538 mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ;
539 ndelim = max(mindelim, ndelim);
540 }
541
542 return ndelim;
543 }
544
545 static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc,
546 struct ath_atx_tid *tid,
547 struct list_head *bf_q)
548 {
549 #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
550 struct ath_buf *bf, *bf_first, *bf_prev = NULL;
551 int rl = 0, nframes = 0, ndelim, prev_al = 0;
552 u16 aggr_limit = 0, al = 0, bpad = 0,
553 al_delta, h_baw = tid->baw_size / 2;
554 enum ATH_AGGR_STATUS status = ATH_AGGR_DONE;
555
556 bf_first = list_first_entry(&tid->buf_q, struct ath_buf, list);
557
558 do {
559 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
560
561 /* do not step over block-ack window */
562 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, bf->bf_seqno)) {
563 status = ATH_AGGR_BAW_CLOSED;
564 break;
565 }
566
567 if (!rl) {
568 aggr_limit = ath_lookup_rate(sc, bf, tid);
569 rl = 1;
570 }
571
572 /* do not exceed aggregation limit */
573 al_delta = ATH_AGGR_DELIM_SZ + bf->bf_frmlen;
574
575 if (nframes &&
576 (aggr_limit < (al + bpad + al_delta + prev_al))) {
577 status = ATH_AGGR_LIMITED;
578 break;
579 }
580
581 /* do not exceed subframe limit */
582 if (nframes >= min((int)h_baw, ATH_AMPDU_SUBFRAME_DEFAULT)) {
583 status = ATH_AGGR_LIMITED;
584 break;
585 }
586 nframes++;
587
588 /* add padding for previous frame to aggregation length */
589 al += bpad + al_delta;
590
591 /*
592 * Get the delimiters needed to meet the MPDU
593 * density for this node.
594 */
595 ndelim = ath_compute_num_delims(sc, tid, bf_first, bf->bf_frmlen);
596 bpad = PADBYTES(al_delta) + (ndelim << 2);
597
598 bf->bf_next = NULL;
599 bf->bf_desc->ds_link = 0;
600
601 /* link buffers of this frame to the aggregate */
602 ath_tx_addto_baw(sc, tid, bf);
603 ath9k_hw_set11n_aggr_middle(sc->sc_ah, bf->bf_desc, ndelim);
604 list_move_tail(&bf->list, bf_q);
605 if (bf_prev) {
606 bf_prev->bf_next = bf;
607 bf_prev->bf_desc->ds_link = bf->bf_daddr;
608 }
609 bf_prev = bf;
610 } while (!list_empty(&tid->buf_q));
611
612 bf_first->bf_al = al;
613 bf_first->bf_nframes = nframes;
614
615 return status;
616 #undef PADBYTES
617 }
618
619 static void ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq,
620 struct ath_atx_tid *tid)
621 {
622 struct ath_buf *bf;
623 enum ATH_AGGR_STATUS status;
624 struct list_head bf_q;
625
626 do {
627 if (list_empty(&tid->buf_q))
628 return;
629
630 INIT_LIST_HEAD(&bf_q);
631
632 status = ath_tx_form_aggr(sc, tid, &bf_q);
633
634 /*
635 * no frames picked up to be aggregated;
636 * block-ack window is not open.
637 */
638 if (list_empty(&bf_q))
639 break;
640
641 bf = list_first_entry(&bf_q, struct ath_buf, list);
642 bf->bf_lastbf = list_entry(bf_q.prev, struct ath_buf, list);
643
644 /* if only one frame, send as non-aggregate */
645 if (bf->bf_nframes == 1) {
646 bf->bf_state.bf_type &= ~BUF_AGGR;
647 ath9k_hw_clr11n_aggr(sc->sc_ah, bf->bf_desc);
648 ath_buf_set_rate(sc, bf);
649 ath_tx_txqaddbuf(sc, txq, &bf_q);
650 continue;
651 }
652
653 /* setup first desc of aggregate */
654 bf->bf_state.bf_type |= BUF_AGGR;
655 ath_buf_set_rate(sc, bf);
656 ath9k_hw_set11n_aggr_first(sc->sc_ah, bf->bf_desc, bf->bf_al);
657
658 /* anchor last desc of aggregate */
659 ath9k_hw_set11n_aggr_last(sc->sc_ah, bf->bf_lastbf->bf_desc);
660
661 txq->axq_aggr_depth++;
662 ath_tx_txqaddbuf(sc, txq, &bf_q);
663
664 } while (txq->axq_depth < ATH_AGGR_MIN_QDEPTH &&
665 status != ATH_AGGR_BAW_CLOSED);
666 }
667
668 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
669 u16 tid, u16 *ssn)
670 {
671 struct ath_atx_tid *txtid;
672 struct ath_node *an;
673
674 an = (struct ath_node *)sta->drv_priv;
675
676 if (sc->sc_flags & SC_OP_TXAGGR) {
677 txtid = ATH_AN_2_TID(an, tid);
678 txtid->state |= AGGR_ADDBA_PROGRESS;
679 ath_tx_pause_tid(sc, txtid);
680 *ssn = txtid->seq_start;
681 }
682
683 return 0;
684 }
685
686 int ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
687 {
688 struct ath_node *an = (struct ath_node *)sta->drv_priv;
689 struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid);
690 struct ath_txq *txq = &sc->tx.txq[txtid->ac->qnum];
691 struct ath_buf *bf;
692 struct list_head bf_head;
693 INIT_LIST_HEAD(&bf_head);
694
695 if (txtid->state & AGGR_CLEANUP)
696 return 0;
697
698 if (!(txtid->state & AGGR_ADDBA_COMPLETE)) {
699 txtid->addba_exchangeattempts = 0;
700 return 0;
701 }
702
703 ath_tx_pause_tid(sc, txtid);
704
705 /* drop all software retried frames and mark this TID */
706 spin_lock_bh(&txq->axq_lock);
707 while (!list_empty(&txtid->buf_q)) {
708 bf = list_first_entry(&txtid->buf_q, struct ath_buf, list);
709 if (!bf_isretried(bf)) {
710 /*
711 * NB: it's based on the assumption that
712 * software retried frame will always stay
713 * at the head of software queue.
714 */
715 break;
716 }
717 list_move_tail(&bf->list, &bf_head);
718 ath_tx_update_baw(sc, txtid, bf->bf_seqno);
719 ath_tx_complete_buf(sc, bf, &bf_head, 0, 0);
720 }
721 spin_unlock_bh(&txq->axq_lock);
722
723 if (txtid->baw_head != txtid->baw_tail) {
724 txtid->state |= AGGR_CLEANUP;
725 } else {
726 txtid->state &= ~AGGR_ADDBA_COMPLETE;
727 txtid->addba_exchangeattempts = 0;
728 ath_tx_flush_tid(sc, txtid);
729 }
730
731 return 0;
732 }
733
734 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
735 {
736 struct ath_atx_tid *txtid;
737 struct ath_node *an;
738
739 an = (struct ath_node *)sta->drv_priv;
740
741 if (sc->sc_flags & SC_OP_TXAGGR) {
742 txtid = ATH_AN_2_TID(an, tid);
743 txtid->baw_size =
744 IEEE80211_MIN_AMPDU_BUF << sta->ht_cap.ampdu_factor;
745 txtid->state |= AGGR_ADDBA_COMPLETE;
746 txtid->state &= ~AGGR_ADDBA_PROGRESS;
747 ath_tx_resume_tid(sc, txtid);
748 }
749 }
750
751 bool ath_tx_aggr_check(struct ath_softc *sc, struct ath_node *an, u8 tidno)
752 {
753 struct ath_atx_tid *txtid;
754
755 if (!(sc->sc_flags & SC_OP_TXAGGR))
756 return false;
757
758 txtid = ATH_AN_2_TID(an, tidno);
759
760 if (!(txtid->state & AGGR_ADDBA_COMPLETE)) {
761 if (!(txtid->state & AGGR_ADDBA_PROGRESS) &&
762 (txtid->addba_exchangeattempts < ADDBA_EXCHANGE_ATTEMPTS)) {
763 txtid->addba_exchangeattempts++;
764 return true;
765 }
766 }
767
768 return false;
769 }
770
771 /********************/
772 /* Queue Management */
773 /********************/
774
775 static void ath_txq_drain_pending_buffers(struct ath_softc *sc,
776 struct ath_txq *txq)
777 {
778 struct ath_atx_ac *ac, *ac_tmp;
779 struct ath_atx_tid *tid, *tid_tmp;
780
781 list_for_each_entry_safe(ac, ac_tmp, &txq->axq_acq, list) {
782 list_del(&ac->list);
783 ac->sched = false;
784 list_for_each_entry_safe(tid, tid_tmp, &ac->tid_q, list) {
785 list_del(&tid->list);
786 tid->sched = false;
787 ath_tid_drain(sc, txq, tid);
788 }
789 }
790 }
791
792 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
793 {
794 struct ath_hw *ah = sc->sc_ah;
795 struct ath9k_tx_queue_info qi;
796 int qnum;
797
798 memset(&qi, 0, sizeof(qi));
799 qi.tqi_subtype = subtype;
800 qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT;
801 qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
802 qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT;
803 qi.tqi_physCompBuf = 0;
804
805 /*
806 * Enable interrupts only for EOL and DESC conditions.
807 * We mark tx descriptors to receive a DESC interrupt
808 * when a tx queue gets deep; otherwise waiting for the
809 * EOL to reap descriptors. Note that this is done to
810 * reduce interrupt load and this only defers reaping
811 * descriptors, never transmitting frames. Aside from
812 * reducing interrupts this also permits more concurrency.
813 * The only potential downside is if the tx queue backs
814 * up in which case the top half of the kernel may backup
815 * due to a lack of tx descriptors.
816 *
817 * The UAPSD queue is an exception, since we take a desc-
818 * based intr on the EOSP frames.
819 */
820 if (qtype == ATH9K_TX_QUEUE_UAPSD)
821 qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE;
822 else
823 qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE |
824 TXQ_FLAG_TXDESCINT_ENABLE;
825 qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi);
826 if (qnum == -1) {
827 /*
828 * NB: don't print a message, this happens
829 * normally on parts with too few tx queues
830 */
831 return NULL;
832 }
833 if (qnum >= ARRAY_SIZE(sc->tx.txq)) {
834 DPRINTF(sc, ATH_DBG_FATAL,
835 "qnum %u out of range, max %u!\n",
836 qnum, (unsigned int)ARRAY_SIZE(sc->tx.txq));
837 ath9k_hw_releasetxqueue(ah, qnum);
838 return NULL;
839 }
840 if (!ATH_TXQ_SETUP(sc, qnum)) {
841 struct ath_txq *txq = &sc->tx.txq[qnum];
842
843 txq->axq_qnum = qnum;
844 txq->axq_link = NULL;
845 INIT_LIST_HEAD(&txq->axq_q);
846 INIT_LIST_HEAD(&txq->axq_acq);
847 spin_lock_init(&txq->axq_lock);
848 txq->axq_depth = 0;
849 txq->axq_aggr_depth = 0;
850 txq->axq_totalqueued = 0;
851 txq->axq_linkbuf = NULL;
852 sc->tx.txqsetup |= 1<<qnum;
853 }
854 return &sc->tx.txq[qnum];
855 }
856
857 static int ath_tx_get_qnum(struct ath_softc *sc, int qtype, int haltype)
858 {
859 int qnum;
860
861 switch (qtype) {
862 case ATH9K_TX_QUEUE_DATA:
863 if (haltype >= ARRAY_SIZE(sc->tx.hwq_map)) {
864 DPRINTF(sc, ATH_DBG_FATAL,
865 "HAL AC %u out of range, max %zu!\n",
866 haltype, ARRAY_SIZE(sc->tx.hwq_map));
867 return -1;
868 }
869 qnum = sc->tx.hwq_map[haltype];
870 break;
871 case ATH9K_TX_QUEUE_BEACON:
872 qnum = sc->beacon.beaconq;
873 break;
874 case ATH9K_TX_QUEUE_CAB:
875 qnum = sc->beacon.cabq->axq_qnum;
876 break;
877 default:
878 qnum = -1;
879 }
880 return qnum;
881 }
882
883 struct ath_txq *ath_test_get_txq(struct ath_softc *sc, struct sk_buff *skb)
884 {
885 struct ath_txq *txq = NULL;
886 int qnum;
887
888 qnum = ath_get_hal_qnum(skb_get_queue_mapping(skb), sc);
889 txq = &sc->tx.txq[qnum];
890
891 spin_lock_bh(&txq->axq_lock);
892
893 if (txq->axq_depth >= (ATH_TXBUF - 20)) {
894 DPRINTF(sc, ATH_DBG_FATAL,
895 "TX queue: %d is full, depth: %d\n",
896 qnum, txq->axq_depth);
897 ieee80211_stop_queue(sc->hw, skb_get_queue_mapping(skb));
898 txq->stopped = 1;
899 spin_unlock_bh(&txq->axq_lock);
900 return NULL;
901 }
902
903 spin_unlock_bh(&txq->axq_lock);
904
905 return txq;
906 }
907
908 int ath_txq_update(struct ath_softc *sc, int qnum,
909 struct ath9k_tx_queue_info *qinfo)
910 {
911 struct ath_hw *ah = sc->sc_ah;
912 int error = 0;
913 struct ath9k_tx_queue_info qi;
914
915 if (qnum == sc->beacon.beaconq) {
916 /*
917 * XXX: for beacon queue, we just save the parameter.
918 * It will be picked up by ath_beaconq_config when
919 * it's necessary.
920 */
921 sc->beacon.beacon_qi = *qinfo;
922 return 0;
923 }
924
925 ASSERT(sc->tx.txq[qnum].axq_qnum == qnum);
926
927 ath9k_hw_get_txq_props(ah, qnum, &qi);
928 qi.tqi_aifs = qinfo->tqi_aifs;
929 qi.tqi_cwmin = qinfo->tqi_cwmin;
930 qi.tqi_cwmax = qinfo->tqi_cwmax;
931 qi.tqi_burstTime = qinfo->tqi_burstTime;
932 qi.tqi_readyTime = qinfo->tqi_readyTime;
933
934 if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) {
935 DPRINTF(sc, ATH_DBG_FATAL,
936 "Unable to update hardware queue %u!\n", qnum);
937 error = -EIO;
938 } else {
939 ath9k_hw_resettxqueue(ah, qnum);
940 }
941
942 return error;
943 }
944
945 int ath_cabq_update(struct ath_softc *sc)
946 {
947 struct ath9k_tx_queue_info qi;
948 int qnum = sc->beacon.cabq->axq_qnum;
949
950 ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi);
951 /*
952 * Ensure the readytime % is within the bounds.
953 */
954 if (sc->config.cabqReadytime < ATH9K_READY_TIME_LO_BOUND)
955 sc->config.cabqReadytime = ATH9K_READY_TIME_LO_BOUND;
956 else if (sc->config.cabqReadytime > ATH9K_READY_TIME_HI_BOUND)
957 sc->config.cabqReadytime = ATH9K_READY_TIME_HI_BOUND;
958
959 qi.tqi_readyTime = (sc->hw->conf.beacon_int *
960 sc->config.cabqReadytime) / 100;
961 ath_txq_update(sc, qnum, &qi);
962
963 return 0;
964 }
965
966 /*
967 * Drain a given TX queue (could be Beacon or Data)
968 *
969 * This assumes output has been stopped and
970 * we do not need to block ath_tx_tasklet.
971 */
972 void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq, bool retry_tx)
973 {
974 struct ath_buf *bf, *lastbf;
975 struct list_head bf_head;
976
977 INIT_LIST_HEAD(&bf_head);
978
979 for (;;) {
980 spin_lock_bh(&txq->axq_lock);
981
982 if (list_empty(&txq->axq_q)) {
983 txq->axq_link = NULL;
984 txq->axq_linkbuf = NULL;
985 spin_unlock_bh(&txq->axq_lock);
986 break;
987 }
988
989 bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
990
991 if (bf->bf_status & ATH_BUFSTATUS_STALE) {
992 list_del(&bf->list);
993 spin_unlock_bh(&txq->axq_lock);
994
995 spin_lock_bh(&sc->tx.txbuflock);
996 list_add_tail(&bf->list, &sc->tx.txbuf);
997 spin_unlock_bh(&sc->tx.txbuflock);
998 continue;
999 }
1000
1001 lastbf = bf->bf_lastbf;
1002 if (!retry_tx)
1003 lastbf->bf_desc->ds_txstat.ts_flags =
1004 ATH9K_TX_SW_ABORTED;
1005
1006 /* remove ath_buf's of the same mpdu from txq */
1007 list_cut_position(&bf_head, &txq->axq_q, &lastbf->list);
1008 txq->axq_depth--;
1009
1010 spin_unlock_bh(&txq->axq_lock);
1011
1012 if (bf_isampdu(bf))
1013 ath_tx_complete_aggr(sc, txq, bf, &bf_head, 0);
1014 else
1015 ath_tx_complete_buf(sc, bf, &bf_head, 0, 0);
1016 }
1017
1018 /* flush any pending frames if aggregation is enabled */
1019 if (sc->sc_flags & SC_OP_TXAGGR) {
1020 if (!retry_tx) {
1021 spin_lock_bh(&txq->axq_lock);
1022 ath_txq_drain_pending_buffers(sc, txq);
1023 spin_unlock_bh(&txq->axq_lock);
1024 }
1025 }
1026 }
1027
1028 void ath_drain_all_txq(struct ath_softc *sc, bool retry_tx)
1029 {
1030 struct ath_hw *ah = sc->sc_ah;
1031 struct ath_txq *txq;
1032 int i, npend = 0;
1033
1034 if (sc->sc_flags & SC_OP_INVALID)
1035 return;
1036
1037 /* Stop beacon queue */
1038 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
1039
1040 /* Stop data queues */
1041 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1042 if (ATH_TXQ_SETUP(sc, i)) {
1043 txq = &sc->tx.txq[i];
1044 ath9k_hw_stoptxdma(ah, txq->axq_qnum);
1045 npend += ath9k_hw_numtxpending(ah, txq->axq_qnum);
1046 }
1047 }
1048
1049 if (npend) {
1050 int r;
1051
1052 DPRINTF(sc, ATH_DBG_XMIT, "Unable to stop TxDMA. Reset HAL!\n");
1053
1054 spin_lock_bh(&sc->sc_resetlock);
1055 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, true);
1056 if (r)
1057 DPRINTF(sc, ATH_DBG_FATAL,
1058 "Unable to reset hardware; reset status %u\n",
1059 r);
1060 spin_unlock_bh(&sc->sc_resetlock);
1061 }
1062
1063 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1064 if (ATH_TXQ_SETUP(sc, i))
1065 ath_draintxq(sc, &sc->tx.txq[i], retry_tx);
1066 }
1067 }
1068
1069 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
1070 {
1071 ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum);
1072 sc->tx.txqsetup &= ~(1<<txq->axq_qnum);
1073 }
1074
1075 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq)
1076 {
1077 struct ath_atx_ac *ac;
1078 struct ath_atx_tid *tid;
1079
1080 if (list_empty(&txq->axq_acq))
1081 return;
1082
1083 ac = list_first_entry(&txq->axq_acq, struct ath_atx_ac, list);
1084 list_del(&ac->list);
1085 ac->sched = false;
1086
1087 do {
1088 if (list_empty(&ac->tid_q))
1089 return;
1090
1091 tid = list_first_entry(&ac->tid_q, struct ath_atx_tid, list);
1092 list_del(&tid->list);
1093 tid->sched = false;
1094
1095 if (tid->paused)
1096 continue;
1097
1098 if ((txq->axq_depth % 2) == 0)
1099 ath_tx_sched_aggr(sc, txq, tid);
1100
1101 /*
1102 * add tid to round-robin queue if more frames
1103 * are pending for the tid
1104 */
1105 if (!list_empty(&tid->buf_q))
1106 ath_tx_queue_tid(txq, tid);
1107
1108 break;
1109 } while (!list_empty(&ac->tid_q));
1110
1111 if (!list_empty(&ac->tid_q)) {
1112 if (!ac->sched) {
1113 ac->sched = true;
1114 list_add_tail(&ac->list, &txq->axq_acq);
1115 }
1116 }
1117 }
1118
1119 int ath_tx_setup(struct ath_softc *sc, int haltype)
1120 {
1121 struct ath_txq *txq;
1122
1123 if (haltype >= ARRAY_SIZE(sc->tx.hwq_map)) {
1124 DPRINTF(sc, ATH_DBG_FATAL,
1125 "HAL AC %u out of range, max %zu!\n",
1126 haltype, ARRAY_SIZE(sc->tx.hwq_map));
1127 return 0;
1128 }
1129 txq = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, haltype);
1130 if (txq != NULL) {
1131 sc->tx.hwq_map[haltype] = txq->axq_qnum;
1132 return 1;
1133 } else
1134 return 0;
1135 }
1136
1137 /***********/
1138 /* TX, DMA */
1139 /***********/
1140
1141 /*
1142 * Insert a chain of ath_buf (descriptors) on a txq and
1143 * assume the descriptors are already chained together by caller.
1144 */
1145 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
1146 struct list_head *head)
1147 {
1148 struct ath_hw *ah = sc->sc_ah;
1149 struct ath_buf *bf;
1150
1151 /*
1152 * Insert the frame on the outbound list and
1153 * pass it on to the hardware.
1154 */
1155
1156 if (list_empty(head))
1157 return;
1158
1159 bf = list_first_entry(head, struct ath_buf, list);
1160
1161 list_splice_tail_init(head, &txq->axq_q);
1162 txq->axq_depth++;
1163 txq->axq_totalqueued++;
1164 txq->axq_linkbuf = list_entry(txq->axq_q.prev, struct ath_buf, list);
1165
1166 DPRINTF(sc, ATH_DBG_QUEUE,
1167 "qnum: %d, txq depth: %d\n", txq->axq_qnum, txq->axq_depth);
1168
1169 if (txq->axq_link == NULL) {
1170 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
1171 DPRINTF(sc, ATH_DBG_XMIT,
1172 "TXDP[%u] = %llx (%p)\n",
1173 txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc);
1174 } else {
1175 *txq->axq_link = bf->bf_daddr;
1176 DPRINTF(sc, ATH_DBG_XMIT, "link[%u] (%p)=%llx (%p)\n",
1177 txq->axq_qnum, txq->axq_link,
1178 ito64(bf->bf_daddr), bf->bf_desc);
1179 }
1180 txq->axq_link = &(bf->bf_lastbf->bf_desc->ds_link);
1181 ath9k_hw_txstart(ah, txq->axq_qnum);
1182 }
1183
1184 static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc)
1185 {
1186 struct ath_buf *bf = NULL;
1187
1188 spin_lock_bh(&sc->tx.txbuflock);
1189
1190 if (unlikely(list_empty(&sc->tx.txbuf))) {
1191 spin_unlock_bh(&sc->tx.txbuflock);
1192 return NULL;
1193 }
1194
1195 bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list);
1196 list_del(&bf->list);
1197
1198 spin_unlock_bh(&sc->tx.txbuflock);
1199
1200 return bf;
1201 }
1202
1203 static void ath_tx_send_ampdu(struct ath_softc *sc, struct ath_atx_tid *tid,
1204 struct list_head *bf_head,
1205 struct ath_tx_control *txctl)
1206 {
1207 struct ath_buf *bf;
1208
1209 bf = list_first_entry(bf_head, struct ath_buf, list);
1210 bf->bf_state.bf_type |= BUF_AMPDU;
1211
1212 /*
1213 * Do not queue to h/w when any of the following conditions is true:
1214 * - there are pending frames in software queue
1215 * - the TID is currently paused for ADDBA/BAR request
1216 * - seqno is not within block-ack window
1217 * - h/w queue depth exceeds low water mark
1218 */
1219 if (!list_empty(&tid->buf_q) || tid->paused ||
1220 !BAW_WITHIN(tid->seq_start, tid->baw_size, bf->bf_seqno) ||
1221 txctl->txq->axq_depth >= ATH_AGGR_MIN_QDEPTH) {
1222 /*
1223 * Add this frame to software queue for scheduling later
1224 * for aggregation.
1225 */
1226 list_move_tail(&bf->list, &tid->buf_q);
1227 ath_tx_queue_tid(txctl->txq, tid);
1228 return;
1229 }
1230
1231 /* Add sub-frame to BAW */
1232 ath_tx_addto_baw(sc, tid, bf);
1233
1234 /* Queue to h/w without aggregation */
1235 bf->bf_nframes = 1;
1236 bf->bf_lastbf = bf;
1237 ath_buf_set_rate(sc, bf);
1238 ath_tx_txqaddbuf(sc, txctl->txq, bf_head);
1239 }
1240
1241 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
1242 struct ath_atx_tid *tid,
1243 struct list_head *bf_head)
1244 {
1245 struct ath_buf *bf;
1246
1247 bf = list_first_entry(bf_head, struct ath_buf, list);
1248 bf->bf_state.bf_type &= ~BUF_AMPDU;
1249
1250 /* update starting sequence number for subsequent ADDBA request */
1251 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
1252
1253 bf->bf_nframes = 1;
1254 bf->bf_lastbf = bf;
1255 ath_buf_set_rate(sc, bf);
1256 ath_tx_txqaddbuf(sc, txq, bf_head);
1257 }
1258
1259 static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb)
1260 {
1261 struct ieee80211_hdr *hdr;
1262 enum ath9k_pkt_type htype;
1263 __le16 fc;
1264
1265 hdr = (struct ieee80211_hdr *)skb->data;
1266 fc = hdr->frame_control;
1267
1268 if (ieee80211_is_beacon(fc))
1269 htype = ATH9K_PKT_TYPE_BEACON;
1270 else if (ieee80211_is_probe_resp(fc))
1271 htype = ATH9K_PKT_TYPE_PROBE_RESP;
1272 else if (ieee80211_is_atim(fc))
1273 htype = ATH9K_PKT_TYPE_ATIM;
1274 else if (ieee80211_is_pspoll(fc))
1275 htype = ATH9K_PKT_TYPE_PSPOLL;
1276 else
1277 htype = ATH9K_PKT_TYPE_NORMAL;
1278
1279 return htype;
1280 }
1281
1282 static bool is_pae(struct sk_buff *skb)
1283 {
1284 struct ieee80211_hdr *hdr;
1285 __le16 fc;
1286
1287 hdr = (struct ieee80211_hdr *)skb->data;
1288 fc = hdr->frame_control;
1289
1290 if (ieee80211_is_data(fc)) {
1291 if (ieee80211_is_nullfunc(fc) ||
1292 /* Port Access Entity (IEEE 802.1X) */
1293 (skb->protocol == cpu_to_be16(ETH_P_PAE))) {
1294 return true;
1295 }
1296 }
1297
1298 return false;
1299 }
1300
1301 static int get_hw_crypto_keytype(struct sk_buff *skb)
1302 {
1303 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1304
1305 if (tx_info->control.hw_key) {
1306 if (tx_info->control.hw_key->alg == ALG_WEP)
1307 return ATH9K_KEY_TYPE_WEP;
1308 else if (tx_info->control.hw_key->alg == ALG_TKIP)
1309 return ATH9K_KEY_TYPE_TKIP;
1310 else if (tx_info->control.hw_key->alg == ALG_CCMP)
1311 return ATH9K_KEY_TYPE_AES;
1312 }
1313
1314 return ATH9K_KEY_TYPE_CLEAR;
1315 }
1316
1317 static void assign_aggr_tid_seqno(struct sk_buff *skb,
1318 struct ath_buf *bf)
1319 {
1320 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1321 struct ieee80211_hdr *hdr;
1322 struct ath_node *an;
1323 struct ath_atx_tid *tid;
1324 __le16 fc;
1325 u8 *qc;
1326
1327 if (!tx_info->control.sta)
1328 return;
1329
1330 an = (struct ath_node *)tx_info->control.sta->drv_priv;
1331 hdr = (struct ieee80211_hdr *)skb->data;
1332 fc = hdr->frame_control;
1333
1334 if (ieee80211_is_data_qos(fc)) {
1335 qc = ieee80211_get_qos_ctl(hdr);
1336 bf->bf_tidno = qc[0] & 0xf;
1337 }
1338
1339 /*
1340 * For HT capable stations, we save tidno for later use.
1341 * We also override seqno set by upper layer with the one
1342 * in tx aggregation state.
1343 *
1344 * If fragmentation is on, the sequence number is
1345 * not overridden, since it has been
1346 * incremented by the fragmentation routine.
1347 *
1348 * FIXME: check if the fragmentation threshold exceeds
1349 * IEEE80211 max.
1350 */
1351 tid = ATH_AN_2_TID(an, bf->bf_tidno);
1352 hdr->seq_ctrl = cpu_to_le16(tid->seq_next <<
1353 IEEE80211_SEQ_SEQ_SHIFT);
1354 bf->bf_seqno = tid->seq_next;
1355 INCR(tid->seq_next, IEEE80211_SEQ_MAX);
1356 }
1357
1358 static int setup_tx_flags(struct ath_softc *sc, struct sk_buff *skb,
1359 struct ath_txq *txq)
1360 {
1361 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1362 int flags = 0;
1363
1364 flags |= ATH9K_TXDESC_CLRDMASK; /* needed for crypto errors */
1365 flags |= ATH9K_TXDESC_INTREQ;
1366
1367 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
1368 flags |= ATH9K_TXDESC_NOACK;
1369
1370 return flags;
1371 }
1372
1373 /*
1374 * rix - rate index
1375 * pktlen - total bytes (delims + data + fcs + pads + pad delims)
1376 * width - 0 for 20 MHz, 1 for 40 MHz
1377 * half_gi - to use 4us v/s 3.6 us for symbol time
1378 */
1379 static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, struct ath_buf *bf,
1380 int width, int half_gi, bool shortPreamble)
1381 {
1382 struct ath_rate_table *rate_table = sc->cur_rate_table;
1383 u32 nbits, nsymbits, duration, nsymbols;
1384 u8 rc;
1385 int streams, pktlen;
1386
1387 pktlen = bf_isaggr(bf) ? bf->bf_al : bf->bf_frmlen;
1388 rc = rate_table->info[rix].ratecode;
1389
1390 /* for legacy rates, use old function to compute packet duration */
1391 if (!IS_HT_RATE(rc))
1392 return ath9k_hw_computetxtime(sc->sc_ah, rate_table, pktlen,
1393 rix, shortPreamble);
1394
1395 /* find number of symbols: PLCP + data */
1396 nbits = (pktlen << 3) + OFDM_PLCP_BITS;
1397 nsymbits = bits_per_symbol[HT_RC_2_MCS(rc)][width];
1398 nsymbols = (nbits + nsymbits - 1) / nsymbits;
1399
1400 if (!half_gi)
1401 duration = SYMBOL_TIME(nsymbols);
1402 else
1403 duration = SYMBOL_TIME_HALFGI(nsymbols);
1404
1405 /* addup duration for legacy/ht training and signal fields */
1406 streams = HT_RC_2_STREAMS(rc);
1407 duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
1408
1409 return duration;
1410 }
1411
1412 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf)
1413 {
1414 struct ath_rate_table *rt = sc->cur_rate_table;
1415 struct ath9k_11n_rate_series series[4];
1416 struct sk_buff *skb;
1417 struct ieee80211_tx_info *tx_info;
1418 struct ieee80211_tx_rate *rates;
1419 struct ieee80211_hdr *hdr;
1420 int i, flags = 0;
1421 u8 rix = 0, ctsrate = 0;
1422 bool is_pspoll;
1423
1424 memset(series, 0, sizeof(struct ath9k_11n_rate_series) * 4);
1425
1426 skb = (struct sk_buff *)bf->bf_mpdu;
1427 tx_info = IEEE80211_SKB_CB(skb);
1428 rates = tx_info->control.rates;
1429 hdr = (struct ieee80211_hdr *)skb->data;
1430 is_pspoll = ieee80211_is_pspoll(hdr->frame_control);
1431
1432 /*
1433 * We check if Short Preamble is needed for the CTS rate by
1434 * checking the BSS's global flag.
1435 * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used.
1436 */
1437 if (sc->sc_flags & SC_OP_PREAMBLE_SHORT)
1438 ctsrate = rt->info[tx_info->control.rts_cts_rate_idx].ratecode |
1439 rt->info[tx_info->control.rts_cts_rate_idx].short_preamble;
1440 else
1441 ctsrate = rt->info[tx_info->control.rts_cts_rate_idx].ratecode;
1442
1443 /*
1444 * ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive.
1445 * Check the first rate in the series to decide whether RTS/CTS
1446 * or CTS-to-self has to be used.
1447 */
1448 if (rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT)
1449 flags = ATH9K_TXDESC_CTSENA;
1450 else if (rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS)
1451 flags = ATH9K_TXDESC_RTSENA;
1452
1453 /* FIXME: Handle aggregation protection */
1454 if (sc->config.ath_aggr_prot &&
1455 (!bf_isaggr(bf) || (bf_isaggr(bf) && bf->bf_al < 8192))) {
1456 flags = ATH9K_TXDESC_RTSENA;
1457 }
1458
1459 /* For AR5416 - RTS cannot be followed by a frame larger than 8K */
1460 if (bf_isaggr(bf) && (bf->bf_al > sc->sc_ah->caps.rts_aggr_limit))
1461 flags &= ~(ATH9K_TXDESC_RTSENA);
1462
1463 for (i = 0; i < 4; i++) {
1464 if (!rates[i].count || (rates[i].idx < 0))
1465 continue;
1466
1467 rix = rates[i].idx;
1468 series[i].Tries = rates[i].count;
1469 series[i].ChSel = sc->tx_chainmask;
1470
1471 if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
1472 series[i].Rate = rt->info[rix].ratecode |
1473 rt->info[rix].short_preamble;
1474 else
1475 series[i].Rate = rt->info[rix].ratecode;
1476
1477 if (rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS)
1478 series[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1479 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
1480 series[i].RateFlags |= ATH9K_RATESERIES_2040;
1481 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
1482 series[i].RateFlags |= ATH9K_RATESERIES_HALFGI;
1483
1484 series[i].PktDuration = ath_pkt_duration(sc, rix, bf,
1485 (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH) != 0,
1486 (rates[i].flags & IEEE80211_TX_RC_SHORT_GI),
1487 (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE));
1488 }
1489
1490 /* set dur_update_en for l-sig computation except for PS-Poll frames */
1491 ath9k_hw_set11n_ratescenario(sc->sc_ah, bf->bf_desc,
1492 bf->bf_lastbf->bf_desc,
1493 !is_pspoll, ctsrate,
1494 0, series, 4, flags);
1495
1496 if (sc->config.ath_aggr_prot && flags)
1497 ath9k_hw_set11n_burstduration(sc->sc_ah, bf->bf_desc, 8192);
1498 }
1499
1500 static int ath_tx_setup_buffer(struct ieee80211_hw *hw, struct ath_buf *bf,
1501 struct sk_buff *skb,
1502 struct ath_tx_control *txctl)
1503 {
1504 struct ath_wiphy *aphy = hw->priv;
1505 struct ath_softc *sc = aphy->sc;
1506 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1507 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1508 struct ath_tx_info_priv *tx_info_priv;
1509 int hdrlen;
1510 __le16 fc;
1511
1512 tx_info_priv = kzalloc(sizeof(*tx_info_priv), GFP_ATOMIC);
1513 if (unlikely(!tx_info_priv))
1514 return -ENOMEM;
1515 tx_info->rate_driver_data[0] = tx_info_priv;
1516 tx_info_priv->aphy = aphy;
1517 tx_info_priv->frame_type = txctl->frame_type;
1518 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1519 fc = hdr->frame_control;
1520
1521 ATH_TXBUF_RESET(bf);
1522
1523 bf->bf_frmlen = skb->len + FCS_LEN - (hdrlen & 3);
1524
1525 if ((conf_is_ht(&sc->hw->conf) && !is_pae(skb) &&
1526 (tx_info->flags & IEEE80211_TX_CTL_AMPDU)))
1527 bf->bf_state.bf_type |= BUF_HT;
1528
1529 bf->bf_flags = setup_tx_flags(sc, skb, txctl->txq);
1530
1531 bf->bf_keytype = get_hw_crypto_keytype(skb);
1532 if (bf->bf_keytype != ATH9K_KEY_TYPE_CLEAR) {
1533 bf->bf_frmlen += tx_info->control.hw_key->icv_len;
1534 bf->bf_keyix = tx_info->control.hw_key->hw_key_idx;
1535 } else {
1536 bf->bf_keyix = ATH9K_TXKEYIX_INVALID;
1537 }
1538
1539 if (ieee80211_is_data_qos(fc) && (sc->sc_flags & SC_OP_TXAGGR))
1540 assign_aggr_tid_seqno(skb, bf);
1541
1542 bf->bf_mpdu = skb;
1543
1544 bf->bf_dmacontext = dma_map_single(sc->dev, skb->data,
1545 skb->len, DMA_TO_DEVICE);
1546 if (unlikely(dma_mapping_error(sc->dev, bf->bf_dmacontext))) {
1547 bf->bf_mpdu = NULL;
1548 DPRINTF(sc, ATH_DBG_CONFIG,
1549 "dma_mapping_error() on TX\n");
1550 return -ENOMEM;
1551 }
1552
1553 bf->bf_buf_addr = bf->bf_dmacontext;
1554 return 0;
1555 }
1556
1557 /* FIXME: tx power */
1558 static void ath_tx_start_dma(struct ath_softc *sc, struct ath_buf *bf,
1559 struct ath_tx_control *txctl)
1560 {
1561 struct sk_buff *skb = (struct sk_buff *)bf->bf_mpdu;
1562 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1563 struct ath_node *an = NULL;
1564 struct list_head bf_head;
1565 struct ath_desc *ds;
1566 struct ath_atx_tid *tid;
1567 struct ath_hw *ah = sc->sc_ah;
1568 int frm_type;
1569
1570 frm_type = get_hw_packet_type(skb);
1571
1572 INIT_LIST_HEAD(&bf_head);
1573 list_add_tail(&bf->list, &bf_head);
1574
1575 ds = bf->bf_desc;
1576 ds->ds_link = 0;
1577 ds->ds_data = bf->bf_buf_addr;
1578
1579 ath9k_hw_set11n_txdesc(ah, ds, bf->bf_frmlen, frm_type, MAX_RATE_POWER,
1580 bf->bf_keyix, bf->bf_keytype, bf->bf_flags);
1581
1582 ath9k_hw_filltxdesc(ah, ds,
1583 skb->len, /* segment length */
1584 true, /* first segment */
1585 true, /* last segment */
1586 ds); /* first descriptor */
1587
1588 spin_lock_bh(&txctl->txq->axq_lock);
1589
1590 if (bf_isht(bf) && (sc->sc_flags & SC_OP_TXAGGR) &&
1591 tx_info->control.sta) {
1592 an = (struct ath_node *)tx_info->control.sta->drv_priv;
1593 tid = ATH_AN_2_TID(an, bf->bf_tidno);
1594
1595 if (ath_aggr_query(sc, an, bf->bf_tidno)) {
1596 /*
1597 * Try aggregation if it's a unicast data frame
1598 * and the destination is HT capable.
1599 */
1600 ath_tx_send_ampdu(sc, tid, &bf_head, txctl);
1601 } else {
1602 /*
1603 * Send this frame as regular when ADDBA
1604 * exchange is neither complete nor pending.
1605 */
1606 ath_tx_send_normal(sc, txctl->txq,
1607 tid, &bf_head);
1608 }
1609 } else {
1610 bf->bf_lastbf = bf;
1611 bf->bf_nframes = 1;
1612
1613 ath_buf_set_rate(sc, bf);
1614 ath_tx_txqaddbuf(sc, txctl->txq, &bf_head);
1615 }
1616
1617 spin_unlock_bh(&txctl->txq->axq_lock);
1618 }
1619
1620 /* Upon failure caller should free skb */
1621 int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
1622 struct ath_tx_control *txctl)
1623 {
1624 struct ath_wiphy *aphy = hw->priv;
1625 struct ath_softc *sc = aphy->sc;
1626 struct ath_buf *bf;
1627 int r;
1628
1629 bf = ath_tx_get_buffer(sc);
1630 if (!bf) {
1631 DPRINTF(sc, ATH_DBG_XMIT, "TX buffers are full\n");
1632 return -1;
1633 }
1634
1635 r = ath_tx_setup_buffer(hw, bf, skb, txctl);
1636 if (unlikely(r)) {
1637 struct ath_txq *txq = txctl->txq;
1638
1639 DPRINTF(sc, ATH_DBG_FATAL, "TX mem alloc failure\n");
1640
1641 /* upon ath_tx_processq() this TX queue will be resumed, we
1642 * guarantee this will happen by knowing beforehand that
1643 * we will at least have to run TX completionon one buffer
1644 * on the queue */
1645 spin_lock_bh(&txq->axq_lock);
1646 if (sc->tx.txq[txq->axq_qnum].axq_depth > 1) {
1647 ieee80211_stop_queue(sc->hw,
1648 skb_get_queue_mapping(skb));
1649 txq->stopped = 1;
1650 }
1651 spin_unlock_bh(&txq->axq_lock);
1652
1653 spin_lock_bh(&sc->tx.txbuflock);
1654 list_add_tail(&bf->list, &sc->tx.txbuf);
1655 spin_unlock_bh(&sc->tx.txbuflock);
1656
1657 return r;
1658 }
1659
1660 ath_tx_start_dma(sc, bf, txctl);
1661
1662 return 0;
1663 }
1664
1665 void ath_tx_cabq(struct ieee80211_hw *hw, struct sk_buff *skb)
1666 {
1667 struct ath_wiphy *aphy = hw->priv;
1668 struct ath_softc *sc = aphy->sc;
1669 int hdrlen, padsize;
1670 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1671 struct ath_tx_control txctl;
1672
1673 memset(&txctl, 0, sizeof(struct ath_tx_control));
1674
1675 /*
1676 * As a temporary workaround, assign seq# here; this will likely need
1677 * to be cleaned up to work better with Beacon transmission and virtual
1678 * BSSes.
1679 */
1680 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1681 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
1682 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
1683 sc->tx.seq_no += 0x10;
1684 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
1685 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
1686 }
1687
1688 /* Add the padding after the header if this is not already done */
1689 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1690 if (hdrlen & 3) {
1691 padsize = hdrlen % 4;
1692 if (skb_headroom(skb) < padsize) {
1693 DPRINTF(sc, ATH_DBG_XMIT, "TX CABQ padding failed\n");
1694 dev_kfree_skb_any(skb);
1695 return;
1696 }
1697 skb_push(skb, padsize);
1698 memmove(skb->data, skb->data + padsize, hdrlen);
1699 }
1700
1701 txctl.txq = sc->beacon.cabq;
1702
1703 DPRINTF(sc, ATH_DBG_XMIT, "transmitting CABQ packet, skb: %p\n", skb);
1704
1705 if (ath_tx_start(hw, skb, &txctl) != 0) {
1706 DPRINTF(sc, ATH_DBG_XMIT, "CABQ TX failed\n");
1707 goto exit;
1708 }
1709
1710 return;
1711 exit:
1712 dev_kfree_skb_any(skb);
1713 }
1714
1715 /*****************/
1716 /* TX Completion */
1717 /*****************/
1718
1719 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
1720 struct ath_xmit_status *tx_status)
1721 {
1722 struct ieee80211_hw *hw = sc->hw;
1723 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1724 struct ath_tx_info_priv *tx_info_priv = ATH_TX_INFO_PRIV(tx_info);
1725 int hdrlen, padsize;
1726 int frame_type = ATH9K_NOT_INTERNAL;
1727
1728 DPRINTF(sc, ATH_DBG_XMIT, "TX complete: skb: %p\n", skb);
1729
1730 if (tx_info_priv) {
1731 hw = tx_info_priv->aphy->hw;
1732 frame_type = tx_info_priv->frame_type;
1733 }
1734
1735 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK ||
1736 tx_info->flags & IEEE80211_TX_STAT_TX_FILTERED) {
1737 kfree(tx_info_priv);
1738 tx_info->rate_driver_data[0] = NULL;
1739 }
1740
1741 if (tx_status->flags & ATH_TX_BAR) {
1742 tx_info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
1743 tx_status->flags &= ~ATH_TX_BAR;
1744 }
1745
1746 if (!(tx_status->flags & (ATH_TX_ERROR | ATH_TX_XRETRY))) {
1747 /* Frame was ACKed */
1748 tx_info->flags |= IEEE80211_TX_STAT_ACK;
1749 }
1750
1751 tx_info->status.rates[0].count = tx_status->retries + 1;
1752
1753 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1754 padsize = hdrlen & 3;
1755 if (padsize && hdrlen >= 24) {
1756 /*
1757 * Remove MAC header padding before giving the frame back to
1758 * mac80211.
1759 */
1760 memmove(skb->data + padsize, skb->data, hdrlen);
1761 skb_pull(skb, padsize);
1762 }
1763
1764 if (frame_type == ATH9K_NOT_INTERNAL)
1765 ieee80211_tx_status(hw, skb);
1766 else
1767 ath9k_tx_status(hw, skb);
1768 }
1769
1770 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
1771 struct list_head *bf_q,
1772 int txok, int sendbar)
1773 {
1774 struct sk_buff *skb = bf->bf_mpdu;
1775 struct ath_xmit_status tx_status;
1776 unsigned long flags;
1777
1778 /*
1779 * Set retry information.
1780 * NB: Don't use the information in the descriptor, because the frame
1781 * could be software retried.
1782 */
1783 tx_status.retries = bf->bf_retries;
1784 tx_status.flags = 0;
1785
1786 if (sendbar)
1787 tx_status.flags = ATH_TX_BAR;
1788
1789 if (!txok) {
1790 tx_status.flags |= ATH_TX_ERROR;
1791
1792 if (bf_isxretried(bf))
1793 tx_status.flags |= ATH_TX_XRETRY;
1794 }
1795
1796 dma_unmap_single(sc->dev, bf->bf_dmacontext, skb->len, DMA_TO_DEVICE);
1797 ath_tx_complete(sc, skb, &tx_status);
1798
1799 /*
1800 * Return the list of ath_buf of this mpdu to free queue
1801 */
1802 spin_lock_irqsave(&sc->tx.txbuflock, flags);
1803 list_splice_tail_init(bf_q, &sc->tx.txbuf);
1804 spin_unlock_irqrestore(&sc->tx.txbuflock, flags);
1805 }
1806
1807 static int ath_tx_num_badfrms(struct ath_softc *sc, struct ath_buf *bf,
1808 int txok)
1809 {
1810 struct ath_buf *bf_last = bf->bf_lastbf;
1811 struct ath_desc *ds = bf_last->bf_desc;
1812 u16 seq_st = 0;
1813 u32 ba[WME_BA_BMP_SIZE >> 5];
1814 int ba_index;
1815 int nbad = 0;
1816 int isaggr = 0;
1817
1818 if (ds->ds_txstat.ts_flags == ATH9K_TX_SW_ABORTED)
1819 return 0;
1820
1821 isaggr = bf_isaggr(bf);
1822 if (isaggr) {
1823 seq_st = ATH_DS_BA_SEQ(ds);
1824 memcpy(ba, ATH_DS_BA_BITMAP(ds), WME_BA_BMP_SIZE >> 3);
1825 }
1826
1827 while (bf) {
1828 ba_index = ATH_BA_INDEX(seq_st, bf->bf_seqno);
1829 if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index)))
1830 nbad++;
1831
1832 bf = bf->bf_next;
1833 }
1834
1835 return nbad;
1836 }
1837
1838 static void ath_tx_rc_status(struct ath_buf *bf, struct ath_desc *ds, int nbad)
1839 {
1840 struct sk_buff *skb = (struct sk_buff *)bf->bf_mpdu;
1841 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1842 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1843 struct ath_tx_info_priv *tx_info_priv = ATH_TX_INFO_PRIV(tx_info);
1844
1845 tx_info_priv->update_rc = false;
1846 if (ds->ds_txstat.ts_status & ATH9K_TXERR_FILT)
1847 tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
1848
1849 if ((ds->ds_txstat.ts_status & ATH9K_TXERR_FILT) == 0 &&
1850 (bf->bf_flags & ATH9K_TXDESC_NOACK) == 0) {
1851 if (ieee80211_is_data(hdr->frame_control)) {
1852 memcpy(&tx_info_priv->tx, &ds->ds_txstat,
1853 sizeof(tx_info_priv->tx));
1854 tx_info_priv->n_frames = bf->bf_nframes;
1855 tx_info_priv->n_bad_frames = nbad;
1856 tx_info_priv->update_rc = true;
1857 }
1858 }
1859 }
1860
1861 static void ath_wake_mac80211_queue(struct ath_softc *sc, struct ath_txq *txq)
1862 {
1863 int qnum;
1864
1865 spin_lock_bh(&txq->axq_lock);
1866 if (txq->stopped &&
1867 sc->tx.txq[txq->axq_qnum].axq_depth <= (ATH_TXBUF - 20)) {
1868 qnum = ath_get_mac80211_qnum(txq->axq_qnum, sc);
1869 if (qnum != -1) {
1870 ieee80211_wake_queue(sc->hw, qnum);
1871 txq->stopped = 0;
1872 }
1873 }
1874 spin_unlock_bh(&txq->axq_lock);
1875 }
1876
1877 static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
1878 {
1879 struct ath_hw *ah = sc->sc_ah;
1880 struct ath_buf *bf, *lastbf, *bf_held = NULL;
1881 struct list_head bf_head;
1882 struct ath_desc *ds;
1883 int txok, nbad = 0;
1884 int status;
1885
1886 DPRINTF(sc, ATH_DBG_QUEUE, "tx queue %d (%x), link %p\n",
1887 txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum),
1888 txq->axq_link);
1889
1890 for (;;) {
1891 spin_lock_bh(&txq->axq_lock);
1892 if (list_empty(&txq->axq_q)) {
1893 txq->axq_link = NULL;
1894 txq->axq_linkbuf = NULL;
1895 spin_unlock_bh(&txq->axq_lock);
1896 break;
1897 }
1898 bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
1899
1900 /*
1901 * There is a race condition that a BH gets scheduled
1902 * after sw writes TxE and before hw re-load the last
1903 * descriptor to get the newly chained one.
1904 * Software must keep the last DONE descriptor as a
1905 * holding descriptor - software does so by marking
1906 * it with the STALE flag.
1907 */
1908 bf_held = NULL;
1909 if (bf->bf_status & ATH_BUFSTATUS_STALE) {
1910 bf_held = bf;
1911 if (list_is_last(&bf_held->list, &txq->axq_q)) {
1912 txq->axq_link = NULL;
1913 txq->axq_linkbuf = NULL;
1914 spin_unlock_bh(&txq->axq_lock);
1915
1916 /*
1917 * The holding descriptor is the last
1918 * descriptor in queue. It's safe to remove
1919 * the last holding descriptor in BH context.
1920 */
1921 spin_lock_bh(&sc->tx.txbuflock);
1922 list_move_tail(&bf_held->list, &sc->tx.txbuf);
1923 spin_unlock_bh(&sc->tx.txbuflock);
1924
1925 break;
1926 } else {
1927 bf = list_entry(bf_held->list.next,
1928 struct ath_buf, list);
1929 }
1930 }
1931
1932 lastbf = bf->bf_lastbf;
1933 ds = lastbf->bf_desc;
1934
1935 status = ath9k_hw_txprocdesc(ah, ds);
1936 if (status == -EINPROGRESS) {
1937 spin_unlock_bh(&txq->axq_lock);
1938 break;
1939 }
1940 if (bf->bf_desc == txq->axq_lastdsWithCTS)
1941 txq->axq_lastdsWithCTS = NULL;
1942 if (ds == txq->axq_gatingds)
1943 txq->axq_gatingds = NULL;
1944
1945 /*
1946 * Remove ath_buf's of the same transmit unit from txq,
1947 * however leave the last descriptor back as the holding
1948 * descriptor for hw.
1949 */
1950 lastbf->bf_status |= ATH_BUFSTATUS_STALE;
1951 INIT_LIST_HEAD(&bf_head);
1952 if (!list_is_singular(&lastbf->list))
1953 list_cut_position(&bf_head,
1954 &txq->axq_q, lastbf->list.prev);
1955
1956 txq->axq_depth--;
1957 if (bf_isaggr(bf))
1958 txq->axq_aggr_depth--;
1959
1960 txok = (ds->ds_txstat.ts_status == 0);
1961 spin_unlock_bh(&txq->axq_lock);
1962
1963 if (bf_held) {
1964 spin_lock_bh(&sc->tx.txbuflock);
1965 list_move_tail(&bf_held->list, &sc->tx.txbuf);
1966 spin_unlock_bh(&sc->tx.txbuflock);
1967 }
1968
1969 if (!bf_isampdu(bf)) {
1970 /*
1971 * This frame is sent out as a single frame.
1972 * Use hardware retry status for this frame.
1973 */
1974 bf->bf_retries = ds->ds_txstat.ts_longretry;
1975 if (ds->ds_txstat.ts_status & ATH9K_TXERR_XRETRY)
1976 bf->bf_state.bf_type |= BUF_XRETRY;
1977 nbad = 0;
1978 } else {
1979 nbad = ath_tx_num_badfrms(sc, bf, txok);
1980 }
1981
1982 ath_tx_rc_status(bf, ds, nbad);
1983
1984 if (bf_isampdu(bf))
1985 ath_tx_complete_aggr(sc, txq, bf, &bf_head, txok);
1986 else
1987 ath_tx_complete_buf(sc, bf, &bf_head, txok, 0);
1988
1989 ath_wake_mac80211_queue(sc, txq);
1990
1991 spin_lock_bh(&txq->axq_lock);
1992 if (sc->sc_flags & SC_OP_TXAGGR)
1993 ath_txq_schedule(sc, txq);
1994 spin_unlock_bh(&txq->axq_lock);
1995 }
1996 }
1997
1998
1999 void ath_tx_tasklet(struct ath_softc *sc)
2000 {
2001 int i;
2002 u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1);
2003
2004 ath9k_hw_gettxintrtxqs(sc->sc_ah, &qcumask);
2005
2006 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2007 if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i)))
2008 ath_tx_processq(sc, &sc->tx.txq[i]);
2009 }
2010 }
2011
2012 /*****************/
2013 /* Init, Cleanup */
2014 /*****************/
2015
2016 int ath_tx_init(struct ath_softc *sc, int nbufs)
2017 {
2018 int error = 0;
2019
2020 do {
2021 spin_lock_init(&sc->tx.txbuflock);
2022
2023 error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf,
2024 "tx", nbufs, 1);
2025 if (error != 0) {
2026 DPRINTF(sc, ATH_DBG_FATAL,
2027 "Failed to allocate tx descriptors: %d\n",
2028 error);
2029 break;
2030 }
2031
2032 error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf,
2033 "beacon", ATH_BCBUF, 1);
2034 if (error != 0) {
2035 DPRINTF(sc, ATH_DBG_FATAL,
2036 "Failed to allocate beacon descriptors: %d\n",
2037 error);
2038 break;
2039 }
2040
2041 } while (0);
2042
2043 if (error != 0)
2044 ath_tx_cleanup(sc);
2045
2046 return error;
2047 }
2048
2049 int ath_tx_cleanup(struct ath_softc *sc)
2050 {
2051 if (sc->beacon.bdma.dd_desc_len != 0)
2052 ath_descdma_cleanup(sc, &sc->beacon.bdma, &sc->beacon.bbuf);
2053
2054 if (sc->tx.txdma.dd_desc_len != 0)
2055 ath_descdma_cleanup(sc, &sc->tx.txdma, &sc->tx.txbuf);
2056
2057 return 0;
2058 }
2059
2060 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an)
2061 {
2062 struct ath_atx_tid *tid;
2063 struct ath_atx_ac *ac;
2064 int tidno, acno;
2065
2066 for (tidno = 0, tid = &an->tid[tidno];
2067 tidno < WME_NUM_TID;
2068 tidno++, tid++) {
2069 tid->an = an;
2070 tid->tidno = tidno;
2071 tid->seq_start = tid->seq_next = 0;
2072 tid->baw_size = WME_MAX_BA;
2073 tid->baw_head = tid->baw_tail = 0;
2074 tid->sched = false;
2075 tid->paused = false;
2076 tid->state &= ~AGGR_CLEANUP;
2077 INIT_LIST_HEAD(&tid->buf_q);
2078 acno = TID_TO_WME_AC(tidno);
2079 tid->ac = &an->ac[acno];
2080 tid->state &= ~AGGR_ADDBA_COMPLETE;
2081 tid->state &= ~AGGR_ADDBA_PROGRESS;
2082 tid->addba_exchangeattempts = 0;
2083 }
2084
2085 for (acno = 0, ac = &an->ac[acno];
2086 acno < WME_NUM_AC; acno++, ac++) {
2087 ac->sched = false;
2088 INIT_LIST_HEAD(&ac->tid_q);
2089
2090 switch (acno) {
2091 case WME_AC_BE:
2092 ac->qnum = ath_tx_get_qnum(sc,
2093 ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BE);
2094 break;
2095 case WME_AC_BK:
2096 ac->qnum = ath_tx_get_qnum(sc,
2097 ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BK);
2098 break;
2099 case WME_AC_VI:
2100 ac->qnum = ath_tx_get_qnum(sc,
2101 ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_VI);
2102 break;
2103 case WME_AC_VO:
2104 ac->qnum = ath_tx_get_qnum(sc,
2105 ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_VO);
2106 break;
2107 }
2108 }
2109 }
2110
2111 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an)
2112 {
2113 int i;
2114 struct ath_atx_ac *ac, *ac_tmp;
2115 struct ath_atx_tid *tid, *tid_tmp;
2116 struct ath_txq *txq;
2117
2118 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2119 if (ATH_TXQ_SETUP(sc, i)) {
2120 txq = &sc->tx.txq[i];
2121
2122 spin_lock(&txq->axq_lock);
2123
2124 list_for_each_entry_safe(ac,
2125 ac_tmp, &txq->axq_acq, list) {
2126 tid = list_first_entry(&ac->tid_q,
2127 struct ath_atx_tid, list);
2128 if (tid && tid->an != an)
2129 continue;
2130 list_del(&ac->list);
2131 ac->sched = false;
2132
2133 list_for_each_entry_safe(tid,
2134 tid_tmp, &ac->tid_q, list) {
2135 list_del(&tid->list);
2136 tid->sched = false;
2137 ath_tid_drain(sc, txq, tid);
2138 tid->state &= ~AGGR_ADDBA_COMPLETE;
2139 tid->addba_exchangeattempts = 0;
2140 tid->state &= ~AGGR_CLEANUP;
2141 }
2142 }
2143
2144 spin_unlock(&txq->axq_lock);
2145 }
2146 }
2147 }
Linux kernel - Deliverables
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