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Merge branch 'master' of master.kernel.org:/pub/scm/linux/kernel/git/davem/net-2.6
[deliverable/linux.git] / drivers / net / wireless / ath9k / xmit.c
1 /*
2 * Copyright (c) 2008 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 /*
18 * Implementation of transmit path.
19 */
20
21 #include "core.h"
22
23 #define BITS_PER_BYTE 8
24 #define OFDM_PLCP_BITS 22
25 #define HT_RC_2_MCS(_rc) ((_rc) & 0x0f)
26 #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
27 #define L_STF 8
28 #define L_LTF 8
29 #define L_SIG 4
30 #define HT_SIG 8
31 #define HT_STF 4
32 #define HT_LTF(_ns) (4 * (_ns))
33 #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */
34 #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */
35 #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
36 #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
37
38 #define OFDM_SIFS_TIME 16
39
40 static u32 bits_per_symbol[][2] = {
41 /* 20MHz 40MHz */
42 { 26, 54 }, /* 0: BPSK */
43 { 52, 108 }, /* 1: QPSK 1/2 */
44 { 78, 162 }, /* 2: QPSK 3/4 */
45 { 104, 216 }, /* 3: 16-QAM 1/2 */
46 { 156, 324 }, /* 4: 16-QAM 3/4 */
47 { 208, 432 }, /* 5: 64-QAM 2/3 */
48 { 234, 486 }, /* 6: 64-QAM 3/4 */
49 { 260, 540 }, /* 7: 64-QAM 5/6 */
50 { 52, 108 }, /* 8: BPSK */
51 { 104, 216 }, /* 9: QPSK 1/2 */
52 { 156, 324 }, /* 10: QPSK 3/4 */
53 { 208, 432 }, /* 11: 16-QAM 1/2 */
54 { 312, 648 }, /* 12: 16-QAM 3/4 */
55 { 416, 864 }, /* 13: 64-QAM 2/3 */
56 { 468, 972 }, /* 14: 64-QAM 3/4 */
57 { 520, 1080 }, /* 15: 64-QAM 5/6 */
58 };
59
60 #define IS_HT_RATE(_rate) ((_rate) & 0x80)
61
62 /*
63 * Insert a chain of ath_buf (descriptors) on a txq and
64 * assume the descriptors are already chained together by caller.
65 * NB: must be called with txq lock held
66 */
67
68 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
69 struct list_head *head)
70 {
71 struct ath_hal *ah = sc->sc_ah;
72 struct ath_buf *bf;
73
74 /*
75 * Insert the frame on the outbound list and
76 * pass it on to the hardware.
77 */
78
79 if (list_empty(head))
80 return;
81
82 bf = list_first_entry(head, struct ath_buf, list);
83
84 list_splice_tail_init(head, &txq->axq_q);
85 txq->axq_depth++;
86 txq->axq_totalqueued++;
87 txq->axq_linkbuf = list_entry(txq->axq_q.prev, struct ath_buf, list);
88
89 DPRINTF(sc, ATH_DBG_QUEUE,
90 "%s: txq depth = %d\n", __func__, txq->axq_depth);
91
92 if (txq->axq_link == NULL) {
93 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
94 DPRINTF(sc, ATH_DBG_XMIT,
95 "%s: TXDP[%u] = %llx (%p)\n",
96 __func__, txq->axq_qnum,
97 ito64(bf->bf_daddr), bf->bf_desc);
98 } else {
99 *txq->axq_link = bf->bf_daddr;
100 DPRINTF(sc, ATH_DBG_XMIT, "%s: link[%u] (%p)=%llx (%p)\n",
101 __func__,
102 txq->axq_qnum, txq->axq_link,
103 ito64(bf->bf_daddr), bf->bf_desc);
104 }
105 txq->axq_link = &(bf->bf_lastbf->bf_desc->ds_link);
106 ath9k_hw_txstart(ah, txq->axq_qnum);
107 }
108
109 /* Get transmit rate index using rate in Kbps */
110
111 static int ath_tx_findindex(const struct ath9k_rate_table *rt, int rate)
112 {
113 int i;
114 int ndx = 0;
115
116 for (i = 0; i < rt->rateCount; i++) {
117 if (rt->info[i].rateKbps == rate) {
118 ndx = i;
119 break;
120 }
121 }
122
123 return ndx;
124 }
125
126 /* Check if it's okay to send out aggregates */
127
128 static int ath_aggr_query(struct ath_softc *sc, struct ath_node *an, u8 tidno)
129 {
130 struct ath_atx_tid *tid;
131 tid = ATH_AN_2_TID(an, tidno);
132
133 if (tid->state & AGGR_ADDBA_COMPLETE ||
134 tid->state & AGGR_ADDBA_PROGRESS)
135 return 1;
136 else
137 return 0;
138 }
139
140 /* Calculate Atheros packet type from IEEE80211 packet header */
141
142 static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb)
143 {
144 struct ieee80211_hdr *hdr;
145 enum ath9k_pkt_type htype;
146 __le16 fc;
147
148 hdr = (struct ieee80211_hdr *)skb->data;
149 fc = hdr->frame_control;
150
151 if (ieee80211_is_beacon(fc))
152 htype = ATH9K_PKT_TYPE_BEACON;
153 else if (ieee80211_is_probe_resp(fc))
154 htype = ATH9K_PKT_TYPE_PROBE_RESP;
155 else if (ieee80211_is_atim(fc))
156 htype = ATH9K_PKT_TYPE_ATIM;
157 else if (ieee80211_is_pspoll(fc))
158 htype = ATH9K_PKT_TYPE_PSPOLL;
159 else
160 htype = ATH9K_PKT_TYPE_NORMAL;
161
162 return htype;
163 }
164
165 static bool check_min_rate(struct sk_buff *skb)
166 {
167 struct ieee80211_hdr *hdr;
168 bool use_minrate = false;
169 __le16 fc;
170
171 hdr = (struct ieee80211_hdr *)skb->data;
172 fc = hdr->frame_control;
173
174 if (ieee80211_is_mgmt(fc) || ieee80211_is_ctl(fc)) {
175 use_minrate = true;
176 } else if (ieee80211_is_data(fc)) {
177 if (ieee80211_is_nullfunc(fc) ||
178 /* Port Access Entity (IEEE 802.1X) */
179 (skb->protocol == cpu_to_be16(ETH_P_PAE))) {
180 use_minrate = true;
181 }
182 }
183
184 return use_minrate;
185 }
186
187 static int get_hw_crypto_keytype(struct sk_buff *skb)
188 {
189 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
190
191 if (tx_info->control.hw_key) {
192 if (tx_info->control.hw_key->alg == ALG_WEP)
193 return ATH9K_KEY_TYPE_WEP;
194 else if (tx_info->control.hw_key->alg == ALG_TKIP)
195 return ATH9K_KEY_TYPE_TKIP;
196 else if (tx_info->control.hw_key->alg == ALG_CCMP)
197 return ATH9K_KEY_TYPE_AES;
198 }
199
200 return ATH9K_KEY_TYPE_CLEAR;
201 }
202
203 static void setup_rate_retries(struct ath_softc *sc, struct sk_buff *skb)
204 {
205 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
206 struct ath_tx_info_priv *tx_info_priv;
207 struct ath_rc_series *rcs;
208 struct ieee80211_hdr *hdr;
209 const struct ath9k_rate_table *rt;
210 bool use_minrate;
211 __le16 fc;
212 u8 rix;
213
214 rt = sc->sc_currates;
215 BUG_ON(!rt);
216
217 hdr = (struct ieee80211_hdr *)skb->data;
218 fc = hdr->frame_control;
219 tx_info_priv = (struct ath_tx_info_priv *)tx_info->control.vif; /* HACK */
220 rcs = tx_info_priv->rcs;
221
222 /* Check if min rates have to be used */
223 use_minrate = check_min_rate(skb);
224
225 if (ieee80211_is_data(fc) && !use_minrate) {
226 if (is_multicast_ether_addr(hdr->addr1)) {
227 rcs[0].rix =
228 ath_tx_findindex(rt, tx_info_priv->min_rate);
229 /* mcast packets are not re-tried */
230 rcs[0].tries = 1;
231 }
232 } else {
233 /* for management and control frames,
234 or for NULL and EAPOL frames */
235 if (use_minrate)
236 rcs[0].rix = ath_rate_findrateix(sc, tx_info_priv->min_rate);
237 else
238 rcs[0].rix = 0;
239 rcs[0].tries = ATH_MGT_TXMAXTRY;
240 }
241
242 rix = rcs[0].rix;
243
244 if (ieee80211_has_morefrags(fc) ||
245 (le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG)) {
246 rcs[1].tries = rcs[2].tries = rcs[3].tries = 0;
247 rcs[1].rix = rcs[2].rix = rcs[3].rix = 0;
248 /* reset tries but keep rate index */
249 rcs[0].tries = ATH_TXMAXTRY;
250 }
251 }
252
253 /* Called only when tx aggregation is enabled and HT is supported */
254
255 static void assign_aggr_tid_seqno(struct sk_buff *skb,
256 struct ath_buf *bf)
257 {
258 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
259 struct ieee80211_hdr *hdr;
260 struct ath_node *an;
261 struct ath_atx_tid *tid;
262 __le16 fc;
263 u8 *qc;
264
265 if (!tx_info->control.sta)
266 return;
267
268 an = (struct ath_node *)tx_info->control.sta->drv_priv;
269 hdr = (struct ieee80211_hdr *)skb->data;
270 fc = hdr->frame_control;
271
272 /* Get tidno */
273
274 if (ieee80211_is_data_qos(fc)) {
275 qc = ieee80211_get_qos_ctl(hdr);
276 bf->bf_tidno = qc[0] & 0xf;
277 }
278
279 /* Get seqno */
280
281 if (ieee80211_is_data(fc) && !check_min_rate(skb)) {
282 /* For HT capable stations, we save tidno for later use.
283 * We also override seqno set by upper layer with the one
284 * in tx aggregation state.
285 *
286 * If fragmentation is on, the sequence number is
287 * not overridden, since it has been
288 * incremented by the fragmentation routine.
289 *
290 * FIXME: check if the fragmentation threshold exceeds
291 * IEEE80211 max.
292 */
293 tid = ATH_AN_2_TID(an, bf->bf_tidno);
294 hdr->seq_ctrl = cpu_to_le16(tid->seq_next <<
295 IEEE80211_SEQ_SEQ_SHIFT);
296 bf->bf_seqno = tid->seq_next;
297 INCR(tid->seq_next, IEEE80211_SEQ_MAX);
298 }
299 }
300
301 static int setup_tx_flags(struct ath_softc *sc, struct sk_buff *skb,
302 struct ath_txq *txq)
303 {
304 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
305 int flags = 0;
306
307 flags |= ATH9K_TXDESC_CLRDMASK; /* needed for crypto errors */
308 flags |= ATH9K_TXDESC_INTREQ;
309
310 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
311 flags |= ATH9K_TXDESC_NOACK;
312 if (tx_info->control.rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS)
313 flags |= ATH9K_TXDESC_RTSENA;
314
315 return flags;
316 }
317
318 static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc)
319 {
320 struct ath_buf *bf = NULL;
321
322 spin_lock_bh(&sc->sc_txbuflock);
323
324 if (unlikely(list_empty(&sc->sc_txbuf))) {
325 spin_unlock_bh(&sc->sc_txbuflock);
326 return NULL;
327 }
328
329 bf = list_first_entry(&sc->sc_txbuf, struct ath_buf, list);
330 list_del(&bf->list);
331
332 spin_unlock_bh(&sc->sc_txbuflock);
333
334 return bf;
335 }
336
337 /* To complete a chain of buffers associated a frame */
338
339 static void ath_tx_complete_buf(struct ath_softc *sc,
340 struct ath_buf *bf,
341 struct list_head *bf_q,
342 int txok, int sendbar)
343 {
344 struct sk_buff *skb = bf->bf_mpdu;
345 struct ath_xmit_status tx_status;
346
347 /*
348 * Set retry information.
349 * NB: Don't use the information in the descriptor, because the frame
350 * could be software retried.
351 */
352 tx_status.retries = bf->bf_retries;
353 tx_status.flags = 0;
354
355 if (sendbar)
356 tx_status.flags = ATH_TX_BAR;
357
358 if (!txok) {
359 tx_status.flags |= ATH_TX_ERROR;
360
361 if (bf_isxretried(bf))
362 tx_status.flags |= ATH_TX_XRETRY;
363 }
364
365 /* Unmap this frame */
366 pci_unmap_single(sc->pdev,
367 bf->bf_dmacontext,
368 skb->len,
369 PCI_DMA_TODEVICE);
370 /* complete this frame */
371 ath_tx_complete(sc, skb, &tx_status);
372
373 /*
374 * Return the list of ath_buf of this mpdu to free queue
375 */
376 spin_lock_bh(&sc->sc_txbuflock);
377 list_splice_tail_init(bf_q, &sc->sc_txbuf);
378 spin_unlock_bh(&sc->sc_txbuflock);
379 }
380
381 /*
382 * queue up a dest/ac pair for tx scheduling
383 * NB: must be called with txq lock held
384 */
385
386 static void ath_tx_queue_tid(struct ath_txq *txq, struct ath_atx_tid *tid)
387 {
388 struct ath_atx_ac *ac = tid->ac;
389
390 /*
391 * if tid is paused, hold off
392 */
393 if (tid->paused)
394 return;
395
396 /*
397 * add tid to ac atmost once
398 */
399 if (tid->sched)
400 return;
401
402 tid->sched = true;
403 list_add_tail(&tid->list, &ac->tid_q);
404
405 /*
406 * add node ac to txq atmost once
407 */
408 if (ac->sched)
409 return;
410
411 ac->sched = true;
412 list_add_tail(&ac->list, &txq->axq_acq);
413 }
414
415 /* pause a tid */
416
417 static void ath_tx_pause_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
418 {
419 struct ath_txq *txq = &sc->sc_txq[tid->ac->qnum];
420
421 spin_lock_bh(&txq->axq_lock);
422
423 tid->paused++;
424
425 spin_unlock_bh(&txq->axq_lock);
426 }
427
428 /* resume a tid and schedule aggregate */
429
430 void ath_tx_resume_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
431 {
432 struct ath_txq *txq = &sc->sc_txq[tid->ac->qnum];
433
434 ASSERT(tid->paused > 0);
435 spin_lock_bh(&txq->axq_lock);
436
437 tid->paused--;
438
439 if (tid->paused > 0)
440 goto unlock;
441
442 if (list_empty(&tid->buf_q))
443 goto unlock;
444
445 /*
446 * Add this TID to scheduler and try to send out aggregates
447 */
448 ath_tx_queue_tid(txq, tid);
449 ath_txq_schedule(sc, txq);
450 unlock:
451 spin_unlock_bh(&txq->axq_lock);
452 }
453
454 /* Compute the number of bad frames */
455
456 static int ath_tx_num_badfrms(struct ath_softc *sc, struct ath_buf *bf,
457 int txok)
458 {
459 struct ath_buf *bf_last = bf->bf_lastbf;
460 struct ath_desc *ds = bf_last->bf_desc;
461 u16 seq_st = 0;
462 u32 ba[WME_BA_BMP_SIZE >> 5];
463 int ba_index;
464 int nbad = 0;
465 int isaggr = 0;
466
467 if (ds->ds_txstat.ts_flags == ATH9K_TX_SW_ABORTED)
468 return 0;
469
470 isaggr = bf_isaggr(bf);
471 if (isaggr) {
472 seq_st = ATH_DS_BA_SEQ(ds);
473 memcpy(ba, ATH_DS_BA_BITMAP(ds), WME_BA_BMP_SIZE >> 3);
474 }
475
476 while (bf) {
477 ba_index = ATH_BA_INDEX(seq_st, bf->bf_seqno);
478 if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index)))
479 nbad++;
480
481 bf = bf->bf_next;
482 }
483
484 return nbad;
485 }
486
487 static void ath_tx_set_retry(struct ath_softc *sc, struct ath_buf *bf)
488 {
489 struct sk_buff *skb;
490 struct ieee80211_hdr *hdr;
491
492 bf->bf_state.bf_type |= BUF_RETRY;
493 bf->bf_retries++;
494
495 skb = bf->bf_mpdu;
496 hdr = (struct ieee80211_hdr *)skb->data;
497 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY);
498 }
499
500 /* Update block ack window */
501
502 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
503 int seqno)
504 {
505 int index, cindex;
506
507 index = ATH_BA_INDEX(tid->seq_start, seqno);
508 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
509
510 tid->tx_buf[cindex] = NULL;
511
512 while (tid->baw_head != tid->baw_tail && !tid->tx_buf[tid->baw_head]) {
513 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
514 INCR(tid->baw_head, ATH_TID_MAX_BUFS);
515 }
516 }
517
518 /*
519 * ath_pkt_dur - compute packet duration (NB: not NAV)
520 *
521 * rix - rate index
522 * pktlen - total bytes (delims + data + fcs + pads + pad delims)
523 * width - 0 for 20 MHz, 1 for 40 MHz
524 * half_gi - to use 4us v/s 3.6 us for symbol time
525 */
526
527 static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, struct ath_buf *bf,
528 int width, int half_gi, bool shortPreamble)
529 {
530 const struct ath9k_rate_table *rt = sc->sc_currates;
531 u32 nbits, nsymbits, duration, nsymbols;
532 u8 rc;
533 int streams, pktlen;
534
535 pktlen = bf_isaggr(bf) ? bf->bf_al : bf->bf_frmlen;
536 rc = rt->info[rix].rateCode;
537
538 /*
539 * for legacy rates, use old function to compute packet duration
540 */
541 if (!IS_HT_RATE(rc))
542 return ath9k_hw_computetxtime(sc->sc_ah, rt, pktlen, rix,
543 shortPreamble);
544 /*
545 * find number of symbols: PLCP + data
546 */
547 nbits = (pktlen << 3) + OFDM_PLCP_BITS;
548 nsymbits = bits_per_symbol[HT_RC_2_MCS(rc)][width];
549 nsymbols = (nbits + nsymbits - 1) / nsymbits;
550
551 if (!half_gi)
552 duration = SYMBOL_TIME(nsymbols);
553 else
554 duration = SYMBOL_TIME_HALFGI(nsymbols);
555
556 /*
557 * addup duration for legacy/ht training and signal fields
558 */
559 streams = HT_RC_2_STREAMS(rc);
560 duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
561
562 return duration;
563 }
564
565 /* Rate module function to set rate related fields in tx descriptor */
566
567 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf)
568 {
569 struct ath_hal *ah = sc->sc_ah;
570 const struct ath9k_rate_table *rt;
571 struct ath_desc *ds = bf->bf_desc;
572 struct ath_desc *lastds = bf->bf_lastbf->bf_desc;
573 struct ath9k_11n_rate_series series[4];
574 int i, flags, rtsctsena = 0;
575 u32 ctsduration = 0;
576 u8 rix = 0, cix, ctsrate = 0;
577 struct ath_node *an = NULL;
578 struct sk_buff *skb;
579 struct ieee80211_tx_info *tx_info;
580
581 skb = (struct sk_buff *)bf->bf_mpdu;
582 tx_info = IEEE80211_SKB_CB(skb);
583
584 if (tx_info->control.sta)
585 an = (struct ath_node *)tx_info->control.sta->drv_priv;
586
587 /*
588 * get the cix for the lowest valid rix.
589 */
590 rt = sc->sc_currates;
591 for (i = 4; i--;) {
592 if (bf->bf_rcs[i].tries) {
593 rix = bf->bf_rcs[i].rix;
594 break;
595 }
596 }
597 flags = (bf->bf_flags & (ATH9K_TXDESC_RTSENA | ATH9K_TXDESC_CTSENA));
598 cix = rt->info[rix].controlRate;
599
600 /*
601 * If 802.11g protection is enabled, determine whether
602 * to use RTS/CTS or just CTS. Note that this is only
603 * done for OFDM/HT unicast frames.
604 */
605 if (sc->sc_protmode != PROT_M_NONE &&
606 (rt->info[rix].phy == PHY_OFDM ||
607 rt->info[rix].phy == PHY_HT) &&
608 (bf->bf_flags & ATH9K_TXDESC_NOACK) == 0) {
609 if (sc->sc_protmode == PROT_M_RTSCTS)
610 flags = ATH9K_TXDESC_RTSENA;
611 else if (sc->sc_protmode == PROT_M_CTSONLY)
612 flags = ATH9K_TXDESC_CTSENA;
613
614 cix = rt->info[sc->sc_protrix].controlRate;
615 rtsctsena = 1;
616 }
617
618 /* For 11n, the default behavior is to enable RTS for
619 * hw retried frames. We enable the global flag here and
620 * let rate series flags determine which rates will actually
621 * use RTS.
622 */
623 if ((ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) && bf_isdata(bf)) {
624 /*
625 * 802.11g protection not needed, use our default behavior
626 */
627 if (!rtsctsena)
628 flags = ATH9K_TXDESC_RTSENA;
629 }
630
631 /*
632 * Set protection if aggregate protection on
633 */
634 if (sc->sc_config.ath_aggr_prot &&
635 (!bf_isaggr(bf) || (bf_isaggr(bf) && bf->bf_al < 8192))) {
636 flags = ATH9K_TXDESC_RTSENA;
637 cix = rt->info[sc->sc_protrix].controlRate;
638 rtsctsena = 1;
639 }
640
641 /*
642 * For AR5416 - RTS cannot be followed by a frame larger than 8K.
643 */
644 if (bf_isaggr(bf) && (bf->bf_al > ah->ah_caps.rts_aggr_limit)) {
645 /*
646 * Ensure that in the case of SM Dynamic power save
647 * while we are bursting the second aggregate the
648 * RTS is cleared.
649 */
650 flags &= ~(ATH9K_TXDESC_RTSENA);
651 }
652
653 /*
654 * CTS transmit rate is derived from the transmit rate
655 * by looking in the h/w rate table. We must also factor
656 * in whether or not a short preamble is to be used.
657 * NB: cix is set above where RTS/CTS is enabled
658 */
659 BUG_ON(cix == 0xff);
660 ctsrate = rt->info[cix].rateCode |
661 (bf_isshpreamble(bf) ? rt->info[cix].shortPreamble : 0);
662
663 /*
664 * Setup HAL rate series
665 */
666 memset(series, 0, sizeof(struct ath9k_11n_rate_series) * 4);
667
668 for (i = 0; i < 4; i++) {
669 if (!bf->bf_rcs[i].tries)
670 continue;
671
672 rix = bf->bf_rcs[i].rix;
673
674 series[i].Rate = rt->info[rix].rateCode |
675 (bf_isshpreamble(bf) ? rt->info[rix].shortPreamble : 0);
676
677 series[i].Tries = bf->bf_rcs[i].tries;
678
679 series[i].RateFlags = (
680 (bf->bf_rcs[i].flags & ATH_RC_RTSCTS_FLAG) ?
681 ATH9K_RATESERIES_RTS_CTS : 0) |
682 ((bf->bf_rcs[i].flags & ATH_RC_CW40_FLAG) ?
683 ATH9K_RATESERIES_2040 : 0) |
684 ((bf->bf_rcs[i].flags & ATH_RC_SGI_FLAG) ?
685 ATH9K_RATESERIES_HALFGI : 0);
686
687 series[i].PktDuration = ath_pkt_duration(sc, rix, bf,
688 (bf->bf_rcs[i].flags & ATH_RC_CW40_FLAG) != 0,
689 (bf->bf_rcs[i].flags & ATH_RC_SGI_FLAG),
690 bf_isshpreamble(bf));
691
692 if (bf_isht(bf) && an)
693 series[i].ChSel = ath_chainmask_sel_logic(sc, an);
694 else
695 series[i].ChSel = sc->sc_tx_chainmask;
696
697 if (rtsctsena)
698 series[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
699 }
700
701 /*
702 * For non-HT devices, calculate RTS/CTS duration in software
703 * and disable multi-rate retry.
704 */
705 if (flags && !(ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT)) {
706 /*
707 * Compute the transmit duration based on the frame
708 * size and the size of an ACK frame. We call into the
709 * HAL to do the computation since it depends on the
710 * characteristics of the actual PHY being used.
711 *
712 * NB: CTS is assumed the same size as an ACK so we can
713 * use the precalculated ACK durations.
714 */
715 if (flags & ATH9K_TXDESC_RTSENA) { /* SIFS + CTS */
716 ctsduration += bf_isshpreamble(bf) ?
717 rt->info[cix].spAckDuration :
718 rt->info[cix].lpAckDuration;
719 }
720
721 ctsduration += series[0].PktDuration;
722
723 if ((bf->bf_flags & ATH9K_TXDESC_NOACK) == 0) { /* SIFS + ACK */
724 ctsduration += bf_isshpreamble(bf) ?
725 rt->info[rix].spAckDuration :
726 rt->info[rix].lpAckDuration;
727 }
728
729 /*
730 * Disable multi-rate retry when using RTS/CTS by clearing
731 * series 1, 2 and 3.
732 */
733 memset(&series[1], 0, sizeof(struct ath9k_11n_rate_series) * 3);
734 }
735
736 /*
737 * set dur_update_en for l-sig computation except for PS-Poll frames
738 */
739 ath9k_hw_set11n_ratescenario(ah, ds, lastds,
740 !bf_ispspoll(bf),
741 ctsrate,
742 ctsduration,
743 series, 4, flags);
744
745 if (sc->sc_config.ath_aggr_prot && flags)
746 ath9k_hw_set11n_burstduration(ah, ds, 8192);
747 }
748
749 /*
750 * Function to send a normal HT (non-AMPDU) frame
751 * NB: must be called with txq lock held
752 */
753
754 static int ath_tx_send_normal(struct ath_softc *sc,
755 struct ath_txq *txq,
756 struct ath_atx_tid *tid,
757 struct list_head *bf_head)
758 {
759 struct ath_buf *bf;
760 struct sk_buff *skb;
761 struct ieee80211_tx_info *tx_info;
762 struct ath_tx_info_priv *tx_info_priv;
763
764 BUG_ON(list_empty(bf_head));
765
766 bf = list_first_entry(bf_head, struct ath_buf, list);
767 bf->bf_state.bf_type &= ~BUF_AMPDU; /* regular HT frame */
768
769 skb = (struct sk_buff *)bf->bf_mpdu;
770 tx_info = IEEE80211_SKB_CB(skb);
771
772 /* XXX: HACK! */
773 tx_info_priv = (struct ath_tx_info_priv *)tx_info->control.vif;
774 memcpy(bf->bf_rcs, tx_info_priv->rcs, 4 * sizeof(tx_info_priv->rcs[0]));
775
776 /* update starting sequence number for subsequent ADDBA request */
777 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
778
779 /* Queue to h/w without aggregation */
780 bf->bf_nframes = 1;
781 bf->bf_lastbf = bf->bf_lastfrm; /* one single frame */
782 ath_buf_set_rate(sc, bf);
783 ath_tx_txqaddbuf(sc, txq, bf_head);
784
785 return 0;
786 }
787
788 /* flush tid's software queue and send frames as non-ampdu's */
789
790 static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
791 {
792 struct ath_txq *txq = &sc->sc_txq[tid->ac->qnum];
793 struct ath_buf *bf;
794 struct list_head bf_head;
795 INIT_LIST_HEAD(&bf_head);
796
797 ASSERT(tid->paused > 0);
798 spin_lock_bh(&txq->axq_lock);
799
800 tid->paused--;
801
802 if (tid->paused > 0) {
803 spin_unlock_bh(&txq->axq_lock);
804 return;
805 }
806
807 while (!list_empty(&tid->buf_q)) {
808 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
809 ASSERT(!bf_isretried(bf));
810 list_cut_position(&bf_head, &tid->buf_q, &bf->bf_lastfrm->list);
811 ath_tx_send_normal(sc, txq, tid, &bf_head);
812 }
813
814 spin_unlock_bh(&txq->axq_lock);
815 }
816
817 /* Completion routine of an aggregate */
818
819 static void ath_tx_complete_aggr_rifs(struct ath_softc *sc,
820 struct ath_txq *txq,
821 struct ath_buf *bf,
822 struct list_head *bf_q,
823 int txok)
824 {
825 struct ath_node *an = NULL;
826 struct sk_buff *skb;
827 struct ieee80211_tx_info *tx_info;
828 struct ath_atx_tid *tid = NULL;
829 struct ath_buf *bf_last = bf->bf_lastbf;
830 struct ath_desc *ds = bf_last->bf_desc;
831 struct ath_buf *bf_next, *bf_lastq = NULL;
832 struct list_head bf_head, bf_pending;
833 u16 seq_st = 0;
834 u32 ba[WME_BA_BMP_SIZE >> 5];
835 int isaggr, txfail, txpending, sendbar = 0, needreset = 0;
836
837 skb = (struct sk_buff *)bf->bf_mpdu;
838 tx_info = IEEE80211_SKB_CB(skb);
839
840 if (tx_info->control.sta) {
841 an = (struct ath_node *)tx_info->control.sta->drv_priv;
842 tid = ATH_AN_2_TID(an, bf->bf_tidno);
843 }
844
845 isaggr = bf_isaggr(bf);
846 if (isaggr) {
847 if (txok) {
848 if (ATH_DS_TX_BA(ds)) {
849 /*
850 * extract starting sequence and
851 * block-ack bitmap
852 */
853 seq_st = ATH_DS_BA_SEQ(ds);
854 memcpy(ba,
855 ATH_DS_BA_BITMAP(ds),
856 WME_BA_BMP_SIZE >> 3);
857 } else {
858 memset(ba, 0, WME_BA_BMP_SIZE >> 3);
859
860 /*
861 * AR5416 can become deaf/mute when BA
862 * issue happens. Chip needs to be reset.
863 * But AP code may have sychronization issues
864 * when perform internal reset in this routine.
865 * Only enable reset in STA mode for now.
866 */
867 if (sc->sc_ah->ah_opmode == ATH9K_M_STA)
868 needreset = 1;
869 }
870 } else {
871 memset(ba, 0, WME_BA_BMP_SIZE >> 3);
872 }
873 }
874
875 INIT_LIST_HEAD(&bf_pending);
876 INIT_LIST_HEAD(&bf_head);
877
878 while (bf) {
879 txfail = txpending = 0;
880 bf_next = bf->bf_next;
881
882 if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, bf->bf_seqno))) {
883 /* transmit completion, subframe is
884 * acked by block ack */
885 } else if (!isaggr && txok) {
886 /* transmit completion */
887 } else {
888
889 if (!(tid->state & AGGR_CLEANUP) &&
890 ds->ds_txstat.ts_flags != ATH9K_TX_SW_ABORTED) {
891 if (bf->bf_retries < ATH_MAX_SW_RETRIES) {
892 ath_tx_set_retry(sc, bf);
893 txpending = 1;
894 } else {
895 bf->bf_state.bf_type |= BUF_XRETRY;
896 txfail = 1;
897 sendbar = 1;
898 }
899 } else {
900 /*
901 * cleanup in progress, just fail
902 * the un-acked sub-frames
903 */
904 txfail = 1;
905 }
906 }
907 /*
908 * Remove ath_buf's of this sub-frame from aggregate queue.
909 */
910 if (bf_next == NULL) { /* last subframe in the aggregate */
911 ASSERT(bf->bf_lastfrm == bf_last);
912
913 /*
914 * The last descriptor of the last sub frame could be
915 * a holding descriptor for h/w. If that's the case,
916 * bf->bf_lastfrm won't be in the bf_q.
917 * Make sure we handle bf_q properly here.
918 */
919
920 if (!list_empty(bf_q)) {
921 bf_lastq = list_entry(bf_q->prev,
922 struct ath_buf, list);
923 list_cut_position(&bf_head,
924 bf_q, &bf_lastq->list);
925 } else {
926 /*
927 * XXX: if the last subframe only has one
928 * descriptor which is also being used as
929 * a holding descriptor. Then the ath_buf
930 * is not in the bf_q at all.
931 */
932 INIT_LIST_HEAD(&bf_head);
933 }
934 } else {
935 ASSERT(!list_empty(bf_q));
936 list_cut_position(&bf_head,
937 bf_q, &bf->bf_lastfrm->list);
938 }
939
940 if (!txpending) {
941 /*
942 * complete the acked-ones/xretried ones; update
943 * block-ack window
944 */
945 spin_lock_bh(&txq->axq_lock);
946 ath_tx_update_baw(sc, tid, bf->bf_seqno);
947 spin_unlock_bh(&txq->axq_lock);
948
949 /* complete this sub-frame */
950 ath_tx_complete_buf(sc, bf, &bf_head, !txfail, sendbar);
951 } else {
952 /*
953 * retry the un-acked ones
954 */
955 /*
956 * XXX: if the last descriptor is holding descriptor,
957 * in order to requeue the frame to software queue, we
958 * need to allocate a new descriptor and
959 * copy the content of holding descriptor to it.
960 */
961 if (bf->bf_next == NULL &&
962 bf_last->bf_status & ATH_BUFSTATUS_STALE) {
963 struct ath_buf *tbf;
964
965 /* allocate new descriptor */
966 spin_lock_bh(&sc->sc_txbuflock);
967 ASSERT(!list_empty((&sc->sc_txbuf)));
968 tbf = list_first_entry(&sc->sc_txbuf,
969 struct ath_buf, list);
970 list_del(&tbf->list);
971 spin_unlock_bh(&sc->sc_txbuflock);
972
973 ATH_TXBUF_RESET(tbf);
974
975 /* copy descriptor content */
976 tbf->bf_mpdu = bf_last->bf_mpdu;
977 tbf->bf_buf_addr = bf_last->bf_buf_addr;
978 *(tbf->bf_desc) = *(bf_last->bf_desc);
979
980 /* link it to the frame */
981 if (bf_lastq) {
982 bf_lastq->bf_desc->ds_link =
983 tbf->bf_daddr;
984 bf->bf_lastfrm = tbf;
985 ath9k_hw_cleartxdesc(sc->sc_ah,
986 bf->bf_lastfrm->bf_desc);
987 } else {
988 tbf->bf_state = bf_last->bf_state;
989 tbf->bf_lastfrm = tbf;
990 ath9k_hw_cleartxdesc(sc->sc_ah,
991 tbf->bf_lastfrm->bf_desc);
992
993 /* copy the DMA context */
994 tbf->bf_dmacontext =
995 bf_last->bf_dmacontext;
996 }
997 list_add_tail(&tbf->list, &bf_head);
998 } else {
999 /*
1000 * Clear descriptor status words for
1001 * software retry
1002 */
1003 ath9k_hw_cleartxdesc(sc->sc_ah,
1004 bf->bf_lastfrm->bf_desc);
1005 }
1006
1007 /*
1008 * Put this buffer to the temporary pending
1009 * queue to retain ordering
1010 */
1011 list_splice_tail_init(&bf_head, &bf_pending);
1012 }
1013
1014 bf = bf_next;
1015 }
1016
1017 if (tid->state & AGGR_CLEANUP) {
1018 /* check to see if we're done with cleaning the h/w queue */
1019 spin_lock_bh(&txq->axq_lock);
1020
1021 if (tid->baw_head == tid->baw_tail) {
1022 tid->state &= ~AGGR_ADDBA_COMPLETE;
1023 tid->addba_exchangeattempts = 0;
1024 spin_unlock_bh(&txq->axq_lock);
1025
1026 tid->state &= ~AGGR_CLEANUP;
1027
1028 /* send buffered frames as singles */
1029 ath_tx_flush_tid(sc, tid);
1030 } else
1031 spin_unlock_bh(&txq->axq_lock);
1032
1033 return;
1034 }
1035
1036 /*
1037 * prepend un-acked frames to the beginning of the pending frame queue
1038 */
1039 if (!list_empty(&bf_pending)) {
1040 spin_lock_bh(&txq->axq_lock);
1041 /* Note: we _prepend_, we _do_not_ at to
1042 * the end of the queue ! */
1043 list_splice(&bf_pending, &tid->buf_q);
1044 ath_tx_queue_tid(txq, tid);
1045 spin_unlock_bh(&txq->axq_lock);
1046 }
1047
1048 if (needreset)
1049 ath_reset(sc, false);
1050
1051 return;
1052 }
1053
1054 /* Process completed xmit descriptors from the specified queue */
1055
1056 static int ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
1057 {
1058 struct ath_hal *ah = sc->sc_ah;
1059 struct ath_buf *bf, *lastbf, *bf_held = NULL;
1060 struct list_head bf_head;
1061 struct ath_desc *ds, *tmp_ds;
1062 struct sk_buff *skb;
1063 struct ieee80211_tx_info *tx_info;
1064 struct ath_tx_info_priv *tx_info_priv;
1065 int nacked, txok, nbad = 0, isrifs = 0;
1066 int status;
1067
1068 DPRINTF(sc, ATH_DBG_QUEUE,
1069 "%s: tx queue %d (%x), link %p\n", __func__,
1070 txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum),
1071 txq->axq_link);
1072
1073 nacked = 0;
1074 for (;;) {
1075 spin_lock_bh(&txq->axq_lock);
1076 if (list_empty(&txq->axq_q)) {
1077 txq->axq_link = NULL;
1078 txq->axq_linkbuf = NULL;
1079 spin_unlock_bh(&txq->axq_lock);
1080 break;
1081 }
1082 bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
1083
1084 /*
1085 * There is a race condition that a BH gets scheduled
1086 * after sw writes TxE and before hw re-load the last
1087 * descriptor to get the newly chained one.
1088 * Software must keep the last DONE descriptor as a
1089 * holding descriptor - software does so by marking
1090 * it with the STALE flag.
1091 */
1092 bf_held = NULL;
1093 if (bf->bf_status & ATH_BUFSTATUS_STALE) {
1094 bf_held = bf;
1095 if (list_is_last(&bf_held->list, &txq->axq_q)) {
1096 /* FIXME:
1097 * The holding descriptor is the last
1098 * descriptor in queue. It's safe to remove
1099 * the last holding descriptor in BH context.
1100 */
1101 spin_unlock_bh(&txq->axq_lock);
1102 break;
1103 } else {
1104 /* Lets work with the next buffer now */
1105 bf = list_entry(bf_held->list.next,
1106 struct ath_buf, list);
1107 }
1108 }
1109
1110 lastbf = bf->bf_lastbf;
1111 ds = lastbf->bf_desc; /* NB: last decriptor */
1112
1113 status = ath9k_hw_txprocdesc(ah, ds);
1114 if (status == -EINPROGRESS) {
1115 spin_unlock_bh(&txq->axq_lock);
1116 break;
1117 }
1118 if (bf->bf_desc == txq->axq_lastdsWithCTS)
1119 txq->axq_lastdsWithCTS = NULL;
1120 if (ds == txq->axq_gatingds)
1121 txq->axq_gatingds = NULL;
1122
1123 /*
1124 * Remove ath_buf's of the same transmit unit from txq,
1125 * however leave the last descriptor back as the holding
1126 * descriptor for hw.
1127 */
1128 lastbf->bf_status |= ATH_BUFSTATUS_STALE;
1129 INIT_LIST_HEAD(&bf_head);
1130
1131 if (!list_is_singular(&lastbf->list))
1132 list_cut_position(&bf_head,
1133 &txq->axq_q, lastbf->list.prev);
1134
1135 txq->axq_depth--;
1136
1137 if (bf_isaggr(bf))
1138 txq->axq_aggr_depth--;
1139
1140 txok = (ds->ds_txstat.ts_status == 0);
1141
1142 spin_unlock_bh(&txq->axq_lock);
1143
1144 if (bf_held) {
1145 list_del(&bf_held->list);
1146 spin_lock_bh(&sc->sc_txbuflock);
1147 list_add_tail(&bf_held->list, &sc->sc_txbuf);
1148 spin_unlock_bh(&sc->sc_txbuflock);
1149 }
1150
1151 if (!bf_isampdu(bf)) {
1152 /*
1153 * This frame is sent out as a single frame.
1154 * Use hardware retry status for this frame.
1155 */
1156 bf->bf_retries = ds->ds_txstat.ts_longretry;
1157 if (ds->ds_txstat.ts_status & ATH9K_TXERR_XRETRY)
1158 bf->bf_state.bf_type |= BUF_XRETRY;
1159 nbad = 0;
1160 } else {
1161 nbad = ath_tx_num_badfrms(sc, bf, txok);
1162 }
1163 skb = bf->bf_mpdu;
1164 tx_info = IEEE80211_SKB_CB(skb);
1165
1166 /* XXX: HACK! */
1167 tx_info_priv = (struct ath_tx_info_priv *) tx_info->control.vif;
1168 if (ds->ds_txstat.ts_status & ATH9K_TXERR_FILT)
1169 tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
1170 if ((ds->ds_txstat.ts_status & ATH9K_TXERR_FILT) == 0 &&
1171 (bf->bf_flags & ATH9K_TXDESC_NOACK) == 0) {
1172 if (ds->ds_txstat.ts_status == 0)
1173 nacked++;
1174
1175 if (bf_isdata(bf)) {
1176 if (isrifs)
1177 tmp_ds = bf->bf_rifslast->bf_desc;
1178 else
1179 tmp_ds = ds;
1180 memcpy(&tx_info_priv->tx,
1181 &tmp_ds->ds_txstat,
1182 sizeof(tx_info_priv->tx));
1183 tx_info_priv->n_frames = bf->bf_nframes;
1184 tx_info_priv->n_bad_frames = nbad;
1185 }
1186 }
1187
1188 /*
1189 * Complete this transmit unit
1190 */
1191 if (bf_isampdu(bf))
1192 ath_tx_complete_aggr_rifs(sc, txq, bf, &bf_head, txok);
1193 else
1194 ath_tx_complete_buf(sc, bf, &bf_head, txok, 0);
1195
1196 /* Wake up mac80211 queue */
1197
1198 spin_lock_bh(&txq->axq_lock);
1199 if (txq->stopped && ath_txq_depth(sc, txq->axq_qnum) <=
1200 (ATH_TXBUF - 20)) {
1201 int qnum;
1202 qnum = ath_get_mac80211_qnum(txq->axq_qnum, sc);
1203 if (qnum != -1) {
1204 ieee80211_wake_queue(sc->hw, qnum);
1205 txq->stopped = 0;
1206 }
1207
1208 }
1209
1210 /*
1211 * schedule any pending packets if aggregation is enabled
1212 */
1213 if (sc->sc_flags & SC_OP_TXAGGR)
1214 ath_txq_schedule(sc, txq);
1215 spin_unlock_bh(&txq->axq_lock);
1216 }
1217 return nacked;
1218 }
1219
1220 static void ath_tx_stopdma(struct ath_softc *sc, struct ath_txq *txq)
1221 {
1222 struct ath_hal *ah = sc->sc_ah;
1223
1224 (void) ath9k_hw_stoptxdma(ah, txq->axq_qnum);
1225 DPRINTF(sc, ATH_DBG_XMIT, "%s: tx queue [%u] %x, link %p\n",
1226 __func__, txq->axq_qnum,
1227 ath9k_hw_gettxbuf(ah, txq->axq_qnum), txq->axq_link);
1228 }
1229
1230 /* Drain only the data queues */
1231
1232 static void ath_drain_txdataq(struct ath_softc *sc, bool retry_tx)
1233 {
1234 struct ath_hal *ah = sc->sc_ah;
1235 int i, status, npend = 0;
1236
1237 if (!(sc->sc_flags & SC_OP_INVALID)) {
1238 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1239 if (ATH_TXQ_SETUP(sc, i)) {
1240 ath_tx_stopdma(sc, &sc->sc_txq[i]);
1241 /* The TxDMA may not really be stopped.
1242 * Double check the hal tx pending count */
1243 npend += ath9k_hw_numtxpending(ah,
1244 sc->sc_txq[i].axq_qnum);
1245 }
1246 }
1247 }
1248
1249 if (npend) {
1250 /* TxDMA not stopped, reset the hal */
1251 DPRINTF(sc, ATH_DBG_XMIT,
1252 "%s: Unable to stop TxDMA. Reset HAL!\n", __func__);
1253
1254 spin_lock_bh(&sc->sc_resetlock);
1255 if (!ath9k_hw_reset(ah,
1256 sc->sc_ah->ah_curchan,
1257 sc->sc_ht_info.tx_chan_width,
1258 sc->sc_tx_chainmask, sc->sc_rx_chainmask,
1259 sc->sc_ht_extprotspacing, true, &status)) {
1260
1261 DPRINTF(sc, ATH_DBG_FATAL,
1262 "%s: unable to reset hardware; hal status %u\n",
1263 __func__,
1264 status);
1265 }
1266 spin_unlock_bh(&sc->sc_resetlock);
1267 }
1268
1269 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1270 if (ATH_TXQ_SETUP(sc, i))
1271 ath_tx_draintxq(sc, &sc->sc_txq[i], retry_tx);
1272 }
1273 }
1274
1275 /* Add a sub-frame to block ack window */
1276
1277 static void ath_tx_addto_baw(struct ath_softc *sc,
1278 struct ath_atx_tid *tid,
1279 struct ath_buf *bf)
1280 {
1281 int index, cindex;
1282
1283 if (bf_isretried(bf))
1284 return;
1285
1286 index = ATH_BA_INDEX(tid->seq_start, bf->bf_seqno);
1287 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
1288
1289 ASSERT(tid->tx_buf[cindex] == NULL);
1290 tid->tx_buf[cindex] = bf;
1291
1292 if (index >= ((tid->baw_tail - tid->baw_head) &
1293 (ATH_TID_MAX_BUFS - 1))) {
1294 tid->baw_tail = cindex;
1295 INCR(tid->baw_tail, ATH_TID_MAX_BUFS);
1296 }
1297 }
1298
1299 /*
1300 * Function to send an A-MPDU
1301 * NB: must be called with txq lock held
1302 */
1303
1304 static int ath_tx_send_ampdu(struct ath_softc *sc,
1305 struct ath_atx_tid *tid,
1306 struct list_head *bf_head,
1307 struct ath_tx_control *txctl)
1308 {
1309 struct ath_buf *bf;
1310 struct sk_buff *skb;
1311 struct ieee80211_tx_info *tx_info;
1312 struct ath_tx_info_priv *tx_info_priv;
1313
1314 BUG_ON(list_empty(bf_head));
1315
1316 bf = list_first_entry(bf_head, struct ath_buf, list);
1317 bf->bf_state.bf_type |= BUF_AMPDU;
1318
1319 /*
1320 * Do not queue to h/w when any of the following conditions is true:
1321 * - there are pending frames in software queue
1322 * - the TID is currently paused for ADDBA/BAR request
1323 * - seqno is not within block-ack window
1324 * - h/w queue depth exceeds low water mark
1325 */
1326 if (!list_empty(&tid->buf_q) || tid->paused ||
1327 !BAW_WITHIN(tid->seq_start, tid->baw_size, bf->bf_seqno) ||
1328 txctl->txq->axq_depth >= ATH_AGGR_MIN_QDEPTH) {
1329 /*
1330 * Add this frame to software queue for scheduling later
1331 * for aggregation.
1332 */
1333 list_splice_tail_init(bf_head, &tid->buf_q);
1334 ath_tx_queue_tid(txctl->txq, tid);
1335 return 0;
1336 }
1337
1338 skb = (struct sk_buff *)bf->bf_mpdu;
1339 tx_info = IEEE80211_SKB_CB(skb);
1340 /* XXX: HACK! */
1341 tx_info_priv = (struct ath_tx_info_priv *)tx_info->control.vif;
1342 memcpy(bf->bf_rcs, tx_info_priv->rcs, 4 * sizeof(tx_info_priv->rcs[0]));
1343
1344 /* Add sub-frame to BAW */
1345 ath_tx_addto_baw(sc, tid, bf);
1346
1347 /* Queue to h/w without aggregation */
1348 bf->bf_nframes = 1;
1349 bf->bf_lastbf = bf->bf_lastfrm; /* one single frame */
1350 ath_buf_set_rate(sc, bf);
1351 ath_tx_txqaddbuf(sc, txctl->txq, bf_head);
1352
1353 return 0;
1354 }
1355
1356 /*
1357 * looks up the rate
1358 * returns aggr limit based on lowest of the rates
1359 */
1360
1361 static u32 ath_lookup_rate(struct ath_softc *sc,
1362 struct ath_buf *bf,
1363 struct ath_atx_tid *tid)
1364 {
1365 const struct ath9k_rate_table *rt = sc->sc_currates;
1366 struct sk_buff *skb;
1367 struct ieee80211_tx_info *tx_info;
1368 struct ath_tx_info_priv *tx_info_priv;
1369 u32 max_4ms_framelen, frame_length;
1370 u16 aggr_limit, legacy = 0, maxampdu;
1371 int i;
1372
1373 skb = (struct sk_buff *)bf->bf_mpdu;
1374 tx_info = IEEE80211_SKB_CB(skb);
1375 tx_info_priv = (struct ath_tx_info_priv *)
1376 tx_info->control.vif; /* XXX: HACK! */
1377 memcpy(bf->bf_rcs,
1378 tx_info_priv->rcs, 4 * sizeof(tx_info_priv->rcs[0]));
1379
1380 /*
1381 * Find the lowest frame length among the rate series that will have a
1382 * 4ms transmit duration.
1383 * TODO - TXOP limit needs to be considered.
1384 */
1385 max_4ms_framelen = ATH_AMPDU_LIMIT_MAX;
1386
1387 for (i = 0; i < 4; i++) {
1388 if (bf->bf_rcs[i].tries) {
1389 frame_length = bf->bf_rcs[i].max_4ms_framelen;
1390
1391 if (rt->info[bf->bf_rcs[i].rix].phy != PHY_HT) {
1392 legacy = 1;
1393 break;
1394 }
1395
1396 max_4ms_framelen = min(max_4ms_framelen, frame_length);
1397 }
1398 }
1399
1400 /*
1401 * limit aggregate size by the minimum rate if rate selected is
1402 * not a probe rate, if rate selected is a probe rate then
1403 * avoid aggregation of this packet.
1404 */
1405 if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy)
1406 return 0;
1407
1408 aggr_limit = min(max_4ms_framelen,
1409 (u32)ATH_AMPDU_LIMIT_DEFAULT);
1410
1411 /*
1412 * h/w can accept aggregates upto 16 bit lengths (65535).
1413 * The IE, however can hold upto 65536, which shows up here
1414 * as zero. Ignore 65536 since we are constrained by hw.
1415 */
1416 maxampdu = tid->an->maxampdu;
1417 if (maxampdu)
1418 aggr_limit = min(aggr_limit, maxampdu);
1419
1420 return aggr_limit;
1421 }
1422
1423 /*
1424 * returns the number of delimiters to be added to
1425 * meet the minimum required mpdudensity.
1426 * caller should make sure that the rate is HT rate .
1427 */
1428
1429 static int ath_compute_num_delims(struct ath_softc *sc,
1430 struct ath_atx_tid *tid,
1431 struct ath_buf *bf,
1432 u16 frmlen)
1433 {
1434 const struct ath9k_rate_table *rt = sc->sc_currates;
1435 u32 nsymbits, nsymbols, mpdudensity;
1436 u16 minlen;
1437 u8 rc, flags, rix;
1438 int width, half_gi, ndelim, mindelim;
1439
1440 /* Select standard number of delimiters based on frame length alone */
1441 ndelim = ATH_AGGR_GET_NDELIM(frmlen);
1442
1443 /*
1444 * If encryption enabled, hardware requires some more padding between
1445 * subframes.
1446 * TODO - this could be improved to be dependent on the rate.
1447 * The hardware can keep up at lower rates, but not higher rates
1448 */
1449 if (bf->bf_keytype != ATH9K_KEY_TYPE_CLEAR)
1450 ndelim += ATH_AGGR_ENCRYPTDELIM;
1451
1452 /*
1453 * Convert desired mpdu density from microeconds to bytes based
1454 * on highest rate in rate series (i.e. first rate) to determine
1455 * required minimum length for subframe. Take into account
1456 * whether high rate is 20 or 40Mhz and half or full GI.
1457 */
1458 mpdudensity = tid->an->mpdudensity;
1459
1460 /*
1461 * If there is no mpdu density restriction, no further calculation
1462 * is needed.
1463 */
1464 if (mpdudensity == 0)
1465 return ndelim;
1466
1467 rix = bf->bf_rcs[0].rix;
1468 flags = bf->bf_rcs[0].flags;
1469 rc = rt->info[rix].rateCode;
1470 width = (flags & ATH_RC_CW40_FLAG) ? 1 : 0;
1471 half_gi = (flags & ATH_RC_SGI_FLAG) ? 1 : 0;
1472
1473 if (half_gi)
1474 nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(mpdudensity);
1475 else
1476 nsymbols = NUM_SYMBOLS_PER_USEC(mpdudensity);
1477
1478 if (nsymbols == 0)
1479 nsymbols = 1;
1480
1481 nsymbits = bits_per_symbol[HT_RC_2_MCS(rc)][width];
1482 minlen = (nsymbols * nsymbits) / BITS_PER_BYTE;
1483
1484 /* Is frame shorter than required minimum length? */
1485 if (frmlen < minlen) {
1486 /* Get the minimum number of delimiters required. */
1487 mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ;
1488 ndelim = max(mindelim, ndelim);
1489 }
1490
1491 return ndelim;
1492 }
1493
1494 /*
1495 * For aggregation from software buffer queue.
1496 * NB: must be called with txq lock held
1497 */
1498
1499 static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc,
1500 struct ath_atx_tid *tid,
1501 struct list_head *bf_q,
1502 struct ath_buf **bf_last,
1503 struct aggr_rifs_param *param,
1504 int *prev_frames)
1505 {
1506 #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
1507 struct ath_buf *bf, *tbf, *bf_first, *bf_prev = NULL;
1508 struct list_head bf_head;
1509 int rl = 0, nframes = 0, ndelim;
1510 u16 aggr_limit = 0, al = 0, bpad = 0,
1511 al_delta, h_baw = tid->baw_size / 2;
1512 enum ATH_AGGR_STATUS status = ATH_AGGR_DONE;
1513 int prev_al = 0, is_ds_rate = 0;
1514 INIT_LIST_HEAD(&bf_head);
1515
1516 BUG_ON(list_empty(&tid->buf_q));
1517
1518 bf_first = list_first_entry(&tid->buf_q, struct ath_buf, list);
1519
1520 do {
1521 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
1522
1523 /*
1524 * do not step over block-ack window
1525 */
1526 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, bf->bf_seqno)) {
1527 status = ATH_AGGR_BAW_CLOSED;
1528 break;
1529 }
1530
1531 if (!rl) {
1532 aggr_limit = ath_lookup_rate(sc, bf, tid);
1533 rl = 1;
1534 /*
1535 * Is rate dual stream
1536 */
1537 is_ds_rate =
1538 (bf->bf_rcs[0].flags & ATH_RC_DS_FLAG) ? 1 : 0;
1539 }
1540
1541 /*
1542 * do not exceed aggregation limit
1543 */
1544 al_delta = ATH_AGGR_DELIM_SZ + bf->bf_frmlen;
1545
1546 if (nframes && (aggr_limit <
1547 (al + bpad + al_delta + prev_al))) {
1548 status = ATH_AGGR_LIMITED;
1549 break;
1550 }
1551
1552 /*
1553 * do not exceed subframe limit
1554 */
1555 if ((nframes + *prev_frames) >=
1556 min((int)h_baw, ATH_AMPDU_SUBFRAME_DEFAULT)) {
1557 status = ATH_AGGR_LIMITED;
1558 break;
1559 }
1560
1561 /*
1562 * add padding for previous frame to aggregation length
1563 */
1564 al += bpad + al_delta;
1565
1566 /*
1567 * Get the delimiters needed to meet the MPDU
1568 * density for this node.
1569 */
1570 ndelim = ath_compute_num_delims(sc, tid, bf_first, bf->bf_frmlen);
1571
1572 bpad = PADBYTES(al_delta) + (ndelim << 2);
1573
1574 bf->bf_next = NULL;
1575 bf->bf_lastfrm->bf_desc->ds_link = 0;
1576
1577 /*
1578 * this packet is part of an aggregate
1579 * - remove all descriptors belonging to this frame from
1580 * software queue
1581 * - add it to block ack window
1582 * - set up descriptors for aggregation
1583 */
1584 list_cut_position(&bf_head, &tid->buf_q, &bf->bf_lastfrm->list);
1585 ath_tx_addto_baw(sc, tid, bf);
1586
1587 list_for_each_entry(tbf, &bf_head, list) {
1588 ath9k_hw_set11n_aggr_middle(sc->sc_ah,
1589 tbf->bf_desc, ndelim);
1590 }
1591
1592 /*
1593 * link buffers of this frame to the aggregate
1594 */
1595 list_splice_tail_init(&bf_head, bf_q);
1596 nframes++;
1597
1598 if (bf_prev) {
1599 bf_prev->bf_next = bf;
1600 bf_prev->bf_lastfrm->bf_desc->ds_link = bf->bf_daddr;
1601 }
1602 bf_prev = bf;
1603
1604 #ifdef AGGR_NOSHORT
1605 /*
1606 * terminate aggregation on a small packet boundary
1607 */
1608 if (bf->bf_frmlen < ATH_AGGR_MINPLEN) {
1609 status = ATH_AGGR_SHORTPKT;
1610 break;
1611 }
1612 #endif
1613 } while (!list_empty(&tid->buf_q));
1614
1615 bf_first->bf_al = al;
1616 bf_first->bf_nframes = nframes;
1617 *bf_last = bf_prev;
1618 return status;
1619 #undef PADBYTES
1620 }
1621
1622 /*
1623 * process pending frames possibly doing a-mpdu aggregation
1624 * NB: must be called with txq lock held
1625 */
1626
1627 static void ath_tx_sched_aggr(struct ath_softc *sc,
1628 struct ath_txq *txq, struct ath_atx_tid *tid)
1629 {
1630 struct ath_buf *bf, *tbf, *bf_last, *bf_lastaggr = NULL;
1631 enum ATH_AGGR_STATUS status;
1632 struct list_head bf_q;
1633 struct aggr_rifs_param param = {0, 0, 0, 0, NULL};
1634 int prev_frames = 0;
1635
1636 do {
1637 if (list_empty(&tid->buf_q))
1638 return;
1639
1640 INIT_LIST_HEAD(&bf_q);
1641
1642 status = ath_tx_form_aggr(sc, tid, &bf_q, &bf_lastaggr, &param,
1643 &prev_frames);
1644
1645 /*
1646 * no frames picked up to be aggregated; block-ack
1647 * window is not open
1648 */
1649 if (list_empty(&bf_q))
1650 break;
1651
1652 bf = list_first_entry(&bf_q, struct ath_buf, list);
1653 bf_last = list_entry(bf_q.prev, struct ath_buf, list);
1654 bf->bf_lastbf = bf_last;
1655
1656 /*
1657 * if only one frame, send as non-aggregate
1658 */
1659 if (bf->bf_nframes == 1) {
1660 ASSERT(bf->bf_lastfrm == bf_last);
1661
1662 bf->bf_state.bf_type &= ~BUF_AGGR;
1663 /*
1664 * clear aggr bits for every descriptor
1665 * XXX TODO: is there a way to optimize it?
1666 */
1667 list_for_each_entry(tbf, &bf_q, list) {
1668 ath9k_hw_clr11n_aggr(sc->sc_ah, tbf->bf_desc);
1669 }
1670
1671 ath_buf_set_rate(sc, bf);
1672 ath_tx_txqaddbuf(sc, txq, &bf_q);
1673 continue;
1674 }
1675
1676 /*
1677 * setup first desc with rate and aggr info
1678 */
1679 bf->bf_state.bf_type |= BUF_AGGR;
1680 ath_buf_set_rate(sc, bf);
1681 ath9k_hw_set11n_aggr_first(sc->sc_ah, bf->bf_desc, bf->bf_al);
1682
1683 /*
1684 * anchor last frame of aggregate correctly
1685 */
1686 ASSERT(bf_lastaggr);
1687 ASSERT(bf_lastaggr->bf_lastfrm == bf_last);
1688 tbf = bf_lastaggr;
1689 ath9k_hw_set11n_aggr_last(sc->sc_ah, tbf->bf_desc);
1690
1691 /* XXX: We don't enter into this loop, consider removing this */
1692 while (!list_empty(&bf_q) && !list_is_last(&tbf->list, &bf_q)) {
1693 tbf = list_entry(tbf->list.next, struct ath_buf, list);
1694 ath9k_hw_set11n_aggr_last(sc->sc_ah, tbf->bf_desc);
1695 }
1696
1697 txq->axq_aggr_depth++;
1698
1699 /*
1700 * Normal aggregate, queue to hardware
1701 */
1702 ath_tx_txqaddbuf(sc, txq, &bf_q);
1703
1704 } while (txq->axq_depth < ATH_AGGR_MIN_QDEPTH &&
1705 status != ATH_AGGR_BAW_CLOSED);
1706 }
1707
1708 /* Called with txq lock held */
1709
1710 static void ath_tid_drain(struct ath_softc *sc,
1711 struct ath_txq *txq,
1712 struct ath_atx_tid *tid)
1713
1714 {
1715 struct ath_buf *bf;
1716 struct list_head bf_head;
1717 INIT_LIST_HEAD(&bf_head);
1718
1719 for (;;) {
1720 if (list_empty(&tid->buf_q))
1721 break;
1722 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
1723
1724 list_cut_position(&bf_head, &tid->buf_q, &bf->bf_lastfrm->list);
1725
1726 /* update baw for software retried frame */
1727 if (bf_isretried(bf))
1728 ath_tx_update_baw(sc, tid, bf->bf_seqno);
1729
1730 /*
1731 * do not indicate packets while holding txq spinlock.
1732 * unlock is intentional here
1733 */
1734 spin_unlock(&txq->axq_lock);
1735
1736 /* complete this sub-frame */
1737 ath_tx_complete_buf(sc, bf, &bf_head, 0, 0);
1738
1739 spin_lock(&txq->axq_lock);
1740 }
1741
1742 /*
1743 * TODO: For frame(s) that are in the retry state, we will reuse the
1744 * sequence number(s) without setting the retry bit. The
1745 * alternative is to give up on these and BAR the receiver's window
1746 * forward.
1747 */
1748 tid->seq_next = tid->seq_start;
1749 tid->baw_tail = tid->baw_head;
1750 }
1751
1752 /*
1753 * Drain all pending buffers
1754 * NB: must be called with txq lock held
1755 */
1756
1757 static void ath_txq_drain_pending_buffers(struct ath_softc *sc,
1758 struct ath_txq *txq)
1759 {
1760 struct ath_atx_ac *ac, *ac_tmp;
1761 struct ath_atx_tid *tid, *tid_tmp;
1762
1763 list_for_each_entry_safe(ac, ac_tmp, &txq->axq_acq, list) {
1764 list_del(&ac->list);
1765 ac->sched = false;
1766 list_for_each_entry_safe(tid, tid_tmp, &ac->tid_q, list) {
1767 list_del(&tid->list);
1768 tid->sched = false;
1769 ath_tid_drain(sc, txq, tid);
1770 }
1771 }
1772 }
1773
1774 static void ath_tx_setup_buffer(struct ath_softc *sc, struct ath_buf *bf,
1775 struct sk_buff *skb, struct scatterlist *sg,
1776 struct ath_tx_control *txctl)
1777 {
1778 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1779 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1780 struct ath_tx_info_priv *tx_info_priv;
1781 struct ath_rc_series *rcs;
1782 int hdrlen;
1783 __le16 fc;
1784
1785 tx_info_priv = (struct ath_tx_info_priv *)tx_info->control.vif;
1786 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1787 fc = hdr->frame_control;
1788 rcs = tx_info_priv->rcs;
1789
1790 ATH_TXBUF_RESET(bf);
1791
1792 /* Frame type */
1793
1794 bf->bf_frmlen = skb->len + FCS_LEN - (hdrlen & 3);
1795
1796 ieee80211_is_data(fc) ?
1797 (bf->bf_state.bf_type |= BUF_DATA) :
1798 (bf->bf_state.bf_type &= ~BUF_DATA);
1799 ieee80211_is_back_req(fc) ?
1800 (bf->bf_state.bf_type |= BUF_BAR) :
1801 (bf->bf_state.bf_type &= ~BUF_BAR);
1802 ieee80211_is_pspoll(fc) ?
1803 (bf->bf_state.bf_type |= BUF_PSPOLL) :
1804 (bf->bf_state.bf_type &= ~BUF_PSPOLL);
1805 (sc->sc_flags & SC_OP_PREAMBLE_SHORT) ?
1806 (bf->bf_state.bf_type |= BUF_SHORT_PREAMBLE) :
1807 (bf->bf_state.bf_type &= ~BUF_SHORT_PREAMBLE);
1808 (sc->hw->conf.ht.enabled &&
1809 (tx_info->flags & IEEE80211_TX_CTL_AMPDU)) ?
1810 (bf->bf_state.bf_type |= BUF_HT) :
1811 (bf->bf_state.bf_type &= ~BUF_HT);
1812
1813 bf->bf_flags = setup_tx_flags(sc, skb, txctl->txq);
1814
1815 /* Crypto */
1816
1817 bf->bf_keytype = get_hw_crypto_keytype(skb);
1818
1819 if (bf->bf_keytype != ATH9K_KEY_TYPE_CLEAR) {
1820 bf->bf_frmlen += tx_info->control.hw_key->icv_len;
1821 bf->bf_keyix = tx_info->control.hw_key->hw_key_idx;
1822 } else {
1823 bf->bf_keyix = ATH9K_TXKEYIX_INVALID;
1824 }
1825
1826 /* Rate series */
1827
1828 setup_rate_retries(sc, skb);
1829
1830 bf->bf_rcs[0] = rcs[0];
1831 bf->bf_rcs[1] = rcs[1];
1832 bf->bf_rcs[2] = rcs[2];
1833 bf->bf_rcs[3] = rcs[3];
1834
1835 /* Assign seqno, tidno */
1836
1837 if (bf_isht(bf) && (sc->sc_flags & SC_OP_TXAGGR))
1838 assign_aggr_tid_seqno(skb, bf);
1839
1840 /* DMA setup */
1841
1842 bf->bf_mpdu = skb;
1843 bf->bf_dmacontext = pci_map_single(sc->pdev, skb->data,
1844 skb->len, PCI_DMA_TODEVICE);
1845 bf->bf_buf_addr = bf->bf_dmacontext;
1846 }
1847
1848 /* FIXME: tx power */
1849 static void ath_tx_start_dma(struct ath_softc *sc, struct ath_buf *bf,
1850 struct scatterlist *sg, u32 n_sg,
1851 struct ath_tx_control *txctl)
1852 {
1853 struct sk_buff *skb = (struct sk_buff *)bf->bf_mpdu;
1854 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1855 struct ath_node *an = NULL;
1856 struct list_head bf_head;
1857 struct ath_desc *ds;
1858 struct ath_atx_tid *tid;
1859 struct ath_hal *ah = sc->sc_ah;
1860 int frm_type;
1861
1862 frm_type = get_hw_packet_type(skb);
1863
1864 INIT_LIST_HEAD(&bf_head);
1865 list_add_tail(&bf->list, &bf_head);
1866
1867 /* setup descriptor */
1868
1869 ds = bf->bf_desc;
1870 ds->ds_link = 0;
1871 ds->ds_data = bf->bf_buf_addr;
1872
1873 /* Formulate first tx descriptor with tx controls */
1874
1875 ath9k_hw_set11n_txdesc(ah, ds, bf->bf_frmlen, frm_type, MAX_RATE_POWER,
1876 bf->bf_keyix, bf->bf_keytype, bf->bf_flags);
1877
1878 ath9k_hw_filltxdesc(ah, ds,
1879 sg_dma_len(sg), /* segment length */
1880 true, /* first segment */
1881 (n_sg == 1) ? true : false, /* last segment */
1882 ds); /* first descriptor */
1883
1884 bf->bf_lastfrm = bf;
1885
1886 spin_lock_bh(&txctl->txq->axq_lock);
1887
1888 if (bf_isht(bf) && (sc->sc_flags & SC_OP_TXAGGR) &&
1889 tx_info->control.sta) {
1890 an = (struct ath_node *)tx_info->control.sta->drv_priv;
1891 tid = ATH_AN_2_TID(an, bf->bf_tidno);
1892
1893 if (ath_aggr_query(sc, an, bf->bf_tidno)) {
1894 /*
1895 * Try aggregation if it's a unicast data frame
1896 * and the destination is HT capable.
1897 */
1898 ath_tx_send_ampdu(sc, tid, &bf_head, txctl);
1899 } else {
1900 /*
1901 * Send this frame as regular when ADDBA
1902 * exchange is neither complete nor pending.
1903 */
1904 ath_tx_send_normal(sc, txctl->txq,
1905 tid, &bf_head);
1906 }
1907 } else {
1908 bf->bf_lastbf = bf;
1909 bf->bf_nframes = 1;
1910
1911 ath_buf_set_rate(sc, bf);
1912 ath_tx_txqaddbuf(sc, txctl->txq, &bf_head);
1913 }
1914
1915 spin_unlock_bh(&txctl->txq->axq_lock);
1916 }
1917
1918 int ath_tx_start(struct ath_softc *sc, struct sk_buff *skb,
1919 struct ath_tx_control *txctl)
1920 {
1921 struct ath_buf *bf;
1922 struct scatterlist sg;
1923
1924 /* Check if a tx buffer is available */
1925
1926 bf = ath_tx_get_buffer(sc);
1927 if (!bf) {
1928 DPRINTF(sc, ATH_DBG_XMIT, "%s: TX buffers are full\n",
1929 __func__);
1930 return -1;
1931 }
1932
1933 ath_tx_setup_buffer(sc, bf, skb, &sg, txctl);
1934
1935 /* Setup S/G */
1936
1937 memset(&sg, 0, sizeof(struct scatterlist));
1938 sg_dma_address(&sg) = bf->bf_dmacontext;
1939 sg_dma_len(&sg) = skb->len;
1940
1941 ath_tx_start_dma(sc, bf, &sg, 1, txctl);
1942
1943 return 0;
1944 }
1945
1946 /* Initialize TX queue and h/w */
1947
1948 int ath_tx_init(struct ath_softc *sc, int nbufs)
1949 {
1950 int error = 0;
1951
1952 do {
1953 spin_lock_init(&sc->sc_txbuflock);
1954
1955 /* Setup tx descriptors */
1956 error = ath_descdma_setup(sc, &sc->sc_txdma, &sc->sc_txbuf,
1957 "tx", nbufs, 1);
1958 if (error != 0) {
1959 DPRINTF(sc, ATH_DBG_FATAL,
1960 "%s: failed to allocate tx descriptors: %d\n",
1961 __func__, error);
1962 break;
1963 }
1964
1965 /* XXX allocate beacon state together with vap */
1966 error = ath_descdma_setup(sc, &sc->sc_bdma, &sc->sc_bbuf,
1967 "beacon", ATH_BCBUF, 1);
1968 if (error != 0) {
1969 DPRINTF(sc, ATH_DBG_FATAL,
1970 "%s: failed to allocate "
1971 "beacon descripotrs: %d\n",
1972 __func__, error);
1973 break;
1974 }
1975
1976 } while (0);
1977
1978 if (error != 0)
1979 ath_tx_cleanup(sc);
1980
1981 return error;
1982 }
1983
1984 /* Reclaim all tx queue resources */
1985
1986 int ath_tx_cleanup(struct ath_softc *sc)
1987 {
1988 /* cleanup beacon descriptors */
1989 if (sc->sc_bdma.dd_desc_len != 0)
1990 ath_descdma_cleanup(sc, &sc->sc_bdma, &sc->sc_bbuf);
1991
1992 /* cleanup tx descriptors */
1993 if (sc->sc_txdma.dd_desc_len != 0)
1994 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf);
1995
1996 return 0;
1997 }
1998
1999 /* Setup a h/w transmit queue */
2000
2001 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
2002 {
2003 struct ath_hal *ah = sc->sc_ah;
2004 struct ath9k_tx_queue_info qi;
2005 int qnum;
2006
2007 memset(&qi, 0, sizeof(qi));
2008 qi.tqi_subtype = subtype;
2009 qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT;
2010 qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
2011 qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT;
2012 qi.tqi_physCompBuf = 0;
2013
2014 /*
2015 * Enable interrupts only for EOL and DESC conditions.
2016 * We mark tx descriptors to receive a DESC interrupt
2017 * when a tx queue gets deep; otherwise waiting for the
2018 * EOL to reap descriptors. Note that this is done to
2019 * reduce interrupt load and this only defers reaping
2020 * descriptors, never transmitting frames. Aside from
2021 * reducing interrupts this also permits more concurrency.
2022 * The only potential downside is if the tx queue backs
2023 * up in which case the top half of the kernel may backup
2024 * due to a lack of tx descriptors.
2025 *
2026 * The UAPSD queue is an exception, since we take a desc-
2027 * based intr on the EOSP frames.
2028 */
2029 if (qtype == ATH9K_TX_QUEUE_UAPSD)
2030 qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE;
2031 else
2032 qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE |
2033 TXQ_FLAG_TXDESCINT_ENABLE;
2034 qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi);
2035 if (qnum == -1) {
2036 /*
2037 * NB: don't print a message, this happens
2038 * normally on parts with too few tx queues
2039 */
2040 return NULL;
2041 }
2042 if (qnum >= ARRAY_SIZE(sc->sc_txq)) {
2043 DPRINTF(sc, ATH_DBG_FATAL,
2044 "%s: hal qnum %u out of range, max %u!\n",
2045 __func__, qnum, (unsigned int)ARRAY_SIZE(sc->sc_txq));
2046 ath9k_hw_releasetxqueue(ah, qnum);
2047 return NULL;
2048 }
2049 if (!ATH_TXQ_SETUP(sc, qnum)) {
2050 struct ath_txq *txq = &sc->sc_txq[qnum];
2051
2052 txq->axq_qnum = qnum;
2053 txq->axq_link = NULL;
2054 INIT_LIST_HEAD(&txq->axq_q);
2055 INIT_LIST_HEAD(&txq->axq_acq);
2056 spin_lock_init(&txq->axq_lock);
2057 txq->axq_depth = 0;
2058 txq->axq_aggr_depth = 0;
2059 txq->axq_totalqueued = 0;
2060 txq->axq_linkbuf = NULL;
2061 sc->sc_txqsetup |= 1<<qnum;
2062 }
2063 return &sc->sc_txq[qnum];
2064 }
2065
2066 /* Reclaim resources for a setup queue */
2067
2068 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
2069 {
2070 ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum);
2071 sc->sc_txqsetup &= ~(1<<txq->axq_qnum);
2072 }
2073
2074 /*
2075 * Setup a hardware data transmit queue for the specified
2076 * access control. The hal may not support all requested
2077 * queues in which case it will return a reference to a
2078 * previously setup queue. We record the mapping from ac's
2079 * to h/w queues for use by ath_tx_start and also track
2080 * the set of h/w queues being used to optimize work in the
2081 * transmit interrupt handler and related routines.
2082 */
2083
2084 int ath_tx_setup(struct ath_softc *sc, int haltype)
2085 {
2086 struct ath_txq *txq;
2087
2088 if (haltype >= ARRAY_SIZE(sc->sc_haltype2q)) {
2089 DPRINTF(sc, ATH_DBG_FATAL,
2090 "%s: HAL AC %u out of range, max %zu!\n",
2091 __func__, haltype, ARRAY_SIZE(sc->sc_haltype2q));
2092 return 0;
2093 }
2094 txq = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, haltype);
2095 if (txq != NULL) {
2096 sc->sc_haltype2q[haltype] = txq->axq_qnum;
2097 return 1;
2098 } else
2099 return 0;
2100 }
2101
2102 int ath_tx_get_qnum(struct ath_softc *sc, int qtype, int haltype)
2103 {
2104 int qnum;
2105
2106 switch (qtype) {
2107 case ATH9K_TX_QUEUE_DATA:
2108 if (haltype >= ARRAY_SIZE(sc->sc_haltype2q)) {
2109 DPRINTF(sc, ATH_DBG_FATAL,
2110 "%s: HAL AC %u out of range, max %zu!\n",
2111 __func__,
2112 haltype, ARRAY_SIZE(sc->sc_haltype2q));
2113 return -1;
2114 }
2115 qnum = sc->sc_haltype2q[haltype];
2116 break;
2117 case ATH9K_TX_QUEUE_BEACON:
2118 qnum = sc->sc_bhalq;
2119 break;
2120 case ATH9K_TX_QUEUE_CAB:
2121 qnum = sc->sc_cabq->axq_qnum;
2122 break;
2123 default:
2124 qnum = -1;
2125 }
2126 return qnum;
2127 }
2128
2129 /* Get a transmit queue, if available */
2130
2131 struct ath_txq *ath_test_get_txq(struct ath_softc *sc, struct sk_buff *skb)
2132 {
2133 struct ath_txq *txq = NULL;
2134 int qnum;
2135
2136 qnum = ath_get_hal_qnum(skb_get_queue_mapping(skb), sc);
2137 txq = &sc->sc_txq[qnum];
2138
2139 spin_lock_bh(&txq->axq_lock);
2140
2141 /* Try to avoid running out of descriptors */
2142 if (txq->axq_depth >= (ATH_TXBUF - 20)) {
2143 DPRINTF(sc, ATH_DBG_FATAL,
2144 "%s: TX queue: %d is full, depth: %d\n",
2145 __func__, qnum, txq->axq_depth);
2146 ieee80211_stop_queue(sc->hw, skb_get_queue_mapping(skb));
2147 txq->stopped = 1;
2148 spin_unlock_bh(&txq->axq_lock);
2149 return NULL;
2150 }
2151
2152 spin_unlock_bh(&txq->axq_lock);
2153
2154 return txq;
2155 }
2156
2157 /* Update parameters for a transmit queue */
2158
2159 int ath_txq_update(struct ath_softc *sc, int qnum,
2160 struct ath9k_tx_queue_info *qinfo)
2161 {
2162 struct ath_hal *ah = sc->sc_ah;
2163 int error = 0;
2164 struct ath9k_tx_queue_info qi;
2165
2166 if (qnum == sc->sc_bhalq) {
2167 /*
2168 * XXX: for beacon queue, we just save the parameter.
2169 * It will be picked up by ath_beaconq_config when
2170 * it's necessary.
2171 */
2172 sc->sc_beacon_qi = *qinfo;
2173 return 0;
2174 }
2175
2176 ASSERT(sc->sc_txq[qnum].axq_qnum == qnum);
2177
2178 ath9k_hw_get_txq_props(ah, qnum, &qi);
2179 qi.tqi_aifs = qinfo->tqi_aifs;
2180 qi.tqi_cwmin = qinfo->tqi_cwmin;
2181 qi.tqi_cwmax = qinfo->tqi_cwmax;
2182 qi.tqi_burstTime = qinfo->tqi_burstTime;
2183 qi.tqi_readyTime = qinfo->tqi_readyTime;
2184
2185 if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) {
2186 DPRINTF(sc, ATH_DBG_FATAL,
2187 "%s: unable to update hardware queue %u!\n",
2188 __func__, qnum);
2189 error = -EIO;
2190 } else {
2191 ath9k_hw_resettxqueue(ah, qnum); /* push to h/w */
2192 }
2193
2194 return error;
2195 }
2196
2197 int ath_cabq_update(struct ath_softc *sc)
2198 {
2199 struct ath9k_tx_queue_info qi;
2200 int qnum = sc->sc_cabq->axq_qnum;
2201 struct ath_beacon_config conf;
2202
2203 ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi);
2204 /*
2205 * Ensure the readytime % is within the bounds.
2206 */
2207 if (sc->sc_config.cabqReadytime < ATH9K_READY_TIME_LO_BOUND)
2208 sc->sc_config.cabqReadytime = ATH9K_READY_TIME_LO_BOUND;
2209 else if (sc->sc_config.cabqReadytime > ATH9K_READY_TIME_HI_BOUND)
2210 sc->sc_config.cabqReadytime = ATH9K_READY_TIME_HI_BOUND;
2211
2212 ath_get_beaconconfig(sc, ATH_IF_ID_ANY, &conf);
2213 qi.tqi_readyTime =
2214 (conf.beacon_interval * sc->sc_config.cabqReadytime) / 100;
2215 ath_txq_update(sc, qnum, &qi);
2216
2217 return 0;
2218 }
2219
2220 /* Deferred processing of transmit interrupt */
2221
2222 void ath_tx_tasklet(struct ath_softc *sc)
2223 {
2224 int i;
2225 u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1);
2226
2227 ath9k_hw_gettxintrtxqs(sc->sc_ah, &qcumask);
2228
2229 /*
2230 * Process each active queue.
2231 */
2232 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2233 if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i)))
2234 ath_tx_processq(sc, &sc->sc_txq[i]);
2235 }
2236 }
2237
2238 void ath_tx_draintxq(struct ath_softc *sc,
2239 struct ath_txq *txq, bool retry_tx)
2240 {
2241 struct ath_buf *bf, *lastbf;
2242 struct list_head bf_head;
2243
2244 INIT_LIST_HEAD(&bf_head);
2245
2246 /*
2247 * NB: this assumes output has been stopped and
2248 * we do not need to block ath_tx_tasklet
2249 */
2250 for (;;) {
2251 spin_lock_bh(&txq->axq_lock);
2252
2253 if (list_empty(&txq->axq_q)) {
2254 txq->axq_link = NULL;
2255 txq->axq_linkbuf = NULL;
2256 spin_unlock_bh(&txq->axq_lock);
2257 break;
2258 }
2259
2260 bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
2261
2262 if (bf->bf_status & ATH_BUFSTATUS_STALE) {
2263 list_del(&bf->list);
2264 spin_unlock_bh(&txq->axq_lock);
2265
2266 spin_lock_bh(&sc->sc_txbuflock);
2267 list_add_tail(&bf->list, &sc->sc_txbuf);
2268 spin_unlock_bh(&sc->sc_txbuflock);
2269 continue;
2270 }
2271
2272 lastbf = bf->bf_lastbf;
2273 if (!retry_tx)
2274 lastbf->bf_desc->ds_txstat.ts_flags =
2275 ATH9K_TX_SW_ABORTED;
2276
2277 /* remove ath_buf's of the same mpdu from txq */
2278 list_cut_position(&bf_head, &txq->axq_q, &lastbf->list);
2279 txq->axq_depth--;
2280
2281 spin_unlock_bh(&txq->axq_lock);
2282
2283 if (bf_isampdu(bf))
2284 ath_tx_complete_aggr_rifs(sc, txq, bf, &bf_head, 0);
2285 else
2286 ath_tx_complete_buf(sc, bf, &bf_head, 0, 0);
2287 }
2288
2289 /* flush any pending frames if aggregation is enabled */
2290 if (sc->sc_flags & SC_OP_TXAGGR) {
2291 if (!retry_tx) {
2292 spin_lock_bh(&txq->axq_lock);
2293 ath_txq_drain_pending_buffers(sc, txq);
2294 spin_unlock_bh(&txq->axq_lock);
2295 }
2296 }
2297 }
2298
2299 /* Drain the transmit queues and reclaim resources */
2300
2301 void ath_draintxq(struct ath_softc *sc, bool retry_tx)
2302 {
2303 /* stop beacon queue. The beacon will be freed when
2304 * we go to INIT state */
2305 if (!(sc->sc_flags & SC_OP_INVALID)) {
2306 (void) ath9k_hw_stoptxdma(sc->sc_ah, sc->sc_bhalq);
2307 DPRINTF(sc, ATH_DBG_XMIT, "%s: beacon queue %x\n", __func__,
2308 ath9k_hw_gettxbuf(sc->sc_ah, sc->sc_bhalq));
2309 }
2310
2311 ath_drain_txdataq(sc, retry_tx);
2312 }
2313
2314 u32 ath_txq_depth(struct ath_softc *sc, int qnum)
2315 {
2316 return sc->sc_txq[qnum].axq_depth;
2317 }
2318
2319 u32 ath_txq_aggr_depth(struct ath_softc *sc, int qnum)
2320 {
2321 return sc->sc_txq[qnum].axq_aggr_depth;
2322 }
2323
2324 bool ath_tx_aggr_check(struct ath_softc *sc, struct ath_node *an, u8 tidno)
2325 {
2326 struct ath_atx_tid *txtid;
2327
2328 if (!(sc->sc_flags & SC_OP_TXAGGR))
2329 return false;
2330
2331 txtid = ATH_AN_2_TID(an, tidno);
2332
2333 if (!(txtid->state & AGGR_ADDBA_COMPLETE)) {
2334 if (!(txtid->state & AGGR_ADDBA_PROGRESS) &&
2335 (txtid->addba_exchangeattempts < ADDBA_EXCHANGE_ATTEMPTS)) {
2336 txtid->addba_exchangeattempts++;
2337 return true;
2338 }
2339 }
2340
2341 return false;
2342 }
2343
2344 /* Start TX aggregation */
2345
2346 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
2347 u16 tid, u16 *ssn)
2348 {
2349 struct ath_atx_tid *txtid;
2350 struct ath_node *an;
2351
2352 an = (struct ath_node *)sta->drv_priv;
2353
2354 if (sc->sc_flags & SC_OP_TXAGGR) {
2355 txtid = ATH_AN_2_TID(an, tid);
2356 txtid->state |= AGGR_ADDBA_PROGRESS;
2357 ath_tx_pause_tid(sc, txtid);
2358 }
2359
2360 return 0;
2361 }
2362
2363 /* Stop tx aggregation */
2364
2365 int ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
2366 {
2367 struct ath_node *an = (struct ath_node *)sta->drv_priv;
2368
2369 ath_tx_aggr_teardown(sc, an, tid);
2370 return 0;
2371 }
2372
2373 /* Resume tx aggregation */
2374
2375 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
2376 {
2377 struct ath_atx_tid *txtid;
2378 struct ath_node *an;
2379
2380 an = (struct ath_node *)sta->drv_priv;
2381
2382 if (sc->sc_flags & SC_OP_TXAGGR) {
2383 txtid = ATH_AN_2_TID(an, tid);
2384 txtid->baw_size =
2385 IEEE80211_MIN_AMPDU_BUF << sta->ht_cap.ampdu_factor;
2386 txtid->state |= AGGR_ADDBA_COMPLETE;
2387 txtid->state &= ~AGGR_ADDBA_PROGRESS;
2388 ath_tx_resume_tid(sc, txtid);
2389 }
2390 }
2391
2392 /*
2393 * Performs transmit side cleanup when TID changes from aggregated to
2394 * unaggregated.
2395 * - Pause the TID and mark cleanup in progress
2396 * - Discard all retry frames from the s/w queue.
2397 */
2398
2399 void ath_tx_aggr_teardown(struct ath_softc *sc, struct ath_node *an, u8 tid)
2400 {
2401 struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid);
2402 struct ath_txq *txq = &sc->sc_txq[txtid->ac->qnum];
2403 struct ath_buf *bf;
2404 struct list_head bf_head;
2405 INIT_LIST_HEAD(&bf_head);
2406
2407 DPRINTF(sc, ATH_DBG_AGGR, "%s: teardown TX aggregation\n", __func__);
2408
2409 if (txtid->state & AGGR_CLEANUP) /* cleanup is in progress */
2410 return;
2411
2412 if (!(txtid->state & AGGR_ADDBA_COMPLETE)) {
2413 txtid->addba_exchangeattempts = 0;
2414 return;
2415 }
2416
2417 /* TID must be paused first */
2418 ath_tx_pause_tid(sc, txtid);
2419
2420 /* drop all software retried frames and mark this TID */
2421 spin_lock_bh(&txq->axq_lock);
2422 while (!list_empty(&txtid->buf_q)) {
2423 bf = list_first_entry(&txtid->buf_q, struct ath_buf, list);
2424 if (!bf_isretried(bf)) {
2425 /*
2426 * NB: it's based on the assumption that
2427 * software retried frame will always stay
2428 * at the head of software queue.
2429 */
2430 break;
2431 }
2432 list_cut_position(&bf_head,
2433 &txtid->buf_q, &bf->bf_lastfrm->list);
2434 ath_tx_update_baw(sc, txtid, bf->bf_seqno);
2435
2436 /* complete this sub-frame */
2437 ath_tx_complete_buf(sc, bf, &bf_head, 0, 0);
2438 }
2439
2440 if (txtid->baw_head != txtid->baw_tail) {
2441 spin_unlock_bh(&txq->axq_lock);
2442 txtid->state |= AGGR_CLEANUP;
2443 } else {
2444 txtid->state &= ~AGGR_ADDBA_COMPLETE;
2445 txtid->addba_exchangeattempts = 0;
2446 spin_unlock_bh(&txq->axq_lock);
2447 ath_tx_flush_tid(sc, txtid);
2448 }
2449 }
2450
2451 /*
2452 * Tx scheduling logic
2453 * NB: must be called with txq lock held
2454 */
2455
2456 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq)
2457 {
2458 struct ath_atx_ac *ac;
2459 struct ath_atx_tid *tid;
2460
2461 /* nothing to schedule */
2462 if (list_empty(&txq->axq_acq))
2463 return;
2464 /*
2465 * get the first node/ac pair on the queue
2466 */
2467 ac = list_first_entry(&txq->axq_acq, struct ath_atx_ac, list);
2468 list_del(&ac->list);
2469 ac->sched = false;
2470
2471 /*
2472 * process a single tid per destination
2473 */
2474 do {
2475 /* nothing to schedule */
2476 if (list_empty(&ac->tid_q))
2477 return;
2478
2479 tid = list_first_entry(&ac->tid_q, struct ath_atx_tid, list);
2480 list_del(&tid->list);
2481 tid->sched = false;
2482
2483 if (tid->paused) /* check next tid to keep h/w busy */
2484 continue;
2485
2486 if ((txq->axq_depth % 2) == 0)
2487 ath_tx_sched_aggr(sc, txq, tid);
2488
2489 /*
2490 * add tid to round-robin queue if more frames
2491 * are pending for the tid
2492 */
2493 if (!list_empty(&tid->buf_q))
2494 ath_tx_queue_tid(txq, tid);
2495
2496 /* only schedule one TID at a time */
2497 break;
2498 } while (!list_empty(&ac->tid_q));
2499
2500 /*
2501 * schedule AC if more TIDs need processing
2502 */
2503 if (!list_empty(&ac->tid_q)) {
2504 /*
2505 * add dest ac to txq if not already added
2506 */
2507 if (!ac->sched) {
2508 ac->sched = true;
2509 list_add_tail(&ac->list, &txq->axq_acq);
2510 }
2511 }
2512 }
2513
2514 /* Initialize per-node transmit state */
2515
2516 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an)
2517 {
2518 struct ath_atx_tid *tid;
2519 struct ath_atx_ac *ac;
2520 int tidno, acno;
2521
2522 /*
2523 * Init per tid tx state
2524 */
2525 for (tidno = 0, tid = &an->an_aggr.tx.tid[tidno];
2526 tidno < WME_NUM_TID;
2527 tidno++, tid++) {
2528 tid->an = an;
2529 tid->tidno = tidno;
2530 tid->seq_start = tid->seq_next = 0;
2531 tid->baw_size = WME_MAX_BA;
2532 tid->baw_head = tid->baw_tail = 0;
2533 tid->sched = false;
2534 tid->paused = false;
2535 tid->state &= ~AGGR_CLEANUP;
2536 INIT_LIST_HEAD(&tid->buf_q);
2537
2538 acno = TID_TO_WME_AC(tidno);
2539 tid->ac = &an->an_aggr.tx.ac[acno];
2540
2541 /* ADDBA state */
2542 tid->state &= ~AGGR_ADDBA_COMPLETE;
2543 tid->state &= ~AGGR_ADDBA_PROGRESS;
2544 tid->addba_exchangeattempts = 0;
2545 }
2546
2547 /*
2548 * Init per ac tx state
2549 */
2550 for (acno = 0, ac = &an->an_aggr.tx.ac[acno];
2551 acno < WME_NUM_AC; acno++, ac++) {
2552 ac->sched = false;
2553 INIT_LIST_HEAD(&ac->tid_q);
2554
2555 switch (acno) {
2556 case WME_AC_BE:
2557 ac->qnum = ath_tx_get_qnum(sc,
2558 ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BE);
2559 break;
2560 case WME_AC_BK:
2561 ac->qnum = ath_tx_get_qnum(sc,
2562 ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BK);
2563 break;
2564 case WME_AC_VI:
2565 ac->qnum = ath_tx_get_qnum(sc,
2566 ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_VI);
2567 break;
2568 case WME_AC_VO:
2569 ac->qnum = ath_tx_get_qnum(sc,
2570 ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_VO);
2571 break;
2572 }
2573 }
2574 }
2575
2576 /* Cleanupthe pending buffers for the node. */
2577
2578 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an)
2579 {
2580 int i;
2581 struct ath_atx_ac *ac, *ac_tmp;
2582 struct ath_atx_tid *tid, *tid_tmp;
2583 struct ath_txq *txq;
2584 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2585 if (ATH_TXQ_SETUP(sc, i)) {
2586 txq = &sc->sc_txq[i];
2587
2588 spin_lock(&txq->axq_lock);
2589
2590 list_for_each_entry_safe(ac,
2591 ac_tmp, &txq->axq_acq, list) {
2592 tid = list_first_entry(&ac->tid_q,
2593 struct ath_atx_tid, list);
2594 if (tid && tid->an != an)
2595 continue;
2596 list_del(&ac->list);
2597 ac->sched = false;
2598
2599 list_for_each_entry_safe(tid,
2600 tid_tmp, &ac->tid_q, list) {
2601 list_del(&tid->list);
2602 tid->sched = false;
2603 ath_tid_drain(sc, txq, tid);
2604 tid->state &= ~AGGR_ADDBA_COMPLETE;
2605 tid->addba_exchangeattempts = 0;
2606 tid->state &= ~AGGR_CLEANUP;
2607 }
2608 }
2609
2610 spin_unlock(&txq->axq_lock);
2611 }
2612 }
2613 }
2614
2615 void ath_tx_cabq(struct ath_softc *sc, struct sk_buff *skb)
2616 {
2617 int hdrlen, padsize;
2618 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2619 struct ath_tx_control txctl;
2620
2621 memset(&txctl, 0, sizeof(struct ath_tx_control));
2622
2623 /*
2624 * As a temporary workaround, assign seq# here; this will likely need
2625 * to be cleaned up to work better with Beacon transmission and virtual
2626 * BSSes.
2627 */
2628 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
2629 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2630 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
2631 sc->seq_no += 0x10;
2632 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
2633 hdr->seq_ctrl |= cpu_to_le16(sc->seq_no);
2634 }
2635
2636 /* Add the padding after the header if this is not already done */
2637 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2638 if (hdrlen & 3) {
2639 padsize = hdrlen % 4;
2640 if (skb_headroom(skb) < padsize) {
2641 DPRINTF(sc, ATH_DBG_XMIT, "%s: TX CABQ padding "
2642 "failed\n", __func__);
2643 dev_kfree_skb_any(skb);
2644 return;
2645 }
2646 skb_push(skb, padsize);
2647 memmove(skb->data, skb->data + padsize, hdrlen);
2648 }
2649
2650 txctl.txq = sc->sc_cabq;
2651
2652 DPRINTF(sc, ATH_DBG_XMIT, "%s: transmitting CABQ packet, skb: %p\n",
2653 __func__,
2654 skb);
2655
2656 if (ath_tx_start(sc, skb, &txctl) != 0) {
2657 DPRINTF(sc, ATH_DBG_XMIT, "%s: TX failed\n", __func__);
2658 goto exit;
2659 }
2660
2661 return;
2662 exit:
2663 dev_kfree_skb_any(skb);
2664 }
Linux kernel - Deliverables
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