2 * Copyright (c) 2008 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 * Implementation of transmit path.
23 #define BITS_PER_BYTE 8
24 #define OFDM_PLCP_BITS 22
25 #define HT_RC_2_MCS(_rc) ((_rc) & 0x0f)
26 #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
32 #define HT_LTF(_ns) (4 * (_ns))
33 #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */
34 #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */
35 #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
36 #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
38 #define OFDM_SIFS_TIME 16
40 static u32 bits_per_symbol
[][2] = {
42 { 26, 54 }, /* 0: BPSK */
43 { 52, 108 }, /* 1: QPSK 1/2 */
44 { 78, 162 }, /* 2: QPSK 3/4 */
45 { 104, 216 }, /* 3: 16-QAM 1/2 */
46 { 156, 324 }, /* 4: 16-QAM 3/4 */
47 { 208, 432 }, /* 5: 64-QAM 2/3 */
48 { 234, 486 }, /* 6: 64-QAM 3/4 */
49 { 260, 540 }, /* 7: 64-QAM 5/6 */
50 { 52, 108 }, /* 8: BPSK */
51 { 104, 216 }, /* 9: QPSK 1/2 */
52 { 156, 324 }, /* 10: QPSK 3/4 */
53 { 208, 432 }, /* 11: 16-QAM 1/2 */
54 { 312, 648 }, /* 12: 16-QAM 3/4 */
55 { 416, 864 }, /* 13: 64-QAM 2/3 */
56 { 468, 972 }, /* 14: 64-QAM 3/4 */
57 { 520, 1080 }, /* 15: 64-QAM 5/6 */
60 #define IS_HT_RATE(_rate) ((_rate) & 0x80)
63 * Insert a chain of ath_buf (descriptors) on a txq and
64 * assume the descriptors are already chained together by caller.
65 * NB: must be called with txq lock held
68 static void ath_tx_txqaddbuf(struct ath_softc
*sc
,
69 struct ath_txq
*txq
, struct list_head
*head
)
71 struct ath_hal
*ah
= sc
->sc_ah
;
74 * Insert the frame on the outbound list and
75 * pass it on to the hardware.
81 bf
= list_first_entry(head
, struct ath_buf
, list
);
83 list_splice_tail_init(head
, &txq
->axq_q
);
85 txq
->axq_totalqueued
++;
86 txq
->axq_linkbuf
= list_entry(txq
->axq_q
.prev
, struct ath_buf
, list
);
88 DPRINTF(sc
, ATH_DBG_QUEUE
,
89 "%s: txq depth = %d\n", __func__
, txq
->axq_depth
);
91 if (txq
->axq_link
== NULL
) {
92 ath9k_hw_puttxbuf(ah
, txq
->axq_qnum
, bf
->bf_daddr
);
93 DPRINTF(sc
, ATH_DBG_XMIT
,
94 "%s: TXDP[%u] = %llx (%p)\n",
95 __func__
, txq
->axq_qnum
,
96 ito64(bf
->bf_daddr
), bf
->bf_desc
);
98 *txq
->axq_link
= bf
->bf_daddr
;
99 DPRINTF(sc
, ATH_DBG_XMIT
, "%s: link[%u] (%p)=%llx (%p)\n",
101 txq
->axq_qnum
, txq
->axq_link
,
102 ito64(bf
->bf_daddr
), bf
->bf_desc
);
104 txq
->axq_link
= &(bf
->bf_lastbf
->bf_desc
->ds_link
);
105 ath9k_hw_txstart(ah
, txq
->axq_qnum
);
108 /* Get transmit rate index using rate in Kbps */
110 static int ath_tx_findindex(const struct ath9k_rate_table
*rt
, int rate
)
115 for (i
= 0; i
< rt
->rateCount
; i
++) {
116 if (rt
->info
[i
].rateKbps
== rate
) {
125 /* Check if it's okay to send out aggregates */
127 static int ath_aggr_query(struct ath_softc
*sc
,
128 struct ath_node
*an
, u8 tidno
)
130 struct ath_atx_tid
*tid
;
131 tid
= ATH_AN_2_TID(an
, tidno
);
133 if (tid
->addba_exchangecomplete
|| tid
->addba_exchangeinprogress
)
139 static enum ath9k_pkt_type
get_hal_packet_type(struct ieee80211_hdr
*hdr
)
141 enum ath9k_pkt_type htype
;
144 fc
= hdr
->frame_control
;
146 /* Calculate Atheros packet type from IEEE80211 packet header */
148 if (ieee80211_is_beacon(fc
))
149 htype
= ATH9K_PKT_TYPE_BEACON
;
150 else if (ieee80211_is_probe_resp(fc
))
151 htype
= ATH9K_PKT_TYPE_PROBE_RESP
;
152 else if (ieee80211_is_atim(fc
))
153 htype
= ATH9K_PKT_TYPE_ATIM
;
154 else if (ieee80211_is_pspoll(fc
))
155 htype
= ATH9K_PKT_TYPE_PSPOLL
;
157 htype
= ATH9K_PKT_TYPE_NORMAL
;
162 static void fill_min_rates(struct sk_buff
*skb
, struct ath_tx_control
*txctl
)
164 struct ieee80211_hdr
*hdr
;
165 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
166 struct ath_tx_info_priv
*tx_info_priv
;
169 hdr
= (struct ieee80211_hdr
*)skb
->data
;
170 fc
= hdr
->frame_control
;
171 tx_info_priv
= (struct ath_tx_info_priv
*)tx_info
->driver_data
[0];
173 if (ieee80211_is_mgmt(fc
) || ieee80211_is_ctl(fc
)) {
174 txctl
->use_minrate
= 1;
175 txctl
->min_rate
= tx_info_priv
->min_rate
;
176 } else if (ieee80211_is_data(fc
)) {
177 if (ieee80211_is_nullfunc(fc
) ||
178 /* Port Access Entity (IEEE 802.1X) */
179 (skb
->protocol
== cpu_to_be16(0x888E))) {
180 txctl
->use_minrate
= 1;
181 txctl
->min_rate
= tx_info_priv
->min_rate
;
183 if (is_multicast_ether_addr(hdr
->addr1
))
184 txctl
->mcast_rate
= tx_info_priv
->min_rate
;
189 /* This function will setup additional txctl information, mostly rate stuff */
190 /* FIXME: seqno, ps */
191 static int ath_tx_prepare(struct ath_softc
*sc
,
193 struct ath_tx_control
*txctl
)
195 struct ieee80211_hw
*hw
= sc
->hw
;
196 struct ieee80211_hdr
*hdr
;
197 struct ath_rc_series
*rcs
;
198 struct ath_txq
*txq
= NULL
;
199 const struct ath9k_rate_table
*rt
;
200 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
201 struct ath_tx_info_priv
*tx_info_priv
;
208 hdr
= (struct ieee80211_hdr
*)skb
->data
;
209 hdrlen
= ieee80211_get_hdrlen_from_skb(skb
);
210 fc
= hdr
->frame_control
;
212 rt
= sc
->sc_currates
;
215 /* Fill misc fields */
217 spin_lock_bh(&sc
->node_lock
);
218 txctl
->an
= ath_node_get(sc
, hdr
->addr1
);
219 /* create a temp node, if the node is not there already */
221 txctl
->an
= ath_node_attach(sc
, hdr
->addr1
, 0);
222 spin_unlock_bh(&sc
->node_lock
);
224 if (ieee80211_is_data_qos(fc
)) {
225 qc
= ieee80211_get_qos_ctl(hdr
);
226 txctl
->tidno
= qc
[0] & 0xf;
230 txctl
->frmlen
= skb
->len
+ FCS_LEN
- (hdrlen
& 3);
231 txctl
->txpower
= MAX_RATE_POWER
; /* FIXME */
233 /* Fill Key related fields */
235 txctl
->keytype
= ATH9K_KEY_TYPE_CLEAR
;
236 txctl
->keyix
= ATH9K_TXKEYIX_INVALID
;
238 if (tx_info
->control
.hw_key
) {
239 txctl
->keyix
= tx_info
->control
.hw_key
->hw_key_idx
;
240 txctl
->frmlen
+= tx_info
->control
.hw_key
->icv_len
;
242 if (tx_info
->control
.hw_key
->alg
== ALG_WEP
)
243 txctl
->keytype
= ATH9K_KEY_TYPE_WEP
;
244 else if (tx_info
->control
.hw_key
->alg
== ALG_TKIP
)
245 txctl
->keytype
= ATH9K_KEY_TYPE_TKIP
;
246 else if (tx_info
->control
.hw_key
->alg
== ALG_CCMP
)
247 txctl
->keytype
= ATH9K_KEY_TYPE_AES
;
250 /* Fill packet type */
252 txctl
->atype
= get_hal_packet_type(hdr
);
256 if (unlikely(txctl
->flags
& ATH9K_TXDESC_CAB
)) {
260 txctl
->qnum
= ath_get_hal_qnum(skb_get_queue_mapping(skb
), sc
);
261 txq
= &sc
->sc_txq
[txctl
->qnum
];
263 spin_lock_bh(&txq
->axq_lock
);
265 /* Try to avoid running out of descriptors */
266 if (txq
->axq_depth
>= (ATH_TXBUF
- 20) &&
267 !(txctl
->flags
& ATH9K_TXDESC_CAB
)) {
268 DPRINTF(sc
, ATH_DBG_FATAL
,
269 "%s: TX queue: %d is full, depth: %d\n",
273 ieee80211_stop_queue(hw
, skb_get_queue_mapping(skb
));
275 spin_unlock_bh(&txq
->axq_lock
);
279 spin_unlock_bh(&txq
->axq_lock
);
283 fill_min_rates(skb
, txctl
);
287 txctl
->flags
|= ATH9K_TXDESC_CLRDMASK
; /* needed for crypto errors */
289 if (tx_info
->flags
& IEEE80211_TX_CTL_NO_ACK
)
290 txctl
->flags
|= ATH9K_TXDESC_NOACK
;
291 if (tx_info
->flags
& IEEE80211_TX_CTL_USE_RTS_CTS
)
292 txctl
->flags
|= ATH9K_TXDESC_RTSENA
;
295 * Setup for rate calculations.
297 tx_info_priv
= (struct ath_tx_info_priv
*)tx_info
->driver_data
[0];
298 rcs
= tx_info_priv
->rcs
;
300 if (ieee80211_is_data(fc
) && !txctl
->use_minrate
) {
302 /* Enable HT only for DATA frames and not for EAPOL */
303 txctl
->ht
= (hw
->conf
.ht_conf
.ht_supported
&&
304 (tx_info
->flags
& IEEE80211_TX_CTL_AMPDU
));
306 if (is_multicast_ether_addr(hdr
->addr1
)) {
308 ath_tx_findindex(rt
, txctl
->mcast_rate
);
311 * mcast packets are not re-tried.
315 /* For HT capable stations, we save tidno for later use.
316 * We also override seqno set by upper layer with the one
317 * in tx aggregation state.
319 * First, the fragmentation stat is determined.
320 * If fragmentation is on, the sequence number is
321 * not overridden, since it has been
322 * incremented by the fragmentation routine.
324 if (likely(!(txctl
->flags
& ATH9K_TXDESC_FRAG_IS_ON
)) &&
325 txctl
->ht
&& (sc
->sc_flags
& SC_OP_TXAGGR
)) {
326 struct ath_atx_tid
*tid
;
328 tid
= ATH_AN_2_TID(txctl
->an
, txctl
->tidno
);
330 hdr
->seq_ctrl
= cpu_to_le16(tid
->seq_next
<<
331 IEEE80211_SEQ_SEQ_SHIFT
);
332 txctl
->seqno
= tid
->seq_next
;
333 INCR(tid
->seq_next
, IEEE80211_SEQ_MAX
);
336 /* for management and control frames,
337 * or for NULL and EAPOL frames */
339 rcs
[0].rix
= ath_rate_findrateix(sc
, txctl
->min_rate
);
342 rcs
[0].tries
= ATH_MGT_TXMAXTRY
;
346 if (ieee80211_has_morefrags(fc
) ||
347 (le16_to_cpu(hdr
->seq_ctrl
) & IEEE80211_SCTL_FRAG
)) {
349 ** Force hardware to use computed duration for next
350 ** fragment by disabling multi-rate retry, which
351 ** updates duration based on the multi-rate
354 rcs
[1].tries
= rcs
[2].tries
= rcs
[3].tries
= 0;
355 rcs
[1].rix
= rcs
[2].rix
= rcs
[3].rix
= 0;
356 /* reset tries but keep rate index */
357 rcs
[0].tries
= ATH_TXMAXTRY
;
361 * Determine if a tx interrupt should be generated for
362 * this descriptor. We take a tx interrupt to reap
363 * descriptors when the h/w hits an EOL condition or
364 * when the descriptor is specifically marked to generate
365 * an interrupt. We periodically mark descriptors in this
366 * way to insure timely replenishing of the supply needed
367 * for sending frames. Defering interrupts reduces system
368 * load and potentially allows more concurrent work to be
369 * done but if done to aggressively can cause senders to
372 * NB: use >= to deal with sc_txintrperiod changing
373 * dynamically through sysctl.
375 spin_lock_bh(&txq
->axq_lock
);
376 if ((++txq
->axq_intrcnt
>= sc
->sc_txintrperiod
)) {
377 txctl
->flags
|= ATH9K_TXDESC_INTREQ
;
378 txq
->axq_intrcnt
= 0;
380 spin_unlock_bh(&txq
->axq_lock
);
382 if (is_multicast_ether_addr(hdr
->addr1
)) {
383 antenna
= sc
->sc_mcastantenna
+ 1;
384 sc
->sc_mcastantenna
= (sc
->sc_mcastantenna
+ 1) & 0x1;
390 /* To complete a chain of buffers associated a frame */
392 static void ath_tx_complete_buf(struct ath_softc
*sc
,
394 struct list_head
*bf_q
,
395 int txok
, int sendbar
)
397 struct sk_buff
*skb
= bf
->bf_mpdu
;
398 struct ath_xmit_status tx_status
;
401 * Set retry information.
402 * NB: Don't use the information in the descriptor, because the frame
403 * could be software retried.
405 tx_status
.retries
= bf
->bf_retries
;
409 tx_status
.flags
= ATH_TX_BAR
;
412 tx_status
.flags
|= ATH_TX_ERROR
;
414 if (bf_isxretried(bf
))
415 tx_status
.flags
|= ATH_TX_XRETRY
;
417 /* Unmap this frame */
418 pci_unmap_single(sc
->pdev
,
422 /* complete this frame */
423 ath_tx_complete(sc
, skb
, &tx_status
, bf
->bf_node
);
426 * Return the list of ath_buf of this mpdu to free queue
428 spin_lock_bh(&sc
->sc_txbuflock
);
429 list_splice_tail_init(bf_q
, &sc
->sc_txbuf
);
430 spin_unlock_bh(&sc
->sc_txbuflock
);
434 * queue up a dest/ac pair for tx scheduling
435 * NB: must be called with txq lock held
438 static void ath_tx_queue_tid(struct ath_txq
*txq
, struct ath_atx_tid
*tid
)
440 struct ath_atx_ac
*ac
= tid
->ac
;
443 * if tid is paused, hold off
449 * add tid to ac atmost once
455 list_add_tail(&tid
->list
, &ac
->tid_q
);
458 * add node ac to txq atmost once
464 list_add_tail(&ac
->list
, &txq
->axq_acq
);
469 static void ath_tx_pause_tid(struct ath_softc
*sc
, struct ath_atx_tid
*tid
)
471 struct ath_txq
*txq
= &sc
->sc_txq
[tid
->ac
->qnum
];
473 spin_lock_bh(&txq
->axq_lock
);
477 spin_unlock_bh(&txq
->axq_lock
);
480 /* resume a tid and schedule aggregate */
482 void ath_tx_resume_tid(struct ath_softc
*sc
, struct ath_atx_tid
*tid
)
484 struct ath_txq
*txq
= &sc
->sc_txq
[tid
->ac
->qnum
];
486 ASSERT(tid
->paused
> 0);
487 spin_lock_bh(&txq
->axq_lock
);
494 if (list_empty(&tid
->buf_q
))
498 * Add this TID to scheduler and try to send out aggregates
500 ath_tx_queue_tid(txq
, tid
);
501 ath_txq_schedule(sc
, txq
);
503 spin_unlock_bh(&txq
->axq_lock
);
506 /* Compute the number of bad frames */
508 static int ath_tx_num_badfrms(struct ath_softc
*sc
,
509 struct ath_buf
*bf
, int txok
)
511 struct ath_node
*an
= bf
->bf_node
;
512 int isnodegone
= (an
->an_flags
& ATH_NODE_CLEAN
);
513 struct ath_buf
*bf_last
= bf
->bf_lastbf
;
514 struct ath_desc
*ds
= bf_last
->bf_desc
;
516 u32 ba
[WME_BA_BMP_SIZE
>> 5];
521 if (isnodegone
|| ds
->ds_txstat
.ts_flags
== ATH9K_TX_SW_ABORTED
)
524 isaggr
= bf_isaggr(bf
);
526 seq_st
= ATH_DS_BA_SEQ(ds
);
527 memcpy(ba
, ATH_DS_BA_BITMAP(ds
), WME_BA_BMP_SIZE
>> 3);
531 ba_index
= ATH_BA_INDEX(seq_st
, bf
->bf_seqno
);
532 if (!txok
|| (isaggr
&& !ATH_BA_ISSET(ba
, ba_index
)))
541 static void ath_tx_set_retry(struct ath_softc
*sc
, struct ath_buf
*bf
)
544 struct ieee80211_hdr
*hdr
;
546 bf
->bf_state
.bf_type
|= BUF_RETRY
;
550 hdr
= (struct ieee80211_hdr
*)skb
->data
;
551 hdr
->frame_control
|= cpu_to_le16(IEEE80211_FCTL_RETRY
);
554 /* Update block ack window */
556 static void ath_tx_update_baw(struct ath_softc
*sc
,
557 struct ath_atx_tid
*tid
, int seqno
)
561 index
= ATH_BA_INDEX(tid
->seq_start
, seqno
);
562 cindex
= (tid
->baw_head
+ index
) & (ATH_TID_MAX_BUFS
- 1);
564 tid
->tx_buf
[cindex
] = NULL
;
566 while (tid
->baw_head
!= tid
->baw_tail
&& !tid
->tx_buf
[tid
->baw_head
]) {
567 INCR(tid
->seq_start
, IEEE80211_SEQ_MAX
);
568 INCR(tid
->baw_head
, ATH_TID_MAX_BUFS
);
573 * ath_pkt_dur - compute packet duration (NB: not NAV)
576 * pktlen - total bytes (delims + data + fcs + pads + pad delims)
577 * width - 0 for 20 MHz, 1 for 40 MHz
578 * half_gi - to use 4us v/s 3.6 us for symbol time
581 static u32
ath_pkt_duration(struct ath_softc
*sc
,
588 const struct ath9k_rate_table
*rt
= sc
->sc_currates
;
589 u32 nbits
, nsymbits
, duration
, nsymbols
;
593 pktlen
= bf_isaggr(bf
) ? bf
->bf_al
: bf
->bf_frmlen
;
594 rc
= rt
->info
[rix
].rateCode
;
597 * for legacy rates, use old function to compute packet duration
600 return ath9k_hw_computetxtime(sc
->sc_ah
,
606 * find number of symbols: PLCP + data
608 nbits
= (pktlen
<< 3) + OFDM_PLCP_BITS
;
609 nsymbits
= bits_per_symbol
[HT_RC_2_MCS(rc
)][width
];
610 nsymbols
= (nbits
+ nsymbits
- 1) / nsymbits
;
613 duration
= SYMBOL_TIME(nsymbols
);
615 duration
= SYMBOL_TIME_HALFGI(nsymbols
);
618 * addup duration for legacy/ht training and signal fields
620 streams
= HT_RC_2_STREAMS(rc
);
621 duration
+= L_STF
+ L_LTF
+ L_SIG
+ HT_SIG
+ HT_STF
+ HT_LTF(streams
);
625 /* Rate module function to set rate related fields in tx descriptor */
627 static void ath_buf_set_rate(struct ath_softc
*sc
, struct ath_buf
*bf
)
629 struct ath_hal
*ah
= sc
->sc_ah
;
630 const struct ath9k_rate_table
*rt
;
631 struct ath_desc
*ds
= bf
->bf_desc
;
632 struct ath_desc
*lastds
= bf
->bf_lastbf
->bf_desc
;
633 struct ath9k_11n_rate_series series
[4];
634 int i
, flags
, rtsctsena
= 0, dynamic_mimops
= 0;
636 u8 rix
= 0, cix
, ctsrate
= 0;
637 u32 aggr_limit_with_rts
= ah
->ah_caps
.rts_aggr_limit
;
638 struct ath_node
*an
= (struct ath_node
*) bf
->bf_node
;
641 * get the cix for the lowest valid rix.
643 rt
= sc
->sc_currates
;
645 if (bf
->bf_rcs
[i
].tries
) {
646 rix
= bf
->bf_rcs
[i
].rix
;
650 flags
= (bf
->bf_flags
& (ATH9K_TXDESC_RTSENA
| ATH9K_TXDESC_CTSENA
));
651 cix
= rt
->info
[rix
].controlRate
;
654 * If 802.11g protection is enabled, determine whether
655 * to use RTS/CTS or just CTS. Note that this is only
656 * done for OFDM/HT unicast frames.
658 if (sc
->sc_protmode
!= PROT_M_NONE
&&
659 (rt
->info
[rix
].phy
== PHY_OFDM
||
660 rt
->info
[rix
].phy
== PHY_HT
) &&
661 (bf
->bf_flags
& ATH9K_TXDESC_NOACK
) == 0) {
662 if (sc
->sc_protmode
== PROT_M_RTSCTS
)
663 flags
= ATH9K_TXDESC_RTSENA
;
664 else if (sc
->sc_protmode
== PROT_M_CTSONLY
)
665 flags
= ATH9K_TXDESC_CTSENA
;
667 cix
= rt
->info
[sc
->sc_protrix
].controlRate
;
671 /* For 11n, the default behavior is to enable RTS for
672 * hw retried frames. We enable the global flag here and
673 * let rate series flags determine which rates will actually
676 if ((ah
->ah_caps
.hw_caps
& ATH9K_HW_CAP_HT
) && bf_isdata(bf
)) {
679 * 802.11g protection not needed, use our default behavior
682 flags
= ATH9K_TXDESC_RTSENA
;
684 * For dynamic MIMO PS, RTS needs to precede the first aggregate
685 * and the second aggregate should have any protection at all.
687 if (an
->an_smmode
== ATH_SM_PWRSAV_DYNAMIC
) {
688 if (!bf_isaggrburst(bf
)) {
689 flags
= ATH9K_TXDESC_RTSENA
;
698 * Set protection if aggregate protection on
700 if (sc
->sc_config
.ath_aggr_prot
&&
701 (!bf_isaggr(bf
) || (bf_isaggr(bf
) && bf
->bf_al
< 8192))) {
702 flags
= ATH9K_TXDESC_RTSENA
;
703 cix
= rt
->info
[sc
->sc_protrix
].controlRate
;
708 * For AR5416 - RTS cannot be followed by a frame larger than 8K.
710 if (bf_isaggr(bf
) && (bf
->bf_al
> aggr_limit_with_rts
)) {
712 * Ensure that in the case of SM Dynamic power save
713 * while we are bursting the second aggregate the
716 flags
&= ~(ATH9K_TXDESC_RTSENA
);
720 * CTS transmit rate is derived from the transmit rate
721 * by looking in the h/w rate table. We must also factor
722 * in whether or not a short preamble is to be used.
724 /* NB: cix is set above where RTS/CTS is enabled */
726 ctsrate
= rt
->info
[cix
].rateCode
|
727 (bf_isshpreamble(bf
) ? rt
->info
[cix
].shortPreamble
: 0);
730 * Setup HAL rate series
732 memset(series
, 0, sizeof(struct ath9k_11n_rate_series
) * 4);
734 for (i
= 0; i
< 4; i
++) {
735 if (!bf
->bf_rcs
[i
].tries
)
738 rix
= bf
->bf_rcs
[i
].rix
;
740 series
[i
].Rate
= rt
->info
[rix
].rateCode
|
741 (bf_isshpreamble(bf
) ? rt
->info
[rix
].shortPreamble
: 0);
743 series
[i
].Tries
= bf
->bf_rcs
[i
].tries
;
745 series
[i
].RateFlags
= (
746 (bf
->bf_rcs
[i
].flags
& ATH_RC_RTSCTS_FLAG
) ?
747 ATH9K_RATESERIES_RTS_CTS
: 0) |
748 ((bf
->bf_rcs
[i
].flags
& ATH_RC_CW40_FLAG
) ?
749 ATH9K_RATESERIES_2040
: 0) |
750 ((bf
->bf_rcs
[i
].flags
& ATH_RC_SGI_FLAG
) ?
751 ATH9K_RATESERIES_HALFGI
: 0);
753 series
[i
].PktDuration
= ath_pkt_duration(
755 (bf
->bf_rcs
[i
].flags
& ATH_RC_CW40_FLAG
) != 0,
756 (bf
->bf_rcs
[i
].flags
& ATH_RC_SGI_FLAG
),
757 bf_isshpreamble(bf
));
759 if ((an
->an_smmode
== ATH_SM_PWRSAV_STATIC
) &&
760 (bf
->bf_rcs
[i
].flags
& ATH_RC_DS_FLAG
) == 0) {
762 * When sending to an HT node that has enabled static
763 * SM/MIMO power save, send at single stream rates but
764 * use maximum allowed transmit chains per user,
765 * hardware, regulatory, or country limits for
768 series
[i
].ChSel
= sc
->sc_tx_chainmask
;
772 ath_chainmask_sel_logic(sc
, an
);
774 series
[i
].ChSel
= sc
->sc_tx_chainmask
;
778 series
[i
].RateFlags
|= ATH9K_RATESERIES_RTS_CTS
;
781 * Set RTS for all rates if node is in dynamic powersave
782 * mode and we are using dual stream rates.
784 if (dynamic_mimops
&& (bf
->bf_rcs
[i
].flags
& ATH_RC_DS_FLAG
))
785 series
[i
].RateFlags
|= ATH9K_RATESERIES_RTS_CTS
;
789 * For non-HT devices, calculate RTS/CTS duration in software
790 * and disable multi-rate retry.
792 if (flags
&& !(ah
->ah_caps
.hw_caps
& ATH9K_HW_CAP_HT
)) {
794 * Compute the transmit duration based on the frame
795 * size and the size of an ACK frame. We call into the
796 * HAL to do the computation since it depends on the
797 * characteristics of the actual PHY being used.
799 * NB: CTS is assumed the same size as an ACK so we can
800 * use the precalculated ACK durations.
802 if (flags
& ATH9K_TXDESC_RTSENA
) { /* SIFS + CTS */
803 ctsduration
+= bf_isshpreamble(bf
) ?
804 rt
->info
[cix
].spAckDuration
:
805 rt
->info
[cix
].lpAckDuration
;
808 ctsduration
+= series
[0].PktDuration
;
810 if ((bf
->bf_flags
& ATH9K_TXDESC_NOACK
) == 0) { /* SIFS + ACK */
811 ctsduration
+= bf_isshpreamble(bf
) ?
812 rt
->info
[rix
].spAckDuration
:
813 rt
->info
[rix
].lpAckDuration
;
817 * Disable multi-rate retry when using RTS/CTS by clearing
820 memset(&series
[1], 0, sizeof(struct ath9k_11n_rate_series
) * 3);
824 * set dur_update_en for l-sig computation except for PS-Poll frames
826 ath9k_hw_set11n_ratescenario(ah
, ds
, lastds
,
831 if (sc
->sc_config
.ath_aggr_prot
&& flags
)
832 ath9k_hw_set11n_burstduration(ah
, ds
, 8192);
836 * Function to send a normal HT (non-AMPDU) frame
837 * NB: must be called with txq lock held
840 static int ath_tx_send_normal(struct ath_softc
*sc
,
842 struct ath_atx_tid
*tid
,
843 struct list_head
*bf_head
)
847 struct ieee80211_tx_info
*tx_info
;
848 struct ath_tx_info_priv
*tx_info_priv
;
850 BUG_ON(list_empty(bf_head
));
852 bf
= list_first_entry(bf_head
, struct ath_buf
, list
);
853 bf
->bf_state
.bf_type
&= ~BUF_AMPDU
; /* regular HT frame */
855 skb
= (struct sk_buff
*)bf
->bf_mpdu
;
856 tx_info
= IEEE80211_SKB_CB(skb
);
857 tx_info_priv
= (struct ath_tx_info_priv
*)tx_info
->driver_data
[0];
858 memcpy(bf
->bf_rcs
, tx_info_priv
->rcs
, 4 * sizeof(tx_info_priv
->rcs
[0]));
860 /* update starting sequence number for subsequent ADDBA request */
861 INCR(tid
->seq_start
, IEEE80211_SEQ_MAX
);
863 /* Queue to h/w without aggregation */
865 bf
->bf_lastbf
= bf
->bf_lastfrm
; /* one single frame */
866 ath_buf_set_rate(sc
, bf
);
867 ath_tx_txqaddbuf(sc
, txq
, bf_head
);
872 /* flush tid's software queue and send frames as non-ampdu's */
874 static void ath_tx_flush_tid(struct ath_softc
*sc
, struct ath_atx_tid
*tid
)
876 struct ath_txq
*txq
= &sc
->sc_txq
[tid
->ac
->qnum
];
878 struct list_head bf_head
;
879 INIT_LIST_HEAD(&bf_head
);
881 ASSERT(tid
->paused
> 0);
882 spin_lock_bh(&txq
->axq_lock
);
886 if (tid
->paused
> 0) {
887 spin_unlock_bh(&txq
->axq_lock
);
891 while (!list_empty(&tid
->buf_q
)) {
892 bf
= list_first_entry(&tid
->buf_q
, struct ath_buf
, list
);
893 ASSERT(!bf_isretried(bf
));
894 list_cut_position(&bf_head
, &tid
->buf_q
, &bf
->bf_lastfrm
->list
);
895 ath_tx_send_normal(sc
, txq
, tid
, &bf_head
);
898 spin_unlock_bh(&txq
->axq_lock
);
901 /* Completion routine of an aggregate */
903 static void ath_tx_complete_aggr_rifs(struct ath_softc
*sc
,
906 struct list_head
*bf_q
,
909 struct ath_node
*an
= bf
->bf_node
;
910 struct ath_atx_tid
*tid
= ATH_AN_2_TID(an
, bf
->bf_tidno
);
911 struct ath_buf
*bf_last
= bf
->bf_lastbf
;
912 struct ath_desc
*ds
= bf_last
->bf_desc
;
913 struct ath_buf
*bf_next
, *bf_lastq
= NULL
;
914 struct list_head bf_head
, bf_pending
;
916 u32 ba
[WME_BA_BMP_SIZE
>> 5];
917 int isaggr
, txfail
, txpending
, sendbar
= 0, needreset
= 0;
918 int isnodegone
= (an
->an_flags
& ATH_NODE_CLEAN
);
920 isaggr
= bf_isaggr(bf
);
923 if (ATH_DS_TX_BA(ds
)) {
925 * extract starting sequence and
928 seq_st
= ATH_DS_BA_SEQ(ds
);
930 ATH_DS_BA_BITMAP(ds
),
931 WME_BA_BMP_SIZE
>> 3);
933 memset(ba
, 0, WME_BA_BMP_SIZE
>> 3);
936 * AR5416 can become deaf/mute when BA
937 * issue happens. Chip needs to be reset.
938 * But AP code may have sychronization issues
939 * when perform internal reset in this routine.
940 * Only enable reset in STA mode for now.
942 if (sc
->sc_ah
->ah_opmode
== ATH9K_M_STA
)
946 memset(ba
, 0, WME_BA_BMP_SIZE
>> 3);
950 INIT_LIST_HEAD(&bf_pending
);
951 INIT_LIST_HEAD(&bf_head
);
954 txfail
= txpending
= 0;
955 bf_next
= bf
->bf_next
;
957 if (ATH_BA_ISSET(ba
, ATH_BA_INDEX(seq_st
, bf
->bf_seqno
))) {
958 /* transmit completion, subframe is
959 * acked by block ack */
960 } else if (!isaggr
&& txok
) {
961 /* transmit completion */
964 if (!tid
->cleanup_inprogress
&& !isnodegone
&&
965 ds
->ds_txstat
.ts_flags
!= ATH9K_TX_SW_ABORTED
) {
966 if (bf
->bf_retries
< ATH_MAX_SW_RETRIES
) {
967 ath_tx_set_retry(sc
, bf
);
970 bf
->bf_state
.bf_type
|= BUF_XRETRY
;
976 * cleanup in progress, just fail
977 * the un-acked sub-frames
983 * Remove ath_buf's of this sub-frame from aggregate queue.
985 if (bf_next
== NULL
) { /* last subframe in the aggregate */
986 ASSERT(bf
->bf_lastfrm
== bf_last
);
989 * The last descriptor of the last sub frame could be
990 * a holding descriptor for h/w. If that's the case,
991 * bf->bf_lastfrm won't be in the bf_q.
992 * Make sure we handle bf_q properly here.
995 if (!list_empty(bf_q
)) {
996 bf_lastq
= list_entry(bf_q
->prev
,
997 struct ath_buf
, list
);
998 list_cut_position(&bf_head
,
999 bf_q
, &bf_lastq
->list
);
1002 * XXX: if the last subframe only has one
1003 * descriptor which is also being used as
1004 * a holding descriptor. Then the ath_buf
1005 * is not in the bf_q at all.
1007 INIT_LIST_HEAD(&bf_head
);
1010 ASSERT(!list_empty(bf_q
));
1011 list_cut_position(&bf_head
,
1012 bf_q
, &bf
->bf_lastfrm
->list
);
1017 * complete the acked-ones/xretried ones; update
1020 spin_lock_bh(&txq
->axq_lock
);
1021 ath_tx_update_baw(sc
, tid
, bf
->bf_seqno
);
1022 spin_unlock_bh(&txq
->axq_lock
);
1024 /* complete this sub-frame */
1025 ath_tx_complete_buf(sc
, bf
, &bf_head
, !txfail
, sendbar
);
1028 * retry the un-acked ones
1031 * XXX: if the last descriptor is holding descriptor,
1032 * in order to requeue the frame to software queue, we
1033 * need to allocate a new descriptor and
1034 * copy the content of holding descriptor to it.
1036 if (bf
->bf_next
== NULL
&&
1037 bf_last
->bf_status
& ATH_BUFSTATUS_STALE
) {
1038 struct ath_buf
*tbf
;
1040 /* allocate new descriptor */
1041 spin_lock_bh(&sc
->sc_txbuflock
);
1042 ASSERT(!list_empty((&sc
->sc_txbuf
)));
1043 tbf
= list_first_entry(&sc
->sc_txbuf
,
1044 struct ath_buf
, list
);
1045 list_del(&tbf
->list
);
1046 spin_unlock_bh(&sc
->sc_txbuflock
);
1048 ATH_TXBUF_RESET(tbf
);
1050 /* copy descriptor content */
1051 tbf
->bf_mpdu
= bf_last
->bf_mpdu
;
1052 tbf
->bf_node
= bf_last
->bf_node
;
1053 tbf
->bf_buf_addr
= bf_last
->bf_buf_addr
;
1054 *(tbf
->bf_desc
) = *(bf_last
->bf_desc
);
1056 /* link it to the frame */
1058 bf_lastq
->bf_desc
->ds_link
=
1060 bf
->bf_lastfrm
= tbf
;
1061 ath9k_hw_cleartxdesc(sc
->sc_ah
,
1062 bf
->bf_lastfrm
->bf_desc
);
1064 tbf
->bf_state
= bf_last
->bf_state
;
1065 tbf
->bf_lastfrm
= tbf
;
1066 ath9k_hw_cleartxdesc(sc
->sc_ah
,
1067 tbf
->bf_lastfrm
->bf_desc
);
1069 /* copy the DMA context */
1070 tbf
->bf_dmacontext
=
1071 bf_last
->bf_dmacontext
;
1073 list_add_tail(&tbf
->list
, &bf_head
);
1076 * Clear descriptor status words for
1079 ath9k_hw_cleartxdesc(sc
->sc_ah
,
1080 bf
->bf_lastfrm
->bf_desc
);
1084 * Put this buffer to the temporary pending
1085 * queue to retain ordering
1087 list_splice_tail_init(&bf_head
, &bf_pending
);
1094 * node is already gone. no more assocication
1095 * with the node. the node might have been freed
1096 * any node acces can result in panic.note tid
1097 * is part of the node.
1102 if (tid
->cleanup_inprogress
) {
1103 /* check to see if we're done with cleaning the h/w queue */
1104 spin_lock_bh(&txq
->axq_lock
);
1106 if (tid
->baw_head
== tid
->baw_tail
) {
1107 tid
->addba_exchangecomplete
= 0;
1108 tid
->addba_exchangeattempts
= 0;
1109 spin_unlock_bh(&txq
->axq_lock
);
1111 tid
->cleanup_inprogress
= false;
1113 /* send buffered frames as singles */
1114 ath_tx_flush_tid(sc
, tid
);
1116 spin_unlock_bh(&txq
->axq_lock
);
1122 * prepend un-acked frames to the beginning of the pending frame queue
1124 if (!list_empty(&bf_pending
)) {
1125 spin_lock_bh(&txq
->axq_lock
);
1126 /* Note: we _prepend_, we _do_not_ at to
1127 * the end of the queue ! */
1128 list_splice(&bf_pending
, &tid
->buf_q
);
1129 ath_tx_queue_tid(txq
, tid
);
1130 spin_unlock_bh(&txq
->axq_lock
);
1134 ath_reset(sc
, false);
1139 /* Process completed xmit descriptors from the specified queue */
1141 static int ath_tx_processq(struct ath_softc
*sc
, struct ath_txq
*txq
)
1143 struct ath_hal
*ah
= sc
->sc_ah
;
1144 struct ath_buf
*bf
, *lastbf
, *bf_held
= NULL
;
1145 struct list_head bf_head
;
1146 struct ath_desc
*ds
, *tmp_ds
;
1147 struct sk_buff
*skb
;
1148 struct ieee80211_tx_info
*tx_info
;
1149 struct ath_tx_info_priv
*tx_info_priv
;
1150 int nacked
, txok
, nbad
= 0, isrifs
= 0;
1153 DPRINTF(sc
, ATH_DBG_QUEUE
,
1154 "%s: tx queue %d (%x), link %p\n", __func__
,
1155 txq
->axq_qnum
, ath9k_hw_gettxbuf(sc
->sc_ah
, txq
->axq_qnum
),
1160 spin_lock_bh(&txq
->axq_lock
);
1161 txq
->axq_intrcnt
= 0; /* reset periodic desc intr count */
1162 if (list_empty(&txq
->axq_q
)) {
1163 txq
->axq_link
= NULL
;
1164 txq
->axq_linkbuf
= NULL
;
1165 spin_unlock_bh(&txq
->axq_lock
);
1168 bf
= list_first_entry(&txq
->axq_q
, struct ath_buf
, list
);
1171 * There is a race condition that a BH gets scheduled
1172 * after sw writes TxE and before hw re-load the last
1173 * descriptor to get the newly chained one.
1174 * Software must keep the last DONE descriptor as a
1175 * holding descriptor - software does so by marking
1176 * it with the STALE flag.
1179 if (bf
->bf_status
& ATH_BUFSTATUS_STALE
) {
1181 if (list_is_last(&bf_held
->list
, &txq
->axq_q
)) {
1183 * The holding descriptor is the last
1184 * descriptor in queue. It's safe to remove
1185 * the last holding descriptor in BH context.
1187 spin_unlock_bh(&txq
->axq_lock
);
1190 /* Lets work with the next buffer now */
1191 bf
= list_entry(bf_held
->list
.next
,
1192 struct ath_buf
, list
);
1196 lastbf
= bf
->bf_lastbf
;
1197 ds
= lastbf
->bf_desc
; /* NB: last decriptor */
1199 status
= ath9k_hw_txprocdesc(ah
, ds
);
1200 if (status
== -EINPROGRESS
) {
1201 spin_unlock_bh(&txq
->axq_lock
);
1204 if (bf
->bf_desc
== txq
->axq_lastdsWithCTS
)
1205 txq
->axq_lastdsWithCTS
= NULL
;
1206 if (ds
== txq
->axq_gatingds
)
1207 txq
->axq_gatingds
= NULL
;
1210 * Remove ath_buf's of the same transmit unit from txq,
1211 * however leave the last descriptor back as the holding
1212 * descriptor for hw.
1214 lastbf
->bf_status
|= ATH_BUFSTATUS_STALE
;
1215 INIT_LIST_HEAD(&bf_head
);
1217 if (!list_is_singular(&lastbf
->list
))
1218 list_cut_position(&bf_head
,
1219 &txq
->axq_q
, lastbf
->list
.prev
);
1224 txq
->axq_aggr_depth
--;
1226 txok
= (ds
->ds_txstat
.ts_status
== 0);
1228 spin_unlock_bh(&txq
->axq_lock
);
1231 list_del(&bf_held
->list
);
1232 spin_lock_bh(&sc
->sc_txbuflock
);
1233 list_add_tail(&bf_held
->list
, &sc
->sc_txbuf
);
1234 spin_unlock_bh(&sc
->sc_txbuflock
);
1237 if (!bf_isampdu(bf
)) {
1239 * This frame is sent out as a single frame.
1240 * Use hardware retry status for this frame.
1242 bf
->bf_retries
= ds
->ds_txstat
.ts_longretry
;
1243 if (ds
->ds_txstat
.ts_status
& ATH9K_TXERR_XRETRY
)
1244 bf
->bf_state
.bf_type
|= BUF_XRETRY
;
1247 nbad
= ath_tx_num_badfrms(sc
, bf
, txok
);
1250 tx_info
= IEEE80211_SKB_CB(skb
);
1251 tx_info_priv
= (struct ath_tx_info_priv
*)
1252 tx_info
->driver_data
[0];
1253 if (ds
->ds_txstat
.ts_status
& ATH9K_TXERR_FILT
)
1254 tx_info
->flags
|= IEEE80211_TX_STAT_TX_FILTERED
;
1255 if ((ds
->ds_txstat
.ts_status
& ATH9K_TXERR_FILT
) == 0 &&
1256 (bf
->bf_flags
& ATH9K_TXDESC_NOACK
) == 0) {
1257 if (ds
->ds_txstat
.ts_status
== 0)
1260 if (bf_isdata(bf
)) {
1262 tmp_ds
= bf
->bf_rifslast
->bf_desc
;
1265 memcpy(&tx_info_priv
->tx
,
1267 sizeof(tx_info_priv
->tx
));
1268 tx_info_priv
->n_frames
= bf
->bf_nframes
;
1269 tx_info_priv
->n_bad_frames
= nbad
;
1274 * Complete this transmit unit
1277 ath_tx_complete_aggr_rifs(sc
, txq
, bf
, &bf_head
, txok
);
1279 ath_tx_complete_buf(sc
, bf
, &bf_head
, txok
, 0);
1281 /* Wake up mac80211 queue */
1283 spin_lock_bh(&txq
->axq_lock
);
1284 if (txq
->stopped
&& ath_txq_depth(sc
, txq
->axq_qnum
) <=
1287 qnum
= ath_get_mac80211_qnum(txq
->axq_qnum
, sc
);
1289 ieee80211_wake_queue(sc
->hw
, qnum
);
1296 * schedule any pending packets if aggregation is enabled
1298 if (sc
->sc_flags
& SC_OP_TXAGGR
)
1299 ath_txq_schedule(sc
, txq
);
1300 spin_unlock_bh(&txq
->axq_lock
);
1305 static void ath_tx_stopdma(struct ath_softc
*sc
, struct ath_txq
*txq
)
1307 struct ath_hal
*ah
= sc
->sc_ah
;
1309 (void) ath9k_hw_stoptxdma(ah
, txq
->axq_qnum
);
1310 DPRINTF(sc
, ATH_DBG_XMIT
, "%s: tx queue [%u] %x, link %p\n",
1311 __func__
, txq
->axq_qnum
,
1312 ath9k_hw_gettxbuf(ah
, txq
->axq_qnum
), txq
->axq_link
);
1315 /* Drain only the data queues */
1317 static void ath_drain_txdataq(struct ath_softc
*sc
, bool retry_tx
)
1319 struct ath_hal
*ah
= sc
->sc_ah
;
1323 /* XXX return value */
1324 if (!(sc
->sc_flags
& SC_OP_INVALID
)) {
1325 for (i
= 0; i
< ATH9K_NUM_TX_QUEUES
; i
++) {
1326 if (ATH_TXQ_SETUP(sc
, i
)) {
1327 ath_tx_stopdma(sc
, &sc
->sc_txq
[i
]);
1329 /* The TxDMA may not really be stopped.
1330 * Double check the hal tx pending count */
1331 npend
+= ath9k_hw_numtxpending(ah
,
1332 sc
->sc_txq
[i
].axq_qnum
);
1340 /* TxDMA not stopped, reset the hal */
1341 DPRINTF(sc
, ATH_DBG_XMIT
,
1342 "%s: Unable to stop TxDMA. Reset HAL!\n", __func__
);
1344 spin_lock_bh(&sc
->sc_resetlock
);
1345 if (!ath9k_hw_reset(ah
,
1346 sc
->sc_ah
->ah_curchan
,
1347 sc
->sc_ht_info
.tx_chan_width
,
1348 sc
->sc_tx_chainmask
, sc
->sc_rx_chainmask
,
1349 sc
->sc_ht_extprotspacing
, true, &status
)) {
1351 DPRINTF(sc
, ATH_DBG_FATAL
,
1352 "%s: unable to reset hardware; hal status %u\n",
1356 spin_unlock_bh(&sc
->sc_resetlock
);
1359 for (i
= 0; i
< ATH9K_NUM_TX_QUEUES
; i
++) {
1360 if (ATH_TXQ_SETUP(sc
, i
))
1361 ath_tx_draintxq(sc
, &sc
->sc_txq
[i
], retry_tx
);
1365 /* Add a sub-frame to block ack window */
1367 static void ath_tx_addto_baw(struct ath_softc
*sc
,
1368 struct ath_atx_tid
*tid
,
1373 if (bf_isretried(bf
))
1376 index
= ATH_BA_INDEX(tid
->seq_start
, bf
->bf_seqno
);
1377 cindex
= (tid
->baw_head
+ index
) & (ATH_TID_MAX_BUFS
- 1);
1379 ASSERT(tid
->tx_buf
[cindex
] == NULL
);
1380 tid
->tx_buf
[cindex
] = bf
;
1382 if (index
>= ((tid
->baw_tail
- tid
->baw_head
) &
1383 (ATH_TID_MAX_BUFS
- 1))) {
1384 tid
->baw_tail
= cindex
;
1385 INCR(tid
->baw_tail
, ATH_TID_MAX_BUFS
);
1390 * Function to send an A-MPDU
1391 * NB: must be called with txq lock held
1394 static int ath_tx_send_ampdu(struct ath_softc
*sc
,
1395 struct ath_txq
*txq
,
1396 struct ath_atx_tid
*tid
,
1397 struct list_head
*bf_head
,
1398 struct ath_tx_control
*txctl
)
1401 struct sk_buff
*skb
;
1402 struct ieee80211_tx_info
*tx_info
;
1403 struct ath_tx_info_priv
*tx_info_priv
;
1405 BUG_ON(list_empty(bf_head
));
1407 bf
= list_first_entry(bf_head
, struct ath_buf
, list
);
1408 bf
->bf_state
.bf_type
|= BUF_AMPDU
;
1409 bf
->bf_seqno
= txctl
->seqno
; /* save seqno and tidno in buffer */
1410 bf
->bf_tidno
= txctl
->tidno
;
1413 * Do not queue to h/w when any of the following conditions is true:
1414 * - there are pending frames in software queue
1415 * - the TID is currently paused for ADDBA/BAR request
1416 * - seqno is not within block-ack window
1417 * - h/w queue depth exceeds low water mark
1419 if (!list_empty(&tid
->buf_q
) || tid
->paused
||
1420 !BAW_WITHIN(tid
->seq_start
, tid
->baw_size
, bf
->bf_seqno
) ||
1421 txq
->axq_depth
>= ATH_AGGR_MIN_QDEPTH
) {
1423 * Add this frame to software queue for scheduling later
1426 list_splice_tail_init(bf_head
, &tid
->buf_q
);
1427 ath_tx_queue_tid(txq
, tid
);
1431 skb
= (struct sk_buff
*)bf
->bf_mpdu
;
1432 tx_info
= IEEE80211_SKB_CB(skb
);
1433 tx_info_priv
= (struct ath_tx_info_priv
*)tx_info
->driver_data
[0];
1434 memcpy(bf
->bf_rcs
, tx_info_priv
->rcs
, 4 * sizeof(tx_info_priv
->rcs
[0]));
1436 /* Add sub-frame to BAW */
1437 ath_tx_addto_baw(sc
, tid
, bf
);
1439 /* Queue to h/w without aggregation */
1441 bf
->bf_lastbf
= bf
->bf_lastfrm
; /* one single frame */
1442 ath_buf_set_rate(sc
, bf
);
1443 ath_tx_txqaddbuf(sc
, txq
, bf_head
);
1449 * returns aggr limit based on lowest of the rates
1452 static u32
ath_lookup_rate(struct ath_softc
*sc
,
1455 const struct ath9k_rate_table
*rt
= sc
->sc_currates
;
1456 struct sk_buff
*skb
;
1457 struct ieee80211_tx_info
*tx_info
;
1458 struct ath_tx_info_priv
*tx_info_priv
;
1459 u32 max_4ms_framelen
, frame_length
;
1460 u16 aggr_limit
, legacy
= 0, maxampdu
;
1464 skb
= (struct sk_buff
*)bf
->bf_mpdu
;
1465 tx_info
= IEEE80211_SKB_CB(skb
);
1466 tx_info_priv
= (struct ath_tx_info_priv
*)
1467 tx_info
->driver_data
[0];
1469 tx_info_priv
->rcs
, 4 * sizeof(tx_info_priv
->rcs
[0]));
1472 * Find the lowest frame length among the rate series that will have a
1473 * 4ms transmit duration.
1474 * TODO - TXOP limit needs to be considered.
1476 max_4ms_framelen
= ATH_AMPDU_LIMIT_MAX
;
1478 for (i
= 0; i
< 4; i
++) {
1479 if (bf
->bf_rcs
[i
].tries
) {
1480 frame_length
= bf
->bf_rcs
[i
].max_4ms_framelen
;
1482 if (rt
->info
[bf
->bf_rcs
[i
].rix
].phy
!= PHY_HT
) {
1487 max_4ms_framelen
= min(max_4ms_framelen
, frame_length
);
1492 * limit aggregate size by the minimum rate if rate selected is
1493 * not a probe rate, if rate selected is a probe rate then
1494 * avoid aggregation of this packet.
1496 if (tx_info
->flags
& IEEE80211_TX_CTL_RATE_CTRL_PROBE
|| legacy
)
1499 aggr_limit
= min(max_4ms_framelen
,
1500 (u32
)ATH_AMPDU_LIMIT_DEFAULT
);
1503 * h/w can accept aggregates upto 16 bit lengths (65535).
1504 * The IE, however can hold upto 65536, which shows up here
1505 * as zero. Ignore 65536 since we are constrained by hw.
1507 maxampdu
= sc
->sc_ht_info
.maxampdu
;
1509 aggr_limit
= min(aggr_limit
, maxampdu
);
1515 * returns the number of delimiters to be added to
1516 * meet the minimum required mpdudensity.
1517 * caller should make sure that the rate is HT rate .
1520 static int ath_compute_num_delims(struct ath_softc
*sc
,
1524 const struct ath9k_rate_table
*rt
= sc
->sc_currates
;
1525 u32 nsymbits
, nsymbols
, mpdudensity
;
1528 int width
, half_gi
, ndelim
, mindelim
;
1530 /* Select standard number of delimiters based on frame length alone */
1531 ndelim
= ATH_AGGR_GET_NDELIM(frmlen
);
1534 * If encryption enabled, hardware requires some more padding between
1536 * TODO - this could be improved to be dependent on the rate.
1537 * The hardware can keep up at lower rates, but not higher rates
1539 if (bf
->bf_keytype
!= ATH9K_KEY_TYPE_CLEAR
)
1540 ndelim
+= ATH_AGGR_ENCRYPTDELIM
;
1543 * Convert desired mpdu density from microeconds to bytes based
1544 * on highest rate in rate series (i.e. first rate) to determine
1545 * required minimum length for subframe. Take into account
1546 * whether high rate is 20 or 40Mhz and half or full GI.
1548 mpdudensity
= sc
->sc_ht_info
.mpdudensity
;
1551 * If there is no mpdu density restriction, no further calculation
1554 if (mpdudensity
== 0)
1557 rix
= bf
->bf_rcs
[0].rix
;
1558 flags
= bf
->bf_rcs
[0].flags
;
1559 rc
= rt
->info
[rix
].rateCode
;
1560 width
= (flags
& ATH_RC_CW40_FLAG
) ? 1 : 0;
1561 half_gi
= (flags
& ATH_RC_SGI_FLAG
) ? 1 : 0;
1564 nsymbols
= NUM_SYMBOLS_PER_USEC_HALFGI(mpdudensity
);
1566 nsymbols
= NUM_SYMBOLS_PER_USEC(mpdudensity
);
1571 nsymbits
= bits_per_symbol
[HT_RC_2_MCS(rc
)][width
];
1572 minlen
= (nsymbols
* nsymbits
) / BITS_PER_BYTE
;
1574 /* Is frame shorter than required minimum length? */
1575 if (frmlen
< minlen
) {
1576 /* Get the minimum number of delimiters required. */
1577 mindelim
= (minlen
- frmlen
) / ATH_AGGR_DELIM_SZ
;
1578 ndelim
= max(mindelim
, ndelim
);
1585 * For aggregation from software buffer queue.
1586 * NB: must be called with txq lock held
1589 static enum ATH_AGGR_STATUS
ath_tx_form_aggr(struct ath_softc
*sc
,
1590 struct ath_atx_tid
*tid
,
1591 struct list_head
*bf_q
,
1592 struct ath_buf
**bf_last
,
1593 struct aggr_rifs_param
*param
,
1596 #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
1597 struct ath_buf
*bf
, *tbf
, *bf_first
, *bf_prev
= NULL
;
1598 struct list_head bf_head
;
1599 int rl
= 0, nframes
= 0, ndelim
;
1600 u16 aggr_limit
= 0, al
= 0, bpad
= 0,
1601 al_delta
, h_baw
= tid
->baw_size
/ 2;
1602 enum ATH_AGGR_STATUS status
= ATH_AGGR_DONE
;
1603 int prev_al
= 0, is_ds_rate
= 0;
1604 INIT_LIST_HEAD(&bf_head
);
1606 BUG_ON(list_empty(&tid
->buf_q
));
1608 bf_first
= list_first_entry(&tid
->buf_q
, struct ath_buf
, list
);
1611 bf
= list_first_entry(&tid
->buf_q
, struct ath_buf
, list
);
1614 * do not step over block-ack window
1616 if (!BAW_WITHIN(tid
->seq_start
, tid
->baw_size
, bf
->bf_seqno
)) {
1617 status
= ATH_AGGR_BAW_CLOSED
;
1622 aggr_limit
= ath_lookup_rate(sc
, bf
);
1625 * Is rate dual stream
1628 (bf
->bf_rcs
[0].flags
& ATH_RC_DS_FLAG
) ? 1 : 0;
1632 * do not exceed aggregation limit
1634 al_delta
= ATH_AGGR_DELIM_SZ
+ bf
->bf_frmlen
;
1636 if (nframes
&& (aggr_limit
<
1637 (al
+ bpad
+ al_delta
+ prev_al
))) {
1638 status
= ATH_AGGR_LIMITED
;
1643 * do not exceed subframe limit
1645 if ((nframes
+ *prev_frames
) >=
1646 min((int)h_baw
, ATH_AMPDU_SUBFRAME_DEFAULT
)) {
1647 status
= ATH_AGGR_LIMITED
;
1652 * add padding for previous frame to aggregation length
1654 al
+= bpad
+ al_delta
;
1657 * Get the delimiters needed to meet the MPDU
1658 * density for this node.
1660 ndelim
= ath_compute_num_delims(sc
, bf_first
, bf
->bf_frmlen
);
1662 bpad
= PADBYTES(al_delta
) + (ndelim
<< 2);
1665 bf
->bf_lastfrm
->bf_desc
->ds_link
= 0;
1668 * this packet is part of an aggregate
1669 * - remove all descriptors belonging to this frame from
1671 * - add it to block ack window
1672 * - set up descriptors for aggregation
1674 list_cut_position(&bf_head
, &tid
->buf_q
, &bf
->bf_lastfrm
->list
);
1675 ath_tx_addto_baw(sc
, tid
, bf
);
1677 list_for_each_entry(tbf
, &bf_head
, list
) {
1678 ath9k_hw_set11n_aggr_middle(sc
->sc_ah
,
1679 tbf
->bf_desc
, ndelim
);
1683 * link buffers of this frame to the aggregate
1685 list_splice_tail_init(&bf_head
, bf_q
);
1689 bf_prev
->bf_next
= bf
;
1690 bf_prev
->bf_lastfrm
->bf_desc
->ds_link
= bf
->bf_daddr
;
1696 * terminate aggregation on a small packet boundary
1698 if (bf
->bf_frmlen
< ATH_AGGR_MINPLEN
) {
1699 status
= ATH_AGGR_SHORTPKT
;
1703 } while (!list_empty(&tid
->buf_q
));
1705 bf_first
->bf_al
= al
;
1706 bf_first
->bf_nframes
= nframes
;
1713 * process pending frames possibly doing a-mpdu aggregation
1714 * NB: must be called with txq lock held
1717 static void ath_tx_sched_aggr(struct ath_softc
*sc
,
1718 struct ath_txq
*txq
, struct ath_atx_tid
*tid
)
1720 struct ath_buf
*bf
, *tbf
, *bf_last
, *bf_lastaggr
= NULL
;
1721 enum ATH_AGGR_STATUS status
;
1722 struct list_head bf_q
;
1723 struct aggr_rifs_param param
= {0, 0, 0, 0, NULL
};
1724 int prev_frames
= 0;
1727 if (list_empty(&tid
->buf_q
))
1730 INIT_LIST_HEAD(&bf_q
);
1732 status
= ath_tx_form_aggr(sc
, tid
, &bf_q
, &bf_lastaggr
, ¶m
,
1736 * no frames picked up to be aggregated; block-ack
1737 * window is not open
1739 if (list_empty(&bf_q
))
1742 bf
= list_first_entry(&bf_q
, struct ath_buf
, list
);
1743 bf_last
= list_entry(bf_q
.prev
, struct ath_buf
, list
);
1744 bf
->bf_lastbf
= bf_last
;
1747 * if only one frame, send as non-aggregate
1749 if (bf
->bf_nframes
== 1) {
1750 ASSERT(bf
->bf_lastfrm
== bf_last
);
1752 bf
->bf_state
.bf_type
&= ~BUF_AGGR
;
1754 * clear aggr bits for every descriptor
1755 * XXX TODO: is there a way to optimize it?
1757 list_for_each_entry(tbf
, &bf_q
, list
) {
1758 ath9k_hw_clr11n_aggr(sc
->sc_ah
, tbf
->bf_desc
);
1761 ath_buf_set_rate(sc
, bf
);
1762 ath_tx_txqaddbuf(sc
, txq
, &bf_q
);
1767 * setup first desc with rate and aggr info
1769 bf
->bf_state
.bf_type
|= BUF_AGGR
;
1770 ath_buf_set_rate(sc
, bf
);
1771 ath9k_hw_set11n_aggr_first(sc
->sc_ah
, bf
->bf_desc
, bf
->bf_al
);
1774 * anchor last frame of aggregate correctly
1776 ASSERT(bf_lastaggr
);
1777 ASSERT(bf_lastaggr
->bf_lastfrm
== bf_last
);
1779 ath9k_hw_set11n_aggr_last(sc
->sc_ah
, tbf
->bf_desc
);
1781 /* XXX: We don't enter into this loop, consider removing this */
1782 while (!list_empty(&bf_q
) && !list_is_last(&tbf
->list
, &bf_q
)) {
1783 tbf
= list_entry(tbf
->list
.next
, struct ath_buf
, list
);
1784 ath9k_hw_set11n_aggr_last(sc
->sc_ah
, tbf
->bf_desc
);
1787 txq
->axq_aggr_depth
++;
1790 * Normal aggregate, queue to hardware
1792 ath_tx_txqaddbuf(sc
, txq
, &bf_q
);
1794 } while (txq
->axq_depth
< ATH_AGGR_MIN_QDEPTH
&&
1795 status
!= ATH_AGGR_BAW_CLOSED
);
1798 /* Called with txq lock held */
1800 static void ath_tid_drain(struct ath_softc
*sc
,
1801 struct ath_txq
*txq
,
1802 struct ath_atx_tid
*tid
,
1806 struct list_head bf_head
;
1807 INIT_LIST_HEAD(&bf_head
);
1810 if (list_empty(&tid
->buf_q
))
1812 bf
= list_first_entry(&tid
->buf_q
, struct ath_buf
, list
);
1814 list_cut_position(&bf_head
, &tid
->buf_q
, &bf
->bf_lastfrm
->list
);
1816 /* update baw for software retried frame */
1817 if (bf_isretried(bf
))
1818 ath_tx_update_baw(sc
, tid
, bf
->bf_seqno
);
1821 * do not indicate packets while holding txq spinlock.
1822 * unlock is intentional here
1824 if (likely(bh_flag
))
1825 spin_unlock_bh(&txq
->axq_lock
);
1827 spin_unlock(&txq
->axq_lock
);
1829 /* complete this sub-frame */
1830 ath_tx_complete_buf(sc
, bf
, &bf_head
, 0, 0);
1832 if (likely(bh_flag
))
1833 spin_lock_bh(&txq
->axq_lock
);
1835 spin_lock(&txq
->axq_lock
);
1839 * TODO: For frame(s) that are in the retry state, we will reuse the
1840 * sequence number(s) without setting the retry bit. The
1841 * alternative is to give up on these and BAR the receiver's window
1844 tid
->seq_next
= tid
->seq_start
;
1845 tid
->baw_tail
= tid
->baw_head
;
1849 * Drain all pending buffers
1850 * NB: must be called with txq lock held
1853 static void ath_txq_drain_pending_buffers(struct ath_softc
*sc
,
1854 struct ath_txq
*txq
,
1857 struct ath_atx_ac
*ac
, *ac_tmp
;
1858 struct ath_atx_tid
*tid
, *tid_tmp
;
1860 list_for_each_entry_safe(ac
, ac_tmp
, &txq
->axq_acq
, list
) {
1861 list_del(&ac
->list
);
1863 list_for_each_entry_safe(tid
, tid_tmp
, &ac
->tid_q
, list
) {
1864 list_del(&tid
->list
);
1866 ath_tid_drain(sc
, txq
, tid
, bh_flag
);
1871 static int ath_tx_start_dma(struct ath_softc
*sc
,
1872 struct sk_buff
*skb
,
1873 struct scatterlist
*sg
,
1875 struct ath_tx_control
*txctl
)
1877 struct ath_node
*an
= txctl
->an
;
1878 struct ath_buf
*bf
= NULL
;
1879 struct list_head bf_head
;
1880 struct ath_desc
*ds
;
1881 struct ath_hal
*ah
= sc
->sc_ah
;
1882 struct ath_txq
*txq
;
1883 struct ath_tx_info_priv
*tx_info_priv
;
1884 struct ath_rc_series
*rcs
;
1885 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*)skb
->data
;
1886 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
1887 __le16 fc
= hdr
->frame_control
;
1889 if (unlikely(txctl
->flags
& ATH9K_TXDESC_CAB
))
1892 txq
= &sc
->sc_txq
[txctl
->qnum
];
1894 /* For each sglist entry, allocate an ath_buf for DMA */
1895 INIT_LIST_HEAD(&bf_head
);
1896 spin_lock_bh(&sc
->sc_txbuflock
);
1897 if (unlikely(list_empty(&sc
->sc_txbuf
))) {
1898 spin_unlock_bh(&sc
->sc_txbuflock
);
1902 bf
= list_first_entry(&sc
->sc_txbuf
, struct ath_buf
, list
);
1903 list_del(&bf
->list
);
1904 spin_unlock_bh(&sc
->sc_txbuflock
);
1906 list_add_tail(&bf
->list
, &bf_head
);
1908 /* set up this buffer */
1909 ATH_TXBUF_RESET(bf
);
1910 bf
->bf_frmlen
= txctl
->frmlen
;
1912 ieee80211_is_data(fc
) ?
1913 (bf
->bf_state
.bf_type
|= BUF_DATA
) :
1914 (bf
->bf_state
.bf_type
&= ~BUF_DATA
);
1915 ieee80211_is_back_req(fc
) ?
1916 (bf
->bf_state
.bf_type
|= BUF_BAR
) :
1917 (bf
->bf_state
.bf_type
&= ~BUF_BAR
);
1918 ieee80211_is_pspoll(fc
) ?
1919 (bf
->bf_state
.bf_type
|= BUF_PSPOLL
) :
1920 (bf
->bf_state
.bf_type
&= ~BUF_PSPOLL
);
1921 (sc
->sc_flags
& SC_OP_PREAMBLE_SHORT
) ?
1922 (bf
->bf_state
.bf_type
|= BUF_SHORT_PREAMBLE
) :
1923 (bf
->bf_state
.bf_type
&= ~BUF_SHORT_PREAMBLE
);
1925 bf
->bf_flags
= txctl
->flags
;
1926 bf
->bf_keytype
= txctl
->keytype
;
1927 tx_info_priv
= (struct ath_tx_info_priv
*)tx_info
->driver_data
[0];
1928 rcs
= tx_info_priv
->rcs
;
1929 bf
->bf_rcs
[0] = rcs
[0];
1930 bf
->bf_rcs
[1] = rcs
[1];
1931 bf
->bf_rcs
[2] = rcs
[2];
1932 bf
->bf_rcs
[3] = rcs
[3];
1935 bf
->bf_buf_addr
= sg_dma_address(sg
);
1937 /* setup descriptor */
1940 ds
->ds_data
= bf
->bf_buf_addr
;
1943 * Save the DMA context in the first ath_buf
1945 bf
->bf_dmacontext
= txctl
->dmacontext
;
1948 * Formulate first tx descriptor with tx controls.
1950 ath9k_hw_set11n_txdesc(ah
,
1952 bf
->bf_frmlen
, /* frame length */
1953 txctl
->atype
, /* Atheros packet type */
1954 min(txctl
->txpower
, (u16
)60), /* txpower */
1955 txctl
->keyix
, /* key cache index */
1956 txctl
->keytype
, /* key type */
1957 txctl
->flags
); /* flags */
1958 ath9k_hw_filltxdesc(ah
,
1960 sg_dma_len(sg
), /* segment length */
1961 true, /* first segment */
1962 (n_sg
== 1) ? true : false, /* last segment */
1963 ds
); /* first descriptor */
1965 bf
->bf_lastfrm
= bf
;
1967 (bf
->bf_state
.bf_type
|= BUF_HT
) :
1968 (bf
->bf_state
.bf_type
&= ~BUF_HT
);
1970 spin_lock_bh(&txq
->axq_lock
);
1972 if (txctl
->ht
&& (sc
->sc_flags
& SC_OP_TXAGGR
)) {
1973 struct ath_atx_tid
*tid
= ATH_AN_2_TID(an
, txctl
->tidno
);
1974 if (ath_aggr_query(sc
, an
, txctl
->tidno
)) {
1976 * Try aggregation if it's a unicast data frame
1977 * and the destination is HT capable.
1979 ath_tx_send_ampdu(sc
, txq
, tid
, &bf_head
, txctl
);
1982 * Send this frame as regular when ADDBA exchange
1983 * is neither complete nor pending.
1985 ath_tx_send_normal(sc
, txq
, tid
, &bf_head
);
1990 ath_buf_set_rate(sc
, bf
);
1992 if (ieee80211_is_back_req(fc
)) {
1993 /* This is required for resuming tid
1994 * during BAR completion */
1995 bf
->bf_tidno
= txctl
->tidno
;
1998 ath_tx_txqaddbuf(sc
, txq
, &bf_head
);
2000 spin_unlock_bh(&txq
->axq_lock
);
2004 static void xmit_map_sg(struct ath_softc
*sc
,
2005 struct sk_buff
*skb
,
2006 struct ath_tx_control
*txctl
)
2008 struct ath_xmit_status tx_status
;
2009 struct ath_atx_tid
*tid
;
2010 struct scatterlist sg
;
2012 txctl
->dmacontext
= pci_map_single(sc
->pdev
, skb
->data
,
2013 skb
->len
, PCI_DMA_TODEVICE
);
2015 /* setup S/G list */
2016 memset(&sg
, 0, sizeof(struct scatterlist
));
2017 sg_dma_address(&sg
) = txctl
->dmacontext
;
2018 sg_dma_len(&sg
) = skb
->len
;
2020 if (ath_tx_start_dma(sc
, skb
, &sg
, 1, txctl
) != 0) {
2022 * We have to do drop frame here.
2024 pci_unmap_single(sc
->pdev
, txctl
->dmacontext
,
2025 skb
->len
, PCI_DMA_TODEVICE
);
2027 tx_status
.retries
= 0;
2028 tx_status
.flags
= ATH_TX_ERROR
;
2030 if (txctl
->ht
&& (sc
->sc_flags
& SC_OP_TXAGGR
)) {
2031 /* Reclaim the seqno. */
2032 tid
= ATH_AN_2_TID((struct ath_node
*)
2033 txctl
->an
, txctl
->tidno
);
2034 DECR(tid
->seq_next
, IEEE80211_SEQ_MAX
);
2036 ath_tx_complete(sc
, skb
, &tx_status
, txctl
->an
);
2040 /* Initialize TX queue and h/w */
2042 int ath_tx_init(struct ath_softc
*sc
, int nbufs
)
2047 spin_lock_init(&sc
->sc_txbuflock
);
2049 /* Setup tx descriptors */
2050 error
= ath_descdma_setup(sc
, &sc
->sc_txdma
, &sc
->sc_txbuf
,
2053 DPRINTF(sc
, ATH_DBG_FATAL
,
2054 "%s: failed to allocate tx descriptors: %d\n",
2059 /* XXX allocate beacon state together with vap */
2060 error
= ath_descdma_setup(sc
, &sc
->sc_bdma
, &sc
->sc_bbuf
,
2061 "beacon", ATH_BCBUF
, 1);
2063 DPRINTF(sc
, ATH_DBG_FATAL
,
2064 "%s: failed to allocate "
2065 "beacon descripotrs: %d\n",
2078 /* Reclaim all tx queue resources */
2080 int ath_tx_cleanup(struct ath_softc
*sc
)
2082 /* cleanup beacon descriptors */
2083 if (sc
->sc_bdma
.dd_desc_len
!= 0)
2084 ath_descdma_cleanup(sc
, &sc
->sc_bdma
, &sc
->sc_bbuf
);
2086 /* cleanup tx descriptors */
2087 if (sc
->sc_txdma
.dd_desc_len
!= 0)
2088 ath_descdma_cleanup(sc
, &sc
->sc_txdma
, &sc
->sc_txbuf
);
2093 /* Setup a h/w transmit queue */
2095 struct ath_txq
*ath_txq_setup(struct ath_softc
*sc
, int qtype
, int subtype
)
2097 struct ath_hal
*ah
= sc
->sc_ah
;
2098 struct ath9k_tx_queue_info qi
;
2101 memset(&qi
, 0, sizeof(qi
));
2102 qi
.tqi_subtype
= subtype
;
2103 qi
.tqi_aifs
= ATH9K_TXQ_USEDEFAULT
;
2104 qi
.tqi_cwmin
= ATH9K_TXQ_USEDEFAULT
;
2105 qi
.tqi_cwmax
= ATH9K_TXQ_USEDEFAULT
;
2106 qi
.tqi_physCompBuf
= 0;
2109 * Enable interrupts only for EOL and DESC conditions.
2110 * We mark tx descriptors to receive a DESC interrupt
2111 * when a tx queue gets deep; otherwise waiting for the
2112 * EOL to reap descriptors. Note that this is done to
2113 * reduce interrupt load and this only defers reaping
2114 * descriptors, never transmitting frames. Aside from
2115 * reducing interrupts this also permits more concurrency.
2116 * The only potential downside is if the tx queue backs
2117 * up in which case the top half of the kernel may backup
2118 * due to a lack of tx descriptors.
2120 * The UAPSD queue is an exception, since we take a desc-
2121 * based intr on the EOSP frames.
2123 if (qtype
== ATH9K_TX_QUEUE_UAPSD
)
2124 qi
.tqi_qflags
= TXQ_FLAG_TXDESCINT_ENABLE
;
2126 qi
.tqi_qflags
= TXQ_FLAG_TXEOLINT_ENABLE
|
2127 TXQ_FLAG_TXDESCINT_ENABLE
;
2128 qnum
= ath9k_hw_setuptxqueue(ah
, qtype
, &qi
);
2131 * NB: don't print a message, this happens
2132 * normally on parts with too few tx queues
2136 if (qnum
>= ARRAY_SIZE(sc
->sc_txq
)) {
2137 DPRINTF(sc
, ATH_DBG_FATAL
,
2138 "%s: hal qnum %u out of range, max %u!\n",
2139 __func__
, qnum
, (unsigned int)ARRAY_SIZE(sc
->sc_txq
));
2140 ath9k_hw_releasetxqueue(ah
, qnum
);
2143 if (!ATH_TXQ_SETUP(sc
, qnum
)) {
2144 struct ath_txq
*txq
= &sc
->sc_txq
[qnum
];
2146 txq
->axq_qnum
= qnum
;
2147 txq
->axq_link
= NULL
;
2148 INIT_LIST_HEAD(&txq
->axq_q
);
2149 INIT_LIST_HEAD(&txq
->axq_acq
);
2150 spin_lock_init(&txq
->axq_lock
);
2152 txq
->axq_aggr_depth
= 0;
2153 txq
->axq_totalqueued
= 0;
2154 txq
->axq_intrcnt
= 0;
2155 txq
->axq_linkbuf
= NULL
;
2156 sc
->sc_txqsetup
|= 1<<qnum
;
2158 return &sc
->sc_txq
[qnum
];
2161 /* Reclaim resources for a setup queue */
2163 void ath_tx_cleanupq(struct ath_softc
*sc
, struct ath_txq
*txq
)
2165 ath9k_hw_releasetxqueue(sc
->sc_ah
, txq
->axq_qnum
);
2166 sc
->sc_txqsetup
&= ~(1<<txq
->axq_qnum
);
2170 * Setup a hardware data transmit queue for the specified
2171 * access control. The hal may not support all requested
2172 * queues in which case it will return a reference to a
2173 * previously setup queue. We record the mapping from ac's
2174 * to h/w queues for use by ath_tx_start and also track
2175 * the set of h/w queues being used to optimize work in the
2176 * transmit interrupt handler and related routines.
2179 int ath_tx_setup(struct ath_softc
*sc
, int haltype
)
2181 struct ath_txq
*txq
;
2183 if (haltype
>= ARRAY_SIZE(sc
->sc_haltype2q
)) {
2184 DPRINTF(sc
, ATH_DBG_FATAL
,
2185 "%s: HAL AC %u out of range, max %zu!\n",
2186 __func__
, haltype
, ARRAY_SIZE(sc
->sc_haltype2q
));
2189 txq
= ath_txq_setup(sc
, ATH9K_TX_QUEUE_DATA
, haltype
);
2191 sc
->sc_haltype2q
[haltype
] = txq
->axq_qnum
;
2197 int ath_tx_get_qnum(struct ath_softc
*sc
, int qtype
, int haltype
)
2202 case ATH9K_TX_QUEUE_DATA
:
2203 if (haltype
>= ARRAY_SIZE(sc
->sc_haltype2q
)) {
2204 DPRINTF(sc
, ATH_DBG_FATAL
,
2205 "%s: HAL AC %u out of range, max %zu!\n",
2207 haltype
, ARRAY_SIZE(sc
->sc_haltype2q
));
2210 qnum
= sc
->sc_haltype2q
[haltype
];
2212 case ATH9K_TX_QUEUE_BEACON
:
2213 qnum
= sc
->sc_bhalq
;
2215 case ATH9K_TX_QUEUE_CAB
:
2216 qnum
= sc
->sc_cabq
->axq_qnum
;
2224 /* Update parameters for a transmit queue */
2226 int ath_txq_update(struct ath_softc
*sc
, int qnum
,
2227 struct ath9k_tx_queue_info
*qinfo
)
2229 struct ath_hal
*ah
= sc
->sc_ah
;
2231 struct ath9k_tx_queue_info qi
;
2233 if (qnum
== sc
->sc_bhalq
) {
2235 * XXX: for beacon queue, we just save the parameter.
2236 * It will be picked up by ath_beaconq_config when
2239 sc
->sc_beacon_qi
= *qinfo
;
2243 ASSERT(sc
->sc_txq
[qnum
].axq_qnum
== qnum
);
2245 ath9k_hw_get_txq_props(ah
, qnum
, &qi
);
2246 qi
.tqi_aifs
= qinfo
->tqi_aifs
;
2247 qi
.tqi_cwmin
= qinfo
->tqi_cwmin
;
2248 qi
.tqi_cwmax
= qinfo
->tqi_cwmax
;
2249 qi
.tqi_burstTime
= qinfo
->tqi_burstTime
;
2250 qi
.tqi_readyTime
= qinfo
->tqi_readyTime
;
2252 if (!ath9k_hw_set_txq_props(ah
, qnum
, &qi
)) {
2253 DPRINTF(sc
, ATH_DBG_FATAL
,
2254 "%s: unable to update hardware queue %u!\n",
2258 ath9k_hw_resettxqueue(ah
, qnum
); /* push to h/w */
2264 int ath_cabq_update(struct ath_softc
*sc
)
2266 struct ath9k_tx_queue_info qi
;
2267 int qnum
= sc
->sc_cabq
->axq_qnum
;
2268 struct ath_beacon_config conf
;
2270 ath9k_hw_get_txq_props(sc
->sc_ah
, qnum
, &qi
);
2272 * Ensure the readytime % is within the bounds.
2274 if (sc
->sc_config
.cabqReadytime
< ATH9K_READY_TIME_LO_BOUND
)
2275 sc
->sc_config
.cabqReadytime
= ATH9K_READY_TIME_LO_BOUND
;
2276 else if (sc
->sc_config
.cabqReadytime
> ATH9K_READY_TIME_HI_BOUND
)
2277 sc
->sc_config
.cabqReadytime
= ATH9K_READY_TIME_HI_BOUND
;
2279 ath_get_beaconconfig(sc
, ATH_IF_ID_ANY
, &conf
);
2281 (conf
.beacon_interval
* sc
->sc_config
.cabqReadytime
) / 100;
2282 ath_txq_update(sc
, qnum
, &qi
);
2287 int ath_tx_start(struct ath_softc
*sc
, struct sk_buff
*skb
)
2289 struct ath_tx_control txctl
;
2292 memset(&txctl
, 0, sizeof(struct ath_tx_control
));
2293 error
= ath_tx_prepare(sc
, skb
, &txctl
);
2296 * Start DMA mapping.
2297 * ath_tx_start_dma() will be called either synchronously
2298 * or asynchrounsly once DMA is complete.
2300 xmit_map_sg(sc
, skb
, &txctl
);
2302 ath_node_put(sc
, txctl
.an
, ATH9K_BH_STATUS_CHANGE
);
2304 /* failed packets will be dropped by the caller */
2308 /* Deferred processing of transmit interrupt */
2310 void ath_tx_tasklet(struct ath_softc
*sc
)
2313 u32 qcumask
= ((1 << ATH9K_NUM_TX_QUEUES
) - 1);
2315 ath9k_hw_gettxintrtxqs(sc
->sc_ah
, &qcumask
);
2318 * Process each active queue.
2320 for (i
= 0; i
< ATH9K_NUM_TX_QUEUES
; i
++) {
2321 if (ATH_TXQ_SETUP(sc
, i
) && (qcumask
& (1 << i
)))
2322 ath_tx_processq(sc
, &sc
->sc_txq
[i
]);
2326 void ath_tx_draintxq(struct ath_softc
*sc
,
2327 struct ath_txq
*txq
, bool retry_tx
)
2329 struct ath_buf
*bf
, *lastbf
;
2330 struct list_head bf_head
;
2332 INIT_LIST_HEAD(&bf_head
);
2335 * NB: this assumes output has been stopped and
2336 * we do not need to block ath_tx_tasklet
2339 spin_lock_bh(&txq
->axq_lock
);
2341 if (list_empty(&txq
->axq_q
)) {
2342 txq
->axq_link
= NULL
;
2343 txq
->axq_linkbuf
= NULL
;
2344 spin_unlock_bh(&txq
->axq_lock
);
2348 bf
= list_first_entry(&txq
->axq_q
, struct ath_buf
, list
);
2350 if (bf
->bf_status
& ATH_BUFSTATUS_STALE
) {
2351 list_del(&bf
->list
);
2352 spin_unlock_bh(&txq
->axq_lock
);
2354 spin_lock_bh(&sc
->sc_txbuflock
);
2355 list_add_tail(&bf
->list
, &sc
->sc_txbuf
);
2356 spin_unlock_bh(&sc
->sc_txbuflock
);
2360 lastbf
= bf
->bf_lastbf
;
2362 lastbf
->bf_desc
->ds_txstat
.ts_flags
=
2363 ATH9K_TX_SW_ABORTED
;
2365 /* remove ath_buf's of the same mpdu from txq */
2366 list_cut_position(&bf_head
, &txq
->axq_q
, &lastbf
->list
);
2369 spin_unlock_bh(&txq
->axq_lock
);
2372 ath_tx_complete_aggr_rifs(sc
, txq
, bf
, &bf_head
, 0);
2374 ath_tx_complete_buf(sc
, bf
, &bf_head
, 0, 0);
2377 /* flush any pending frames if aggregation is enabled */
2378 if (sc
->sc_flags
& SC_OP_TXAGGR
) {
2380 spin_lock_bh(&txq
->axq_lock
);
2381 ath_txq_drain_pending_buffers(sc
, txq
,
2382 ATH9K_BH_STATUS_CHANGE
);
2383 spin_unlock_bh(&txq
->axq_lock
);
2388 /* Drain the transmit queues and reclaim resources */
2390 void ath_draintxq(struct ath_softc
*sc
, bool retry_tx
)
2392 /* stop beacon queue. The beacon will be freed when
2393 * we go to INIT state */
2394 if (!(sc
->sc_flags
& SC_OP_INVALID
)) {
2395 (void) ath9k_hw_stoptxdma(sc
->sc_ah
, sc
->sc_bhalq
);
2396 DPRINTF(sc
, ATH_DBG_XMIT
, "%s: beacon queue %x\n", __func__
,
2397 ath9k_hw_gettxbuf(sc
->sc_ah
, sc
->sc_bhalq
));
2400 ath_drain_txdataq(sc
, retry_tx
);
2403 u32
ath_txq_depth(struct ath_softc
*sc
, int qnum
)
2405 return sc
->sc_txq
[qnum
].axq_depth
;
2408 u32
ath_txq_aggr_depth(struct ath_softc
*sc
, int qnum
)
2410 return sc
->sc_txq
[qnum
].axq_aggr_depth
;
2413 /* Check if an ADDBA is required. A valid node must be passed. */
2414 enum ATH_AGGR_CHECK
ath_tx_aggr_check(struct ath_softc
*sc
,
2415 struct ath_node
*an
,
2418 struct ath_atx_tid
*txtid
;
2419 DECLARE_MAC_BUF(mac
);
2421 if (!(sc
->sc_flags
& SC_OP_TXAGGR
))
2422 return AGGR_NOT_REQUIRED
;
2424 /* ADDBA exchange must be completed before sending aggregates */
2425 txtid
= ATH_AN_2_TID(an
, tidno
);
2427 if (txtid
->addba_exchangecomplete
)
2428 return AGGR_EXCHANGE_DONE
;
2430 if (txtid
->cleanup_inprogress
)
2431 return AGGR_CLEANUP_PROGRESS
;
2433 if (txtid
->addba_exchangeinprogress
)
2434 return AGGR_EXCHANGE_PROGRESS
;
2436 if (!txtid
->addba_exchangecomplete
) {
2437 if (!txtid
->addba_exchangeinprogress
&&
2438 (txtid
->addba_exchangeattempts
< ADDBA_EXCHANGE_ATTEMPTS
)) {
2439 txtid
->addba_exchangeattempts
++;
2440 return AGGR_REQUIRED
;
2444 return AGGR_NOT_REQUIRED
;
2447 /* Start TX aggregation */
2449 int ath_tx_aggr_start(struct ath_softc
*sc
,
2454 struct ath_atx_tid
*txtid
;
2455 struct ath_node
*an
;
2457 spin_lock_bh(&sc
->node_lock
);
2458 an
= ath_node_find(sc
, (u8
*) addr
);
2459 spin_unlock_bh(&sc
->node_lock
);
2462 DPRINTF(sc
, ATH_DBG_AGGR
,
2463 "%s: Node not found to initialize "
2464 "TX aggregation\n", __func__
);
2468 if (sc
->sc_flags
& SC_OP_TXAGGR
) {
2469 txtid
= ATH_AN_2_TID(an
, tid
);
2470 txtid
->addba_exchangeinprogress
= 1;
2471 ath_tx_pause_tid(sc
, txtid
);
2477 /* Stop tx aggregation */
2479 int ath_tx_aggr_stop(struct ath_softc
*sc
,
2483 struct ath_node
*an
;
2485 spin_lock_bh(&sc
->node_lock
);
2486 an
= ath_node_find(sc
, (u8
*) addr
);
2487 spin_unlock_bh(&sc
->node_lock
);
2490 DPRINTF(sc
, ATH_DBG_AGGR
,
2491 "%s: TX aggr stop for non-existent node\n", __func__
);
2495 ath_tx_aggr_teardown(sc
, an
, tid
);
2500 * Performs transmit side cleanup when TID changes from aggregated to
2502 * - Pause the TID and mark cleanup in progress
2503 * - Discard all retry frames from the s/w queue.
2506 void ath_tx_aggr_teardown(struct ath_softc
*sc
,
2507 struct ath_node
*an
, u8 tid
)
2509 struct ath_atx_tid
*txtid
= ATH_AN_2_TID(an
, tid
);
2510 struct ath_txq
*txq
= &sc
->sc_txq
[txtid
->ac
->qnum
];
2512 struct list_head bf_head
;
2513 INIT_LIST_HEAD(&bf_head
);
2515 DPRINTF(sc
, ATH_DBG_AGGR
, "%s: teardown TX aggregation\n", __func__
);
2517 if (txtid
->cleanup_inprogress
) /* cleanup is in progress */
2520 if (!txtid
->addba_exchangecomplete
) {
2521 txtid
->addba_exchangeattempts
= 0;
2525 /* TID must be paused first */
2526 ath_tx_pause_tid(sc
, txtid
);
2528 /* drop all software retried frames and mark this TID */
2529 spin_lock_bh(&txq
->axq_lock
);
2530 while (!list_empty(&txtid
->buf_q
)) {
2531 bf
= list_first_entry(&txtid
->buf_q
, struct ath_buf
, list
);
2532 if (!bf_isretried(bf
)) {
2534 * NB: it's based on the assumption that
2535 * software retried frame will always stay
2536 * at the head of software queue.
2540 list_cut_position(&bf_head
,
2541 &txtid
->buf_q
, &bf
->bf_lastfrm
->list
);
2542 ath_tx_update_baw(sc
, txtid
, bf
->bf_seqno
);
2544 /* complete this sub-frame */
2545 ath_tx_complete_buf(sc
, bf
, &bf_head
, 0, 0);
2548 if (txtid
->baw_head
!= txtid
->baw_tail
) {
2549 spin_unlock_bh(&txq
->axq_lock
);
2550 txtid
->cleanup_inprogress
= true;
2552 txtid
->addba_exchangecomplete
= 0;
2553 txtid
->addba_exchangeattempts
= 0;
2554 spin_unlock_bh(&txq
->axq_lock
);
2555 ath_tx_flush_tid(sc
, txtid
);
2560 * Tx scheduling logic
2561 * NB: must be called with txq lock held
2564 void ath_txq_schedule(struct ath_softc
*sc
, struct ath_txq
*txq
)
2566 struct ath_atx_ac
*ac
;
2567 struct ath_atx_tid
*tid
;
2569 /* nothing to schedule */
2570 if (list_empty(&txq
->axq_acq
))
2573 * get the first node/ac pair on the queue
2575 ac
= list_first_entry(&txq
->axq_acq
, struct ath_atx_ac
, list
);
2576 list_del(&ac
->list
);
2580 * process a single tid per destination
2583 /* nothing to schedule */
2584 if (list_empty(&ac
->tid_q
))
2587 tid
= list_first_entry(&ac
->tid_q
, struct ath_atx_tid
, list
);
2588 list_del(&tid
->list
);
2591 if (tid
->paused
) /* check next tid to keep h/w busy */
2594 if (!(tid
->an
->an_smmode
== ATH_SM_PWRSAV_DYNAMIC
) ||
2595 ((txq
->axq_depth
% 2) == 0)) {
2596 ath_tx_sched_aggr(sc
, txq
, tid
);
2600 * add tid to round-robin queue if more frames
2601 * are pending for the tid
2603 if (!list_empty(&tid
->buf_q
))
2604 ath_tx_queue_tid(txq
, tid
);
2606 /* only schedule one TID at a time */
2608 } while (!list_empty(&ac
->tid_q
));
2611 * schedule AC if more TIDs need processing
2613 if (!list_empty(&ac
->tid_q
)) {
2615 * add dest ac to txq if not already added
2619 list_add_tail(&ac
->list
, &txq
->axq_acq
);
2624 /* Initialize per-node transmit state */
2626 void ath_tx_node_init(struct ath_softc
*sc
, struct ath_node
*an
)
2628 if (sc
->sc_flags
& SC_OP_TXAGGR
) {
2629 struct ath_atx_tid
*tid
;
2630 struct ath_atx_ac
*ac
;
2633 sc
->sc_ht_info
.maxampdu
= ATH_AMPDU_LIMIT_DEFAULT
;
2636 * Init per tid tx state
2638 for (tidno
= 0, tid
= &an
->an_aggr
.tx
.tid
[tidno
];
2639 tidno
< WME_NUM_TID
;
2643 tid
->seq_start
= tid
->seq_next
= 0;
2644 tid
->baw_size
= WME_MAX_BA
;
2645 tid
->baw_head
= tid
->baw_tail
= 0;
2647 tid
->paused
= false;
2648 tid
->cleanup_inprogress
= false;
2649 INIT_LIST_HEAD(&tid
->buf_q
);
2651 acno
= TID_TO_WME_AC(tidno
);
2652 tid
->ac
= &an
->an_aggr
.tx
.ac
[acno
];
2655 tid
->addba_exchangecomplete
= 0;
2656 tid
->addba_exchangeinprogress
= 0;
2657 tid
->addba_exchangeattempts
= 0;
2661 * Init per ac tx state
2663 for (acno
= 0, ac
= &an
->an_aggr
.tx
.ac
[acno
];
2664 acno
< WME_NUM_AC
; acno
++, ac
++) {
2666 INIT_LIST_HEAD(&ac
->tid_q
);
2670 ac
->qnum
= ath_tx_get_qnum(sc
,
2671 ATH9K_TX_QUEUE_DATA
, ATH9K_WME_AC_BE
);
2674 ac
->qnum
= ath_tx_get_qnum(sc
,
2675 ATH9K_TX_QUEUE_DATA
, ATH9K_WME_AC_BK
);
2678 ac
->qnum
= ath_tx_get_qnum(sc
,
2679 ATH9K_TX_QUEUE_DATA
, ATH9K_WME_AC_VI
);
2682 ac
->qnum
= ath_tx_get_qnum(sc
,
2683 ATH9K_TX_QUEUE_DATA
, ATH9K_WME_AC_VO
);
2690 /* Cleanupthe pending buffers for the node. */
2692 void ath_tx_node_cleanup(struct ath_softc
*sc
,
2693 struct ath_node
*an
, bool bh_flag
)
2696 struct ath_atx_ac
*ac
, *ac_tmp
;
2697 struct ath_atx_tid
*tid
, *tid_tmp
;
2698 struct ath_txq
*txq
;
2699 for (i
= 0; i
< ATH9K_NUM_TX_QUEUES
; i
++) {
2700 if (ATH_TXQ_SETUP(sc
, i
)) {
2701 txq
= &sc
->sc_txq
[i
];
2703 if (likely(bh_flag
))
2704 spin_lock_bh(&txq
->axq_lock
);
2706 spin_lock(&txq
->axq_lock
);
2708 list_for_each_entry_safe(ac
,
2709 ac_tmp
, &txq
->axq_acq
, list
) {
2710 tid
= list_first_entry(&ac
->tid_q
,
2711 struct ath_atx_tid
, list
);
2712 if (tid
&& tid
->an
!= an
)
2714 list_del(&ac
->list
);
2717 list_for_each_entry_safe(tid
,
2718 tid_tmp
, &ac
->tid_q
, list
) {
2719 list_del(&tid
->list
);
2721 ath_tid_drain(sc
, txq
, tid
, bh_flag
);
2722 tid
->addba_exchangecomplete
= 0;
2723 tid
->addba_exchangeattempts
= 0;
2724 tid
->cleanup_inprogress
= false;
2728 if (likely(bh_flag
))
2729 spin_unlock_bh(&txq
->axq_lock
);
2731 spin_unlock(&txq
->axq_lock
);
2736 /* Cleanup per node transmit state */
2738 void ath_tx_node_free(struct ath_softc
*sc
, struct ath_node
*an
)
2740 if (sc
->sc_flags
& SC_OP_TXAGGR
) {
2741 struct ath_atx_tid
*tid
;
2744 /* Init per tid rx state */
2745 for (tidno
= 0, tid
= &an
->an_aggr
.tx
.tid
[tidno
];
2746 tidno
< WME_NUM_TID
;
2749 for (i
= 0; i
< ATH_TID_MAX_BUFS
; i
++)
2750 ASSERT(tid
->tx_buf
[i
] == NULL
);
2755 void ath_tx_cabq(struct ath_softc
*sc
, struct sk_buff
*skb
)
2757 int hdrlen
, padsize
;
2758 struct ieee80211_tx_info
*info
= IEEE80211_SKB_CB(skb
);
2759 struct ath_tx_control txctl
;
2762 * As a temporary workaround, assign seq# here; this will likely need
2763 * to be cleaned up to work better with Beacon transmission and virtual
2766 if (info
->flags
& IEEE80211_TX_CTL_ASSIGN_SEQ
) {
2767 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*) skb
->data
;
2768 if (info
->flags
& IEEE80211_TX_CTL_FIRST_FRAGMENT
)
2770 hdr
->seq_ctrl
&= cpu_to_le16(IEEE80211_SCTL_FRAG
);
2771 hdr
->seq_ctrl
|= cpu_to_le16(sc
->seq_no
);
2774 /* Add the padding after the header if this is not already done */
2775 hdrlen
= ieee80211_get_hdrlen_from_skb(skb
);
2777 padsize
= hdrlen
% 4;
2778 if (skb_headroom(skb
) < padsize
) {
2779 DPRINTF(sc
, ATH_DBG_XMIT
, "%s: TX CABQ padding "
2780 "failed\n", __func__
);
2781 dev_kfree_skb_any(skb
);
2784 skb_push(skb
, padsize
);
2785 memmove(skb
->data
, skb
->data
+ padsize
, hdrlen
);
2788 DPRINTF(sc
, ATH_DBG_XMIT
, "%s: transmitting CABQ packet, skb: %p\n",
2792 memset(&txctl
, 0, sizeof(struct ath_tx_control
));
2793 txctl
.flags
= ATH9K_TXDESC_CAB
;
2794 if (ath_tx_prepare(sc
, skb
, &txctl
) == 0) {
2796 * Start DMA mapping.
2797 * ath_tx_start_dma() will be called either synchronously
2798 * or asynchrounsly once DMA is complete.
2800 xmit_map_sg(sc
, skb
, &txctl
);
2802 ath_node_put(sc
, txctl
.an
, ATH9K_BH_STATUS_CHANGE
);
2803 DPRINTF(sc
, ATH_DBG_XMIT
, "%s: TX CABQ failed\n", __func__
);
2804 dev_kfree_skb_any(skb
);