drivers/net/wireless/b43/b43.h

   1 #ifndef B43_H_
   2 #define B43_H_
   3
   4 #include <linux/kernel.h>
   5 #include <linux/spinlock.h>
   6 #include <linux/interrupt.h>
   7 #include <linux/hw_random.h>
   8 #include <linux/ssb/ssb.h>
   9 #include <net/mac80211.h>
  10
  11 #include "debugfs.h"
  12 #include "leds.h"
  13 #include "lo.h"
  14 #include "phy.h"
  15
  16 #ifdef CONFIG_B43_DEBUG
  17 # define B43_DEBUG      1
  18 #else
  19 # define B43_DEBUG      0
  20 #endif
  21
  22 #define B43_RX_MAX_SSI                  60
  23
  24 /* MMIO offsets */
  25 #define B43_MMIO_DMA0_REASON            0x20
  26 #define B43_MMIO_DMA0_IRQ_MASK          0x24
  27 #define B43_MMIO_DMA1_REASON            0x28
  28 #define B43_MMIO_DMA1_IRQ_MASK          0x2C
  29 #define B43_MMIO_DMA2_REASON            0x30
  30 #define B43_MMIO_DMA2_IRQ_MASK          0x34
  31 #define B43_MMIO_DMA3_REASON            0x38
  32 #define B43_MMIO_DMA3_IRQ_MASK          0x3C
  33 #define B43_MMIO_DMA4_REASON            0x40
  34 #define B43_MMIO_DMA4_IRQ_MASK          0x44
  35 #define B43_MMIO_DMA5_REASON            0x48
  36 #define B43_MMIO_DMA5_IRQ_MASK          0x4C
  37 #define B43_MMIO_MACCTL                 0x120
  38 #define B43_MMIO_STATUS2_BITFIELD       0x124
  39 #define B43_MMIO_GEN_IRQ_REASON         0x128
  40 #define B43_MMIO_GEN_IRQ_MASK           0x12C
  41 #define B43_MMIO_RAM_CONTROL            0x130
  42 #define B43_MMIO_RAM_DATA               0x134
  43 #define B43_MMIO_PS_STATUS              0x140
  44 #define B43_MMIO_RADIO_HWENABLED_HI     0x158
  45 #define B43_MMIO_SHM_CONTROL            0x160
  46 #define B43_MMIO_SHM_DATA               0x164
  47 #define B43_MMIO_SHM_DATA_UNALIGNED     0x166
  48 #define B43_MMIO_XMITSTAT_0             0x170
  49 #define B43_MMIO_XMITSTAT_1             0x174
  50 #define B43_MMIO_REV3PLUS_TSF_LOW       0x180   /* core rev >= 3 only */
  51 #define B43_MMIO_REV3PLUS_TSF_HIGH      0x184   /* core rev >= 3 only */
  52
  53 /* 32-bit DMA */
  54 #define B43_MMIO_DMA32_BASE0            0x200
  55 #define B43_MMIO_DMA32_BASE1            0x220
  56 #define B43_MMIO_DMA32_BASE2            0x240
  57 #define B43_MMIO_DMA32_BASE3            0x260
  58 #define B43_MMIO_DMA32_BASE4            0x280
  59 #define B43_MMIO_DMA32_BASE5            0x2A0
  60 /* 64-bit DMA */
  61 #define B43_MMIO_DMA64_BASE0            0x200
  62 #define B43_MMIO_DMA64_BASE1            0x240
  63 #define B43_MMIO_DMA64_BASE2            0x280
  64 #define B43_MMIO_DMA64_BASE3            0x2C0
  65 #define B43_MMIO_DMA64_BASE4            0x300
  66 #define B43_MMIO_DMA64_BASE5            0x340
  67 /* PIO */
  68 #define B43_MMIO_PIO1_BASE              0x300
  69 #define B43_MMIO_PIO2_BASE              0x310
  70 #define B43_MMIO_PIO3_BASE              0x320
  71 #define B43_MMIO_PIO4_BASE              0x330
  72
  73 #define B43_MMIO_PHY_VER                0x3E0
  74 #define B43_MMIO_PHY_RADIO              0x3E2
  75 #define B43_MMIO_PHY0                   0x3E6
  76 #define B43_MMIO_ANTENNA                0x3E8
  77 #define B43_MMIO_CHANNEL                0x3F0
  78 #define B43_MMIO_CHANNEL_EXT            0x3F4
  79 #define B43_MMIO_RADIO_CONTROL          0x3F6
  80 #define B43_MMIO_RADIO_DATA_HIGH        0x3F8
  81 #define B43_MMIO_RADIO_DATA_LOW         0x3FA
  82 #define B43_MMIO_PHY_CONTROL            0x3FC
  83 #define B43_MMIO_PHY_DATA               0x3FE
  84 #define B43_MMIO_MACFILTER_CONTROL      0x420
  85 #define B43_MMIO_MACFILTER_DATA         0x422
  86 #define B43_MMIO_RCMTA_COUNT            0x43C
  87 #define B43_MMIO_RADIO_HWENABLED_LO     0x49A
  88 #define B43_MMIO_GPIO_CONTROL           0x49C
  89 #define B43_MMIO_GPIO_MASK              0x49E
  90 #define B43_MMIO_TSF_0                  0x632   /* core rev < 3 only */
  91 #define B43_MMIO_TSF_1                  0x634   /* core rev < 3 only */
  92 #define B43_MMIO_TSF_2                  0x636   /* core rev < 3 only */
  93 #define B43_MMIO_TSF_3                  0x638   /* core rev < 3 only */
  94 #define B43_MMIO_RNG                    0x65A
  95 #define B43_MMIO_POWERUP_DELAY          0x6A8
  96
  97 /* SPROM boardflags_lo values */
  98 #define B43_BFL_BTCOEXIST               0x0001  /* implements Bluetooth coexistance */
  99 #define B43_BFL_PACTRL                  0x0002  /* GPIO 9 controlling the PA */
 100 #define B43_BFL_AIRLINEMODE             0x0004  /* implements GPIO 13 radio disable indication */
 101 #define B43_BFL_RSSI                    0x0008  /* software calculates nrssi slope. */
 102 #define B43_BFL_ENETSPI                 0x0010  /* has ephy roboswitch spi */
 103 #define B43_BFL_XTAL_NOSLOW             0x0020  /* no slow clock available */
 104 #define B43_BFL_CCKHIPWR                0x0040  /* can do high power CCK transmission */
 105 #define B43_BFL_ENETADM                 0x0080  /* has ADMtek switch */
 106 #define B43_BFL_ENETVLAN                0x0100  /* can do vlan */
 107 #define B43_BFL_AFTERBURNER             0x0200  /* supports Afterburner mode */
 108 #define B43_BFL_NOPCI                   0x0400  /* leaves PCI floating */
 109 #define B43_BFL_FEM                     0x0800  /* supports the Front End Module */
 110 #define B43_BFL_EXTLNA                  0x1000  /* has an external LNA */
 111 #define B43_BFL_HGPA                    0x2000  /* had high gain PA */
 112 #define B43_BFL_BTCMOD                  0x4000  /* BFL_BTCOEXIST is given in alternate GPIOs */
 113 #define B43_BFL_ALTIQ                   0x8000  /* alternate I/Q settings */
 114
 115 /* GPIO register offset, in both ChipCommon and PCI core. */
 116 #define B43_GPIO_CONTROL                0x6c
 117
 118 /* SHM Routing */
 119 enum {
 120         B43_SHM_UCODE,          /* Microcode memory */
 121         B43_SHM_SHARED,         /* Shared memory */
 122         B43_SHM_SCRATCH,        /* Scratch memory */
 123         B43_SHM_HW,             /* Internal hardware register */
 124         B43_SHM_RCMTA,          /* Receive match transmitter address (rev >= 5 only) */
 125 };
 126 /* SHM Routing modifiers */
 127 #define B43_SHM_AUTOINC_R               0x0200  /* Auto-increment address on read */
 128 #define B43_SHM_AUTOINC_W               0x0100  /* Auto-increment address on write */
 129 #define B43_SHM_AUTOINC_RW              (B43_SHM_AUTOINC_R | \
 130                                          B43_SHM_AUTOINC_W)
 131
 132 /* Misc SHM_SHARED offsets */
 133 #define B43_SHM_SH_WLCOREREV            0x0016  /* 802.11 core revision */
 134 #define B43_SHM_SH_PCTLWDPOS            0x0008
 135 #define B43_SHM_SH_RXPADOFF             0x0034  /* RX Padding data offset (PIO only) */
 136 #define B43_SHM_SH_PHYVER               0x0050  /* PHY version */
 137 #define B43_SHM_SH_PHYTYPE              0x0052  /* PHY type */
 138 #define B43_SHM_SH_ANTSWAP              0x005C  /* Antenna swap threshold */
 139 #define B43_SHM_SH_HOSTFLO              0x005E  /* Hostflags for ucode options (low) */
 140 #define B43_SHM_SH_HOSTFHI              0x0060  /* Hostflags for ucode options (high) */
 141 #define B43_SHM_SH_RFATT                0x0064  /* Current radio attenuation value */
 142 #define B43_SHM_SH_RADAR                0x0066  /* Radar register */
 143 #define B43_SHM_SH_PHYTXNOI             0x006E  /* PHY noise directly after TX (lower 8bit only) */
 144 #define B43_SHM_SH_RFRXSP1              0x0072  /* RF RX SP Register 1 */
 145 #define B43_SHM_SH_CHAN                 0x00A0  /* Current channel (low 8bit only) */
 146 #define  B43_SHM_SH_CHAN_5GHZ           0x0100  /* Bit set, if 5Ghz channel */
 147 #define B43_SHM_SH_BCMCFIFOID           0x0108  /* Last posted cookie to the bcast/mcast FIFO */
 148 /* SHM_SHARED TX FIFO variables */
 149 #define B43_SHM_SH_SIZE01               0x0098  /* TX FIFO size for FIFO 0 (low) and 1 (high) */
 150 #define B43_SHM_SH_SIZE23               0x009A  /* TX FIFO size for FIFO 2 and 3 */
 151 #define B43_SHM_SH_SIZE45               0x009C  /* TX FIFO size for FIFO 4 and 5 */
 152 #define B43_SHM_SH_SIZE67               0x009E  /* TX FIFO size for FIFO 6 and 7 */
 153 /* SHM_SHARED background noise */
 154 #define B43_SHM_SH_JSSI0                0x0088  /* Measure JSSI 0 */
 155 #define B43_SHM_SH_JSSI1                0x008A  /* Measure JSSI 1 */
 156 #define B43_SHM_SH_JSSIAUX              0x008C  /* Measure JSSI AUX */
 157 /* SHM_SHARED crypto engine */
 158 #define B43_SHM_SH_DEFAULTIV            0x003C  /* Default IV location */
 159 #define B43_SHM_SH_NRRXTRANS            0x003E  /* # of soft RX transmitter addresses (max 8) */
 160 #define B43_SHM_SH_KTP                  0x0056  /* Key table pointer */
 161 #define B43_SHM_SH_TKIPTSCTTAK          0x0318
 162 #define B43_SHM_SH_KEYIDXBLOCK          0x05D4  /* Key index/algorithm block (v4 firmware) */
 163 #define B43_SHM_SH_PSM                  0x05F4  /* PSM transmitter address match block (rev < 5) */
 164 /* SHM_SHARED WME variables */
 165 #define B43_SHM_SH_EDCFSTAT             0x000E  /* EDCF status */
 166 #define B43_SHM_SH_TXFCUR               0x0030  /* TXF current index */
 167 #define B43_SHM_SH_EDCFQ                0x0240  /* EDCF Q info */
 168 /* SHM_SHARED powersave mode related */
 169 #define B43_SHM_SH_SLOTT                0x0010  /* Slot time */
 170 #define B43_SHM_SH_DTIMPER              0x0012  /* DTIM period */
 171 #define B43_SHM_SH_NOSLPZNATDTIM        0x004C  /* NOSLPZNAT DTIM */
 172 /* SHM_SHARED beacon variables */
 173 #define B43_SHM_SH_BTL0                 0x0018  /* Beacon template length 0 */
 174 #define B43_SHM_SH_BTL1                 0x001A  /* Beacon template length 1 */
 175 #define B43_SHM_SH_BTSFOFF              0x001C  /* Beacon TSF offset */
 176 #define B43_SHM_SH_TIMBPOS              0x001E  /* TIM B position in beacon */
 177 #define B43_SHM_SH_SFFBLIM              0x0044  /* Short frame fallback retry limit */
 178 #define B43_SHM_SH_LFFBLIM              0x0046  /* Long frame fallback retry limit */
 179 #define B43_SHM_SH_BEACPHYCTL           0x0054  /* Beacon PHY TX control word (see PHY TX control) */
 180 /* SHM_SHARED ACK/CTS control */
 181 #define B43_SHM_SH_ACKCTSPHYCTL         0x0022  /* ACK/CTS PHY control word (see PHY TX control) */
 182 /* SHM_SHARED probe response variables */
 183 #define B43_SHM_SH_PRSSID               0x0160  /* Probe Response SSID */
 184 #define B43_SHM_SH_PRSSIDLEN            0x0048  /* Probe Response SSID length */
 185 #define B43_SHM_SH_PRTLEN               0x004A  /* Probe Response template length */
 186 #define B43_SHM_SH_PRMAXTIME            0x0074  /* Probe Response max time */
 187 #define B43_SHM_SH_PRPHYCTL             0x0188  /* Probe Response PHY TX control word */
 188 /* SHM_SHARED rate tables */
 189 #define B43_SHM_SH_OFDMDIRECT           0x01C0  /* Pointer to OFDM direct map */
 190 #define B43_SHM_SH_OFDMBASIC            0x01E0  /* Pointer to OFDM basic rate map */
 191 #define B43_SHM_SH_CCKDIRECT            0x0200  /* Pointer to CCK direct map */
 192 #define B43_SHM_SH_CCKBASIC             0x0220  /* Pointer to CCK basic rate map */
 193 /* SHM_SHARED microcode soft registers */
 194 #define B43_SHM_SH_UCODEREV             0x0000  /* Microcode revision */
 195 #define B43_SHM_SH_UCODEPATCH           0x0002  /* Microcode patchlevel */
 196 #define B43_SHM_SH_UCODEDATE            0x0004  /* Microcode date */
 197 #define B43_SHM_SH_UCODETIME            0x0006  /* Microcode time */
 198 #define B43_SHM_SH_UCODESTAT            0x0040  /* Microcode debug status code */
 199 #define  B43_SHM_SH_UCODESTAT_INVALID   0
 200 #define  B43_SHM_SH_UCODESTAT_INIT      1
 201 #define  B43_SHM_SH_UCODESTAT_ACTIVE    2
 202 #define  B43_SHM_SH_UCODESTAT_SUSP      3       /* suspended */
 203 #define  B43_SHM_SH_UCODESTAT_SLEEP     4       /* asleep (PS) */
 204 #define B43_SHM_SH_MAXBFRAMES           0x0080  /* Maximum number of frames in a burst */
 205 #define B43_SHM_SH_SPUWKUP              0x0094  /* pre-wakeup for synth PU in us */
 206 #define B43_SHM_SH_PRETBTT              0x0096  /* pre-TBTT in us */
 207
 208 /* SHM_SCRATCH offsets */
 209 #define B43_SHM_SC_MINCONT              0x0003  /* Minimum contention window */
 210 #define B43_SHM_SC_MAXCONT              0x0004  /* Maximum contention window */
 211 #define B43_SHM_SC_CURCONT              0x0005  /* Current contention window */
 212 #define B43_SHM_SC_SRLIMIT              0x0006  /* Short retry count limit */
 213 #define B43_SHM_SC_LRLIMIT              0x0007  /* Long retry count limit */
 214 #define B43_SHM_SC_DTIMC                0x0008  /* Current DTIM count */
 215 #define B43_SHM_SC_BTL0LEN              0x0015  /* Beacon 0 template length */
 216 #define B43_SHM_SC_BTL1LEN              0x0016  /* Beacon 1 template length */
 217 #define B43_SHM_SC_SCFB                 0x0017  /* Short frame transmit count threshold for rate fallback */
 218 #define B43_SHM_SC_LCFB                 0x0018  /* Long frame transmit count threshold for rate fallback */
 219
 220 /* Hardware Radio Enable masks */
 221 #define B43_MMIO_RADIO_HWENABLED_HI_MASK (1 << 16)
 222 #define B43_MMIO_RADIO_HWENABLED_LO_MASK (1 << 4)
 223
 224 /* HostFlags. See b43_hf_read/write() */
 225 #define B43_HF_ANTDIVHELP               0x00000001      /* ucode antenna div helper */
 226 #define B43_HF_SYMW                     0x00000002      /* G-PHY SYM workaround */
 227 #define B43_HF_RXPULLW                  0x00000004      /* RX pullup workaround */
 228 #define B43_HF_CCKBOOST                 0x00000008      /* 4dB CCK power boost (exclusive with OFDM boost) */
 229 #define B43_HF_BTCOEX                   0x00000010      /* Bluetooth coexistance */
 230 #define B43_HF_GDCW                     0x00000020      /* G-PHY DV canceller filter bw workaround */
 231 #define B43_HF_OFDMPABOOST              0x00000040      /* Enable PA gain boost for OFDM */
 232 #define B43_HF_ACPR                     0x00000080      /* Disable for Japan, channel 14 */
 233 #define B43_HF_EDCF                     0x00000100      /* on if WME and MAC suspended */
 234 #define B43_HF_TSSIRPSMW                0x00000200      /* TSSI reset PSM ucode workaround */
 235 #define B43_HF_DSCRQ                    0x00000400      /* Disable slow clock request in ucode */
 236 #define B43_HF_ACIW                     0x00000800      /* ACI workaround: shift bits by 2 on PHY CRS */
 237 #define B43_HF_2060W                    0x00001000      /* 2060 radio workaround */
 238 #define B43_HF_RADARW                   0x00002000      /* Radar workaround */
 239 #define B43_HF_USEDEFKEYS               0x00004000      /* Enable use of default keys */
 240 #define B43_HF_BT4PRIOCOEX              0x00010000      /* Bluetooth 2-priority coexistance */
 241 #define B43_HF_FWKUP                    0x00020000      /* Fast wake-up ucode */
 242 #define B43_HF_VCORECALC                0x00040000      /* Force VCO recalculation when powering up synthpu */
 243 #define B43_HF_PCISCW                   0x00080000      /* PCI slow clock workaround */
 244 #define B43_HF_4318TSSI                 0x00200000      /* 4318 TSSI */
 245 #define B43_HF_FBCMCFIFO                0x00400000      /* Flush bcast/mcast FIFO immediately */
 246 #define B43_HF_HWPCTL                   0x00800000      /* Enable hardwarre power control */
 247 #define B43_HF_BTCOEXALT                0x01000000      /* Bluetooth coexistance in alternate pins */
 248 #define B43_HF_TXBTCHECK                0x02000000      /* Bluetooth check during transmission */
 249 #define B43_HF_SKCFPUP                  0x04000000      /* Skip CFP update */
 250
 251 /* MacFilter offsets. */
 252 #define B43_MACFILTER_SELF              0x0000
 253 #define B43_MACFILTER_BSSID             0x0003
 254
 255 /* PowerControl */
 256 #define B43_PCTL_IN                     0xB0
 257 #define B43_PCTL_OUT                    0xB4
 258 #define B43_PCTL_OUTENABLE              0xB8
 259 #define B43_PCTL_XTAL_POWERUP           0x40
 260 #define B43_PCTL_PLL_POWERDOWN          0x80
 261
 262 /* PowerControl Clock Modes */
 263 #define B43_PCTL_CLK_FAST               0x00
 264 #define B43_PCTL_CLK_SLOW               0x01
 265 #define B43_PCTL_CLK_DYNAMIC            0x02
 266
 267 #define B43_PCTL_FORCE_SLOW             0x0800
 268 #define B43_PCTL_FORCE_PLL              0x1000
 269 #define B43_PCTL_DYN_XTAL               0x2000
 270
 271 /* PHYVersioning */
 272 #define B43_PHYTYPE_A                   0x00
 273 #define B43_PHYTYPE_B                   0x01
 274 #define B43_PHYTYPE_G                   0x02
 275
 276 /* PHYRegisters */
 277 #define B43_PHY_ILT_A_CTRL              0x0072
 278 #define B43_PHY_ILT_A_DATA1             0x0073
 279 #define B43_PHY_ILT_A_DATA2             0x0074
 280 #define B43_PHY_G_LO_CONTROL            0x0810
 281 #define B43_PHY_ILT_G_CTRL              0x0472
 282 #define B43_PHY_ILT_G_DATA1             0x0473
 283 #define B43_PHY_ILT_G_DATA2             0x0474
 284 #define B43_PHY_A_PCTL                  0x007B
 285 #define B43_PHY_G_PCTL                  0x0029
 286 #define B43_PHY_A_CRS                   0x0029
 287 #define B43_PHY_RADIO_BITFIELD          0x0401
 288 #define B43_PHY_G_CRS                   0x0429
 289 #define B43_PHY_NRSSILT_CTRL            0x0803
 290 #define B43_PHY_NRSSILT_DATA            0x0804
 291
 292 /* RadioRegisters */
 293 #define B43_RADIOCTL_ID                 0x01
 294
 295 /* MAC Control bitfield */
 296 #define B43_MACCTL_ENABLED              0x00000001      /* MAC Enabled */
 297 #define B43_MACCTL_PSM_RUN              0x00000002      /* Run Microcode */
 298 #define B43_MACCTL_PSM_JMP0             0x00000004      /* Microcode jump to 0 */
 299 #define B43_MACCTL_SHM_ENABLED          0x00000100      /* SHM Enabled */
 300 #define B43_MACCTL_SHM_UPPER            0x00000200      /* SHM Upper */
 301 #define B43_MACCTL_IHR_ENABLED          0x00000400      /* IHR Region Enabled */
 302 #define B43_MACCTL_PSM_DBG              0x00002000      /* Microcode debugging enabled */
 303 #define B43_MACCTL_GPOUTSMSK            0x0000C000      /* GPOUT Select Mask */
 304 #define B43_MACCTL_BE                   0x00010000      /* Big Endian mode */
 305 #define B43_MACCTL_INFRA                0x00020000      /* Infrastructure mode */
 306 #define B43_MACCTL_AP                   0x00040000      /* AccessPoint mode */
 307 #define B43_MACCTL_RADIOLOCK            0x00080000      /* Radio lock */
 308 #define B43_MACCTL_BEACPROMISC          0x00100000      /* Beacon Promiscuous */
 309 #define B43_MACCTL_KEEP_BADPLCP         0x00200000      /* Keep frames with bad PLCP */
 310 #define B43_MACCTL_KEEP_CTL             0x00400000      /* Keep control frames */
 311 #define B43_MACCTL_KEEP_BAD             0x00800000      /* Keep bad frames (FCS) */
 312 #define B43_MACCTL_PROMISC              0x01000000      /* Promiscuous mode */
 313 #define B43_MACCTL_HWPS                 0x02000000      /* Hardware Power Saving */
 314 #define B43_MACCTL_AWAKE                0x04000000      /* Device is awake */
 315 #define B43_MACCTL_CLOSEDNET            0x08000000      /* Closed net (no SSID bcast) */
 316 #define B43_MACCTL_TBTTHOLD             0x10000000      /* TBTT Hold */
 317 #define B43_MACCTL_DISCTXSTAT           0x20000000      /* Discard TX status */
 318 #define B43_MACCTL_DISCPMQ              0x40000000      /* Discard Power Management Queue */
 319 #define B43_MACCTL_GMODE                0x80000000      /* G Mode */
 320
 321 /* 802.11 core specific TM State Low flags */
 322 #define B43_TMSLOW_GMODE                0x20000000      /* G Mode Enable */
 323 #define B43_TMSLOW_PLLREFSEL            0x00200000      /* PLL Frequency Reference Select */
 324 #define B43_TMSLOW_MACPHYCLKEN          0x00100000      /* MAC PHY Clock Control Enable (rev >= 5) */
 325 #define B43_TMSLOW_PHYRESET             0x00080000      /* PHY Reset */
 326 #define B43_TMSLOW_PHYCLKEN             0x00040000      /* PHY Clock Enable */
 327
 328 /* 802.11 core specific TM State High flags */
 329 #define B43_TMSHIGH_FCLOCK              0x00040000      /* Fast Clock Available (rev >= 5) */
 330 #define B43_TMSHIGH_APHY                0x00020000      /* A-PHY available (rev >= 5) */
 331 #define B43_TMSHIGH_GPHY                0x00010000      /* G-PHY available (rev >= 5) */
 332
 333 /* Generic-Interrupt reasons. */
 334 #define B43_IRQ_MAC_SUSPENDED           0x00000001
 335 #define B43_IRQ_BEACON                  0x00000002
 336 #define B43_IRQ_TBTT_INDI               0x00000004
 337 #define B43_IRQ_BEACON_TX_OK            0x00000008
 338 #define B43_IRQ_BEACON_CANCEL           0x00000010
 339 #define B43_IRQ_ATIM_END                0x00000020
 340 #define B43_IRQ_PMQ                     0x00000040
 341 #define B43_IRQ_PIO_WORKAROUND          0x00000100
 342 #define B43_IRQ_MAC_TXERR               0x00000200
 343 #define B43_IRQ_PHY_TXERR               0x00000800
 344 #define B43_IRQ_PMEVENT                 0x00001000
 345 #define B43_IRQ_TIMER0                  0x00002000
 346 #define B43_IRQ_TIMER1                  0x00004000
 347 #define B43_IRQ_DMA                     0x00008000
 348 #define B43_IRQ_TXFIFO_FLUSH_OK         0x00010000
 349 #define B43_IRQ_CCA_MEASURE_OK          0x00020000
 350 #define B43_IRQ_NOISESAMPLE_OK          0x00040000
 351 #define B43_IRQ_UCODE_DEBUG             0x08000000
 352 #define B43_IRQ_RFKILL                  0x10000000
 353 #define B43_IRQ_TX_OK                   0x20000000
 354 #define B43_IRQ_PHY_G_CHANGED           0x40000000
 355 #define B43_IRQ_TIMEOUT                 0x80000000
 356
 357 #define B43_IRQ_ALL                     0xFFFFFFFF
 358 #define B43_IRQ_MASKTEMPLATE            (B43_IRQ_MAC_SUSPENDED | \
 359                                          B43_IRQ_BEACON | \
 360                                          B43_IRQ_TBTT_INDI | \
 361                                          B43_IRQ_ATIM_END | \
 362                                          B43_IRQ_PMQ | \
 363                                          B43_IRQ_MAC_TXERR | \
 364                                          B43_IRQ_PHY_TXERR | \
 365                                          B43_IRQ_DMA | \
 366                                          B43_IRQ_TXFIFO_FLUSH_OK | \
 367                                          B43_IRQ_NOISESAMPLE_OK | \
 368                                          B43_IRQ_UCODE_DEBUG | \
 369                                          B43_IRQ_RFKILL | \
 370                                          B43_IRQ_TX_OK)
 371
 372 /* Device specific rate values.
 373  * The actual values defined here are (rate_in_mbps * 2).
 374  * Some code depends on this. Don't change it. */
 375 #define B43_CCK_RATE_1MB                0x02
 376 #define B43_CCK_RATE_2MB                0x04
 377 #define B43_CCK_RATE_5MB                0x0B
 378 #define B43_CCK_RATE_11MB               0x16
 379 #define B43_OFDM_RATE_6MB               0x0C
 380 #define B43_OFDM_RATE_9MB               0x12
 381 #define B43_OFDM_RATE_12MB              0x18
 382 #define B43_OFDM_RATE_18MB              0x24
 383 #define B43_OFDM_RATE_24MB              0x30
 384 #define B43_OFDM_RATE_36MB              0x48
 385 #define B43_OFDM_RATE_48MB              0x60
 386 #define B43_OFDM_RATE_54MB              0x6C
 387 /* Convert a b43 rate value to a rate in 100kbps */
 388 #define B43_RATE_TO_BASE100KBPS(rate)   (((rate) * 10) / 2)
 389
 390 #define B43_DEFAULT_SHORT_RETRY_LIMIT   7
 391 #define B43_DEFAULT_LONG_RETRY_LIMIT    4
 392
 393 /* Max size of a security key */
 394 #define B43_SEC_KEYSIZE                 16
 395 /* Security algorithms. */
 396 enum {
 397         B43_SEC_ALGO_NONE = 0,  /* unencrypted, as of TX header. */
 398         B43_SEC_ALGO_WEP40,
 399         B43_SEC_ALGO_TKIP,
 400         B43_SEC_ALGO_AES,
 401         B43_SEC_ALGO_WEP104,
 402         B43_SEC_ALGO_AES_LEGACY,
 403 };
 404
 405 struct b43_dmaring;
 406 struct b43_pioqueue;
 407
 408 /* The firmware file header */
 409 #define B43_FW_TYPE_UCODE       'u'
 410 #define B43_FW_TYPE_PCM         'p'
 411 #define B43_FW_TYPE_IV          'i'
 412 struct b43_fw_header {
 413         /* File type */
 414         u8 type;
 415         /* File format version */
 416         u8 ver;
 417         u8 __padding[2];
 418         /* Size of the data. For ucode and PCM this is in bytes.
 419          * For IV this is number-of-ivs. */
 420         __be32 size;
 421 } __attribute__((__packed__));
 422
 423 /* Initial Value file format */
 424 #define B43_IV_OFFSET_MASK      0x7FFF
 425 #define B43_IV_32BIT            0x8000
 426 struct b43_iv {
 427         __be16 offset_size;
 428         union {
 429                 __be16 d16;
 430                 __be32 d32;
 431         } data __attribute__((__packed__));
 432 } __attribute__((__packed__));
 433
 434
 435 #define B43_PHYMODE(phytype)            (1 << (phytype))
 436 #define B43_PHYMODE_A                   B43_PHYMODE(B43_PHYTYPE_A)
 437 #define B43_PHYMODE_B                   B43_PHYMODE(B43_PHYTYPE_B)
 438 #define B43_PHYMODE_G                   B43_PHYMODE(B43_PHYTYPE_G)
 439
 440 struct b43_phy {
 441         /* Possible PHYMODEs on this PHY */
 442         u8 possible_phymodes;
 443         /* GMODE bit enabled? */
 444         bool gmode;
 445         /* Possible ieee80211 subsystem hwmodes for this PHY.
 446          * Which mode is selected, depends on thr GMODE enabled bit */
 447 #define B43_MAX_PHYHWMODES      2
 448         struct ieee80211_hw_mode hwmodes[B43_MAX_PHYHWMODES];
 449
 450         /* Analog Type */
 451         u8 analog;
 452         /* B43_PHYTYPE_ */
 453         u8 type;
 454         /* PHY revision number. */
 455         u8 rev;
 456
 457         /* Radio versioning */
 458         u16 radio_manuf;        /* Radio manufacturer */
 459         u16 radio_ver;          /* Radio version */
 460         u8 radio_rev;           /* Radio revision */
 461
 462         bool locked;            /* Only used in b43_phy_{un}lock() */
 463         bool dyn_tssi_tbl;      /* tssi2dbm is kmalloc()ed. */
 464
 465         /* ACI (adjacent channel interference) flags. */
 466         bool aci_enable;
 467         bool aci_wlan_automatic;
 468         bool aci_hw_rssi;
 469
 470         /* Radio switched on/off */
 471         bool radio_on;
 472         struct {
 473                 /* Values saved when turning the radio off.
 474                  * They are needed when turning it on again. */
 475                 bool valid;
 476                 u16 rfover;
 477                 u16 rfoverval;
 478         } radio_off_context;
 479
 480         u16 minlowsig[2];
 481         u16 minlowsigpos[2];
 482
 483         /* TSSI to dBm table in use */
 484         const s8 *tssi2dbm;
 485         /* Target idle TSSI */
 486         int tgt_idle_tssi;
 487         /* Current idle TSSI */
 488         int cur_idle_tssi;
 489
 490         /* LocalOscillator control values. */
 491         struct b43_txpower_lo_control *lo_control;
 492         /* Values from b43_calc_loopback_gain() */
 493         s16 max_lb_gain;        /* Maximum Loopback gain in hdB */
 494         s16 trsw_rx_gain;       /* TRSW RX gain in hdB */
 495         s16 lna_lod_gain;       /* LNA lod */
 496         s16 lna_gain;           /* LNA */
 497         s16 pga_gain;           /* PGA */
 498
 499         /* PHY lock for core.rev < 3
 500          * This lock is only used by b43_phy_{un}lock()
 501          */
 502         spinlock_t lock;
 503
 504         /* Desired TX power level (in dBm).
 505          * This is set by the user and adjusted in b43_phy_xmitpower(). */
 506         u8 power_level;
 507         /* A-PHY TX Power control value. */
 508         u16 txpwr_offset;
 509
 510         /* Current TX power level attenuation control values */
 511         struct b43_bbatt bbatt;
 512         struct b43_rfatt rfatt;
 513         u8 tx_control;          /* B43_TXCTL_XXX */
 514 #ifdef CONFIG_B43_DEBUG
 515         bool manual_txpower_control;    /* Manual TX-power control enabled? */
 516 #endif
 517         /* Hardware Power Control enabled? */
 518         bool hardware_power_control;
 519
 520         /* Current Interference Mitigation mode */
 521         int interfmode;
 522         /* Stack of saved values from the Interference Mitigation code.
 523          * Each value in the stack is layed out as follows:
 524          * bit 0-11:  offset
 525          * bit 12-15: register ID
 526          * bit 16-32: value
 527          * register ID is: 0x1 PHY, 0x2 Radio, 0x3 ILT
 528          */
 529 #define B43_INTERFSTACK_SIZE    26
 530         u32 interfstack[B43_INTERFSTACK_SIZE];  //FIXME: use a data structure
 531
 532         /* Saved values from the NRSSI Slope calculation */
 533         s16 nrssi[2];
 534         s32 nrssislope;
 535         /* In memory nrssi lookup table. */
 536         s8 nrssi_lt[64];
 537
 538         /* current channel */
 539         u8 channel;
 540
 541         u16 lofcal;
 542
 543         u16 initval;            //FIXME rename?
 544 };
 545
 546 /* Data structures for DMA transmission, per 80211 core. */
 547 struct b43_dma {
 548         struct b43_dmaring *tx_ring0;
 549         struct b43_dmaring *tx_ring1;
 550         struct b43_dmaring *tx_ring2;
 551         struct b43_dmaring *tx_ring3;
 552         struct b43_dmaring *tx_ring4;
 553         struct b43_dmaring *tx_ring5;
 554
 555         struct b43_dmaring *rx_ring0;
 556         struct b43_dmaring *rx_ring3;   /* only available on core.rev < 5 */
 557 };
 558
 559 /* Data structures for PIO transmission, per 80211 core. */
 560 struct b43_pio {
 561         struct b43_pioqueue *queue0;
 562         struct b43_pioqueue *queue1;
 563         struct b43_pioqueue *queue2;
 564         struct b43_pioqueue *queue3;
 565 };
 566
 567 /* Context information for a noise calculation (Link Quality). */
 568 struct b43_noise_calculation {
 569         u8 channel_at_start;
 570         bool calculation_running;
 571         u8 nr_samples;
 572         s8 samples[8][4];
 573 };
 574
 575 struct b43_stats {
 576         u8 link_noise;
 577         /* Store the last TX/RX times here for updating the leds. */
 578         unsigned long last_tx;
 579         unsigned long last_rx;
 580 };
 581
 582 struct b43_key {
 583         /* If keyconf is NULL, this key is disabled.
 584          * keyconf is a cookie. Don't derefenrence it outside of the set_key
 585          * path, because b43 doesn't own it. */
 586         struct ieee80211_key_conf *keyconf;
 587         u8 algorithm;
 588 };
 589
 590 struct b43_wldev;
 591
 592 /* Data structure for the WLAN parts (802.11 cores) of the b43 chip. */
 593 struct b43_wl {
 594         /* Pointer to the active wireless device on this chip */
 595         struct b43_wldev *current_dev;
 596         /* Pointer to the ieee80211 hardware data structure */
 597         struct ieee80211_hw *hw;
 598
 599         spinlock_t irq_lock;
 600         struct mutex mutex;
 601         spinlock_t leds_lock;
 602
 603         /* We can only have one operating interface (802.11 core)
 604          * at a time. General information about this interface follows.
 605          */
 606
 607         /* Opaque ID of the operating interface (!= monitor
 608          * interface) from the ieee80211 subsystem.
 609          * Do not modify.
 610          */
 611         int if_id;
 612         /* The MAC address of the operating interface. */
 613         u8 mac_addr[ETH_ALEN];
 614         /* Current BSSID */
 615         u8 bssid[ETH_ALEN];
 616         /* Interface type. (IEEE80211_IF_TYPE_XXX) */
 617         int if_type;
 618         /* Counter of active monitor interfaces. */
 619         int monitor;
 620         /* Is the card operating in AP, STA or IBSS mode? */
 621         bool operating;
 622         /* Promisc mode active?
 623          * Note that (monitor != 0) implies promisc.
 624          */
 625         bool promisc;
 626         /* Stats about the wireless interface */
 627         struct ieee80211_low_level_stats ieee_stats;
 628
 629         struct hwrng rng;
 630         u8 rng_initialized;
 631         char rng_name[30 + 1];
 632
 633         /* List of all wireless devices on this chip */
 634         struct list_head devlist;
 635         u8 nr_devs;
 636 };
 637
 638 /* Pointers to the firmware data and meta information about it. */
 639 struct b43_firmware {
 640         /* Microcode */
 641         const struct firmware *ucode;
 642         /* PCM code */
 643         const struct firmware *pcm;
 644         /* Initial MMIO values for the firmware */
 645         const struct firmware *initvals;
 646         /* Initial MMIO values for the firmware, band-specific */
 647         const struct firmware *initvals_band;
 648         /* Firmware revision */
 649         u16 rev;
 650         /* Firmware patchlevel */
 651         u16 patch;
 652 };
 653
 654 /* Device (802.11 core) initialization status. */
 655 enum {
 656         B43_STAT_UNINIT = 0,    /* Uninitialized. */
 657         B43_STAT_INITIALIZED = 1,       /* Initialized, but not started, yet. */
 658         B43_STAT_STARTED = 2,   /* Up and running. */
 659 };
 660 #define b43_status(wldev)               atomic_read(&(wldev)->__init_status)
 661 #define b43_set_status(wldev, stat)     do {                    \
 662                 atomic_set(&(wldev)->__init_status, (stat));    \
 663                 smp_wmb();                                      \
 664                                         } while (0)
 665
 666 /* XXX---   HOW LOCKING WORKS IN B43   ---XXX
 667  *
 668  * You should always acquire both, wl->mutex and wl->irq_lock unless:
 669  * - You don't need to acquire wl->irq_lock, if the interface is stopped.
 670  * - You don't need to acquire wl->mutex in the IRQ handler, IRQ tasklet
 671  *   and packet TX path (and _ONLY_ there.)
 672  */
 673
 674 /* Data structure for one wireless device (802.11 core) */
 675 struct b43_wldev {
 676         struct ssb_device *dev;
 677         struct b43_wl *wl;
 678
 679         /* The device initialization status.
 680          * Use b43_status() to query. */
 681         atomic_t __init_status;
 682         /* Saved init status for handling suspend. */
 683         int suspend_init_status;
 684
 685         bool __using_pio;       /* Internal, use b43_using_pio(). */
 686         bool bad_frames_preempt;        /* Use "Bad Frames Preemption" (default off) */
 687         bool reg124_set_0x4;    /* Some variable to keep track of IRQ stuff. */
 688         bool short_preamble;    /* TRUE, if short preamble is enabled. */
 689         bool short_slot;        /* TRUE, if short slot timing is enabled. */
 690         bool radio_hw_enable;   /* saved state of radio hardware enabled state */
 691
 692         /* PHY/Radio device. */
 693         struct b43_phy phy;
 694         union {
 695                 /* DMA engines. */
 696                 struct b43_dma dma;
 697                 /* PIO engines. */
 698                 struct b43_pio pio;
 699         };
 700
 701         /* Various statistics about the physical device. */
 702         struct b43_stats stats;
 703
 704 #define B43_NR_LEDS             4
 705         struct b43_led leds[B43_NR_LEDS];
 706
 707         /* Reason code of the last interrupt. */
 708         u32 irq_reason;
 709         u32 dma_reason[6];
 710         /* saved irq enable/disable state bitfield. */
 711         u32 irq_savedstate;
 712         /* Link Quality calculation context. */
 713         struct b43_noise_calculation noisecalc;
 714         /* if > 0 MAC is suspended. if == 0 MAC is enabled. */
 715         int mac_suspended;
 716
 717         /* Interrupt Service Routine tasklet (bottom-half) */
 718         struct tasklet_struct isr_tasklet;
 719
 720         /* Periodic tasks */
 721         struct delayed_work periodic_work;
 722         unsigned int periodic_state;
 723
 724         struct work_struct restart_work;
 725
 726         /* encryption/decryption */
 727         u16 ktp;                /* Key table pointer */
 728         u8 max_nr_keys;
 729         struct b43_key key[58];
 730
 731         /* Cached beacon template while uploading the template. */
 732         struct sk_buff *cached_beacon;
 733
 734         /* Firmware data */
 735         struct b43_firmware fw;
 736
 737         /* Devicelist in struct b43_wl (all 802.11 cores) */
 738         struct list_head list;
 739
 740         /* Debugging stuff follows. */
 741 #ifdef CONFIG_B43_DEBUG
 742         struct b43_dfsentry *dfsentry;
 743 #endif
 744 };
 745
 746 static inline struct b43_wl *hw_to_b43_wl(struct ieee80211_hw *hw)
 747 {
 748         return hw->priv;
 749 }
 750
 751 /* Helper function, which returns a boolean.
 752  * TRUE, if PIO is used; FALSE, if DMA is used.
 753  */
 754 #if defined(CONFIG_B43_DMA) && defined(CONFIG_B43_PIO)
 755 static inline int b43_using_pio(struct b43_wldev *dev)
 756 {
 757         return dev->__using_pio;
 758 }
 759 #elif defined(CONFIG_B43_DMA)
 760 static inline int b43_using_pio(struct b43_wldev *dev)
 761 {
 762         return 0;
 763 }
 764 #elif defined(CONFIG_B43_PIO)
 765 static inline int b43_using_pio(struct b43_wldev *dev)
 766 {
 767         return 1;
 768 }
 769 #else
 770 # error "Using neither DMA nor PIO? Confused..."
 771 #endif
 772
 773 static inline struct b43_wldev *dev_to_b43_wldev(struct device *dev)
 774 {
 775         struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
 776         return ssb_get_drvdata(ssb_dev);
 777 }
 778
 779 /* Is the device operating in a specified mode (IEEE80211_IF_TYPE_XXX). */
 780 static inline int b43_is_mode(struct b43_wl *wl, int type)
 781 {
 782         if (type == IEEE80211_IF_TYPE_MNTR)
 783                 return !!(wl->monitor);
 784         return (wl->operating && wl->if_type == type);
 785 }
 786
 787 static inline u16 b43_read16(struct b43_wldev *dev, u16 offset)
 788 {
 789         return ssb_read16(dev->dev, offset);
 790 }
 791
 792 static inline void b43_write16(struct b43_wldev *dev, u16 offset, u16 value)
 793 {
 794         ssb_write16(dev->dev, offset, value);
 795 }
 796
 797 static inline u32 b43_read32(struct b43_wldev *dev, u16 offset)
 798 {
 799         return ssb_read32(dev->dev, offset);
 800 }
 801
 802 static inline void b43_write32(struct b43_wldev *dev, u16 offset, u32 value)
 803 {
 804         ssb_write32(dev->dev, offset, value);
 805 }
 806
 807 /* Message printing */
 808 void b43info(struct b43_wl *wl, const char *fmt, ...)
 809     __attribute__ ((format(printf, 2, 3)));
 810 void b43err(struct b43_wl *wl, const char *fmt, ...)
 811     __attribute__ ((format(printf, 2, 3)));
 812 void b43warn(struct b43_wl *wl, const char *fmt, ...)
 813     __attribute__ ((format(printf, 2, 3)));
 814 #if B43_DEBUG
 815 void b43dbg(struct b43_wl *wl, const char *fmt, ...)
 816     __attribute__ ((format(printf, 2, 3)));
 817 #else /* DEBUG */
 818 # define b43dbg(wl, fmt...) do { /* nothing */ } while (0)
 819 #endif /* DEBUG */
 820
 821 /* A WARN_ON variant that vanishes when b43 debugging is disabled.
 822  * This _also_ evaluates the arg with debugging disabled. */
 823 #if B43_DEBUG
 824 # define B43_WARN_ON(x) WARN_ON(x)
 825 #else
 826 static inline bool __b43_warn_on_dummy(bool x) { return x; }
 827 # define B43_WARN_ON(x) __b43_warn_on_dummy(unlikely(!!(x)))
 828 #endif
 829
 830 /** Limit a value between two limits */
 831 #ifdef limit_value
 832 # undef limit_value
 833 #endif
 834 #define limit_value(value, min, max)  \
 835         ({                                              \
 836                 typeof(value) __value = (value);        \
 837                 typeof(value) __min = (min);            \
 838                 typeof(value) __max = (max);            \
 839                 if (__value < __min)                    \
 840                         __value = __min;                \
 841                 else if (__value > __max)               \
 842                         __value = __max;                \
 843                 __value;                                \
 844         })
 845
 846 /* Convert an integer to a Q5.2 value */
 847 #define INT_TO_Q52(i)   ((i) << 2)
 848 /* Convert a Q5.2 value to an integer (precision loss!) */
 849 #define Q52_TO_INT(q52) ((q52) >> 2)
 850 /* Macros for printing a value in Q5.2 format */
 851 #define Q52_FMT         "%u.%u"
 852 #define Q52_ARG(q52)    Q52_TO_INT(q52), ((((q52) & 0x3) * 100) / 4)
 853
 854 #endif /* B43_H_ */