3 Broadcom B43 wireless driver
5 DMA ringbuffer and descriptor allocation/management
7 Copyright (c) 2005, 2006 Michael Buesch <m@bues.ch>
9 Some code in this file is derived from the b44.c driver
10 Copyright (C) 2002 David S. Miller
11 Copyright (C) Pekka Pietikainen
13 This program is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 2 of the License, or
16 (at your option) any later version.
18 This program is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with this program; see the file COPYING. If not, write to
25 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
26 Boston, MA 02110-1301, USA.
36 #include <linux/dma-mapping.h>
37 #include <linux/pci.h>
38 #include <linux/delay.h>
39 #include <linux/skbuff.h>
40 #include <linux/etherdevice.h>
41 #include <linux/slab.h>
42 #include <asm/div64.h>
45 /* Required number of TX DMA slots per TX frame.
46 * This currently is 2, because we put the header and the ieee80211 frame
47 * into separate slots. */
48 #define TX_SLOTS_PER_FRAME 2
53 struct b43_dmadesc_generic
*op32_idx2desc(struct b43_dmaring
*ring
,
55 struct b43_dmadesc_meta
**meta
)
57 struct b43_dmadesc32
*desc
;
59 *meta
= &(ring
->meta
[slot
]);
60 desc
= ring
->descbase
;
63 return (struct b43_dmadesc_generic
*)desc
;
66 static void op32_fill_descriptor(struct b43_dmaring
*ring
,
67 struct b43_dmadesc_generic
*desc
,
68 dma_addr_t dmaaddr
, u16 bufsize
,
69 int start
, int end
, int irq
)
71 struct b43_dmadesc32
*descbase
= ring
->descbase
;
77 slot
= (int)(&(desc
->dma32
) - descbase
);
78 B43_WARN_ON(!(slot
>= 0 && slot
< ring
->nr_slots
));
80 addr
= (u32
) (dmaaddr
& ~SSB_DMA_TRANSLATION_MASK
);
81 addrext
= (u32
) (dmaaddr
& SSB_DMA_TRANSLATION_MASK
)
82 >> SSB_DMA_TRANSLATION_SHIFT
;
83 addr
|= ring
->dev
->dma
.translation
;
84 ctl
= bufsize
& B43_DMA32_DCTL_BYTECNT
;
85 if (slot
== ring
->nr_slots
- 1)
86 ctl
|= B43_DMA32_DCTL_DTABLEEND
;
88 ctl
|= B43_DMA32_DCTL_FRAMESTART
;
90 ctl
|= B43_DMA32_DCTL_FRAMEEND
;
92 ctl
|= B43_DMA32_DCTL_IRQ
;
93 ctl
|= (addrext
<< B43_DMA32_DCTL_ADDREXT_SHIFT
)
94 & B43_DMA32_DCTL_ADDREXT_MASK
;
96 desc
->dma32
.control
= cpu_to_le32(ctl
);
97 desc
->dma32
.address
= cpu_to_le32(addr
);
100 static void op32_poke_tx(struct b43_dmaring
*ring
, int slot
)
102 b43_dma_write(ring
, B43_DMA32_TXINDEX
,
103 (u32
) (slot
* sizeof(struct b43_dmadesc32
)));
106 static void op32_tx_suspend(struct b43_dmaring
*ring
)
108 b43_dma_write(ring
, B43_DMA32_TXCTL
, b43_dma_read(ring
, B43_DMA32_TXCTL
)
109 | B43_DMA32_TXSUSPEND
);
112 static void op32_tx_resume(struct b43_dmaring
*ring
)
114 b43_dma_write(ring
, B43_DMA32_TXCTL
, b43_dma_read(ring
, B43_DMA32_TXCTL
)
115 & ~B43_DMA32_TXSUSPEND
);
118 static int op32_get_current_rxslot(struct b43_dmaring
*ring
)
122 val
= b43_dma_read(ring
, B43_DMA32_RXSTATUS
);
123 val
&= B43_DMA32_RXDPTR
;
125 return (val
/ sizeof(struct b43_dmadesc32
));
128 static void op32_set_current_rxslot(struct b43_dmaring
*ring
, int slot
)
130 b43_dma_write(ring
, B43_DMA32_RXINDEX
,
131 (u32
) (slot
* sizeof(struct b43_dmadesc32
)));
134 static const struct b43_dma_ops dma32_ops
= {
135 .idx2desc
= op32_idx2desc
,
136 .fill_descriptor
= op32_fill_descriptor
,
137 .poke_tx
= op32_poke_tx
,
138 .tx_suspend
= op32_tx_suspend
,
139 .tx_resume
= op32_tx_resume
,
140 .get_current_rxslot
= op32_get_current_rxslot
,
141 .set_current_rxslot
= op32_set_current_rxslot
,
146 struct b43_dmadesc_generic
*op64_idx2desc(struct b43_dmaring
*ring
,
148 struct b43_dmadesc_meta
**meta
)
150 struct b43_dmadesc64
*desc
;
152 *meta
= &(ring
->meta
[slot
]);
153 desc
= ring
->descbase
;
154 desc
= &(desc
[slot
]);
156 return (struct b43_dmadesc_generic
*)desc
;
159 static void op64_fill_descriptor(struct b43_dmaring
*ring
,
160 struct b43_dmadesc_generic
*desc
,
161 dma_addr_t dmaaddr
, u16 bufsize
,
162 int start
, int end
, int irq
)
164 struct b43_dmadesc64
*descbase
= ring
->descbase
;
166 u32 ctl0
= 0, ctl1
= 0;
170 slot
= (int)(&(desc
->dma64
) - descbase
);
171 B43_WARN_ON(!(slot
>= 0 && slot
< ring
->nr_slots
));
173 addrlo
= (u32
) (dmaaddr
& 0xFFFFFFFF);
174 addrhi
= (((u64
) dmaaddr
>> 32) & ~SSB_DMA_TRANSLATION_MASK
);
175 addrext
= (((u64
) dmaaddr
>> 32) & SSB_DMA_TRANSLATION_MASK
)
176 >> SSB_DMA_TRANSLATION_SHIFT
;
177 addrhi
|= ring
->dev
->dma
.translation
;
178 if (slot
== ring
->nr_slots
- 1)
179 ctl0
|= B43_DMA64_DCTL0_DTABLEEND
;
181 ctl0
|= B43_DMA64_DCTL0_FRAMESTART
;
183 ctl0
|= B43_DMA64_DCTL0_FRAMEEND
;
185 ctl0
|= B43_DMA64_DCTL0_IRQ
;
186 ctl1
|= bufsize
& B43_DMA64_DCTL1_BYTECNT
;
187 ctl1
|= (addrext
<< B43_DMA64_DCTL1_ADDREXT_SHIFT
)
188 & B43_DMA64_DCTL1_ADDREXT_MASK
;
190 desc
->dma64
.control0
= cpu_to_le32(ctl0
);
191 desc
->dma64
.control1
= cpu_to_le32(ctl1
);
192 desc
->dma64
.address_low
= cpu_to_le32(addrlo
);
193 desc
->dma64
.address_high
= cpu_to_le32(addrhi
);
196 static void op64_poke_tx(struct b43_dmaring
*ring
, int slot
)
198 b43_dma_write(ring
, B43_DMA64_TXINDEX
,
199 (u32
) (slot
* sizeof(struct b43_dmadesc64
)));
202 static void op64_tx_suspend(struct b43_dmaring
*ring
)
204 b43_dma_write(ring
, B43_DMA64_TXCTL
, b43_dma_read(ring
, B43_DMA64_TXCTL
)
205 | B43_DMA64_TXSUSPEND
);
208 static void op64_tx_resume(struct b43_dmaring
*ring
)
210 b43_dma_write(ring
, B43_DMA64_TXCTL
, b43_dma_read(ring
, B43_DMA64_TXCTL
)
211 & ~B43_DMA64_TXSUSPEND
);
214 static int op64_get_current_rxslot(struct b43_dmaring
*ring
)
218 val
= b43_dma_read(ring
, B43_DMA64_RXSTATUS
);
219 val
&= B43_DMA64_RXSTATDPTR
;
221 return (val
/ sizeof(struct b43_dmadesc64
));
224 static void op64_set_current_rxslot(struct b43_dmaring
*ring
, int slot
)
226 b43_dma_write(ring
, B43_DMA64_RXINDEX
,
227 (u32
) (slot
* sizeof(struct b43_dmadesc64
)));
230 static const struct b43_dma_ops dma64_ops
= {
231 .idx2desc
= op64_idx2desc
,
232 .fill_descriptor
= op64_fill_descriptor
,
233 .poke_tx
= op64_poke_tx
,
234 .tx_suspend
= op64_tx_suspend
,
235 .tx_resume
= op64_tx_resume
,
236 .get_current_rxslot
= op64_get_current_rxslot
,
237 .set_current_rxslot
= op64_set_current_rxslot
,
240 static inline int free_slots(struct b43_dmaring
*ring
)
242 return (ring
->nr_slots
- ring
->used_slots
);
245 static inline int next_slot(struct b43_dmaring
*ring
, int slot
)
247 B43_WARN_ON(!(slot
>= -1 && slot
<= ring
->nr_slots
- 1));
248 if (slot
== ring
->nr_slots
- 1)
253 static inline int prev_slot(struct b43_dmaring
*ring
, int slot
)
255 B43_WARN_ON(!(slot
>= 0 && slot
<= ring
->nr_slots
- 1));
257 return ring
->nr_slots
- 1;
261 #ifdef CONFIG_B43_DEBUG
262 static void update_max_used_slots(struct b43_dmaring
*ring
,
263 int current_used_slots
)
265 if (current_used_slots
<= ring
->max_used_slots
)
267 ring
->max_used_slots
= current_used_slots
;
268 if (b43_debug(ring
->dev
, B43_DBG_DMAVERBOSE
)) {
269 b43dbg(ring
->dev
->wl
,
270 "max_used_slots increased to %d on %s ring %d\n",
271 ring
->max_used_slots
,
272 ring
->tx
? "TX" : "RX", ring
->index
);
277 void update_max_used_slots(struct b43_dmaring
*ring
, int current_used_slots
)
282 /* Request a slot for usage. */
283 static inline int request_slot(struct b43_dmaring
*ring
)
287 B43_WARN_ON(!ring
->tx
);
288 B43_WARN_ON(ring
->stopped
);
289 B43_WARN_ON(free_slots(ring
) == 0);
291 slot
= next_slot(ring
, ring
->current_slot
);
292 ring
->current_slot
= slot
;
295 update_max_used_slots(ring
, ring
->used_slots
);
300 static u16
b43_dmacontroller_base(enum b43_dmatype type
, int controller_idx
)
302 static const u16 map64
[] = {
303 B43_MMIO_DMA64_BASE0
,
304 B43_MMIO_DMA64_BASE1
,
305 B43_MMIO_DMA64_BASE2
,
306 B43_MMIO_DMA64_BASE3
,
307 B43_MMIO_DMA64_BASE4
,
308 B43_MMIO_DMA64_BASE5
,
310 static const u16 map32
[] = {
311 B43_MMIO_DMA32_BASE0
,
312 B43_MMIO_DMA32_BASE1
,
313 B43_MMIO_DMA32_BASE2
,
314 B43_MMIO_DMA32_BASE3
,
315 B43_MMIO_DMA32_BASE4
,
316 B43_MMIO_DMA32_BASE5
,
319 if (type
== B43_DMA_64BIT
) {
320 B43_WARN_ON(!(controller_idx
>= 0 &&
321 controller_idx
< ARRAY_SIZE(map64
)));
322 return map64
[controller_idx
];
324 B43_WARN_ON(!(controller_idx
>= 0 &&
325 controller_idx
< ARRAY_SIZE(map32
)));
326 return map32
[controller_idx
];
330 dma_addr_t
map_descbuffer(struct b43_dmaring
*ring
,
331 unsigned char *buf
, size_t len
, int tx
)
336 dmaaddr
= dma_map_single(ring
->dev
->dev
->dma_dev
,
337 buf
, len
, DMA_TO_DEVICE
);
339 dmaaddr
= dma_map_single(ring
->dev
->dev
->dma_dev
,
340 buf
, len
, DMA_FROM_DEVICE
);
347 void unmap_descbuffer(struct b43_dmaring
*ring
,
348 dma_addr_t addr
, size_t len
, int tx
)
351 dma_unmap_single(ring
->dev
->dev
->dma_dev
,
352 addr
, len
, DMA_TO_DEVICE
);
354 dma_unmap_single(ring
->dev
->dev
->dma_dev
,
355 addr
, len
, DMA_FROM_DEVICE
);
360 void sync_descbuffer_for_cpu(struct b43_dmaring
*ring
,
361 dma_addr_t addr
, size_t len
)
363 B43_WARN_ON(ring
->tx
);
364 dma_sync_single_for_cpu(ring
->dev
->dev
->dma_dev
,
365 addr
, len
, DMA_FROM_DEVICE
);
369 void sync_descbuffer_for_device(struct b43_dmaring
*ring
,
370 dma_addr_t addr
, size_t len
)
372 B43_WARN_ON(ring
->tx
);
373 dma_sync_single_for_device(ring
->dev
->dev
->dma_dev
,
374 addr
, len
, DMA_FROM_DEVICE
);
378 void free_descriptor_buffer(struct b43_dmaring
*ring
,
379 struct b43_dmadesc_meta
*meta
)
382 dev_kfree_skb_any(meta
->skb
);
387 static int alloc_ringmemory(struct b43_dmaring
*ring
)
389 gfp_t flags
= GFP_KERNEL
;
391 /* The specs call for 4K buffers for 30- and 32-bit DMA with 4K
392 * alignment and 8K buffers for 64-bit DMA with 8K alignment. Testing
393 * has shown that 4K is sufficient for the latter as long as the buffer
394 * does not cross an 8K boundary.
396 * For unknown reasons - possibly a hardware error - the BCM4311 rev
397 * 02, which uses 64-bit DMA, needs the ring buffer in very low memory,
398 * which accounts for the GFP_DMA flag below.
400 * The flags here must match the flags in free_ringmemory below!
402 if (ring
->type
== B43_DMA_64BIT
)
404 ring
->descbase
= dma_alloc_coherent(ring
->dev
->dev
->dma_dev
,
406 &(ring
->dmabase
), flags
);
407 if (!ring
->descbase
) {
408 b43err(ring
->dev
->wl
, "DMA ringmemory allocation failed\n");
411 memset(ring
->descbase
, 0, B43_DMA_RINGMEMSIZE
);
416 static void free_ringmemory(struct b43_dmaring
*ring
)
418 dma_free_coherent(ring
->dev
->dev
->dma_dev
, B43_DMA_RINGMEMSIZE
,
419 ring
->descbase
, ring
->dmabase
);
422 /* Reset the RX DMA channel */
423 static int b43_dmacontroller_rx_reset(struct b43_wldev
*dev
, u16 mmio_base
,
424 enum b43_dmatype type
)
432 offset
= (type
== B43_DMA_64BIT
) ? B43_DMA64_RXCTL
: B43_DMA32_RXCTL
;
433 b43_write32(dev
, mmio_base
+ offset
, 0);
434 for (i
= 0; i
< 10; i
++) {
435 offset
= (type
== B43_DMA_64BIT
) ? B43_DMA64_RXSTATUS
:
437 value
= b43_read32(dev
, mmio_base
+ offset
);
438 if (type
== B43_DMA_64BIT
) {
439 value
&= B43_DMA64_RXSTAT
;
440 if (value
== B43_DMA64_RXSTAT_DISABLED
) {
445 value
&= B43_DMA32_RXSTATE
;
446 if (value
== B43_DMA32_RXSTAT_DISABLED
) {
454 b43err(dev
->wl
, "DMA RX reset timed out\n");
461 /* Reset the TX DMA channel */
462 static int b43_dmacontroller_tx_reset(struct b43_wldev
*dev
, u16 mmio_base
,
463 enum b43_dmatype type
)
471 for (i
= 0; i
< 10; i
++) {
472 offset
= (type
== B43_DMA_64BIT
) ? B43_DMA64_TXSTATUS
:
474 value
= b43_read32(dev
, mmio_base
+ offset
);
475 if (type
== B43_DMA_64BIT
) {
476 value
&= B43_DMA64_TXSTAT
;
477 if (value
== B43_DMA64_TXSTAT_DISABLED
||
478 value
== B43_DMA64_TXSTAT_IDLEWAIT
||
479 value
== B43_DMA64_TXSTAT_STOPPED
)
482 value
&= B43_DMA32_TXSTATE
;
483 if (value
== B43_DMA32_TXSTAT_DISABLED
||
484 value
== B43_DMA32_TXSTAT_IDLEWAIT
||
485 value
== B43_DMA32_TXSTAT_STOPPED
)
490 offset
= (type
== B43_DMA_64BIT
) ? B43_DMA64_TXCTL
: B43_DMA32_TXCTL
;
491 b43_write32(dev
, mmio_base
+ offset
, 0);
492 for (i
= 0; i
< 10; i
++) {
493 offset
= (type
== B43_DMA_64BIT
) ? B43_DMA64_TXSTATUS
:
495 value
= b43_read32(dev
, mmio_base
+ offset
);
496 if (type
== B43_DMA_64BIT
) {
497 value
&= B43_DMA64_TXSTAT
;
498 if (value
== B43_DMA64_TXSTAT_DISABLED
) {
503 value
&= B43_DMA32_TXSTATE
;
504 if (value
== B43_DMA32_TXSTAT_DISABLED
) {
512 b43err(dev
->wl
, "DMA TX reset timed out\n");
515 /* ensure the reset is completed. */
521 /* Check if a DMA mapping address is invalid. */
522 static bool b43_dma_mapping_error(struct b43_dmaring
*ring
,
524 size_t buffersize
, bool dma_to_device
)
526 if (unlikely(dma_mapping_error(ring
->dev
->dev
->dma_dev
, addr
)))
529 switch (ring
->type
) {
531 if ((u64
)addr
+ buffersize
> (1ULL << 30))
535 if ((u64
)addr
+ buffersize
> (1ULL << 32))
539 /* Currently we can't have addresses beyond
540 * 64bit in the kernel. */
544 /* The address is OK. */
548 /* We can't support this address. Unmap it again. */
549 unmap_descbuffer(ring
, addr
, buffersize
, dma_to_device
);
554 static bool b43_rx_buffer_is_poisoned(struct b43_dmaring
*ring
, struct sk_buff
*skb
)
556 unsigned char *f
= skb
->data
+ ring
->frameoffset
;
558 return ((f
[0] & f
[1] & f
[2] & f
[3] & f
[4] & f
[5] & f
[6] & f
[7]) == 0xFF);
561 static void b43_poison_rx_buffer(struct b43_dmaring
*ring
, struct sk_buff
*skb
)
563 struct b43_rxhdr_fw4
*rxhdr
;
564 unsigned char *frame
;
566 /* This poisons the RX buffer to detect DMA failures. */
568 rxhdr
= (struct b43_rxhdr_fw4
*)(skb
->data
);
569 rxhdr
->frame_len
= 0;
571 B43_WARN_ON(ring
->rx_buffersize
< ring
->frameoffset
+ sizeof(struct b43_plcp_hdr6
) + 2);
572 frame
= skb
->data
+ ring
->frameoffset
;
573 memset(frame
, 0xFF, sizeof(struct b43_plcp_hdr6
) + 2 /* padding */);
576 static int setup_rx_descbuffer(struct b43_dmaring
*ring
,
577 struct b43_dmadesc_generic
*desc
,
578 struct b43_dmadesc_meta
*meta
, gfp_t gfp_flags
)
583 B43_WARN_ON(ring
->tx
);
585 skb
= __dev_alloc_skb(ring
->rx_buffersize
, gfp_flags
);
588 b43_poison_rx_buffer(ring
, skb
);
589 dmaaddr
= map_descbuffer(ring
, skb
->data
, ring
->rx_buffersize
, 0);
590 if (b43_dma_mapping_error(ring
, dmaaddr
, ring
->rx_buffersize
, 0)) {
591 /* ugh. try to realloc in zone_dma */
592 gfp_flags
|= GFP_DMA
;
594 dev_kfree_skb_any(skb
);
596 skb
= __dev_alloc_skb(ring
->rx_buffersize
, gfp_flags
);
599 b43_poison_rx_buffer(ring
, skb
);
600 dmaaddr
= map_descbuffer(ring
, skb
->data
,
601 ring
->rx_buffersize
, 0);
602 if (b43_dma_mapping_error(ring
, dmaaddr
, ring
->rx_buffersize
, 0)) {
603 b43err(ring
->dev
->wl
, "RX DMA buffer allocation failed\n");
604 dev_kfree_skb_any(skb
);
610 meta
->dmaaddr
= dmaaddr
;
611 ring
->ops
->fill_descriptor(ring
, desc
, dmaaddr
,
612 ring
->rx_buffersize
, 0, 0, 0);
617 /* Allocate the initial descbuffers.
618 * This is used for an RX ring only.
620 static int alloc_initial_descbuffers(struct b43_dmaring
*ring
)
622 int i
, err
= -ENOMEM
;
623 struct b43_dmadesc_generic
*desc
;
624 struct b43_dmadesc_meta
*meta
;
626 for (i
= 0; i
< ring
->nr_slots
; i
++) {
627 desc
= ring
->ops
->idx2desc(ring
, i
, &meta
);
629 err
= setup_rx_descbuffer(ring
, desc
, meta
, GFP_KERNEL
);
631 b43err(ring
->dev
->wl
,
632 "Failed to allocate initial descbuffers\n");
637 ring
->used_slots
= ring
->nr_slots
;
643 for (i
--; i
>= 0; i
--) {
644 desc
= ring
->ops
->idx2desc(ring
, i
, &meta
);
646 unmap_descbuffer(ring
, meta
->dmaaddr
, ring
->rx_buffersize
, 0);
647 dev_kfree_skb(meta
->skb
);
652 /* Do initial setup of the DMA controller.
653 * Reset the controller, write the ring busaddress
654 * and switch the "enable" bit on.
656 static int dmacontroller_setup(struct b43_dmaring
*ring
)
661 u32 trans
= ring
->dev
->dma
.translation
;
662 bool parity
= ring
->dev
->dma
.parity
;
665 if (ring
->type
== B43_DMA_64BIT
) {
666 u64 ringbase
= (u64
) (ring
->dmabase
);
668 addrext
= ((ringbase
>> 32) & SSB_DMA_TRANSLATION_MASK
)
669 >> SSB_DMA_TRANSLATION_SHIFT
;
670 value
= B43_DMA64_TXENABLE
;
671 value
|= (addrext
<< B43_DMA64_TXADDREXT_SHIFT
)
672 & B43_DMA64_TXADDREXT_MASK
;
674 value
|= B43_DMA64_TXPARITYDISABLE
;
675 b43_dma_write(ring
, B43_DMA64_TXCTL
, value
);
676 b43_dma_write(ring
, B43_DMA64_TXRINGLO
,
677 (ringbase
& 0xFFFFFFFF));
678 b43_dma_write(ring
, B43_DMA64_TXRINGHI
,
680 ~SSB_DMA_TRANSLATION_MASK
)
683 u32 ringbase
= (u32
) (ring
->dmabase
);
685 addrext
= (ringbase
& SSB_DMA_TRANSLATION_MASK
)
686 >> SSB_DMA_TRANSLATION_SHIFT
;
687 value
= B43_DMA32_TXENABLE
;
688 value
|= (addrext
<< B43_DMA32_TXADDREXT_SHIFT
)
689 & B43_DMA32_TXADDREXT_MASK
;
691 value
|= B43_DMA32_TXPARITYDISABLE
;
692 b43_dma_write(ring
, B43_DMA32_TXCTL
, value
);
693 b43_dma_write(ring
, B43_DMA32_TXRING
,
694 (ringbase
& ~SSB_DMA_TRANSLATION_MASK
)
698 err
= alloc_initial_descbuffers(ring
);
701 if (ring
->type
== B43_DMA_64BIT
) {
702 u64 ringbase
= (u64
) (ring
->dmabase
);
704 addrext
= ((ringbase
>> 32) & SSB_DMA_TRANSLATION_MASK
)
705 >> SSB_DMA_TRANSLATION_SHIFT
;
706 value
= (ring
->frameoffset
<< B43_DMA64_RXFROFF_SHIFT
);
707 value
|= B43_DMA64_RXENABLE
;
708 value
|= (addrext
<< B43_DMA64_RXADDREXT_SHIFT
)
709 & B43_DMA64_RXADDREXT_MASK
;
711 value
|= B43_DMA64_RXPARITYDISABLE
;
712 b43_dma_write(ring
, B43_DMA64_RXCTL
, value
);
713 b43_dma_write(ring
, B43_DMA64_RXRINGLO
,
714 (ringbase
& 0xFFFFFFFF));
715 b43_dma_write(ring
, B43_DMA64_RXRINGHI
,
717 ~SSB_DMA_TRANSLATION_MASK
)
719 b43_dma_write(ring
, B43_DMA64_RXINDEX
, ring
->nr_slots
*
720 sizeof(struct b43_dmadesc64
));
722 u32 ringbase
= (u32
) (ring
->dmabase
);
724 addrext
= (ringbase
& SSB_DMA_TRANSLATION_MASK
)
725 >> SSB_DMA_TRANSLATION_SHIFT
;
726 value
= (ring
->frameoffset
<< B43_DMA32_RXFROFF_SHIFT
);
727 value
|= B43_DMA32_RXENABLE
;
728 value
|= (addrext
<< B43_DMA32_RXADDREXT_SHIFT
)
729 & B43_DMA32_RXADDREXT_MASK
;
731 value
|= B43_DMA32_RXPARITYDISABLE
;
732 b43_dma_write(ring
, B43_DMA32_RXCTL
, value
);
733 b43_dma_write(ring
, B43_DMA32_RXRING
,
734 (ringbase
& ~SSB_DMA_TRANSLATION_MASK
)
736 b43_dma_write(ring
, B43_DMA32_RXINDEX
, ring
->nr_slots
*
737 sizeof(struct b43_dmadesc32
));
745 /* Shutdown the DMA controller. */
746 static void dmacontroller_cleanup(struct b43_dmaring
*ring
)
749 b43_dmacontroller_tx_reset(ring
->dev
, ring
->mmio_base
,
751 if (ring
->type
== B43_DMA_64BIT
) {
752 b43_dma_write(ring
, B43_DMA64_TXRINGLO
, 0);
753 b43_dma_write(ring
, B43_DMA64_TXRINGHI
, 0);
755 b43_dma_write(ring
, B43_DMA32_TXRING
, 0);
757 b43_dmacontroller_rx_reset(ring
->dev
, ring
->mmio_base
,
759 if (ring
->type
== B43_DMA_64BIT
) {
760 b43_dma_write(ring
, B43_DMA64_RXRINGLO
, 0);
761 b43_dma_write(ring
, B43_DMA64_RXRINGHI
, 0);
763 b43_dma_write(ring
, B43_DMA32_RXRING
, 0);
767 static void free_all_descbuffers(struct b43_dmaring
*ring
)
769 struct b43_dmadesc_meta
*meta
;
772 if (!ring
->used_slots
)
774 for (i
= 0; i
< ring
->nr_slots
; i
++) {
775 /* get meta - ignore returned value */
776 ring
->ops
->idx2desc(ring
, i
, &meta
);
778 if (!meta
->skb
|| b43_dma_ptr_is_poisoned(meta
->skb
)) {
779 B43_WARN_ON(!ring
->tx
);
783 unmap_descbuffer(ring
, meta
->dmaaddr
,
786 unmap_descbuffer(ring
, meta
->dmaaddr
,
787 ring
->rx_buffersize
, 0);
789 free_descriptor_buffer(ring
, meta
);
793 static u64
supported_dma_mask(struct b43_wldev
*dev
)
798 tmp
= b43_read32(dev
, SSB_TMSHIGH
);
799 if (tmp
& SSB_TMSHIGH_DMA64
)
800 return DMA_BIT_MASK(64);
801 mmio_base
= b43_dmacontroller_base(0, 0);
802 b43_write32(dev
, mmio_base
+ B43_DMA32_TXCTL
, B43_DMA32_TXADDREXT_MASK
);
803 tmp
= b43_read32(dev
, mmio_base
+ B43_DMA32_TXCTL
);
804 if (tmp
& B43_DMA32_TXADDREXT_MASK
)
805 return DMA_BIT_MASK(32);
807 return DMA_BIT_MASK(30);
810 static enum b43_dmatype
dma_mask_to_engine_type(u64 dmamask
)
812 if (dmamask
== DMA_BIT_MASK(30))
813 return B43_DMA_30BIT
;
814 if (dmamask
== DMA_BIT_MASK(32))
815 return B43_DMA_32BIT
;
816 if (dmamask
== DMA_BIT_MASK(64))
817 return B43_DMA_64BIT
;
819 return B43_DMA_30BIT
;
822 /* Main initialization function. */
824 struct b43_dmaring
*b43_setup_dmaring(struct b43_wldev
*dev
,
825 int controller_index
,
827 enum b43_dmatype type
)
829 struct b43_dmaring
*ring
;
833 ring
= kzalloc(sizeof(*ring
), GFP_KERNEL
);
837 ring
->nr_slots
= B43_RXRING_SLOTS
;
839 ring
->nr_slots
= B43_TXRING_SLOTS
;
841 ring
->meta
= kcalloc(ring
->nr_slots
, sizeof(struct b43_dmadesc_meta
),
845 for (i
= 0; i
< ring
->nr_slots
; i
++)
846 ring
->meta
->skb
= B43_DMA_PTR_POISON
;
850 ring
->mmio_base
= b43_dmacontroller_base(type
, controller_index
);
851 ring
->index
= controller_index
;
852 if (type
== B43_DMA_64BIT
)
853 ring
->ops
= &dma64_ops
;
855 ring
->ops
= &dma32_ops
;
858 ring
->current_slot
= -1;
860 if (ring
->index
== 0) {
861 ring
->rx_buffersize
= B43_DMA0_RX_BUFFERSIZE
;
862 ring
->frameoffset
= B43_DMA0_RX_FRAMEOFFSET
;
866 #ifdef CONFIG_B43_DEBUG
867 ring
->last_injected_overflow
= jiffies
;
871 /* Assumption: B43_TXRING_SLOTS can be divided by TX_SLOTS_PER_FRAME */
872 BUILD_BUG_ON(B43_TXRING_SLOTS
% TX_SLOTS_PER_FRAME
!= 0);
874 ring
->txhdr_cache
= kcalloc(ring
->nr_slots
/ TX_SLOTS_PER_FRAME
,
877 if (!ring
->txhdr_cache
)
880 /* test for ability to dma to txhdr_cache */
881 dma_test
= dma_map_single(dev
->dev
->dma_dev
,
886 if (b43_dma_mapping_error(ring
, dma_test
,
887 b43_txhdr_size(dev
), 1)) {
889 kfree(ring
->txhdr_cache
);
890 ring
->txhdr_cache
= kcalloc(ring
->nr_slots
/ TX_SLOTS_PER_FRAME
,
892 GFP_KERNEL
| GFP_DMA
);
893 if (!ring
->txhdr_cache
)
896 dma_test
= dma_map_single(dev
->dev
->dma_dev
,
901 if (b43_dma_mapping_error(ring
, dma_test
,
902 b43_txhdr_size(dev
), 1)) {
905 "TXHDR DMA allocation failed\n");
906 goto err_kfree_txhdr_cache
;
910 dma_unmap_single(dev
->dev
->dma_dev
,
911 dma_test
, b43_txhdr_size(dev
),
915 err
= alloc_ringmemory(ring
);
917 goto err_kfree_txhdr_cache
;
918 err
= dmacontroller_setup(ring
);
920 goto err_free_ringmemory
;
926 free_ringmemory(ring
);
927 err_kfree_txhdr_cache
:
928 kfree(ring
->txhdr_cache
);
937 #define divide(a, b) ({ \
943 #define modulo(a, b) ({ \
948 /* Main cleanup function. */
949 static void b43_destroy_dmaring(struct b43_dmaring
*ring
,
950 const char *ringname
)
955 #ifdef CONFIG_B43_DEBUG
957 /* Print some statistics. */
958 u64 failed_packets
= ring
->nr_failed_tx_packets
;
959 u64 succeed_packets
= ring
->nr_succeed_tx_packets
;
960 u64 nr_packets
= failed_packets
+ succeed_packets
;
961 u64 permille_failed
= 0, average_tries
= 0;
964 permille_failed
= divide(failed_packets
* 1000, nr_packets
);
966 average_tries
= divide(ring
->nr_total_packet_tries
* 100, nr_packets
);
968 b43dbg(ring
->dev
->wl
, "DMA-%u %s: "
969 "Used slots %d/%d, Failed frames %llu/%llu = %llu.%01llu%%, "
970 "Average tries %llu.%02llu\n",
971 (unsigned int)(ring
->type
), ringname
,
972 ring
->max_used_slots
,
974 (unsigned long long)failed_packets
,
975 (unsigned long long)nr_packets
,
976 (unsigned long long)divide(permille_failed
, 10),
977 (unsigned long long)modulo(permille_failed
, 10),
978 (unsigned long long)divide(average_tries
, 100),
979 (unsigned long long)modulo(average_tries
, 100));
983 /* Device IRQs are disabled prior entering this function,
984 * so no need to take care of concurrency with rx handler stuff.
986 dmacontroller_cleanup(ring
);
987 free_all_descbuffers(ring
);
988 free_ringmemory(ring
);
990 kfree(ring
->txhdr_cache
);
995 #define destroy_ring(dma, ring) do { \
996 b43_destroy_dmaring((dma)->ring, __stringify(ring)); \
997 (dma)->ring = NULL; \
1000 void b43_dma_free(struct b43_wldev
*dev
)
1002 struct b43_dma
*dma
;
1004 if (b43_using_pio_transfers(dev
))
1008 destroy_ring(dma
, rx_ring
);
1009 destroy_ring(dma
, tx_ring_AC_BK
);
1010 destroy_ring(dma
, tx_ring_AC_BE
);
1011 destroy_ring(dma
, tx_ring_AC_VI
);
1012 destroy_ring(dma
, tx_ring_AC_VO
);
1013 destroy_ring(dma
, tx_ring_mcast
);
1016 static int b43_dma_set_mask(struct b43_wldev
*dev
, u64 mask
)
1018 u64 orig_mask
= mask
;
1022 /* Try to set the DMA mask. If it fails, try falling back to a
1023 * lower mask, as we can always also support a lower one. */
1025 err
= dma_set_mask(dev
->dev
->dma_dev
, mask
);
1027 err
= dma_set_coherent_mask(dev
->dev
->dma_dev
, mask
);
1031 if (mask
== DMA_BIT_MASK(64)) {
1032 mask
= DMA_BIT_MASK(32);
1036 if (mask
== DMA_BIT_MASK(32)) {
1037 mask
= DMA_BIT_MASK(30);
1041 b43err(dev
->wl
, "The machine/kernel does not support "
1042 "the required %u-bit DMA mask\n",
1043 (unsigned int)dma_mask_to_engine_type(orig_mask
));
1047 b43info(dev
->wl
, "DMA mask fallback from %u-bit to %u-bit\n",
1048 (unsigned int)dma_mask_to_engine_type(orig_mask
),
1049 (unsigned int)dma_mask_to_engine_type(mask
));
1055 int b43_dma_init(struct b43_wldev
*dev
)
1057 struct b43_dma
*dma
= &dev
->dma
;
1060 enum b43_dmatype type
;
1062 dmamask
= supported_dma_mask(dev
);
1063 type
= dma_mask_to_engine_type(dmamask
);
1064 err
= b43_dma_set_mask(dev
, dmamask
);
1068 switch (dev
->dev
->bus_type
) {
1069 #ifdef CONFIG_B43_BCMA
1071 dma
->translation
= bcma_core_dma_translation(dev
->dev
->bdev
);
1074 #ifdef CONFIG_B43_SSB
1076 dma
->translation
= ssb_dma_translation(dev
->dev
->sdev
);
1082 #ifdef CONFIG_B43_BCMA
1083 /* TODO: find out which SSB devices need disabling parity */
1084 if (dev
->dev
->bus_type
== B43_BUS_BCMA
)
1085 dma
->parity
= false;
1089 /* setup TX DMA channels. */
1090 dma
->tx_ring_AC_BK
= b43_setup_dmaring(dev
, 0, 1, type
);
1091 if (!dma
->tx_ring_AC_BK
)
1094 dma
->tx_ring_AC_BE
= b43_setup_dmaring(dev
, 1, 1, type
);
1095 if (!dma
->tx_ring_AC_BE
)
1096 goto err_destroy_bk
;
1098 dma
->tx_ring_AC_VI
= b43_setup_dmaring(dev
, 2, 1, type
);
1099 if (!dma
->tx_ring_AC_VI
)
1100 goto err_destroy_be
;
1102 dma
->tx_ring_AC_VO
= b43_setup_dmaring(dev
, 3, 1, type
);
1103 if (!dma
->tx_ring_AC_VO
)
1104 goto err_destroy_vi
;
1106 dma
->tx_ring_mcast
= b43_setup_dmaring(dev
, 4, 1, type
);
1107 if (!dma
->tx_ring_mcast
)
1108 goto err_destroy_vo
;
1110 /* setup RX DMA channel. */
1111 dma
->rx_ring
= b43_setup_dmaring(dev
, 0, 0, type
);
1113 goto err_destroy_mcast
;
1115 /* No support for the TX status DMA ring. */
1116 B43_WARN_ON(dev
->dev
->core_rev
< 5);
1118 b43dbg(dev
->wl
, "%u-bit DMA initialized\n",
1119 (unsigned int)type
);
1125 destroy_ring(dma
, tx_ring_mcast
);
1127 destroy_ring(dma
, tx_ring_AC_VO
);
1129 destroy_ring(dma
, tx_ring_AC_VI
);
1131 destroy_ring(dma
, tx_ring_AC_BE
);
1133 destroy_ring(dma
, tx_ring_AC_BK
);
1137 /* Generate a cookie for the TX header. */
1138 static u16
generate_cookie(struct b43_dmaring
*ring
, int slot
)
1142 /* Use the upper 4 bits of the cookie as
1143 * DMA controller ID and store the slot number
1144 * in the lower 12 bits.
1145 * Note that the cookie must never be 0, as this
1146 * is a special value used in RX path.
1147 * It can also not be 0xFFFF because that is special
1148 * for multicast frames.
1150 cookie
= (((u16
)ring
->index
+ 1) << 12);
1151 B43_WARN_ON(slot
& ~0x0FFF);
1152 cookie
|= (u16
)slot
;
1157 /* Inspect a cookie and find out to which controller/slot it belongs. */
1159 struct b43_dmaring
*parse_cookie(struct b43_wldev
*dev
, u16 cookie
, int *slot
)
1161 struct b43_dma
*dma
= &dev
->dma
;
1162 struct b43_dmaring
*ring
= NULL
;
1164 switch (cookie
& 0xF000) {
1166 ring
= dma
->tx_ring_AC_BK
;
1169 ring
= dma
->tx_ring_AC_BE
;
1172 ring
= dma
->tx_ring_AC_VI
;
1175 ring
= dma
->tx_ring_AC_VO
;
1178 ring
= dma
->tx_ring_mcast
;
1181 *slot
= (cookie
& 0x0FFF);
1182 if (unlikely(!ring
|| *slot
< 0 || *slot
>= ring
->nr_slots
)) {
1183 b43dbg(dev
->wl
, "TX-status contains "
1184 "invalid cookie: 0x%04X\n", cookie
);
1191 static int dma_tx_fragment(struct b43_dmaring
*ring
,
1192 struct sk_buff
*skb
)
1194 const struct b43_dma_ops
*ops
= ring
->ops
;
1195 struct ieee80211_tx_info
*info
= IEEE80211_SKB_CB(skb
);
1196 struct b43_private_tx_info
*priv_info
= b43_get_priv_tx_info(info
);
1198 int slot
, old_top_slot
, old_used_slots
;
1200 struct b43_dmadesc_generic
*desc
;
1201 struct b43_dmadesc_meta
*meta
;
1202 struct b43_dmadesc_meta
*meta_hdr
;
1204 size_t hdrsize
= b43_txhdr_size(ring
->dev
);
1206 /* Important note: If the number of used DMA slots per TX frame
1207 * is changed here, the TX_SLOTS_PER_FRAME definition at the top of
1208 * the file has to be updated, too!
1211 old_top_slot
= ring
->current_slot
;
1212 old_used_slots
= ring
->used_slots
;
1214 /* Get a slot for the header. */
1215 slot
= request_slot(ring
);
1216 desc
= ops
->idx2desc(ring
, slot
, &meta_hdr
);
1217 memset(meta_hdr
, 0, sizeof(*meta_hdr
));
1219 header
= &(ring
->txhdr_cache
[(slot
/ TX_SLOTS_PER_FRAME
) * hdrsize
]);
1220 cookie
= generate_cookie(ring
, slot
);
1221 err
= b43_generate_txhdr(ring
->dev
, header
,
1223 if (unlikely(err
)) {
1224 ring
->current_slot
= old_top_slot
;
1225 ring
->used_slots
= old_used_slots
;
1229 meta_hdr
->dmaaddr
= map_descbuffer(ring
, (unsigned char *)header
,
1231 if (b43_dma_mapping_error(ring
, meta_hdr
->dmaaddr
, hdrsize
, 1)) {
1232 ring
->current_slot
= old_top_slot
;
1233 ring
->used_slots
= old_used_slots
;
1236 ops
->fill_descriptor(ring
, desc
, meta_hdr
->dmaaddr
,
1239 /* Get a slot for the payload. */
1240 slot
= request_slot(ring
);
1241 desc
= ops
->idx2desc(ring
, slot
, &meta
);
1242 memset(meta
, 0, sizeof(*meta
));
1245 meta
->is_last_fragment
= 1;
1246 priv_info
->bouncebuffer
= NULL
;
1248 meta
->dmaaddr
= map_descbuffer(ring
, skb
->data
, skb
->len
, 1);
1249 /* create a bounce buffer in zone_dma on mapping failure. */
1250 if (b43_dma_mapping_error(ring
, meta
->dmaaddr
, skb
->len
, 1)) {
1251 priv_info
->bouncebuffer
= kmemdup(skb
->data
, skb
->len
,
1252 GFP_ATOMIC
| GFP_DMA
);
1253 if (!priv_info
->bouncebuffer
) {
1254 ring
->current_slot
= old_top_slot
;
1255 ring
->used_slots
= old_used_slots
;
1260 meta
->dmaaddr
= map_descbuffer(ring
, priv_info
->bouncebuffer
, skb
->len
, 1);
1261 if (b43_dma_mapping_error(ring
, meta
->dmaaddr
, skb
->len
, 1)) {
1262 kfree(priv_info
->bouncebuffer
);
1263 priv_info
->bouncebuffer
= NULL
;
1264 ring
->current_slot
= old_top_slot
;
1265 ring
->used_slots
= old_used_slots
;
1271 ops
->fill_descriptor(ring
, desc
, meta
->dmaaddr
, skb
->len
, 0, 1, 1);
1273 if (info
->flags
& IEEE80211_TX_CTL_SEND_AFTER_DTIM
) {
1274 /* Tell the firmware about the cookie of the last
1275 * mcast frame, so it can clear the more-data bit in it. */
1276 b43_shm_write16(ring
->dev
, B43_SHM_SHARED
,
1277 B43_SHM_SH_MCASTCOOKIE
, cookie
);
1279 /* Now transfer the whole frame. */
1281 ops
->poke_tx(ring
, next_slot(ring
, slot
));
1285 unmap_descbuffer(ring
, meta_hdr
->dmaaddr
,
1290 static inline int should_inject_overflow(struct b43_dmaring
*ring
)
1292 #ifdef CONFIG_B43_DEBUG
1293 if (unlikely(b43_debug(ring
->dev
, B43_DBG_DMAOVERFLOW
))) {
1294 /* Check if we should inject another ringbuffer overflow
1295 * to test handling of this situation in the stack. */
1296 unsigned long next_overflow
;
1298 next_overflow
= ring
->last_injected_overflow
+ HZ
;
1299 if (time_after(jiffies
, next_overflow
)) {
1300 ring
->last_injected_overflow
= jiffies
;
1301 b43dbg(ring
->dev
->wl
,
1302 "Injecting TX ring overflow on "
1303 "DMA controller %d\n", ring
->index
);
1307 #endif /* CONFIG_B43_DEBUG */
1311 /* Static mapping of mac80211's queues (priorities) to b43 DMA rings. */
1312 static struct b43_dmaring
*select_ring_by_priority(struct b43_wldev
*dev
,
1315 struct b43_dmaring
*ring
;
1317 if (dev
->qos_enabled
) {
1318 /* 0 = highest priority */
1319 switch (queue_prio
) {
1324 ring
= dev
->dma
.tx_ring_AC_VO
;
1327 ring
= dev
->dma
.tx_ring_AC_VI
;
1330 ring
= dev
->dma
.tx_ring_AC_BE
;
1333 ring
= dev
->dma
.tx_ring_AC_BK
;
1337 ring
= dev
->dma
.tx_ring_AC_BE
;
1342 int b43_dma_tx(struct b43_wldev
*dev
, struct sk_buff
*skb
)
1344 struct b43_dmaring
*ring
;
1345 struct ieee80211_hdr
*hdr
;
1347 struct ieee80211_tx_info
*info
= IEEE80211_SKB_CB(skb
);
1349 hdr
= (struct ieee80211_hdr
*)skb
->data
;
1350 if (info
->flags
& IEEE80211_TX_CTL_SEND_AFTER_DTIM
) {
1351 /* The multicast ring will be sent after the DTIM */
1352 ring
= dev
->dma
.tx_ring_mcast
;
1353 /* Set the more-data bit. Ucode will clear it on
1354 * the last frame for us. */
1355 hdr
->frame_control
|= cpu_to_le16(IEEE80211_FCTL_MOREDATA
);
1357 /* Decide by priority where to put this frame. */
1358 ring
= select_ring_by_priority(
1359 dev
, skb_get_queue_mapping(skb
));
1362 B43_WARN_ON(!ring
->tx
);
1364 if (unlikely(ring
->stopped
)) {
1365 /* We get here only because of a bug in mac80211.
1366 * Because of a race, one packet may be queued after
1367 * the queue is stopped, thus we got called when we shouldn't.
1368 * For now, just refuse the transmit. */
1369 if (b43_debug(dev
, B43_DBG_DMAVERBOSE
))
1370 b43err(dev
->wl
, "Packet after queue stopped\n");
1375 if (unlikely(WARN_ON(free_slots(ring
) < TX_SLOTS_PER_FRAME
))) {
1376 /* If we get here, we have a real error with the queue
1377 * full, but queues not stopped. */
1378 b43err(dev
->wl
, "DMA queue overflow\n");
1383 /* Assign the queue number to the ring (if not already done before)
1384 * so TX status handling can use it. The queue to ring mapping is
1385 * static, so we don't need to store it per frame. */
1386 ring
->queue_prio
= skb_get_queue_mapping(skb
);
1388 err
= dma_tx_fragment(ring
, skb
);
1389 if (unlikely(err
== -ENOKEY
)) {
1390 /* Drop this packet, as we don't have the encryption key
1391 * anymore and must not transmit it unencrypted. */
1392 dev_kfree_skb_any(skb
);
1396 if (unlikely(err
)) {
1397 b43err(dev
->wl
, "DMA tx mapping failure\n");
1400 if ((free_slots(ring
) < TX_SLOTS_PER_FRAME
) ||
1401 should_inject_overflow(ring
)) {
1402 /* This TX ring is full. */
1403 ieee80211_stop_queue(dev
->wl
->hw
, skb_get_queue_mapping(skb
));
1405 if (b43_debug(dev
, B43_DBG_DMAVERBOSE
)) {
1406 b43dbg(dev
->wl
, "Stopped TX ring %d\n", ring
->index
);
1414 void b43_dma_handle_txstatus(struct b43_wldev
*dev
,
1415 const struct b43_txstatus
*status
)
1417 const struct b43_dma_ops
*ops
;
1418 struct b43_dmaring
*ring
;
1419 struct b43_dmadesc_meta
*meta
;
1420 int slot
, firstused
;
1423 ring
= parse_cookie(dev
, status
->cookie
, &slot
);
1424 if (unlikely(!ring
))
1426 B43_WARN_ON(!ring
->tx
);
1428 /* Sanity check: TX packets are processed in-order on one ring.
1429 * Check if the slot deduced from the cookie really is the first
1431 firstused
= ring
->current_slot
- ring
->used_slots
+ 1;
1433 firstused
= ring
->nr_slots
+ firstused
;
1434 if (unlikely(slot
!= firstused
)) {
1435 /* This possibly is a firmware bug and will result in
1436 * malfunction, memory leaks and/or stall of DMA functionality. */
1437 b43dbg(dev
->wl
, "Out of order TX status report on DMA ring %d. "
1438 "Expected %d, but got %d\n",
1439 ring
->index
, firstused
, slot
);
1445 B43_WARN_ON(slot
< 0 || slot
>= ring
->nr_slots
);
1446 /* get meta - ignore returned value */
1447 ops
->idx2desc(ring
, slot
, &meta
);
1449 if (b43_dma_ptr_is_poisoned(meta
->skb
)) {
1450 b43dbg(dev
->wl
, "Poisoned TX slot %d (first=%d) "
1452 slot
, firstused
, ring
->index
);
1456 struct b43_private_tx_info
*priv_info
=
1457 b43_get_priv_tx_info(IEEE80211_SKB_CB(meta
->skb
));
1459 unmap_descbuffer(ring
, meta
->dmaaddr
, meta
->skb
->len
, 1);
1460 kfree(priv_info
->bouncebuffer
);
1461 priv_info
->bouncebuffer
= NULL
;
1463 unmap_descbuffer(ring
, meta
->dmaaddr
,
1464 b43_txhdr_size(dev
), 1);
1467 if (meta
->is_last_fragment
) {
1468 struct ieee80211_tx_info
*info
;
1470 if (unlikely(!meta
->skb
)) {
1471 /* This is a scatter-gather fragment of a frame, so
1472 * the skb pointer must not be NULL. */
1473 b43dbg(dev
->wl
, "TX status unexpected NULL skb "
1474 "at slot %d (first=%d) on ring %d\n",
1475 slot
, firstused
, ring
->index
);
1479 info
= IEEE80211_SKB_CB(meta
->skb
);
1482 * Call back to inform the ieee80211 subsystem about
1483 * the status of the transmission.
1485 frame_succeed
= b43_fill_txstatus_report(dev
, info
, status
);
1486 #ifdef CONFIG_B43_DEBUG
1488 ring
->nr_succeed_tx_packets
++;
1490 ring
->nr_failed_tx_packets
++;
1491 ring
->nr_total_packet_tries
+= status
->frame_count
;
1493 ieee80211_tx_status(dev
->wl
->hw
, meta
->skb
);
1495 /* skb will be freed by ieee80211_tx_status().
1496 * Poison our pointer. */
1497 meta
->skb
= B43_DMA_PTR_POISON
;
1499 /* No need to call free_descriptor_buffer here, as
1500 * this is only the txhdr, which is not allocated.
1502 if (unlikely(meta
->skb
)) {
1503 b43dbg(dev
->wl
, "TX status unexpected non-NULL skb "
1504 "at slot %d (first=%d) on ring %d\n",
1505 slot
, firstused
, ring
->index
);
1510 /* Everything unmapped and free'd. So it's not used anymore. */
1513 if (meta
->is_last_fragment
) {
1514 /* This is the last scatter-gather
1515 * fragment of the frame. We are done. */
1518 slot
= next_slot(ring
, slot
);
1520 if (ring
->stopped
) {
1521 B43_WARN_ON(free_slots(ring
) < TX_SLOTS_PER_FRAME
);
1522 ieee80211_wake_queue(dev
->wl
->hw
, ring
->queue_prio
);
1524 if (b43_debug(dev
, B43_DBG_DMAVERBOSE
)) {
1525 b43dbg(dev
->wl
, "Woke up TX ring %d\n", ring
->index
);
1530 static void dma_rx(struct b43_dmaring
*ring
, int *slot
)
1532 const struct b43_dma_ops
*ops
= ring
->ops
;
1533 struct b43_dmadesc_generic
*desc
;
1534 struct b43_dmadesc_meta
*meta
;
1535 struct b43_rxhdr_fw4
*rxhdr
;
1536 struct sk_buff
*skb
;
1541 desc
= ops
->idx2desc(ring
, *slot
, &meta
);
1543 sync_descbuffer_for_cpu(ring
, meta
->dmaaddr
, ring
->rx_buffersize
);
1546 rxhdr
= (struct b43_rxhdr_fw4
*)skb
->data
;
1547 len
= le16_to_cpu(rxhdr
->frame_len
);
1554 len
= le16_to_cpu(rxhdr
->frame_len
);
1555 } while (len
== 0 && i
++ < 5);
1556 if (unlikely(len
== 0)) {
1557 dmaaddr
= meta
->dmaaddr
;
1558 goto drop_recycle_buffer
;
1561 if (unlikely(b43_rx_buffer_is_poisoned(ring
, skb
))) {
1562 /* Something went wrong with the DMA.
1563 * The device did not touch the buffer and did not overwrite the poison. */
1564 b43dbg(ring
->dev
->wl
, "DMA RX: Dropping poisoned buffer.\n");
1565 dmaaddr
= meta
->dmaaddr
;
1566 goto drop_recycle_buffer
;
1568 if (unlikely(len
+ ring
->frameoffset
> ring
->rx_buffersize
)) {
1569 /* The data did not fit into one descriptor buffer
1570 * and is split over multiple buffers.
1571 * This should never happen, as we try to allocate buffers
1572 * big enough. So simply ignore this packet.
1578 desc
= ops
->idx2desc(ring
, *slot
, &meta
);
1579 /* recycle the descriptor buffer. */
1580 b43_poison_rx_buffer(ring
, meta
->skb
);
1581 sync_descbuffer_for_device(ring
, meta
->dmaaddr
,
1582 ring
->rx_buffersize
);
1583 *slot
= next_slot(ring
, *slot
);
1585 tmp
-= ring
->rx_buffersize
;
1589 b43err(ring
->dev
->wl
, "DMA RX buffer too small "
1590 "(len: %u, buffer: %u, nr-dropped: %d)\n",
1591 len
, ring
->rx_buffersize
, cnt
);
1595 dmaaddr
= meta
->dmaaddr
;
1596 err
= setup_rx_descbuffer(ring
, desc
, meta
, GFP_ATOMIC
);
1597 if (unlikely(err
)) {
1598 b43dbg(ring
->dev
->wl
, "DMA RX: setup_rx_descbuffer() failed\n");
1599 goto drop_recycle_buffer
;
1602 unmap_descbuffer(ring
, dmaaddr
, ring
->rx_buffersize
, 0);
1603 skb_put(skb
, len
+ ring
->frameoffset
);
1604 skb_pull(skb
, ring
->frameoffset
);
1606 b43_rx(ring
->dev
, skb
, rxhdr
);
1610 drop_recycle_buffer
:
1611 /* Poison and recycle the RX buffer. */
1612 b43_poison_rx_buffer(ring
, skb
);
1613 sync_descbuffer_for_device(ring
, dmaaddr
, ring
->rx_buffersize
);
1616 void b43_dma_rx(struct b43_dmaring
*ring
)
1618 const struct b43_dma_ops
*ops
= ring
->ops
;
1619 int slot
, current_slot
;
1622 B43_WARN_ON(ring
->tx
);
1623 current_slot
= ops
->get_current_rxslot(ring
);
1624 B43_WARN_ON(!(current_slot
>= 0 && current_slot
< ring
->nr_slots
));
1626 slot
= ring
->current_slot
;
1627 for (; slot
!= current_slot
; slot
= next_slot(ring
, slot
)) {
1628 dma_rx(ring
, &slot
);
1629 update_max_used_slots(ring
, ++used_slots
);
1632 ops
->set_current_rxslot(ring
, slot
);
1633 ring
->current_slot
= slot
;
1636 static void b43_dma_tx_suspend_ring(struct b43_dmaring
*ring
)
1638 B43_WARN_ON(!ring
->tx
);
1639 ring
->ops
->tx_suspend(ring
);
1642 static void b43_dma_tx_resume_ring(struct b43_dmaring
*ring
)
1644 B43_WARN_ON(!ring
->tx
);
1645 ring
->ops
->tx_resume(ring
);
1648 void b43_dma_tx_suspend(struct b43_wldev
*dev
)
1650 b43_power_saving_ctl_bits(dev
, B43_PS_AWAKE
);
1651 b43_dma_tx_suspend_ring(dev
->dma
.tx_ring_AC_BK
);
1652 b43_dma_tx_suspend_ring(dev
->dma
.tx_ring_AC_BE
);
1653 b43_dma_tx_suspend_ring(dev
->dma
.tx_ring_AC_VI
);
1654 b43_dma_tx_suspend_ring(dev
->dma
.tx_ring_AC_VO
);
1655 b43_dma_tx_suspend_ring(dev
->dma
.tx_ring_mcast
);
1658 void b43_dma_tx_resume(struct b43_wldev
*dev
)
1660 b43_dma_tx_resume_ring(dev
->dma
.tx_ring_mcast
);
1661 b43_dma_tx_resume_ring(dev
->dma
.tx_ring_AC_VO
);
1662 b43_dma_tx_resume_ring(dev
->dma
.tx_ring_AC_VI
);
1663 b43_dma_tx_resume_ring(dev
->dma
.tx_ring_AC_BE
);
1664 b43_dma_tx_resume_ring(dev
->dma
.tx_ring_AC_BK
);
1665 b43_power_saving_ctl_bits(dev
, 0);
1668 static void direct_fifo_rx(struct b43_wldev
*dev
, enum b43_dmatype type
,
1669 u16 mmio_base
, bool enable
)
1673 if (type
== B43_DMA_64BIT
) {
1674 ctl
= b43_read32(dev
, mmio_base
+ B43_DMA64_RXCTL
);
1675 ctl
&= ~B43_DMA64_RXDIRECTFIFO
;
1677 ctl
|= B43_DMA64_RXDIRECTFIFO
;
1678 b43_write32(dev
, mmio_base
+ B43_DMA64_RXCTL
, ctl
);
1680 ctl
= b43_read32(dev
, mmio_base
+ B43_DMA32_RXCTL
);
1681 ctl
&= ~B43_DMA32_RXDIRECTFIFO
;
1683 ctl
|= B43_DMA32_RXDIRECTFIFO
;
1684 b43_write32(dev
, mmio_base
+ B43_DMA32_RXCTL
, ctl
);
1688 /* Enable/Disable Direct FIFO Receive Mode (PIO) on a RX engine.
1689 * This is called from PIO code, so DMA structures are not available. */
1690 void b43_dma_direct_fifo_rx(struct b43_wldev
*dev
,
1691 unsigned int engine_index
, bool enable
)
1693 enum b43_dmatype type
;
1696 type
= dma_mask_to_engine_type(supported_dma_mask(dev
));
1698 mmio_base
= b43_dmacontroller_base(type
, engine_index
);
1699 direct_fifo_rx(dev
, type
, mmio_base
, enable
);