3 Broadcom B43 wireless driver
5 DMA ringbuffer and descriptor allocation/management
7 Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de>
9 Some code in this file is derived from the b44.c driver
10 Copyright (C) 2002 David S. Miller
11 Copyright (C) Pekka Pietikainen
13 This program is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 2 of the License, or
16 (at your option) any later version.
18 This program is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with this program; see the file COPYING. If not, write to
25 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
26 Boston, MA 02110-1301, USA.
36 #include <linux/dma-mapping.h>
37 #include <linux/pci.h>
38 #include <linux/delay.h>
39 #include <linux/skbuff.h>
40 #include <linux/etherdevice.h>
41 #include <asm/div64.h>
46 struct b43_dmadesc_generic
*op32_idx2desc(struct b43_dmaring
*ring
,
48 struct b43_dmadesc_meta
**meta
)
50 struct b43_dmadesc32
*desc
;
52 *meta
= &(ring
->meta
[slot
]);
53 desc
= ring
->descbase
;
56 return (struct b43_dmadesc_generic
*)desc
;
59 static void op32_fill_descriptor(struct b43_dmaring
*ring
,
60 struct b43_dmadesc_generic
*desc
,
61 dma_addr_t dmaaddr
, u16 bufsize
,
62 int start
, int end
, int irq
)
64 struct b43_dmadesc32
*descbase
= ring
->descbase
;
70 slot
= (int)(&(desc
->dma32
) - descbase
);
71 B43_WARN_ON(!(slot
>= 0 && slot
< ring
->nr_slots
));
73 addr
= (u32
) (dmaaddr
& ~SSB_DMA_TRANSLATION_MASK
);
74 addrext
= (u32
) (dmaaddr
& SSB_DMA_TRANSLATION_MASK
)
75 >> SSB_DMA_TRANSLATION_SHIFT
;
76 addr
|= ssb_dma_translation(ring
->dev
->dev
);
77 ctl
= (bufsize
- ring
->frameoffset
)
78 & B43_DMA32_DCTL_BYTECNT
;
79 if (slot
== ring
->nr_slots
- 1)
80 ctl
|= B43_DMA32_DCTL_DTABLEEND
;
82 ctl
|= B43_DMA32_DCTL_FRAMESTART
;
84 ctl
|= B43_DMA32_DCTL_FRAMEEND
;
86 ctl
|= B43_DMA32_DCTL_IRQ
;
87 ctl
|= (addrext
<< B43_DMA32_DCTL_ADDREXT_SHIFT
)
88 & B43_DMA32_DCTL_ADDREXT_MASK
;
90 desc
->dma32
.control
= cpu_to_le32(ctl
);
91 desc
->dma32
.address
= cpu_to_le32(addr
);
94 static void op32_poke_tx(struct b43_dmaring
*ring
, int slot
)
96 b43_dma_write(ring
, B43_DMA32_TXINDEX
,
97 (u32
) (slot
* sizeof(struct b43_dmadesc32
)));
100 static void op32_tx_suspend(struct b43_dmaring
*ring
)
102 b43_dma_write(ring
, B43_DMA32_TXCTL
, b43_dma_read(ring
, B43_DMA32_TXCTL
)
103 | B43_DMA32_TXSUSPEND
);
106 static void op32_tx_resume(struct b43_dmaring
*ring
)
108 b43_dma_write(ring
, B43_DMA32_TXCTL
, b43_dma_read(ring
, B43_DMA32_TXCTL
)
109 & ~B43_DMA32_TXSUSPEND
);
112 static int op32_get_current_rxslot(struct b43_dmaring
*ring
)
116 val
= b43_dma_read(ring
, B43_DMA32_RXSTATUS
);
117 val
&= B43_DMA32_RXDPTR
;
119 return (val
/ sizeof(struct b43_dmadesc32
));
122 static void op32_set_current_rxslot(struct b43_dmaring
*ring
, int slot
)
124 b43_dma_write(ring
, B43_DMA32_RXINDEX
,
125 (u32
) (slot
* sizeof(struct b43_dmadesc32
)));
128 static const struct b43_dma_ops dma32_ops
= {
129 .idx2desc
= op32_idx2desc
,
130 .fill_descriptor
= op32_fill_descriptor
,
131 .poke_tx
= op32_poke_tx
,
132 .tx_suspend
= op32_tx_suspend
,
133 .tx_resume
= op32_tx_resume
,
134 .get_current_rxslot
= op32_get_current_rxslot
,
135 .set_current_rxslot
= op32_set_current_rxslot
,
140 struct b43_dmadesc_generic
*op64_idx2desc(struct b43_dmaring
*ring
,
142 struct b43_dmadesc_meta
**meta
)
144 struct b43_dmadesc64
*desc
;
146 *meta
= &(ring
->meta
[slot
]);
147 desc
= ring
->descbase
;
148 desc
= &(desc
[slot
]);
150 return (struct b43_dmadesc_generic
*)desc
;
153 static void op64_fill_descriptor(struct b43_dmaring
*ring
,
154 struct b43_dmadesc_generic
*desc
,
155 dma_addr_t dmaaddr
, u16 bufsize
,
156 int start
, int end
, int irq
)
158 struct b43_dmadesc64
*descbase
= ring
->descbase
;
160 u32 ctl0
= 0, ctl1
= 0;
164 slot
= (int)(&(desc
->dma64
) - descbase
);
165 B43_WARN_ON(!(slot
>= 0 && slot
< ring
->nr_slots
));
167 addrlo
= (u32
) (dmaaddr
& 0xFFFFFFFF);
168 addrhi
= (((u64
) dmaaddr
>> 32) & ~SSB_DMA_TRANSLATION_MASK
);
169 addrext
= (((u64
) dmaaddr
>> 32) & SSB_DMA_TRANSLATION_MASK
)
170 >> SSB_DMA_TRANSLATION_SHIFT
;
171 addrhi
|= (ssb_dma_translation(ring
->dev
->dev
) << 1);
172 if (slot
== ring
->nr_slots
- 1)
173 ctl0
|= B43_DMA64_DCTL0_DTABLEEND
;
175 ctl0
|= B43_DMA64_DCTL0_FRAMESTART
;
177 ctl0
|= B43_DMA64_DCTL0_FRAMEEND
;
179 ctl0
|= B43_DMA64_DCTL0_IRQ
;
180 ctl1
|= (bufsize
- ring
->frameoffset
)
181 & B43_DMA64_DCTL1_BYTECNT
;
182 ctl1
|= (addrext
<< B43_DMA64_DCTL1_ADDREXT_SHIFT
)
183 & B43_DMA64_DCTL1_ADDREXT_MASK
;
185 desc
->dma64
.control0
= cpu_to_le32(ctl0
);
186 desc
->dma64
.control1
= cpu_to_le32(ctl1
);
187 desc
->dma64
.address_low
= cpu_to_le32(addrlo
);
188 desc
->dma64
.address_high
= cpu_to_le32(addrhi
);
191 static void op64_poke_tx(struct b43_dmaring
*ring
, int slot
)
193 b43_dma_write(ring
, B43_DMA64_TXINDEX
,
194 (u32
) (slot
* sizeof(struct b43_dmadesc64
)));
197 static void op64_tx_suspend(struct b43_dmaring
*ring
)
199 b43_dma_write(ring
, B43_DMA64_TXCTL
, b43_dma_read(ring
, B43_DMA64_TXCTL
)
200 | B43_DMA64_TXSUSPEND
);
203 static void op64_tx_resume(struct b43_dmaring
*ring
)
205 b43_dma_write(ring
, B43_DMA64_TXCTL
, b43_dma_read(ring
, B43_DMA64_TXCTL
)
206 & ~B43_DMA64_TXSUSPEND
);
209 static int op64_get_current_rxslot(struct b43_dmaring
*ring
)
213 val
= b43_dma_read(ring
, B43_DMA64_RXSTATUS
);
214 val
&= B43_DMA64_RXSTATDPTR
;
216 return (val
/ sizeof(struct b43_dmadesc64
));
219 static void op64_set_current_rxslot(struct b43_dmaring
*ring
, int slot
)
221 b43_dma_write(ring
, B43_DMA64_RXINDEX
,
222 (u32
) (slot
* sizeof(struct b43_dmadesc64
)));
225 static const struct b43_dma_ops dma64_ops
= {
226 .idx2desc
= op64_idx2desc
,
227 .fill_descriptor
= op64_fill_descriptor
,
228 .poke_tx
= op64_poke_tx
,
229 .tx_suspend
= op64_tx_suspend
,
230 .tx_resume
= op64_tx_resume
,
231 .get_current_rxslot
= op64_get_current_rxslot
,
232 .set_current_rxslot
= op64_set_current_rxslot
,
235 static inline int free_slots(struct b43_dmaring
*ring
)
237 return (ring
->nr_slots
- ring
->used_slots
);
240 static inline int next_slot(struct b43_dmaring
*ring
, int slot
)
242 B43_WARN_ON(!(slot
>= -1 && slot
<= ring
->nr_slots
- 1));
243 if (slot
== ring
->nr_slots
- 1)
248 static inline int prev_slot(struct b43_dmaring
*ring
, int slot
)
250 B43_WARN_ON(!(slot
>= 0 && slot
<= ring
->nr_slots
- 1));
252 return ring
->nr_slots
- 1;
256 #ifdef CONFIG_B43_DEBUG
257 static void update_max_used_slots(struct b43_dmaring
*ring
,
258 int current_used_slots
)
260 if (current_used_slots
<= ring
->max_used_slots
)
262 ring
->max_used_slots
= current_used_slots
;
263 if (b43_debug(ring
->dev
, B43_DBG_DMAVERBOSE
)) {
264 b43dbg(ring
->dev
->wl
,
265 "max_used_slots increased to %d on %s ring %d\n",
266 ring
->max_used_slots
,
267 ring
->tx
? "TX" : "RX", ring
->index
);
272 void update_max_used_slots(struct b43_dmaring
*ring
, int current_used_slots
)
277 /* Request a slot for usage. */
278 static inline int request_slot(struct b43_dmaring
*ring
)
282 B43_WARN_ON(!ring
->tx
);
283 B43_WARN_ON(ring
->stopped
);
284 B43_WARN_ON(free_slots(ring
) == 0);
286 slot
= next_slot(ring
, ring
->current_slot
);
287 ring
->current_slot
= slot
;
290 update_max_used_slots(ring
, ring
->used_slots
);
295 static u16
b43_dmacontroller_base(enum b43_dmatype type
, int controller_idx
)
297 static const u16 map64
[] = {
298 B43_MMIO_DMA64_BASE0
,
299 B43_MMIO_DMA64_BASE1
,
300 B43_MMIO_DMA64_BASE2
,
301 B43_MMIO_DMA64_BASE3
,
302 B43_MMIO_DMA64_BASE4
,
303 B43_MMIO_DMA64_BASE5
,
305 static const u16 map32
[] = {
306 B43_MMIO_DMA32_BASE0
,
307 B43_MMIO_DMA32_BASE1
,
308 B43_MMIO_DMA32_BASE2
,
309 B43_MMIO_DMA32_BASE3
,
310 B43_MMIO_DMA32_BASE4
,
311 B43_MMIO_DMA32_BASE5
,
314 if (type
== B43_DMA_64BIT
) {
315 B43_WARN_ON(!(controller_idx
>= 0 &&
316 controller_idx
< ARRAY_SIZE(map64
)));
317 return map64
[controller_idx
];
319 B43_WARN_ON(!(controller_idx
>= 0 &&
320 controller_idx
< ARRAY_SIZE(map32
)));
321 return map32
[controller_idx
];
325 dma_addr_t
map_descbuffer(struct b43_dmaring
*ring
,
326 unsigned char *buf
, size_t len
, int tx
)
331 dmaaddr
= dma_map_single(ring
->dev
->dev
->dma_dev
,
332 buf
, len
, DMA_TO_DEVICE
);
334 dmaaddr
= dma_map_single(ring
->dev
->dev
->dma_dev
,
335 buf
, len
, DMA_FROM_DEVICE
);
342 void unmap_descbuffer(struct b43_dmaring
*ring
,
343 dma_addr_t addr
, size_t len
, int tx
)
346 dma_unmap_single(ring
->dev
->dev
->dma_dev
,
347 addr
, len
, DMA_TO_DEVICE
);
349 dma_unmap_single(ring
->dev
->dev
->dma_dev
,
350 addr
, len
, DMA_FROM_DEVICE
);
355 void sync_descbuffer_for_cpu(struct b43_dmaring
*ring
,
356 dma_addr_t addr
, size_t len
)
358 B43_WARN_ON(ring
->tx
);
359 dma_sync_single_for_cpu(ring
->dev
->dev
->dma_dev
,
360 addr
, len
, DMA_FROM_DEVICE
);
364 void sync_descbuffer_for_device(struct b43_dmaring
*ring
,
365 dma_addr_t addr
, size_t len
)
367 B43_WARN_ON(ring
->tx
);
368 dma_sync_single_for_device(ring
->dev
->dev
->dma_dev
,
369 addr
, len
, DMA_FROM_DEVICE
);
373 void free_descriptor_buffer(struct b43_dmaring
*ring
,
374 struct b43_dmadesc_meta
*meta
)
377 dev_kfree_skb_any(meta
->skb
);
382 static int alloc_ringmemory(struct b43_dmaring
*ring
)
384 struct device
*dma_dev
= ring
->dev
->dev
->dma_dev
;
385 gfp_t flags
= GFP_KERNEL
;
387 /* The specs call for 4K buffers for 30- and 32-bit DMA with 4K
388 * alignment and 8K buffers for 64-bit DMA with 8K alignment. Testing
389 * has shown that 4K is sufficient for the latter as long as the buffer
390 * does not cross an 8K boundary.
392 * For unknown reasons - possibly a hardware error - the BCM4311 rev
393 * 02, which uses 64-bit DMA, needs the ring buffer in very low memory,
394 * which accounts for the GFP_DMA flag below.
396 if (ring
->type
== B43_DMA_64BIT
)
398 ring
->descbase
= dma_alloc_coherent(dma_dev
, B43_DMA_RINGMEMSIZE
,
399 &(ring
->dmabase
), flags
);
400 if (!ring
->descbase
) {
401 b43err(ring
->dev
->wl
, "DMA ringmemory allocation failed\n");
404 memset(ring
->descbase
, 0, B43_DMA_RINGMEMSIZE
);
409 static void free_ringmemory(struct b43_dmaring
*ring
)
411 struct device
*dma_dev
= ring
->dev
->dev
->dma_dev
;
413 dma_free_coherent(dma_dev
, B43_DMA_RINGMEMSIZE
,
414 ring
->descbase
, ring
->dmabase
);
417 /* Reset the RX DMA channel */
418 static int b43_dmacontroller_rx_reset(struct b43_wldev
*dev
, u16 mmio_base
,
419 enum b43_dmatype type
)
427 offset
= (type
== B43_DMA_64BIT
) ? B43_DMA64_RXCTL
: B43_DMA32_RXCTL
;
428 b43_write32(dev
, mmio_base
+ offset
, 0);
429 for (i
= 0; i
< 10; i
++) {
430 offset
= (type
== B43_DMA_64BIT
) ? B43_DMA64_RXSTATUS
:
432 value
= b43_read32(dev
, mmio_base
+ offset
);
433 if (type
== B43_DMA_64BIT
) {
434 value
&= B43_DMA64_RXSTAT
;
435 if (value
== B43_DMA64_RXSTAT_DISABLED
) {
440 value
&= B43_DMA32_RXSTATE
;
441 if (value
== B43_DMA32_RXSTAT_DISABLED
) {
449 b43err(dev
->wl
, "DMA RX reset timed out\n");
456 /* Reset the TX DMA channel */
457 static int b43_dmacontroller_tx_reset(struct b43_wldev
*dev
, u16 mmio_base
,
458 enum b43_dmatype type
)
466 for (i
= 0; i
< 10; i
++) {
467 offset
= (type
== B43_DMA_64BIT
) ? B43_DMA64_TXSTATUS
:
469 value
= b43_read32(dev
, mmio_base
+ offset
);
470 if (type
== B43_DMA_64BIT
) {
471 value
&= B43_DMA64_TXSTAT
;
472 if (value
== B43_DMA64_TXSTAT_DISABLED
||
473 value
== B43_DMA64_TXSTAT_IDLEWAIT
||
474 value
== B43_DMA64_TXSTAT_STOPPED
)
477 value
&= B43_DMA32_TXSTATE
;
478 if (value
== B43_DMA32_TXSTAT_DISABLED
||
479 value
== B43_DMA32_TXSTAT_IDLEWAIT
||
480 value
== B43_DMA32_TXSTAT_STOPPED
)
485 offset
= (type
== B43_DMA_64BIT
) ? B43_DMA64_TXCTL
: B43_DMA32_TXCTL
;
486 b43_write32(dev
, mmio_base
+ offset
, 0);
487 for (i
= 0; i
< 10; i
++) {
488 offset
= (type
== B43_DMA_64BIT
) ? B43_DMA64_TXSTATUS
:
490 value
= b43_read32(dev
, mmio_base
+ offset
);
491 if (type
== B43_DMA_64BIT
) {
492 value
&= B43_DMA64_TXSTAT
;
493 if (value
== B43_DMA64_TXSTAT_DISABLED
) {
498 value
&= B43_DMA32_TXSTATE
;
499 if (value
== B43_DMA32_TXSTAT_DISABLED
) {
507 b43err(dev
->wl
, "DMA TX reset timed out\n");
510 /* ensure the reset is completed. */
516 /* Check if a DMA mapping address is invalid. */
517 static bool b43_dma_mapping_error(struct b43_dmaring
*ring
,
519 size_t buffersize
, bool dma_to_device
)
521 if (unlikely(dma_mapping_error(addr
)))
524 switch (ring
->type
) {
526 if ((u64
)addr
+ buffersize
> (1ULL << 30))
530 if ((u64
)addr
+ buffersize
> (1ULL << 32))
534 /* Currently we can't have addresses beyond
535 * 64bit in the kernel. */
539 /* The address is OK. */
543 /* We can't support this address. Unmap it again. */
544 unmap_descbuffer(ring
, addr
, buffersize
, dma_to_device
);
549 static int setup_rx_descbuffer(struct b43_dmaring
*ring
,
550 struct b43_dmadesc_generic
*desc
,
551 struct b43_dmadesc_meta
*meta
, gfp_t gfp_flags
)
553 struct b43_rxhdr_fw4
*rxhdr
;
557 B43_WARN_ON(ring
->tx
);
559 skb
= __dev_alloc_skb(ring
->rx_buffersize
, gfp_flags
);
562 dmaaddr
= map_descbuffer(ring
, skb
->data
, ring
->rx_buffersize
, 0);
563 if (b43_dma_mapping_error(ring
, dmaaddr
, ring
->rx_buffersize
, 0)) {
564 /* ugh. try to realloc in zone_dma */
565 gfp_flags
|= GFP_DMA
;
567 dev_kfree_skb_any(skb
);
569 skb
= __dev_alloc_skb(ring
->rx_buffersize
, gfp_flags
);
572 dmaaddr
= map_descbuffer(ring
, skb
->data
,
573 ring
->rx_buffersize
, 0);
576 if (b43_dma_mapping_error(ring
, dmaaddr
, ring
->rx_buffersize
, 0)) {
577 b43err(ring
->dev
->wl
, "RX DMA buffer allocation failed\n");
578 dev_kfree_skb_any(skb
);
583 meta
->dmaaddr
= dmaaddr
;
584 ring
->ops
->fill_descriptor(ring
, desc
, dmaaddr
,
585 ring
->rx_buffersize
, 0, 0, 0);
587 rxhdr
= (struct b43_rxhdr_fw4
*)(skb
->data
);
588 rxhdr
->frame_len
= 0;
593 /* Allocate the initial descbuffers.
594 * This is used for an RX ring only.
596 static int alloc_initial_descbuffers(struct b43_dmaring
*ring
)
598 int i
, err
= -ENOMEM
;
599 struct b43_dmadesc_generic
*desc
;
600 struct b43_dmadesc_meta
*meta
;
602 for (i
= 0; i
< ring
->nr_slots
; i
++) {
603 desc
= ring
->ops
->idx2desc(ring
, i
, &meta
);
605 err
= setup_rx_descbuffer(ring
, desc
, meta
, GFP_KERNEL
);
607 b43err(ring
->dev
->wl
,
608 "Failed to allocate initial descbuffers\n");
613 ring
->used_slots
= ring
->nr_slots
;
619 for (i
--; i
>= 0; i
--) {
620 desc
= ring
->ops
->idx2desc(ring
, i
, &meta
);
622 unmap_descbuffer(ring
, meta
->dmaaddr
, ring
->rx_buffersize
, 0);
623 dev_kfree_skb(meta
->skb
);
628 /* Do initial setup of the DMA controller.
629 * Reset the controller, write the ring busaddress
630 * and switch the "enable" bit on.
632 static int dmacontroller_setup(struct b43_dmaring
*ring
)
637 u32 trans
= ssb_dma_translation(ring
->dev
->dev
);
640 if (ring
->type
== B43_DMA_64BIT
) {
641 u64 ringbase
= (u64
) (ring
->dmabase
);
643 addrext
= ((ringbase
>> 32) & SSB_DMA_TRANSLATION_MASK
)
644 >> SSB_DMA_TRANSLATION_SHIFT
;
645 value
= B43_DMA64_TXENABLE
;
646 value
|= (addrext
<< B43_DMA64_TXADDREXT_SHIFT
)
647 & B43_DMA64_TXADDREXT_MASK
;
648 b43_dma_write(ring
, B43_DMA64_TXCTL
, value
);
649 b43_dma_write(ring
, B43_DMA64_TXRINGLO
,
650 (ringbase
& 0xFFFFFFFF));
651 b43_dma_write(ring
, B43_DMA64_TXRINGHI
,
653 ~SSB_DMA_TRANSLATION_MASK
)
656 u32 ringbase
= (u32
) (ring
->dmabase
);
658 addrext
= (ringbase
& SSB_DMA_TRANSLATION_MASK
)
659 >> SSB_DMA_TRANSLATION_SHIFT
;
660 value
= B43_DMA32_TXENABLE
;
661 value
|= (addrext
<< B43_DMA32_TXADDREXT_SHIFT
)
662 & B43_DMA32_TXADDREXT_MASK
;
663 b43_dma_write(ring
, B43_DMA32_TXCTL
, value
);
664 b43_dma_write(ring
, B43_DMA32_TXRING
,
665 (ringbase
& ~SSB_DMA_TRANSLATION_MASK
)
669 err
= alloc_initial_descbuffers(ring
);
672 if (ring
->type
== B43_DMA_64BIT
) {
673 u64 ringbase
= (u64
) (ring
->dmabase
);
675 addrext
= ((ringbase
>> 32) & SSB_DMA_TRANSLATION_MASK
)
676 >> SSB_DMA_TRANSLATION_SHIFT
;
677 value
= (ring
->frameoffset
<< B43_DMA64_RXFROFF_SHIFT
);
678 value
|= B43_DMA64_RXENABLE
;
679 value
|= (addrext
<< B43_DMA64_RXADDREXT_SHIFT
)
680 & B43_DMA64_RXADDREXT_MASK
;
681 b43_dma_write(ring
, B43_DMA64_RXCTL
, value
);
682 b43_dma_write(ring
, B43_DMA64_RXRINGLO
,
683 (ringbase
& 0xFFFFFFFF));
684 b43_dma_write(ring
, B43_DMA64_RXRINGHI
,
686 ~SSB_DMA_TRANSLATION_MASK
)
688 b43_dma_write(ring
, B43_DMA64_RXINDEX
, ring
->nr_slots
*
689 sizeof(struct b43_dmadesc64
));
691 u32 ringbase
= (u32
) (ring
->dmabase
);
693 addrext
= (ringbase
& SSB_DMA_TRANSLATION_MASK
)
694 >> SSB_DMA_TRANSLATION_SHIFT
;
695 value
= (ring
->frameoffset
<< B43_DMA32_RXFROFF_SHIFT
);
696 value
|= B43_DMA32_RXENABLE
;
697 value
|= (addrext
<< B43_DMA32_RXADDREXT_SHIFT
)
698 & B43_DMA32_RXADDREXT_MASK
;
699 b43_dma_write(ring
, B43_DMA32_RXCTL
, value
);
700 b43_dma_write(ring
, B43_DMA32_RXRING
,
701 (ringbase
& ~SSB_DMA_TRANSLATION_MASK
)
703 b43_dma_write(ring
, B43_DMA32_RXINDEX
, ring
->nr_slots
*
704 sizeof(struct b43_dmadesc32
));
712 /* Shutdown the DMA controller. */
713 static void dmacontroller_cleanup(struct b43_dmaring
*ring
)
716 b43_dmacontroller_tx_reset(ring
->dev
, ring
->mmio_base
,
718 if (ring
->type
== B43_DMA_64BIT
) {
719 b43_dma_write(ring
, B43_DMA64_TXRINGLO
, 0);
720 b43_dma_write(ring
, B43_DMA64_TXRINGHI
, 0);
722 b43_dma_write(ring
, B43_DMA32_TXRING
, 0);
724 b43_dmacontroller_rx_reset(ring
->dev
, ring
->mmio_base
,
726 if (ring
->type
== B43_DMA_64BIT
) {
727 b43_dma_write(ring
, B43_DMA64_RXRINGLO
, 0);
728 b43_dma_write(ring
, B43_DMA64_RXRINGHI
, 0);
730 b43_dma_write(ring
, B43_DMA32_RXRING
, 0);
734 static void free_all_descbuffers(struct b43_dmaring
*ring
)
736 struct b43_dmadesc_generic
*desc
;
737 struct b43_dmadesc_meta
*meta
;
740 if (!ring
->used_slots
)
742 for (i
= 0; i
< ring
->nr_slots
; i
++) {
743 desc
= ring
->ops
->idx2desc(ring
, i
, &meta
);
746 B43_WARN_ON(!ring
->tx
);
750 unmap_descbuffer(ring
, meta
->dmaaddr
,
753 unmap_descbuffer(ring
, meta
->dmaaddr
,
754 ring
->rx_buffersize
, 0);
756 free_descriptor_buffer(ring
, meta
);
760 static u64
supported_dma_mask(struct b43_wldev
*dev
)
765 tmp
= b43_read32(dev
, SSB_TMSHIGH
);
766 if (tmp
& SSB_TMSHIGH_DMA64
)
767 return DMA_64BIT_MASK
;
768 mmio_base
= b43_dmacontroller_base(0, 0);
769 b43_write32(dev
, mmio_base
+ B43_DMA32_TXCTL
, B43_DMA32_TXADDREXT_MASK
);
770 tmp
= b43_read32(dev
, mmio_base
+ B43_DMA32_TXCTL
);
771 if (tmp
& B43_DMA32_TXADDREXT_MASK
)
772 return DMA_32BIT_MASK
;
774 return DMA_30BIT_MASK
;
777 static enum b43_dmatype
dma_mask_to_engine_type(u64 dmamask
)
779 if (dmamask
== DMA_30BIT_MASK
)
780 return B43_DMA_30BIT
;
781 if (dmamask
== DMA_32BIT_MASK
)
782 return B43_DMA_32BIT
;
783 if (dmamask
== DMA_64BIT_MASK
)
784 return B43_DMA_64BIT
;
786 return B43_DMA_30BIT
;
789 /* Main initialization function. */
791 struct b43_dmaring
*b43_setup_dmaring(struct b43_wldev
*dev
,
792 int controller_index
,
794 enum b43_dmatype type
)
796 struct b43_dmaring
*ring
;
801 ring
= kzalloc(sizeof(*ring
), GFP_KERNEL
);
806 nr_slots
= B43_RXRING_SLOTS
;
808 nr_slots
= B43_TXRING_SLOTS
;
810 ring
->meta
= kcalloc(nr_slots
, sizeof(struct b43_dmadesc_meta
),
815 ring
->txhdr_cache
= kcalloc(nr_slots
,
818 if (!ring
->txhdr_cache
)
821 /* test for ability to dma to txhdr_cache */
822 dma_test
= dma_map_single(dev
->dev
->dma_dev
,
827 if (b43_dma_mapping_error(ring
, dma_test
,
828 b43_txhdr_size(dev
), 1)) {
830 kfree(ring
->txhdr_cache
);
831 ring
->txhdr_cache
= kcalloc(nr_slots
,
833 GFP_KERNEL
| GFP_DMA
);
834 if (!ring
->txhdr_cache
)
837 dma_test
= dma_map_single(dev
->dev
->dma_dev
,
842 if (b43_dma_mapping_error(ring
, dma_test
,
843 b43_txhdr_size(dev
), 1)) {
846 "TXHDR DMA allocation failed\n");
847 goto err_kfree_txhdr_cache
;
851 dma_unmap_single(dev
->dev
->dma_dev
,
852 dma_test
, b43_txhdr_size(dev
),
857 ring
->nr_slots
= nr_slots
;
858 ring
->mmio_base
= b43_dmacontroller_base(type
, controller_index
);
859 ring
->index
= controller_index
;
860 if (type
== B43_DMA_64BIT
)
861 ring
->ops
= &dma64_ops
;
863 ring
->ops
= &dma32_ops
;
866 ring
->current_slot
= -1;
868 if (ring
->index
== 0) {
869 ring
->rx_buffersize
= B43_DMA0_RX_BUFFERSIZE
;
870 ring
->frameoffset
= B43_DMA0_RX_FRAMEOFFSET
;
871 } else if (ring
->index
== 3) {
872 ring
->rx_buffersize
= B43_DMA3_RX_BUFFERSIZE
;
873 ring
->frameoffset
= B43_DMA3_RX_FRAMEOFFSET
;
877 spin_lock_init(&ring
->lock
);
878 #ifdef CONFIG_B43_DEBUG
879 ring
->last_injected_overflow
= jiffies
;
882 err
= alloc_ringmemory(ring
);
884 goto err_kfree_txhdr_cache
;
885 err
= dmacontroller_setup(ring
);
887 goto err_free_ringmemory
;
893 free_ringmemory(ring
);
894 err_kfree_txhdr_cache
:
895 kfree(ring
->txhdr_cache
);
904 #define divide(a, b) ({ \
910 #define modulo(a, b) ({ \
915 /* Main cleanup function. */
916 static void b43_destroy_dmaring(struct b43_dmaring
*ring
,
917 const char *ringname
)
922 #ifdef CONFIG_B43_DEBUG
924 /* Print some statistics. */
925 u64 failed_packets
= ring
->nr_failed_tx_packets
;
926 u64 succeed_packets
= ring
->nr_succeed_tx_packets
;
927 u64 nr_packets
= failed_packets
+ succeed_packets
;
928 u64 permille_failed
= 0, average_tries
= 0;
931 permille_failed
= divide(failed_packets
* 1000, nr_packets
);
933 average_tries
= divide(ring
->nr_total_packet_tries
* 100, nr_packets
);
935 b43dbg(ring
->dev
->wl
, "DMA-%u %s: "
936 "Used slots %d/%d, Failed frames %llu/%llu = %llu.%01llu%%, "
937 "Average tries %llu.%02llu\n",
938 (unsigned int)(ring
->type
), ringname
,
939 ring
->max_used_slots
,
941 (unsigned long long)failed_packets
,
942 (unsigned long long)nr_packets
,
943 (unsigned long long)divide(permille_failed
, 10),
944 (unsigned long long)modulo(permille_failed
, 10),
945 (unsigned long long)divide(average_tries
, 100),
946 (unsigned long long)modulo(average_tries
, 100));
950 /* Device IRQs are disabled prior entering this function,
951 * so no need to take care of concurrency with rx handler stuff.
953 dmacontroller_cleanup(ring
);
954 free_all_descbuffers(ring
);
955 free_ringmemory(ring
);
957 kfree(ring
->txhdr_cache
);
962 #define destroy_ring(dma, ring) do { \
963 b43_destroy_dmaring((dma)->ring, __stringify(ring)); \
964 (dma)->ring = NULL; \
967 void b43_dma_free(struct b43_wldev
*dev
)
971 if (b43_using_pio_transfers(dev
))
975 destroy_ring(dma
, rx_ring
);
976 destroy_ring(dma
, tx_ring_AC_BK
);
977 destroy_ring(dma
, tx_ring_AC_BE
);
978 destroy_ring(dma
, tx_ring_AC_VI
);
979 destroy_ring(dma
, tx_ring_AC_VO
);
980 destroy_ring(dma
, tx_ring_mcast
);
983 int b43_dma_init(struct b43_wldev
*dev
)
985 struct b43_dma
*dma
= &dev
->dma
;
988 enum b43_dmatype type
;
990 dmamask
= supported_dma_mask(dev
);
991 type
= dma_mask_to_engine_type(dmamask
);
992 err
= ssb_dma_set_mask(dev
->dev
, dmamask
);
994 b43err(dev
->wl
, "The machine/kernel does not support "
995 "the required DMA mask (0x%08X%08X)\n",
996 (unsigned int)((dmamask
& 0xFFFFFFFF00000000ULL
) >> 32),
997 (unsigned int)(dmamask
& 0x00000000FFFFFFFFULL
));
1002 /* setup TX DMA channels. */
1003 dma
->tx_ring_AC_BK
= b43_setup_dmaring(dev
, 0, 1, type
);
1004 if (!dma
->tx_ring_AC_BK
)
1007 dma
->tx_ring_AC_BE
= b43_setup_dmaring(dev
, 1, 1, type
);
1008 if (!dma
->tx_ring_AC_BE
)
1009 goto err_destroy_bk
;
1011 dma
->tx_ring_AC_VI
= b43_setup_dmaring(dev
, 2, 1, type
);
1012 if (!dma
->tx_ring_AC_VI
)
1013 goto err_destroy_be
;
1015 dma
->tx_ring_AC_VO
= b43_setup_dmaring(dev
, 3, 1, type
);
1016 if (!dma
->tx_ring_AC_VO
)
1017 goto err_destroy_vi
;
1019 dma
->tx_ring_mcast
= b43_setup_dmaring(dev
, 4, 1, type
);
1020 if (!dma
->tx_ring_mcast
)
1021 goto err_destroy_vo
;
1023 /* setup RX DMA channel. */
1024 dma
->rx_ring
= b43_setup_dmaring(dev
, 0, 0, type
);
1026 goto err_destroy_mcast
;
1028 /* No support for the TX status DMA ring. */
1029 B43_WARN_ON(dev
->dev
->id
.revision
< 5);
1031 b43dbg(dev
->wl
, "%u-bit DMA initialized\n",
1032 (unsigned int)type
);
1038 destroy_ring(dma
, tx_ring_mcast
);
1040 destroy_ring(dma
, tx_ring_AC_VO
);
1042 destroy_ring(dma
, tx_ring_AC_VI
);
1044 destroy_ring(dma
, tx_ring_AC_BE
);
1046 destroy_ring(dma
, tx_ring_AC_BK
);
1050 /* Generate a cookie for the TX header. */
1051 static u16
generate_cookie(struct b43_dmaring
*ring
, int slot
)
1055 /* Use the upper 4 bits of the cookie as
1056 * DMA controller ID and store the slot number
1057 * in the lower 12 bits.
1058 * Note that the cookie must never be 0, as this
1059 * is a special value used in RX path.
1060 * It can also not be 0xFFFF because that is special
1061 * for multicast frames.
1063 cookie
= (((u16
)ring
->index
+ 1) << 12);
1064 B43_WARN_ON(slot
& ~0x0FFF);
1065 cookie
|= (u16
)slot
;
1070 /* Inspect a cookie and find out to which controller/slot it belongs. */
1072 struct b43_dmaring
*parse_cookie(struct b43_wldev
*dev
, u16 cookie
, int *slot
)
1074 struct b43_dma
*dma
= &dev
->dma
;
1075 struct b43_dmaring
*ring
= NULL
;
1077 switch (cookie
& 0xF000) {
1079 ring
= dma
->tx_ring_AC_BK
;
1082 ring
= dma
->tx_ring_AC_BE
;
1085 ring
= dma
->tx_ring_AC_VI
;
1088 ring
= dma
->tx_ring_AC_VO
;
1091 ring
= dma
->tx_ring_mcast
;
1096 *slot
= (cookie
& 0x0FFF);
1097 B43_WARN_ON(!(ring
&& *slot
>= 0 && *slot
< ring
->nr_slots
));
1102 static int dma_tx_fragment(struct b43_dmaring
*ring
,
1103 struct sk_buff
*skb
,
1104 struct ieee80211_tx_control
*ctl
)
1106 const struct b43_dma_ops
*ops
= ring
->ops
;
1108 int slot
, old_top_slot
, old_used_slots
;
1110 struct b43_dmadesc_generic
*desc
;
1111 struct b43_dmadesc_meta
*meta
;
1112 struct b43_dmadesc_meta
*meta_hdr
;
1113 struct sk_buff
*bounce_skb
;
1115 size_t hdrsize
= b43_txhdr_size(ring
->dev
);
1117 #define SLOTS_PER_PACKET 2
1119 old_top_slot
= ring
->current_slot
;
1120 old_used_slots
= ring
->used_slots
;
1122 /* Get a slot for the header. */
1123 slot
= request_slot(ring
);
1124 desc
= ops
->idx2desc(ring
, slot
, &meta_hdr
);
1125 memset(meta_hdr
, 0, sizeof(*meta_hdr
));
1127 header
= &(ring
->txhdr_cache
[slot
* hdrsize
]);
1128 cookie
= generate_cookie(ring
, slot
);
1129 err
= b43_generate_txhdr(ring
->dev
, header
,
1130 skb
->data
, skb
->len
, ctl
, cookie
);
1131 if (unlikely(err
)) {
1132 ring
->current_slot
= old_top_slot
;
1133 ring
->used_slots
= old_used_slots
;
1137 meta_hdr
->dmaaddr
= map_descbuffer(ring
, (unsigned char *)header
,
1139 if (b43_dma_mapping_error(ring
, meta_hdr
->dmaaddr
, hdrsize
, 1)) {
1140 ring
->current_slot
= old_top_slot
;
1141 ring
->used_slots
= old_used_slots
;
1144 ops
->fill_descriptor(ring
, desc
, meta_hdr
->dmaaddr
,
1147 /* Get a slot for the payload. */
1148 slot
= request_slot(ring
);
1149 desc
= ops
->idx2desc(ring
, slot
, &meta
);
1150 memset(meta
, 0, sizeof(*meta
));
1152 memcpy(&meta
->txstat
.control
, ctl
, sizeof(*ctl
));
1154 meta
->is_last_fragment
= 1;
1156 meta
->dmaaddr
= map_descbuffer(ring
, skb
->data
, skb
->len
, 1);
1157 /* create a bounce buffer in zone_dma on mapping failure. */
1158 if (b43_dma_mapping_error(ring
, meta
->dmaaddr
, skb
->len
, 1)) {
1159 bounce_skb
= __dev_alloc_skb(skb
->len
, GFP_ATOMIC
| GFP_DMA
);
1161 ring
->current_slot
= old_top_slot
;
1162 ring
->used_slots
= old_used_slots
;
1167 memcpy(skb_put(bounce_skb
, skb
->len
), skb
->data
, skb
->len
);
1168 dev_kfree_skb_any(skb
);
1171 meta
->dmaaddr
= map_descbuffer(ring
, skb
->data
, skb
->len
, 1);
1172 if (b43_dma_mapping_error(ring
, meta
->dmaaddr
, skb
->len
, 1)) {
1173 ring
->current_slot
= old_top_slot
;
1174 ring
->used_slots
= old_used_slots
;
1176 goto out_free_bounce
;
1180 ops
->fill_descriptor(ring
, desc
, meta
->dmaaddr
, skb
->len
, 0, 1, 1);
1182 if (ctl
->flags
& IEEE80211_TXCTL_SEND_AFTER_DTIM
) {
1183 /* Tell the firmware about the cookie of the last
1184 * mcast frame, so it can clear the more-data bit in it. */
1185 b43_shm_write16(ring
->dev
, B43_SHM_SHARED
,
1186 B43_SHM_SH_MCASTCOOKIE
, cookie
);
1188 /* Now transfer the whole frame. */
1190 ops
->poke_tx(ring
, next_slot(ring
, slot
));
1194 dev_kfree_skb_any(skb
);
1196 unmap_descbuffer(ring
, meta_hdr
->dmaaddr
,
1201 static inline int should_inject_overflow(struct b43_dmaring
*ring
)
1203 #ifdef CONFIG_B43_DEBUG
1204 if (unlikely(b43_debug(ring
->dev
, B43_DBG_DMAOVERFLOW
))) {
1205 /* Check if we should inject another ringbuffer overflow
1206 * to test handling of this situation in the stack. */
1207 unsigned long next_overflow
;
1209 next_overflow
= ring
->last_injected_overflow
+ HZ
;
1210 if (time_after(jiffies
, next_overflow
)) {
1211 ring
->last_injected_overflow
= jiffies
;
1212 b43dbg(ring
->dev
->wl
,
1213 "Injecting TX ring overflow on "
1214 "DMA controller %d\n", ring
->index
);
1218 #endif /* CONFIG_B43_DEBUG */
1222 /* Static mapping of mac80211's queues (priorities) to b43 DMA rings. */
1223 static struct b43_dmaring
* select_ring_by_priority(struct b43_wldev
*dev
,
1226 struct b43_dmaring
*ring
;
1228 if (b43_modparam_qos
) {
1229 /* 0 = highest priority */
1230 switch (queue_prio
) {
1235 ring
= dev
->dma
.tx_ring_AC_VO
;
1238 ring
= dev
->dma
.tx_ring_AC_VI
;
1241 ring
= dev
->dma
.tx_ring_AC_BE
;
1244 ring
= dev
->dma
.tx_ring_AC_BK
;
1248 ring
= dev
->dma
.tx_ring_AC_BE
;
1253 int b43_dma_tx(struct b43_wldev
*dev
,
1254 struct sk_buff
*skb
, struct ieee80211_tx_control
*ctl
)
1256 struct b43_dmaring
*ring
;
1257 struct ieee80211_hdr
*hdr
;
1259 unsigned long flags
;
1261 hdr
= (struct ieee80211_hdr
*)skb
->data
;
1262 if (ctl
->flags
& IEEE80211_TXCTL_SEND_AFTER_DTIM
) {
1263 /* The multicast ring will be sent after the DTIM */
1264 ring
= dev
->dma
.tx_ring_mcast
;
1265 /* Set the more-data bit. Ucode will clear it on
1266 * the last frame for us. */
1267 hdr
->frame_control
|= cpu_to_le16(IEEE80211_FCTL_MOREDATA
);
1269 /* Decide by priority where to put this frame. */
1270 ring
= select_ring_by_priority(dev
, ctl
->queue
);
1273 spin_lock_irqsave(&ring
->lock
, flags
);
1274 B43_WARN_ON(!ring
->tx
);
1275 if (unlikely(free_slots(ring
) < SLOTS_PER_PACKET
)) {
1276 b43warn(dev
->wl
, "DMA queue overflow\n");
1280 /* Check if the queue was stopped in mac80211,
1281 * but we got called nevertheless.
1282 * That would be a mac80211 bug. */
1283 B43_WARN_ON(ring
->stopped
);
1285 /* Assign the queue number to the ring (if not already done before)
1286 * so TX status handling can use it. The queue to ring mapping is
1287 * static, so we don't need to store it per frame. */
1288 ring
->queue_prio
= ctl
->queue
;
1290 err
= dma_tx_fragment(ring
, skb
, ctl
);
1291 if (unlikely(err
== -ENOKEY
)) {
1292 /* Drop this packet, as we don't have the encryption key
1293 * anymore and must not transmit it unencrypted. */
1294 dev_kfree_skb_any(skb
);
1298 if (unlikely(err
)) {
1299 b43err(dev
->wl
, "DMA tx mapping failure\n");
1302 ring
->nr_tx_packets
++;
1303 if ((free_slots(ring
) < SLOTS_PER_PACKET
) ||
1304 should_inject_overflow(ring
)) {
1305 /* This TX ring is full. */
1306 ieee80211_stop_queue(dev
->wl
->hw
, ctl
->queue
);
1308 if (b43_debug(dev
, B43_DBG_DMAVERBOSE
)) {
1309 b43dbg(dev
->wl
, "Stopped TX ring %d\n", ring
->index
);
1313 spin_unlock_irqrestore(&ring
->lock
, flags
);
1318 /* Called with IRQs disabled. */
1319 void b43_dma_handle_txstatus(struct b43_wldev
*dev
,
1320 const struct b43_txstatus
*status
)
1322 const struct b43_dma_ops
*ops
;
1323 struct b43_dmaring
*ring
;
1324 struct b43_dmadesc_generic
*desc
;
1325 struct b43_dmadesc_meta
*meta
;
1329 ring
= parse_cookie(dev
, status
->cookie
, &slot
);
1330 if (unlikely(!ring
))
1333 spin_lock(&ring
->lock
); /* IRQs are already disabled. */
1335 B43_WARN_ON(!ring
->tx
);
1338 B43_WARN_ON(!(slot
>= 0 && slot
< ring
->nr_slots
));
1339 desc
= ops
->idx2desc(ring
, slot
, &meta
);
1342 unmap_descbuffer(ring
, meta
->dmaaddr
, meta
->skb
->len
,
1345 unmap_descbuffer(ring
, meta
->dmaaddr
,
1346 b43_txhdr_size(dev
), 1);
1348 if (meta
->is_last_fragment
) {
1349 B43_WARN_ON(!meta
->skb
);
1350 /* Call back to inform the ieee80211 subsystem about the
1351 * status of the transmission.
1352 * Some fields of txstat are already filled in dma_tx().
1354 frame_succeed
= b43_fill_txstatus_report(
1355 &(meta
->txstat
), status
);
1356 #ifdef CONFIG_B43_DEBUG
1358 ring
->nr_succeed_tx_packets
++;
1360 ring
->nr_failed_tx_packets
++;
1361 ring
->nr_total_packet_tries
+= status
->frame_count
;
1363 ieee80211_tx_status_irqsafe(dev
->wl
->hw
, meta
->skb
,
1365 /* skb is freed by ieee80211_tx_status_irqsafe() */
1368 /* No need to call free_descriptor_buffer here, as
1369 * this is only the txhdr, which is not allocated.
1371 B43_WARN_ON(meta
->skb
);
1374 /* Everything unmapped and free'd. So it's not used anymore. */
1377 if (meta
->is_last_fragment
)
1379 slot
= next_slot(ring
, slot
);
1381 dev
->stats
.last_tx
= jiffies
;
1382 if (ring
->stopped
) {
1383 B43_WARN_ON(free_slots(ring
) < SLOTS_PER_PACKET
);
1384 ieee80211_wake_queue(dev
->wl
->hw
, ring
->queue_prio
);
1386 if (b43_debug(dev
, B43_DBG_DMAVERBOSE
)) {
1387 b43dbg(dev
->wl
, "Woke up TX ring %d\n", ring
->index
);
1391 spin_unlock(&ring
->lock
);
1394 void b43_dma_get_tx_stats(struct b43_wldev
*dev
,
1395 struct ieee80211_tx_queue_stats
*stats
)
1397 const int nr_queues
= dev
->wl
->hw
->queues
;
1398 struct b43_dmaring
*ring
;
1399 struct ieee80211_tx_queue_stats_data
*data
;
1400 unsigned long flags
;
1403 for (i
= 0; i
< nr_queues
; i
++) {
1404 data
= &(stats
->data
[i
]);
1405 ring
= select_ring_by_priority(dev
, i
);
1407 spin_lock_irqsave(&ring
->lock
, flags
);
1408 data
->len
= ring
->used_slots
/ SLOTS_PER_PACKET
;
1409 data
->limit
= ring
->nr_slots
/ SLOTS_PER_PACKET
;
1410 data
->count
= ring
->nr_tx_packets
;
1411 spin_unlock_irqrestore(&ring
->lock
, flags
);
1415 static void dma_rx(struct b43_dmaring
*ring
, int *slot
)
1417 const struct b43_dma_ops
*ops
= ring
->ops
;
1418 struct b43_dmadesc_generic
*desc
;
1419 struct b43_dmadesc_meta
*meta
;
1420 struct b43_rxhdr_fw4
*rxhdr
;
1421 struct sk_buff
*skb
;
1426 desc
= ops
->idx2desc(ring
, *slot
, &meta
);
1428 sync_descbuffer_for_cpu(ring
, meta
->dmaaddr
, ring
->rx_buffersize
);
1431 rxhdr
= (struct b43_rxhdr_fw4
*)skb
->data
;
1432 len
= le16_to_cpu(rxhdr
->frame_len
);
1439 len
= le16_to_cpu(rxhdr
->frame_len
);
1440 } while (len
== 0 && i
++ < 5);
1441 if (unlikely(len
== 0)) {
1442 /* recycle the descriptor buffer. */
1443 sync_descbuffer_for_device(ring
, meta
->dmaaddr
,
1444 ring
->rx_buffersize
);
1448 if (unlikely(len
> ring
->rx_buffersize
)) {
1449 /* The data did not fit into one descriptor buffer
1450 * and is split over multiple buffers.
1451 * This should never happen, as we try to allocate buffers
1452 * big enough. So simply ignore this packet.
1458 desc
= ops
->idx2desc(ring
, *slot
, &meta
);
1459 /* recycle the descriptor buffer. */
1460 sync_descbuffer_for_device(ring
, meta
->dmaaddr
,
1461 ring
->rx_buffersize
);
1462 *slot
= next_slot(ring
, *slot
);
1464 tmp
-= ring
->rx_buffersize
;
1468 b43err(ring
->dev
->wl
, "DMA RX buffer too small "
1469 "(len: %u, buffer: %u, nr-dropped: %d)\n",
1470 len
, ring
->rx_buffersize
, cnt
);
1474 dmaaddr
= meta
->dmaaddr
;
1475 err
= setup_rx_descbuffer(ring
, desc
, meta
, GFP_ATOMIC
);
1476 if (unlikely(err
)) {
1477 b43dbg(ring
->dev
->wl
, "DMA RX: setup_rx_descbuffer() failed\n");
1478 sync_descbuffer_for_device(ring
, dmaaddr
, ring
->rx_buffersize
);
1482 unmap_descbuffer(ring
, dmaaddr
, ring
->rx_buffersize
, 0);
1483 skb_put(skb
, len
+ ring
->frameoffset
);
1484 skb_pull(skb
, ring
->frameoffset
);
1486 b43_rx(ring
->dev
, skb
, rxhdr
);
1491 void b43_dma_rx(struct b43_dmaring
*ring
)
1493 const struct b43_dma_ops
*ops
= ring
->ops
;
1494 int slot
, current_slot
;
1497 B43_WARN_ON(ring
->tx
);
1498 current_slot
= ops
->get_current_rxslot(ring
);
1499 B43_WARN_ON(!(current_slot
>= 0 && current_slot
< ring
->nr_slots
));
1501 slot
= ring
->current_slot
;
1502 for (; slot
!= current_slot
; slot
= next_slot(ring
, slot
)) {
1503 dma_rx(ring
, &slot
);
1504 update_max_used_slots(ring
, ++used_slots
);
1506 ops
->set_current_rxslot(ring
, slot
);
1507 ring
->current_slot
= slot
;
1510 static void b43_dma_tx_suspend_ring(struct b43_dmaring
*ring
)
1512 unsigned long flags
;
1514 spin_lock_irqsave(&ring
->lock
, flags
);
1515 B43_WARN_ON(!ring
->tx
);
1516 ring
->ops
->tx_suspend(ring
);
1517 spin_unlock_irqrestore(&ring
->lock
, flags
);
1520 static void b43_dma_tx_resume_ring(struct b43_dmaring
*ring
)
1522 unsigned long flags
;
1524 spin_lock_irqsave(&ring
->lock
, flags
);
1525 B43_WARN_ON(!ring
->tx
);
1526 ring
->ops
->tx_resume(ring
);
1527 spin_unlock_irqrestore(&ring
->lock
, flags
);
1530 void b43_dma_tx_suspend(struct b43_wldev
*dev
)
1532 b43_power_saving_ctl_bits(dev
, B43_PS_AWAKE
);
1533 b43_dma_tx_suspend_ring(dev
->dma
.tx_ring_AC_BK
);
1534 b43_dma_tx_suspend_ring(dev
->dma
.tx_ring_AC_BE
);
1535 b43_dma_tx_suspend_ring(dev
->dma
.tx_ring_AC_VI
);
1536 b43_dma_tx_suspend_ring(dev
->dma
.tx_ring_AC_VO
);
1537 b43_dma_tx_suspend_ring(dev
->dma
.tx_ring_mcast
);
1540 void b43_dma_tx_resume(struct b43_wldev
*dev
)
1542 b43_dma_tx_resume_ring(dev
->dma
.tx_ring_mcast
);
1543 b43_dma_tx_resume_ring(dev
->dma
.tx_ring_AC_VO
);
1544 b43_dma_tx_resume_ring(dev
->dma
.tx_ring_AC_VI
);
1545 b43_dma_tx_resume_ring(dev
->dma
.tx_ring_AC_BE
);
1546 b43_dma_tx_resume_ring(dev
->dma
.tx_ring_AC_BK
);
1547 b43_power_saving_ctl_bits(dev
, 0);
1550 #ifdef CONFIG_B43_PIO
1551 static void direct_fifo_rx(struct b43_wldev
*dev
, enum b43_dmatype type
,
1552 u16 mmio_base
, bool enable
)
1556 if (type
== B43_DMA_64BIT
) {
1557 ctl
= b43_read32(dev
, mmio_base
+ B43_DMA64_RXCTL
);
1558 ctl
&= ~B43_DMA64_RXDIRECTFIFO
;
1560 ctl
|= B43_DMA64_RXDIRECTFIFO
;
1561 b43_write32(dev
, mmio_base
+ B43_DMA64_RXCTL
, ctl
);
1563 ctl
= b43_read32(dev
, mmio_base
+ B43_DMA32_RXCTL
);
1564 ctl
&= ~B43_DMA32_RXDIRECTFIFO
;
1566 ctl
|= B43_DMA32_RXDIRECTFIFO
;
1567 b43_write32(dev
, mmio_base
+ B43_DMA32_RXCTL
, ctl
);
1571 /* Enable/Disable Direct FIFO Receive Mode (PIO) on a RX engine.
1572 * This is called from PIO code, so DMA structures are not available. */
1573 void b43_dma_direct_fifo_rx(struct b43_wldev
*dev
,
1574 unsigned int engine_index
, bool enable
)
1576 enum b43_dmatype type
;
1579 type
= dma_mask_to_engine_type(supported_dma_mask(dev
));
1581 mmio_base
= b43_dmacontroller_base(type
, engine_index
);
1582 direct_fifo_rx(dev
, type
, mmio_base
, enable
);
1584 #endif /* CONFIG_B43_PIO */