3 Broadcom B43 wireless driver
5 DMA ringbuffer and descriptor allocation/management
7 Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de>
9 Some code in this file is derived from the b44.c driver
10 Copyright (C) 2002 David S. Miller
11 Copyright (C) Pekka Pietikainen
13 This program is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 2 of the License, or
16 (at your option) any later version.
18 This program is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with this program; see the file COPYING. If not, write to
25 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
26 Boston, MA 02110-1301, USA.
36 #include <linux/dma-mapping.h>
37 #include <linux/pci.h>
38 #include <linux/delay.h>
39 #include <linux/skbuff.h>
40 #include <linux/etherdevice.h>
45 struct b43_dmadesc_generic
*op32_idx2desc(struct b43_dmaring
*ring
,
47 struct b43_dmadesc_meta
**meta
)
49 struct b43_dmadesc32
*desc
;
51 *meta
= &(ring
->meta
[slot
]);
52 desc
= ring
->descbase
;
55 return (struct b43_dmadesc_generic
*)desc
;
58 static void op32_fill_descriptor(struct b43_dmaring
*ring
,
59 struct b43_dmadesc_generic
*desc
,
60 dma_addr_t dmaaddr
, u16 bufsize
,
61 int start
, int end
, int irq
)
63 struct b43_dmadesc32
*descbase
= ring
->descbase
;
69 slot
= (int)(&(desc
->dma32
) - descbase
);
70 B43_WARN_ON(!(slot
>= 0 && slot
< ring
->nr_slots
));
72 addr
= (u32
) (dmaaddr
& ~SSB_DMA_TRANSLATION_MASK
);
73 addrext
= (u32
) (dmaaddr
& SSB_DMA_TRANSLATION_MASK
)
74 >> SSB_DMA_TRANSLATION_SHIFT
;
75 addr
|= ssb_dma_translation(ring
->dev
->dev
);
76 ctl
= (bufsize
- ring
->frameoffset
)
77 & B43_DMA32_DCTL_BYTECNT
;
78 if (slot
== ring
->nr_slots
- 1)
79 ctl
|= B43_DMA32_DCTL_DTABLEEND
;
81 ctl
|= B43_DMA32_DCTL_FRAMESTART
;
83 ctl
|= B43_DMA32_DCTL_FRAMEEND
;
85 ctl
|= B43_DMA32_DCTL_IRQ
;
86 ctl
|= (addrext
<< B43_DMA32_DCTL_ADDREXT_SHIFT
)
87 & B43_DMA32_DCTL_ADDREXT_MASK
;
89 desc
->dma32
.control
= cpu_to_le32(ctl
);
90 desc
->dma32
.address
= cpu_to_le32(addr
);
93 static void op32_poke_tx(struct b43_dmaring
*ring
, int slot
)
95 b43_dma_write(ring
, B43_DMA32_TXINDEX
,
96 (u32
) (slot
* sizeof(struct b43_dmadesc32
)));
99 static void op32_tx_suspend(struct b43_dmaring
*ring
)
101 b43_dma_write(ring
, B43_DMA32_TXCTL
, b43_dma_read(ring
, B43_DMA32_TXCTL
)
102 | B43_DMA32_TXSUSPEND
);
105 static void op32_tx_resume(struct b43_dmaring
*ring
)
107 b43_dma_write(ring
, B43_DMA32_TXCTL
, b43_dma_read(ring
, B43_DMA32_TXCTL
)
108 & ~B43_DMA32_TXSUSPEND
);
111 static int op32_get_current_rxslot(struct b43_dmaring
*ring
)
115 val
= b43_dma_read(ring
, B43_DMA32_RXSTATUS
);
116 val
&= B43_DMA32_RXDPTR
;
118 return (val
/ sizeof(struct b43_dmadesc32
));
121 static void op32_set_current_rxslot(struct b43_dmaring
*ring
, int slot
)
123 b43_dma_write(ring
, B43_DMA32_RXINDEX
,
124 (u32
) (slot
* sizeof(struct b43_dmadesc32
)));
127 static const struct b43_dma_ops dma32_ops
= {
128 .idx2desc
= op32_idx2desc
,
129 .fill_descriptor
= op32_fill_descriptor
,
130 .poke_tx
= op32_poke_tx
,
131 .tx_suspend
= op32_tx_suspend
,
132 .tx_resume
= op32_tx_resume
,
133 .get_current_rxslot
= op32_get_current_rxslot
,
134 .set_current_rxslot
= op32_set_current_rxslot
,
139 struct b43_dmadesc_generic
*op64_idx2desc(struct b43_dmaring
*ring
,
141 struct b43_dmadesc_meta
**meta
)
143 struct b43_dmadesc64
*desc
;
145 *meta
= &(ring
->meta
[slot
]);
146 desc
= ring
->descbase
;
147 desc
= &(desc
[slot
]);
149 return (struct b43_dmadesc_generic
*)desc
;
152 static void op64_fill_descriptor(struct b43_dmaring
*ring
,
153 struct b43_dmadesc_generic
*desc
,
154 dma_addr_t dmaaddr
, u16 bufsize
,
155 int start
, int end
, int irq
)
157 struct b43_dmadesc64
*descbase
= ring
->descbase
;
159 u32 ctl0
= 0, ctl1
= 0;
163 slot
= (int)(&(desc
->dma64
) - descbase
);
164 B43_WARN_ON(!(slot
>= 0 && slot
< ring
->nr_slots
));
166 addrlo
= (u32
) (dmaaddr
& 0xFFFFFFFF);
167 addrhi
= (((u64
) dmaaddr
>> 32) & ~SSB_DMA_TRANSLATION_MASK
);
168 addrext
= (((u64
) dmaaddr
>> 32) & SSB_DMA_TRANSLATION_MASK
)
169 >> SSB_DMA_TRANSLATION_SHIFT
;
170 addrhi
|= (ssb_dma_translation(ring
->dev
->dev
) << 1);
171 if (slot
== ring
->nr_slots
- 1)
172 ctl0
|= B43_DMA64_DCTL0_DTABLEEND
;
174 ctl0
|= B43_DMA64_DCTL0_FRAMESTART
;
176 ctl0
|= B43_DMA64_DCTL0_FRAMEEND
;
178 ctl0
|= B43_DMA64_DCTL0_IRQ
;
179 ctl1
|= (bufsize
- ring
->frameoffset
)
180 & B43_DMA64_DCTL1_BYTECNT
;
181 ctl1
|= (addrext
<< B43_DMA64_DCTL1_ADDREXT_SHIFT
)
182 & B43_DMA64_DCTL1_ADDREXT_MASK
;
184 desc
->dma64
.control0
= cpu_to_le32(ctl0
);
185 desc
->dma64
.control1
= cpu_to_le32(ctl1
);
186 desc
->dma64
.address_low
= cpu_to_le32(addrlo
);
187 desc
->dma64
.address_high
= cpu_to_le32(addrhi
);
190 static void op64_poke_tx(struct b43_dmaring
*ring
, int slot
)
192 b43_dma_write(ring
, B43_DMA64_TXINDEX
,
193 (u32
) (slot
* sizeof(struct b43_dmadesc64
)));
196 static void op64_tx_suspend(struct b43_dmaring
*ring
)
198 b43_dma_write(ring
, B43_DMA64_TXCTL
, b43_dma_read(ring
, B43_DMA64_TXCTL
)
199 | B43_DMA64_TXSUSPEND
);
202 static void op64_tx_resume(struct b43_dmaring
*ring
)
204 b43_dma_write(ring
, B43_DMA64_TXCTL
, b43_dma_read(ring
, B43_DMA64_TXCTL
)
205 & ~B43_DMA64_TXSUSPEND
);
208 static int op64_get_current_rxslot(struct b43_dmaring
*ring
)
212 val
= b43_dma_read(ring
, B43_DMA64_RXSTATUS
);
213 val
&= B43_DMA64_RXSTATDPTR
;
215 return (val
/ sizeof(struct b43_dmadesc64
));
218 static void op64_set_current_rxslot(struct b43_dmaring
*ring
, int slot
)
220 b43_dma_write(ring
, B43_DMA64_RXINDEX
,
221 (u32
) (slot
* sizeof(struct b43_dmadesc64
)));
224 static const struct b43_dma_ops dma64_ops
= {
225 .idx2desc
= op64_idx2desc
,
226 .fill_descriptor
= op64_fill_descriptor
,
227 .poke_tx
= op64_poke_tx
,
228 .tx_suspend
= op64_tx_suspend
,
229 .tx_resume
= op64_tx_resume
,
230 .get_current_rxslot
= op64_get_current_rxslot
,
231 .set_current_rxslot
= op64_set_current_rxslot
,
234 static inline int free_slots(struct b43_dmaring
*ring
)
236 return (ring
->nr_slots
- ring
->used_slots
);
239 static inline int next_slot(struct b43_dmaring
*ring
, int slot
)
241 B43_WARN_ON(!(slot
>= -1 && slot
<= ring
->nr_slots
- 1));
242 if (slot
== ring
->nr_slots
- 1)
247 static inline int prev_slot(struct b43_dmaring
*ring
, int slot
)
249 B43_WARN_ON(!(slot
>= 0 && slot
<= ring
->nr_slots
- 1));
251 return ring
->nr_slots
- 1;
255 #ifdef CONFIG_B43_DEBUG
256 static void update_max_used_slots(struct b43_dmaring
*ring
,
257 int current_used_slots
)
259 if (current_used_slots
<= ring
->max_used_slots
)
261 ring
->max_used_slots
= current_used_slots
;
262 if (b43_debug(ring
->dev
, B43_DBG_DMAVERBOSE
)) {
263 b43dbg(ring
->dev
->wl
,
264 "max_used_slots increased to %d on %s ring %d\n",
265 ring
->max_used_slots
,
266 ring
->tx
? "TX" : "RX", ring
->index
);
271 void update_max_used_slots(struct b43_dmaring
*ring
, int current_used_slots
)
276 /* Request a slot for usage. */
277 static inline int request_slot(struct b43_dmaring
*ring
)
281 B43_WARN_ON(!ring
->tx
);
282 B43_WARN_ON(ring
->stopped
);
283 B43_WARN_ON(free_slots(ring
) == 0);
285 slot
= next_slot(ring
, ring
->current_slot
);
286 ring
->current_slot
= slot
;
289 update_max_used_slots(ring
, ring
->used_slots
);
294 /* Mac80211-queue to b43-ring mapping */
295 static struct b43_dmaring
*priority_to_txring(struct b43_wldev
*dev
,
298 struct b43_dmaring
*ring
;
300 /*FIXME: For now we always run on TX-ring-1 */
301 return dev
->dma
.tx_ring1
;
303 /* 0 = highest priority */
304 switch (queue_priority
) {
309 ring
= dev
->dma
.tx_ring3
;
312 ring
= dev
->dma
.tx_ring2
;
315 ring
= dev
->dma
.tx_ring1
;
318 ring
= dev
->dma
.tx_ring0
;
325 /* b43-ring to mac80211-queue mapping */
326 static inline int txring_to_priority(struct b43_dmaring
*ring
)
328 static const u8 idx_to_prio
[] = { 3, 2, 1, 0, };
331 /*FIXME: have only one queue, for now */
335 if (B43_WARN_ON(index
>= ARRAY_SIZE(idx_to_prio
)))
337 return idx_to_prio
[index
];
340 static u16
b43_dmacontroller_base(enum b43_dmatype type
, int controller_idx
)
342 static const u16 map64
[] = {
343 B43_MMIO_DMA64_BASE0
,
344 B43_MMIO_DMA64_BASE1
,
345 B43_MMIO_DMA64_BASE2
,
346 B43_MMIO_DMA64_BASE3
,
347 B43_MMIO_DMA64_BASE4
,
348 B43_MMIO_DMA64_BASE5
,
350 static const u16 map32
[] = {
351 B43_MMIO_DMA32_BASE0
,
352 B43_MMIO_DMA32_BASE1
,
353 B43_MMIO_DMA32_BASE2
,
354 B43_MMIO_DMA32_BASE3
,
355 B43_MMIO_DMA32_BASE4
,
356 B43_MMIO_DMA32_BASE5
,
359 if (type
== B43_DMA_64BIT
) {
360 B43_WARN_ON(!(controller_idx
>= 0 &&
361 controller_idx
< ARRAY_SIZE(map64
)));
362 return map64
[controller_idx
];
364 B43_WARN_ON(!(controller_idx
>= 0 &&
365 controller_idx
< ARRAY_SIZE(map32
)));
366 return map32
[controller_idx
];
370 dma_addr_t
map_descbuffer(struct b43_dmaring
*ring
,
371 unsigned char *buf
, size_t len
, int tx
)
376 dmaaddr
= dma_map_single(ring
->dev
->dev
->dev
,
377 buf
, len
, DMA_TO_DEVICE
);
379 dmaaddr
= dma_map_single(ring
->dev
->dev
->dev
,
380 buf
, len
, DMA_FROM_DEVICE
);
387 void unmap_descbuffer(struct b43_dmaring
*ring
,
388 dma_addr_t addr
, size_t len
, int tx
)
391 dma_unmap_single(ring
->dev
->dev
->dev
, addr
, len
, DMA_TO_DEVICE
);
393 dma_unmap_single(ring
->dev
->dev
->dev
,
394 addr
, len
, DMA_FROM_DEVICE
);
399 void sync_descbuffer_for_cpu(struct b43_dmaring
*ring
,
400 dma_addr_t addr
, size_t len
)
402 B43_WARN_ON(ring
->tx
);
403 dma_sync_single_for_cpu(ring
->dev
->dev
->dev
,
404 addr
, len
, DMA_FROM_DEVICE
);
408 void sync_descbuffer_for_device(struct b43_dmaring
*ring
,
409 dma_addr_t addr
, size_t len
)
411 B43_WARN_ON(ring
->tx
);
412 dma_sync_single_for_device(ring
->dev
->dev
->dev
,
413 addr
, len
, DMA_FROM_DEVICE
);
417 void free_descriptor_buffer(struct b43_dmaring
*ring
,
418 struct b43_dmadesc_meta
*meta
)
421 dev_kfree_skb_any(meta
->skb
);
426 static int alloc_ringmemory(struct b43_dmaring
*ring
)
428 struct device
*dev
= ring
->dev
->dev
->dev
;
429 gfp_t flags
= GFP_KERNEL
;
431 /* The specs call for 4K buffers for 30- and 32-bit DMA with 4K
432 * alignment and 8K buffers for 64-bit DMA with 8K alignment. Testing
433 * has shown that 4K is sufficient for the latter as long as the buffer
434 * does not cross an 8K boundary.
436 * For unknown reasons - possibly a hardware error - the BCM4311 rev
437 * 02, which uses 64-bit DMA, needs the ring buffer in very low memory,
438 * which accounts for the GFP_DMA flag below.
440 if (ring
->type
== B43_DMA_64BIT
)
442 ring
->descbase
= dma_alloc_coherent(dev
, B43_DMA_RINGMEMSIZE
,
443 &(ring
->dmabase
), flags
);
444 if (!ring
->descbase
) {
445 b43err(ring
->dev
->wl
, "DMA ringmemory allocation failed\n");
448 memset(ring
->descbase
, 0, B43_DMA_RINGMEMSIZE
);
453 static void free_ringmemory(struct b43_dmaring
*ring
)
455 struct device
*dev
= ring
->dev
->dev
->dev
;
457 dma_free_coherent(dev
, B43_DMA_RINGMEMSIZE
,
458 ring
->descbase
, ring
->dmabase
);
461 /* Reset the RX DMA channel */
462 static int b43_dmacontroller_rx_reset(struct b43_wldev
*dev
, u16 mmio_base
,
463 enum b43_dmatype type
)
471 offset
= (type
== B43_DMA_64BIT
) ? B43_DMA64_RXCTL
: B43_DMA32_RXCTL
;
472 b43_write32(dev
, mmio_base
+ offset
, 0);
473 for (i
= 0; i
< 10; i
++) {
474 offset
= (type
== B43_DMA_64BIT
) ? B43_DMA64_RXSTATUS
:
476 value
= b43_read32(dev
, mmio_base
+ offset
);
477 if (type
== B43_DMA_64BIT
) {
478 value
&= B43_DMA64_RXSTAT
;
479 if (value
== B43_DMA64_RXSTAT_DISABLED
) {
484 value
&= B43_DMA32_RXSTATE
;
485 if (value
== B43_DMA32_RXSTAT_DISABLED
) {
493 b43err(dev
->wl
, "DMA RX reset timed out\n");
500 /* Reset the TX DMA channel */
501 static int b43_dmacontroller_tx_reset(struct b43_wldev
*dev
, u16 mmio_base
,
502 enum b43_dmatype type
)
510 for (i
= 0; i
< 10; i
++) {
511 offset
= (type
== B43_DMA_64BIT
) ? B43_DMA64_TXSTATUS
:
513 value
= b43_read32(dev
, mmio_base
+ offset
);
514 if (type
== B43_DMA_64BIT
) {
515 value
&= B43_DMA64_TXSTAT
;
516 if (value
== B43_DMA64_TXSTAT_DISABLED
||
517 value
== B43_DMA64_TXSTAT_IDLEWAIT
||
518 value
== B43_DMA64_TXSTAT_STOPPED
)
521 value
&= B43_DMA32_TXSTATE
;
522 if (value
== B43_DMA32_TXSTAT_DISABLED
||
523 value
== B43_DMA32_TXSTAT_IDLEWAIT
||
524 value
== B43_DMA32_TXSTAT_STOPPED
)
529 offset
= (type
== B43_DMA_64BIT
) ? B43_DMA64_TXCTL
: B43_DMA32_TXCTL
;
530 b43_write32(dev
, mmio_base
+ offset
, 0);
531 for (i
= 0; i
< 10; i
++) {
532 offset
= (type
== B43_DMA_64BIT
) ? B43_DMA64_TXSTATUS
:
534 value
= b43_read32(dev
, mmio_base
+ offset
);
535 if (type
== B43_DMA_64BIT
) {
536 value
&= B43_DMA64_TXSTAT
;
537 if (value
== B43_DMA64_TXSTAT_DISABLED
) {
542 value
&= B43_DMA32_TXSTATE
;
543 if (value
== B43_DMA32_TXSTAT_DISABLED
) {
551 b43err(dev
->wl
, "DMA TX reset timed out\n");
554 /* ensure the reset is completed. */
560 /* Check if a DMA mapping address is invalid. */
561 static bool b43_dma_mapping_error(struct b43_dmaring
*ring
,
563 size_t buffersize
, bool dma_to_device
)
565 if (unlikely(dma_mapping_error(addr
)))
568 switch (ring
->type
) {
570 if ((u64
)addr
+ buffersize
> (1ULL << 30))
574 if ((u64
)addr
+ buffersize
> (1ULL << 32))
578 /* Currently we can't have addresses beyond
579 * 64bit in the kernel. */
583 /* The address is OK. */
587 /* We can't support this address. Unmap it again. */
588 unmap_descbuffer(ring
, addr
, buffersize
, dma_to_device
);
593 static int setup_rx_descbuffer(struct b43_dmaring
*ring
,
594 struct b43_dmadesc_generic
*desc
,
595 struct b43_dmadesc_meta
*meta
, gfp_t gfp_flags
)
597 struct b43_rxhdr_fw4
*rxhdr
;
598 struct b43_hwtxstatus
*txstat
;
602 B43_WARN_ON(ring
->tx
);
604 skb
= __dev_alloc_skb(ring
->rx_buffersize
, gfp_flags
);
607 dmaaddr
= map_descbuffer(ring
, skb
->data
, ring
->rx_buffersize
, 0);
608 if (b43_dma_mapping_error(ring
, dmaaddr
, ring
->rx_buffersize
, 0)) {
609 /* ugh. try to realloc in zone_dma */
610 gfp_flags
|= GFP_DMA
;
612 dev_kfree_skb_any(skb
);
614 skb
= __dev_alloc_skb(ring
->rx_buffersize
, gfp_flags
);
617 dmaaddr
= map_descbuffer(ring
, skb
->data
,
618 ring
->rx_buffersize
, 0);
621 if (b43_dma_mapping_error(ring
, dmaaddr
, ring
->rx_buffersize
, 0)) {
622 dev_kfree_skb_any(skb
);
627 meta
->dmaaddr
= dmaaddr
;
628 ring
->ops
->fill_descriptor(ring
, desc
, dmaaddr
,
629 ring
->rx_buffersize
, 0, 0, 0);
631 rxhdr
= (struct b43_rxhdr_fw4
*)(skb
->data
);
632 rxhdr
->frame_len
= 0;
633 txstat
= (struct b43_hwtxstatus
*)(skb
->data
);
639 /* Allocate the initial descbuffers.
640 * This is used for an RX ring only.
642 static int alloc_initial_descbuffers(struct b43_dmaring
*ring
)
644 int i
, err
= -ENOMEM
;
645 struct b43_dmadesc_generic
*desc
;
646 struct b43_dmadesc_meta
*meta
;
648 for (i
= 0; i
< ring
->nr_slots
; i
++) {
649 desc
= ring
->ops
->idx2desc(ring
, i
, &meta
);
651 err
= setup_rx_descbuffer(ring
, desc
, meta
, GFP_KERNEL
);
653 b43err(ring
->dev
->wl
,
654 "Failed to allocate initial descbuffers\n");
659 ring
->used_slots
= ring
->nr_slots
;
665 for (i
--; i
>= 0; i
--) {
666 desc
= ring
->ops
->idx2desc(ring
, i
, &meta
);
668 unmap_descbuffer(ring
, meta
->dmaaddr
, ring
->rx_buffersize
, 0);
669 dev_kfree_skb(meta
->skb
);
674 /* Do initial setup of the DMA controller.
675 * Reset the controller, write the ring busaddress
676 * and switch the "enable" bit on.
678 static int dmacontroller_setup(struct b43_dmaring
*ring
)
683 u32 trans
= ssb_dma_translation(ring
->dev
->dev
);
686 if (ring
->type
== B43_DMA_64BIT
) {
687 u64 ringbase
= (u64
) (ring
->dmabase
);
689 addrext
= ((ringbase
>> 32) & SSB_DMA_TRANSLATION_MASK
)
690 >> SSB_DMA_TRANSLATION_SHIFT
;
691 value
= B43_DMA64_TXENABLE
;
692 value
|= (addrext
<< B43_DMA64_TXADDREXT_SHIFT
)
693 & B43_DMA64_TXADDREXT_MASK
;
694 b43_dma_write(ring
, B43_DMA64_TXCTL
, value
);
695 b43_dma_write(ring
, B43_DMA64_TXRINGLO
,
696 (ringbase
& 0xFFFFFFFF));
697 b43_dma_write(ring
, B43_DMA64_TXRINGHI
,
699 ~SSB_DMA_TRANSLATION_MASK
)
702 u32 ringbase
= (u32
) (ring
->dmabase
);
704 addrext
= (ringbase
& SSB_DMA_TRANSLATION_MASK
)
705 >> SSB_DMA_TRANSLATION_SHIFT
;
706 value
= B43_DMA32_TXENABLE
;
707 value
|= (addrext
<< B43_DMA32_TXADDREXT_SHIFT
)
708 & B43_DMA32_TXADDREXT_MASK
;
709 b43_dma_write(ring
, B43_DMA32_TXCTL
, value
);
710 b43_dma_write(ring
, B43_DMA32_TXRING
,
711 (ringbase
& ~SSB_DMA_TRANSLATION_MASK
)
715 err
= alloc_initial_descbuffers(ring
);
718 if (ring
->type
== B43_DMA_64BIT
) {
719 u64 ringbase
= (u64
) (ring
->dmabase
);
721 addrext
= ((ringbase
>> 32) & SSB_DMA_TRANSLATION_MASK
)
722 >> SSB_DMA_TRANSLATION_SHIFT
;
723 value
= (ring
->frameoffset
<< B43_DMA64_RXFROFF_SHIFT
);
724 value
|= B43_DMA64_RXENABLE
;
725 value
|= (addrext
<< B43_DMA64_RXADDREXT_SHIFT
)
726 & B43_DMA64_RXADDREXT_MASK
;
727 b43_dma_write(ring
, B43_DMA64_RXCTL
, value
);
728 b43_dma_write(ring
, B43_DMA64_RXRINGLO
,
729 (ringbase
& 0xFFFFFFFF));
730 b43_dma_write(ring
, B43_DMA64_RXRINGHI
,
732 ~SSB_DMA_TRANSLATION_MASK
)
734 b43_dma_write(ring
, B43_DMA64_RXINDEX
, ring
->nr_slots
*
735 sizeof(struct b43_dmadesc64
));
737 u32 ringbase
= (u32
) (ring
->dmabase
);
739 addrext
= (ringbase
& SSB_DMA_TRANSLATION_MASK
)
740 >> SSB_DMA_TRANSLATION_SHIFT
;
741 value
= (ring
->frameoffset
<< B43_DMA32_RXFROFF_SHIFT
);
742 value
|= B43_DMA32_RXENABLE
;
743 value
|= (addrext
<< B43_DMA32_RXADDREXT_SHIFT
)
744 & B43_DMA32_RXADDREXT_MASK
;
745 b43_dma_write(ring
, B43_DMA32_RXCTL
, value
);
746 b43_dma_write(ring
, B43_DMA32_RXRING
,
747 (ringbase
& ~SSB_DMA_TRANSLATION_MASK
)
749 b43_dma_write(ring
, B43_DMA32_RXINDEX
, ring
->nr_slots
*
750 sizeof(struct b43_dmadesc32
));
758 /* Shutdown the DMA controller. */
759 static void dmacontroller_cleanup(struct b43_dmaring
*ring
)
762 b43_dmacontroller_tx_reset(ring
->dev
, ring
->mmio_base
,
764 if (ring
->type
== B43_DMA_64BIT
) {
765 b43_dma_write(ring
, B43_DMA64_TXRINGLO
, 0);
766 b43_dma_write(ring
, B43_DMA64_TXRINGHI
, 0);
768 b43_dma_write(ring
, B43_DMA32_TXRING
, 0);
770 b43_dmacontroller_rx_reset(ring
->dev
, ring
->mmio_base
,
772 if (ring
->type
== B43_DMA_64BIT
) {
773 b43_dma_write(ring
, B43_DMA64_RXRINGLO
, 0);
774 b43_dma_write(ring
, B43_DMA64_RXRINGHI
, 0);
776 b43_dma_write(ring
, B43_DMA32_RXRING
, 0);
780 static void free_all_descbuffers(struct b43_dmaring
*ring
)
782 struct b43_dmadesc_generic
*desc
;
783 struct b43_dmadesc_meta
*meta
;
786 if (!ring
->used_slots
)
788 for (i
= 0; i
< ring
->nr_slots
; i
++) {
789 desc
= ring
->ops
->idx2desc(ring
, i
, &meta
);
792 B43_WARN_ON(!ring
->tx
);
796 unmap_descbuffer(ring
, meta
->dmaaddr
,
799 unmap_descbuffer(ring
, meta
->dmaaddr
,
800 ring
->rx_buffersize
, 0);
802 free_descriptor_buffer(ring
, meta
);
806 static u64
supported_dma_mask(struct b43_wldev
*dev
)
811 tmp
= b43_read32(dev
, SSB_TMSHIGH
);
812 if (tmp
& SSB_TMSHIGH_DMA64
)
813 return DMA_64BIT_MASK
;
814 mmio_base
= b43_dmacontroller_base(0, 0);
815 b43_write32(dev
, mmio_base
+ B43_DMA32_TXCTL
, B43_DMA32_TXADDREXT_MASK
);
816 tmp
= b43_read32(dev
, mmio_base
+ B43_DMA32_TXCTL
);
817 if (tmp
& B43_DMA32_TXADDREXT_MASK
)
818 return DMA_32BIT_MASK
;
820 return DMA_30BIT_MASK
;
823 /* Main initialization function. */
825 struct b43_dmaring
*b43_setup_dmaring(struct b43_wldev
*dev
,
826 int controller_index
,
828 enum b43_dmatype type
)
830 struct b43_dmaring
*ring
;
835 ring
= kzalloc(sizeof(*ring
), GFP_KERNEL
);
840 nr_slots
= B43_RXRING_SLOTS
;
842 nr_slots
= B43_TXRING_SLOTS
;
844 ring
->meta
= kcalloc(nr_slots
, sizeof(struct b43_dmadesc_meta
),
849 ring
->txhdr_cache
= kcalloc(nr_slots
,
852 if (!ring
->txhdr_cache
)
855 /* test for ability to dma to txhdr_cache */
856 dma_test
= dma_map_single(dev
->dev
->dev
,
861 if (b43_dma_mapping_error(ring
, dma_test
,
862 b43_txhdr_size(dev
), 1)) {
864 kfree(ring
->txhdr_cache
);
865 ring
->txhdr_cache
= kcalloc(nr_slots
,
867 GFP_KERNEL
| GFP_DMA
);
868 if (!ring
->txhdr_cache
)
871 dma_test
= dma_map_single(dev
->dev
->dev
,
876 if (b43_dma_mapping_error(ring
, dma_test
,
877 b43_txhdr_size(dev
), 1))
878 goto err_kfree_txhdr_cache
;
881 dma_unmap_single(dev
->dev
->dev
,
882 dma_test
, b43_txhdr_size(dev
),
887 ring
->nr_slots
= nr_slots
;
888 ring
->mmio_base
= b43_dmacontroller_base(type
, controller_index
);
889 ring
->index
= controller_index
;
890 if (type
== B43_DMA_64BIT
)
891 ring
->ops
= &dma64_ops
;
893 ring
->ops
= &dma32_ops
;
896 ring
->current_slot
= -1;
898 if (ring
->index
== 0) {
899 ring
->rx_buffersize
= B43_DMA0_RX_BUFFERSIZE
;
900 ring
->frameoffset
= B43_DMA0_RX_FRAMEOFFSET
;
901 } else if (ring
->index
== 3) {
902 ring
->rx_buffersize
= B43_DMA3_RX_BUFFERSIZE
;
903 ring
->frameoffset
= B43_DMA3_RX_FRAMEOFFSET
;
907 spin_lock_init(&ring
->lock
);
908 #ifdef CONFIG_B43_DEBUG
909 ring
->last_injected_overflow
= jiffies
;
912 err
= alloc_ringmemory(ring
);
914 goto err_kfree_txhdr_cache
;
915 err
= dmacontroller_setup(ring
);
917 goto err_free_ringmemory
;
923 free_ringmemory(ring
);
924 err_kfree_txhdr_cache
:
925 kfree(ring
->txhdr_cache
);
934 /* Main cleanup function. */
935 static void b43_destroy_dmaring(struct b43_dmaring
*ring
)
940 b43dbg(ring
->dev
->wl
, "DMA-%u 0x%04X (%s) max used slots: %d/%d\n",
941 (unsigned int)(ring
->type
),
943 (ring
->tx
) ? "TX" : "RX", ring
->max_used_slots
, ring
->nr_slots
);
944 /* Device IRQs are disabled prior entering this function,
945 * so no need to take care of concurrency with rx handler stuff.
947 dmacontroller_cleanup(ring
);
948 free_all_descbuffers(ring
);
949 free_ringmemory(ring
);
951 kfree(ring
->txhdr_cache
);
956 void b43_dma_free(struct b43_wldev
*dev
)
958 struct b43_dma
*dma
= &dev
->dma
;
960 b43_destroy_dmaring(dma
->rx_ring3
);
961 dma
->rx_ring3
= NULL
;
962 b43_destroy_dmaring(dma
->rx_ring0
);
963 dma
->rx_ring0
= NULL
;
965 b43_destroy_dmaring(dma
->tx_ring5
);
966 dma
->tx_ring5
= NULL
;
967 b43_destroy_dmaring(dma
->tx_ring4
);
968 dma
->tx_ring4
= NULL
;
969 b43_destroy_dmaring(dma
->tx_ring3
);
970 dma
->tx_ring3
= NULL
;
971 b43_destroy_dmaring(dma
->tx_ring2
);
972 dma
->tx_ring2
= NULL
;
973 b43_destroy_dmaring(dma
->tx_ring1
);
974 dma
->tx_ring1
= NULL
;
975 b43_destroy_dmaring(dma
->tx_ring0
);
976 dma
->tx_ring0
= NULL
;
979 int b43_dma_init(struct b43_wldev
*dev
)
981 struct b43_dma
*dma
= &dev
->dma
;
982 struct b43_dmaring
*ring
;
985 enum b43_dmatype type
;
987 dmamask
= supported_dma_mask(dev
);
992 type
= B43_DMA_30BIT
;
995 type
= B43_DMA_32BIT
;
998 type
= B43_DMA_64BIT
;
1001 err
= ssb_dma_set_mask(dev
->dev
, dmamask
);
1003 b43err(dev
->wl
, "The machine/kernel does not support "
1004 "the required DMA mask (0x%08X%08X)\n",
1005 (unsigned int)((dmamask
& 0xFFFFFFFF00000000ULL
) >> 32),
1006 (unsigned int)(dmamask
& 0x00000000FFFFFFFFULL
));
1011 /* setup TX DMA channels. */
1012 ring
= b43_setup_dmaring(dev
, 0, 1, type
);
1015 dma
->tx_ring0
= ring
;
1017 ring
= b43_setup_dmaring(dev
, 1, 1, type
);
1019 goto err_destroy_tx0
;
1020 dma
->tx_ring1
= ring
;
1022 ring
= b43_setup_dmaring(dev
, 2, 1, type
);
1024 goto err_destroy_tx1
;
1025 dma
->tx_ring2
= ring
;
1027 ring
= b43_setup_dmaring(dev
, 3, 1, type
);
1029 goto err_destroy_tx2
;
1030 dma
->tx_ring3
= ring
;
1032 ring
= b43_setup_dmaring(dev
, 4, 1, type
);
1034 goto err_destroy_tx3
;
1035 dma
->tx_ring4
= ring
;
1037 ring
= b43_setup_dmaring(dev
, 5, 1, type
);
1039 goto err_destroy_tx4
;
1040 dma
->tx_ring5
= ring
;
1042 /* setup RX DMA channels. */
1043 ring
= b43_setup_dmaring(dev
, 0, 0, type
);
1045 goto err_destroy_tx5
;
1046 dma
->rx_ring0
= ring
;
1048 if (dev
->dev
->id
.revision
< 5) {
1049 ring
= b43_setup_dmaring(dev
, 3, 0, type
);
1051 goto err_destroy_rx0
;
1052 dma
->rx_ring3
= ring
;
1055 b43dbg(dev
->wl
, "%u-bit DMA initialized\n",
1056 (unsigned int)type
);
1062 b43_destroy_dmaring(dma
->rx_ring0
);
1063 dma
->rx_ring0
= NULL
;
1065 b43_destroy_dmaring(dma
->tx_ring5
);
1066 dma
->tx_ring5
= NULL
;
1068 b43_destroy_dmaring(dma
->tx_ring4
);
1069 dma
->tx_ring4
= NULL
;
1071 b43_destroy_dmaring(dma
->tx_ring3
);
1072 dma
->tx_ring3
= NULL
;
1074 b43_destroy_dmaring(dma
->tx_ring2
);
1075 dma
->tx_ring2
= NULL
;
1077 b43_destroy_dmaring(dma
->tx_ring1
);
1078 dma
->tx_ring1
= NULL
;
1080 b43_destroy_dmaring(dma
->tx_ring0
);
1081 dma
->tx_ring0
= NULL
;
1085 /* Generate a cookie for the TX header. */
1086 static u16
generate_cookie(struct b43_dmaring
*ring
, int slot
)
1088 u16 cookie
= 0x1000;
1090 /* Use the upper 4 bits of the cookie as
1091 * DMA controller ID and store the slot number
1092 * in the lower 12 bits.
1093 * Note that the cookie must never be 0, as this
1094 * is a special value used in RX path.
1095 * It can also not be 0xFFFF because that is special
1096 * for multicast frames.
1098 switch (ring
->index
) {
1120 B43_WARN_ON(slot
& ~0x0FFF);
1121 cookie
|= (u16
) slot
;
1126 /* Inspect a cookie and find out to which controller/slot it belongs. */
1128 struct b43_dmaring
*parse_cookie(struct b43_wldev
*dev
, u16 cookie
, int *slot
)
1130 struct b43_dma
*dma
= &dev
->dma
;
1131 struct b43_dmaring
*ring
= NULL
;
1133 switch (cookie
& 0xF000) {
1135 ring
= dma
->tx_ring0
;
1138 ring
= dma
->tx_ring1
;
1141 ring
= dma
->tx_ring2
;
1144 ring
= dma
->tx_ring3
;
1147 ring
= dma
->tx_ring4
;
1150 ring
= dma
->tx_ring5
;
1155 *slot
= (cookie
& 0x0FFF);
1156 B43_WARN_ON(!(ring
&& *slot
>= 0 && *slot
< ring
->nr_slots
));
1161 static int dma_tx_fragment(struct b43_dmaring
*ring
,
1162 struct sk_buff
*skb
,
1163 struct ieee80211_tx_control
*ctl
)
1165 const struct b43_dma_ops
*ops
= ring
->ops
;
1167 int slot
, old_top_slot
, old_used_slots
;
1169 struct b43_dmadesc_generic
*desc
;
1170 struct b43_dmadesc_meta
*meta
;
1171 struct b43_dmadesc_meta
*meta_hdr
;
1172 struct sk_buff
*bounce_skb
;
1174 size_t hdrsize
= b43_txhdr_size(ring
->dev
);
1176 #define SLOTS_PER_PACKET 2
1177 B43_WARN_ON(skb_shinfo(skb
)->nr_frags
);
1179 old_top_slot
= ring
->current_slot
;
1180 old_used_slots
= ring
->used_slots
;
1182 /* Get a slot for the header. */
1183 slot
= request_slot(ring
);
1184 desc
= ops
->idx2desc(ring
, slot
, &meta_hdr
);
1185 memset(meta_hdr
, 0, sizeof(*meta_hdr
));
1187 header
= &(ring
->txhdr_cache
[slot
* hdrsize
]);
1188 cookie
= generate_cookie(ring
, slot
);
1189 err
= b43_generate_txhdr(ring
->dev
, header
,
1190 skb
->data
, skb
->len
, ctl
, cookie
);
1191 if (unlikely(err
)) {
1192 ring
->current_slot
= old_top_slot
;
1193 ring
->used_slots
= old_used_slots
;
1197 meta_hdr
->dmaaddr
= map_descbuffer(ring
, (unsigned char *)header
,
1199 if (b43_dma_mapping_error(ring
, meta_hdr
->dmaaddr
, hdrsize
, 1)) {
1200 ring
->current_slot
= old_top_slot
;
1201 ring
->used_slots
= old_used_slots
;
1204 ops
->fill_descriptor(ring
, desc
, meta_hdr
->dmaaddr
,
1207 /* Get a slot for the payload. */
1208 slot
= request_slot(ring
);
1209 desc
= ops
->idx2desc(ring
, slot
, &meta
);
1210 memset(meta
, 0, sizeof(*meta
));
1212 memcpy(&meta
->txstat
.control
, ctl
, sizeof(*ctl
));
1214 meta
->is_last_fragment
= 1;
1216 meta
->dmaaddr
= map_descbuffer(ring
, skb
->data
, skb
->len
, 1);
1217 /* create a bounce buffer in zone_dma on mapping failure. */
1218 if (b43_dma_mapping_error(ring
, meta
->dmaaddr
, skb
->len
, 1)) {
1219 bounce_skb
= __dev_alloc_skb(skb
->len
, GFP_ATOMIC
| GFP_DMA
);
1221 ring
->current_slot
= old_top_slot
;
1222 ring
->used_slots
= old_used_slots
;
1227 memcpy(skb_put(bounce_skb
, skb
->len
), skb
->data
, skb
->len
);
1228 dev_kfree_skb_any(skb
);
1231 meta
->dmaaddr
= map_descbuffer(ring
, skb
->data
, skb
->len
, 1);
1232 if (b43_dma_mapping_error(ring
, meta
->dmaaddr
, skb
->len
, 1)) {
1233 ring
->current_slot
= old_top_slot
;
1234 ring
->used_slots
= old_used_slots
;
1236 goto out_free_bounce
;
1240 ops
->fill_descriptor(ring
, desc
, meta
->dmaaddr
, skb
->len
, 0, 1, 1);
1242 if (ctl
->flags
& IEEE80211_TXCTL_SEND_AFTER_DTIM
) {
1243 /* Tell the firmware about the cookie of the last
1244 * mcast frame, so it can clear the more-data bit in it. */
1245 b43_shm_write16(ring
->dev
, B43_SHM_SHARED
,
1246 B43_SHM_SH_MCASTCOOKIE
, cookie
);
1248 /* Now transfer the whole frame. */
1250 ops
->poke_tx(ring
, next_slot(ring
, slot
));
1254 dev_kfree_skb_any(skb
);
1256 unmap_descbuffer(ring
, meta_hdr
->dmaaddr
,
1261 static inline int should_inject_overflow(struct b43_dmaring
*ring
)
1263 #ifdef CONFIG_B43_DEBUG
1264 if (unlikely(b43_debug(ring
->dev
, B43_DBG_DMAOVERFLOW
))) {
1265 /* Check if we should inject another ringbuffer overflow
1266 * to test handling of this situation in the stack. */
1267 unsigned long next_overflow
;
1269 next_overflow
= ring
->last_injected_overflow
+ HZ
;
1270 if (time_after(jiffies
, next_overflow
)) {
1271 ring
->last_injected_overflow
= jiffies
;
1272 b43dbg(ring
->dev
->wl
,
1273 "Injecting TX ring overflow on "
1274 "DMA controller %d\n", ring
->index
);
1278 #endif /* CONFIG_B43_DEBUG */
1282 int b43_dma_tx(struct b43_wldev
*dev
,
1283 struct sk_buff
*skb
, struct ieee80211_tx_control
*ctl
)
1285 struct b43_dmaring
*ring
;
1286 struct ieee80211_hdr
*hdr
;
1288 unsigned long flags
;
1290 if (unlikely(skb
->len
< 2 + 2 + 6)) {
1291 /* Too short, this can't be a valid frame. */
1295 hdr
= (struct ieee80211_hdr
*)skb
->data
;
1296 if (ctl
->flags
& IEEE80211_TXCTL_SEND_AFTER_DTIM
) {
1297 /* The multicast ring will be sent after the DTIM */
1298 ring
= dev
->dma
.tx_ring4
;
1299 /* Set the more-data bit. Ucode will clear it on
1300 * the last frame for us. */
1301 hdr
->frame_control
|= cpu_to_le16(IEEE80211_FCTL_MOREDATA
);
1303 /* Decide by priority where to put this frame. */
1304 ring
= priority_to_txring(dev
, ctl
->queue
);
1307 spin_lock_irqsave(&ring
->lock
, flags
);
1308 B43_WARN_ON(!ring
->tx
);
1309 if (unlikely(free_slots(ring
) < SLOTS_PER_PACKET
)) {
1310 b43warn(dev
->wl
, "DMA queue overflow\n");
1314 /* Check if the queue was stopped in mac80211,
1315 * but we got called nevertheless.
1316 * That would be a mac80211 bug. */
1317 B43_WARN_ON(ring
->stopped
);
1319 err
= dma_tx_fragment(ring
, skb
, ctl
);
1320 if (unlikely(err
== -ENOKEY
)) {
1321 /* Drop this packet, as we don't have the encryption key
1322 * anymore and must not transmit it unencrypted. */
1323 dev_kfree_skb_any(skb
);
1327 if (unlikely(err
)) {
1328 b43err(dev
->wl
, "DMA tx mapping failure\n");
1331 ring
->nr_tx_packets
++;
1332 if ((free_slots(ring
) < SLOTS_PER_PACKET
) ||
1333 should_inject_overflow(ring
)) {
1334 /* This TX ring is full. */
1335 ieee80211_stop_queue(dev
->wl
->hw
, txring_to_priority(ring
));
1337 if (b43_debug(dev
, B43_DBG_DMAVERBOSE
)) {
1338 b43dbg(dev
->wl
, "Stopped TX ring %d\n", ring
->index
);
1342 spin_unlock_irqrestore(&ring
->lock
, flags
);
1347 /* Called with IRQs disabled. */
1348 void b43_dma_handle_txstatus(struct b43_wldev
*dev
,
1349 const struct b43_txstatus
*status
)
1351 const struct b43_dma_ops
*ops
;
1352 struct b43_dmaring
*ring
;
1353 struct b43_dmadesc_generic
*desc
;
1354 struct b43_dmadesc_meta
*meta
;
1357 ring
= parse_cookie(dev
, status
->cookie
, &slot
);
1358 if (unlikely(!ring
))
1361 spin_lock(&ring
->lock
); /* IRQs are already disabled. */
1363 B43_WARN_ON(!ring
->tx
);
1366 B43_WARN_ON(!(slot
>= 0 && slot
< ring
->nr_slots
));
1367 desc
= ops
->idx2desc(ring
, slot
, &meta
);
1370 unmap_descbuffer(ring
, meta
->dmaaddr
, meta
->skb
->len
,
1373 unmap_descbuffer(ring
, meta
->dmaaddr
,
1374 b43_txhdr_size(dev
), 1);
1376 if (meta
->is_last_fragment
) {
1377 B43_WARN_ON(!meta
->skb
);
1378 /* Call back to inform the ieee80211 subsystem about the
1379 * status of the transmission.
1380 * Some fields of txstat are already filled in dma_tx().
1382 if (status
->acked
) {
1383 meta
->txstat
.flags
|= IEEE80211_TX_STATUS_ACK
;
1385 if (!(meta
->txstat
.control
.flags
1386 & IEEE80211_TXCTL_NO_ACK
))
1387 meta
->txstat
.excessive_retries
= 1;
1389 if (status
->frame_count
== 0) {
1390 /* The frame was not transmitted at all. */
1391 meta
->txstat
.retry_count
= 0;
1393 meta
->txstat
.retry_count
= status
->frame_count
- 1;
1394 ieee80211_tx_status_irqsafe(dev
->wl
->hw
, meta
->skb
,
1396 /* skb is freed by ieee80211_tx_status_irqsafe() */
1399 /* No need to call free_descriptor_buffer here, as
1400 * this is only the txhdr, which is not allocated.
1402 B43_WARN_ON(meta
->skb
);
1405 /* Everything unmapped and free'd. So it's not used anymore. */
1408 if (meta
->is_last_fragment
)
1410 slot
= next_slot(ring
, slot
);
1412 dev
->stats
.last_tx
= jiffies
;
1413 if (ring
->stopped
) {
1414 B43_WARN_ON(free_slots(ring
) < SLOTS_PER_PACKET
);
1415 ieee80211_wake_queue(dev
->wl
->hw
, txring_to_priority(ring
));
1417 if (b43_debug(dev
, B43_DBG_DMAVERBOSE
)) {
1418 b43dbg(dev
->wl
, "Woke up TX ring %d\n", ring
->index
);
1422 spin_unlock(&ring
->lock
);
1425 void b43_dma_get_tx_stats(struct b43_wldev
*dev
,
1426 struct ieee80211_tx_queue_stats
*stats
)
1428 const int nr_queues
= dev
->wl
->hw
->queues
;
1429 struct b43_dmaring
*ring
;
1430 struct ieee80211_tx_queue_stats_data
*data
;
1431 unsigned long flags
;
1434 for (i
= 0; i
< nr_queues
; i
++) {
1435 data
= &(stats
->data
[i
]);
1436 ring
= priority_to_txring(dev
, i
);
1438 spin_lock_irqsave(&ring
->lock
, flags
);
1439 data
->len
= ring
->used_slots
/ SLOTS_PER_PACKET
;
1440 data
->limit
= ring
->nr_slots
/ SLOTS_PER_PACKET
;
1441 data
->count
= ring
->nr_tx_packets
;
1442 spin_unlock_irqrestore(&ring
->lock
, flags
);
1446 static void dma_rx(struct b43_dmaring
*ring
, int *slot
)
1448 const struct b43_dma_ops
*ops
= ring
->ops
;
1449 struct b43_dmadesc_generic
*desc
;
1450 struct b43_dmadesc_meta
*meta
;
1451 struct b43_rxhdr_fw4
*rxhdr
;
1452 struct sk_buff
*skb
;
1457 desc
= ops
->idx2desc(ring
, *slot
, &meta
);
1459 sync_descbuffer_for_cpu(ring
, meta
->dmaaddr
, ring
->rx_buffersize
);
1462 if (ring
->index
== 3) {
1463 /* We received an xmit status. */
1464 struct b43_hwtxstatus
*hw
= (struct b43_hwtxstatus
*)skb
->data
;
1467 while (hw
->cookie
== 0) {
1474 b43_handle_hwtxstatus(ring
->dev
, hw
);
1475 /* recycle the descriptor buffer. */
1476 sync_descbuffer_for_device(ring
, meta
->dmaaddr
,
1477 ring
->rx_buffersize
);
1481 rxhdr
= (struct b43_rxhdr_fw4
*)skb
->data
;
1482 len
= le16_to_cpu(rxhdr
->frame_len
);
1489 len
= le16_to_cpu(rxhdr
->frame_len
);
1490 } while (len
== 0 && i
++ < 5);
1491 if (unlikely(len
== 0)) {
1492 /* recycle the descriptor buffer. */
1493 sync_descbuffer_for_device(ring
, meta
->dmaaddr
,
1494 ring
->rx_buffersize
);
1498 if (unlikely(len
> ring
->rx_buffersize
)) {
1499 /* The data did not fit into one descriptor buffer
1500 * and is split over multiple buffers.
1501 * This should never happen, as we try to allocate buffers
1502 * big enough. So simply ignore this packet.
1508 desc
= ops
->idx2desc(ring
, *slot
, &meta
);
1509 /* recycle the descriptor buffer. */
1510 sync_descbuffer_for_device(ring
, meta
->dmaaddr
,
1511 ring
->rx_buffersize
);
1512 *slot
= next_slot(ring
, *slot
);
1514 tmp
-= ring
->rx_buffersize
;
1518 b43err(ring
->dev
->wl
, "DMA RX buffer too small "
1519 "(len: %u, buffer: %u, nr-dropped: %d)\n",
1520 len
, ring
->rx_buffersize
, cnt
);
1524 dmaaddr
= meta
->dmaaddr
;
1525 err
= setup_rx_descbuffer(ring
, desc
, meta
, GFP_ATOMIC
);
1526 if (unlikely(err
)) {
1527 b43dbg(ring
->dev
->wl
, "DMA RX: setup_rx_descbuffer() failed\n");
1528 sync_descbuffer_for_device(ring
, dmaaddr
, ring
->rx_buffersize
);
1532 unmap_descbuffer(ring
, dmaaddr
, ring
->rx_buffersize
, 0);
1533 skb_put(skb
, len
+ ring
->frameoffset
);
1534 skb_pull(skb
, ring
->frameoffset
);
1536 b43_rx(ring
->dev
, skb
, rxhdr
);
1541 void b43_dma_rx(struct b43_dmaring
*ring
)
1543 const struct b43_dma_ops
*ops
= ring
->ops
;
1544 int slot
, current_slot
;
1547 B43_WARN_ON(ring
->tx
);
1548 current_slot
= ops
->get_current_rxslot(ring
);
1549 B43_WARN_ON(!(current_slot
>= 0 && current_slot
< ring
->nr_slots
));
1551 slot
= ring
->current_slot
;
1552 for (; slot
!= current_slot
; slot
= next_slot(ring
, slot
)) {
1553 dma_rx(ring
, &slot
);
1554 update_max_used_slots(ring
, ++used_slots
);
1556 ops
->set_current_rxslot(ring
, slot
);
1557 ring
->current_slot
= slot
;
1560 static void b43_dma_tx_suspend_ring(struct b43_dmaring
*ring
)
1562 unsigned long flags
;
1564 spin_lock_irqsave(&ring
->lock
, flags
);
1565 B43_WARN_ON(!ring
->tx
);
1566 ring
->ops
->tx_suspend(ring
);
1567 spin_unlock_irqrestore(&ring
->lock
, flags
);
1570 static void b43_dma_tx_resume_ring(struct b43_dmaring
*ring
)
1572 unsigned long flags
;
1574 spin_lock_irqsave(&ring
->lock
, flags
);
1575 B43_WARN_ON(!ring
->tx
);
1576 ring
->ops
->tx_resume(ring
);
1577 spin_unlock_irqrestore(&ring
->lock
, flags
);
1580 void b43_dma_tx_suspend(struct b43_wldev
*dev
)
1582 b43_power_saving_ctl_bits(dev
, B43_PS_AWAKE
);
1583 b43_dma_tx_suspend_ring(dev
->dma
.tx_ring0
);
1584 b43_dma_tx_suspend_ring(dev
->dma
.tx_ring1
);
1585 b43_dma_tx_suspend_ring(dev
->dma
.tx_ring2
);
1586 b43_dma_tx_suspend_ring(dev
->dma
.tx_ring3
);
1587 b43_dma_tx_suspend_ring(dev
->dma
.tx_ring4
);
1588 b43_dma_tx_suspend_ring(dev
->dma
.tx_ring5
);
1591 void b43_dma_tx_resume(struct b43_wldev
*dev
)
1593 b43_dma_tx_resume_ring(dev
->dma
.tx_ring5
);
1594 b43_dma_tx_resume_ring(dev
->dma
.tx_ring4
);
1595 b43_dma_tx_resume_ring(dev
->dma
.tx_ring3
);
1596 b43_dma_tx_resume_ring(dev
->dma
.tx_ring2
);
1597 b43_dma_tx_resume_ring(dev
->dma
.tx_ring1
);
1598 b43_dma_tx_resume_ring(dev
->dma
.tx_ring0
);
1599 b43_power_saving_ctl_bits(dev
, 0);