3 Broadcom B43 wireless driver
5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
6 Copyright (c) 2005 Stefano Brivio <stefano.brivio@polimi.it>
7 Copyright (c) 2005-2009 Michael Buesch <m@bues.ch>
8 Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
9 Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
10 Copyright (c) 2010-2011 Rafał Miłecki <zajec5@gmail.com>
13 Copyright (c) 2009 Albert Herranz <albert_herranz@yahoo.es>
15 Some parts of the code in this file are derived from the ipw2200
16 driver Copyright(c) 2003 - 2004 Intel Corporation.
18 This program is free software; you can redistribute it and/or modify
19 it under the terms of the GNU General Public License as published by
20 the Free Software Foundation; either version 2 of the License, or
21 (at your option) any later version.
23 This program is distributed in the hope that it will be useful,
24 but WITHOUT ANY WARRANTY; without even the implied warranty of
25 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 GNU General Public License for more details.
28 You should have received a copy of the GNU General Public License
29 along with this program; see the file COPYING. If not, write to
30 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
31 Boston, MA 02110-1301, USA.
35 #include <linux/delay.h>
36 #include <linux/init.h>
37 #include <linux/module.h>
38 #include <linux/if_arp.h>
39 #include <linux/etherdevice.h>
40 #include <linux/firmware.h>
41 #include <linux/workqueue.h>
42 #include <linux/skbuff.h>
44 #include <linux/dma-mapping.h>
45 #include <linux/slab.h>
46 #include <asm/unaligned.h>
51 #include "phy_common.h"
61 #include <linux/mmc/sdio_func.h>
63 MODULE_DESCRIPTION("Broadcom B43 wireless driver");
64 MODULE_AUTHOR("Martin Langer");
65 MODULE_AUTHOR("Stefano Brivio");
66 MODULE_AUTHOR("Michael Buesch");
67 MODULE_AUTHOR("Gábor Stefanik");
68 MODULE_AUTHOR("Rafał Miłecki");
69 MODULE_LICENSE("GPL");
71 MODULE_FIRMWARE("b43/ucode11.fw");
72 MODULE_FIRMWARE("b43/ucode13.fw");
73 MODULE_FIRMWARE("b43/ucode14.fw");
74 MODULE_FIRMWARE("b43/ucode15.fw");
75 MODULE_FIRMWARE("b43/ucode16_mimo.fw");
76 MODULE_FIRMWARE("b43/ucode5.fw");
77 MODULE_FIRMWARE("b43/ucode9.fw");
79 static int modparam_bad_frames_preempt
;
80 module_param_named(bad_frames_preempt
, modparam_bad_frames_preempt
, int, 0444);
81 MODULE_PARM_DESC(bad_frames_preempt
,
82 "enable(1) / disable(0) Bad Frames Preemption");
84 static char modparam_fwpostfix
[16];
85 module_param_string(fwpostfix
, modparam_fwpostfix
, 16, 0444);
86 MODULE_PARM_DESC(fwpostfix
, "Postfix for the .fw files to load.");
88 static int modparam_hwpctl
;
89 module_param_named(hwpctl
, modparam_hwpctl
, int, 0444);
90 MODULE_PARM_DESC(hwpctl
, "Enable hardware-side power control (default off)");
92 static int modparam_nohwcrypt
;
93 module_param_named(nohwcrypt
, modparam_nohwcrypt
, int, 0444);
94 MODULE_PARM_DESC(nohwcrypt
, "Disable hardware encryption.");
96 static int modparam_hwtkip
;
97 module_param_named(hwtkip
, modparam_hwtkip
, int, 0444);
98 MODULE_PARM_DESC(hwtkip
, "Enable hardware tkip.");
100 static int modparam_qos
= 1;
101 module_param_named(qos
, modparam_qos
, int, 0444);
102 MODULE_PARM_DESC(qos
, "Enable QOS support (default on)");
104 static int modparam_btcoex
= 1;
105 module_param_named(btcoex
, modparam_btcoex
, int, 0444);
106 MODULE_PARM_DESC(btcoex
, "Enable Bluetooth coexistence (default on)");
108 int b43_modparam_verbose
= B43_VERBOSITY_DEFAULT
;
109 module_param_named(verbose
, b43_modparam_verbose
, int, 0644);
110 MODULE_PARM_DESC(verbose
, "Log message verbosity: 0=error, 1=warn, 2=info(default), 3=debug");
112 static int b43_modparam_pio
= 0;
113 module_param_named(pio
, b43_modparam_pio
, int, 0644);
114 MODULE_PARM_DESC(pio
, "Use PIO accesses by default: 0=DMA, 1=PIO");
116 static int modparam_allhwsupport
= !IS_ENABLED(CONFIG_BRCMSMAC
);
117 module_param_named(allhwsupport
, modparam_allhwsupport
, int, 0444);
118 MODULE_PARM_DESC(allhwsupport
, "Enable support for all hardware (even it if overlaps with the brcmsmac driver)");
120 #ifdef CONFIG_B43_BCMA
121 static const struct bcma_device_id b43_bcma_tbl
[] = {
122 BCMA_CORE(BCMA_MANUF_BCM
, BCMA_CORE_80211
, 0x11, BCMA_ANY_CLASS
),
123 BCMA_CORE(BCMA_MANUF_BCM
, BCMA_CORE_80211
, 0x17, BCMA_ANY_CLASS
),
124 BCMA_CORE(BCMA_MANUF_BCM
, BCMA_CORE_80211
, 0x18, BCMA_ANY_CLASS
),
125 BCMA_CORE(BCMA_MANUF_BCM
, BCMA_CORE_80211
, 0x1D, BCMA_ANY_CLASS
),
128 MODULE_DEVICE_TABLE(bcma
, b43_bcma_tbl
);
131 #ifdef CONFIG_B43_SSB
132 static const struct ssb_device_id b43_ssb_tbl
[] = {
133 SSB_DEVICE(SSB_VENDOR_BROADCOM
, SSB_DEV_80211
, 5),
134 SSB_DEVICE(SSB_VENDOR_BROADCOM
, SSB_DEV_80211
, 6),
135 SSB_DEVICE(SSB_VENDOR_BROADCOM
, SSB_DEV_80211
, 7),
136 SSB_DEVICE(SSB_VENDOR_BROADCOM
, SSB_DEV_80211
, 9),
137 SSB_DEVICE(SSB_VENDOR_BROADCOM
, SSB_DEV_80211
, 10),
138 SSB_DEVICE(SSB_VENDOR_BROADCOM
, SSB_DEV_80211
, 11),
139 SSB_DEVICE(SSB_VENDOR_BROADCOM
, SSB_DEV_80211
, 12),
140 SSB_DEVICE(SSB_VENDOR_BROADCOM
, SSB_DEV_80211
, 13),
141 SSB_DEVICE(SSB_VENDOR_BROADCOM
, SSB_DEV_80211
, 15),
142 SSB_DEVICE(SSB_VENDOR_BROADCOM
, SSB_DEV_80211
, 16),
145 MODULE_DEVICE_TABLE(ssb
, b43_ssb_tbl
);
148 /* Channel and ratetables are shared for all devices.
149 * They can't be const, because ieee80211 puts some precalculated
150 * data in there. This data is the same for all devices, so we don't
151 * get concurrency issues */
152 #define RATETAB_ENT(_rateid, _flags) \
154 .bitrate = B43_RATE_TO_BASE100KBPS(_rateid), \
155 .hw_value = (_rateid), \
160 * NOTE: When changing this, sync with xmit.c's
161 * b43_plcp_get_bitrate_idx_* functions!
163 static struct ieee80211_rate __b43_ratetable
[] = {
164 RATETAB_ENT(B43_CCK_RATE_1MB
, 0),
165 RATETAB_ENT(B43_CCK_RATE_2MB
, IEEE80211_RATE_SHORT_PREAMBLE
),
166 RATETAB_ENT(B43_CCK_RATE_5MB
, IEEE80211_RATE_SHORT_PREAMBLE
),
167 RATETAB_ENT(B43_CCK_RATE_11MB
, IEEE80211_RATE_SHORT_PREAMBLE
),
168 RATETAB_ENT(B43_OFDM_RATE_6MB
, 0),
169 RATETAB_ENT(B43_OFDM_RATE_9MB
, 0),
170 RATETAB_ENT(B43_OFDM_RATE_12MB
, 0),
171 RATETAB_ENT(B43_OFDM_RATE_18MB
, 0),
172 RATETAB_ENT(B43_OFDM_RATE_24MB
, 0),
173 RATETAB_ENT(B43_OFDM_RATE_36MB
, 0),
174 RATETAB_ENT(B43_OFDM_RATE_48MB
, 0),
175 RATETAB_ENT(B43_OFDM_RATE_54MB
, 0),
178 #define b43_a_ratetable (__b43_ratetable + 4)
179 #define b43_a_ratetable_size 8
180 #define b43_b_ratetable (__b43_ratetable + 0)
181 #define b43_b_ratetable_size 4
182 #define b43_g_ratetable (__b43_ratetable + 0)
183 #define b43_g_ratetable_size 12
185 #define CHAN2G(_channel, _freq, _flags) { \
186 .band = IEEE80211_BAND_2GHZ, \
187 .center_freq = (_freq), \
188 .hw_value = (_channel), \
190 .max_antenna_gain = 0, \
193 static struct ieee80211_channel b43_2ghz_chantable
[] = {
211 #define CHAN4G(_channel, _flags) { \
212 .band = IEEE80211_BAND_5GHZ, \
213 .center_freq = 4000 + (5 * (_channel)), \
214 .hw_value = (_channel), \
216 .max_antenna_gain = 0, \
219 #define CHAN5G(_channel, _flags) { \
220 .band = IEEE80211_BAND_5GHZ, \
221 .center_freq = 5000 + (5 * (_channel)), \
222 .hw_value = (_channel), \
224 .max_antenna_gain = 0, \
227 static struct ieee80211_channel b43_5ghz_nphy_chantable
[] = {
228 CHAN4G(184, 0), CHAN4G(186, 0),
229 CHAN4G(188, 0), CHAN4G(190, 0),
230 CHAN4G(192, 0), CHAN4G(194, 0),
231 CHAN4G(196, 0), CHAN4G(198, 0),
232 CHAN4G(200, 0), CHAN4G(202, 0),
233 CHAN4G(204, 0), CHAN4G(206, 0),
234 CHAN4G(208, 0), CHAN4G(210, 0),
235 CHAN4G(212, 0), CHAN4G(214, 0),
236 CHAN4G(216, 0), CHAN4G(218, 0),
237 CHAN4G(220, 0), CHAN4G(222, 0),
238 CHAN4G(224, 0), CHAN4G(226, 0),
240 CHAN5G(32, 0), CHAN5G(34, 0),
241 CHAN5G(36, 0), CHAN5G(38, 0),
242 CHAN5G(40, 0), CHAN5G(42, 0),
243 CHAN5G(44, 0), CHAN5G(46, 0),
244 CHAN5G(48, 0), CHAN5G(50, 0),
245 CHAN5G(52, 0), CHAN5G(54, 0),
246 CHAN5G(56, 0), CHAN5G(58, 0),
247 CHAN5G(60, 0), CHAN5G(62, 0),
248 CHAN5G(64, 0), CHAN5G(66, 0),
249 CHAN5G(68, 0), CHAN5G(70, 0),
250 CHAN5G(72, 0), CHAN5G(74, 0),
251 CHAN5G(76, 0), CHAN5G(78, 0),
252 CHAN5G(80, 0), CHAN5G(82, 0),
253 CHAN5G(84, 0), CHAN5G(86, 0),
254 CHAN5G(88, 0), CHAN5G(90, 0),
255 CHAN5G(92, 0), CHAN5G(94, 0),
256 CHAN5G(96, 0), CHAN5G(98, 0),
257 CHAN5G(100, 0), CHAN5G(102, 0),
258 CHAN5G(104, 0), CHAN5G(106, 0),
259 CHAN5G(108, 0), CHAN5G(110, 0),
260 CHAN5G(112, 0), CHAN5G(114, 0),
261 CHAN5G(116, 0), CHAN5G(118, 0),
262 CHAN5G(120, 0), CHAN5G(122, 0),
263 CHAN5G(124, 0), CHAN5G(126, 0),
264 CHAN5G(128, 0), CHAN5G(130, 0),
265 CHAN5G(132, 0), CHAN5G(134, 0),
266 CHAN5G(136, 0), CHAN5G(138, 0),
267 CHAN5G(140, 0), CHAN5G(142, 0),
268 CHAN5G(144, 0), CHAN5G(145, 0),
269 CHAN5G(146, 0), CHAN5G(147, 0),
270 CHAN5G(148, 0), CHAN5G(149, 0),
271 CHAN5G(150, 0), CHAN5G(151, 0),
272 CHAN5G(152, 0), CHAN5G(153, 0),
273 CHAN5G(154, 0), CHAN5G(155, 0),
274 CHAN5G(156, 0), CHAN5G(157, 0),
275 CHAN5G(158, 0), CHAN5G(159, 0),
276 CHAN5G(160, 0), CHAN5G(161, 0),
277 CHAN5G(162, 0), CHAN5G(163, 0),
278 CHAN5G(164, 0), CHAN5G(165, 0),
279 CHAN5G(166, 0), CHAN5G(168, 0),
280 CHAN5G(170, 0), CHAN5G(172, 0),
281 CHAN5G(174, 0), CHAN5G(176, 0),
282 CHAN5G(178, 0), CHAN5G(180, 0),
286 static struct ieee80211_channel b43_5ghz_aphy_chantable
[] = {
287 CHAN5G(34, 0), CHAN5G(36, 0),
288 CHAN5G(38, 0), CHAN5G(40, 0),
289 CHAN5G(42, 0), CHAN5G(44, 0),
290 CHAN5G(46, 0), CHAN5G(48, 0),
291 CHAN5G(52, 0), CHAN5G(56, 0),
292 CHAN5G(60, 0), CHAN5G(64, 0),
293 CHAN5G(100, 0), CHAN5G(104, 0),
294 CHAN5G(108, 0), CHAN5G(112, 0),
295 CHAN5G(116, 0), CHAN5G(120, 0),
296 CHAN5G(124, 0), CHAN5G(128, 0),
297 CHAN5G(132, 0), CHAN5G(136, 0),
298 CHAN5G(140, 0), CHAN5G(149, 0),
299 CHAN5G(153, 0), CHAN5G(157, 0),
300 CHAN5G(161, 0), CHAN5G(165, 0),
301 CHAN5G(184, 0), CHAN5G(188, 0),
302 CHAN5G(192, 0), CHAN5G(196, 0),
303 CHAN5G(200, 0), CHAN5G(204, 0),
304 CHAN5G(208, 0), CHAN5G(212, 0),
310 static struct ieee80211_supported_band b43_band_5GHz_nphy
= {
311 .band
= IEEE80211_BAND_5GHZ
,
312 .channels
= b43_5ghz_nphy_chantable
,
313 .n_channels
= ARRAY_SIZE(b43_5ghz_nphy_chantable
),
314 .bitrates
= b43_a_ratetable
,
315 .n_bitrates
= b43_a_ratetable_size
,
318 static struct ieee80211_supported_band b43_band_5GHz_aphy
= {
319 .band
= IEEE80211_BAND_5GHZ
,
320 .channels
= b43_5ghz_aphy_chantable
,
321 .n_channels
= ARRAY_SIZE(b43_5ghz_aphy_chantable
),
322 .bitrates
= b43_a_ratetable
,
323 .n_bitrates
= b43_a_ratetable_size
,
326 static struct ieee80211_supported_band b43_band_2GHz
= {
327 .band
= IEEE80211_BAND_2GHZ
,
328 .channels
= b43_2ghz_chantable
,
329 .n_channels
= ARRAY_SIZE(b43_2ghz_chantable
),
330 .bitrates
= b43_g_ratetable
,
331 .n_bitrates
= b43_g_ratetable_size
,
334 static void b43_wireless_core_exit(struct b43_wldev
*dev
);
335 static int b43_wireless_core_init(struct b43_wldev
*dev
);
336 static struct b43_wldev
* b43_wireless_core_stop(struct b43_wldev
*dev
);
337 static int b43_wireless_core_start(struct b43_wldev
*dev
);
338 static void b43_op_bss_info_changed(struct ieee80211_hw
*hw
,
339 struct ieee80211_vif
*vif
,
340 struct ieee80211_bss_conf
*conf
,
343 static int b43_ratelimit(struct b43_wl
*wl
)
345 if (!wl
|| !wl
->current_dev
)
347 if (b43_status(wl
->current_dev
) < B43_STAT_STARTED
)
349 /* We are up and running.
350 * Ratelimit the messages to avoid DoS over the net. */
351 return net_ratelimit();
354 void b43info(struct b43_wl
*wl
, const char *fmt
, ...)
356 struct va_format vaf
;
359 if (b43_modparam_verbose
< B43_VERBOSITY_INFO
)
361 if (!b43_ratelimit(wl
))
369 printk(KERN_INFO
"b43-%s: %pV",
370 (wl
&& wl
->hw
) ? wiphy_name(wl
->hw
->wiphy
) : "wlan", &vaf
);
375 void b43err(struct b43_wl
*wl
, const char *fmt
, ...)
377 struct va_format vaf
;
380 if (b43_modparam_verbose
< B43_VERBOSITY_ERROR
)
382 if (!b43_ratelimit(wl
))
390 printk(KERN_ERR
"b43-%s ERROR: %pV",
391 (wl
&& wl
->hw
) ? wiphy_name(wl
->hw
->wiphy
) : "wlan", &vaf
);
396 void b43warn(struct b43_wl
*wl
, const char *fmt
, ...)
398 struct va_format vaf
;
401 if (b43_modparam_verbose
< B43_VERBOSITY_WARN
)
403 if (!b43_ratelimit(wl
))
411 printk(KERN_WARNING
"b43-%s warning: %pV",
412 (wl
&& wl
->hw
) ? wiphy_name(wl
->hw
->wiphy
) : "wlan", &vaf
);
417 void b43dbg(struct b43_wl
*wl
, const char *fmt
, ...)
419 struct va_format vaf
;
422 if (b43_modparam_verbose
< B43_VERBOSITY_DEBUG
)
430 printk(KERN_DEBUG
"b43-%s debug: %pV",
431 (wl
&& wl
->hw
) ? wiphy_name(wl
->hw
->wiphy
) : "wlan", &vaf
);
436 static void b43_ram_write(struct b43_wldev
*dev
, u16 offset
, u32 val
)
440 B43_WARN_ON(offset
% 4 != 0);
442 macctl
= b43_read32(dev
, B43_MMIO_MACCTL
);
443 if (macctl
& B43_MACCTL_BE
)
446 b43_write32(dev
, B43_MMIO_RAM_CONTROL
, offset
);
448 b43_write32(dev
, B43_MMIO_RAM_DATA
, val
);
451 static inline void b43_shm_control_word(struct b43_wldev
*dev
,
452 u16 routing
, u16 offset
)
456 /* "offset" is the WORD offset. */
460 b43_write32(dev
, B43_MMIO_SHM_CONTROL
, control
);
463 u32
b43_shm_read32(struct b43_wldev
*dev
, u16 routing
, u16 offset
)
467 if (routing
== B43_SHM_SHARED
) {
468 B43_WARN_ON(offset
& 0x0001);
469 if (offset
& 0x0003) {
470 /* Unaligned access */
471 b43_shm_control_word(dev
, routing
, offset
>> 2);
472 ret
= b43_read16(dev
, B43_MMIO_SHM_DATA_UNALIGNED
);
473 b43_shm_control_word(dev
, routing
, (offset
>> 2) + 1);
474 ret
|= ((u32
)b43_read16(dev
, B43_MMIO_SHM_DATA
)) << 16;
480 b43_shm_control_word(dev
, routing
, offset
);
481 ret
= b43_read32(dev
, B43_MMIO_SHM_DATA
);
486 u16
b43_shm_read16(struct b43_wldev
*dev
, u16 routing
, u16 offset
)
490 if (routing
== B43_SHM_SHARED
) {
491 B43_WARN_ON(offset
& 0x0001);
492 if (offset
& 0x0003) {
493 /* Unaligned access */
494 b43_shm_control_word(dev
, routing
, offset
>> 2);
495 ret
= b43_read16(dev
, B43_MMIO_SHM_DATA_UNALIGNED
);
501 b43_shm_control_word(dev
, routing
, offset
);
502 ret
= b43_read16(dev
, B43_MMIO_SHM_DATA
);
507 void b43_shm_write32(struct b43_wldev
*dev
, u16 routing
, u16 offset
, u32 value
)
509 if (routing
== B43_SHM_SHARED
) {
510 B43_WARN_ON(offset
& 0x0001);
511 if (offset
& 0x0003) {
512 /* Unaligned access */
513 b43_shm_control_word(dev
, routing
, offset
>> 2);
514 b43_write16(dev
, B43_MMIO_SHM_DATA_UNALIGNED
,
516 b43_shm_control_word(dev
, routing
, (offset
>> 2) + 1);
517 b43_write16(dev
, B43_MMIO_SHM_DATA
,
518 (value
>> 16) & 0xFFFF);
523 b43_shm_control_word(dev
, routing
, offset
);
524 b43_write32(dev
, B43_MMIO_SHM_DATA
, value
);
527 void b43_shm_write16(struct b43_wldev
*dev
, u16 routing
, u16 offset
, u16 value
)
529 if (routing
== B43_SHM_SHARED
) {
530 B43_WARN_ON(offset
& 0x0001);
531 if (offset
& 0x0003) {
532 /* Unaligned access */
533 b43_shm_control_word(dev
, routing
, offset
>> 2);
534 b43_write16(dev
, B43_MMIO_SHM_DATA_UNALIGNED
, value
);
539 b43_shm_control_word(dev
, routing
, offset
);
540 b43_write16(dev
, B43_MMIO_SHM_DATA
, value
);
544 u64
b43_hf_read(struct b43_wldev
*dev
)
548 ret
= b43_shm_read16(dev
, B43_SHM_SHARED
, B43_SHM_SH_HOSTF3
);
550 ret
|= b43_shm_read16(dev
, B43_SHM_SHARED
, B43_SHM_SH_HOSTF2
);
552 ret
|= b43_shm_read16(dev
, B43_SHM_SHARED
, B43_SHM_SH_HOSTF1
);
557 /* Write HostFlags */
558 void b43_hf_write(struct b43_wldev
*dev
, u64 value
)
562 lo
= (value
& 0x00000000FFFFULL
);
563 mi
= (value
& 0x0000FFFF0000ULL
) >> 16;
564 hi
= (value
& 0xFFFF00000000ULL
) >> 32;
565 b43_shm_write16(dev
, B43_SHM_SHARED
, B43_SHM_SH_HOSTF1
, lo
);
566 b43_shm_write16(dev
, B43_SHM_SHARED
, B43_SHM_SH_HOSTF2
, mi
);
567 b43_shm_write16(dev
, B43_SHM_SHARED
, B43_SHM_SH_HOSTF3
, hi
);
570 /* Read the firmware capabilities bitmask (Opensource firmware only) */
571 static u16
b43_fwcapa_read(struct b43_wldev
*dev
)
573 B43_WARN_ON(!dev
->fw
.opensource
);
574 return b43_shm_read16(dev
, B43_SHM_SHARED
, B43_SHM_SH_FWCAPA
);
577 void b43_tsf_read(struct b43_wldev
*dev
, u64
*tsf
)
581 B43_WARN_ON(dev
->dev
->core_rev
< 3);
583 /* The hardware guarantees us an atomic read, if we
584 * read the low register first. */
585 low
= b43_read32(dev
, B43_MMIO_REV3PLUS_TSF_LOW
);
586 high
= b43_read32(dev
, B43_MMIO_REV3PLUS_TSF_HIGH
);
593 static void b43_time_lock(struct b43_wldev
*dev
)
595 b43_maskset32(dev
, B43_MMIO_MACCTL
, ~0, B43_MACCTL_TBTTHOLD
);
596 /* Commit the write */
597 b43_read32(dev
, B43_MMIO_MACCTL
);
600 static void b43_time_unlock(struct b43_wldev
*dev
)
602 b43_maskset32(dev
, B43_MMIO_MACCTL
, ~B43_MACCTL_TBTTHOLD
, 0);
603 /* Commit the write */
604 b43_read32(dev
, B43_MMIO_MACCTL
);
607 static void b43_tsf_write_locked(struct b43_wldev
*dev
, u64 tsf
)
611 B43_WARN_ON(dev
->dev
->core_rev
< 3);
615 /* The hardware guarantees us an atomic write, if we
616 * write the low register first. */
617 b43_write32(dev
, B43_MMIO_REV3PLUS_TSF_LOW
, low
);
619 b43_write32(dev
, B43_MMIO_REV3PLUS_TSF_HIGH
, high
);
623 void b43_tsf_write(struct b43_wldev
*dev
, u64 tsf
)
626 b43_tsf_write_locked(dev
, tsf
);
627 b43_time_unlock(dev
);
631 void b43_macfilter_set(struct b43_wldev
*dev
, u16 offset
, const u8
*mac
)
633 static const u8 zero_addr
[ETH_ALEN
] = { 0 };
640 b43_write16(dev
, B43_MMIO_MACFILTER_CONTROL
, offset
);
644 b43_write16(dev
, B43_MMIO_MACFILTER_DATA
, data
);
647 b43_write16(dev
, B43_MMIO_MACFILTER_DATA
, data
);
650 b43_write16(dev
, B43_MMIO_MACFILTER_DATA
, data
);
653 static void b43_write_mac_bssid_templates(struct b43_wldev
*dev
)
657 u8 mac_bssid
[ETH_ALEN
* 2];
661 bssid
= dev
->wl
->bssid
;
662 mac
= dev
->wl
->mac_addr
;
664 b43_macfilter_set(dev
, B43_MACFILTER_BSSID
, bssid
);
666 memcpy(mac_bssid
, mac
, ETH_ALEN
);
667 memcpy(mac_bssid
+ ETH_ALEN
, bssid
, ETH_ALEN
);
669 /* Write our MAC address and BSSID to template ram */
670 for (i
= 0; i
< ARRAY_SIZE(mac_bssid
); i
+= sizeof(u32
)) {
671 tmp
= (u32
) (mac_bssid
[i
+ 0]);
672 tmp
|= (u32
) (mac_bssid
[i
+ 1]) << 8;
673 tmp
|= (u32
) (mac_bssid
[i
+ 2]) << 16;
674 tmp
|= (u32
) (mac_bssid
[i
+ 3]) << 24;
675 b43_ram_write(dev
, 0x20 + i
, tmp
);
679 static void b43_upload_card_macaddress(struct b43_wldev
*dev
)
681 b43_write_mac_bssid_templates(dev
);
682 b43_macfilter_set(dev
, B43_MACFILTER_SELF
, dev
->wl
->mac_addr
);
685 static void b43_set_slot_time(struct b43_wldev
*dev
, u16 slot_time
)
687 /* slot_time is in usec. */
688 /* This test used to exit for all but a G PHY. */
689 if (b43_current_band(dev
->wl
) == IEEE80211_BAND_5GHZ
)
691 b43_write16(dev
, B43_MMIO_IFSSLOT
, 510 + slot_time
);
692 /* Shared memory location 0x0010 is the slot time and should be
693 * set to slot_time; however, this register is initially 0 and changing
694 * the value adversely affects the transmit rate for BCM4311
695 * devices. Until this behavior is unterstood, delete this step
697 * b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time);
701 static void b43_short_slot_timing_enable(struct b43_wldev
*dev
)
703 b43_set_slot_time(dev
, 9);
706 static void b43_short_slot_timing_disable(struct b43_wldev
*dev
)
708 b43_set_slot_time(dev
, 20);
711 /* DummyTransmission function, as documented on
712 * http://bcm-v4.sipsolutions.net/802.11/DummyTransmission
714 void b43_dummy_transmission(struct b43_wldev
*dev
, bool ofdm
, bool pa_on
)
716 struct b43_phy
*phy
= &dev
->phy
;
717 unsigned int i
, max_loop
;
729 buffer
[0] = 0x000201CC;
732 buffer
[0] = 0x000B846E;
735 for (i
= 0; i
< 5; i
++)
736 b43_ram_write(dev
, i
* 4, buffer
[i
]);
738 b43_write16(dev
, B43_MMIO_XMTSEL
, 0x0000);
740 if (dev
->dev
->core_rev
< 11)
741 b43_write16(dev
, B43_MMIO_WEPCTL
, 0x0000);
743 b43_write16(dev
, B43_MMIO_WEPCTL
, 0x0100);
745 value
= (ofdm
? 0x41 : 0x40);
746 b43_write16(dev
, B43_MMIO_TXE0_PHYCTL
, value
);
747 if (phy
->type
== B43_PHYTYPE_N
|| phy
->type
== B43_PHYTYPE_LP
||
748 phy
->type
== B43_PHYTYPE_LCN
)
749 b43_write16(dev
, B43_MMIO_TXE0_PHYCTL1
, 0x1A02);
751 b43_write16(dev
, B43_MMIO_TXE0_WM_0
, 0x0000);
752 b43_write16(dev
, B43_MMIO_TXE0_WM_1
, 0x0000);
754 b43_write16(dev
, B43_MMIO_XMTTPLATETXPTR
, 0x0000);
755 b43_write16(dev
, B43_MMIO_XMTTXCNT
, 0x0014);
756 b43_write16(dev
, B43_MMIO_XMTSEL
, 0x0826);
757 b43_write16(dev
, B43_MMIO_TXE0_CTL
, 0x0000);
759 if (!pa_on
&& phy
->type
== B43_PHYTYPE_N
)
760 ; /*b43_nphy_pa_override(dev, false) */
764 case B43_PHYTYPE_LCN
:
765 b43_write16(dev
, B43_MMIO_TXE0_AUX
, 0x00D0);
768 b43_write16(dev
, B43_MMIO_TXE0_AUX
, 0x0050);
771 b43_write16(dev
, B43_MMIO_TXE0_AUX
, 0x0030);
773 b43_read16(dev
, B43_MMIO_TXE0_AUX
);
775 if (phy
->radio_ver
== 0x2050 && phy
->radio_rev
<= 0x5)
776 b43_radio_write16(dev
, 0x0051, 0x0017);
777 for (i
= 0x00; i
< max_loop
; i
++) {
778 value
= b43_read16(dev
, B43_MMIO_TXE0_STATUS
);
783 for (i
= 0x00; i
< 0x0A; i
++) {
784 value
= b43_read16(dev
, B43_MMIO_TXE0_STATUS
);
789 for (i
= 0x00; i
< 0x19; i
++) {
790 value
= b43_read16(dev
, B43_MMIO_IFSSTAT
);
791 if (!(value
& 0x0100))
795 if (phy
->radio_ver
== 0x2050 && phy
->radio_rev
<= 0x5)
796 b43_radio_write16(dev
, 0x0051, 0x0037);
799 static void key_write(struct b43_wldev
*dev
,
800 u8 index
, u8 algorithm
, const u8
*key
)
807 /* Key index/algo block */
808 kidx
= b43_kidx_to_fw(dev
, index
);
809 value
= ((kidx
<< 4) | algorithm
);
810 b43_shm_write16(dev
, B43_SHM_SHARED
,
811 B43_SHM_SH_KEYIDXBLOCK
+ (kidx
* 2), value
);
813 /* Write the key to the Key Table Pointer offset */
814 offset
= dev
->ktp
+ (index
* B43_SEC_KEYSIZE
);
815 for (i
= 0; i
< B43_SEC_KEYSIZE
; i
+= 2) {
817 value
|= (u16
) (key
[i
+ 1]) << 8;
818 b43_shm_write16(dev
, B43_SHM_SHARED
, offset
+ i
, value
);
822 static void keymac_write(struct b43_wldev
*dev
, u8 index
, const u8
*addr
)
824 u32 addrtmp
[2] = { 0, 0, };
825 u8 pairwise_keys_start
= B43_NR_GROUP_KEYS
* 2;
827 if (b43_new_kidx_api(dev
))
828 pairwise_keys_start
= B43_NR_GROUP_KEYS
;
830 B43_WARN_ON(index
< pairwise_keys_start
);
831 /* We have four default TX keys and possibly four default RX keys.
832 * Physical mac 0 is mapped to physical key 4 or 8, depending
833 * on the firmware version.
834 * So we must adjust the index here.
836 index
-= pairwise_keys_start
;
837 B43_WARN_ON(index
>= B43_NR_PAIRWISE_KEYS
);
840 addrtmp
[0] = addr
[0];
841 addrtmp
[0] |= ((u32
) (addr
[1]) << 8);
842 addrtmp
[0] |= ((u32
) (addr
[2]) << 16);
843 addrtmp
[0] |= ((u32
) (addr
[3]) << 24);
844 addrtmp
[1] = addr
[4];
845 addrtmp
[1] |= ((u32
) (addr
[5]) << 8);
848 /* Receive match transmitter address (RCMTA) mechanism */
849 b43_shm_write32(dev
, B43_SHM_RCMTA
,
850 (index
* 2) + 0, addrtmp
[0]);
851 b43_shm_write16(dev
, B43_SHM_RCMTA
,
852 (index
* 2) + 1, addrtmp
[1]);
855 /* The ucode will use phase1 key with TEK key to decrypt rx packets.
856 * When a packet is received, the iv32 is checked.
857 * - if it doesn't the packet is returned without modification (and software
858 * decryption can be done). That's what happen when iv16 wrap.
859 * - if it does, the rc4 key is computed, and decryption is tried.
860 * Either it will success and B43_RX_MAC_DEC is returned,
861 * either it fails and B43_RX_MAC_DEC|B43_RX_MAC_DECERR is returned
862 * and the packet is not usable (it got modified by the ucode).
863 * So in order to never have B43_RX_MAC_DECERR, we should provide
864 * a iv32 and phase1key that match. Because we drop packets in case of
865 * B43_RX_MAC_DECERR, if we have a correct iv32 but a wrong phase1key, all
866 * packets will be lost without higher layer knowing (ie no resync possible
869 * NOTE : this should support 50 key like RCMTA because
870 * (B43_SHM_SH_KEYIDXBLOCK - B43_SHM_SH_TKIPTSCTTAK)/14 = 50
872 static void rx_tkip_phase1_write(struct b43_wldev
*dev
, u8 index
, u32 iv32
,
877 u8 pairwise_keys_start
= B43_NR_GROUP_KEYS
* 2;
879 if (!modparam_hwtkip
)
882 if (b43_new_kidx_api(dev
))
883 pairwise_keys_start
= B43_NR_GROUP_KEYS
;
885 B43_WARN_ON(index
< pairwise_keys_start
);
886 /* We have four default TX keys and possibly four default RX keys.
887 * Physical mac 0 is mapped to physical key 4 or 8, depending
888 * on the firmware version.
889 * So we must adjust the index here.
891 index
-= pairwise_keys_start
;
892 B43_WARN_ON(index
>= B43_NR_PAIRWISE_KEYS
);
894 if (b43_debug(dev
, B43_DBG_KEYS
)) {
895 b43dbg(dev
->wl
, "rx_tkip_phase1_write : idx 0x%x, iv32 0x%x\n",
898 /* Write the key to the RX tkip shared mem */
899 offset
= B43_SHM_SH_TKIPTSCTTAK
+ index
* (10 + 4);
900 for (i
= 0; i
< 10; i
+= 2) {
901 b43_shm_write16(dev
, B43_SHM_SHARED
, offset
+ i
,
902 phase1key
? phase1key
[i
/ 2] : 0);
904 b43_shm_write16(dev
, B43_SHM_SHARED
, offset
+ i
, iv32
);
905 b43_shm_write16(dev
, B43_SHM_SHARED
, offset
+ i
+ 2, iv32
>> 16);
908 static void b43_op_update_tkip_key(struct ieee80211_hw
*hw
,
909 struct ieee80211_vif
*vif
,
910 struct ieee80211_key_conf
*keyconf
,
911 struct ieee80211_sta
*sta
,
912 u32 iv32
, u16
*phase1key
)
914 struct b43_wl
*wl
= hw_to_b43_wl(hw
);
915 struct b43_wldev
*dev
;
916 int index
= keyconf
->hw_key_idx
;
918 if (B43_WARN_ON(!modparam_hwtkip
))
921 /* This is only called from the RX path through mac80211, where
922 * our mutex is already locked. */
923 B43_WARN_ON(!mutex_is_locked(&wl
->mutex
));
924 dev
= wl
->current_dev
;
925 B43_WARN_ON(!dev
|| b43_status(dev
) < B43_STAT_INITIALIZED
);
927 keymac_write(dev
, index
, NULL
); /* First zero out mac to avoid race */
929 rx_tkip_phase1_write(dev
, index
, iv32
, phase1key
);
930 /* only pairwise TKIP keys are supported right now */
933 keymac_write(dev
, index
, sta
->addr
);
936 static void do_key_write(struct b43_wldev
*dev
,
937 u8 index
, u8 algorithm
,
938 const u8
*key
, size_t key_len
, const u8
*mac_addr
)
940 u8 buf
[B43_SEC_KEYSIZE
] = { 0, };
941 u8 pairwise_keys_start
= B43_NR_GROUP_KEYS
* 2;
943 if (b43_new_kidx_api(dev
))
944 pairwise_keys_start
= B43_NR_GROUP_KEYS
;
946 B43_WARN_ON(index
>= ARRAY_SIZE(dev
->key
));
947 B43_WARN_ON(key_len
> B43_SEC_KEYSIZE
);
949 if (index
>= pairwise_keys_start
)
950 keymac_write(dev
, index
, NULL
); /* First zero out mac. */
951 if (algorithm
== B43_SEC_ALGO_TKIP
) {
953 * We should provide an initial iv32, phase1key pair.
954 * We could start with iv32=0 and compute the corresponding
955 * phase1key, but this means calling ieee80211_get_tkip_key
956 * with a fake skb (or export other tkip function).
957 * Because we are lazy we hope iv32 won't start with
958 * 0xffffffff and let's b43_op_update_tkip_key provide a
961 rx_tkip_phase1_write(dev
, index
, 0xffffffff, (u16
*)buf
);
962 } else if (index
>= pairwise_keys_start
) /* clear it */
963 rx_tkip_phase1_write(dev
, index
, 0, NULL
);
965 memcpy(buf
, key
, key_len
);
966 key_write(dev
, index
, algorithm
, buf
);
967 if (index
>= pairwise_keys_start
)
968 keymac_write(dev
, index
, mac_addr
);
970 dev
->key
[index
].algorithm
= algorithm
;
973 static int b43_key_write(struct b43_wldev
*dev
,
974 int index
, u8 algorithm
,
975 const u8
*key
, size_t key_len
,
977 struct ieee80211_key_conf
*keyconf
)
980 int pairwise_keys_start
;
982 /* For ALG_TKIP the key is encoded as a 256-bit (32 byte) data block:
983 * - Temporal Encryption Key (128 bits)
984 * - Temporal Authenticator Tx MIC Key (64 bits)
985 * - Temporal Authenticator Rx MIC Key (64 bits)
987 * Hardware only store TEK
989 if (algorithm
== B43_SEC_ALGO_TKIP
&& key_len
== 32)
991 if (key_len
> B43_SEC_KEYSIZE
)
993 for (i
= 0; i
< ARRAY_SIZE(dev
->key
); i
++) {
994 /* Check that we don't already have this key. */
995 B43_WARN_ON(dev
->key
[i
].keyconf
== keyconf
);
998 /* Pairwise key. Get an empty slot for the key. */
999 if (b43_new_kidx_api(dev
))
1000 pairwise_keys_start
= B43_NR_GROUP_KEYS
;
1002 pairwise_keys_start
= B43_NR_GROUP_KEYS
* 2;
1003 for (i
= pairwise_keys_start
;
1004 i
< pairwise_keys_start
+ B43_NR_PAIRWISE_KEYS
;
1006 B43_WARN_ON(i
>= ARRAY_SIZE(dev
->key
));
1007 if (!dev
->key
[i
].keyconf
) {
1014 b43warn(dev
->wl
, "Out of hardware key memory\n");
1018 B43_WARN_ON(index
> 3);
1020 do_key_write(dev
, index
, algorithm
, key
, key_len
, mac_addr
);
1021 if ((index
<= 3) && !b43_new_kidx_api(dev
)) {
1022 /* Default RX key */
1023 B43_WARN_ON(mac_addr
);
1024 do_key_write(dev
, index
+ 4, algorithm
, key
, key_len
, NULL
);
1026 keyconf
->hw_key_idx
= index
;
1027 dev
->key
[index
].keyconf
= keyconf
;
1032 static int b43_key_clear(struct b43_wldev
*dev
, int index
)
1034 if (B43_WARN_ON((index
< 0) || (index
>= ARRAY_SIZE(dev
->key
))))
1036 do_key_write(dev
, index
, B43_SEC_ALGO_NONE
,
1037 NULL
, B43_SEC_KEYSIZE
, NULL
);
1038 if ((index
<= 3) && !b43_new_kidx_api(dev
)) {
1039 do_key_write(dev
, index
+ 4, B43_SEC_ALGO_NONE
,
1040 NULL
, B43_SEC_KEYSIZE
, NULL
);
1042 dev
->key
[index
].keyconf
= NULL
;
1047 static void b43_clear_keys(struct b43_wldev
*dev
)
1051 if (b43_new_kidx_api(dev
))
1052 count
= B43_NR_GROUP_KEYS
+ B43_NR_PAIRWISE_KEYS
;
1054 count
= B43_NR_GROUP_KEYS
* 2 + B43_NR_PAIRWISE_KEYS
;
1055 for (i
= 0; i
< count
; i
++)
1056 b43_key_clear(dev
, i
);
1059 static void b43_dump_keymemory(struct b43_wldev
*dev
)
1061 unsigned int i
, index
, count
, offset
, pairwise_keys_start
;
1067 struct b43_key
*key
;
1069 if (!b43_debug(dev
, B43_DBG_KEYS
))
1072 hf
= b43_hf_read(dev
);
1073 b43dbg(dev
->wl
, "Hardware key memory dump: USEDEFKEYS=%u\n",
1074 !!(hf
& B43_HF_USEDEFKEYS
));
1075 if (b43_new_kidx_api(dev
)) {
1076 pairwise_keys_start
= B43_NR_GROUP_KEYS
;
1077 count
= B43_NR_GROUP_KEYS
+ B43_NR_PAIRWISE_KEYS
;
1079 pairwise_keys_start
= B43_NR_GROUP_KEYS
* 2;
1080 count
= B43_NR_GROUP_KEYS
* 2 + B43_NR_PAIRWISE_KEYS
;
1082 for (index
= 0; index
< count
; index
++) {
1083 key
= &(dev
->key
[index
]);
1084 printk(KERN_DEBUG
"Key slot %02u: %s",
1085 index
, (key
->keyconf
== NULL
) ? " " : "*");
1086 offset
= dev
->ktp
+ (index
* B43_SEC_KEYSIZE
);
1087 for (i
= 0; i
< B43_SEC_KEYSIZE
; i
+= 2) {
1088 u16 tmp
= b43_shm_read16(dev
, B43_SHM_SHARED
, offset
+ i
);
1089 printk("%02X%02X", (tmp
& 0xFF), ((tmp
>> 8) & 0xFF));
1092 algo
= b43_shm_read16(dev
, B43_SHM_SHARED
,
1093 B43_SHM_SH_KEYIDXBLOCK
+ (index
* 2));
1094 printk(" Algo: %04X/%02X", algo
, key
->algorithm
);
1096 if (index
>= pairwise_keys_start
) {
1097 if (key
->algorithm
== B43_SEC_ALGO_TKIP
) {
1099 offset
= B43_SHM_SH_TKIPTSCTTAK
+ (index
- 4) * (10 + 4);
1100 for (i
= 0; i
< 14; i
+= 2) {
1101 u16 tmp
= b43_shm_read16(dev
, B43_SHM_SHARED
, offset
+ i
);
1102 printk("%02X%02X", (tmp
& 0xFF), ((tmp
>> 8) & 0xFF));
1105 rcmta0
= b43_shm_read32(dev
, B43_SHM_RCMTA
,
1106 ((index
- pairwise_keys_start
) * 2) + 0);
1107 rcmta1
= b43_shm_read16(dev
, B43_SHM_RCMTA
,
1108 ((index
- pairwise_keys_start
) * 2) + 1);
1109 *((__le32
*)(&mac
[0])) = cpu_to_le32(rcmta0
);
1110 *((__le16
*)(&mac
[4])) = cpu_to_le16(rcmta1
);
1111 printk(" MAC: %pM", mac
);
1113 printk(" DEFAULT KEY");
1118 void b43_power_saving_ctl_bits(struct b43_wldev
*dev
, unsigned int ps_flags
)
1126 B43_WARN_ON((ps_flags
& B43_PS_ENABLED
) &&
1127 (ps_flags
& B43_PS_DISABLED
));
1128 B43_WARN_ON((ps_flags
& B43_PS_AWAKE
) && (ps_flags
& B43_PS_ASLEEP
));
1130 if (ps_flags
& B43_PS_ENABLED
) {
1132 } else if (ps_flags
& B43_PS_DISABLED
) {
1135 //TODO: If powersave is not off and FIXME is not set and we are not in adhoc
1136 // and thus is not an AP and we are associated, set bit 25
1138 if (ps_flags
& B43_PS_AWAKE
) {
1140 } else if (ps_flags
& B43_PS_ASLEEP
) {
1143 //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME,
1144 // or we are associated, or FIXME, or the latest PS-Poll packet sent was
1145 // successful, set bit26
1148 /* FIXME: For now we force awake-on and hwps-off */
1152 macctl
= b43_read32(dev
, B43_MMIO_MACCTL
);
1154 macctl
|= B43_MACCTL_HWPS
;
1156 macctl
&= ~B43_MACCTL_HWPS
;
1158 macctl
|= B43_MACCTL_AWAKE
;
1160 macctl
&= ~B43_MACCTL_AWAKE
;
1161 b43_write32(dev
, B43_MMIO_MACCTL
, macctl
);
1163 b43_read32(dev
, B43_MMIO_MACCTL
);
1164 if (awake
&& dev
->dev
->core_rev
>= 5) {
1165 /* Wait for the microcode to wake up. */
1166 for (i
= 0; i
< 100; i
++) {
1167 ucstat
= b43_shm_read16(dev
, B43_SHM_SHARED
,
1168 B43_SHM_SH_UCODESTAT
);
1169 if (ucstat
!= B43_SHM_SH_UCODESTAT_SLEEP
)
1176 #ifdef CONFIG_B43_BCMA
1177 static void b43_bcma_phy_reset(struct b43_wldev
*dev
)
1181 /* Put PHY into reset */
1182 flags
= bcma_aread32(dev
->dev
->bdev
, BCMA_IOCTL
);
1183 flags
|= B43_BCMA_IOCTL_PHY_RESET
;
1184 flags
|= B43_BCMA_IOCTL_PHY_BW_20MHZ
; /* Make 20 MHz def */
1185 bcma_awrite32(dev
->dev
->bdev
, BCMA_IOCTL
, flags
);
1188 b43_phy_take_out_of_reset(dev
);
1191 static void b43_bcma_wireless_core_reset(struct b43_wldev
*dev
, bool gmode
)
1193 u32 req
= B43_BCMA_CLKCTLST_80211_PLL_REQ
|
1194 B43_BCMA_CLKCTLST_PHY_PLL_REQ
;
1195 u32 status
= B43_BCMA_CLKCTLST_80211_PLL_ST
|
1196 B43_BCMA_CLKCTLST_PHY_PLL_ST
;
1199 flags
= B43_BCMA_IOCTL_PHY_CLKEN
;
1201 flags
|= B43_BCMA_IOCTL_GMODE
;
1202 b43_device_enable(dev
, flags
);
1204 bcma_core_set_clockmode(dev
->dev
->bdev
, BCMA_CLKMODE_FAST
);
1205 b43_bcma_phy_reset(dev
);
1206 bcma_core_pll_ctl(dev
->dev
->bdev
, req
, status
, true);
1210 #ifdef CONFIG_B43_SSB
1211 static void b43_ssb_wireless_core_reset(struct b43_wldev
*dev
, bool gmode
)
1216 flags
|= B43_TMSLOW_GMODE
;
1217 flags
|= B43_TMSLOW_PHYCLKEN
;
1218 flags
|= B43_TMSLOW_PHYRESET
;
1219 if (dev
->phy
.type
== B43_PHYTYPE_N
)
1220 flags
|= B43_TMSLOW_PHY_BANDWIDTH_20MHZ
; /* Make 20 MHz def */
1221 b43_device_enable(dev
, flags
);
1222 msleep(2); /* Wait for the PLL to turn on. */
1224 b43_phy_take_out_of_reset(dev
);
1228 void b43_wireless_core_reset(struct b43_wldev
*dev
, bool gmode
)
1232 switch (dev
->dev
->bus_type
) {
1233 #ifdef CONFIG_B43_BCMA
1235 b43_bcma_wireless_core_reset(dev
, gmode
);
1238 #ifdef CONFIG_B43_SSB
1240 b43_ssb_wireless_core_reset(dev
, gmode
);
1245 /* Turn Analog ON, but only if we already know the PHY-type.
1246 * This protects against very early setup where we don't know the
1247 * PHY-type, yet. wireless_core_reset will be called once again later,
1248 * when we know the PHY-type. */
1250 dev
->phy
.ops
->switch_analog(dev
, 1);
1252 macctl
= b43_read32(dev
, B43_MMIO_MACCTL
);
1253 macctl
&= ~B43_MACCTL_GMODE
;
1255 macctl
|= B43_MACCTL_GMODE
;
1256 macctl
|= B43_MACCTL_IHR_ENABLED
;
1257 b43_write32(dev
, B43_MMIO_MACCTL
, macctl
);
1260 static void handle_irq_transmit_status(struct b43_wldev
*dev
)
1264 struct b43_txstatus stat
;
1267 v0
= b43_read32(dev
, B43_MMIO_XMITSTAT_0
);
1268 if (!(v0
& 0x00000001))
1270 v1
= b43_read32(dev
, B43_MMIO_XMITSTAT_1
);
1272 stat
.cookie
= (v0
>> 16);
1273 stat
.seq
= (v1
& 0x0000FFFF);
1274 stat
.phy_stat
= ((v1
& 0x00FF0000) >> 16);
1275 tmp
= (v0
& 0x0000FFFF);
1276 stat
.frame_count
= ((tmp
& 0xF000) >> 12);
1277 stat
.rts_count
= ((tmp
& 0x0F00) >> 8);
1278 stat
.supp_reason
= ((tmp
& 0x001C) >> 2);
1279 stat
.pm_indicated
= !!(tmp
& 0x0080);
1280 stat
.intermediate
= !!(tmp
& 0x0040);
1281 stat
.for_ampdu
= !!(tmp
& 0x0020);
1282 stat
.acked
= !!(tmp
& 0x0002);
1284 b43_handle_txstatus(dev
, &stat
);
1288 static void drain_txstatus_queue(struct b43_wldev
*dev
)
1292 if (dev
->dev
->core_rev
< 5)
1294 /* Read all entries from the microcode TXstatus FIFO
1295 * and throw them away.
1298 dummy
= b43_read32(dev
, B43_MMIO_XMITSTAT_0
);
1299 if (!(dummy
& 0x00000001))
1301 dummy
= b43_read32(dev
, B43_MMIO_XMITSTAT_1
);
1305 static u32
b43_jssi_read(struct b43_wldev
*dev
)
1309 val
= b43_shm_read16(dev
, B43_SHM_SHARED
, B43_SHM_SH_JSSI1
);
1311 val
|= b43_shm_read16(dev
, B43_SHM_SHARED
, B43_SHM_SH_JSSI0
);
1316 static void b43_jssi_write(struct b43_wldev
*dev
, u32 jssi
)
1318 b43_shm_write16(dev
, B43_SHM_SHARED
, B43_SHM_SH_JSSI0
,
1319 (jssi
& 0x0000FFFF));
1320 b43_shm_write16(dev
, B43_SHM_SHARED
, B43_SHM_SH_JSSI1
,
1321 (jssi
& 0xFFFF0000) >> 16);
1324 static void b43_generate_noise_sample(struct b43_wldev
*dev
)
1326 b43_jssi_write(dev
, 0x7F7F7F7F);
1327 b43_write32(dev
, B43_MMIO_MACCMD
,
1328 b43_read32(dev
, B43_MMIO_MACCMD
) | B43_MACCMD_BGNOISE
);
1331 static void b43_calculate_link_quality(struct b43_wldev
*dev
)
1333 /* Top half of Link Quality calculation. */
1335 if (dev
->phy
.type
!= B43_PHYTYPE_G
)
1337 if (dev
->noisecalc
.calculation_running
)
1339 dev
->noisecalc
.calculation_running
= true;
1340 dev
->noisecalc
.nr_samples
= 0;
1342 b43_generate_noise_sample(dev
);
1345 static void handle_irq_noise(struct b43_wldev
*dev
)
1347 struct b43_phy_g
*phy
= dev
->phy
.g
;
1353 /* Bottom half of Link Quality calculation. */
1355 if (dev
->phy
.type
!= B43_PHYTYPE_G
)
1358 /* Possible race condition: It might be possible that the user
1359 * changed to a different channel in the meantime since we
1360 * started the calculation. We ignore that fact, since it's
1361 * not really that much of a problem. The background noise is
1362 * an estimation only anyway. Slightly wrong results will get damped
1363 * by the averaging of the 8 sample rounds. Additionally the
1364 * value is shortlived. So it will be replaced by the next noise
1365 * calculation round soon. */
1367 B43_WARN_ON(!dev
->noisecalc
.calculation_running
);
1368 *((__le32
*)noise
) = cpu_to_le32(b43_jssi_read(dev
));
1369 if (noise
[0] == 0x7F || noise
[1] == 0x7F ||
1370 noise
[2] == 0x7F || noise
[3] == 0x7F)
1373 /* Get the noise samples. */
1374 B43_WARN_ON(dev
->noisecalc
.nr_samples
>= 8);
1375 i
= dev
->noisecalc
.nr_samples
;
1376 noise
[0] = clamp_val(noise
[0], 0, ARRAY_SIZE(phy
->nrssi_lt
) - 1);
1377 noise
[1] = clamp_val(noise
[1], 0, ARRAY_SIZE(phy
->nrssi_lt
) - 1);
1378 noise
[2] = clamp_val(noise
[2], 0, ARRAY_SIZE(phy
->nrssi_lt
) - 1);
1379 noise
[3] = clamp_val(noise
[3], 0, ARRAY_SIZE(phy
->nrssi_lt
) - 1);
1380 dev
->noisecalc
.samples
[i
][0] = phy
->nrssi_lt
[noise
[0]];
1381 dev
->noisecalc
.samples
[i
][1] = phy
->nrssi_lt
[noise
[1]];
1382 dev
->noisecalc
.samples
[i
][2] = phy
->nrssi_lt
[noise
[2]];
1383 dev
->noisecalc
.samples
[i
][3] = phy
->nrssi_lt
[noise
[3]];
1384 dev
->noisecalc
.nr_samples
++;
1385 if (dev
->noisecalc
.nr_samples
== 8) {
1386 /* Calculate the Link Quality by the noise samples. */
1388 for (i
= 0; i
< 8; i
++) {
1389 for (j
= 0; j
< 4; j
++)
1390 average
+= dev
->noisecalc
.samples
[i
][j
];
1396 tmp
= b43_shm_read16(dev
, B43_SHM_SHARED
, 0x40C);
1397 tmp
= (tmp
/ 128) & 0x1F;
1407 dev
->stats
.link_noise
= average
;
1408 dev
->noisecalc
.calculation_running
= false;
1412 b43_generate_noise_sample(dev
);
1415 static void handle_irq_tbtt_indication(struct b43_wldev
*dev
)
1417 if (b43_is_mode(dev
->wl
, NL80211_IFTYPE_AP
)) {
1420 if (1 /*FIXME: the last PSpoll frame was sent successfully */ )
1421 b43_power_saving_ctl_bits(dev
, 0);
1423 if (b43_is_mode(dev
->wl
, NL80211_IFTYPE_ADHOC
))
1424 dev
->dfq_valid
= true;
1427 static void handle_irq_atim_end(struct b43_wldev
*dev
)
1429 if (dev
->dfq_valid
) {
1430 b43_write32(dev
, B43_MMIO_MACCMD
,
1431 b43_read32(dev
, B43_MMIO_MACCMD
)
1432 | B43_MACCMD_DFQ_VALID
);
1433 dev
->dfq_valid
= false;
1437 static void handle_irq_pmq(struct b43_wldev
*dev
)
1444 tmp
= b43_read32(dev
, B43_MMIO_PS_STATUS
);
1445 if (!(tmp
& 0x00000008))
1448 /* 16bit write is odd, but correct. */
1449 b43_write16(dev
, B43_MMIO_PS_STATUS
, 0x0002);
1452 static void b43_write_template_common(struct b43_wldev
*dev
,
1453 const u8
*data
, u16 size
,
1455 u16 shm_size_offset
, u8 rate
)
1458 struct b43_plcp_hdr4 plcp
;
1461 b43_generate_plcp_hdr(&plcp
, size
+ FCS_LEN
, rate
);
1462 b43_ram_write(dev
, ram_offset
, le32_to_cpu(plcp
.data
));
1463 ram_offset
+= sizeof(u32
);
1464 /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
1465 * So leave the first two bytes of the next write blank.
1467 tmp
= (u32
) (data
[0]) << 16;
1468 tmp
|= (u32
) (data
[1]) << 24;
1469 b43_ram_write(dev
, ram_offset
, tmp
);
1470 ram_offset
+= sizeof(u32
);
1471 for (i
= 2; i
< size
; i
+= sizeof(u32
)) {
1472 tmp
= (u32
) (data
[i
+ 0]);
1474 tmp
|= (u32
) (data
[i
+ 1]) << 8;
1476 tmp
|= (u32
) (data
[i
+ 2]) << 16;
1478 tmp
|= (u32
) (data
[i
+ 3]) << 24;
1479 b43_ram_write(dev
, ram_offset
+ i
- 2, tmp
);
1481 b43_shm_write16(dev
, B43_SHM_SHARED
, shm_size_offset
,
1482 size
+ sizeof(struct b43_plcp_hdr6
));
1485 /* Check if the use of the antenna that ieee80211 told us to
1486 * use is possible. This will fall back to DEFAULT.
1487 * "antenna_nr" is the antenna identifier we got from ieee80211. */
1488 u8
b43_ieee80211_antenna_sanitize(struct b43_wldev
*dev
,
1493 if (antenna_nr
== 0) {
1494 /* Zero means "use default antenna". That's always OK. */
1498 /* Get the mask of available antennas. */
1500 antenna_mask
= dev
->dev
->bus_sprom
->ant_available_bg
;
1502 antenna_mask
= dev
->dev
->bus_sprom
->ant_available_a
;
1504 if (!(antenna_mask
& (1 << (antenna_nr
- 1)))) {
1505 /* This antenna is not available. Fall back to default. */
1512 /* Convert a b43 antenna number value to the PHY TX control value. */
1513 static u16
b43_antenna_to_phyctl(int antenna
)
1517 return B43_TXH_PHY_ANT0
;
1519 return B43_TXH_PHY_ANT1
;
1521 return B43_TXH_PHY_ANT2
;
1523 return B43_TXH_PHY_ANT3
;
1524 case B43_ANTENNA_AUTO0
:
1525 case B43_ANTENNA_AUTO1
:
1526 return B43_TXH_PHY_ANT01AUTO
;
1532 static void b43_write_beacon_template(struct b43_wldev
*dev
,
1534 u16 shm_size_offset
)
1536 unsigned int i
, len
, variable_len
;
1537 const struct ieee80211_mgmt
*bcn
;
1539 bool tim_found
= false;
1543 struct ieee80211_tx_info
*info
= IEEE80211_SKB_CB(dev
->wl
->current_beacon
);
1545 bcn
= (const struct ieee80211_mgmt
*)(dev
->wl
->current_beacon
->data
);
1546 len
= min_t(size_t, dev
->wl
->current_beacon
->len
,
1547 0x200 - sizeof(struct b43_plcp_hdr6
));
1548 rate
= ieee80211_get_tx_rate(dev
->wl
->hw
, info
)->hw_value
;
1550 b43_write_template_common(dev
, (const u8
*)bcn
,
1551 len
, ram_offset
, shm_size_offset
, rate
);
1553 /* Write the PHY TX control parameters. */
1554 antenna
= B43_ANTENNA_DEFAULT
;
1555 antenna
= b43_antenna_to_phyctl(antenna
);
1556 ctl
= b43_shm_read16(dev
, B43_SHM_SHARED
, B43_SHM_SH_BEACPHYCTL
);
1557 /* We can't send beacons with short preamble. Would get PHY errors. */
1558 ctl
&= ~B43_TXH_PHY_SHORTPRMBL
;
1559 ctl
&= ~B43_TXH_PHY_ANT
;
1560 ctl
&= ~B43_TXH_PHY_ENC
;
1562 if (b43_is_cck_rate(rate
))
1563 ctl
|= B43_TXH_PHY_ENC_CCK
;
1565 ctl
|= B43_TXH_PHY_ENC_OFDM
;
1566 b43_shm_write16(dev
, B43_SHM_SHARED
, B43_SHM_SH_BEACPHYCTL
, ctl
);
1568 /* Find the position of the TIM and the DTIM_period value
1569 * and write them to SHM. */
1570 ie
= bcn
->u
.beacon
.variable
;
1571 variable_len
= len
- offsetof(struct ieee80211_mgmt
, u
.beacon
.variable
);
1572 for (i
= 0; i
< variable_len
- 2; ) {
1573 uint8_t ie_id
, ie_len
;
1580 /* This is the TIM Information Element */
1582 /* Check whether the ie_len is in the beacon data range. */
1583 if (variable_len
< ie_len
+ 2 + i
)
1585 /* A valid TIM is at least 4 bytes long. */
1590 tim_position
= sizeof(struct b43_plcp_hdr6
);
1591 tim_position
+= offsetof(struct ieee80211_mgmt
, u
.beacon
.variable
);
1594 dtim_period
= ie
[i
+ 3];
1596 b43_shm_write16(dev
, B43_SHM_SHARED
,
1597 B43_SHM_SH_TIMBPOS
, tim_position
);
1598 b43_shm_write16(dev
, B43_SHM_SHARED
,
1599 B43_SHM_SH_DTIMPER
, dtim_period
);
1606 * If ucode wants to modify TIM do it behind the beacon, this
1607 * will happen, for example, when doing mesh networking.
1609 b43_shm_write16(dev
, B43_SHM_SHARED
,
1611 len
+ sizeof(struct b43_plcp_hdr6
));
1612 b43_shm_write16(dev
, B43_SHM_SHARED
,
1613 B43_SHM_SH_DTIMPER
, 0);
1615 b43dbg(dev
->wl
, "Updated beacon template at 0x%x\n", ram_offset
);
1618 static void b43_upload_beacon0(struct b43_wldev
*dev
)
1620 struct b43_wl
*wl
= dev
->wl
;
1622 if (wl
->beacon0_uploaded
)
1624 b43_write_beacon_template(dev
, B43_SHM_SH_BT_BASE0
, B43_SHM_SH_BTL0
);
1625 wl
->beacon0_uploaded
= true;
1628 static void b43_upload_beacon1(struct b43_wldev
*dev
)
1630 struct b43_wl
*wl
= dev
->wl
;
1632 if (wl
->beacon1_uploaded
)
1634 b43_write_beacon_template(dev
, B43_SHM_SH_BT_BASE1
, B43_SHM_SH_BTL1
);
1635 wl
->beacon1_uploaded
= true;
1638 static void handle_irq_beacon(struct b43_wldev
*dev
)
1640 struct b43_wl
*wl
= dev
->wl
;
1641 u32 cmd
, beacon0_valid
, beacon1_valid
;
1643 if (!b43_is_mode(wl
, NL80211_IFTYPE_AP
) &&
1644 !b43_is_mode(wl
, NL80211_IFTYPE_MESH_POINT
) &&
1645 !b43_is_mode(wl
, NL80211_IFTYPE_ADHOC
))
1648 /* This is the bottom half of the asynchronous beacon update. */
1650 /* Ignore interrupt in the future. */
1651 dev
->irq_mask
&= ~B43_IRQ_BEACON
;
1653 cmd
= b43_read32(dev
, B43_MMIO_MACCMD
);
1654 beacon0_valid
= (cmd
& B43_MACCMD_BEACON0_VALID
);
1655 beacon1_valid
= (cmd
& B43_MACCMD_BEACON1_VALID
);
1657 /* Schedule interrupt manually, if busy. */
1658 if (beacon0_valid
&& beacon1_valid
) {
1659 b43_write32(dev
, B43_MMIO_GEN_IRQ_REASON
, B43_IRQ_BEACON
);
1660 dev
->irq_mask
|= B43_IRQ_BEACON
;
1664 if (unlikely(wl
->beacon_templates_virgin
)) {
1665 /* We never uploaded a beacon before.
1666 * Upload both templates now, but only mark one valid. */
1667 wl
->beacon_templates_virgin
= false;
1668 b43_upload_beacon0(dev
);
1669 b43_upload_beacon1(dev
);
1670 cmd
= b43_read32(dev
, B43_MMIO_MACCMD
);
1671 cmd
|= B43_MACCMD_BEACON0_VALID
;
1672 b43_write32(dev
, B43_MMIO_MACCMD
, cmd
);
1674 if (!beacon0_valid
) {
1675 b43_upload_beacon0(dev
);
1676 cmd
= b43_read32(dev
, B43_MMIO_MACCMD
);
1677 cmd
|= B43_MACCMD_BEACON0_VALID
;
1678 b43_write32(dev
, B43_MMIO_MACCMD
, cmd
);
1679 } else if (!beacon1_valid
) {
1680 b43_upload_beacon1(dev
);
1681 cmd
= b43_read32(dev
, B43_MMIO_MACCMD
);
1682 cmd
|= B43_MACCMD_BEACON1_VALID
;
1683 b43_write32(dev
, B43_MMIO_MACCMD
, cmd
);
1688 static void b43_do_beacon_update_trigger_work(struct b43_wldev
*dev
)
1690 u32 old_irq_mask
= dev
->irq_mask
;
1692 /* update beacon right away or defer to irq */
1693 handle_irq_beacon(dev
);
1694 if (old_irq_mask
!= dev
->irq_mask
) {
1695 /* The handler updated the IRQ mask. */
1696 B43_WARN_ON(!dev
->irq_mask
);
1697 if (b43_read32(dev
, B43_MMIO_GEN_IRQ_MASK
)) {
1698 b43_write32(dev
, B43_MMIO_GEN_IRQ_MASK
, dev
->irq_mask
);
1700 /* Device interrupts are currently disabled. That means
1701 * we just ran the hardirq handler and scheduled the
1702 * IRQ thread. The thread will write the IRQ mask when
1703 * it finished, so there's nothing to do here. Writing
1704 * the mask _here_ would incorrectly re-enable IRQs. */
1709 static void b43_beacon_update_trigger_work(struct work_struct
*work
)
1711 struct b43_wl
*wl
= container_of(work
, struct b43_wl
,
1712 beacon_update_trigger
);
1713 struct b43_wldev
*dev
;
1715 mutex_lock(&wl
->mutex
);
1716 dev
= wl
->current_dev
;
1717 if (likely(dev
&& (b43_status(dev
) >= B43_STAT_INITIALIZED
))) {
1718 if (b43_bus_host_is_sdio(dev
->dev
)) {
1719 /* wl->mutex is enough. */
1720 b43_do_beacon_update_trigger_work(dev
);
1723 spin_lock_irq(&wl
->hardirq_lock
);
1724 b43_do_beacon_update_trigger_work(dev
);
1726 spin_unlock_irq(&wl
->hardirq_lock
);
1729 mutex_unlock(&wl
->mutex
);
1732 /* Asynchronously update the packet templates in template RAM.
1733 * Locking: Requires wl->mutex to be locked. */
1734 static void b43_update_templates(struct b43_wl
*wl
)
1736 struct sk_buff
*beacon
;
1738 /* This is the top half of the ansynchronous beacon update.
1739 * The bottom half is the beacon IRQ.
1740 * Beacon update must be asynchronous to avoid sending an
1741 * invalid beacon. This can happen for example, if the firmware
1742 * transmits a beacon while we are updating it. */
1744 /* We could modify the existing beacon and set the aid bit in
1745 * the TIM field, but that would probably require resizing and
1746 * moving of data within the beacon template.
1747 * Simply request a new beacon and let mac80211 do the hard work. */
1748 beacon
= ieee80211_beacon_get(wl
->hw
, wl
->vif
);
1749 if (unlikely(!beacon
))
1752 if (wl
->current_beacon
)
1753 dev_kfree_skb_any(wl
->current_beacon
);
1754 wl
->current_beacon
= beacon
;
1755 wl
->beacon0_uploaded
= false;
1756 wl
->beacon1_uploaded
= false;
1757 ieee80211_queue_work(wl
->hw
, &wl
->beacon_update_trigger
);
1760 static void b43_set_beacon_int(struct b43_wldev
*dev
, u16 beacon_int
)
1763 if (dev
->dev
->core_rev
>= 3) {
1764 b43_write32(dev
, B43_MMIO_TSF_CFP_REP
, (beacon_int
<< 16));
1765 b43_write32(dev
, B43_MMIO_TSF_CFP_START
, (beacon_int
<< 10));
1767 b43_write16(dev
, 0x606, (beacon_int
>> 6));
1768 b43_write16(dev
, 0x610, beacon_int
);
1770 b43_time_unlock(dev
);
1771 b43dbg(dev
->wl
, "Set beacon interval to %u\n", beacon_int
);
1774 static void b43_handle_firmware_panic(struct b43_wldev
*dev
)
1778 /* Read the register that contains the reason code for the panic. */
1779 reason
= b43_shm_read16(dev
, B43_SHM_SCRATCH
, B43_FWPANIC_REASON_REG
);
1780 b43err(dev
->wl
, "Whoopsy, firmware panic! Reason: %u\n", reason
);
1784 b43dbg(dev
->wl
, "The panic reason is unknown.\n");
1786 case B43_FWPANIC_DIE
:
1787 /* Do not restart the controller or firmware.
1788 * The device is nonfunctional from now on.
1789 * Restarting would result in this panic to trigger again,
1790 * so we avoid that recursion. */
1792 case B43_FWPANIC_RESTART
:
1793 b43_controller_restart(dev
, "Microcode panic");
1798 static void handle_irq_ucode_debug(struct b43_wldev
*dev
)
1800 unsigned int i
, cnt
;
1801 u16 reason
, marker_id
, marker_line
;
1804 /* The proprietary firmware doesn't have this IRQ. */
1805 if (!dev
->fw
.opensource
)
1808 /* Read the register that contains the reason code for this IRQ. */
1809 reason
= b43_shm_read16(dev
, B43_SHM_SCRATCH
, B43_DEBUGIRQ_REASON_REG
);
1812 case B43_DEBUGIRQ_PANIC
:
1813 b43_handle_firmware_panic(dev
);
1815 case B43_DEBUGIRQ_DUMP_SHM
:
1817 break; /* Only with driver debugging enabled. */
1818 buf
= kmalloc(4096, GFP_ATOMIC
);
1820 b43dbg(dev
->wl
, "SHM-dump: Failed to allocate memory\n");
1823 for (i
= 0; i
< 4096; i
+= 2) {
1824 u16 tmp
= b43_shm_read16(dev
, B43_SHM_SHARED
, i
);
1825 buf
[i
/ 2] = cpu_to_le16(tmp
);
1827 b43info(dev
->wl
, "Shared memory dump:\n");
1828 print_hex_dump(KERN_INFO
, "", DUMP_PREFIX_OFFSET
,
1829 16, 2, buf
, 4096, 1);
1832 case B43_DEBUGIRQ_DUMP_REGS
:
1834 break; /* Only with driver debugging enabled. */
1835 b43info(dev
->wl
, "Microcode register dump:\n");
1836 for (i
= 0, cnt
= 0; i
< 64; i
++) {
1837 u16 tmp
= b43_shm_read16(dev
, B43_SHM_SCRATCH
, i
);
1840 printk("r%02u: 0x%04X ", i
, tmp
);
1849 case B43_DEBUGIRQ_MARKER
:
1851 break; /* Only with driver debugging enabled. */
1852 marker_id
= b43_shm_read16(dev
, B43_SHM_SCRATCH
,
1854 marker_line
= b43_shm_read16(dev
, B43_SHM_SCRATCH
,
1855 B43_MARKER_LINE_REG
);
1856 b43info(dev
->wl
, "The firmware just executed the MARKER(%u) "
1857 "at line number %u\n",
1858 marker_id
, marker_line
);
1861 b43dbg(dev
->wl
, "Debug-IRQ triggered for unknown reason: %u\n",
1865 /* Acknowledge the debug-IRQ, so the firmware can continue. */
1866 b43_shm_write16(dev
, B43_SHM_SCRATCH
,
1867 B43_DEBUGIRQ_REASON_REG
, B43_DEBUGIRQ_ACK
);
1870 static void b43_do_interrupt_thread(struct b43_wldev
*dev
)
1873 u32 dma_reason
[ARRAY_SIZE(dev
->dma_reason
)];
1874 u32 merged_dma_reason
= 0;
1877 if (unlikely(b43_status(dev
) != B43_STAT_STARTED
))
1880 reason
= dev
->irq_reason
;
1881 for (i
= 0; i
< ARRAY_SIZE(dma_reason
); i
++) {
1882 dma_reason
[i
] = dev
->dma_reason
[i
];
1883 merged_dma_reason
|= dma_reason
[i
];
1886 if (unlikely(reason
& B43_IRQ_MAC_TXERR
))
1887 b43err(dev
->wl
, "MAC transmission error\n");
1889 if (unlikely(reason
& B43_IRQ_PHY_TXERR
)) {
1890 b43err(dev
->wl
, "PHY transmission error\n");
1892 if (unlikely(atomic_dec_and_test(&dev
->phy
.txerr_cnt
))) {
1893 atomic_set(&dev
->phy
.txerr_cnt
,
1894 B43_PHY_TX_BADNESS_LIMIT
);
1895 b43err(dev
->wl
, "Too many PHY TX errors, "
1896 "restarting the controller\n");
1897 b43_controller_restart(dev
, "PHY TX errors");
1901 if (unlikely(merged_dma_reason
& (B43_DMAIRQ_FATALMASK
))) {
1903 "Fatal DMA error: 0x%08X, 0x%08X, 0x%08X, 0x%08X, 0x%08X, 0x%08X\n",
1904 dma_reason
[0], dma_reason
[1],
1905 dma_reason
[2], dma_reason
[3],
1906 dma_reason
[4], dma_reason
[5]);
1907 b43err(dev
->wl
, "This device does not support DMA "
1908 "on your system. It will now be switched to PIO.\n");
1909 /* Fall back to PIO transfers if we get fatal DMA errors! */
1910 dev
->use_pio
= true;
1911 b43_controller_restart(dev
, "DMA error");
1915 if (unlikely(reason
& B43_IRQ_UCODE_DEBUG
))
1916 handle_irq_ucode_debug(dev
);
1917 if (reason
& B43_IRQ_TBTT_INDI
)
1918 handle_irq_tbtt_indication(dev
);
1919 if (reason
& B43_IRQ_ATIM_END
)
1920 handle_irq_atim_end(dev
);
1921 if (reason
& B43_IRQ_BEACON
)
1922 handle_irq_beacon(dev
);
1923 if (reason
& B43_IRQ_PMQ
)
1924 handle_irq_pmq(dev
);
1925 if (reason
& B43_IRQ_TXFIFO_FLUSH_OK
)
1927 if (reason
& B43_IRQ_NOISESAMPLE_OK
)
1928 handle_irq_noise(dev
);
1930 /* Check the DMA reason registers for received data. */
1931 if (dma_reason
[0] & B43_DMAIRQ_RDESC_UFLOW
) {
1933 b43warn(dev
->wl
, "RX descriptor underrun\n");
1934 b43_dma_handle_rx_overflow(dev
->dma
.rx_ring
);
1936 if (dma_reason
[0] & B43_DMAIRQ_RX_DONE
) {
1937 if (b43_using_pio_transfers(dev
))
1938 b43_pio_rx(dev
->pio
.rx_queue
);
1940 b43_dma_rx(dev
->dma
.rx_ring
);
1942 B43_WARN_ON(dma_reason
[1] & B43_DMAIRQ_RX_DONE
);
1943 B43_WARN_ON(dma_reason
[2] & B43_DMAIRQ_RX_DONE
);
1944 B43_WARN_ON(dma_reason
[3] & B43_DMAIRQ_RX_DONE
);
1945 B43_WARN_ON(dma_reason
[4] & B43_DMAIRQ_RX_DONE
);
1946 B43_WARN_ON(dma_reason
[5] & B43_DMAIRQ_RX_DONE
);
1948 if (reason
& B43_IRQ_TX_OK
)
1949 handle_irq_transmit_status(dev
);
1951 /* Re-enable interrupts on the device by restoring the current interrupt mask. */
1952 b43_write32(dev
, B43_MMIO_GEN_IRQ_MASK
, dev
->irq_mask
);
1955 if (b43_debug(dev
, B43_DBG_VERBOSESTATS
)) {
1957 for (i
= 0; i
< ARRAY_SIZE(dev
->irq_bit_count
); i
++) {
1958 if (reason
& (1 << i
))
1959 dev
->irq_bit_count
[i
]++;
1965 /* Interrupt thread handler. Handles device interrupts in thread context. */
1966 static irqreturn_t
b43_interrupt_thread_handler(int irq
, void *dev_id
)
1968 struct b43_wldev
*dev
= dev_id
;
1970 mutex_lock(&dev
->wl
->mutex
);
1971 b43_do_interrupt_thread(dev
);
1973 mutex_unlock(&dev
->wl
->mutex
);
1978 static irqreturn_t
b43_do_interrupt(struct b43_wldev
*dev
)
1982 /* This code runs under wl->hardirq_lock, but _only_ on non-SDIO busses.
1983 * On SDIO, this runs under wl->mutex. */
1985 reason
= b43_read32(dev
, B43_MMIO_GEN_IRQ_REASON
);
1986 if (reason
== 0xffffffff) /* shared IRQ */
1988 reason
&= dev
->irq_mask
;
1992 dev
->dma_reason
[0] = b43_read32(dev
, B43_MMIO_DMA0_REASON
)
1994 dev
->dma_reason
[1] = b43_read32(dev
, B43_MMIO_DMA1_REASON
)
1996 dev
->dma_reason
[2] = b43_read32(dev
, B43_MMIO_DMA2_REASON
)
1998 dev
->dma_reason
[3] = b43_read32(dev
, B43_MMIO_DMA3_REASON
)
2000 dev
->dma_reason
[4] = b43_read32(dev
, B43_MMIO_DMA4_REASON
)
2003 dev->dma_reason[5] = b43_read32(dev, B43_MMIO_DMA5_REASON)
2007 /* ACK the interrupt. */
2008 b43_write32(dev
, B43_MMIO_GEN_IRQ_REASON
, reason
);
2009 b43_write32(dev
, B43_MMIO_DMA0_REASON
, dev
->dma_reason
[0]);
2010 b43_write32(dev
, B43_MMIO_DMA1_REASON
, dev
->dma_reason
[1]);
2011 b43_write32(dev
, B43_MMIO_DMA2_REASON
, dev
->dma_reason
[2]);
2012 b43_write32(dev
, B43_MMIO_DMA3_REASON
, dev
->dma_reason
[3]);
2013 b43_write32(dev
, B43_MMIO_DMA4_REASON
, dev
->dma_reason
[4]);
2015 b43_write32(dev, B43_MMIO_DMA5_REASON, dev->dma_reason[5]);
2018 /* Disable IRQs on the device. The IRQ thread handler will re-enable them. */
2019 b43_write32(dev
, B43_MMIO_GEN_IRQ_MASK
, 0);
2020 /* Save the reason bitmasks for the IRQ thread handler. */
2021 dev
->irq_reason
= reason
;
2023 return IRQ_WAKE_THREAD
;
2026 /* Interrupt handler top-half. This runs with interrupts disabled. */
2027 static irqreturn_t
b43_interrupt_handler(int irq
, void *dev_id
)
2029 struct b43_wldev
*dev
= dev_id
;
2032 if (unlikely(b43_status(dev
) < B43_STAT_STARTED
))
2035 spin_lock(&dev
->wl
->hardirq_lock
);
2036 ret
= b43_do_interrupt(dev
);
2038 spin_unlock(&dev
->wl
->hardirq_lock
);
2043 /* SDIO interrupt handler. This runs in process context. */
2044 static void b43_sdio_interrupt_handler(struct b43_wldev
*dev
)
2046 struct b43_wl
*wl
= dev
->wl
;
2049 mutex_lock(&wl
->mutex
);
2051 ret
= b43_do_interrupt(dev
);
2052 if (ret
== IRQ_WAKE_THREAD
)
2053 b43_do_interrupt_thread(dev
);
2055 mutex_unlock(&wl
->mutex
);
2058 void b43_do_release_fw(struct b43_firmware_file
*fw
)
2060 release_firmware(fw
->data
);
2062 fw
->filename
= NULL
;
2065 static void b43_release_firmware(struct b43_wldev
*dev
)
2067 complete(&dev
->fw_load_complete
);
2068 b43_do_release_fw(&dev
->fw
.ucode
);
2069 b43_do_release_fw(&dev
->fw
.pcm
);
2070 b43_do_release_fw(&dev
->fw
.initvals
);
2071 b43_do_release_fw(&dev
->fw
.initvals_band
);
2074 static void b43_print_fw_helptext(struct b43_wl
*wl
, bool error
)
2078 "http://wireless.kernel.org/en/users/Drivers/b43#devicefirmware " \
2079 "and download the correct firmware for this driver version. " \
2080 "Please carefully read all instructions on this website.\n";
2088 static void b43_fw_cb(const struct firmware
*firmware
, void *context
)
2090 struct b43_request_fw_context
*ctx
= context
;
2092 ctx
->blob
= firmware
;
2093 complete(&ctx
->dev
->fw_load_complete
);
2096 int b43_do_request_fw(struct b43_request_fw_context
*ctx
,
2098 struct b43_firmware_file
*fw
, bool async
)
2100 struct b43_fw_header
*hdr
;
2105 /* Don't fetch anything. Free possibly cached firmware. */
2106 /* FIXME: We should probably keep it anyway, to save some headache
2107 * on suspend/resume with multiband devices. */
2108 b43_do_release_fw(fw
);
2112 if ((fw
->type
== ctx
->req_type
) &&
2113 (strcmp(fw
->filename
, name
) == 0))
2114 return 0; /* Already have this fw. */
2115 /* Free the cached firmware first. */
2116 /* FIXME: We should probably do this later after we successfully
2117 * got the new fw. This could reduce headache with multiband devices.
2118 * We could also redesign this to cache the firmware for all possible
2119 * bands all the time. */
2120 b43_do_release_fw(fw
);
2123 switch (ctx
->req_type
) {
2124 case B43_FWTYPE_PROPRIETARY
:
2125 snprintf(ctx
->fwname
, sizeof(ctx
->fwname
),
2127 modparam_fwpostfix
, name
);
2129 case B43_FWTYPE_OPENSOURCE
:
2130 snprintf(ctx
->fwname
, sizeof(ctx
->fwname
),
2132 modparam_fwpostfix
, name
);
2139 /* do this part asynchronously */
2140 init_completion(&ctx
->dev
->fw_load_complete
);
2141 err
= request_firmware_nowait(THIS_MODULE
, 1, ctx
->fwname
,
2142 ctx
->dev
->dev
->dev
, GFP_KERNEL
,
2145 pr_err("Unable to load firmware\n");
2148 wait_for_completion(&ctx
->dev
->fw_load_complete
);
2151 /* On some ARM systems, the async request will fail, but the next sync
2152 * request works. For this reason, we fall through here
2155 err
= request_firmware(&ctx
->blob
, ctx
->fwname
,
2156 ctx
->dev
->dev
->dev
);
2157 if (err
== -ENOENT
) {
2158 snprintf(ctx
->errors
[ctx
->req_type
],
2159 sizeof(ctx
->errors
[ctx
->req_type
]),
2160 "Firmware file \"%s\" not found\n",
2164 snprintf(ctx
->errors
[ctx
->req_type
],
2165 sizeof(ctx
->errors
[ctx
->req_type
]),
2166 "Firmware file \"%s\" request failed (err=%d)\n",
2171 if (ctx
->blob
->size
< sizeof(struct b43_fw_header
))
2173 hdr
= (struct b43_fw_header
*)(ctx
->blob
->data
);
2174 switch (hdr
->type
) {
2175 case B43_FW_TYPE_UCODE
:
2176 case B43_FW_TYPE_PCM
:
2177 size
= be32_to_cpu(hdr
->size
);
2178 if (size
!= ctx
->blob
->size
- sizeof(struct b43_fw_header
))
2181 case B43_FW_TYPE_IV
:
2189 fw
->data
= ctx
->blob
;
2190 fw
->filename
= name
;
2191 fw
->type
= ctx
->req_type
;
2196 snprintf(ctx
->errors
[ctx
->req_type
],
2197 sizeof(ctx
->errors
[ctx
->req_type
]),
2198 "Firmware file \"%s\" format error.\n", ctx
->fwname
);
2199 release_firmware(ctx
->blob
);
2204 static int b43_try_request_fw(struct b43_request_fw_context
*ctx
)
2206 struct b43_wldev
*dev
= ctx
->dev
;
2207 struct b43_firmware
*fw
= &ctx
->dev
->fw
;
2208 const u8 rev
= ctx
->dev
->dev
->core_rev
;
2209 const char *filename
;
2213 /* Files for HT and LCN were found by trying one by one */
2216 if ((rev
>= 5) && (rev
<= 10)) {
2217 filename
= "ucode5";
2218 } else if ((rev
>= 11) && (rev
<= 12)) {
2219 filename
= "ucode11";
2220 } else if (rev
== 13) {
2221 filename
= "ucode13";
2222 } else if (rev
== 14) {
2223 filename
= "ucode14";
2224 } else if (rev
== 15) {
2225 filename
= "ucode15";
2227 switch (dev
->phy
.type
) {
2230 filename
= "ucode16_mimo";
2234 case B43_PHYTYPE_HT
:
2236 filename
= "ucode29_mimo";
2240 case B43_PHYTYPE_LCN
:
2242 filename
= "ucode24_mimo";
2250 err
= b43_do_request_fw(ctx
, filename
, &fw
->ucode
, true);
2255 if ((rev
>= 5) && (rev
<= 10))
2261 fw
->pcm_request_failed
= false;
2262 err
= b43_do_request_fw(ctx
, filename
, &fw
->pcm
, false);
2263 if (err
== -ENOENT
) {
2264 /* We did not find a PCM file? Not fatal, but
2265 * core rev <= 10 must do without hwcrypto then. */
2266 fw
->pcm_request_failed
= true;
2271 switch (dev
->phy
.type
) {
2273 if ((rev
>= 5) && (rev
<= 10)) {
2274 tmshigh
= ssb_read32(dev
->dev
->sdev
, SSB_TMSHIGH
);
2275 if (tmshigh
& B43_TMSHIGH_HAVE_2GHZ_PHY
)
2276 filename
= "a0g1initvals5";
2278 filename
= "a0g0initvals5";
2280 goto err_no_initvals
;
2283 if ((rev
>= 5) && (rev
<= 10))
2284 filename
= "b0g0initvals5";
2286 filename
= "b0g0initvals13";
2288 goto err_no_initvals
;
2292 filename
= "n0initvals16";
2293 else if ((rev
>= 11) && (rev
<= 12))
2294 filename
= "n0initvals11";
2296 goto err_no_initvals
;
2298 case B43_PHYTYPE_LP
:
2300 filename
= "lp0initvals13";
2302 filename
= "lp0initvals14";
2304 filename
= "lp0initvals15";
2306 goto err_no_initvals
;
2308 case B43_PHYTYPE_HT
:
2310 filename
= "ht0initvals29";
2312 goto err_no_initvals
;
2314 case B43_PHYTYPE_LCN
:
2316 filename
= "lcn0initvals24";
2318 goto err_no_initvals
;
2321 goto err_no_initvals
;
2323 err
= b43_do_request_fw(ctx
, filename
, &fw
->initvals
, false);
2327 /* Get bandswitch initvals */
2328 switch (dev
->phy
.type
) {
2330 if ((rev
>= 5) && (rev
<= 10)) {
2331 tmshigh
= ssb_read32(dev
->dev
->sdev
, SSB_TMSHIGH
);
2332 if (tmshigh
& B43_TMSHIGH_HAVE_2GHZ_PHY
)
2333 filename
= "a0g1bsinitvals5";
2335 filename
= "a0g0bsinitvals5";
2336 } else if (rev
>= 11)
2339 goto err_no_initvals
;
2342 if ((rev
>= 5) && (rev
<= 10))
2343 filename
= "b0g0bsinitvals5";
2347 goto err_no_initvals
;
2351 filename
= "n0bsinitvals16";
2352 else if ((rev
>= 11) && (rev
<= 12))
2353 filename
= "n0bsinitvals11";
2355 goto err_no_initvals
;
2357 case B43_PHYTYPE_LP
:
2359 filename
= "lp0bsinitvals13";
2361 filename
= "lp0bsinitvals14";
2363 filename
= "lp0bsinitvals15";
2365 goto err_no_initvals
;
2367 case B43_PHYTYPE_HT
:
2369 filename
= "ht0bsinitvals29";
2371 goto err_no_initvals
;
2373 case B43_PHYTYPE_LCN
:
2375 filename
= "lcn0bsinitvals24";
2377 goto err_no_initvals
;
2380 goto err_no_initvals
;
2382 err
= b43_do_request_fw(ctx
, filename
, &fw
->initvals_band
, false);
2386 fw
->opensource
= (ctx
->req_type
== B43_FWTYPE_OPENSOURCE
);
2391 err
= ctx
->fatal_failure
= -EOPNOTSUPP
;
2392 b43err(dev
->wl
, "The driver does not know which firmware (ucode) "
2393 "is required for your device (wl-core rev %u)\n", rev
);
2397 err
= ctx
->fatal_failure
= -EOPNOTSUPP
;
2398 b43err(dev
->wl
, "The driver does not know which firmware (PCM) "
2399 "is required for your device (wl-core rev %u)\n", rev
);
2403 err
= ctx
->fatal_failure
= -EOPNOTSUPP
;
2404 b43err(dev
->wl
, "The driver does not know which firmware (initvals) "
2405 "is required for your device (wl-core rev %u)\n", rev
);
2409 /* We failed to load this firmware image. The error message
2410 * already is in ctx->errors. Return and let our caller decide
2415 b43_release_firmware(dev
);
2419 static int b43_one_core_attach(struct b43_bus_dev
*dev
, struct b43_wl
*wl
);
2420 static void b43_one_core_detach(struct b43_bus_dev
*dev
);
2421 static int b43_rng_init(struct b43_wl
*wl
);
2423 static void b43_request_firmware(struct work_struct
*work
)
2425 struct b43_wl
*wl
= container_of(work
,
2426 struct b43_wl
, firmware_load
);
2427 struct b43_wldev
*dev
= wl
->current_dev
;
2428 struct b43_request_fw_context
*ctx
;
2433 ctx
= kzalloc(sizeof(*ctx
), GFP_KERNEL
);
2438 ctx
->req_type
= B43_FWTYPE_PROPRIETARY
;
2439 err
= b43_try_request_fw(ctx
);
2441 goto start_ieee80211
; /* Successfully loaded it. */
2442 /* Was fw version known? */
2443 if (ctx
->fatal_failure
)
2446 /* proprietary fw not found, try open source */
2447 ctx
->req_type
= B43_FWTYPE_OPENSOURCE
;
2448 err
= b43_try_request_fw(ctx
);
2450 goto start_ieee80211
; /* Successfully loaded it. */
2451 if(ctx
->fatal_failure
)
2454 /* Could not find a usable firmware. Print the errors. */
2455 for (i
= 0; i
< B43_NR_FWTYPES
; i
++) {
2456 errmsg
= ctx
->errors
[i
];
2458 b43err(dev
->wl
, "%s", errmsg
);
2460 b43_print_fw_helptext(dev
->wl
, 1);
2464 wl
->hw
->queues
= B43_QOS_QUEUE_NUM
;
2465 if (!modparam_qos
|| dev
->fw
.opensource
)
2468 err
= ieee80211_register_hw(wl
->hw
);
2470 goto err_one_core_detach
;
2471 wl
->hw_registred
= true;
2472 b43_leds_register(wl
->current_dev
);
2474 /* Register HW RNG driver */
2479 err_one_core_detach
:
2480 b43_one_core_detach(dev
->dev
);
2486 static int b43_upload_microcode(struct b43_wldev
*dev
)
2488 struct wiphy
*wiphy
= dev
->wl
->hw
->wiphy
;
2489 const size_t hdr_len
= sizeof(struct b43_fw_header
);
2491 unsigned int i
, len
;
2492 u16 fwrev
, fwpatch
, fwdate
, fwtime
;
2496 /* Jump the microcode PSM to offset 0 */
2497 macctl
= b43_read32(dev
, B43_MMIO_MACCTL
);
2498 B43_WARN_ON(macctl
& B43_MACCTL_PSM_RUN
);
2499 macctl
|= B43_MACCTL_PSM_JMP0
;
2500 b43_write32(dev
, B43_MMIO_MACCTL
, macctl
);
2501 /* Zero out all microcode PSM registers and shared memory. */
2502 for (i
= 0; i
< 64; i
++)
2503 b43_shm_write16(dev
, B43_SHM_SCRATCH
, i
, 0);
2504 for (i
= 0; i
< 4096; i
+= 2)
2505 b43_shm_write16(dev
, B43_SHM_SHARED
, i
, 0);
2507 /* Upload Microcode. */
2508 data
= (__be32
*) (dev
->fw
.ucode
.data
->data
+ hdr_len
);
2509 len
= (dev
->fw
.ucode
.data
->size
- hdr_len
) / sizeof(__be32
);
2510 b43_shm_control_word(dev
, B43_SHM_UCODE
| B43_SHM_AUTOINC_W
, 0x0000);
2511 for (i
= 0; i
< len
; i
++) {
2512 b43_write32(dev
, B43_MMIO_SHM_DATA
, be32_to_cpu(data
[i
]));
2516 if (dev
->fw
.pcm
.data
) {
2517 /* Upload PCM data. */
2518 data
= (__be32
*) (dev
->fw
.pcm
.data
->data
+ hdr_len
);
2519 len
= (dev
->fw
.pcm
.data
->size
- hdr_len
) / sizeof(__be32
);
2520 b43_shm_control_word(dev
, B43_SHM_HW
, 0x01EA);
2521 b43_write32(dev
, B43_MMIO_SHM_DATA
, 0x00004000);
2522 /* No need for autoinc bit in SHM_HW */
2523 b43_shm_control_word(dev
, B43_SHM_HW
, 0x01EB);
2524 for (i
= 0; i
< len
; i
++) {
2525 b43_write32(dev
, B43_MMIO_SHM_DATA
, be32_to_cpu(data
[i
]));
2530 b43_write32(dev
, B43_MMIO_GEN_IRQ_REASON
, B43_IRQ_ALL
);
2532 /* Start the microcode PSM */
2533 b43_maskset32(dev
, B43_MMIO_MACCTL
, ~B43_MACCTL_PSM_JMP0
,
2534 B43_MACCTL_PSM_RUN
);
2536 /* Wait for the microcode to load and respond */
2539 tmp
= b43_read32(dev
, B43_MMIO_GEN_IRQ_REASON
);
2540 if (tmp
== B43_IRQ_MAC_SUSPENDED
)
2544 b43err(dev
->wl
, "Microcode not responding\n");
2545 b43_print_fw_helptext(dev
->wl
, 1);
2551 b43_read32(dev
, B43_MMIO_GEN_IRQ_REASON
); /* dummy read */
2553 /* Get and check the revisions. */
2554 fwrev
= b43_shm_read16(dev
, B43_SHM_SHARED
, B43_SHM_SH_UCODEREV
);
2555 fwpatch
= b43_shm_read16(dev
, B43_SHM_SHARED
, B43_SHM_SH_UCODEPATCH
);
2556 fwdate
= b43_shm_read16(dev
, B43_SHM_SHARED
, B43_SHM_SH_UCODEDATE
);
2557 fwtime
= b43_shm_read16(dev
, B43_SHM_SHARED
, B43_SHM_SH_UCODETIME
);
2559 if (fwrev
<= 0x128) {
2560 b43err(dev
->wl
, "YOUR FIRMWARE IS TOO OLD. Firmware from "
2561 "binary drivers older than version 4.x is unsupported. "
2562 "You must upgrade your firmware files.\n");
2563 b43_print_fw_helptext(dev
->wl
, 1);
2567 dev
->fw
.rev
= fwrev
;
2568 dev
->fw
.patch
= fwpatch
;
2569 if (dev
->fw
.rev
>= 598)
2570 dev
->fw
.hdr_format
= B43_FW_HDR_598
;
2571 else if (dev
->fw
.rev
>= 410)
2572 dev
->fw
.hdr_format
= B43_FW_HDR_410
;
2574 dev
->fw
.hdr_format
= B43_FW_HDR_351
;
2575 WARN_ON(dev
->fw
.opensource
!= (fwdate
== 0xFFFF));
2577 dev
->qos_enabled
= dev
->wl
->hw
->queues
> 1;
2578 /* Default to firmware/hardware crypto acceleration. */
2579 dev
->hwcrypto_enabled
= true;
2581 if (dev
->fw
.opensource
) {
2584 /* Patchlevel info is encoded in the "time" field. */
2585 dev
->fw
.patch
= fwtime
;
2586 b43info(dev
->wl
, "Loading OpenSource firmware version %u.%u\n",
2587 dev
->fw
.rev
, dev
->fw
.patch
);
2589 fwcapa
= b43_fwcapa_read(dev
);
2590 if (!(fwcapa
& B43_FWCAPA_HWCRYPTO
) || dev
->fw
.pcm_request_failed
) {
2591 b43info(dev
->wl
, "Hardware crypto acceleration not supported by firmware\n");
2592 /* Disable hardware crypto and fall back to software crypto. */
2593 dev
->hwcrypto_enabled
= false;
2595 /* adding QoS support should use an offline discovery mechanism */
2596 WARN(fwcapa
& B43_FWCAPA_QOS
, "QoS in OpenFW not supported\n");
2598 b43info(dev
->wl
, "Loading firmware version %u.%u "
2599 "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n",
2601 (fwdate
>> 12) & 0xF, (fwdate
>> 8) & 0xF, fwdate
& 0xFF,
2602 (fwtime
>> 11) & 0x1F, (fwtime
>> 5) & 0x3F, fwtime
& 0x1F);
2603 if (dev
->fw
.pcm_request_failed
) {
2604 b43warn(dev
->wl
, "No \"pcm5.fw\" firmware file found. "
2605 "Hardware accelerated cryptography is disabled.\n");
2606 b43_print_fw_helptext(dev
->wl
, 0);
2610 snprintf(wiphy
->fw_version
, sizeof(wiphy
->fw_version
), "%u.%u",
2611 dev
->fw
.rev
, dev
->fw
.patch
);
2612 wiphy
->hw_version
= dev
->dev
->core_id
;
2614 if (dev
->fw
.hdr_format
== B43_FW_HDR_351
) {
2615 /* We're over the deadline, but we keep support for old fw
2616 * until it turns out to be in major conflict with something new. */
2617 b43warn(dev
->wl
, "You are using an old firmware image. "
2618 "Support for old firmware will be removed soon "
2619 "(official deadline was July 2008).\n");
2620 b43_print_fw_helptext(dev
->wl
, 0);
2626 /* Stop the microcode PSM. */
2627 b43_maskset32(dev
, B43_MMIO_MACCTL
, ~B43_MACCTL_PSM_RUN
,
2628 B43_MACCTL_PSM_JMP0
);
2633 static int b43_write_initvals(struct b43_wldev
*dev
,
2634 const struct b43_iv
*ivals
,
2638 const struct b43_iv
*iv
;
2643 BUILD_BUG_ON(sizeof(struct b43_iv
) != 6);
2645 for (i
= 0; i
< count
; i
++) {
2646 if (array_size
< sizeof(iv
->offset_size
))
2648 array_size
-= sizeof(iv
->offset_size
);
2649 offset
= be16_to_cpu(iv
->offset_size
);
2650 bit32
= !!(offset
& B43_IV_32BIT
);
2651 offset
&= B43_IV_OFFSET_MASK
;
2652 if (offset
>= 0x1000)
2657 if (array_size
< sizeof(iv
->data
.d32
))
2659 array_size
-= sizeof(iv
->data
.d32
);
2661 value
= get_unaligned_be32(&iv
->data
.d32
);
2662 b43_write32(dev
, offset
, value
);
2664 iv
= (const struct b43_iv
*)((const uint8_t *)iv
+
2670 if (array_size
< sizeof(iv
->data
.d16
))
2672 array_size
-= sizeof(iv
->data
.d16
);
2674 value
= be16_to_cpu(iv
->data
.d16
);
2675 b43_write16(dev
, offset
, value
);
2677 iv
= (const struct b43_iv
*)((const uint8_t *)iv
+
2688 b43err(dev
->wl
, "Initial Values Firmware file-format error.\n");
2689 b43_print_fw_helptext(dev
->wl
, 1);
2694 static int b43_upload_initvals(struct b43_wldev
*dev
)
2696 const size_t hdr_len
= sizeof(struct b43_fw_header
);
2697 const struct b43_fw_header
*hdr
;
2698 struct b43_firmware
*fw
= &dev
->fw
;
2699 const struct b43_iv
*ivals
;
2702 hdr
= (const struct b43_fw_header
*)(fw
->initvals
.data
->data
);
2703 ivals
= (const struct b43_iv
*)(fw
->initvals
.data
->data
+ hdr_len
);
2704 count
= be32_to_cpu(hdr
->size
);
2705 return b43_write_initvals(dev
, ivals
, count
,
2706 fw
->initvals
.data
->size
- hdr_len
);
2709 static int b43_upload_initvals_band(struct b43_wldev
*dev
)
2711 const size_t hdr_len
= sizeof(struct b43_fw_header
);
2712 const struct b43_fw_header
*hdr
;
2713 struct b43_firmware
*fw
= &dev
->fw
;
2714 const struct b43_iv
*ivals
;
2717 if (!fw
->initvals_band
.data
)
2720 hdr
= (const struct b43_fw_header
*)(fw
->initvals_band
.data
->data
);
2721 ivals
= (const struct b43_iv
*)(fw
->initvals_band
.data
->data
+ hdr_len
);
2722 count
= be32_to_cpu(hdr
->size
);
2723 return b43_write_initvals(dev
, ivals
, count
,
2724 fw
->initvals_band
.data
->size
- hdr_len
);
2727 /* Initialize the GPIOs
2728 * http://bcm-specs.sipsolutions.net/GPIO
2731 #ifdef CONFIG_B43_SSB
2732 static struct ssb_device
*b43_ssb_gpio_dev(struct b43_wldev
*dev
)
2734 struct ssb_bus
*bus
= dev
->dev
->sdev
->bus
;
2736 #ifdef CONFIG_SSB_DRIVER_PCICORE
2737 return (bus
->chipco
.dev
? bus
->chipco
.dev
: bus
->pcicore
.dev
);
2739 return bus
->chipco
.dev
;
2744 static int b43_gpio_init(struct b43_wldev
*dev
)
2746 #ifdef CONFIG_B43_SSB
2747 struct ssb_device
*gpiodev
;
2751 b43_maskset32(dev
, B43_MMIO_MACCTL
, ~B43_MACCTL_GPOUTSMSK
, 0);
2752 b43_maskset16(dev
, B43_MMIO_GPIO_MASK
, ~0, 0xF);
2756 if (dev
->dev
->chip_id
== 0x4301) {
2759 } else if (dev
->dev
->chip_id
== 0x5354) {
2760 /* Don't allow overtaking buttons GPIOs */
2761 set
&= 0x2; /* 0x2 is LED GPIO on BCM5354 */
2764 if (0 /* FIXME: conditional unknown */ ) {
2765 b43_write16(dev
, B43_MMIO_GPIO_MASK
,
2766 b43_read16(dev
, B43_MMIO_GPIO_MASK
)
2768 /* BT Coexistance Input */
2771 /* BT Coexistance Out */
2775 if (dev
->dev
->bus_sprom
->boardflags_lo
& B43_BFL_PACTRL
) {
2776 /* PA is controlled by gpio 9, let ucode handle it */
2777 b43_write16(dev
, B43_MMIO_GPIO_MASK
,
2778 b43_read16(dev
, B43_MMIO_GPIO_MASK
)
2784 switch (dev
->dev
->bus_type
) {
2785 #ifdef CONFIG_B43_BCMA
2787 bcma_chipco_gpio_control(&dev
->dev
->bdev
->bus
->drv_cc
, mask
, set
);
2790 #ifdef CONFIG_B43_SSB
2792 gpiodev
= b43_ssb_gpio_dev(dev
);
2794 ssb_write32(gpiodev
, B43_GPIO_CONTROL
,
2795 (ssb_read32(gpiodev
, B43_GPIO_CONTROL
)
2804 /* Turn off all GPIO stuff. Call this on module unload, for example. */
2805 static void b43_gpio_cleanup(struct b43_wldev
*dev
)
2807 #ifdef CONFIG_B43_SSB
2808 struct ssb_device
*gpiodev
;
2811 switch (dev
->dev
->bus_type
) {
2812 #ifdef CONFIG_B43_BCMA
2814 bcma_chipco_gpio_control(&dev
->dev
->bdev
->bus
->drv_cc
, ~0, 0);
2817 #ifdef CONFIG_B43_SSB
2819 gpiodev
= b43_ssb_gpio_dev(dev
);
2821 ssb_write32(gpiodev
, B43_GPIO_CONTROL
, 0);
2827 /* http://bcm-specs.sipsolutions.net/EnableMac */
2828 void b43_mac_enable(struct b43_wldev
*dev
)
2830 if (b43_debug(dev
, B43_DBG_FIRMWARE
)) {
2833 fwstate
= b43_shm_read16(dev
, B43_SHM_SHARED
,
2834 B43_SHM_SH_UCODESTAT
);
2835 if ((fwstate
!= B43_SHM_SH_UCODESTAT_SUSP
) &&
2836 (fwstate
!= B43_SHM_SH_UCODESTAT_SLEEP
)) {
2837 b43err(dev
->wl
, "b43_mac_enable(): The firmware "
2838 "should be suspended, but current state is %u\n",
2843 dev
->mac_suspended
--;
2844 B43_WARN_ON(dev
->mac_suspended
< 0);
2845 if (dev
->mac_suspended
== 0) {
2846 b43_maskset32(dev
, B43_MMIO_MACCTL
, ~0, B43_MACCTL_ENABLED
);
2847 b43_write32(dev
, B43_MMIO_GEN_IRQ_REASON
,
2848 B43_IRQ_MAC_SUSPENDED
);
2850 b43_read32(dev
, B43_MMIO_MACCTL
);
2851 b43_read32(dev
, B43_MMIO_GEN_IRQ_REASON
);
2852 b43_power_saving_ctl_bits(dev
, 0);
2856 /* http://bcm-specs.sipsolutions.net/SuspendMAC */
2857 void b43_mac_suspend(struct b43_wldev
*dev
)
2863 B43_WARN_ON(dev
->mac_suspended
< 0);
2865 if (dev
->mac_suspended
== 0) {
2866 b43_power_saving_ctl_bits(dev
, B43_PS_AWAKE
);
2867 b43_maskset32(dev
, B43_MMIO_MACCTL
, ~B43_MACCTL_ENABLED
, 0);
2868 /* force pci to flush the write */
2869 b43_read32(dev
, B43_MMIO_MACCTL
);
2870 for (i
= 35; i
; i
--) {
2871 tmp
= b43_read32(dev
, B43_MMIO_GEN_IRQ_REASON
);
2872 if (tmp
& B43_IRQ_MAC_SUSPENDED
)
2876 /* Hm, it seems this will take some time. Use msleep(). */
2877 for (i
= 40; i
; i
--) {
2878 tmp
= b43_read32(dev
, B43_MMIO_GEN_IRQ_REASON
);
2879 if (tmp
& B43_IRQ_MAC_SUSPENDED
)
2883 b43err(dev
->wl
, "MAC suspend failed\n");
2886 dev
->mac_suspended
++;
2889 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MacPhyClkSet */
2890 void b43_mac_phy_clock_set(struct b43_wldev
*dev
, bool on
)
2894 switch (dev
->dev
->bus_type
) {
2895 #ifdef CONFIG_B43_BCMA
2897 tmp
= bcma_aread32(dev
->dev
->bdev
, BCMA_IOCTL
);
2899 tmp
|= B43_BCMA_IOCTL_MACPHYCLKEN
;
2901 tmp
&= ~B43_BCMA_IOCTL_MACPHYCLKEN
;
2902 bcma_awrite32(dev
->dev
->bdev
, BCMA_IOCTL
, tmp
);
2905 #ifdef CONFIG_B43_SSB
2907 tmp
= ssb_read32(dev
->dev
->sdev
, SSB_TMSLOW
);
2909 tmp
|= B43_TMSLOW_MACPHYCLKEN
;
2911 tmp
&= ~B43_TMSLOW_MACPHYCLKEN
;
2912 ssb_write32(dev
->dev
->sdev
, SSB_TMSLOW
, tmp
);
2918 static void b43_adjust_opmode(struct b43_wldev
*dev
)
2920 struct b43_wl
*wl
= dev
->wl
;
2924 ctl
= b43_read32(dev
, B43_MMIO_MACCTL
);
2925 /* Reset status to STA infrastructure mode. */
2926 ctl
&= ~B43_MACCTL_AP
;
2927 ctl
&= ~B43_MACCTL_KEEP_CTL
;
2928 ctl
&= ~B43_MACCTL_KEEP_BADPLCP
;
2929 ctl
&= ~B43_MACCTL_KEEP_BAD
;
2930 ctl
&= ~B43_MACCTL_PROMISC
;
2931 ctl
&= ~B43_MACCTL_BEACPROMISC
;
2932 ctl
|= B43_MACCTL_INFRA
;
2934 if (b43_is_mode(wl
, NL80211_IFTYPE_AP
) ||
2935 b43_is_mode(wl
, NL80211_IFTYPE_MESH_POINT
))
2936 ctl
|= B43_MACCTL_AP
;
2937 else if (b43_is_mode(wl
, NL80211_IFTYPE_ADHOC
))
2938 ctl
&= ~B43_MACCTL_INFRA
;
2940 if (wl
->filter_flags
& FIF_CONTROL
)
2941 ctl
|= B43_MACCTL_KEEP_CTL
;
2942 if (wl
->filter_flags
& FIF_FCSFAIL
)
2943 ctl
|= B43_MACCTL_KEEP_BAD
;
2944 if (wl
->filter_flags
& FIF_PLCPFAIL
)
2945 ctl
|= B43_MACCTL_KEEP_BADPLCP
;
2946 if (wl
->filter_flags
& FIF_PROMISC_IN_BSS
)
2947 ctl
|= B43_MACCTL_PROMISC
;
2948 if (wl
->filter_flags
& FIF_BCN_PRBRESP_PROMISC
)
2949 ctl
|= B43_MACCTL_BEACPROMISC
;
2951 /* Workaround: On old hardware the HW-MAC-address-filter
2952 * doesn't work properly, so always run promisc in filter
2953 * it in software. */
2954 if (dev
->dev
->core_rev
<= 4)
2955 ctl
|= B43_MACCTL_PROMISC
;
2957 b43_write32(dev
, B43_MMIO_MACCTL
, ctl
);
2960 if ((ctl
& B43_MACCTL_INFRA
) && !(ctl
& B43_MACCTL_AP
)) {
2961 if (dev
->dev
->chip_id
== 0x4306 &&
2962 dev
->dev
->chip_rev
== 3)
2967 b43_write16(dev
, 0x612, cfp_pretbtt
);
2969 /* FIXME: We don't currently implement the PMQ mechanism,
2970 * so always disable it. If we want to implement PMQ,
2971 * we need to enable it here (clear DISCPMQ) in AP mode.
2973 if (0 /* ctl & B43_MACCTL_AP */)
2974 b43_maskset32(dev
, B43_MMIO_MACCTL
, ~B43_MACCTL_DISCPMQ
, 0);
2976 b43_maskset32(dev
, B43_MMIO_MACCTL
, ~0, B43_MACCTL_DISCPMQ
);
2979 static void b43_rate_memory_write(struct b43_wldev
*dev
, u16 rate
, int is_ofdm
)
2985 offset
+= (b43_plcp_get_ratecode_ofdm(rate
) & 0x000F) * 2;
2988 offset
+= (b43_plcp_get_ratecode_cck(rate
) & 0x000F) * 2;
2990 b43_shm_write16(dev
, B43_SHM_SHARED
, offset
+ 0x20,
2991 b43_shm_read16(dev
, B43_SHM_SHARED
, offset
));
2994 static void b43_rate_memory_init(struct b43_wldev
*dev
)
2996 switch (dev
->phy
.type
) {
3000 case B43_PHYTYPE_LP
:
3001 case B43_PHYTYPE_HT
:
3002 case B43_PHYTYPE_LCN
:
3003 b43_rate_memory_write(dev
, B43_OFDM_RATE_6MB
, 1);
3004 b43_rate_memory_write(dev
, B43_OFDM_RATE_12MB
, 1);
3005 b43_rate_memory_write(dev
, B43_OFDM_RATE_18MB
, 1);
3006 b43_rate_memory_write(dev
, B43_OFDM_RATE_24MB
, 1);
3007 b43_rate_memory_write(dev
, B43_OFDM_RATE_36MB
, 1);
3008 b43_rate_memory_write(dev
, B43_OFDM_RATE_48MB
, 1);
3009 b43_rate_memory_write(dev
, B43_OFDM_RATE_54MB
, 1);
3010 if (dev
->phy
.type
== B43_PHYTYPE_A
)
3014 b43_rate_memory_write(dev
, B43_CCK_RATE_1MB
, 0);
3015 b43_rate_memory_write(dev
, B43_CCK_RATE_2MB
, 0);
3016 b43_rate_memory_write(dev
, B43_CCK_RATE_5MB
, 0);
3017 b43_rate_memory_write(dev
, B43_CCK_RATE_11MB
, 0);
3024 /* Set the default values for the PHY TX Control Words. */
3025 static void b43_set_phytxctl_defaults(struct b43_wldev
*dev
)
3029 ctl
|= B43_TXH_PHY_ENC_CCK
;
3030 ctl
|= B43_TXH_PHY_ANT01AUTO
;
3031 ctl
|= B43_TXH_PHY_TXPWR
;
3033 b43_shm_write16(dev
, B43_SHM_SHARED
, B43_SHM_SH_BEACPHYCTL
, ctl
);
3034 b43_shm_write16(dev
, B43_SHM_SHARED
, B43_SHM_SH_ACKCTSPHYCTL
, ctl
);
3035 b43_shm_write16(dev
, B43_SHM_SHARED
, B43_SHM_SH_PRPHYCTL
, ctl
);
3038 /* Set the TX-Antenna for management frames sent by firmware. */
3039 static void b43_mgmtframe_txantenna(struct b43_wldev
*dev
, int antenna
)
3044 ant
= b43_antenna_to_phyctl(antenna
);
3047 tmp
= b43_shm_read16(dev
, B43_SHM_SHARED
, B43_SHM_SH_ACKCTSPHYCTL
);
3048 tmp
= (tmp
& ~B43_TXH_PHY_ANT
) | ant
;
3049 b43_shm_write16(dev
, B43_SHM_SHARED
, B43_SHM_SH_ACKCTSPHYCTL
, tmp
);
3050 /* For Probe Resposes */
3051 tmp
= b43_shm_read16(dev
, B43_SHM_SHARED
, B43_SHM_SH_PRPHYCTL
);
3052 tmp
= (tmp
& ~B43_TXH_PHY_ANT
) | ant
;
3053 b43_shm_write16(dev
, B43_SHM_SHARED
, B43_SHM_SH_PRPHYCTL
, tmp
);
3056 /* This is the opposite of b43_chip_init() */
3057 static void b43_chip_exit(struct b43_wldev
*dev
)
3060 b43_gpio_cleanup(dev
);
3061 /* firmware is released later */
3064 /* Initialize the chip
3065 * http://bcm-specs.sipsolutions.net/ChipInit
3067 static int b43_chip_init(struct b43_wldev
*dev
)
3069 struct b43_phy
*phy
= &dev
->phy
;
3074 /* Initialize the MAC control */
3075 macctl
= B43_MACCTL_IHR_ENABLED
| B43_MACCTL_SHM_ENABLED
;
3077 macctl
|= B43_MACCTL_GMODE
;
3078 macctl
|= B43_MACCTL_INFRA
;
3079 b43_write32(dev
, B43_MMIO_MACCTL
, macctl
);
3081 err
= b43_upload_microcode(dev
);
3083 goto out
; /* firmware is released later */
3085 err
= b43_gpio_init(dev
);
3087 goto out
; /* firmware is released later */
3089 err
= b43_upload_initvals(dev
);
3091 goto err_gpio_clean
;
3093 err
= b43_upload_initvals_band(dev
);
3095 goto err_gpio_clean
;
3097 /* Turn the Analog on and initialize the PHY. */
3098 phy
->ops
->switch_analog(dev
, 1);
3099 err
= b43_phy_init(dev
);
3101 goto err_gpio_clean
;
3103 /* Disable Interference Mitigation. */
3104 if (phy
->ops
->interf_mitigation
)
3105 phy
->ops
->interf_mitigation(dev
, B43_INTERFMODE_NONE
);
3107 /* Select the antennae */
3108 if (phy
->ops
->set_rx_antenna
)
3109 phy
->ops
->set_rx_antenna(dev
, B43_ANTENNA_DEFAULT
);
3110 b43_mgmtframe_txantenna(dev
, B43_ANTENNA_DEFAULT
);
3112 if (phy
->type
== B43_PHYTYPE_B
) {
3113 value16
= b43_read16(dev
, 0x005E);
3115 b43_write16(dev
, 0x005E, value16
);
3117 b43_write32(dev
, 0x0100, 0x01000000);
3118 if (dev
->dev
->core_rev
< 5)
3119 b43_write32(dev
, 0x010C, 0x01000000);
3121 b43_maskset32(dev
, B43_MMIO_MACCTL
, ~B43_MACCTL_INFRA
, 0);
3122 b43_maskset32(dev
, B43_MMIO_MACCTL
, ~0, B43_MACCTL_INFRA
);
3124 /* Probe Response Timeout value */
3125 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
3126 b43_shm_write16(dev
, B43_SHM_SHARED
, B43_SHM_SH_PRMAXTIME
, 0);
3128 /* Initially set the wireless operation mode. */
3129 b43_adjust_opmode(dev
);
3131 if (dev
->dev
->core_rev
< 3) {
3132 b43_write16(dev
, 0x060E, 0x0000);
3133 b43_write16(dev
, 0x0610, 0x8000);
3134 b43_write16(dev
, 0x0604, 0x0000);
3135 b43_write16(dev
, 0x0606, 0x0200);
3137 b43_write32(dev
, 0x0188, 0x80000000);
3138 b43_write32(dev
, 0x018C, 0x02000000);
3140 b43_write32(dev
, B43_MMIO_GEN_IRQ_REASON
, 0x00004000);
3141 b43_write32(dev
, B43_MMIO_DMA0_IRQ_MASK
, 0x0001FC00);
3142 b43_write32(dev
, B43_MMIO_DMA1_IRQ_MASK
, 0x0000DC00);
3143 b43_write32(dev
, B43_MMIO_DMA2_IRQ_MASK
, 0x0000DC00);
3144 b43_write32(dev
, B43_MMIO_DMA3_IRQ_MASK
, 0x0001DC00);
3145 b43_write32(dev
, B43_MMIO_DMA4_IRQ_MASK
, 0x0000DC00);
3146 b43_write32(dev
, B43_MMIO_DMA5_IRQ_MASK
, 0x0000DC00);
3148 b43_mac_phy_clock_set(dev
, true);
3150 switch (dev
->dev
->bus_type
) {
3151 #ifdef CONFIG_B43_BCMA
3153 /* FIXME: 0xE74 is quite common, but should be read from CC */
3154 b43_write16(dev
, B43_MMIO_POWERUP_DELAY
, 0xE74);
3157 #ifdef CONFIG_B43_SSB
3159 b43_write16(dev
, B43_MMIO_POWERUP_DELAY
,
3160 dev
->dev
->sdev
->bus
->chipco
.fast_pwrup_delay
);
3166 b43dbg(dev
->wl
, "Chip initialized\n");
3171 b43_gpio_cleanup(dev
);
3175 static void b43_periodic_every60sec(struct b43_wldev
*dev
)
3177 const struct b43_phy_operations
*ops
= dev
->phy
.ops
;
3179 if (ops
->pwork_60sec
)
3180 ops
->pwork_60sec(dev
);
3182 /* Force check the TX power emission now. */
3183 b43_phy_txpower_check(dev
, B43_TXPWR_IGNORE_TIME
);
3186 static void b43_periodic_every30sec(struct b43_wldev
*dev
)
3188 /* Update device statistics. */
3189 b43_calculate_link_quality(dev
);
3192 static void b43_periodic_every15sec(struct b43_wldev
*dev
)
3194 struct b43_phy
*phy
= &dev
->phy
;
3197 if (dev
->fw
.opensource
) {
3198 /* Check if the firmware is still alive.
3199 * It will reset the watchdog counter to 0 in its idle loop. */
3200 wdr
= b43_shm_read16(dev
, B43_SHM_SCRATCH
, B43_WATCHDOG_REG
);
3201 if (unlikely(wdr
)) {
3202 b43err(dev
->wl
, "Firmware watchdog: The firmware died!\n");
3203 b43_controller_restart(dev
, "Firmware watchdog");
3206 b43_shm_write16(dev
, B43_SHM_SCRATCH
,
3207 B43_WATCHDOG_REG
, 1);
3211 if (phy
->ops
->pwork_15sec
)
3212 phy
->ops
->pwork_15sec(dev
);
3214 atomic_set(&phy
->txerr_cnt
, B43_PHY_TX_BADNESS_LIMIT
);
3218 if (b43_debug(dev
, B43_DBG_VERBOSESTATS
)) {
3221 b43dbg(dev
->wl
, "Stats: %7u IRQs/sec, %7u TX/sec, %7u RX/sec\n",
3222 dev
->irq_count
/ 15,
3224 dev
->rx_count
/ 15);
3228 for (i
= 0; i
< ARRAY_SIZE(dev
->irq_bit_count
); i
++) {
3229 if (dev
->irq_bit_count
[i
]) {
3230 b43dbg(dev
->wl
, "Stats: %7u IRQ-%02u/sec (0x%08X)\n",
3231 dev
->irq_bit_count
[i
] / 15, i
, (1 << i
));
3232 dev
->irq_bit_count
[i
] = 0;
3239 static void do_periodic_work(struct b43_wldev
*dev
)
3243 state
= dev
->periodic_state
;
3245 b43_periodic_every60sec(dev
);
3247 b43_periodic_every30sec(dev
);
3248 b43_periodic_every15sec(dev
);
3251 /* Periodic work locking policy:
3252 * The whole periodic work handler is protected by
3253 * wl->mutex. If another lock is needed somewhere in the
3254 * pwork callchain, it's acquired in-place, where it's needed.
3256 static void b43_periodic_work_handler(struct work_struct
*work
)
3258 struct b43_wldev
*dev
= container_of(work
, struct b43_wldev
,
3259 periodic_work
.work
);
3260 struct b43_wl
*wl
= dev
->wl
;
3261 unsigned long delay
;
3263 mutex_lock(&wl
->mutex
);
3265 if (unlikely(b43_status(dev
) != B43_STAT_STARTED
))
3267 if (b43_debug(dev
, B43_DBG_PWORK_STOP
))
3270 do_periodic_work(dev
);
3272 dev
->periodic_state
++;
3274 if (b43_debug(dev
, B43_DBG_PWORK_FAST
))
3275 delay
= msecs_to_jiffies(50);
3277 delay
= round_jiffies_relative(HZ
* 15);
3278 ieee80211_queue_delayed_work(wl
->hw
, &dev
->periodic_work
, delay
);
3280 mutex_unlock(&wl
->mutex
);
3283 static void b43_periodic_tasks_setup(struct b43_wldev
*dev
)
3285 struct delayed_work
*work
= &dev
->periodic_work
;
3287 dev
->periodic_state
= 0;
3288 INIT_DELAYED_WORK(work
, b43_periodic_work_handler
);
3289 ieee80211_queue_delayed_work(dev
->wl
->hw
, work
, 0);
3292 /* Check if communication with the device works correctly. */
3293 static int b43_validate_chipaccess(struct b43_wldev
*dev
)
3295 u32 v
, backup0
, backup4
;
3297 backup0
= b43_shm_read32(dev
, B43_SHM_SHARED
, 0);
3298 backup4
= b43_shm_read32(dev
, B43_SHM_SHARED
, 4);
3300 /* Check for read/write and endianness problems. */
3301 b43_shm_write32(dev
, B43_SHM_SHARED
, 0, 0x55AAAA55);
3302 if (b43_shm_read32(dev
, B43_SHM_SHARED
, 0) != 0x55AAAA55)
3304 b43_shm_write32(dev
, B43_SHM_SHARED
, 0, 0xAA5555AA);
3305 if (b43_shm_read32(dev
, B43_SHM_SHARED
, 0) != 0xAA5555AA)
3308 /* Check if unaligned 32bit SHM_SHARED access works properly.
3309 * However, don't bail out on failure, because it's noncritical. */
3310 b43_shm_write16(dev
, B43_SHM_SHARED
, 0, 0x1122);
3311 b43_shm_write16(dev
, B43_SHM_SHARED
, 2, 0x3344);
3312 b43_shm_write16(dev
, B43_SHM_SHARED
, 4, 0x5566);
3313 b43_shm_write16(dev
, B43_SHM_SHARED
, 6, 0x7788);
3314 if (b43_shm_read32(dev
, B43_SHM_SHARED
, 2) != 0x55663344)
3315 b43warn(dev
->wl
, "Unaligned 32bit SHM read access is broken\n");
3316 b43_shm_write32(dev
, B43_SHM_SHARED
, 2, 0xAABBCCDD);
3317 if (b43_shm_read16(dev
, B43_SHM_SHARED
, 0) != 0x1122 ||
3318 b43_shm_read16(dev
, B43_SHM_SHARED
, 2) != 0xCCDD ||
3319 b43_shm_read16(dev
, B43_SHM_SHARED
, 4) != 0xAABB ||
3320 b43_shm_read16(dev
, B43_SHM_SHARED
, 6) != 0x7788)
3321 b43warn(dev
->wl
, "Unaligned 32bit SHM write access is broken\n");
3323 b43_shm_write32(dev
, B43_SHM_SHARED
, 0, backup0
);
3324 b43_shm_write32(dev
, B43_SHM_SHARED
, 4, backup4
);
3326 if ((dev
->dev
->core_rev
>= 3) && (dev
->dev
->core_rev
<= 10)) {
3327 /* The 32bit register shadows the two 16bit registers
3328 * with update sideeffects. Validate this. */
3329 b43_write16(dev
, B43_MMIO_TSF_CFP_START
, 0xAAAA);
3330 b43_write32(dev
, B43_MMIO_TSF_CFP_START
, 0xCCCCBBBB);
3331 if (b43_read16(dev
, B43_MMIO_TSF_CFP_START_LOW
) != 0xBBBB)
3333 if (b43_read16(dev
, B43_MMIO_TSF_CFP_START_HIGH
) != 0xCCCC)
3336 b43_write32(dev
, B43_MMIO_TSF_CFP_START
, 0);
3338 v
= b43_read32(dev
, B43_MMIO_MACCTL
);
3339 v
|= B43_MACCTL_GMODE
;
3340 if (v
!= (B43_MACCTL_GMODE
| B43_MACCTL_IHR_ENABLED
))
3345 b43err(dev
->wl
, "Failed to validate the chipaccess\n");
3349 static void b43_security_init(struct b43_wldev
*dev
)
3351 dev
->ktp
= b43_shm_read16(dev
, B43_SHM_SHARED
, B43_SHM_SH_KTP
);
3352 /* KTP is a word address, but we address SHM bytewise.
3353 * So multiply by two.
3356 /* Number of RCMTA address slots */
3357 b43_write16(dev
, B43_MMIO_RCMTA_COUNT
, B43_NR_PAIRWISE_KEYS
);
3358 /* Clear the key memory. */
3359 b43_clear_keys(dev
);
3362 #ifdef CONFIG_B43_HWRNG
3363 static int b43_rng_read(struct hwrng
*rng
, u32
*data
)
3365 struct b43_wl
*wl
= (struct b43_wl
*)rng
->priv
;
3366 struct b43_wldev
*dev
;
3367 int count
= -ENODEV
;
3369 mutex_lock(&wl
->mutex
);
3370 dev
= wl
->current_dev
;
3371 if (likely(dev
&& b43_status(dev
) >= B43_STAT_INITIALIZED
)) {
3372 *data
= b43_read16(dev
, B43_MMIO_RNG
);
3373 count
= sizeof(u16
);
3375 mutex_unlock(&wl
->mutex
);
3379 #endif /* CONFIG_B43_HWRNG */
3381 static void b43_rng_exit(struct b43_wl
*wl
)
3383 #ifdef CONFIG_B43_HWRNG
3384 if (wl
->rng_initialized
)
3385 hwrng_unregister(&wl
->rng
);
3386 #endif /* CONFIG_B43_HWRNG */
3389 static int b43_rng_init(struct b43_wl
*wl
)
3393 #ifdef CONFIG_B43_HWRNG
3394 snprintf(wl
->rng_name
, ARRAY_SIZE(wl
->rng_name
),
3395 "%s_%s", KBUILD_MODNAME
, wiphy_name(wl
->hw
->wiphy
));
3396 wl
->rng
.name
= wl
->rng_name
;
3397 wl
->rng
.data_read
= b43_rng_read
;
3398 wl
->rng
.priv
= (unsigned long)wl
;
3399 wl
->rng_initialized
= true;
3400 err
= hwrng_register(&wl
->rng
);
3402 wl
->rng_initialized
= false;
3403 b43err(wl
, "Failed to register the random "
3404 "number generator (%d)\n", err
);
3406 #endif /* CONFIG_B43_HWRNG */
3411 static void b43_tx_work(struct work_struct
*work
)
3413 struct b43_wl
*wl
= container_of(work
, struct b43_wl
, tx_work
);
3414 struct b43_wldev
*dev
;
3415 struct sk_buff
*skb
;
3419 mutex_lock(&wl
->mutex
);
3420 dev
= wl
->current_dev
;
3421 if (unlikely(!dev
|| b43_status(dev
) < B43_STAT_STARTED
)) {
3422 mutex_unlock(&wl
->mutex
);
3426 for (queue_num
= 0; queue_num
< B43_QOS_QUEUE_NUM
; queue_num
++) {
3427 while (skb_queue_len(&wl
->tx_queue
[queue_num
])) {
3428 skb
= skb_dequeue(&wl
->tx_queue
[queue_num
]);
3429 if (b43_using_pio_transfers(dev
))
3430 err
= b43_pio_tx(dev
, skb
);
3432 err
= b43_dma_tx(dev
, skb
);
3433 if (err
== -ENOSPC
) {
3434 wl
->tx_queue_stopped
[queue_num
] = 1;
3435 ieee80211_stop_queue(wl
->hw
, queue_num
);
3436 skb_queue_head(&wl
->tx_queue
[queue_num
], skb
);
3440 ieee80211_free_txskb(wl
->hw
, skb
);
3445 wl
->tx_queue_stopped
[queue_num
] = 0;
3451 mutex_unlock(&wl
->mutex
);
3454 static void b43_op_tx(struct ieee80211_hw
*hw
,
3455 struct ieee80211_tx_control
*control
,
3456 struct sk_buff
*skb
)
3458 struct b43_wl
*wl
= hw_to_b43_wl(hw
);
3460 if (unlikely(skb
->len
< 2 + 2 + 6)) {
3461 /* Too short, this can't be a valid frame. */
3462 ieee80211_free_txskb(hw
, skb
);
3465 B43_WARN_ON(skb_shinfo(skb
)->nr_frags
);
3467 skb_queue_tail(&wl
->tx_queue
[skb
->queue_mapping
], skb
);
3468 if (!wl
->tx_queue_stopped
[skb
->queue_mapping
]) {
3469 ieee80211_queue_work(wl
->hw
, &wl
->tx_work
);
3471 ieee80211_stop_queue(wl
->hw
, skb
->queue_mapping
);
3475 static void b43_qos_params_upload(struct b43_wldev
*dev
,
3476 const struct ieee80211_tx_queue_params
*p
,
3479 u16 params
[B43_NR_QOSPARAMS
];
3483 if (!dev
->qos_enabled
)
3486 bslots
= b43_read16(dev
, B43_MMIO_RNG
) & p
->cw_min
;
3488 memset(¶ms
, 0, sizeof(params
));
3490 params
[B43_QOSPARAM_TXOP
] = p
->txop
* 32;
3491 params
[B43_QOSPARAM_CWMIN
] = p
->cw_min
;
3492 params
[B43_QOSPARAM_CWMAX
] = p
->cw_max
;
3493 params
[B43_QOSPARAM_CWCUR
] = p
->cw_min
;
3494 params
[B43_QOSPARAM_AIFS
] = p
->aifs
;
3495 params
[B43_QOSPARAM_BSLOTS
] = bslots
;
3496 params
[B43_QOSPARAM_REGGAP
] = bslots
+ p
->aifs
;
3498 for (i
= 0; i
< ARRAY_SIZE(params
); i
++) {
3499 if (i
== B43_QOSPARAM_STATUS
) {
3500 tmp
= b43_shm_read16(dev
, B43_SHM_SHARED
,
3501 shm_offset
+ (i
* 2));
3502 /* Mark the parameters as updated. */
3504 b43_shm_write16(dev
, B43_SHM_SHARED
,
3505 shm_offset
+ (i
* 2),
3508 b43_shm_write16(dev
, B43_SHM_SHARED
,
3509 shm_offset
+ (i
* 2),
3515 /* Mapping of mac80211 queue numbers to b43 QoS SHM offsets. */
3516 static const u16 b43_qos_shm_offsets
[] = {
3517 /* [mac80211-queue-nr] = SHM_OFFSET, */
3518 [0] = B43_QOS_VOICE
,
3519 [1] = B43_QOS_VIDEO
,
3520 [2] = B43_QOS_BESTEFFORT
,
3521 [3] = B43_QOS_BACKGROUND
,
3524 /* Update all QOS parameters in hardware. */
3525 static void b43_qos_upload_all(struct b43_wldev
*dev
)
3527 struct b43_wl
*wl
= dev
->wl
;
3528 struct b43_qos_params
*params
;
3531 if (!dev
->qos_enabled
)
3534 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets
) !=
3535 ARRAY_SIZE(wl
->qos_params
));
3537 b43_mac_suspend(dev
);
3538 for (i
= 0; i
< ARRAY_SIZE(wl
->qos_params
); i
++) {
3539 params
= &(wl
->qos_params
[i
]);
3540 b43_qos_params_upload(dev
, &(params
->p
),
3541 b43_qos_shm_offsets
[i
]);
3543 b43_mac_enable(dev
);
3546 static void b43_qos_clear(struct b43_wl
*wl
)
3548 struct b43_qos_params
*params
;
3551 /* Initialize QoS parameters to sane defaults. */
3553 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets
) !=
3554 ARRAY_SIZE(wl
->qos_params
));
3556 for (i
= 0; i
< ARRAY_SIZE(wl
->qos_params
); i
++) {
3557 params
= &(wl
->qos_params
[i
]);
3559 switch (b43_qos_shm_offsets
[i
]) {
3563 params
->p
.cw_min
= 0x0001;
3564 params
->p
.cw_max
= 0x0001;
3569 params
->p
.cw_min
= 0x0001;
3570 params
->p
.cw_max
= 0x0001;
3572 case B43_QOS_BESTEFFORT
:
3575 params
->p
.cw_min
= 0x0001;
3576 params
->p
.cw_max
= 0x03FF;
3578 case B43_QOS_BACKGROUND
:
3581 params
->p
.cw_min
= 0x0001;
3582 params
->p
.cw_max
= 0x03FF;
3590 /* Initialize the core's QOS capabilities */
3591 static void b43_qos_init(struct b43_wldev
*dev
)
3593 if (!dev
->qos_enabled
) {
3594 /* Disable QOS support. */
3595 b43_hf_write(dev
, b43_hf_read(dev
) & ~B43_HF_EDCF
);
3596 b43_write16(dev
, B43_MMIO_IFSCTL
,
3597 b43_read16(dev
, B43_MMIO_IFSCTL
)
3598 & ~B43_MMIO_IFSCTL_USE_EDCF
);
3599 b43dbg(dev
->wl
, "QoS disabled\n");
3603 /* Upload the current QOS parameters. */
3604 b43_qos_upload_all(dev
);
3606 /* Enable QOS support. */
3607 b43_hf_write(dev
, b43_hf_read(dev
) | B43_HF_EDCF
);
3608 b43_write16(dev
, B43_MMIO_IFSCTL
,
3609 b43_read16(dev
, B43_MMIO_IFSCTL
)
3610 | B43_MMIO_IFSCTL_USE_EDCF
);
3611 b43dbg(dev
->wl
, "QoS enabled\n");
3614 static int b43_op_conf_tx(struct ieee80211_hw
*hw
,
3615 struct ieee80211_vif
*vif
, u16 _queue
,
3616 const struct ieee80211_tx_queue_params
*params
)
3618 struct b43_wl
*wl
= hw_to_b43_wl(hw
);
3619 struct b43_wldev
*dev
;
3620 unsigned int queue
= (unsigned int)_queue
;
3623 if (queue
>= ARRAY_SIZE(wl
->qos_params
)) {
3624 /* Queue not available or don't support setting
3625 * params on this queue. Return success to not
3626 * confuse mac80211. */
3629 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets
) !=
3630 ARRAY_SIZE(wl
->qos_params
));
3632 mutex_lock(&wl
->mutex
);
3633 dev
= wl
->current_dev
;
3634 if (unlikely(!dev
|| (b43_status(dev
) < B43_STAT_INITIALIZED
)))
3637 memcpy(&(wl
->qos_params
[queue
].p
), params
, sizeof(*params
));
3638 b43_mac_suspend(dev
);
3639 b43_qos_params_upload(dev
, &(wl
->qos_params
[queue
].p
),
3640 b43_qos_shm_offsets
[queue
]);
3641 b43_mac_enable(dev
);
3645 mutex_unlock(&wl
->mutex
);
3650 static int b43_op_get_stats(struct ieee80211_hw
*hw
,
3651 struct ieee80211_low_level_stats
*stats
)
3653 struct b43_wl
*wl
= hw_to_b43_wl(hw
);
3655 mutex_lock(&wl
->mutex
);
3656 memcpy(stats
, &wl
->ieee_stats
, sizeof(*stats
));
3657 mutex_unlock(&wl
->mutex
);
3662 static u64
b43_op_get_tsf(struct ieee80211_hw
*hw
, struct ieee80211_vif
*vif
)
3664 struct b43_wl
*wl
= hw_to_b43_wl(hw
);
3665 struct b43_wldev
*dev
;
3668 mutex_lock(&wl
->mutex
);
3669 dev
= wl
->current_dev
;
3671 if (dev
&& (b43_status(dev
) >= B43_STAT_INITIALIZED
))
3672 b43_tsf_read(dev
, &tsf
);
3676 mutex_unlock(&wl
->mutex
);
3681 static void b43_op_set_tsf(struct ieee80211_hw
*hw
,
3682 struct ieee80211_vif
*vif
, u64 tsf
)
3684 struct b43_wl
*wl
= hw_to_b43_wl(hw
);
3685 struct b43_wldev
*dev
;
3687 mutex_lock(&wl
->mutex
);
3688 dev
= wl
->current_dev
;
3690 if (dev
&& (b43_status(dev
) >= B43_STAT_INITIALIZED
))
3691 b43_tsf_write(dev
, tsf
);
3693 mutex_unlock(&wl
->mutex
);
3696 static const char *band_to_string(enum ieee80211_band band
)
3699 case IEEE80211_BAND_5GHZ
:
3701 case IEEE80211_BAND_2GHZ
:
3710 /* Expects wl->mutex locked */
3711 static int b43_switch_band(struct b43_wldev
*dev
,
3712 struct ieee80211_channel
*chan
)
3714 struct b43_phy
*phy
= &dev
->phy
;
3718 switch (chan
->band
) {
3719 case IEEE80211_BAND_5GHZ
:
3722 case IEEE80211_BAND_2GHZ
:
3730 if (!((gmode
&& phy
->supports_2ghz
) ||
3731 (!gmode
&& phy
->supports_5ghz
))) {
3732 b43err(dev
->wl
, "This device doesn't support %s-GHz band\n",
3733 band_to_string(chan
->band
));
3737 if (!!phy
->gmode
== !!gmode
) {
3738 /* This device is already running. */
3742 b43dbg(dev
->wl
, "Switching to %s GHz band\n",
3743 band_to_string(chan
->band
));
3745 /* Some new devices don't need disabling radio for band switching */
3746 if (!(phy
->type
== B43_PHYTYPE_N
&& phy
->rev
>= 3))
3747 b43_software_rfkill(dev
, true);
3750 b43_phy_put_into_reset(dev
);
3751 switch (dev
->dev
->bus_type
) {
3752 #ifdef CONFIG_B43_BCMA
3754 tmp
= bcma_aread32(dev
->dev
->bdev
, BCMA_IOCTL
);
3756 tmp
|= B43_BCMA_IOCTL_GMODE
;
3758 tmp
&= ~B43_BCMA_IOCTL_GMODE
;
3759 bcma_awrite32(dev
->dev
->bdev
, BCMA_IOCTL
, tmp
);
3762 #ifdef CONFIG_B43_SSB
3764 tmp
= ssb_read32(dev
->dev
->sdev
, SSB_TMSLOW
);
3766 tmp
|= B43_TMSLOW_GMODE
;
3768 tmp
&= ~B43_TMSLOW_GMODE
;
3769 ssb_write32(dev
->dev
->sdev
, SSB_TMSLOW
, tmp
);
3773 b43_phy_take_out_of_reset(dev
);
3775 b43_upload_initvals_band(dev
);
3782 /* Write the short and long frame retry limit values. */
3783 static void b43_set_retry_limits(struct b43_wldev
*dev
,
3784 unsigned int short_retry
,
3785 unsigned int long_retry
)
3787 /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing
3788 * the chip-internal counter. */
3789 short_retry
= min(short_retry
, (unsigned int)0xF);
3790 long_retry
= min(long_retry
, (unsigned int)0xF);
3792 b43_shm_write16(dev
, B43_SHM_SCRATCH
, B43_SHM_SC_SRLIMIT
,
3794 b43_shm_write16(dev
, B43_SHM_SCRATCH
, B43_SHM_SC_LRLIMIT
,
3798 static int b43_op_config(struct ieee80211_hw
*hw
, u32 changed
)
3800 struct b43_wl
*wl
= hw_to_b43_wl(hw
);
3801 struct b43_wldev
*dev
;
3802 struct b43_phy
*phy
;
3803 struct ieee80211_conf
*conf
= &hw
->conf
;
3806 bool reload_bss
= false;
3808 mutex_lock(&wl
->mutex
);
3810 dev
= wl
->current_dev
;
3812 b43_mac_suspend(dev
);
3814 /* Switch the band (if necessary). This might change the active core. */
3815 err
= b43_switch_band(dev
, conf
->chandef
.chan
);
3817 goto out_unlock_mutex
;
3819 /* Need to reload all settings if the core changed */
3820 if (dev
!= wl
->current_dev
) {
3821 dev
= wl
->current_dev
;
3828 if (conf_is_ht(conf
))
3830 (conf_is_ht40_minus(conf
) || conf_is_ht40_plus(conf
));
3832 phy
->is_40mhz
= false;
3834 if (changed
& IEEE80211_CONF_CHANGE_RETRY_LIMITS
)
3835 b43_set_retry_limits(dev
, conf
->short_frame_max_tx_count
,
3836 conf
->long_frame_max_tx_count
);
3837 changed
&= ~IEEE80211_CONF_CHANGE_RETRY_LIMITS
;
3839 goto out_mac_enable
;
3841 /* Switch to the requested channel.
3842 * The firmware takes care of races with the TX handler. */
3843 if (conf
->chandef
.chan
->hw_value
!= phy
->channel
)
3844 b43_switch_channel(dev
, conf
->chandef
.chan
->hw_value
);
3846 dev
->wl
->radiotap_enabled
= !!(conf
->flags
& IEEE80211_CONF_MONITOR
);
3848 /* Adjust the desired TX power level. */
3849 if (conf
->power_level
!= 0) {
3850 if (conf
->power_level
!= phy
->desired_txpower
) {
3851 phy
->desired_txpower
= conf
->power_level
;
3852 b43_phy_txpower_check(dev
, B43_TXPWR_IGNORE_TIME
|
3853 B43_TXPWR_IGNORE_TSSI
);
3857 /* Antennas for RX and management frame TX. */
3858 antenna
= B43_ANTENNA_DEFAULT
;
3859 b43_mgmtframe_txantenna(dev
, antenna
);
3860 antenna
= B43_ANTENNA_DEFAULT
;
3861 if (phy
->ops
->set_rx_antenna
)
3862 phy
->ops
->set_rx_antenna(dev
, antenna
);
3864 if (wl
->radio_enabled
!= phy
->radio_on
) {
3865 if (wl
->radio_enabled
) {
3866 b43_software_rfkill(dev
, false);
3867 b43info(dev
->wl
, "Radio turned on by software\n");
3868 if (!dev
->radio_hw_enable
) {
3869 b43info(dev
->wl
, "The hardware RF-kill button "
3870 "still turns the radio physically off. "
3871 "Press the button to turn it on.\n");
3874 b43_software_rfkill(dev
, true);
3875 b43info(dev
->wl
, "Radio turned off by software\n");
3880 b43_mac_enable(dev
);
3882 mutex_unlock(&wl
->mutex
);
3884 if (wl
->vif
&& reload_bss
)
3885 b43_op_bss_info_changed(hw
, wl
->vif
, &wl
->vif
->bss_conf
, ~0);
3890 static void b43_update_basic_rates(struct b43_wldev
*dev
, u32 brates
)
3892 struct ieee80211_supported_band
*sband
=
3893 dev
->wl
->hw
->wiphy
->bands
[b43_current_band(dev
->wl
)];
3894 struct ieee80211_rate
*rate
;
3896 u16 basic
, direct
, offset
, basic_offset
, rateptr
;
3898 for (i
= 0; i
< sband
->n_bitrates
; i
++) {
3899 rate
= &sband
->bitrates
[i
];
3901 if (b43_is_cck_rate(rate
->hw_value
)) {
3902 direct
= B43_SHM_SH_CCKDIRECT
;
3903 basic
= B43_SHM_SH_CCKBASIC
;
3904 offset
= b43_plcp_get_ratecode_cck(rate
->hw_value
);
3907 direct
= B43_SHM_SH_OFDMDIRECT
;
3908 basic
= B43_SHM_SH_OFDMBASIC
;
3909 offset
= b43_plcp_get_ratecode_ofdm(rate
->hw_value
);
3913 rate
= ieee80211_get_response_rate(sband
, brates
, rate
->bitrate
);
3915 if (b43_is_cck_rate(rate
->hw_value
)) {
3916 basic_offset
= b43_plcp_get_ratecode_cck(rate
->hw_value
);
3917 basic_offset
&= 0xF;
3919 basic_offset
= b43_plcp_get_ratecode_ofdm(rate
->hw_value
);
3920 basic_offset
&= 0xF;
3924 * Get the pointer that we need to point to
3925 * from the direct map
3927 rateptr
= b43_shm_read16(dev
, B43_SHM_SHARED
,
3928 direct
+ 2 * basic_offset
);
3929 /* and write it to the basic map */
3930 b43_shm_write16(dev
, B43_SHM_SHARED
, basic
+ 2 * offset
,
3935 static void b43_op_bss_info_changed(struct ieee80211_hw
*hw
,
3936 struct ieee80211_vif
*vif
,
3937 struct ieee80211_bss_conf
*conf
,
3940 struct b43_wl
*wl
= hw_to_b43_wl(hw
);
3941 struct b43_wldev
*dev
;
3943 mutex_lock(&wl
->mutex
);
3945 dev
= wl
->current_dev
;
3946 if (!dev
|| b43_status(dev
) < B43_STAT_STARTED
)
3947 goto out_unlock_mutex
;
3949 B43_WARN_ON(wl
->vif
!= vif
);
3951 if (changed
& BSS_CHANGED_BSSID
) {
3953 memcpy(wl
->bssid
, conf
->bssid
, ETH_ALEN
);
3955 memset(wl
->bssid
, 0, ETH_ALEN
);
3958 if (b43_status(dev
) >= B43_STAT_INITIALIZED
) {
3959 if (changed
& BSS_CHANGED_BEACON
&&
3960 (b43_is_mode(wl
, NL80211_IFTYPE_AP
) ||
3961 b43_is_mode(wl
, NL80211_IFTYPE_MESH_POINT
) ||
3962 b43_is_mode(wl
, NL80211_IFTYPE_ADHOC
)))
3963 b43_update_templates(wl
);
3965 if (changed
& BSS_CHANGED_BSSID
)
3966 b43_write_mac_bssid_templates(dev
);
3969 b43_mac_suspend(dev
);
3971 /* Update templates for AP/mesh mode. */
3972 if (changed
& BSS_CHANGED_BEACON_INT
&&
3973 (b43_is_mode(wl
, NL80211_IFTYPE_AP
) ||
3974 b43_is_mode(wl
, NL80211_IFTYPE_MESH_POINT
) ||
3975 b43_is_mode(wl
, NL80211_IFTYPE_ADHOC
)) &&
3977 b43_set_beacon_int(dev
, conf
->beacon_int
);
3979 if (changed
& BSS_CHANGED_BASIC_RATES
)
3980 b43_update_basic_rates(dev
, conf
->basic_rates
);
3982 if (changed
& BSS_CHANGED_ERP_SLOT
) {
3983 if (conf
->use_short_slot
)
3984 b43_short_slot_timing_enable(dev
);
3986 b43_short_slot_timing_disable(dev
);
3989 b43_mac_enable(dev
);
3991 mutex_unlock(&wl
->mutex
);
3994 static int b43_op_set_key(struct ieee80211_hw
*hw
, enum set_key_cmd cmd
,
3995 struct ieee80211_vif
*vif
, struct ieee80211_sta
*sta
,
3996 struct ieee80211_key_conf
*key
)
3998 struct b43_wl
*wl
= hw_to_b43_wl(hw
);
3999 struct b43_wldev
*dev
;
4003 static const u8 bcast_addr
[ETH_ALEN
] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
4005 if (modparam_nohwcrypt
)
4006 return -ENOSPC
; /* User disabled HW-crypto */
4008 if ((vif
->type
== NL80211_IFTYPE_ADHOC
||
4009 vif
->type
== NL80211_IFTYPE_MESH_POINT
) &&
4010 (key
->cipher
== WLAN_CIPHER_SUITE_TKIP
||
4011 key
->cipher
== WLAN_CIPHER_SUITE_CCMP
) &&
4012 !(key
->flags
& IEEE80211_KEY_FLAG_PAIRWISE
)) {
4014 * For now, disable hw crypto for the RSN IBSS group keys. This
4015 * could be optimized in the future, but until that gets
4016 * implemented, use of software crypto for group addressed
4017 * frames is a acceptable to allow RSN IBSS to be used.
4022 mutex_lock(&wl
->mutex
);
4024 dev
= wl
->current_dev
;
4026 if (!dev
|| b43_status(dev
) < B43_STAT_INITIALIZED
)
4029 if (dev
->fw
.pcm_request_failed
|| !dev
->hwcrypto_enabled
) {
4030 /* We don't have firmware for the crypto engine.
4031 * Must use software-crypto. */
4037 switch (key
->cipher
) {
4038 case WLAN_CIPHER_SUITE_WEP40
:
4039 algorithm
= B43_SEC_ALGO_WEP40
;
4041 case WLAN_CIPHER_SUITE_WEP104
:
4042 algorithm
= B43_SEC_ALGO_WEP104
;
4044 case WLAN_CIPHER_SUITE_TKIP
:
4045 algorithm
= B43_SEC_ALGO_TKIP
;
4047 case WLAN_CIPHER_SUITE_CCMP
:
4048 algorithm
= B43_SEC_ALGO_AES
;
4054 index
= (u8
) (key
->keyidx
);
4060 if (algorithm
== B43_SEC_ALGO_TKIP
&&
4061 (!(key
->flags
& IEEE80211_KEY_FLAG_PAIRWISE
) ||
4062 !modparam_hwtkip
)) {
4063 /* We support only pairwise key */
4068 if (key
->flags
& IEEE80211_KEY_FLAG_PAIRWISE
) {
4069 if (WARN_ON(!sta
)) {
4073 /* Pairwise key with an assigned MAC address. */
4074 err
= b43_key_write(dev
, -1, algorithm
,
4075 key
->key
, key
->keylen
,
4079 err
= b43_key_write(dev
, index
, algorithm
,
4080 key
->key
, key
->keylen
, NULL
, key
);
4085 if (algorithm
== B43_SEC_ALGO_WEP40
||
4086 algorithm
== B43_SEC_ALGO_WEP104
) {
4087 b43_hf_write(dev
, b43_hf_read(dev
) | B43_HF_USEDEFKEYS
);
4090 b43_hf_read(dev
) & ~B43_HF_USEDEFKEYS
);
4092 key
->flags
|= IEEE80211_KEY_FLAG_GENERATE_IV
;
4093 if (algorithm
== B43_SEC_ALGO_TKIP
)
4094 key
->flags
|= IEEE80211_KEY_FLAG_GENERATE_MMIC
;
4097 err
= b43_key_clear(dev
, key
->hw_key_idx
);
4108 b43dbg(wl
, "%s hardware based encryption for keyidx: %d, "
4110 cmd
== SET_KEY
? "Using" : "Disabling", key
->keyidx
,
4111 sta
? sta
->addr
: bcast_addr
);
4112 b43_dump_keymemory(dev
);
4114 mutex_unlock(&wl
->mutex
);
4119 static void b43_op_configure_filter(struct ieee80211_hw
*hw
,
4120 unsigned int changed
, unsigned int *fflags
,
4123 struct b43_wl
*wl
= hw_to_b43_wl(hw
);
4124 struct b43_wldev
*dev
;
4126 mutex_lock(&wl
->mutex
);
4127 dev
= wl
->current_dev
;
4133 *fflags
&= FIF_PROMISC_IN_BSS
|
4139 FIF_BCN_PRBRESP_PROMISC
;
4141 changed
&= FIF_PROMISC_IN_BSS
|
4147 FIF_BCN_PRBRESP_PROMISC
;
4149 wl
->filter_flags
= *fflags
;
4151 if (changed
&& b43_status(dev
) >= B43_STAT_INITIALIZED
)
4152 b43_adjust_opmode(dev
);
4155 mutex_unlock(&wl
->mutex
);
4158 /* Locking: wl->mutex
4159 * Returns the current dev. This might be different from the passed in dev,
4160 * because the core might be gone away while we unlocked the mutex. */
4161 static struct b43_wldev
* b43_wireless_core_stop(struct b43_wldev
*dev
)
4164 struct b43_wldev
*orig_dev
;
4172 if (!dev
|| b43_status(dev
) < B43_STAT_STARTED
)
4175 /* Cancel work. Unlock to avoid deadlocks. */
4176 mutex_unlock(&wl
->mutex
);
4177 cancel_delayed_work_sync(&dev
->periodic_work
);
4178 cancel_work_sync(&wl
->tx_work
);
4179 mutex_lock(&wl
->mutex
);
4180 dev
= wl
->current_dev
;
4181 if (!dev
|| b43_status(dev
) < B43_STAT_STARTED
) {
4182 /* Whoops, aliens ate up the device while we were unlocked. */
4186 /* Disable interrupts on the device. */
4187 b43_set_status(dev
, B43_STAT_INITIALIZED
);
4188 if (b43_bus_host_is_sdio(dev
->dev
)) {
4189 /* wl->mutex is locked. That is enough. */
4190 b43_write32(dev
, B43_MMIO_GEN_IRQ_MASK
, 0);
4191 b43_read32(dev
, B43_MMIO_GEN_IRQ_MASK
); /* Flush */
4193 spin_lock_irq(&wl
->hardirq_lock
);
4194 b43_write32(dev
, B43_MMIO_GEN_IRQ_MASK
, 0);
4195 b43_read32(dev
, B43_MMIO_GEN_IRQ_MASK
); /* Flush */
4196 spin_unlock_irq(&wl
->hardirq_lock
);
4198 /* Synchronize and free the interrupt handlers. Unlock to avoid deadlocks. */
4200 mutex_unlock(&wl
->mutex
);
4201 if (b43_bus_host_is_sdio(dev
->dev
)) {
4202 b43_sdio_free_irq(dev
);
4204 synchronize_irq(dev
->dev
->irq
);
4205 free_irq(dev
->dev
->irq
, dev
);
4207 mutex_lock(&wl
->mutex
);
4208 dev
= wl
->current_dev
;
4211 if (dev
!= orig_dev
) {
4212 if (b43_status(dev
) >= B43_STAT_STARTED
)
4216 mask
= b43_read32(dev
, B43_MMIO_GEN_IRQ_MASK
);
4217 B43_WARN_ON(mask
!= 0xFFFFFFFF && mask
);
4219 /* Drain all TX queues. */
4220 for (queue_num
= 0; queue_num
< B43_QOS_QUEUE_NUM
; queue_num
++) {
4221 while (skb_queue_len(&wl
->tx_queue
[queue_num
])) {
4222 struct sk_buff
*skb
;
4224 skb
= skb_dequeue(&wl
->tx_queue
[queue_num
]);
4225 ieee80211_free_txskb(wl
->hw
, skb
);
4229 b43_mac_suspend(dev
);
4231 b43dbg(wl
, "Wireless interface stopped\n");
4236 /* Locking: wl->mutex */
4237 static int b43_wireless_core_start(struct b43_wldev
*dev
)
4241 B43_WARN_ON(b43_status(dev
) != B43_STAT_INITIALIZED
);
4243 drain_txstatus_queue(dev
);
4244 if (b43_bus_host_is_sdio(dev
->dev
)) {
4245 err
= b43_sdio_request_irq(dev
, b43_sdio_interrupt_handler
);
4247 b43err(dev
->wl
, "Cannot request SDIO IRQ\n");
4251 err
= request_threaded_irq(dev
->dev
->irq
, b43_interrupt_handler
,
4252 b43_interrupt_thread_handler
,
4253 IRQF_SHARED
, KBUILD_MODNAME
, dev
);
4255 b43err(dev
->wl
, "Cannot request IRQ-%d\n",
4261 /* We are ready to run. */
4262 ieee80211_wake_queues(dev
->wl
->hw
);
4263 b43_set_status(dev
, B43_STAT_STARTED
);
4265 /* Start data flow (TX/RX). */
4266 b43_mac_enable(dev
);
4267 b43_write32(dev
, B43_MMIO_GEN_IRQ_MASK
, dev
->irq_mask
);
4269 /* Start maintenance work */
4270 b43_periodic_tasks_setup(dev
);
4274 b43dbg(dev
->wl
, "Wireless interface started\n");
4279 static char *b43_phy_name(struct b43_wldev
*dev
, u8 phy_type
)
4290 case B43_PHYTYPE_LP
:
4292 case B43_PHYTYPE_SSLPN
:
4294 case B43_PHYTYPE_HT
:
4296 case B43_PHYTYPE_LCN
:
4298 case B43_PHYTYPE_LCNXN
:
4300 case B43_PHYTYPE_LCN40
:
4302 case B43_PHYTYPE_AC
:
4308 /* Get PHY and RADIO versioning numbers */
4309 static int b43_phy_versioning(struct b43_wldev
*dev
)
4311 struct b43_phy
*phy
= &dev
->phy
;
4319 int unsupported
= 0;
4321 /* Get PHY versioning */
4322 tmp
= b43_read16(dev
, B43_MMIO_PHY_VER
);
4323 analog_type
= (tmp
& B43_PHYVER_ANALOG
) >> B43_PHYVER_ANALOG_SHIFT
;
4324 phy_type
= (tmp
& B43_PHYVER_TYPE
) >> B43_PHYVER_TYPE_SHIFT
;
4325 phy_rev
= (tmp
& B43_PHYVER_VERSION
);
4332 if (phy_rev
!= 2 && phy_rev
!= 4 && phy_rev
!= 6
4340 #ifdef CONFIG_B43_PHY_N
4346 #ifdef CONFIG_B43_PHY_LP
4347 case B43_PHYTYPE_LP
:
4352 #ifdef CONFIG_B43_PHY_HT
4353 case B43_PHYTYPE_HT
:
4358 #ifdef CONFIG_B43_PHY_LCN
4359 case B43_PHYTYPE_LCN
:
4368 b43err(dev
->wl
, "FOUND UNSUPPORTED PHY (Analog %u, Type %d (%s), Revision %u)\n",
4369 analog_type
, phy_type
, b43_phy_name(dev
, phy_type
),
4373 b43info(dev
->wl
, "Found PHY: Analog %u, Type %d (%s), Revision %u\n",
4374 analog_type
, phy_type
, b43_phy_name(dev
, phy_type
), phy_rev
);
4376 /* Get RADIO versioning */
4377 if (dev
->dev
->core_rev
>= 24) {
4380 for (tmp
= 0; tmp
< 3; tmp
++) {
4381 b43_write16(dev
, B43_MMIO_RADIO24_CONTROL
, tmp
);
4382 radio24
[tmp
] = b43_read16(dev
, B43_MMIO_RADIO24_DATA
);
4385 /* Broadcom uses "id" for our "ver" and has separated "ver" */
4386 /* radio_ver = (radio24[0] & 0xF0) >> 4; */
4388 radio_manuf
= 0x17F;
4389 radio_ver
= (radio24
[2] << 8) | radio24
[1];
4390 radio_rev
= (radio24
[0] & 0xF);
4392 if (dev
->dev
->chip_id
== 0x4317) {
4393 if (dev
->dev
->chip_rev
== 0)
4395 else if (dev
->dev
->chip_rev
== 1)
4400 b43_write16(dev
, B43_MMIO_RADIO_CONTROL
,
4402 tmp
= b43_read16(dev
, B43_MMIO_RADIO_DATA_LOW
);
4403 b43_write16(dev
, B43_MMIO_RADIO_CONTROL
,
4405 tmp
|= (u32
)b43_read16(dev
, B43_MMIO_RADIO_DATA_HIGH
)
4408 radio_manuf
= (tmp
& 0x00000FFF);
4409 radio_ver
= (tmp
& 0x0FFFF000) >> 12;
4410 radio_rev
= (tmp
& 0xF0000000) >> 28;
4413 if (radio_manuf
!= 0x17F /* Broadcom */)
4417 if (radio_ver
!= 0x2060)
4421 if (radio_manuf
!= 0x17F)
4425 if ((radio_ver
& 0xFFF0) != 0x2050)
4429 if (radio_ver
!= 0x2050)
4433 if (radio_ver
!= 0x2055 && radio_ver
!= 0x2056)
4436 case B43_PHYTYPE_LP
:
4437 if (radio_ver
!= 0x2062 && radio_ver
!= 0x2063)
4440 case B43_PHYTYPE_HT
:
4441 if (radio_ver
!= 0x2059)
4444 case B43_PHYTYPE_LCN
:
4445 if (radio_ver
!= 0x2064)
4452 b43err(dev
->wl
, "FOUND UNSUPPORTED RADIO "
4453 "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
4454 radio_manuf
, radio_ver
, radio_rev
);
4457 b43dbg(dev
->wl
, "Found Radio: Manuf 0x%X, Version 0x%X, Revision %u\n",
4458 radio_manuf
, radio_ver
, radio_rev
);
4460 phy
->radio_manuf
= radio_manuf
;
4461 phy
->radio_ver
= radio_ver
;
4462 phy
->radio_rev
= radio_rev
;
4464 phy
->analog
= analog_type
;
4465 phy
->type
= phy_type
;
4471 static void setup_struct_phy_for_init(struct b43_wldev
*dev
,
4472 struct b43_phy
*phy
)
4474 phy
->hardware_power_control
= !!modparam_hwpctl
;
4475 phy
->next_txpwr_check_time
= jiffies
;
4476 /* PHY TX errors counter. */
4477 atomic_set(&phy
->txerr_cnt
, B43_PHY_TX_BADNESS_LIMIT
);
4480 phy
->phy_locked
= false;
4481 phy
->radio_locked
= false;
4485 static void setup_struct_wldev_for_init(struct b43_wldev
*dev
)
4487 dev
->dfq_valid
= false;
4489 /* Assume the radio is enabled. If it's not enabled, the state will
4490 * immediately get fixed on the first periodic work run. */
4491 dev
->radio_hw_enable
= true;
4494 memset(&dev
->stats
, 0, sizeof(dev
->stats
));
4496 setup_struct_phy_for_init(dev
, &dev
->phy
);
4498 /* IRQ related flags */
4499 dev
->irq_reason
= 0;
4500 memset(dev
->dma_reason
, 0, sizeof(dev
->dma_reason
));
4501 dev
->irq_mask
= B43_IRQ_MASKTEMPLATE
;
4502 if (b43_modparam_verbose
< B43_VERBOSITY_DEBUG
)
4503 dev
->irq_mask
&= ~B43_IRQ_PHY_TXERR
;
4505 dev
->mac_suspended
= 1;
4507 /* Noise calculation context */
4508 memset(&dev
->noisecalc
, 0, sizeof(dev
->noisecalc
));
4511 static void b43_bluetooth_coext_enable(struct b43_wldev
*dev
)
4513 struct ssb_sprom
*sprom
= dev
->dev
->bus_sprom
;
4516 if (!modparam_btcoex
)
4518 if (!(sprom
->boardflags_lo
& B43_BFL_BTCOEXIST
))
4520 if (dev
->phy
.type
!= B43_PHYTYPE_B
&& !dev
->phy
.gmode
)
4523 hf
= b43_hf_read(dev
);
4524 if (sprom
->boardflags_lo
& B43_BFL_BTCMOD
)
4525 hf
|= B43_HF_BTCOEXALT
;
4527 hf
|= B43_HF_BTCOEX
;
4528 b43_hf_write(dev
, hf
);
4531 static void b43_bluetooth_coext_disable(struct b43_wldev
*dev
)
4533 if (!modparam_btcoex
)
4538 static void b43_imcfglo_timeouts_workaround(struct b43_wldev
*dev
)
4540 struct ssb_bus
*bus
;
4543 #ifdef CONFIG_B43_SSB
4544 if (dev
->dev
->bus_type
!= B43_BUS_SSB
)
4550 bus
= dev
->dev
->sdev
->bus
;
4552 if ((bus
->chip_id
== 0x4311 && bus
->chip_rev
== 2) ||
4553 (bus
->chip_id
== 0x4312)) {
4554 tmp
= ssb_read32(dev
->dev
->sdev
, SSB_IMCFGLO
);
4555 tmp
&= ~SSB_IMCFGLO_REQTO
;
4556 tmp
&= ~SSB_IMCFGLO_SERTO
;
4558 ssb_write32(dev
->dev
->sdev
, SSB_IMCFGLO
, tmp
);
4559 ssb_commit_settings(bus
);
4563 static void b43_set_synth_pu_delay(struct b43_wldev
*dev
, bool idle
)
4567 /* The time value is in microseconds. */
4568 if (dev
->phy
.type
== B43_PHYTYPE_A
)
4572 if (b43_is_mode(dev
->wl
, NL80211_IFTYPE_ADHOC
) || idle
)
4574 if ((dev
->phy
.radio_ver
== 0x2050) && (dev
->phy
.radio_rev
== 8))
4575 pu_delay
= max(pu_delay
, (u16
)2400);
4577 b43_shm_write16(dev
, B43_SHM_SHARED
, B43_SHM_SH_SPUWKUP
, pu_delay
);
4580 /* Set the TSF CFP pre-TargetBeaconTransmissionTime. */
4581 static void b43_set_pretbtt(struct b43_wldev
*dev
)
4585 /* The time value is in microseconds. */
4586 if (b43_is_mode(dev
->wl
, NL80211_IFTYPE_ADHOC
)) {
4589 if (dev
->phy
.type
== B43_PHYTYPE_A
)
4594 b43_shm_write16(dev
, B43_SHM_SHARED
, B43_SHM_SH_PRETBTT
, pretbtt
);
4595 b43_write16(dev
, B43_MMIO_TSF_CFP_PRETBTT
, pretbtt
);
4598 /* Shutdown a wireless core */
4599 /* Locking: wl->mutex */
4600 static void b43_wireless_core_exit(struct b43_wldev
*dev
)
4602 B43_WARN_ON(dev
&& b43_status(dev
) > B43_STAT_INITIALIZED
);
4603 if (!dev
|| b43_status(dev
) != B43_STAT_INITIALIZED
)
4606 b43_set_status(dev
, B43_STAT_UNINIT
);
4608 /* Stop the microcode PSM. */
4609 b43_maskset32(dev
, B43_MMIO_MACCTL
, ~B43_MACCTL_PSM_RUN
,
4610 B43_MACCTL_PSM_JMP0
);
4612 switch (dev
->dev
->bus_type
) {
4613 #ifdef CONFIG_B43_BCMA
4615 bcma_core_pci_down(dev
->dev
->bdev
->bus
);
4618 #ifdef CONFIG_B43_SSB
4628 dev
->phy
.ops
->switch_analog(dev
, 0);
4629 if (dev
->wl
->current_beacon
) {
4630 dev_kfree_skb_any(dev
->wl
->current_beacon
);
4631 dev
->wl
->current_beacon
= NULL
;
4634 b43_device_disable(dev
, 0);
4635 b43_bus_may_powerdown(dev
);
4638 /* Initialize a wireless core */
4639 static int b43_wireless_core_init(struct b43_wldev
*dev
)
4641 struct ssb_sprom
*sprom
= dev
->dev
->bus_sprom
;
4642 struct b43_phy
*phy
= &dev
->phy
;
4646 B43_WARN_ON(b43_status(dev
) != B43_STAT_UNINIT
);
4648 err
= b43_bus_powerup(dev
, 0);
4651 if (!b43_device_is_enabled(dev
))
4652 b43_wireless_core_reset(dev
, phy
->gmode
);
4654 /* Reset all data structures. */
4655 setup_struct_wldev_for_init(dev
);
4656 phy
->ops
->prepare_structs(dev
);
4658 /* Enable IRQ routing to this device. */
4659 switch (dev
->dev
->bus_type
) {
4660 #ifdef CONFIG_B43_BCMA
4662 bcma_core_pci_irq_ctl(&dev
->dev
->bdev
->bus
->drv_pci
[0],
4663 dev
->dev
->bdev
, true);
4664 bcma_core_pci_up(dev
->dev
->bdev
->bus
);
4667 #ifdef CONFIG_B43_SSB
4669 ssb_pcicore_dev_irqvecs_enable(&dev
->dev
->sdev
->bus
->pcicore
,
4675 b43_imcfglo_timeouts_workaround(dev
);
4676 b43_bluetooth_coext_disable(dev
);
4677 if (phy
->ops
->prepare_hardware
) {
4678 err
= phy
->ops
->prepare_hardware(dev
);
4682 err
= b43_chip_init(dev
);
4685 b43_shm_write16(dev
, B43_SHM_SHARED
,
4686 B43_SHM_SH_WLCOREREV
, dev
->dev
->core_rev
);
4687 hf
= b43_hf_read(dev
);
4688 if (phy
->type
== B43_PHYTYPE_G
) {
4692 if (sprom
->boardflags_lo
& B43_BFL_PACTRL
)
4693 hf
|= B43_HF_OFDMPABOOST
;
4695 if (phy
->radio_ver
== 0x2050) {
4696 if (phy
->radio_rev
== 6)
4697 hf
|= B43_HF_4318TSSI
;
4698 if (phy
->radio_rev
< 6)
4699 hf
|= B43_HF_VCORECALC
;
4701 if (sprom
->boardflags_lo
& B43_BFL_XTAL_NOSLOW
)
4702 hf
|= B43_HF_DSCRQ
; /* Disable slowclock requests from ucode. */
4703 #if defined(CONFIG_B43_SSB) && defined(CONFIG_SSB_DRIVER_PCICORE)
4704 if (dev
->dev
->bus_type
== B43_BUS_SSB
&&
4705 dev
->dev
->sdev
->bus
->bustype
== SSB_BUSTYPE_PCI
&&
4706 dev
->dev
->sdev
->bus
->pcicore
.dev
->id
.revision
<= 10)
4707 hf
|= B43_HF_PCISCW
; /* PCI slow clock workaround. */
4709 hf
&= ~B43_HF_SKCFPUP
;
4710 b43_hf_write(dev
, hf
);
4712 b43_set_retry_limits(dev
, B43_DEFAULT_SHORT_RETRY_LIMIT
,
4713 B43_DEFAULT_LONG_RETRY_LIMIT
);
4714 b43_shm_write16(dev
, B43_SHM_SHARED
, B43_SHM_SH_SFFBLIM
, 3);
4715 b43_shm_write16(dev
, B43_SHM_SHARED
, B43_SHM_SH_LFFBLIM
, 2);
4717 /* Disable sending probe responses from firmware.
4718 * Setting the MaxTime to one usec will always trigger
4719 * a timeout, so we never send any probe resp.
4720 * A timeout of zero is infinite. */
4721 b43_shm_write16(dev
, B43_SHM_SHARED
, B43_SHM_SH_PRMAXTIME
, 1);
4723 b43_rate_memory_init(dev
);
4724 b43_set_phytxctl_defaults(dev
);
4726 /* Minimum Contention Window */
4727 if (phy
->type
== B43_PHYTYPE_B
)
4728 b43_shm_write16(dev
, B43_SHM_SCRATCH
, B43_SHM_SC_MINCONT
, 0x1F);
4730 b43_shm_write16(dev
, B43_SHM_SCRATCH
, B43_SHM_SC_MINCONT
, 0xF);
4731 /* Maximum Contention Window */
4732 b43_shm_write16(dev
, B43_SHM_SCRATCH
, B43_SHM_SC_MAXCONT
, 0x3FF);
4734 if (b43_bus_host_is_pcmcia(dev
->dev
) ||
4735 b43_bus_host_is_sdio(dev
->dev
)) {
4736 dev
->__using_pio_transfers
= true;
4737 err
= b43_pio_init(dev
);
4738 } else if (dev
->use_pio
) {
4739 b43warn(dev
->wl
, "Forced PIO by use_pio module parameter. "
4740 "This should not be needed and will result in lower "
4742 dev
->__using_pio_transfers
= true;
4743 err
= b43_pio_init(dev
);
4745 dev
->__using_pio_transfers
= false;
4746 err
= b43_dma_init(dev
);
4751 b43_set_synth_pu_delay(dev
, 1);
4752 b43_bluetooth_coext_enable(dev
);
4754 b43_bus_powerup(dev
, !(sprom
->boardflags_lo
& B43_BFL_XTAL_NOSLOW
));
4755 b43_upload_card_macaddress(dev
);
4756 b43_security_init(dev
);
4758 ieee80211_wake_queues(dev
->wl
->hw
);
4760 b43_set_status(dev
, B43_STAT_INITIALIZED
);
4768 b43_bus_may_powerdown(dev
);
4769 B43_WARN_ON(b43_status(dev
) != B43_STAT_UNINIT
);
4773 static int b43_op_add_interface(struct ieee80211_hw
*hw
,
4774 struct ieee80211_vif
*vif
)
4776 struct b43_wl
*wl
= hw_to_b43_wl(hw
);
4777 struct b43_wldev
*dev
;
4778 int err
= -EOPNOTSUPP
;
4780 /* TODO: allow WDS/AP devices to coexist */
4782 if (vif
->type
!= NL80211_IFTYPE_AP
&&
4783 vif
->type
!= NL80211_IFTYPE_MESH_POINT
&&
4784 vif
->type
!= NL80211_IFTYPE_STATION
&&
4785 vif
->type
!= NL80211_IFTYPE_WDS
&&
4786 vif
->type
!= NL80211_IFTYPE_ADHOC
)
4789 mutex_lock(&wl
->mutex
);
4791 goto out_mutex_unlock
;
4793 b43dbg(wl
, "Adding Interface type %d\n", vif
->type
);
4795 dev
= wl
->current_dev
;
4796 wl
->operating
= true;
4798 wl
->if_type
= vif
->type
;
4799 memcpy(wl
->mac_addr
, vif
->addr
, ETH_ALEN
);
4801 b43_adjust_opmode(dev
);
4802 b43_set_pretbtt(dev
);
4803 b43_set_synth_pu_delay(dev
, 0);
4804 b43_upload_card_macaddress(dev
);
4808 mutex_unlock(&wl
->mutex
);
4811 b43_op_bss_info_changed(hw
, vif
, &vif
->bss_conf
, ~0);
4816 static void b43_op_remove_interface(struct ieee80211_hw
*hw
,
4817 struct ieee80211_vif
*vif
)
4819 struct b43_wl
*wl
= hw_to_b43_wl(hw
);
4820 struct b43_wldev
*dev
= wl
->current_dev
;
4822 b43dbg(wl
, "Removing Interface type %d\n", vif
->type
);
4824 mutex_lock(&wl
->mutex
);
4826 B43_WARN_ON(!wl
->operating
);
4827 B43_WARN_ON(wl
->vif
!= vif
);
4830 wl
->operating
= false;
4832 b43_adjust_opmode(dev
);
4833 memset(wl
->mac_addr
, 0, ETH_ALEN
);
4834 b43_upload_card_macaddress(dev
);
4836 mutex_unlock(&wl
->mutex
);
4839 static int b43_op_start(struct ieee80211_hw
*hw
)
4841 struct b43_wl
*wl
= hw_to_b43_wl(hw
);
4842 struct b43_wldev
*dev
= wl
->current_dev
;
4846 /* Kill all old instance specific information to make sure
4847 * the card won't use it in the short timeframe between start
4848 * and mac80211 reconfiguring it. */
4849 memset(wl
->bssid
, 0, ETH_ALEN
);
4850 memset(wl
->mac_addr
, 0, ETH_ALEN
);
4851 wl
->filter_flags
= 0;
4852 wl
->radiotap_enabled
= false;
4854 wl
->beacon0_uploaded
= false;
4855 wl
->beacon1_uploaded
= false;
4856 wl
->beacon_templates_virgin
= true;
4857 wl
->radio_enabled
= true;
4859 mutex_lock(&wl
->mutex
);
4861 if (b43_status(dev
) < B43_STAT_INITIALIZED
) {
4862 err
= b43_wireless_core_init(dev
);
4864 goto out_mutex_unlock
;
4868 if (b43_status(dev
) < B43_STAT_STARTED
) {
4869 err
= b43_wireless_core_start(dev
);
4872 b43_wireless_core_exit(dev
);
4873 goto out_mutex_unlock
;
4877 /* XXX: only do if device doesn't support rfkill irq */
4878 wiphy_rfkill_start_polling(hw
->wiphy
);
4881 mutex_unlock(&wl
->mutex
);
4884 * Configuration may have been overwritten during initialization.
4885 * Reload the configuration, but only if initialization was
4886 * successful. Reloading the configuration after a failed init
4887 * may hang the system.
4890 b43_op_config(hw
, ~0);
4895 static void b43_op_stop(struct ieee80211_hw
*hw
)
4897 struct b43_wl
*wl
= hw_to_b43_wl(hw
);
4898 struct b43_wldev
*dev
= wl
->current_dev
;
4900 cancel_work_sync(&(wl
->beacon_update_trigger
));
4905 mutex_lock(&wl
->mutex
);
4906 if (b43_status(dev
) >= B43_STAT_STARTED
) {
4907 dev
= b43_wireless_core_stop(dev
);
4911 b43_wireless_core_exit(dev
);
4912 wl
->radio_enabled
= false;
4915 mutex_unlock(&wl
->mutex
);
4917 cancel_work_sync(&(wl
->txpower_adjust_work
));
4920 static int b43_op_beacon_set_tim(struct ieee80211_hw
*hw
,
4921 struct ieee80211_sta
*sta
, bool set
)
4923 struct b43_wl
*wl
= hw_to_b43_wl(hw
);
4925 /* FIXME: add locking */
4926 b43_update_templates(wl
);
4931 static void b43_op_sta_notify(struct ieee80211_hw
*hw
,
4932 struct ieee80211_vif
*vif
,
4933 enum sta_notify_cmd notify_cmd
,
4934 struct ieee80211_sta
*sta
)
4936 struct b43_wl
*wl
= hw_to_b43_wl(hw
);
4938 B43_WARN_ON(!vif
|| wl
->vif
!= vif
);
4941 static void b43_op_sw_scan_start_notifier(struct ieee80211_hw
*hw
)
4943 struct b43_wl
*wl
= hw_to_b43_wl(hw
);
4944 struct b43_wldev
*dev
;
4946 mutex_lock(&wl
->mutex
);
4947 dev
= wl
->current_dev
;
4948 if (dev
&& (b43_status(dev
) >= B43_STAT_INITIALIZED
)) {
4949 /* Disable CFP update during scan on other channels. */
4950 b43_hf_write(dev
, b43_hf_read(dev
) | B43_HF_SKCFPUP
);
4952 mutex_unlock(&wl
->mutex
);
4955 static void b43_op_sw_scan_complete_notifier(struct ieee80211_hw
*hw
)
4957 struct b43_wl
*wl
= hw_to_b43_wl(hw
);
4958 struct b43_wldev
*dev
;
4960 mutex_lock(&wl
->mutex
);
4961 dev
= wl
->current_dev
;
4962 if (dev
&& (b43_status(dev
) >= B43_STAT_INITIALIZED
)) {
4963 /* Re-enable CFP update. */
4964 b43_hf_write(dev
, b43_hf_read(dev
) & ~B43_HF_SKCFPUP
);
4966 mutex_unlock(&wl
->mutex
);
4969 static int b43_op_get_survey(struct ieee80211_hw
*hw
, int idx
,
4970 struct survey_info
*survey
)
4972 struct b43_wl
*wl
= hw_to_b43_wl(hw
);
4973 struct b43_wldev
*dev
= wl
->current_dev
;
4974 struct ieee80211_conf
*conf
= &hw
->conf
;
4979 survey
->channel
= conf
->chandef
.chan
;
4980 survey
->filled
= SURVEY_INFO_NOISE_DBM
;
4981 survey
->noise
= dev
->stats
.link_noise
;
4986 static const struct ieee80211_ops b43_hw_ops
= {
4988 .conf_tx
= b43_op_conf_tx
,
4989 .add_interface
= b43_op_add_interface
,
4990 .remove_interface
= b43_op_remove_interface
,
4991 .config
= b43_op_config
,
4992 .bss_info_changed
= b43_op_bss_info_changed
,
4993 .configure_filter
= b43_op_configure_filter
,
4994 .set_key
= b43_op_set_key
,
4995 .update_tkip_key
= b43_op_update_tkip_key
,
4996 .get_stats
= b43_op_get_stats
,
4997 .get_tsf
= b43_op_get_tsf
,
4998 .set_tsf
= b43_op_set_tsf
,
4999 .start
= b43_op_start
,
5000 .stop
= b43_op_stop
,
5001 .set_tim
= b43_op_beacon_set_tim
,
5002 .sta_notify
= b43_op_sta_notify
,
5003 .sw_scan_start
= b43_op_sw_scan_start_notifier
,
5004 .sw_scan_complete
= b43_op_sw_scan_complete_notifier
,
5005 .get_survey
= b43_op_get_survey
,
5006 .rfkill_poll
= b43_rfkill_poll
,
5009 /* Hard-reset the chip. Do not call this directly.
5010 * Use b43_controller_restart()
5012 static void b43_chip_reset(struct work_struct
*work
)
5014 struct b43_wldev
*dev
=
5015 container_of(work
, struct b43_wldev
, restart_work
);
5016 struct b43_wl
*wl
= dev
->wl
;
5020 mutex_lock(&wl
->mutex
);
5022 prev_status
= b43_status(dev
);
5023 /* Bring the device down... */
5024 if (prev_status
>= B43_STAT_STARTED
) {
5025 dev
= b43_wireless_core_stop(dev
);
5031 if (prev_status
>= B43_STAT_INITIALIZED
)
5032 b43_wireless_core_exit(dev
);
5034 /* ...and up again. */
5035 if (prev_status
>= B43_STAT_INITIALIZED
) {
5036 err
= b43_wireless_core_init(dev
);
5040 if (prev_status
>= B43_STAT_STARTED
) {
5041 err
= b43_wireless_core_start(dev
);
5043 b43_wireless_core_exit(dev
);
5049 wl
->current_dev
= NULL
; /* Failed to init the dev. */
5050 mutex_unlock(&wl
->mutex
);
5053 b43err(wl
, "Controller restart FAILED\n");
5057 /* reload configuration */
5058 b43_op_config(wl
->hw
, ~0);
5060 b43_op_bss_info_changed(wl
->hw
, wl
->vif
, &wl
->vif
->bss_conf
, ~0);
5062 b43info(wl
, "Controller restarted\n");
5065 static int b43_setup_bands(struct b43_wldev
*dev
,
5066 bool have_2ghz_phy
, bool have_5ghz_phy
)
5068 struct ieee80211_hw
*hw
= dev
->wl
->hw
;
5071 hw
->wiphy
->bands
[IEEE80211_BAND_2GHZ
] = &b43_band_2GHz
;
5072 if (dev
->phy
.type
== B43_PHYTYPE_N
) {
5074 hw
->wiphy
->bands
[IEEE80211_BAND_5GHZ
] = &b43_band_5GHz_nphy
;
5077 hw
->wiphy
->bands
[IEEE80211_BAND_5GHZ
] = &b43_band_5GHz_aphy
;
5080 dev
->phy
.supports_2ghz
= have_2ghz_phy
;
5081 dev
->phy
.supports_5ghz
= have_5ghz_phy
;
5086 static void b43_wireless_core_detach(struct b43_wldev
*dev
)
5088 /* We release firmware that late to not be required to re-request
5089 * is all the time when we reinit the core. */
5090 b43_release_firmware(dev
);
5094 static void b43_supported_bands(struct b43_wldev
*dev
, bool *have_2ghz_phy
,
5095 bool *have_5ghz_phy
)
5099 #ifdef CONFIG_B43_BCMA
5100 if (dev
->dev
->bus_type
== B43_BUS_BCMA
&&
5101 dev
->dev
->bdev
->bus
->hosttype
== BCMA_HOSTTYPE_PCI
)
5102 dev_id
= dev
->dev
->bdev
->bus
->host_pci
->device
;
5104 #ifdef CONFIG_B43_SSB
5105 if (dev
->dev
->bus_type
== B43_BUS_SSB
&&
5106 dev
->dev
->sdev
->bus
->bustype
== SSB_BUSTYPE_PCI
)
5107 dev_id
= dev
->dev
->sdev
->bus
->host_pci
->device
;
5109 /* Override with SPROM value if available */
5110 if (dev
->dev
->bus_sprom
->dev_id
)
5111 dev_id
= dev
->dev
->bus_sprom
->dev_id
;
5113 /* Note: below IDs can be "virtual" (not maching e.g. real PCI ID) */
5115 case 0x4324: /* BCM4306 */
5116 case 0x4312: /* BCM4311 */
5117 case 0x4319: /* BCM4318 */
5118 case 0x4328: /* BCM4321 */
5119 case 0x432b: /* BCM4322 */
5120 case 0x4350: /* BCM43222 */
5121 case 0x4353: /* BCM43224 */
5122 case 0x0576: /* BCM43224 */
5123 case 0x435f: /* BCM6362 */
5124 case 0x4331: /* BCM4331 */
5125 case 0x4359: /* BCM43228 */
5126 case 0x43a0: /* BCM4360 */
5127 case 0x43b1: /* BCM4352 */
5128 /* Dual band devices */
5129 *have_2ghz_phy
= true;
5130 *have_5ghz_phy
= true;
5132 case 0x4321: /* BCM4306 */
5133 case 0x4313: /* BCM4311 */
5134 case 0x431a: /* BCM4318 */
5135 case 0x432a: /* BCM4321 */
5136 case 0x432d: /* BCM4322 */
5137 case 0x4352: /* BCM43222 */
5138 case 0x4333: /* BCM4331 */
5139 case 0x43a2: /* BCM4360 */
5140 case 0x43b3: /* BCM4352 */
5141 /* 5 GHz only devices */
5142 *have_2ghz_phy
= false;
5143 *have_5ghz_phy
= true;
5147 /* As a fallback, try to guess using PHY type */
5148 switch (dev
->phy
.type
) {
5150 *have_2ghz_phy
= false;
5151 *have_5ghz_phy
= true;
5155 case B43_PHYTYPE_LP
:
5156 case B43_PHYTYPE_HT
:
5157 case B43_PHYTYPE_LCN
:
5158 *have_2ghz_phy
= true;
5159 *have_5ghz_phy
= false;
5166 static int b43_wireless_core_attach(struct b43_wldev
*dev
)
5168 struct b43_wl
*wl
= dev
->wl
;
5169 struct b43_phy
*phy
= &dev
->phy
;
5172 bool have_2ghz_phy
= false, have_5ghz_phy
= false;
5174 /* Do NOT do any device initialization here.
5175 * Do it in wireless_core_init() instead.
5176 * This function is for gathering basic information about the HW, only.
5177 * Also some structs may be set up here. But most likely you want to have
5178 * that in core_init(), too.
5181 err
= b43_bus_powerup(dev
, 0);
5183 b43err(wl
, "Bus powerup failed\n");
5187 phy
->do_full_init
= true;
5189 /* Try to guess supported bands for the first init needs */
5190 switch (dev
->dev
->bus_type
) {
5191 #ifdef CONFIG_B43_BCMA
5193 tmp
= bcma_aread32(dev
->dev
->bdev
, BCMA_IOST
);
5194 have_2ghz_phy
= !!(tmp
& B43_BCMA_IOST_2G_PHY
);
5195 have_5ghz_phy
= !!(tmp
& B43_BCMA_IOST_5G_PHY
);
5198 #ifdef CONFIG_B43_SSB
5200 if (dev
->dev
->core_rev
>= 5) {
5201 tmp
= ssb_read32(dev
->dev
->sdev
, SSB_TMSHIGH
);
5202 have_2ghz_phy
= !!(tmp
& B43_TMSHIGH_HAVE_2GHZ_PHY
);
5203 have_5ghz_phy
= !!(tmp
& B43_TMSHIGH_HAVE_5GHZ_PHY
);
5210 dev
->phy
.gmode
= have_2ghz_phy
;
5211 b43_wireless_core_reset(dev
, dev
->phy
.gmode
);
5213 /* Get the PHY type. */
5214 err
= b43_phy_versioning(dev
);
5218 /* Get real info about supported bands */
5219 b43_supported_bands(dev
, &have_2ghz_phy
, &have_5ghz_phy
);
5221 /* We don't support 5 GHz on some PHYs yet */
5222 switch (dev
->phy
.type
) {
5226 case B43_PHYTYPE_LP
:
5227 case B43_PHYTYPE_HT
:
5228 b43warn(wl
, "5 GHz band is unsupported on this PHY\n");
5229 have_5ghz_phy
= false;
5232 if (!have_2ghz_phy
&& !have_5ghz_phy
) {
5233 b43err(wl
, "b43 can't support any band on this device\n");
5238 err
= b43_phy_allocate(dev
);
5242 dev
->phy
.gmode
= have_2ghz_phy
;
5243 b43_wireless_core_reset(dev
, dev
->phy
.gmode
);
5245 err
= b43_validate_chipaccess(dev
);
5248 err
= b43_setup_bands(dev
, have_2ghz_phy
, have_5ghz_phy
);
5252 /* Now set some default "current_dev" */
5253 if (!wl
->current_dev
)
5254 wl
->current_dev
= dev
;
5255 INIT_WORK(&dev
->restart_work
, b43_chip_reset
);
5257 dev
->phy
.ops
->switch_analog(dev
, 0);
5258 b43_device_disable(dev
, 0);
5259 b43_bus_may_powerdown(dev
);
5267 b43_bus_may_powerdown(dev
);
5271 static void b43_one_core_detach(struct b43_bus_dev
*dev
)
5273 struct b43_wldev
*wldev
;
5276 /* Do not cancel ieee80211-workqueue based work here.
5277 * See comment in b43_remove(). */
5279 wldev
= b43_bus_get_wldev(dev
);
5281 b43_debugfs_remove_device(wldev
);
5282 b43_wireless_core_detach(wldev
);
5283 list_del(&wldev
->list
);
5284 b43_bus_set_wldev(dev
, NULL
);
5288 static int b43_one_core_attach(struct b43_bus_dev
*dev
, struct b43_wl
*wl
)
5290 struct b43_wldev
*wldev
;
5293 wldev
= kzalloc(sizeof(*wldev
), GFP_KERNEL
);
5297 wldev
->use_pio
= b43_modparam_pio
;
5300 b43_set_status(wldev
, B43_STAT_UNINIT
);
5301 wldev
->bad_frames_preempt
= modparam_bad_frames_preempt
;
5302 INIT_LIST_HEAD(&wldev
->list
);
5304 err
= b43_wireless_core_attach(wldev
);
5306 goto err_kfree_wldev
;
5308 b43_bus_set_wldev(dev
, wldev
);
5309 b43_debugfs_add_device(wldev
);
5319 #define IS_PDEV(pdev, _vendor, _device, _subvendor, _subdevice) ( \
5320 (pdev->vendor == PCI_VENDOR_ID_##_vendor) && \
5321 (pdev->device == _device) && \
5322 (pdev->subsystem_vendor == PCI_VENDOR_ID_##_subvendor) && \
5323 (pdev->subsystem_device == _subdevice) )
5325 #ifdef CONFIG_B43_SSB
5326 static void b43_sprom_fixup(struct ssb_bus
*bus
)
5328 struct pci_dev
*pdev
;
5330 /* boardflags workarounds */
5331 if (bus
->boardinfo
.vendor
== SSB_BOARDVENDOR_DELL
&&
5332 bus
->chip_id
== 0x4301 && bus
->sprom
.board_rev
== 0x74)
5333 bus
->sprom
.boardflags_lo
|= B43_BFL_BTCOEXIST
;
5334 if (bus
->boardinfo
.vendor
== PCI_VENDOR_ID_APPLE
&&
5335 bus
->boardinfo
.type
== 0x4E && bus
->sprom
.board_rev
> 0x40)
5336 bus
->sprom
.boardflags_lo
|= B43_BFL_PACTRL
;
5337 if (bus
->bustype
== SSB_BUSTYPE_PCI
) {
5338 pdev
= bus
->host_pci
;
5339 if (IS_PDEV(pdev
, BROADCOM
, 0x4318, ASUSTEK
, 0x100F) ||
5340 IS_PDEV(pdev
, BROADCOM
, 0x4320, DELL
, 0x0003) ||
5341 IS_PDEV(pdev
, BROADCOM
, 0x4320, HP
, 0x12f8) ||
5342 IS_PDEV(pdev
, BROADCOM
, 0x4320, LINKSYS
, 0x0015) ||
5343 IS_PDEV(pdev
, BROADCOM
, 0x4320, LINKSYS
, 0x0014) ||
5344 IS_PDEV(pdev
, BROADCOM
, 0x4320, LINKSYS
, 0x0013) ||
5345 IS_PDEV(pdev
, BROADCOM
, 0x4320, MOTOROLA
, 0x7010))
5346 bus
->sprom
.boardflags_lo
&= ~B43_BFL_BTCOEXIST
;
5350 static void b43_wireless_exit(struct b43_bus_dev
*dev
, struct b43_wl
*wl
)
5352 struct ieee80211_hw
*hw
= wl
->hw
;
5354 ssb_set_devtypedata(dev
->sdev
, NULL
);
5355 ieee80211_free_hw(hw
);
5359 static struct b43_wl
*b43_wireless_init(struct b43_bus_dev
*dev
)
5361 struct ssb_sprom
*sprom
= dev
->bus_sprom
;
5362 struct ieee80211_hw
*hw
;
5367 hw
= ieee80211_alloc_hw(sizeof(*wl
), &b43_hw_ops
);
5369 b43err(NULL
, "Could not allocate ieee80211 device\n");
5370 return ERR_PTR(-ENOMEM
);
5372 wl
= hw_to_b43_wl(hw
);
5375 hw
->flags
= IEEE80211_HW_RX_INCLUDES_FCS
|
5376 IEEE80211_HW_SIGNAL_DBM
;
5378 hw
->wiphy
->interface_modes
=
5379 BIT(NL80211_IFTYPE_AP
) |
5380 BIT(NL80211_IFTYPE_MESH_POINT
) |
5381 BIT(NL80211_IFTYPE_STATION
) |
5382 BIT(NL80211_IFTYPE_WDS
) |
5383 BIT(NL80211_IFTYPE_ADHOC
);
5385 hw
->wiphy
->flags
|= WIPHY_FLAG_IBSS_RSN
;
5387 wl
->hw_registred
= false;
5389 SET_IEEE80211_DEV(hw
, dev
->dev
);
5390 if (is_valid_ether_addr(sprom
->et1mac
))
5391 SET_IEEE80211_PERM_ADDR(hw
, sprom
->et1mac
);
5393 SET_IEEE80211_PERM_ADDR(hw
, sprom
->il0mac
);
5395 /* Initialize struct b43_wl */
5397 mutex_init(&wl
->mutex
);
5398 spin_lock_init(&wl
->hardirq_lock
);
5399 INIT_WORK(&wl
->beacon_update_trigger
, b43_beacon_update_trigger_work
);
5400 INIT_WORK(&wl
->txpower_adjust_work
, b43_phy_txpower_adjust_work
);
5401 INIT_WORK(&wl
->tx_work
, b43_tx_work
);
5403 /* Initialize queues and flags. */
5404 for (queue_num
= 0; queue_num
< B43_QOS_QUEUE_NUM
; queue_num
++) {
5405 skb_queue_head_init(&wl
->tx_queue
[queue_num
]);
5406 wl
->tx_queue_stopped
[queue_num
] = 0;
5409 snprintf(chip_name
, ARRAY_SIZE(chip_name
),
5410 (dev
->chip_id
> 0x9999) ? "%d" : "%04X", dev
->chip_id
);
5411 b43info(wl
, "Broadcom %s WLAN found (core revision %u)\n", chip_name
,
5416 #ifdef CONFIG_B43_BCMA
5417 static int b43_bcma_probe(struct bcma_device
*core
)
5419 struct b43_bus_dev
*dev
;
5423 if (!modparam_allhwsupport
&&
5424 (core
->id
.rev
== 0x17 || core
->id
.rev
== 0x18)) {
5425 pr_err("Support for cores revisions 0x17 and 0x18 disabled by module param allhwsupport=0. Try b43.allhwsupport=1\n");
5429 dev
= b43_bus_dev_bcma_init(core
);
5433 wl
= b43_wireless_init(dev
);
5439 err
= b43_one_core_attach(dev
, wl
);
5441 goto bcma_err_wireless_exit
;
5443 /* setup and start work to load firmware */
5444 INIT_WORK(&wl
->firmware_load
, b43_request_firmware
);
5445 schedule_work(&wl
->firmware_load
);
5450 bcma_err_wireless_exit
:
5451 ieee80211_free_hw(wl
->hw
);
5455 static void b43_bcma_remove(struct bcma_device
*core
)
5457 struct b43_wldev
*wldev
= bcma_get_drvdata(core
);
5458 struct b43_wl
*wl
= wldev
->wl
;
5460 /* We must cancel any work here before unregistering from ieee80211,
5461 * as the ieee80211 unreg will destroy the workqueue. */
5462 cancel_work_sync(&wldev
->restart_work
);
5463 cancel_work_sync(&wl
->firmware_load
);
5466 if (!wldev
->fw
.ucode
.data
)
5467 return; /* NULL if firmware never loaded */
5468 if (wl
->current_dev
== wldev
&& wl
->hw_registred
) {
5469 b43_leds_stop(wldev
);
5470 ieee80211_unregister_hw(wl
->hw
);
5473 b43_one_core_detach(wldev
->dev
);
5475 /* Unregister HW RNG driver */
5478 b43_leds_unregister(wl
);
5480 ieee80211_free_hw(wl
->hw
);
5483 static struct bcma_driver b43_bcma_driver
= {
5484 .name
= KBUILD_MODNAME
,
5485 .id_table
= b43_bcma_tbl
,
5486 .probe
= b43_bcma_probe
,
5487 .remove
= b43_bcma_remove
,
5491 #ifdef CONFIG_B43_SSB
5493 int b43_ssb_probe(struct ssb_device
*sdev
, const struct ssb_device_id
*id
)
5495 struct b43_bus_dev
*dev
;
5499 dev
= b43_bus_dev_ssb_init(sdev
);
5503 wl
= ssb_get_devtypedata(sdev
);
5505 b43err(NULL
, "Dual-core devices are not supported\n");
5507 goto err_ssb_kfree_dev
;
5510 b43_sprom_fixup(sdev
->bus
);
5512 wl
= b43_wireless_init(dev
);
5515 goto err_ssb_kfree_dev
;
5517 ssb_set_devtypedata(sdev
, wl
);
5518 B43_WARN_ON(ssb_get_devtypedata(sdev
) != wl
);
5520 err
= b43_one_core_attach(dev
, wl
);
5522 goto err_ssb_wireless_exit
;
5524 /* setup and start work to load firmware */
5525 INIT_WORK(&wl
->firmware_load
, b43_request_firmware
);
5526 schedule_work(&wl
->firmware_load
);
5530 err_ssb_wireless_exit
:
5531 b43_wireless_exit(dev
, wl
);
5537 static void b43_ssb_remove(struct ssb_device
*sdev
)
5539 struct b43_wl
*wl
= ssb_get_devtypedata(sdev
);
5540 struct b43_wldev
*wldev
= ssb_get_drvdata(sdev
);
5541 struct b43_bus_dev
*dev
= wldev
->dev
;
5543 /* We must cancel any work here before unregistering from ieee80211,
5544 * as the ieee80211 unreg will destroy the workqueue. */
5545 cancel_work_sync(&wldev
->restart_work
);
5546 cancel_work_sync(&wl
->firmware_load
);
5549 if (!wldev
->fw
.ucode
.data
)
5550 return; /* NULL if firmware never loaded */
5551 if (wl
->current_dev
== wldev
&& wl
->hw_registred
) {
5552 b43_leds_stop(wldev
);
5553 ieee80211_unregister_hw(wl
->hw
);
5556 b43_one_core_detach(dev
);
5558 /* Unregister HW RNG driver */
5561 b43_leds_unregister(wl
);
5562 b43_wireless_exit(dev
, wl
);
5565 static struct ssb_driver b43_ssb_driver
= {
5566 .name
= KBUILD_MODNAME
,
5567 .id_table
= b43_ssb_tbl
,
5568 .probe
= b43_ssb_probe
,
5569 .remove
= b43_ssb_remove
,
5571 #endif /* CONFIG_B43_SSB */
5573 /* Perform a hardware reset. This can be called from any context. */
5574 void b43_controller_restart(struct b43_wldev
*dev
, const char *reason
)
5576 /* Must avoid requeueing, if we are in shutdown. */
5577 if (b43_status(dev
) < B43_STAT_INITIALIZED
)
5579 b43info(dev
->wl
, "Controller RESET (%s) ...\n", reason
);
5580 ieee80211_queue_work(dev
->wl
->hw
, &dev
->restart_work
);
5583 static void b43_print_driverinfo(void)
5585 const char *feat_pci
= "", *feat_pcmcia
= "", *feat_nphy
= "",
5586 *feat_leds
= "", *feat_sdio
= "";
5588 #ifdef CONFIG_B43_PCI_AUTOSELECT
5591 #ifdef CONFIG_B43_PCMCIA
5594 #ifdef CONFIG_B43_PHY_N
5597 #ifdef CONFIG_B43_LEDS
5600 #ifdef CONFIG_B43_SDIO
5603 printk(KERN_INFO
"Broadcom 43xx driver loaded "
5604 "[ Features: %s%s%s%s%s ]\n",
5605 feat_pci
, feat_pcmcia
, feat_nphy
,
5606 feat_leds
, feat_sdio
);
5609 static int __init
b43_init(void)
5614 err
= b43_pcmcia_init();
5617 err
= b43_sdio_init();
5619 goto err_pcmcia_exit
;
5620 #ifdef CONFIG_B43_BCMA
5621 err
= bcma_driver_register(&b43_bcma_driver
);
5625 #ifdef CONFIG_B43_SSB
5626 err
= ssb_driver_register(&b43_ssb_driver
);
5628 goto err_bcma_driver_exit
;
5630 b43_print_driverinfo();
5634 #ifdef CONFIG_B43_SSB
5635 err_bcma_driver_exit
:
5637 #ifdef CONFIG_B43_BCMA
5638 bcma_driver_unregister(&b43_bcma_driver
);
5649 static void __exit
b43_exit(void)
5651 #ifdef CONFIG_B43_SSB
5652 ssb_driver_unregister(&b43_ssb_driver
);
5654 #ifdef CONFIG_B43_BCMA
5655 bcma_driver_unregister(&b43_bcma_driver
);
5662 module_init(b43_init
)
5663 module_exit(b43_exit
)