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Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wirel...
[deliverable/linux.git] / drivers / net / wireless / b43 / main.c
1 /*
2
3 Broadcom B43 wireless driver
4
5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
6 Copyright (c) 2005 Stefano Brivio <stefano.brivio@polimi.it>
7 Copyright (c) 2005-2009 Michael Buesch <mb@bu3sch.de>
8 Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
9 Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
10
11 Some parts of the code in this file are derived from the ipw2200
12 driver Copyright(c) 2003 - 2004 Intel Corporation.
13
14 This program is free software; you can redistribute it and/or modify
15 it under the terms of the GNU General Public License as published by
16 the Free Software Foundation; either version 2 of the License, or
17 (at your option) any later version.
18
19 This program is distributed in the hope that it will be useful,
20 but WITHOUT ANY WARRANTY; without even the implied warranty of
21 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 GNU General Public License for more details.
23
24 You should have received a copy of the GNU General Public License
25 along with this program; see the file COPYING. If not, write to
26 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
27 Boston, MA 02110-1301, USA.
28
29 */
30
31 #include <linux/delay.h>
32 #include <linux/init.h>
33 #include <linux/moduleparam.h>
34 #include <linux/if_arp.h>
35 #include <linux/etherdevice.h>
36 #include <linux/firmware.h>
37 #include <linux/wireless.h>
38 #include <linux/workqueue.h>
39 #include <linux/skbuff.h>
40 #include <linux/io.h>
41 #include <linux/dma-mapping.h>
42 #include <asm/unaligned.h>
43
44 #include "b43.h"
45 #include "main.h"
46 #include "debugfs.h"
47 #include "phy_common.h"
48 #include "phy_g.h"
49 #include "phy_n.h"
50 #include "dma.h"
51 #include "pio.h"
52 #include "sysfs.h"
53 #include "xmit.h"
54 #include "lo.h"
55 #include "pcmcia.h"
56
57 MODULE_DESCRIPTION("Broadcom B43 wireless driver");
58 MODULE_AUTHOR("Martin Langer");
59 MODULE_AUTHOR("Stefano Brivio");
60 MODULE_AUTHOR("Michael Buesch");
61 MODULE_LICENSE("GPL");
62
63 MODULE_FIRMWARE(B43_SUPPORTED_FIRMWARE_ID);
64
65
66 static int modparam_bad_frames_preempt;
67 module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
68 MODULE_PARM_DESC(bad_frames_preempt,
69 "enable(1) / disable(0) Bad Frames Preemption");
70
71 static char modparam_fwpostfix[16];
72 module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
73 MODULE_PARM_DESC(fwpostfix, "Postfix for the .fw files to load.");
74
75 static int modparam_hwpctl;
76 module_param_named(hwpctl, modparam_hwpctl, int, 0444);
77 MODULE_PARM_DESC(hwpctl, "Enable hardware-side power control (default off)");
78
79 static int modparam_nohwcrypt;
80 module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
81 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
82
83 static int modparam_hwtkip;
84 module_param_named(hwtkip, modparam_hwtkip, int, 0444);
85 MODULE_PARM_DESC(hwtkip, "Enable hardware tkip.");
86
87 static int modparam_qos = 1;
88 module_param_named(qos, modparam_qos, int, 0444);
89 MODULE_PARM_DESC(qos, "Enable QOS support (default on)");
90
91 static int modparam_btcoex = 1;
92 module_param_named(btcoex, modparam_btcoex, int, 0444);
93 MODULE_PARM_DESC(btcoex, "Enable Bluetooth coexistance (default on)");
94
95 int b43_modparam_verbose = B43_VERBOSITY_DEFAULT;
96 module_param_named(verbose, b43_modparam_verbose, int, 0644);
97 MODULE_PARM_DESC(verbose, "Log message verbosity: 0=error, 1=warn, 2=info(default), 3=debug");
98
99
100 static const struct ssb_device_id b43_ssb_tbl[] = {
101 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 5),
102 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 6),
103 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 7),
104 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 9),
105 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 10),
106 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 11),
107 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 13),
108 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 15),
109 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 16),
110 SSB_DEVTABLE_END
111 };
112
113 MODULE_DEVICE_TABLE(ssb, b43_ssb_tbl);
114
115 /* Channel and ratetables are shared for all devices.
116 * They can't be const, because ieee80211 puts some precalculated
117 * data in there. This data is the same for all devices, so we don't
118 * get concurrency issues */
119 #define RATETAB_ENT(_rateid, _flags) \
120 { \
121 .bitrate = B43_RATE_TO_BASE100KBPS(_rateid), \
122 .hw_value = (_rateid), \
123 .flags = (_flags), \
124 }
125
126 /*
127 * NOTE: When changing this, sync with xmit.c's
128 * b43_plcp_get_bitrate_idx_* functions!
129 */
130 static struct ieee80211_rate __b43_ratetable[] = {
131 RATETAB_ENT(B43_CCK_RATE_1MB, 0),
132 RATETAB_ENT(B43_CCK_RATE_2MB, IEEE80211_RATE_SHORT_PREAMBLE),
133 RATETAB_ENT(B43_CCK_RATE_5MB, IEEE80211_RATE_SHORT_PREAMBLE),
134 RATETAB_ENT(B43_CCK_RATE_11MB, IEEE80211_RATE_SHORT_PREAMBLE),
135 RATETAB_ENT(B43_OFDM_RATE_6MB, 0),
136 RATETAB_ENT(B43_OFDM_RATE_9MB, 0),
137 RATETAB_ENT(B43_OFDM_RATE_12MB, 0),
138 RATETAB_ENT(B43_OFDM_RATE_18MB, 0),
139 RATETAB_ENT(B43_OFDM_RATE_24MB, 0),
140 RATETAB_ENT(B43_OFDM_RATE_36MB, 0),
141 RATETAB_ENT(B43_OFDM_RATE_48MB, 0),
142 RATETAB_ENT(B43_OFDM_RATE_54MB, 0),
143 };
144
145 #define b43_a_ratetable (__b43_ratetable + 4)
146 #define b43_a_ratetable_size 8
147 #define b43_b_ratetable (__b43_ratetable + 0)
148 #define b43_b_ratetable_size 4
149 #define b43_g_ratetable (__b43_ratetable + 0)
150 #define b43_g_ratetable_size 12
151
152 #define CHAN4G(_channel, _freq, _flags) { \
153 .band = IEEE80211_BAND_2GHZ, \
154 .center_freq = (_freq), \
155 .hw_value = (_channel), \
156 .flags = (_flags), \
157 .max_antenna_gain = 0, \
158 .max_power = 30, \
159 }
160 static struct ieee80211_channel b43_2ghz_chantable[] = {
161 CHAN4G(1, 2412, 0),
162 CHAN4G(2, 2417, 0),
163 CHAN4G(3, 2422, 0),
164 CHAN4G(4, 2427, 0),
165 CHAN4G(5, 2432, 0),
166 CHAN4G(6, 2437, 0),
167 CHAN4G(7, 2442, 0),
168 CHAN4G(8, 2447, 0),
169 CHAN4G(9, 2452, 0),
170 CHAN4G(10, 2457, 0),
171 CHAN4G(11, 2462, 0),
172 CHAN4G(12, 2467, 0),
173 CHAN4G(13, 2472, 0),
174 CHAN4G(14, 2484, 0),
175 };
176 #undef CHAN4G
177
178 #define CHAN5G(_channel, _flags) { \
179 .band = IEEE80211_BAND_5GHZ, \
180 .center_freq = 5000 + (5 * (_channel)), \
181 .hw_value = (_channel), \
182 .flags = (_flags), \
183 .max_antenna_gain = 0, \
184 .max_power = 30, \
185 }
186 static struct ieee80211_channel b43_5ghz_nphy_chantable[] = {
187 CHAN5G(32, 0), CHAN5G(34, 0),
188 CHAN5G(36, 0), CHAN5G(38, 0),
189 CHAN5G(40, 0), CHAN5G(42, 0),
190 CHAN5G(44, 0), CHAN5G(46, 0),
191 CHAN5G(48, 0), CHAN5G(50, 0),
192 CHAN5G(52, 0), CHAN5G(54, 0),
193 CHAN5G(56, 0), CHAN5G(58, 0),
194 CHAN5G(60, 0), CHAN5G(62, 0),
195 CHAN5G(64, 0), CHAN5G(66, 0),
196 CHAN5G(68, 0), CHAN5G(70, 0),
197 CHAN5G(72, 0), CHAN5G(74, 0),
198 CHAN5G(76, 0), CHAN5G(78, 0),
199 CHAN5G(80, 0), CHAN5G(82, 0),
200 CHAN5G(84, 0), CHAN5G(86, 0),
201 CHAN5G(88, 0), CHAN5G(90, 0),
202 CHAN5G(92, 0), CHAN5G(94, 0),
203 CHAN5G(96, 0), CHAN5G(98, 0),
204 CHAN5G(100, 0), CHAN5G(102, 0),
205 CHAN5G(104, 0), CHAN5G(106, 0),
206 CHAN5G(108, 0), CHAN5G(110, 0),
207 CHAN5G(112, 0), CHAN5G(114, 0),
208 CHAN5G(116, 0), CHAN5G(118, 0),
209 CHAN5G(120, 0), CHAN5G(122, 0),
210 CHAN5G(124, 0), CHAN5G(126, 0),
211 CHAN5G(128, 0), CHAN5G(130, 0),
212 CHAN5G(132, 0), CHAN5G(134, 0),
213 CHAN5G(136, 0), CHAN5G(138, 0),
214 CHAN5G(140, 0), CHAN5G(142, 0),
215 CHAN5G(144, 0), CHAN5G(145, 0),
216 CHAN5G(146, 0), CHAN5G(147, 0),
217 CHAN5G(148, 0), CHAN5G(149, 0),
218 CHAN5G(150, 0), CHAN5G(151, 0),
219 CHAN5G(152, 0), CHAN5G(153, 0),
220 CHAN5G(154, 0), CHAN5G(155, 0),
221 CHAN5G(156, 0), CHAN5G(157, 0),
222 CHAN5G(158, 0), CHAN5G(159, 0),
223 CHAN5G(160, 0), CHAN5G(161, 0),
224 CHAN5G(162, 0), CHAN5G(163, 0),
225 CHAN5G(164, 0), CHAN5G(165, 0),
226 CHAN5G(166, 0), CHAN5G(168, 0),
227 CHAN5G(170, 0), CHAN5G(172, 0),
228 CHAN5G(174, 0), CHAN5G(176, 0),
229 CHAN5G(178, 0), CHAN5G(180, 0),
230 CHAN5G(182, 0), CHAN5G(184, 0),
231 CHAN5G(186, 0), CHAN5G(188, 0),
232 CHAN5G(190, 0), CHAN5G(192, 0),
233 CHAN5G(194, 0), CHAN5G(196, 0),
234 CHAN5G(198, 0), CHAN5G(200, 0),
235 CHAN5G(202, 0), CHAN5G(204, 0),
236 CHAN5G(206, 0), CHAN5G(208, 0),
237 CHAN5G(210, 0), CHAN5G(212, 0),
238 CHAN5G(214, 0), CHAN5G(216, 0),
239 CHAN5G(218, 0), CHAN5G(220, 0),
240 CHAN5G(222, 0), CHAN5G(224, 0),
241 CHAN5G(226, 0), CHAN5G(228, 0),
242 };
243
244 static struct ieee80211_channel b43_5ghz_aphy_chantable[] = {
245 CHAN5G(34, 0), CHAN5G(36, 0),
246 CHAN5G(38, 0), CHAN5G(40, 0),
247 CHAN5G(42, 0), CHAN5G(44, 0),
248 CHAN5G(46, 0), CHAN5G(48, 0),
249 CHAN5G(52, 0), CHAN5G(56, 0),
250 CHAN5G(60, 0), CHAN5G(64, 0),
251 CHAN5G(100, 0), CHAN5G(104, 0),
252 CHAN5G(108, 0), CHAN5G(112, 0),
253 CHAN5G(116, 0), CHAN5G(120, 0),
254 CHAN5G(124, 0), CHAN5G(128, 0),
255 CHAN5G(132, 0), CHAN5G(136, 0),
256 CHAN5G(140, 0), CHAN5G(149, 0),
257 CHAN5G(153, 0), CHAN5G(157, 0),
258 CHAN5G(161, 0), CHAN5G(165, 0),
259 CHAN5G(184, 0), CHAN5G(188, 0),
260 CHAN5G(192, 0), CHAN5G(196, 0),
261 CHAN5G(200, 0), CHAN5G(204, 0),
262 CHAN5G(208, 0), CHAN5G(212, 0),
263 CHAN5G(216, 0),
264 };
265 #undef CHAN5G
266
267 static struct ieee80211_supported_band b43_band_5GHz_nphy = {
268 .band = IEEE80211_BAND_5GHZ,
269 .channels = b43_5ghz_nphy_chantable,
270 .n_channels = ARRAY_SIZE(b43_5ghz_nphy_chantable),
271 .bitrates = b43_a_ratetable,
272 .n_bitrates = b43_a_ratetable_size,
273 };
274
275 static struct ieee80211_supported_band b43_band_5GHz_aphy = {
276 .band = IEEE80211_BAND_5GHZ,
277 .channels = b43_5ghz_aphy_chantable,
278 .n_channels = ARRAY_SIZE(b43_5ghz_aphy_chantable),
279 .bitrates = b43_a_ratetable,
280 .n_bitrates = b43_a_ratetable_size,
281 };
282
283 static struct ieee80211_supported_band b43_band_2GHz = {
284 .band = IEEE80211_BAND_2GHZ,
285 .channels = b43_2ghz_chantable,
286 .n_channels = ARRAY_SIZE(b43_2ghz_chantable),
287 .bitrates = b43_g_ratetable,
288 .n_bitrates = b43_g_ratetable_size,
289 };
290
291 static void b43_wireless_core_exit(struct b43_wldev *dev);
292 static int b43_wireless_core_init(struct b43_wldev *dev);
293 static void b43_wireless_core_stop(struct b43_wldev *dev);
294 static int b43_wireless_core_start(struct b43_wldev *dev);
295
296 static int b43_ratelimit(struct b43_wl *wl)
297 {
298 if (!wl || !wl->current_dev)
299 return 1;
300 if (b43_status(wl->current_dev) < B43_STAT_STARTED)
301 return 1;
302 /* We are up and running.
303 * Ratelimit the messages to avoid DoS over the net. */
304 return net_ratelimit();
305 }
306
307 void b43info(struct b43_wl *wl, const char *fmt, ...)
308 {
309 va_list args;
310
311 if (b43_modparam_verbose < B43_VERBOSITY_INFO)
312 return;
313 if (!b43_ratelimit(wl))
314 return;
315 va_start(args, fmt);
316 printk(KERN_INFO "b43-%s: ",
317 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
318 vprintk(fmt, args);
319 va_end(args);
320 }
321
322 void b43err(struct b43_wl *wl, const char *fmt, ...)
323 {
324 va_list args;
325
326 if (b43_modparam_verbose < B43_VERBOSITY_ERROR)
327 return;
328 if (!b43_ratelimit(wl))
329 return;
330 va_start(args, fmt);
331 printk(KERN_ERR "b43-%s ERROR: ",
332 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
333 vprintk(fmt, args);
334 va_end(args);
335 }
336
337 void b43warn(struct b43_wl *wl, const char *fmt, ...)
338 {
339 va_list args;
340
341 if (b43_modparam_verbose < B43_VERBOSITY_WARN)
342 return;
343 if (!b43_ratelimit(wl))
344 return;
345 va_start(args, fmt);
346 printk(KERN_WARNING "b43-%s warning: ",
347 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
348 vprintk(fmt, args);
349 va_end(args);
350 }
351
352 void b43dbg(struct b43_wl *wl, const char *fmt, ...)
353 {
354 va_list args;
355
356 if (b43_modparam_verbose < B43_VERBOSITY_DEBUG)
357 return;
358 va_start(args, fmt);
359 printk(KERN_DEBUG "b43-%s debug: ",
360 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
361 vprintk(fmt, args);
362 va_end(args);
363 }
364
365 static void b43_ram_write(struct b43_wldev *dev, u16 offset, u32 val)
366 {
367 u32 macctl;
368
369 B43_WARN_ON(offset % 4 != 0);
370
371 macctl = b43_read32(dev, B43_MMIO_MACCTL);
372 if (macctl & B43_MACCTL_BE)
373 val = swab32(val);
374
375 b43_write32(dev, B43_MMIO_RAM_CONTROL, offset);
376 mmiowb();
377 b43_write32(dev, B43_MMIO_RAM_DATA, val);
378 }
379
380 static inline void b43_shm_control_word(struct b43_wldev *dev,
381 u16 routing, u16 offset)
382 {
383 u32 control;
384
385 /* "offset" is the WORD offset. */
386 control = routing;
387 control <<= 16;
388 control |= offset;
389 b43_write32(dev, B43_MMIO_SHM_CONTROL, control);
390 }
391
392 u32 __b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
393 {
394 u32 ret;
395
396 if (routing == B43_SHM_SHARED) {
397 B43_WARN_ON(offset & 0x0001);
398 if (offset & 0x0003) {
399 /* Unaligned access */
400 b43_shm_control_word(dev, routing, offset >> 2);
401 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
402 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
403 ret |= ((u32)b43_read16(dev, B43_MMIO_SHM_DATA)) << 16;
404
405 goto out;
406 }
407 offset >>= 2;
408 }
409 b43_shm_control_word(dev, routing, offset);
410 ret = b43_read32(dev, B43_MMIO_SHM_DATA);
411 out:
412 return ret;
413 }
414
415 u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
416 {
417 struct b43_wl *wl = dev->wl;
418 unsigned long flags;
419 u32 ret;
420
421 spin_lock_irqsave(&wl->shm_lock, flags);
422 ret = __b43_shm_read32(dev, routing, offset);
423 spin_unlock_irqrestore(&wl->shm_lock, flags);
424
425 return ret;
426 }
427
428 u16 __b43_shm_read16(struct b43_wldev *dev, u16 routing, u16 offset)
429 {
430 u16 ret;
431
432 if (routing == B43_SHM_SHARED) {
433 B43_WARN_ON(offset & 0x0001);
434 if (offset & 0x0003) {
435 /* Unaligned access */
436 b43_shm_control_word(dev, routing, offset >> 2);
437 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
438
439 goto out;
440 }
441 offset >>= 2;
442 }
443 b43_shm_control_word(dev, routing, offset);
444 ret = b43_read16(dev, B43_MMIO_SHM_DATA);
445 out:
446 return ret;
447 }
448
449 u16 b43_shm_read16(struct b43_wldev *dev, u16 routing, u16 offset)
450 {
451 struct b43_wl *wl = dev->wl;
452 unsigned long flags;
453 u16 ret;
454
455 spin_lock_irqsave(&wl->shm_lock, flags);
456 ret = __b43_shm_read16(dev, routing, offset);
457 spin_unlock_irqrestore(&wl->shm_lock, flags);
458
459 return ret;
460 }
461
462 void __b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
463 {
464 if (routing == B43_SHM_SHARED) {
465 B43_WARN_ON(offset & 0x0001);
466 if (offset & 0x0003) {
467 /* Unaligned access */
468 b43_shm_control_word(dev, routing, offset >> 2);
469 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED,
470 value & 0xFFFF);
471 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
472 b43_write16(dev, B43_MMIO_SHM_DATA,
473 (value >> 16) & 0xFFFF);
474 return;
475 }
476 offset >>= 2;
477 }
478 b43_shm_control_word(dev, routing, offset);
479 b43_write32(dev, B43_MMIO_SHM_DATA, value);
480 }
481
482 void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
483 {
484 struct b43_wl *wl = dev->wl;
485 unsigned long flags;
486
487 spin_lock_irqsave(&wl->shm_lock, flags);
488 __b43_shm_write32(dev, routing, offset, value);
489 spin_unlock_irqrestore(&wl->shm_lock, flags);
490 }
491
492 void __b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
493 {
494 if (routing == B43_SHM_SHARED) {
495 B43_WARN_ON(offset & 0x0001);
496 if (offset & 0x0003) {
497 /* Unaligned access */
498 b43_shm_control_word(dev, routing, offset >> 2);
499 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, value);
500 return;
501 }
502 offset >>= 2;
503 }
504 b43_shm_control_word(dev, routing, offset);
505 b43_write16(dev, B43_MMIO_SHM_DATA, value);
506 }
507
508 void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
509 {
510 struct b43_wl *wl = dev->wl;
511 unsigned long flags;
512
513 spin_lock_irqsave(&wl->shm_lock, flags);
514 __b43_shm_write16(dev, routing, offset, value);
515 spin_unlock_irqrestore(&wl->shm_lock, flags);
516 }
517
518 /* Read HostFlags */
519 u64 b43_hf_read(struct b43_wldev *dev)
520 {
521 u64 ret;
522
523 ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI);
524 ret <<= 16;
525 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI);
526 ret <<= 16;
527 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO);
528
529 return ret;
530 }
531
532 /* Write HostFlags */
533 void b43_hf_write(struct b43_wldev *dev, u64 value)
534 {
535 u16 lo, mi, hi;
536
537 lo = (value & 0x00000000FFFFULL);
538 mi = (value & 0x0000FFFF0000ULL) >> 16;
539 hi = (value & 0xFFFF00000000ULL) >> 32;
540 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO, lo);
541 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI, mi);
542 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI, hi);
543 }
544
545 /* Read the firmware capabilities bitmask (Opensource firmware only) */
546 static u16 b43_fwcapa_read(struct b43_wldev *dev)
547 {
548 B43_WARN_ON(!dev->fw.opensource);
549 return b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_FWCAPA);
550 }
551
552 void b43_tsf_read(struct b43_wldev *dev, u64 *tsf)
553 {
554 u32 low, high;
555
556 B43_WARN_ON(dev->dev->id.revision < 3);
557
558 /* The hardware guarantees us an atomic read, if we
559 * read the low register first. */
560 low = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_LOW);
561 high = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
562
563 *tsf = high;
564 *tsf <<= 32;
565 *tsf |= low;
566 }
567
568 static void b43_time_lock(struct b43_wldev *dev)
569 {
570 u32 macctl;
571
572 macctl = b43_read32(dev, B43_MMIO_MACCTL);
573 macctl |= B43_MACCTL_TBTTHOLD;
574 b43_write32(dev, B43_MMIO_MACCTL, macctl);
575 /* Commit the write */
576 b43_read32(dev, B43_MMIO_MACCTL);
577 }
578
579 static void b43_time_unlock(struct b43_wldev *dev)
580 {
581 u32 macctl;
582
583 macctl = b43_read32(dev, B43_MMIO_MACCTL);
584 macctl &= ~B43_MACCTL_TBTTHOLD;
585 b43_write32(dev, B43_MMIO_MACCTL, macctl);
586 /* Commit the write */
587 b43_read32(dev, B43_MMIO_MACCTL);
588 }
589
590 static void b43_tsf_write_locked(struct b43_wldev *dev, u64 tsf)
591 {
592 u32 low, high;
593
594 B43_WARN_ON(dev->dev->id.revision < 3);
595
596 low = tsf;
597 high = (tsf >> 32);
598 /* The hardware guarantees us an atomic write, if we
599 * write the low register first. */
600 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, low);
601 mmiowb();
602 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_HIGH, high);
603 mmiowb();
604 }
605
606 void b43_tsf_write(struct b43_wldev *dev, u64 tsf)
607 {
608 b43_time_lock(dev);
609 b43_tsf_write_locked(dev, tsf);
610 b43_time_unlock(dev);
611 }
612
613 static
614 void b43_macfilter_set(struct b43_wldev *dev, u16 offset, const u8 *mac)
615 {
616 static const u8 zero_addr[ETH_ALEN] = { 0 };
617 u16 data;
618
619 if (!mac)
620 mac = zero_addr;
621
622 offset |= 0x0020;
623 b43_write16(dev, B43_MMIO_MACFILTER_CONTROL, offset);
624
625 data = mac[0];
626 data |= mac[1] << 8;
627 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
628 data = mac[2];
629 data |= mac[3] << 8;
630 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
631 data = mac[4];
632 data |= mac[5] << 8;
633 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
634 }
635
636 static void b43_write_mac_bssid_templates(struct b43_wldev *dev)
637 {
638 const u8 *mac;
639 const u8 *bssid;
640 u8 mac_bssid[ETH_ALEN * 2];
641 int i;
642 u32 tmp;
643
644 bssid = dev->wl->bssid;
645 mac = dev->wl->mac_addr;
646
647 b43_macfilter_set(dev, B43_MACFILTER_BSSID, bssid);
648
649 memcpy(mac_bssid, mac, ETH_ALEN);
650 memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
651
652 /* Write our MAC address and BSSID to template ram */
653 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
654 tmp = (u32) (mac_bssid[i + 0]);
655 tmp |= (u32) (mac_bssid[i + 1]) << 8;
656 tmp |= (u32) (mac_bssid[i + 2]) << 16;
657 tmp |= (u32) (mac_bssid[i + 3]) << 24;
658 b43_ram_write(dev, 0x20 + i, tmp);
659 }
660 }
661
662 static void b43_upload_card_macaddress(struct b43_wldev *dev)
663 {
664 b43_write_mac_bssid_templates(dev);
665 b43_macfilter_set(dev, B43_MACFILTER_SELF, dev->wl->mac_addr);
666 }
667
668 static void b43_set_slot_time(struct b43_wldev *dev, u16 slot_time)
669 {
670 /* slot_time is in usec. */
671 if (dev->phy.type != B43_PHYTYPE_G)
672 return;
673 b43_write16(dev, 0x684, 510 + slot_time);
674 b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time);
675 }
676
677 static void b43_short_slot_timing_enable(struct b43_wldev *dev)
678 {
679 b43_set_slot_time(dev, 9);
680 }
681
682 static void b43_short_slot_timing_disable(struct b43_wldev *dev)
683 {
684 b43_set_slot_time(dev, 20);
685 }
686
687 /* Synchronize IRQ top- and bottom-half.
688 * IRQs must be masked before calling this.
689 * This must not be called with the irq_lock held.
690 */
691 static void b43_synchronize_irq(struct b43_wldev *dev)
692 {
693 synchronize_irq(dev->dev->irq);
694 tasklet_kill(&dev->isr_tasklet);
695 }
696
697 /* DummyTransmission function, as documented on
698 * http://bcm-v4.sipsolutions.net/802.11/DummyTransmission
699 */
700 void b43_dummy_transmission(struct b43_wldev *dev, bool ofdm, bool pa_on)
701 {
702 struct b43_wl *wl = dev->wl;
703 struct b43_phy *phy = &dev->phy;
704 unsigned int i, max_loop;
705 u16 value;
706 u32 buffer[5] = {
707 0x00000000,
708 0x00D40000,
709 0x00000000,
710 0x01000000,
711 0x00000000,
712 };
713
714 if (ofdm) {
715 max_loop = 0x1E;
716 buffer[0] = 0x000201CC;
717 } else {
718 max_loop = 0xFA;
719 buffer[0] = 0x000B846E;
720 }
721
722 spin_lock_irq(&wl->irq_lock);
723 write_lock(&wl->tx_lock);
724
725 for (i = 0; i < 5; i++)
726 b43_ram_write(dev, i * 4, buffer[i]);
727
728 b43_write16(dev, 0x0568, 0x0000);
729 if (dev->dev->id.revision < 11)
730 b43_write16(dev, 0x07C0, 0x0000);
731 else
732 b43_write16(dev, 0x07C0, 0x0100);
733 value = (ofdm ? 0x41 : 0x40);
734 b43_write16(dev, 0x050C, value);
735 if ((phy->type == B43_PHYTYPE_N) || (phy->type == B43_PHYTYPE_LP))
736 b43_write16(dev, 0x0514, 0x1A02);
737 b43_write16(dev, 0x0508, 0x0000);
738 b43_write16(dev, 0x050A, 0x0000);
739 b43_write16(dev, 0x054C, 0x0000);
740 b43_write16(dev, 0x056A, 0x0014);
741 b43_write16(dev, 0x0568, 0x0826);
742 b43_write16(dev, 0x0500, 0x0000);
743 if (!pa_on && (phy->type == B43_PHYTYPE_N)) {
744 //SPEC TODO
745 }
746
747 switch (phy->type) {
748 case B43_PHYTYPE_N:
749 b43_write16(dev, 0x0502, 0x00D0);
750 break;
751 case B43_PHYTYPE_LP:
752 b43_write16(dev, 0x0502, 0x0050);
753 break;
754 default:
755 b43_write16(dev, 0x0502, 0x0030);
756 }
757
758 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
759 b43_radio_write16(dev, 0x0051, 0x0017);
760 for (i = 0x00; i < max_loop; i++) {
761 value = b43_read16(dev, 0x050E);
762 if (value & 0x0080)
763 break;
764 udelay(10);
765 }
766 for (i = 0x00; i < 0x0A; i++) {
767 value = b43_read16(dev, 0x050E);
768 if (value & 0x0400)
769 break;
770 udelay(10);
771 }
772 for (i = 0x00; i < 0x19; i++) {
773 value = b43_read16(dev, 0x0690);
774 if (!(value & 0x0100))
775 break;
776 udelay(10);
777 }
778 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
779 b43_radio_write16(dev, 0x0051, 0x0037);
780
781 write_unlock(&wl->tx_lock);
782 spin_unlock_irq(&wl->irq_lock);
783 }
784
785 static void key_write(struct b43_wldev *dev,
786 u8 index, u8 algorithm, const u8 *key)
787 {
788 unsigned int i;
789 u32 offset;
790 u16 value;
791 u16 kidx;
792
793 /* Key index/algo block */
794 kidx = b43_kidx_to_fw(dev, index);
795 value = ((kidx << 4) | algorithm);
796 b43_shm_write16(dev, B43_SHM_SHARED,
797 B43_SHM_SH_KEYIDXBLOCK + (kidx * 2), value);
798
799 /* Write the key to the Key Table Pointer offset */
800 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
801 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
802 value = key[i];
803 value |= (u16) (key[i + 1]) << 8;
804 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, value);
805 }
806 }
807
808 static void keymac_write(struct b43_wldev *dev, u8 index, const u8 *addr)
809 {
810 u32 addrtmp[2] = { 0, 0, };
811 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
812
813 if (b43_new_kidx_api(dev))
814 pairwise_keys_start = B43_NR_GROUP_KEYS;
815
816 B43_WARN_ON(index < pairwise_keys_start);
817 /* We have four default TX keys and possibly four default RX keys.
818 * Physical mac 0 is mapped to physical key 4 or 8, depending
819 * on the firmware version.
820 * So we must adjust the index here.
821 */
822 index -= pairwise_keys_start;
823 B43_WARN_ON(index >= B43_NR_PAIRWISE_KEYS);
824
825 if (addr) {
826 addrtmp[0] = addr[0];
827 addrtmp[0] |= ((u32) (addr[1]) << 8);
828 addrtmp[0] |= ((u32) (addr[2]) << 16);
829 addrtmp[0] |= ((u32) (addr[3]) << 24);
830 addrtmp[1] = addr[4];
831 addrtmp[1] |= ((u32) (addr[5]) << 8);
832 }
833
834 /* Receive match transmitter address (RCMTA) mechanism */
835 b43_shm_write32(dev, B43_SHM_RCMTA,
836 (index * 2) + 0, addrtmp[0]);
837 b43_shm_write16(dev, B43_SHM_RCMTA,
838 (index * 2) + 1, addrtmp[1]);
839 }
840
841 /* The ucode will use phase1 key with TEK key to decrypt rx packets.
842 * When a packet is received, the iv32 is checked.
843 * - if it doesn't the packet is returned without modification (and software
844 * decryption can be done). That's what happen when iv16 wrap.
845 * - if it does, the rc4 key is computed, and decryption is tried.
846 * Either it will success and B43_RX_MAC_DEC is returned,
847 * either it fails and B43_RX_MAC_DEC|B43_RX_MAC_DECERR is returned
848 * and the packet is not usable (it got modified by the ucode).
849 * So in order to never have B43_RX_MAC_DECERR, we should provide
850 * a iv32 and phase1key that match. Because we drop packets in case of
851 * B43_RX_MAC_DECERR, if we have a correct iv32 but a wrong phase1key, all
852 * packets will be lost without higher layer knowing (ie no resync possible
853 * until next wrap).
854 *
855 * NOTE : this should support 50 key like RCMTA because
856 * (B43_SHM_SH_KEYIDXBLOCK - B43_SHM_SH_TKIPTSCTTAK)/14 = 50
857 */
858 static void rx_tkip_phase1_write(struct b43_wldev *dev, u8 index, u32 iv32,
859 u16 *phase1key)
860 {
861 unsigned int i;
862 u32 offset;
863 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
864
865 if (!modparam_hwtkip)
866 return;
867
868 if (b43_new_kidx_api(dev))
869 pairwise_keys_start = B43_NR_GROUP_KEYS;
870
871 B43_WARN_ON(index < pairwise_keys_start);
872 /* We have four default TX keys and possibly four default RX keys.
873 * Physical mac 0 is mapped to physical key 4 or 8, depending
874 * on the firmware version.
875 * So we must adjust the index here.
876 */
877 index -= pairwise_keys_start;
878 B43_WARN_ON(index >= B43_NR_PAIRWISE_KEYS);
879
880 if (b43_debug(dev, B43_DBG_KEYS)) {
881 b43dbg(dev->wl, "rx_tkip_phase1_write : idx 0x%x, iv32 0x%x\n",
882 index, iv32);
883 }
884 /* Write the key to the RX tkip shared mem */
885 offset = B43_SHM_SH_TKIPTSCTTAK + index * (10 + 4);
886 for (i = 0; i < 10; i += 2) {
887 b43_shm_write16(dev, B43_SHM_SHARED, offset + i,
888 phase1key ? phase1key[i / 2] : 0);
889 }
890 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, iv32);
891 b43_shm_write16(dev, B43_SHM_SHARED, offset + i + 2, iv32 >> 16);
892 }
893
894 static void b43_op_update_tkip_key(struct ieee80211_hw *hw,
895 struct ieee80211_key_conf *keyconf, const u8 *addr,
896 u32 iv32, u16 *phase1key)
897 {
898 struct b43_wl *wl = hw_to_b43_wl(hw);
899 struct b43_wldev *dev;
900 int index = keyconf->hw_key_idx;
901
902 if (B43_WARN_ON(!modparam_hwtkip))
903 return;
904
905 mutex_lock(&wl->mutex);
906
907 dev = wl->current_dev;
908 if (!dev || b43_status(dev) < B43_STAT_INITIALIZED)
909 goto out_unlock;
910
911 keymac_write(dev, index, NULL); /* First zero out mac to avoid race */
912
913 rx_tkip_phase1_write(dev, index, iv32, phase1key);
914 keymac_write(dev, index, addr);
915
916 out_unlock:
917 mutex_unlock(&wl->mutex);
918 }
919
920 static void do_key_write(struct b43_wldev *dev,
921 u8 index, u8 algorithm,
922 const u8 *key, size_t key_len, const u8 *mac_addr)
923 {
924 u8 buf[B43_SEC_KEYSIZE] = { 0, };
925 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
926
927 if (b43_new_kidx_api(dev))
928 pairwise_keys_start = B43_NR_GROUP_KEYS;
929
930 B43_WARN_ON(index >= ARRAY_SIZE(dev->key));
931 B43_WARN_ON(key_len > B43_SEC_KEYSIZE);
932
933 if (index >= pairwise_keys_start)
934 keymac_write(dev, index, NULL); /* First zero out mac. */
935 if (algorithm == B43_SEC_ALGO_TKIP) {
936 /*
937 * We should provide an initial iv32, phase1key pair.
938 * We could start with iv32=0 and compute the corresponding
939 * phase1key, but this means calling ieee80211_get_tkip_key
940 * with a fake skb (or export other tkip function).
941 * Because we are lazy we hope iv32 won't start with
942 * 0xffffffff and let's b43_op_update_tkip_key provide a
943 * correct pair.
944 */
945 rx_tkip_phase1_write(dev, index, 0xffffffff, (u16*)buf);
946 } else if (index >= pairwise_keys_start) /* clear it */
947 rx_tkip_phase1_write(dev, index, 0, NULL);
948 if (key)
949 memcpy(buf, key, key_len);
950 key_write(dev, index, algorithm, buf);
951 if (index >= pairwise_keys_start)
952 keymac_write(dev, index, mac_addr);
953
954 dev->key[index].algorithm = algorithm;
955 }
956
957 static int b43_key_write(struct b43_wldev *dev,
958 int index, u8 algorithm,
959 const u8 *key, size_t key_len,
960 const u8 *mac_addr,
961 struct ieee80211_key_conf *keyconf)
962 {
963 int i;
964 int pairwise_keys_start;
965
966 /* For ALG_TKIP the key is encoded as a 256-bit (32 byte) data block:
967 * - Temporal Encryption Key (128 bits)
968 * - Temporal Authenticator Tx MIC Key (64 bits)
969 * - Temporal Authenticator Rx MIC Key (64 bits)
970 *
971 * Hardware only store TEK
972 */
973 if (algorithm == B43_SEC_ALGO_TKIP && key_len == 32)
974 key_len = 16;
975 if (key_len > B43_SEC_KEYSIZE)
976 return -EINVAL;
977 for (i = 0; i < ARRAY_SIZE(dev->key); i++) {
978 /* Check that we don't already have this key. */
979 B43_WARN_ON(dev->key[i].keyconf == keyconf);
980 }
981 if (index < 0) {
982 /* Pairwise key. Get an empty slot for the key. */
983 if (b43_new_kidx_api(dev))
984 pairwise_keys_start = B43_NR_GROUP_KEYS;
985 else
986 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
987 for (i = pairwise_keys_start;
988 i < pairwise_keys_start + B43_NR_PAIRWISE_KEYS;
989 i++) {
990 B43_WARN_ON(i >= ARRAY_SIZE(dev->key));
991 if (!dev->key[i].keyconf) {
992 /* found empty */
993 index = i;
994 break;
995 }
996 }
997 if (index < 0) {
998 b43warn(dev->wl, "Out of hardware key memory\n");
999 return -ENOSPC;
1000 }
1001 } else
1002 B43_WARN_ON(index > 3);
1003
1004 do_key_write(dev, index, algorithm, key, key_len, mac_addr);
1005 if ((index <= 3) && !b43_new_kidx_api(dev)) {
1006 /* Default RX key */
1007 B43_WARN_ON(mac_addr);
1008 do_key_write(dev, index + 4, algorithm, key, key_len, NULL);
1009 }
1010 keyconf->hw_key_idx = index;
1011 dev->key[index].keyconf = keyconf;
1012
1013 return 0;
1014 }
1015
1016 static int b43_key_clear(struct b43_wldev *dev, int index)
1017 {
1018 if (B43_WARN_ON((index < 0) || (index >= ARRAY_SIZE(dev->key))))
1019 return -EINVAL;
1020 do_key_write(dev, index, B43_SEC_ALGO_NONE,
1021 NULL, B43_SEC_KEYSIZE, NULL);
1022 if ((index <= 3) && !b43_new_kidx_api(dev)) {
1023 do_key_write(dev, index + 4, B43_SEC_ALGO_NONE,
1024 NULL, B43_SEC_KEYSIZE, NULL);
1025 }
1026 dev->key[index].keyconf = NULL;
1027
1028 return 0;
1029 }
1030
1031 static void b43_clear_keys(struct b43_wldev *dev)
1032 {
1033 int i, count;
1034
1035 if (b43_new_kidx_api(dev))
1036 count = B43_NR_GROUP_KEYS + B43_NR_PAIRWISE_KEYS;
1037 else
1038 count = B43_NR_GROUP_KEYS * 2 + B43_NR_PAIRWISE_KEYS;
1039 for (i = 0; i < count; i++)
1040 b43_key_clear(dev, i);
1041 }
1042
1043 static void b43_dump_keymemory(struct b43_wldev *dev)
1044 {
1045 unsigned int i, index, count, offset, pairwise_keys_start;
1046 u8 mac[ETH_ALEN];
1047 u16 algo;
1048 u32 rcmta0;
1049 u16 rcmta1;
1050 u64 hf;
1051 struct b43_key *key;
1052
1053 if (!b43_debug(dev, B43_DBG_KEYS))
1054 return;
1055
1056 hf = b43_hf_read(dev);
1057 b43dbg(dev->wl, "Hardware key memory dump: USEDEFKEYS=%u\n",
1058 !!(hf & B43_HF_USEDEFKEYS));
1059 if (b43_new_kidx_api(dev)) {
1060 pairwise_keys_start = B43_NR_GROUP_KEYS;
1061 count = B43_NR_GROUP_KEYS + B43_NR_PAIRWISE_KEYS;
1062 } else {
1063 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
1064 count = B43_NR_GROUP_KEYS * 2 + B43_NR_PAIRWISE_KEYS;
1065 }
1066 for (index = 0; index < count; index++) {
1067 key = &(dev->key[index]);
1068 printk(KERN_DEBUG "Key slot %02u: %s",
1069 index, (key->keyconf == NULL) ? " " : "*");
1070 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
1071 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
1072 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, offset + i);
1073 printk("%02X%02X", (tmp & 0xFF), ((tmp >> 8) & 0xFF));
1074 }
1075
1076 algo = b43_shm_read16(dev, B43_SHM_SHARED,
1077 B43_SHM_SH_KEYIDXBLOCK + (index * 2));
1078 printk(" Algo: %04X/%02X", algo, key->algorithm);
1079
1080 if (index >= pairwise_keys_start) {
1081 if (key->algorithm == B43_SEC_ALGO_TKIP) {
1082 printk(" TKIP: ");
1083 offset = B43_SHM_SH_TKIPTSCTTAK + (index - 4) * (10 + 4);
1084 for (i = 0; i < 14; i += 2) {
1085 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, offset + i);
1086 printk("%02X%02X", (tmp & 0xFF), ((tmp >> 8) & 0xFF));
1087 }
1088 }
1089 rcmta0 = b43_shm_read32(dev, B43_SHM_RCMTA,
1090 ((index - pairwise_keys_start) * 2) + 0);
1091 rcmta1 = b43_shm_read16(dev, B43_SHM_RCMTA,
1092 ((index - pairwise_keys_start) * 2) + 1);
1093 *((__le32 *)(&mac[0])) = cpu_to_le32(rcmta0);
1094 *((__le16 *)(&mac[4])) = cpu_to_le16(rcmta1);
1095 printk(" MAC: %pM", mac);
1096 } else
1097 printk(" DEFAULT KEY");
1098 printk("\n");
1099 }
1100 }
1101
1102 void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags)
1103 {
1104 u32 macctl;
1105 u16 ucstat;
1106 bool hwps;
1107 bool awake;
1108 int i;
1109
1110 B43_WARN_ON((ps_flags & B43_PS_ENABLED) &&
1111 (ps_flags & B43_PS_DISABLED));
1112 B43_WARN_ON((ps_flags & B43_PS_AWAKE) && (ps_flags & B43_PS_ASLEEP));
1113
1114 if (ps_flags & B43_PS_ENABLED) {
1115 hwps = 1;
1116 } else if (ps_flags & B43_PS_DISABLED) {
1117 hwps = 0;
1118 } else {
1119 //TODO: If powersave is not off and FIXME is not set and we are not in adhoc
1120 // and thus is not an AP and we are associated, set bit 25
1121 }
1122 if (ps_flags & B43_PS_AWAKE) {
1123 awake = 1;
1124 } else if (ps_flags & B43_PS_ASLEEP) {
1125 awake = 0;
1126 } else {
1127 //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME,
1128 // or we are associated, or FIXME, or the latest PS-Poll packet sent was
1129 // successful, set bit26
1130 }
1131
1132 /* FIXME: For now we force awake-on and hwps-off */
1133 hwps = 0;
1134 awake = 1;
1135
1136 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1137 if (hwps)
1138 macctl |= B43_MACCTL_HWPS;
1139 else
1140 macctl &= ~B43_MACCTL_HWPS;
1141 if (awake)
1142 macctl |= B43_MACCTL_AWAKE;
1143 else
1144 macctl &= ~B43_MACCTL_AWAKE;
1145 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1146 /* Commit write */
1147 b43_read32(dev, B43_MMIO_MACCTL);
1148 if (awake && dev->dev->id.revision >= 5) {
1149 /* Wait for the microcode to wake up. */
1150 for (i = 0; i < 100; i++) {
1151 ucstat = b43_shm_read16(dev, B43_SHM_SHARED,
1152 B43_SHM_SH_UCODESTAT);
1153 if (ucstat != B43_SHM_SH_UCODESTAT_SLEEP)
1154 break;
1155 udelay(10);
1156 }
1157 }
1158 }
1159
1160 void b43_wireless_core_reset(struct b43_wldev *dev, u32 flags)
1161 {
1162 u32 tmslow;
1163 u32 macctl;
1164
1165 flags |= B43_TMSLOW_PHYCLKEN;
1166 flags |= B43_TMSLOW_PHYRESET;
1167 ssb_device_enable(dev->dev, flags);
1168 msleep(2); /* Wait for the PLL to turn on. */
1169
1170 /* Now take the PHY out of Reset again */
1171 tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
1172 tmslow |= SSB_TMSLOW_FGC;
1173 tmslow &= ~B43_TMSLOW_PHYRESET;
1174 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
1175 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
1176 msleep(1);
1177 tmslow &= ~SSB_TMSLOW_FGC;
1178 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
1179 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
1180 msleep(1);
1181
1182 /* Turn Analog ON, but only if we already know the PHY-type.
1183 * This protects against very early setup where we don't know the
1184 * PHY-type, yet. wireless_core_reset will be called once again later,
1185 * when we know the PHY-type. */
1186 if (dev->phy.ops)
1187 dev->phy.ops->switch_analog(dev, 1);
1188
1189 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1190 macctl &= ~B43_MACCTL_GMODE;
1191 if (flags & B43_TMSLOW_GMODE)
1192 macctl |= B43_MACCTL_GMODE;
1193 macctl |= B43_MACCTL_IHR_ENABLED;
1194 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1195 }
1196
1197 static void handle_irq_transmit_status(struct b43_wldev *dev)
1198 {
1199 u32 v0, v1;
1200 u16 tmp;
1201 struct b43_txstatus stat;
1202
1203 while (1) {
1204 v0 = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1205 if (!(v0 & 0x00000001))
1206 break;
1207 v1 = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1208
1209 stat.cookie = (v0 >> 16);
1210 stat.seq = (v1 & 0x0000FFFF);
1211 stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
1212 tmp = (v0 & 0x0000FFFF);
1213 stat.frame_count = ((tmp & 0xF000) >> 12);
1214 stat.rts_count = ((tmp & 0x0F00) >> 8);
1215 stat.supp_reason = ((tmp & 0x001C) >> 2);
1216 stat.pm_indicated = !!(tmp & 0x0080);
1217 stat.intermediate = !!(tmp & 0x0040);
1218 stat.for_ampdu = !!(tmp & 0x0020);
1219 stat.acked = !!(tmp & 0x0002);
1220
1221 b43_handle_txstatus(dev, &stat);
1222 }
1223 }
1224
1225 static void drain_txstatus_queue(struct b43_wldev *dev)
1226 {
1227 u32 dummy;
1228
1229 if (dev->dev->id.revision < 5)
1230 return;
1231 /* Read all entries from the microcode TXstatus FIFO
1232 * and throw them away.
1233 */
1234 while (1) {
1235 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1236 if (!(dummy & 0x00000001))
1237 break;
1238 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1239 }
1240 }
1241
1242 static u32 b43_jssi_read(struct b43_wldev *dev)
1243 {
1244 u32 val = 0;
1245
1246 val = b43_shm_read16(dev, B43_SHM_SHARED, 0x08A);
1247 val <<= 16;
1248 val |= b43_shm_read16(dev, B43_SHM_SHARED, 0x088);
1249
1250 return val;
1251 }
1252
1253 static void b43_jssi_write(struct b43_wldev *dev, u32 jssi)
1254 {
1255 b43_shm_write16(dev, B43_SHM_SHARED, 0x088, (jssi & 0x0000FFFF));
1256 b43_shm_write16(dev, B43_SHM_SHARED, 0x08A, (jssi & 0xFFFF0000) >> 16);
1257 }
1258
1259 static void b43_generate_noise_sample(struct b43_wldev *dev)
1260 {
1261 b43_jssi_write(dev, 0x7F7F7F7F);
1262 b43_write32(dev, B43_MMIO_MACCMD,
1263 b43_read32(dev, B43_MMIO_MACCMD) | B43_MACCMD_BGNOISE);
1264 }
1265
1266 static void b43_calculate_link_quality(struct b43_wldev *dev)
1267 {
1268 /* Top half of Link Quality calculation. */
1269
1270 if (dev->phy.type != B43_PHYTYPE_G)
1271 return;
1272 if (dev->noisecalc.calculation_running)
1273 return;
1274 dev->noisecalc.calculation_running = 1;
1275 dev->noisecalc.nr_samples = 0;
1276
1277 b43_generate_noise_sample(dev);
1278 }
1279
1280 static void handle_irq_noise(struct b43_wldev *dev)
1281 {
1282 struct b43_phy_g *phy = dev->phy.g;
1283 u16 tmp;
1284 u8 noise[4];
1285 u8 i, j;
1286 s32 average;
1287
1288 /* Bottom half of Link Quality calculation. */
1289
1290 if (dev->phy.type != B43_PHYTYPE_G)
1291 return;
1292
1293 /* Possible race condition: It might be possible that the user
1294 * changed to a different channel in the meantime since we
1295 * started the calculation. We ignore that fact, since it's
1296 * not really that much of a problem. The background noise is
1297 * an estimation only anyway. Slightly wrong results will get damped
1298 * by the averaging of the 8 sample rounds. Additionally the
1299 * value is shortlived. So it will be replaced by the next noise
1300 * calculation round soon. */
1301
1302 B43_WARN_ON(!dev->noisecalc.calculation_running);
1303 *((__le32 *)noise) = cpu_to_le32(b43_jssi_read(dev));
1304 if (noise[0] == 0x7F || noise[1] == 0x7F ||
1305 noise[2] == 0x7F || noise[3] == 0x7F)
1306 goto generate_new;
1307
1308 /* Get the noise samples. */
1309 B43_WARN_ON(dev->noisecalc.nr_samples >= 8);
1310 i = dev->noisecalc.nr_samples;
1311 noise[0] = clamp_val(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1312 noise[1] = clamp_val(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1313 noise[2] = clamp_val(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1314 noise[3] = clamp_val(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1315 dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
1316 dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
1317 dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
1318 dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
1319 dev->noisecalc.nr_samples++;
1320 if (dev->noisecalc.nr_samples == 8) {
1321 /* Calculate the Link Quality by the noise samples. */
1322 average = 0;
1323 for (i = 0; i < 8; i++) {
1324 for (j = 0; j < 4; j++)
1325 average += dev->noisecalc.samples[i][j];
1326 }
1327 average /= (8 * 4);
1328 average *= 125;
1329 average += 64;
1330 average /= 128;
1331 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x40C);
1332 tmp = (tmp / 128) & 0x1F;
1333 if (tmp >= 8)
1334 average += 2;
1335 else
1336 average -= 25;
1337 if (tmp == 8)
1338 average -= 72;
1339 else
1340 average -= 48;
1341
1342 dev->stats.link_noise = average;
1343 dev->noisecalc.calculation_running = 0;
1344 return;
1345 }
1346 generate_new:
1347 b43_generate_noise_sample(dev);
1348 }
1349
1350 static void handle_irq_tbtt_indication(struct b43_wldev *dev)
1351 {
1352 if (b43_is_mode(dev->wl, NL80211_IFTYPE_AP)) {
1353 ///TODO: PS TBTT
1354 } else {
1355 if (1 /*FIXME: the last PSpoll frame was sent successfully */ )
1356 b43_power_saving_ctl_bits(dev, 0);
1357 }
1358 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC))
1359 dev->dfq_valid = 1;
1360 }
1361
1362 static void handle_irq_atim_end(struct b43_wldev *dev)
1363 {
1364 if (dev->dfq_valid) {
1365 b43_write32(dev, B43_MMIO_MACCMD,
1366 b43_read32(dev, B43_MMIO_MACCMD)
1367 | B43_MACCMD_DFQ_VALID);
1368 dev->dfq_valid = 0;
1369 }
1370 }
1371
1372 static void handle_irq_pmq(struct b43_wldev *dev)
1373 {
1374 u32 tmp;
1375
1376 //TODO: AP mode.
1377
1378 while (1) {
1379 tmp = b43_read32(dev, B43_MMIO_PS_STATUS);
1380 if (!(tmp & 0x00000008))
1381 break;
1382 }
1383 /* 16bit write is odd, but correct. */
1384 b43_write16(dev, B43_MMIO_PS_STATUS, 0x0002);
1385 }
1386
1387 static void b43_write_template_common(struct b43_wldev *dev,
1388 const u8 *data, u16 size,
1389 u16 ram_offset,
1390 u16 shm_size_offset, u8 rate)
1391 {
1392 u32 i, tmp;
1393 struct b43_plcp_hdr4 plcp;
1394
1395 plcp.data = 0;
1396 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1397 b43_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
1398 ram_offset += sizeof(u32);
1399 /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
1400 * So leave the first two bytes of the next write blank.
1401 */
1402 tmp = (u32) (data[0]) << 16;
1403 tmp |= (u32) (data[1]) << 24;
1404 b43_ram_write(dev, ram_offset, tmp);
1405 ram_offset += sizeof(u32);
1406 for (i = 2; i < size; i += sizeof(u32)) {
1407 tmp = (u32) (data[i + 0]);
1408 if (i + 1 < size)
1409 tmp |= (u32) (data[i + 1]) << 8;
1410 if (i + 2 < size)
1411 tmp |= (u32) (data[i + 2]) << 16;
1412 if (i + 3 < size)
1413 tmp |= (u32) (data[i + 3]) << 24;
1414 b43_ram_write(dev, ram_offset + i - 2, tmp);
1415 }
1416 b43_shm_write16(dev, B43_SHM_SHARED, shm_size_offset,
1417 size + sizeof(struct b43_plcp_hdr6));
1418 }
1419
1420 /* Check if the use of the antenna that ieee80211 told us to
1421 * use is possible. This will fall back to DEFAULT.
1422 * "antenna_nr" is the antenna identifier we got from ieee80211. */
1423 u8 b43_ieee80211_antenna_sanitize(struct b43_wldev *dev,
1424 u8 antenna_nr)
1425 {
1426 u8 antenna_mask;
1427
1428 if (antenna_nr == 0) {
1429 /* Zero means "use default antenna". That's always OK. */
1430 return 0;
1431 }
1432
1433 /* Get the mask of available antennas. */
1434 if (dev->phy.gmode)
1435 antenna_mask = dev->dev->bus->sprom.ant_available_bg;
1436 else
1437 antenna_mask = dev->dev->bus->sprom.ant_available_a;
1438
1439 if (!(antenna_mask & (1 << (antenna_nr - 1)))) {
1440 /* This antenna is not available. Fall back to default. */
1441 return 0;
1442 }
1443
1444 return antenna_nr;
1445 }
1446
1447 /* Convert a b43 antenna number value to the PHY TX control value. */
1448 static u16 b43_antenna_to_phyctl(int antenna)
1449 {
1450 switch (antenna) {
1451 case B43_ANTENNA0:
1452 return B43_TXH_PHY_ANT0;
1453 case B43_ANTENNA1:
1454 return B43_TXH_PHY_ANT1;
1455 case B43_ANTENNA2:
1456 return B43_TXH_PHY_ANT2;
1457 case B43_ANTENNA3:
1458 return B43_TXH_PHY_ANT3;
1459 case B43_ANTENNA_AUTO0:
1460 case B43_ANTENNA_AUTO1:
1461 return B43_TXH_PHY_ANT01AUTO;
1462 }
1463 B43_WARN_ON(1);
1464 return 0;
1465 }
1466
1467 static void b43_write_beacon_template(struct b43_wldev *dev,
1468 u16 ram_offset,
1469 u16 shm_size_offset)
1470 {
1471 unsigned int i, len, variable_len;
1472 const struct ieee80211_mgmt *bcn;
1473 const u8 *ie;
1474 bool tim_found = 0;
1475 unsigned int rate;
1476 u16 ctl;
1477 int antenna;
1478 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(dev->wl->current_beacon);
1479
1480 bcn = (const struct ieee80211_mgmt *)(dev->wl->current_beacon->data);
1481 len = min((size_t) dev->wl->current_beacon->len,
1482 0x200 - sizeof(struct b43_plcp_hdr6));
1483 rate = ieee80211_get_tx_rate(dev->wl->hw, info)->hw_value;
1484
1485 b43_write_template_common(dev, (const u8 *)bcn,
1486 len, ram_offset, shm_size_offset, rate);
1487
1488 /* Write the PHY TX control parameters. */
1489 antenna = B43_ANTENNA_DEFAULT;
1490 antenna = b43_antenna_to_phyctl(antenna);
1491 ctl = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL);
1492 /* We can't send beacons with short preamble. Would get PHY errors. */
1493 ctl &= ~B43_TXH_PHY_SHORTPRMBL;
1494 ctl &= ~B43_TXH_PHY_ANT;
1495 ctl &= ~B43_TXH_PHY_ENC;
1496 ctl |= antenna;
1497 if (b43_is_cck_rate(rate))
1498 ctl |= B43_TXH_PHY_ENC_CCK;
1499 else
1500 ctl |= B43_TXH_PHY_ENC_OFDM;
1501 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
1502
1503 /* Find the position of the TIM and the DTIM_period value
1504 * and write them to SHM. */
1505 ie = bcn->u.beacon.variable;
1506 variable_len = len - offsetof(struct ieee80211_mgmt, u.beacon.variable);
1507 for (i = 0; i < variable_len - 2; ) {
1508 uint8_t ie_id, ie_len;
1509
1510 ie_id = ie[i];
1511 ie_len = ie[i + 1];
1512 if (ie_id == 5) {
1513 u16 tim_position;
1514 u16 dtim_period;
1515 /* This is the TIM Information Element */
1516
1517 /* Check whether the ie_len is in the beacon data range. */
1518 if (variable_len < ie_len + 2 + i)
1519 break;
1520 /* A valid TIM is at least 4 bytes long. */
1521 if (ie_len < 4)
1522 break;
1523 tim_found = 1;
1524
1525 tim_position = sizeof(struct b43_plcp_hdr6);
1526 tim_position += offsetof(struct ieee80211_mgmt, u.beacon.variable);
1527 tim_position += i;
1528
1529 dtim_period = ie[i + 3];
1530
1531 b43_shm_write16(dev, B43_SHM_SHARED,
1532 B43_SHM_SH_TIMBPOS, tim_position);
1533 b43_shm_write16(dev, B43_SHM_SHARED,
1534 B43_SHM_SH_DTIMPER, dtim_period);
1535 break;
1536 }
1537 i += ie_len + 2;
1538 }
1539 if (!tim_found) {
1540 /*
1541 * If ucode wants to modify TIM do it behind the beacon, this
1542 * will happen, for example, when doing mesh networking.
1543 */
1544 b43_shm_write16(dev, B43_SHM_SHARED,
1545 B43_SHM_SH_TIMBPOS,
1546 len + sizeof(struct b43_plcp_hdr6));
1547 b43_shm_write16(dev, B43_SHM_SHARED,
1548 B43_SHM_SH_DTIMPER, 0);
1549 }
1550 b43dbg(dev->wl, "Updated beacon template at 0x%x\n", ram_offset);
1551 }
1552
1553 static void b43_upload_beacon0(struct b43_wldev *dev)
1554 {
1555 struct b43_wl *wl = dev->wl;
1556
1557 if (wl->beacon0_uploaded)
1558 return;
1559 b43_write_beacon_template(dev, 0x68, 0x18);
1560 wl->beacon0_uploaded = 1;
1561 }
1562
1563 static void b43_upload_beacon1(struct b43_wldev *dev)
1564 {
1565 struct b43_wl *wl = dev->wl;
1566
1567 if (wl->beacon1_uploaded)
1568 return;
1569 b43_write_beacon_template(dev, 0x468, 0x1A);
1570 wl->beacon1_uploaded = 1;
1571 }
1572
1573 static void handle_irq_beacon(struct b43_wldev *dev)
1574 {
1575 struct b43_wl *wl = dev->wl;
1576 u32 cmd, beacon0_valid, beacon1_valid;
1577
1578 if (!b43_is_mode(wl, NL80211_IFTYPE_AP) &&
1579 !b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT))
1580 return;
1581
1582 /* This is the bottom half of the asynchronous beacon update. */
1583
1584 /* Ignore interrupt in the future. */
1585 dev->irq_mask &= ~B43_IRQ_BEACON;
1586
1587 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1588 beacon0_valid = (cmd & B43_MACCMD_BEACON0_VALID);
1589 beacon1_valid = (cmd & B43_MACCMD_BEACON1_VALID);
1590
1591 /* Schedule interrupt manually, if busy. */
1592 if (beacon0_valid && beacon1_valid) {
1593 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_BEACON);
1594 dev->irq_mask |= B43_IRQ_BEACON;
1595 return;
1596 }
1597
1598 if (unlikely(wl->beacon_templates_virgin)) {
1599 /* We never uploaded a beacon before.
1600 * Upload both templates now, but only mark one valid. */
1601 wl->beacon_templates_virgin = 0;
1602 b43_upload_beacon0(dev);
1603 b43_upload_beacon1(dev);
1604 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1605 cmd |= B43_MACCMD_BEACON0_VALID;
1606 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1607 } else {
1608 if (!beacon0_valid) {
1609 b43_upload_beacon0(dev);
1610 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1611 cmd |= B43_MACCMD_BEACON0_VALID;
1612 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1613 } else if (!beacon1_valid) {
1614 b43_upload_beacon1(dev);
1615 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1616 cmd |= B43_MACCMD_BEACON1_VALID;
1617 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1618 }
1619 }
1620 }
1621
1622 static void b43_beacon_update_trigger_work(struct work_struct *work)
1623 {
1624 struct b43_wl *wl = container_of(work, struct b43_wl,
1625 beacon_update_trigger);
1626 struct b43_wldev *dev;
1627
1628 mutex_lock(&wl->mutex);
1629 dev = wl->current_dev;
1630 if (likely(dev && (b43_status(dev) >= B43_STAT_INITIALIZED))) {
1631 spin_lock_irq(&wl->irq_lock);
1632 /* update beacon right away or defer to irq */
1633 handle_irq_beacon(dev);
1634 /* The handler might have updated the IRQ mask. */
1635 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
1636 mmiowb();
1637 spin_unlock_irq(&wl->irq_lock);
1638 }
1639 mutex_unlock(&wl->mutex);
1640 }
1641
1642 /* Asynchronously update the packet templates in template RAM.
1643 * Locking: Requires wl->irq_lock to be locked. */
1644 static void b43_update_templates(struct b43_wl *wl)
1645 {
1646 struct sk_buff *beacon;
1647
1648 /* This is the top half of the ansynchronous beacon update.
1649 * The bottom half is the beacon IRQ.
1650 * Beacon update must be asynchronous to avoid sending an
1651 * invalid beacon. This can happen for example, if the firmware
1652 * transmits a beacon while we are updating it. */
1653
1654 /* We could modify the existing beacon and set the aid bit in
1655 * the TIM field, but that would probably require resizing and
1656 * moving of data within the beacon template.
1657 * Simply request a new beacon and let mac80211 do the hard work. */
1658 beacon = ieee80211_beacon_get(wl->hw, wl->vif);
1659 if (unlikely(!beacon))
1660 return;
1661
1662 if (wl->current_beacon)
1663 dev_kfree_skb_any(wl->current_beacon);
1664 wl->current_beacon = beacon;
1665 wl->beacon0_uploaded = 0;
1666 wl->beacon1_uploaded = 0;
1667 ieee80211_queue_work(wl->hw, &wl->beacon_update_trigger);
1668 }
1669
1670 static void b43_set_beacon_int(struct b43_wldev *dev, u16 beacon_int)
1671 {
1672 b43_time_lock(dev);
1673 if (dev->dev->id.revision >= 3) {
1674 b43_write32(dev, B43_MMIO_TSF_CFP_REP, (beacon_int << 16));
1675 b43_write32(dev, B43_MMIO_TSF_CFP_START, (beacon_int << 10));
1676 } else {
1677 b43_write16(dev, 0x606, (beacon_int >> 6));
1678 b43_write16(dev, 0x610, beacon_int);
1679 }
1680 b43_time_unlock(dev);
1681 b43dbg(dev->wl, "Set beacon interval to %u\n", beacon_int);
1682 }
1683
1684 static void b43_handle_firmware_panic(struct b43_wldev *dev)
1685 {
1686 u16 reason;
1687
1688 /* Read the register that contains the reason code for the panic. */
1689 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_FWPANIC_REASON_REG);
1690 b43err(dev->wl, "Whoopsy, firmware panic! Reason: %u\n", reason);
1691
1692 switch (reason) {
1693 default:
1694 b43dbg(dev->wl, "The panic reason is unknown.\n");
1695 /* fallthrough */
1696 case B43_FWPANIC_DIE:
1697 /* Do not restart the controller or firmware.
1698 * The device is nonfunctional from now on.
1699 * Restarting would result in this panic to trigger again,
1700 * so we avoid that recursion. */
1701 break;
1702 case B43_FWPANIC_RESTART:
1703 b43_controller_restart(dev, "Microcode panic");
1704 break;
1705 }
1706 }
1707
1708 static void handle_irq_ucode_debug(struct b43_wldev *dev)
1709 {
1710 unsigned int i, cnt;
1711 u16 reason, marker_id, marker_line;
1712 __le16 *buf;
1713
1714 /* The proprietary firmware doesn't have this IRQ. */
1715 if (!dev->fw.opensource)
1716 return;
1717
1718 /* Read the register that contains the reason code for this IRQ. */
1719 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_DEBUGIRQ_REASON_REG);
1720
1721 switch (reason) {
1722 case B43_DEBUGIRQ_PANIC:
1723 b43_handle_firmware_panic(dev);
1724 break;
1725 case B43_DEBUGIRQ_DUMP_SHM:
1726 if (!B43_DEBUG)
1727 break; /* Only with driver debugging enabled. */
1728 buf = kmalloc(4096, GFP_ATOMIC);
1729 if (!buf) {
1730 b43dbg(dev->wl, "SHM-dump: Failed to allocate memory\n");
1731 goto out;
1732 }
1733 for (i = 0; i < 4096; i += 2) {
1734 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, i);
1735 buf[i / 2] = cpu_to_le16(tmp);
1736 }
1737 b43info(dev->wl, "Shared memory dump:\n");
1738 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET,
1739 16, 2, buf, 4096, 1);
1740 kfree(buf);
1741 break;
1742 case B43_DEBUGIRQ_DUMP_REGS:
1743 if (!B43_DEBUG)
1744 break; /* Only with driver debugging enabled. */
1745 b43info(dev->wl, "Microcode register dump:\n");
1746 for (i = 0, cnt = 0; i < 64; i++) {
1747 u16 tmp = b43_shm_read16(dev, B43_SHM_SCRATCH, i);
1748 if (cnt == 0)
1749 printk(KERN_INFO);
1750 printk("r%02u: 0x%04X ", i, tmp);
1751 cnt++;
1752 if (cnt == 6) {
1753 printk("\n");
1754 cnt = 0;
1755 }
1756 }
1757 printk("\n");
1758 break;
1759 case B43_DEBUGIRQ_MARKER:
1760 if (!B43_DEBUG)
1761 break; /* Only with driver debugging enabled. */
1762 marker_id = b43_shm_read16(dev, B43_SHM_SCRATCH,
1763 B43_MARKER_ID_REG);
1764 marker_line = b43_shm_read16(dev, B43_SHM_SCRATCH,
1765 B43_MARKER_LINE_REG);
1766 b43info(dev->wl, "The firmware just executed the MARKER(%u) "
1767 "at line number %u\n",
1768 marker_id, marker_line);
1769 break;
1770 default:
1771 b43dbg(dev->wl, "Debug-IRQ triggered for unknown reason: %u\n",
1772 reason);
1773 }
1774 out:
1775 /* Acknowledge the debug-IRQ, so the firmware can continue. */
1776 b43_shm_write16(dev, B43_SHM_SCRATCH,
1777 B43_DEBUGIRQ_REASON_REG, B43_DEBUGIRQ_ACK);
1778 }
1779
1780 /* Interrupt handler bottom-half */
1781 static void b43_interrupt_tasklet(struct b43_wldev *dev)
1782 {
1783 u32 reason;
1784 u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
1785 u32 merged_dma_reason = 0;
1786 int i;
1787 unsigned long flags;
1788
1789 spin_lock_irqsave(&dev->wl->irq_lock, flags);
1790
1791 B43_WARN_ON(b43_status(dev) != B43_STAT_STARTED);
1792
1793 reason = dev->irq_reason;
1794 for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
1795 dma_reason[i] = dev->dma_reason[i];
1796 merged_dma_reason |= dma_reason[i];
1797 }
1798
1799 if (unlikely(reason & B43_IRQ_MAC_TXERR))
1800 b43err(dev->wl, "MAC transmission error\n");
1801
1802 if (unlikely(reason & B43_IRQ_PHY_TXERR)) {
1803 b43err(dev->wl, "PHY transmission error\n");
1804 rmb();
1805 if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) {
1806 atomic_set(&dev->phy.txerr_cnt,
1807 B43_PHY_TX_BADNESS_LIMIT);
1808 b43err(dev->wl, "Too many PHY TX errors, "
1809 "restarting the controller\n");
1810 b43_controller_restart(dev, "PHY TX errors");
1811 }
1812 }
1813
1814 if (unlikely(merged_dma_reason & (B43_DMAIRQ_FATALMASK |
1815 B43_DMAIRQ_NONFATALMASK))) {
1816 if (merged_dma_reason & B43_DMAIRQ_FATALMASK) {
1817 b43err(dev->wl, "Fatal DMA error: "
1818 "0x%08X, 0x%08X, 0x%08X, "
1819 "0x%08X, 0x%08X, 0x%08X\n",
1820 dma_reason[0], dma_reason[1],
1821 dma_reason[2], dma_reason[3],
1822 dma_reason[4], dma_reason[5]);
1823 b43_controller_restart(dev, "DMA error");
1824 mmiowb();
1825 spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1826 return;
1827 }
1828 if (merged_dma_reason & B43_DMAIRQ_NONFATALMASK) {
1829 b43err(dev->wl, "DMA error: "
1830 "0x%08X, 0x%08X, 0x%08X, "
1831 "0x%08X, 0x%08X, 0x%08X\n",
1832 dma_reason[0], dma_reason[1],
1833 dma_reason[2], dma_reason[3],
1834 dma_reason[4], dma_reason[5]);
1835 }
1836 }
1837
1838 if (unlikely(reason & B43_IRQ_UCODE_DEBUG))
1839 handle_irq_ucode_debug(dev);
1840 if (reason & B43_IRQ_TBTT_INDI)
1841 handle_irq_tbtt_indication(dev);
1842 if (reason & B43_IRQ_ATIM_END)
1843 handle_irq_atim_end(dev);
1844 if (reason & B43_IRQ_BEACON)
1845 handle_irq_beacon(dev);
1846 if (reason & B43_IRQ_PMQ)
1847 handle_irq_pmq(dev);
1848 if (reason & B43_IRQ_TXFIFO_FLUSH_OK)
1849 ;/* TODO */
1850 if (reason & B43_IRQ_NOISESAMPLE_OK)
1851 handle_irq_noise(dev);
1852
1853 /* Check the DMA reason registers for received data. */
1854 if (dma_reason[0] & B43_DMAIRQ_RX_DONE) {
1855 if (b43_using_pio_transfers(dev))
1856 b43_pio_rx(dev->pio.rx_queue);
1857 else
1858 b43_dma_rx(dev->dma.rx_ring);
1859 }
1860 B43_WARN_ON(dma_reason[1] & B43_DMAIRQ_RX_DONE);
1861 B43_WARN_ON(dma_reason[2] & B43_DMAIRQ_RX_DONE);
1862 B43_WARN_ON(dma_reason[3] & B43_DMAIRQ_RX_DONE);
1863 B43_WARN_ON(dma_reason[4] & B43_DMAIRQ_RX_DONE);
1864 B43_WARN_ON(dma_reason[5] & B43_DMAIRQ_RX_DONE);
1865
1866 if (reason & B43_IRQ_TX_OK)
1867 handle_irq_transmit_status(dev);
1868
1869 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
1870 mmiowb();
1871 spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1872 }
1873
1874 static void b43_interrupt_ack(struct b43_wldev *dev, u32 reason)
1875 {
1876 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, reason);
1877
1878 b43_write32(dev, B43_MMIO_DMA0_REASON, dev->dma_reason[0]);
1879 b43_write32(dev, B43_MMIO_DMA1_REASON, dev->dma_reason[1]);
1880 b43_write32(dev, B43_MMIO_DMA2_REASON, dev->dma_reason[2]);
1881 b43_write32(dev, B43_MMIO_DMA3_REASON, dev->dma_reason[3]);
1882 b43_write32(dev, B43_MMIO_DMA4_REASON, dev->dma_reason[4]);
1883 /* Unused ring
1884 b43_write32(dev, B43_MMIO_DMA5_REASON, dev->dma_reason[5]);
1885 */
1886 }
1887
1888 /* Interrupt handler top-half */
1889 static irqreturn_t b43_interrupt_handler(int irq, void *dev_id)
1890 {
1891 irqreturn_t ret = IRQ_NONE;
1892 struct b43_wldev *dev = dev_id;
1893 u32 reason;
1894
1895 B43_WARN_ON(!dev);
1896
1897 spin_lock(&dev->wl->irq_lock);
1898
1899 if (unlikely(b43_status(dev) < B43_STAT_STARTED)) {
1900 /* This can only happen on shared IRQ lines. */
1901 goto out;
1902 }
1903 reason = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1904 if (reason == 0xffffffff) /* shared IRQ */
1905 goto out;
1906 ret = IRQ_HANDLED;
1907 reason &= dev->irq_mask;
1908 if (!reason)
1909 goto out;
1910
1911 dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON)
1912 & 0x0001DC00;
1913 dev->dma_reason[1] = b43_read32(dev, B43_MMIO_DMA1_REASON)
1914 & 0x0000DC00;
1915 dev->dma_reason[2] = b43_read32(dev, B43_MMIO_DMA2_REASON)
1916 & 0x0000DC00;
1917 dev->dma_reason[3] = b43_read32(dev, B43_MMIO_DMA3_REASON)
1918 & 0x0001DC00;
1919 dev->dma_reason[4] = b43_read32(dev, B43_MMIO_DMA4_REASON)
1920 & 0x0000DC00;
1921 /* Unused ring
1922 dev->dma_reason[5] = b43_read32(dev, B43_MMIO_DMA5_REASON)
1923 & 0x0000DC00;
1924 */
1925
1926 b43_interrupt_ack(dev, reason);
1927 /* disable all IRQs. They are enabled again in the bottom half. */
1928 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
1929 /* save the reason code and call our bottom half. */
1930 dev->irq_reason = reason;
1931 tasklet_schedule(&dev->isr_tasklet);
1932 out:
1933 mmiowb();
1934 spin_unlock(&dev->wl->irq_lock);
1935
1936 return ret;
1937 }
1938
1939 void b43_do_release_fw(struct b43_firmware_file *fw)
1940 {
1941 release_firmware(fw->data);
1942 fw->data = NULL;
1943 fw->filename = NULL;
1944 }
1945
1946 static void b43_release_firmware(struct b43_wldev *dev)
1947 {
1948 b43_do_release_fw(&dev->fw.ucode);
1949 b43_do_release_fw(&dev->fw.pcm);
1950 b43_do_release_fw(&dev->fw.initvals);
1951 b43_do_release_fw(&dev->fw.initvals_band);
1952 }
1953
1954 static void b43_print_fw_helptext(struct b43_wl *wl, bool error)
1955 {
1956 const char text[] =
1957 "You must go to " \
1958 "http://wireless.kernel.org/en/users/Drivers/b43#devicefirmware " \
1959 "and download the correct firmware for this driver version. " \
1960 "Please carefully read all instructions on this website.\n";
1961
1962 if (error)
1963 b43err(wl, text);
1964 else
1965 b43warn(wl, text);
1966 }
1967
1968 int b43_do_request_fw(struct b43_request_fw_context *ctx,
1969 const char *name,
1970 struct b43_firmware_file *fw)
1971 {
1972 const struct firmware *blob;
1973 struct b43_fw_header *hdr;
1974 u32 size;
1975 int err;
1976
1977 if (!name) {
1978 /* Don't fetch anything. Free possibly cached firmware. */
1979 /* FIXME: We should probably keep it anyway, to save some headache
1980 * on suspend/resume with multiband devices. */
1981 b43_do_release_fw(fw);
1982 return 0;
1983 }
1984 if (fw->filename) {
1985 if ((fw->type == ctx->req_type) &&
1986 (strcmp(fw->filename, name) == 0))
1987 return 0; /* Already have this fw. */
1988 /* Free the cached firmware first. */
1989 /* FIXME: We should probably do this later after we successfully
1990 * got the new fw. This could reduce headache with multiband devices.
1991 * We could also redesign this to cache the firmware for all possible
1992 * bands all the time. */
1993 b43_do_release_fw(fw);
1994 }
1995
1996 switch (ctx->req_type) {
1997 case B43_FWTYPE_PROPRIETARY:
1998 snprintf(ctx->fwname, sizeof(ctx->fwname),
1999 "b43%s/%s.fw",
2000 modparam_fwpostfix, name);
2001 break;
2002 case B43_FWTYPE_OPENSOURCE:
2003 snprintf(ctx->fwname, sizeof(ctx->fwname),
2004 "b43-open%s/%s.fw",
2005 modparam_fwpostfix, name);
2006 break;
2007 default:
2008 B43_WARN_ON(1);
2009 return -ENOSYS;
2010 }
2011 err = request_firmware(&blob, ctx->fwname, ctx->dev->dev->dev);
2012 if (err == -ENOENT) {
2013 snprintf(ctx->errors[ctx->req_type],
2014 sizeof(ctx->errors[ctx->req_type]),
2015 "Firmware file \"%s\" not found\n", ctx->fwname);
2016 return err;
2017 } else if (err) {
2018 snprintf(ctx->errors[ctx->req_type],
2019 sizeof(ctx->errors[ctx->req_type]),
2020 "Firmware file \"%s\" request failed (err=%d)\n",
2021 ctx->fwname, err);
2022 return err;
2023 }
2024 if (blob->size < sizeof(struct b43_fw_header))
2025 goto err_format;
2026 hdr = (struct b43_fw_header *)(blob->data);
2027 switch (hdr->type) {
2028 case B43_FW_TYPE_UCODE:
2029 case B43_FW_TYPE_PCM:
2030 size = be32_to_cpu(hdr->size);
2031 if (size != blob->size - sizeof(struct b43_fw_header))
2032 goto err_format;
2033 /* fallthrough */
2034 case B43_FW_TYPE_IV:
2035 if (hdr->ver != 1)
2036 goto err_format;
2037 break;
2038 default:
2039 goto err_format;
2040 }
2041
2042 fw->data = blob;
2043 fw->filename = name;
2044 fw->type = ctx->req_type;
2045
2046 return 0;
2047
2048 err_format:
2049 snprintf(ctx->errors[ctx->req_type],
2050 sizeof(ctx->errors[ctx->req_type]),
2051 "Firmware file \"%s\" format error.\n", ctx->fwname);
2052 release_firmware(blob);
2053
2054 return -EPROTO;
2055 }
2056
2057 static int b43_try_request_fw(struct b43_request_fw_context *ctx)
2058 {
2059 struct b43_wldev *dev = ctx->dev;
2060 struct b43_firmware *fw = &ctx->dev->fw;
2061 const u8 rev = ctx->dev->dev->id.revision;
2062 const char *filename;
2063 u32 tmshigh;
2064 int err;
2065
2066 /* Get microcode */
2067 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
2068 if ((rev >= 5) && (rev <= 10))
2069 filename = "ucode5";
2070 else if ((rev >= 11) && (rev <= 12))
2071 filename = "ucode11";
2072 else if (rev == 13)
2073 filename = "ucode13";
2074 else if (rev == 14)
2075 filename = "ucode14";
2076 else if (rev >= 15)
2077 filename = "ucode15";
2078 else
2079 goto err_no_ucode;
2080 err = b43_do_request_fw(ctx, filename, &fw->ucode);
2081 if (err)
2082 goto err_load;
2083
2084 /* Get PCM code */
2085 if ((rev >= 5) && (rev <= 10))
2086 filename = "pcm5";
2087 else if (rev >= 11)
2088 filename = NULL;
2089 else
2090 goto err_no_pcm;
2091 fw->pcm_request_failed = 0;
2092 err = b43_do_request_fw(ctx, filename, &fw->pcm);
2093 if (err == -ENOENT) {
2094 /* We did not find a PCM file? Not fatal, but
2095 * core rev <= 10 must do without hwcrypto then. */
2096 fw->pcm_request_failed = 1;
2097 } else if (err)
2098 goto err_load;
2099
2100 /* Get initvals */
2101 switch (dev->phy.type) {
2102 case B43_PHYTYPE_A:
2103 if ((rev >= 5) && (rev <= 10)) {
2104 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
2105 filename = "a0g1initvals5";
2106 else
2107 filename = "a0g0initvals5";
2108 } else
2109 goto err_no_initvals;
2110 break;
2111 case B43_PHYTYPE_G:
2112 if ((rev >= 5) && (rev <= 10))
2113 filename = "b0g0initvals5";
2114 else if (rev >= 13)
2115 filename = "b0g0initvals13";
2116 else
2117 goto err_no_initvals;
2118 break;
2119 case B43_PHYTYPE_N:
2120 if ((rev >= 11) && (rev <= 12))
2121 filename = "n0initvals11";
2122 else
2123 goto err_no_initvals;
2124 break;
2125 case B43_PHYTYPE_LP:
2126 if (rev == 13)
2127 filename = "lp0initvals13";
2128 else if (rev == 14)
2129 filename = "lp0initvals14";
2130 else if (rev >= 15)
2131 filename = "lp0initvals15";
2132 else
2133 goto err_no_initvals;
2134 break;
2135 default:
2136 goto err_no_initvals;
2137 }
2138 err = b43_do_request_fw(ctx, filename, &fw->initvals);
2139 if (err)
2140 goto err_load;
2141
2142 /* Get bandswitch initvals */
2143 switch (dev->phy.type) {
2144 case B43_PHYTYPE_A:
2145 if ((rev >= 5) && (rev <= 10)) {
2146 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
2147 filename = "a0g1bsinitvals5";
2148 else
2149 filename = "a0g0bsinitvals5";
2150 } else if (rev >= 11)
2151 filename = NULL;
2152 else
2153 goto err_no_initvals;
2154 break;
2155 case B43_PHYTYPE_G:
2156 if ((rev >= 5) && (rev <= 10))
2157 filename = "b0g0bsinitvals5";
2158 else if (rev >= 11)
2159 filename = NULL;
2160 else
2161 goto err_no_initvals;
2162 break;
2163 case B43_PHYTYPE_N:
2164 if ((rev >= 11) && (rev <= 12))
2165 filename = "n0bsinitvals11";
2166 else
2167 goto err_no_initvals;
2168 break;
2169 case B43_PHYTYPE_LP:
2170 if (rev == 13)
2171 filename = "lp0bsinitvals13";
2172 else if (rev == 14)
2173 filename = "lp0bsinitvals14";
2174 else if (rev >= 15)
2175 filename = "lp0bsinitvals15";
2176 else
2177 goto err_no_initvals;
2178 break;
2179 default:
2180 goto err_no_initvals;
2181 }
2182 err = b43_do_request_fw(ctx, filename, &fw->initvals_band);
2183 if (err)
2184 goto err_load;
2185
2186 return 0;
2187
2188 err_no_ucode:
2189 err = ctx->fatal_failure = -EOPNOTSUPP;
2190 b43err(dev->wl, "The driver does not know which firmware (ucode) "
2191 "is required for your device (wl-core rev %u)\n", rev);
2192 goto error;
2193
2194 err_no_pcm:
2195 err = ctx->fatal_failure = -EOPNOTSUPP;
2196 b43err(dev->wl, "The driver does not know which firmware (PCM) "
2197 "is required for your device (wl-core rev %u)\n", rev);
2198 goto error;
2199
2200 err_no_initvals:
2201 err = ctx->fatal_failure = -EOPNOTSUPP;
2202 b43err(dev->wl, "The driver does not know which firmware (initvals) "
2203 "is required for your device (wl-core rev %u)\n", rev);
2204 goto error;
2205
2206 err_load:
2207 /* We failed to load this firmware image. The error message
2208 * already is in ctx->errors. Return and let our caller decide
2209 * what to do. */
2210 goto error;
2211
2212 error:
2213 b43_release_firmware(dev);
2214 return err;
2215 }
2216
2217 static int b43_request_firmware(struct b43_wldev *dev)
2218 {
2219 struct b43_request_fw_context *ctx;
2220 unsigned int i;
2221 int err;
2222 const char *errmsg;
2223
2224 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
2225 if (!ctx)
2226 return -ENOMEM;
2227 ctx->dev = dev;
2228
2229 ctx->req_type = B43_FWTYPE_PROPRIETARY;
2230 err = b43_try_request_fw(ctx);
2231 if (!err)
2232 goto out; /* Successfully loaded it. */
2233 err = ctx->fatal_failure;
2234 if (err)
2235 goto out;
2236
2237 ctx->req_type = B43_FWTYPE_OPENSOURCE;
2238 err = b43_try_request_fw(ctx);
2239 if (!err)
2240 goto out; /* Successfully loaded it. */
2241 err = ctx->fatal_failure;
2242 if (err)
2243 goto out;
2244
2245 /* Could not find a usable firmware. Print the errors. */
2246 for (i = 0; i < B43_NR_FWTYPES; i++) {
2247 errmsg = ctx->errors[i];
2248 if (strlen(errmsg))
2249 b43err(dev->wl, errmsg);
2250 }
2251 b43_print_fw_helptext(dev->wl, 1);
2252 err = -ENOENT;
2253
2254 out:
2255 kfree(ctx);
2256 return err;
2257 }
2258
2259 static int b43_upload_microcode(struct b43_wldev *dev)
2260 {
2261 const size_t hdr_len = sizeof(struct b43_fw_header);
2262 const __be32 *data;
2263 unsigned int i, len;
2264 u16 fwrev, fwpatch, fwdate, fwtime;
2265 u32 tmp, macctl;
2266 int err = 0;
2267
2268 /* Jump the microcode PSM to offset 0 */
2269 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2270 B43_WARN_ON(macctl & B43_MACCTL_PSM_RUN);
2271 macctl |= B43_MACCTL_PSM_JMP0;
2272 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2273 /* Zero out all microcode PSM registers and shared memory. */
2274 for (i = 0; i < 64; i++)
2275 b43_shm_write16(dev, B43_SHM_SCRATCH, i, 0);
2276 for (i = 0; i < 4096; i += 2)
2277 b43_shm_write16(dev, B43_SHM_SHARED, i, 0);
2278
2279 /* Upload Microcode. */
2280 data = (__be32 *) (dev->fw.ucode.data->data + hdr_len);
2281 len = (dev->fw.ucode.data->size - hdr_len) / sizeof(__be32);
2282 b43_shm_control_word(dev, B43_SHM_UCODE | B43_SHM_AUTOINC_W, 0x0000);
2283 for (i = 0; i < len; i++) {
2284 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2285 udelay(10);
2286 }
2287
2288 if (dev->fw.pcm.data) {
2289 /* Upload PCM data. */
2290 data = (__be32 *) (dev->fw.pcm.data->data + hdr_len);
2291 len = (dev->fw.pcm.data->size - hdr_len) / sizeof(__be32);
2292 b43_shm_control_word(dev, B43_SHM_HW, 0x01EA);
2293 b43_write32(dev, B43_MMIO_SHM_DATA, 0x00004000);
2294 /* No need for autoinc bit in SHM_HW */
2295 b43_shm_control_word(dev, B43_SHM_HW, 0x01EB);
2296 for (i = 0; i < len; i++) {
2297 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2298 udelay(10);
2299 }
2300 }
2301
2302 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_ALL);
2303
2304 /* Start the microcode PSM */
2305 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2306 macctl &= ~B43_MACCTL_PSM_JMP0;
2307 macctl |= B43_MACCTL_PSM_RUN;
2308 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2309
2310 /* Wait for the microcode to load and respond */
2311 i = 0;
2312 while (1) {
2313 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2314 if (tmp == B43_IRQ_MAC_SUSPENDED)
2315 break;
2316 i++;
2317 if (i >= 20) {
2318 b43err(dev->wl, "Microcode not responding\n");
2319 b43_print_fw_helptext(dev->wl, 1);
2320 err = -ENODEV;
2321 goto error;
2322 }
2323 msleep_interruptible(50);
2324 if (signal_pending(current)) {
2325 err = -EINTR;
2326 goto error;
2327 }
2328 }
2329 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); /* dummy read */
2330
2331 /* Get and check the revisions. */
2332 fwrev = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEREV);
2333 fwpatch = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEPATCH);
2334 fwdate = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEDATE);
2335 fwtime = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODETIME);
2336
2337 if (fwrev <= 0x128) {
2338 b43err(dev->wl, "YOUR FIRMWARE IS TOO OLD. Firmware from "
2339 "binary drivers older than version 4.x is unsupported. "
2340 "You must upgrade your firmware files.\n");
2341 b43_print_fw_helptext(dev->wl, 1);
2342 err = -EOPNOTSUPP;
2343 goto error;
2344 }
2345 dev->fw.rev = fwrev;
2346 dev->fw.patch = fwpatch;
2347 dev->fw.opensource = (fwdate == 0xFFFF);
2348
2349 /* Default to use-all-queues. */
2350 dev->wl->hw->queues = dev->wl->mac80211_initially_registered_queues;
2351 dev->qos_enabled = !!modparam_qos;
2352 /* Default to firmware/hardware crypto acceleration. */
2353 dev->hwcrypto_enabled = 1;
2354
2355 if (dev->fw.opensource) {
2356 u16 fwcapa;
2357
2358 /* Patchlevel info is encoded in the "time" field. */
2359 dev->fw.patch = fwtime;
2360 b43info(dev->wl, "Loading OpenSource firmware version %u.%u\n",
2361 dev->fw.rev, dev->fw.patch);
2362
2363 fwcapa = b43_fwcapa_read(dev);
2364 if (!(fwcapa & B43_FWCAPA_HWCRYPTO) || dev->fw.pcm_request_failed) {
2365 b43info(dev->wl, "Hardware crypto acceleration not supported by firmware\n");
2366 /* Disable hardware crypto and fall back to software crypto. */
2367 dev->hwcrypto_enabled = 0;
2368 }
2369 if (!(fwcapa & B43_FWCAPA_QOS)) {
2370 b43info(dev->wl, "QoS not supported by firmware\n");
2371 /* Disable QoS. Tweak hw->queues to 1. It will be restored before
2372 * ieee80211_unregister to make sure the networking core can
2373 * properly free possible resources. */
2374 dev->wl->hw->queues = 1;
2375 dev->qos_enabled = 0;
2376 }
2377 } else {
2378 b43info(dev->wl, "Loading firmware version %u.%u "
2379 "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n",
2380 fwrev, fwpatch,
2381 (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
2382 (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F);
2383 if (dev->fw.pcm_request_failed) {
2384 b43warn(dev->wl, "No \"pcm5.fw\" firmware file found. "
2385 "Hardware accelerated cryptography is disabled.\n");
2386 b43_print_fw_helptext(dev->wl, 0);
2387 }
2388 }
2389
2390 if (b43_is_old_txhdr_format(dev)) {
2391 /* We're over the deadline, but we keep support for old fw
2392 * until it turns out to be in major conflict with something new. */
2393 b43warn(dev->wl, "You are using an old firmware image. "
2394 "Support for old firmware will be removed soon "
2395 "(official deadline was July 2008).\n");
2396 b43_print_fw_helptext(dev->wl, 0);
2397 }
2398
2399 return 0;
2400
2401 error:
2402 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2403 macctl &= ~B43_MACCTL_PSM_RUN;
2404 macctl |= B43_MACCTL_PSM_JMP0;
2405 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2406
2407 return err;
2408 }
2409
2410 static int b43_write_initvals(struct b43_wldev *dev,
2411 const struct b43_iv *ivals,
2412 size_t count,
2413 size_t array_size)
2414 {
2415 const struct b43_iv *iv;
2416 u16 offset;
2417 size_t i;
2418 bool bit32;
2419
2420 BUILD_BUG_ON(sizeof(struct b43_iv) != 6);
2421 iv = ivals;
2422 for (i = 0; i < count; i++) {
2423 if (array_size < sizeof(iv->offset_size))
2424 goto err_format;
2425 array_size -= sizeof(iv->offset_size);
2426 offset = be16_to_cpu(iv->offset_size);
2427 bit32 = !!(offset & B43_IV_32BIT);
2428 offset &= B43_IV_OFFSET_MASK;
2429 if (offset >= 0x1000)
2430 goto err_format;
2431 if (bit32) {
2432 u32 value;
2433
2434 if (array_size < sizeof(iv->data.d32))
2435 goto err_format;
2436 array_size -= sizeof(iv->data.d32);
2437
2438 value = get_unaligned_be32(&iv->data.d32);
2439 b43_write32(dev, offset, value);
2440
2441 iv = (const struct b43_iv *)((const uint8_t *)iv +
2442 sizeof(__be16) +
2443 sizeof(__be32));
2444 } else {
2445 u16 value;
2446
2447 if (array_size < sizeof(iv->data.d16))
2448 goto err_format;
2449 array_size -= sizeof(iv->data.d16);
2450
2451 value = be16_to_cpu(iv->data.d16);
2452 b43_write16(dev, offset, value);
2453
2454 iv = (const struct b43_iv *)((const uint8_t *)iv +
2455 sizeof(__be16) +
2456 sizeof(__be16));
2457 }
2458 }
2459 if (array_size)
2460 goto err_format;
2461
2462 return 0;
2463
2464 err_format:
2465 b43err(dev->wl, "Initial Values Firmware file-format error.\n");
2466 b43_print_fw_helptext(dev->wl, 1);
2467
2468 return -EPROTO;
2469 }
2470
2471 static int b43_upload_initvals(struct b43_wldev *dev)
2472 {
2473 const size_t hdr_len = sizeof(struct b43_fw_header);
2474 const struct b43_fw_header *hdr;
2475 struct b43_firmware *fw = &dev->fw;
2476 const struct b43_iv *ivals;
2477 size_t count;
2478 int err;
2479
2480 hdr = (const struct b43_fw_header *)(fw->initvals.data->data);
2481 ivals = (const struct b43_iv *)(fw->initvals.data->data + hdr_len);
2482 count = be32_to_cpu(hdr->size);
2483 err = b43_write_initvals(dev, ivals, count,
2484 fw->initvals.data->size - hdr_len);
2485 if (err)
2486 goto out;
2487 if (fw->initvals_band.data) {
2488 hdr = (const struct b43_fw_header *)(fw->initvals_band.data->data);
2489 ivals = (const struct b43_iv *)(fw->initvals_band.data->data + hdr_len);
2490 count = be32_to_cpu(hdr->size);
2491 err = b43_write_initvals(dev, ivals, count,
2492 fw->initvals_band.data->size - hdr_len);
2493 if (err)
2494 goto out;
2495 }
2496 out:
2497
2498 return err;
2499 }
2500
2501 /* Initialize the GPIOs
2502 * http://bcm-specs.sipsolutions.net/GPIO
2503 */
2504 static int b43_gpio_init(struct b43_wldev *dev)
2505 {
2506 struct ssb_bus *bus = dev->dev->bus;
2507 struct ssb_device *gpiodev, *pcidev = NULL;
2508 u32 mask, set;
2509
2510 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2511 & ~B43_MACCTL_GPOUTSMSK);
2512
2513 b43_write16(dev, B43_MMIO_GPIO_MASK, b43_read16(dev, B43_MMIO_GPIO_MASK)
2514 | 0x000F);
2515
2516 mask = 0x0000001F;
2517 set = 0x0000000F;
2518 if (dev->dev->bus->chip_id == 0x4301) {
2519 mask |= 0x0060;
2520 set |= 0x0060;
2521 }
2522 if (0 /* FIXME: conditional unknown */ ) {
2523 b43_write16(dev, B43_MMIO_GPIO_MASK,
2524 b43_read16(dev, B43_MMIO_GPIO_MASK)
2525 | 0x0100);
2526 mask |= 0x0180;
2527 set |= 0x0180;
2528 }
2529 if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_PACTRL) {
2530 b43_write16(dev, B43_MMIO_GPIO_MASK,
2531 b43_read16(dev, B43_MMIO_GPIO_MASK)
2532 | 0x0200);
2533 mask |= 0x0200;
2534 set |= 0x0200;
2535 }
2536 if (dev->dev->id.revision >= 2)
2537 mask |= 0x0010; /* FIXME: This is redundant. */
2538
2539 #ifdef CONFIG_SSB_DRIVER_PCICORE
2540 pcidev = bus->pcicore.dev;
2541 #endif
2542 gpiodev = bus->chipco.dev ? : pcidev;
2543 if (!gpiodev)
2544 return 0;
2545 ssb_write32(gpiodev, B43_GPIO_CONTROL,
2546 (ssb_read32(gpiodev, B43_GPIO_CONTROL)
2547 & mask) | set);
2548
2549 return 0;
2550 }
2551
2552 /* Turn off all GPIO stuff. Call this on module unload, for example. */
2553 static void b43_gpio_cleanup(struct b43_wldev *dev)
2554 {
2555 struct ssb_bus *bus = dev->dev->bus;
2556 struct ssb_device *gpiodev, *pcidev = NULL;
2557
2558 #ifdef CONFIG_SSB_DRIVER_PCICORE
2559 pcidev = bus->pcicore.dev;
2560 #endif
2561 gpiodev = bus->chipco.dev ? : pcidev;
2562 if (!gpiodev)
2563 return;
2564 ssb_write32(gpiodev, B43_GPIO_CONTROL, 0);
2565 }
2566
2567 /* http://bcm-specs.sipsolutions.net/EnableMac */
2568 void b43_mac_enable(struct b43_wldev *dev)
2569 {
2570 if (b43_debug(dev, B43_DBG_FIRMWARE)) {
2571 u16 fwstate;
2572
2573 fwstate = b43_shm_read16(dev, B43_SHM_SHARED,
2574 B43_SHM_SH_UCODESTAT);
2575 if ((fwstate != B43_SHM_SH_UCODESTAT_SUSP) &&
2576 (fwstate != B43_SHM_SH_UCODESTAT_SLEEP)) {
2577 b43err(dev->wl, "b43_mac_enable(): The firmware "
2578 "should be suspended, but current state is %u\n",
2579 fwstate);
2580 }
2581 }
2582
2583 dev->mac_suspended--;
2584 B43_WARN_ON(dev->mac_suspended < 0);
2585 if (dev->mac_suspended == 0) {
2586 b43_write32(dev, B43_MMIO_MACCTL,
2587 b43_read32(dev, B43_MMIO_MACCTL)
2588 | B43_MACCTL_ENABLED);
2589 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON,
2590 B43_IRQ_MAC_SUSPENDED);
2591 /* Commit writes */
2592 b43_read32(dev, B43_MMIO_MACCTL);
2593 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2594 b43_power_saving_ctl_bits(dev, 0);
2595 }
2596 }
2597
2598 /* http://bcm-specs.sipsolutions.net/SuspendMAC */
2599 void b43_mac_suspend(struct b43_wldev *dev)
2600 {
2601 int i;
2602 u32 tmp;
2603
2604 might_sleep();
2605 B43_WARN_ON(dev->mac_suspended < 0);
2606
2607 if (dev->mac_suspended == 0) {
2608 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
2609 b43_write32(dev, B43_MMIO_MACCTL,
2610 b43_read32(dev, B43_MMIO_MACCTL)
2611 & ~B43_MACCTL_ENABLED);
2612 /* force pci to flush the write */
2613 b43_read32(dev, B43_MMIO_MACCTL);
2614 for (i = 35; i; i--) {
2615 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2616 if (tmp & B43_IRQ_MAC_SUSPENDED)
2617 goto out;
2618 udelay(10);
2619 }
2620 /* Hm, it seems this will take some time. Use msleep(). */
2621 for (i = 40; i; i--) {
2622 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2623 if (tmp & B43_IRQ_MAC_SUSPENDED)
2624 goto out;
2625 msleep(1);
2626 }
2627 b43err(dev->wl, "MAC suspend failed\n");
2628 }
2629 out:
2630 dev->mac_suspended++;
2631 }
2632
2633 static void b43_adjust_opmode(struct b43_wldev *dev)
2634 {
2635 struct b43_wl *wl = dev->wl;
2636 u32 ctl;
2637 u16 cfp_pretbtt;
2638
2639 ctl = b43_read32(dev, B43_MMIO_MACCTL);
2640 /* Reset status to STA infrastructure mode. */
2641 ctl &= ~B43_MACCTL_AP;
2642 ctl &= ~B43_MACCTL_KEEP_CTL;
2643 ctl &= ~B43_MACCTL_KEEP_BADPLCP;
2644 ctl &= ~B43_MACCTL_KEEP_BAD;
2645 ctl &= ~B43_MACCTL_PROMISC;
2646 ctl &= ~B43_MACCTL_BEACPROMISC;
2647 ctl |= B43_MACCTL_INFRA;
2648
2649 if (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
2650 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT))
2651 ctl |= B43_MACCTL_AP;
2652 else if (b43_is_mode(wl, NL80211_IFTYPE_ADHOC))
2653 ctl &= ~B43_MACCTL_INFRA;
2654
2655 if (wl->filter_flags & FIF_CONTROL)
2656 ctl |= B43_MACCTL_KEEP_CTL;
2657 if (wl->filter_flags & FIF_FCSFAIL)
2658 ctl |= B43_MACCTL_KEEP_BAD;
2659 if (wl->filter_flags & FIF_PLCPFAIL)
2660 ctl |= B43_MACCTL_KEEP_BADPLCP;
2661 if (wl->filter_flags & FIF_PROMISC_IN_BSS)
2662 ctl |= B43_MACCTL_PROMISC;
2663 if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC)
2664 ctl |= B43_MACCTL_BEACPROMISC;
2665
2666 /* Workaround: On old hardware the HW-MAC-address-filter
2667 * doesn't work properly, so always run promisc in filter
2668 * it in software. */
2669 if (dev->dev->id.revision <= 4)
2670 ctl |= B43_MACCTL_PROMISC;
2671
2672 b43_write32(dev, B43_MMIO_MACCTL, ctl);
2673
2674 cfp_pretbtt = 2;
2675 if ((ctl & B43_MACCTL_INFRA) && !(ctl & B43_MACCTL_AP)) {
2676 if (dev->dev->bus->chip_id == 0x4306 &&
2677 dev->dev->bus->chip_rev == 3)
2678 cfp_pretbtt = 100;
2679 else
2680 cfp_pretbtt = 50;
2681 }
2682 b43_write16(dev, 0x612, cfp_pretbtt);
2683 }
2684
2685 static void b43_rate_memory_write(struct b43_wldev *dev, u16 rate, int is_ofdm)
2686 {
2687 u16 offset;
2688
2689 if (is_ofdm) {
2690 offset = 0x480;
2691 offset += (b43_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
2692 } else {
2693 offset = 0x4C0;
2694 offset += (b43_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
2695 }
2696 b43_shm_write16(dev, B43_SHM_SHARED, offset + 0x20,
2697 b43_shm_read16(dev, B43_SHM_SHARED, offset));
2698 }
2699
2700 static void b43_rate_memory_init(struct b43_wldev *dev)
2701 {
2702 switch (dev->phy.type) {
2703 case B43_PHYTYPE_A:
2704 case B43_PHYTYPE_G:
2705 case B43_PHYTYPE_N:
2706 case B43_PHYTYPE_LP:
2707 b43_rate_memory_write(dev, B43_OFDM_RATE_6MB, 1);
2708 b43_rate_memory_write(dev, B43_OFDM_RATE_12MB, 1);
2709 b43_rate_memory_write(dev, B43_OFDM_RATE_18MB, 1);
2710 b43_rate_memory_write(dev, B43_OFDM_RATE_24MB, 1);
2711 b43_rate_memory_write(dev, B43_OFDM_RATE_36MB, 1);
2712 b43_rate_memory_write(dev, B43_OFDM_RATE_48MB, 1);
2713 b43_rate_memory_write(dev, B43_OFDM_RATE_54MB, 1);
2714 if (dev->phy.type == B43_PHYTYPE_A)
2715 break;
2716 /* fallthrough */
2717 case B43_PHYTYPE_B:
2718 b43_rate_memory_write(dev, B43_CCK_RATE_1MB, 0);
2719 b43_rate_memory_write(dev, B43_CCK_RATE_2MB, 0);
2720 b43_rate_memory_write(dev, B43_CCK_RATE_5MB, 0);
2721 b43_rate_memory_write(dev, B43_CCK_RATE_11MB, 0);
2722 break;
2723 default:
2724 B43_WARN_ON(1);
2725 }
2726 }
2727
2728 /* Set the default values for the PHY TX Control Words. */
2729 static void b43_set_phytxctl_defaults(struct b43_wldev *dev)
2730 {
2731 u16 ctl = 0;
2732
2733 ctl |= B43_TXH_PHY_ENC_CCK;
2734 ctl |= B43_TXH_PHY_ANT01AUTO;
2735 ctl |= B43_TXH_PHY_TXPWR;
2736
2737 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
2738 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, ctl);
2739 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, ctl);
2740 }
2741
2742 /* Set the TX-Antenna for management frames sent by firmware. */
2743 static void b43_mgmtframe_txantenna(struct b43_wldev *dev, int antenna)
2744 {
2745 u16 ant;
2746 u16 tmp;
2747
2748 ant = b43_antenna_to_phyctl(antenna);
2749
2750 /* For ACK/CTS */
2751 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL);
2752 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
2753 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, tmp);
2754 /* For Probe Resposes */
2755 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL);
2756 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
2757 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, tmp);
2758 }
2759
2760 /* This is the opposite of b43_chip_init() */
2761 static void b43_chip_exit(struct b43_wldev *dev)
2762 {
2763 b43_phy_exit(dev);
2764 b43_gpio_cleanup(dev);
2765 /* firmware is released later */
2766 }
2767
2768 /* Initialize the chip
2769 * http://bcm-specs.sipsolutions.net/ChipInit
2770 */
2771 static int b43_chip_init(struct b43_wldev *dev)
2772 {
2773 struct b43_phy *phy = &dev->phy;
2774 int err;
2775 u32 value32, macctl;
2776 u16 value16;
2777
2778 /* Initialize the MAC control */
2779 macctl = B43_MACCTL_IHR_ENABLED | B43_MACCTL_SHM_ENABLED;
2780 if (dev->phy.gmode)
2781 macctl |= B43_MACCTL_GMODE;
2782 macctl |= B43_MACCTL_INFRA;
2783 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2784
2785 err = b43_request_firmware(dev);
2786 if (err)
2787 goto out;
2788 err = b43_upload_microcode(dev);
2789 if (err)
2790 goto out; /* firmware is released later */
2791
2792 err = b43_gpio_init(dev);
2793 if (err)
2794 goto out; /* firmware is released later */
2795
2796 err = b43_upload_initvals(dev);
2797 if (err)
2798 goto err_gpio_clean;
2799
2800 /* Turn the Analog on and initialize the PHY. */
2801 phy->ops->switch_analog(dev, 1);
2802 err = b43_phy_init(dev);
2803 if (err)
2804 goto err_gpio_clean;
2805
2806 /* Disable Interference Mitigation. */
2807 if (phy->ops->interf_mitigation)
2808 phy->ops->interf_mitigation(dev, B43_INTERFMODE_NONE);
2809
2810 /* Select the antennae */
2811 if (phy->ops->set_rx_antenna)
2812 phy->ops->set_rx_antenna(dev, B43_ANTENNA_DEFAULT);
2813 b43_mgmtframe_txantenna(dev, B43_ANTENNA_DEFAULT);
2814
2815 if (phy->type == B43_PHYTYPE_B) {
2816 value16 = b43_read16(dev, 0x005E);
2817 value16 |= 0x0004;
2818 b43_write16(dev, 0x005E, value16);
2819 }
2820 b43_write32(dev, 0x0100, 0x01000000);
2821 if (dev->dev->id.revision < 5)
2822 b43_write32(dev, 0x010C, 0x01000000);
2823
2824 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2825 & ~B43_MACCTL_INFRA);
2826 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2827 | B43_MACCTL_INFRA);
2828
2829 /* Probe Response Timeout value */
2830 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
2831 b43_shm_write16(dev, B43_SHM_SHARED, 0x0074, 0x0000);
2832
2833 /* Initially set the wireless operation mode. */
2834 b43_adjust_opmode(dev);
2835
2836 if (dev->dev->id.revision < 3) {
2837 b43_write16(dev, 0x060E, 0x0000);
2838 b43_write16(dev, 0x0610, 0x8000);
2839 b43_write16(dev, 0x0604, 0x0000);
2840 b43_write16(dev, 0x0606, 0x0200);
2841 } else {
2842 b43_write32(dev, 0x0188, 0x80000000);
2843 b43_write32(dev, 0x018C, 0x02000000);
2844 }
2845 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 0x00004000);
2846 b43_write32(dev, B43_MMIO_DMA0_IRQ_MASK, 0x0001DC00);
2847 b43_write32(dev, B43_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
2848 b43_write32(dev, B43_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
2849 b43_write32(dev, B43_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
2850 b43_write32(dev, B43_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
2851 b43_write32(dev, B43_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
2852
2853 value32 = ssb_read32(dev->dev, SSB_TMSLOW);
2854 value32 |= 0x00100000;
2855 ssb_write32(dev->dev, SSB_TMSLOW, value32);
2856
2857 b43_write16(dev, B43_MMIO_POWERUP_DELAY,
2858 dev->dev->bus->chipco.fast_pwrup_delay);
2859
2860 err = 0;
2861 b43dbg(dev->wl, "Chip initialized\n");
2862 out:
2863 return err;
2864
2865 err_gpio_clean:
2866 b43_gpio_cleanup(dev);
2867 return err;
2868 }
2869
2870 static void b43_periodic_every60sec(struct b43_wldev *dev)
2871 {
2872 const struct b43_phy_operations *ops = dev->phy.ops;
2873
2874 if (ops->pwork_60sec)
2875 ops->pwork_60sec(dev);
2876
2877 /* Force check the TX power emission now. */
2878 b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME);
2879 }
2880
2881 static void b43_periodic_every30sec(struct b43_wldev *dev)
2882 {
2883 /* Update device statistics. */
2884 b43_calculate_link_quality(dev);
2885 }
2886
2887 static void b43_periodic_every15sec(struct b43_wldev *dev)
2888 {
2889 struct b43_phy *phy = &dev->phy;
2890 u16 wdr;
2891
2892 if (dev->fw.opensource) {
2893 /* Check if the firmware is still alive.
2894 * It will reset the watchdog counter to 0 in its idle loop. */
2895 wdr = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_WATCHDOG_REG);
2896 if (unlikely(wdr)) {
2897 b43err(dev->wl, "Firmware watchdog: The firmware died!\n");
2898 b43_controller_restart(dev, "Firmware watchdog");
2899 return;
2900 } else {
2901 b43_shm_write16(dev, B43_SHM_SCRATCH,
2902 B43_WATCHDOG_REG, 1);
2903 }
2904 }
2905
2906 if (phy->ops->pwork_15sec)
2907 phy->ops->pwork_15sec(dev);
2908
2909 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
2910 wmb();
2911 }
2912
2913 static void do_periodic_work(struct b43_wldev *dev)
2914 {
2915 unsigned int state;
2916
2917 state = dev->periodic_state;
2918 if (state % 4 == 0)
2919 b43_periodic_every60sec(dev);
2920 if (state % 2 == 0)
2921 b43_periodic_every30sec(dev);
2922 b43_periodic_every15sec(dev);
2923 }
2924
2925 /* Periodic work locking policy:
2926 * The whole periodic work handler is protected by
2927 * wl->mutex. If another lock is needed somewhere in the
2928 * pwork callchain, it's aquired in-place, where it's needed.
2929 */
2930 static void b43_periodic_work_handler(struct work_struct *work)
2931 {
2932 struct b43_wldev *dev = container_of(work, struct b43_wldev,
2933 periodic_work.work);
2934 struct b43_wl *wl = dev->wl;
2935 unsigned long delay;
2936
2937 mutex_lock(&wl->mutex);
2938
2939 if (unlikely(b43_status(dev) != B43_STAT_STARTED))
2940 goto out;
2941 if (b43_debug(dev, B43_DBG_PWORK_STOP))
2942 goto out_requeue;
2943
2944 do_periodic_work(dev);
2945
2946 dev->periodic_state++;
2947 out_requeue:
2948 if (b43_debug(dev, B43_DBG_PWORK_FAST))
2949 delay = msecs_to_jiffies(50);
2950 else
2951 delay = round_jiffies_relative(HZ * 15);
2952 ieee80211_queue_delayed_work(wl->hw, &dev->periodic_work, delay);
2953 out:
2954 mutex_unlock(&wl->mutex);
2955 }
2956
2957 static void b43_periodic_tasks_setup(struct b43_wldev *dev)
2958 {
2959 struct delayed_work *work = &dev->periodic_work;
2960
2961 dev->periodic_state = 0;
2962 INIT_DELAYED_WORK(work, b43_periodic_work_handler);
2963 ieee80211_queue_delayed_work(dev->wl->hw, work, 0);
2964 }
2965
2966 /* Check if communication with the device works correctly. */
2967 static int b43_validate_chipaccess(struct b43_wldev *dev)
2968 {
2969 u32 v, backup0, backup4;
2970
2971 backup0 = b43_shm_read32(dev, B43_SHM_SHARED, 0);
2972 backup4 = b43_shm_read32(dev, B43_SHM_SHARED, 4);
2973
2974 /* Check for read/write and endianness problems. */
2975 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0x55AAAA55);
2976 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0x55AAAA55)
2977 goto error;
2978 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0xAA5555AA);
2979 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0xAA5555AA)
2980 goto error;
2981
2982 /* Check if unaligned 32bit SHM_SHARED access works properly.
2983 * However, don't bail out on failure, because it's noncritical. */
2984 b43_shm_write16(dev, B43_SHM_SHARED, 0, 0x1122);
2985 b43_shm_write16(dev, B43_SHM_SHARED, 2, 0x3344);
2986 b43_shm_write16(dev, B43_SHM_SHARED, 4, 0x5566);
2987 b43_shm_write16(dev, B43_SHM_SHARED, 6, 0x7788);
2988 if (b43_shm_read32(dev, B43_SHM_SHARED, 2) != 0x55663344)
2989 b43warn(dev->wl, "Unaligned 32bit SHM read access is broken\n");
2990 b43_shm_write32(dev, B43_SHM_SHARED, 2, 0xAABBCCDD);
2991 if (b43_shm_read16(dev, B43_SHM_SHARED, 0) != 0x1122 ||
2992 b43_shm_read16(dev, B43_SHM_SHARED, 2) != 0xCCDD ||
2993 b43_shm_read16(dev, B43_SHM_SHARED, 4) != 0xAABB ||
2994 b43_shm_read16(dev, B43_SHM_SHARED, 6) != 0x7788)
2995 b43warn(dev->wl, "Unaligned 32bit SHM write access is broken\n");
2996
2997 b43_shm_write32(dev, B43_SHM_SHARED, 0, backup0);
2998 b43_shm_write32(dev, B43_SHM_SHARED, 4, backup4);
2999
3000 if ((dev->dev->id.revision >= 3) && (dev->dev->id.revision <= 10)) {
3001 /* The 32bit register shadows the two 16bit registers
3002 * with update sideeffects. Validate this. */
3003 b43_write16(dev, B43_MMIO_TSF_CFP_START, 0xAAAA);
3004 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0xCCCCBBBB);
3005 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_LOW) != 0xBBBB)
3006 goto error;
3007 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_HIGH) != 0xCCCC)
3008 goto error;
3009 }
3010 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0);
3011
3012 v = b43_read32(dev, B43_MMIO_MACCTL);
3013 v |= B43_MACCTL_GMODE;
3014 if (v != (B43_MACCTL_GMODE | B43_MACCTL_IHR_ENABLED))
3015 goto error;
3016
3017 return 0;
3018 error:
3019 b43err(dev->wl, "Failed to validate the chipaccess\n");
3020 return -ENODEV;
3021 }
3022
3023 static void b43_security_init(struct b43_wldev *dev)
3024 {
3025 dev->ktp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_KTP);
3026 /* KTP is a word address, but we address SHM bytewise.
3027 * So multiply by two.
3028 */
3029 dev->ktp *= 2;
3030 /* Number of RCMTA address slots */
3031 b43_write16(dev, B43_MMIO_RCMTA_COUNT, B43_NR_PAIRWISE_KEYS);
3032 /* Clear the key memory. */
3033 b43_clear_keys(dev);
3034 }
3035
3036 #ifdef CONFIG_B43_HWRNG
3037 static int b43_rng_read(struct hwrng *rng, u32 *data)
3038 {
3039 struct b43_wl *wl = (struct b43_wl *)rng->priv;
3040 unsigned long flags;
3041
3042 /* Don't take wl->mutex here, as it could deadlock with
3043 * hwrng internal locking. It's not needed to take
3044 * wl->mutex here, anyway. */
3045
3046 spin_lock_irqsave(&wl->irq_lock, flags);
3047 *data = b43_read16(wl->current_dev, B43_MMIO_RNG);
3048 spin_unlock_irqrestore(&wl->irq_lock, flags);
3049
3050 return (sizeof(u16));
3051 }
3052 #endif /* CONFIG_B43_HWRNG */
3053
3054 static void b43_rng_exit(struct b43_wl *wl)
3055 {
3056 #ifdef CONFIG_B43_HWRNG
3057 if (wl->rng_initialized)
3058 hwrng_unregister(&wl->rng);
3059 #endif /* CONFIG_B43_HWRNG */
3060 }
3061
3062 static int b43_rng_init(struct b43_wl *wl)
3063 {
3064 int err = 0;
3065
3066 #ifdef CONFIG_B43_HWRNG
3067 snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
3068 "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
3069 wl->rng.name = wl->rng_name;
3070 wl->rng.data_read = b43_rng_read;
3071 wl->rng.priv = (unsigned long)wl;
3072 wl->rng_initialized = 1;
3073 err = hwrng_register(&wl->rng);
3074 if (err) {
3075 wl->rng_initialized = 0;
3076 b43err(wl, "Failed to register the random "
3077 "number generator (%d)\n", err);
3078 }
3079 #endif /* CONFIG_B43_HWRNG */
3080
3081 return err;
3082 }
3083
3084 static int b43_op_tx(struct ieee80211_hw *hw,
3085 struct sk_buff *skb)
3086 {
3087 struct b43_wl *wl = hw_to_b43_wl(hw);
3088 struct b43_wldev *dev = wl->current_dev;
3089 unsigned long flags;
3090 int err;
3091
3092 if (unlikely(skb->len < 2 + 2 + 6)) {
3093 /* Too short, this can't be a valid frame. */
3094 goto drop_packet;
3095 }
3096 B43_WARN_ON(skb_shinfo(skb)->nr_frags);
3097 if (unlikely(!dev))
3098 goto drop_packet;
3099
3100 /* Transmissions on seperate queues can run concurrently. */
3101 read_lock_irqsave(&wl->tx_lock, flags);
3102
3103 err = -ENODEV;
3104 if (likely(b43_status(dev) >= B43_STAT_STARTED)) {
3105 if (b43_using_pio_transfers(dev))
3106 err = b43_pio_tx(dev, skb);
3107 else
3108 err = b43_dma_tx(dev, skb);
3109 }
3110
3111 read_unlock_irqrestore(&wl->tx_lock, flags);
3112
3113 if (unlikely(err))
3114 goto drop_packet;
3115 return NETDEV_TX_OK;
3116
3117 drop_packet:
3118 /* We can not transmit this packet. Drop it. */
3119 dev_kfree_skb_any(skb);
3120 return NETDEV_TX_OK;
3121 }
3122
3123 /* Locking: wl->irq_lock */
3124 static void b43_qos_params_upload(struct b43_wldev *dev,
3125 const struct ieee80211_tx_queue_params *p,
3126 u16 shm_offset)
3127 {
3128 u16 params[B43_NR_QOSPARAMS];
3129 int bslots, tmp;
3130 unsigned int i;
3131
3132 bslots = b43_read16(dev, B43_MMIO_RNG) & p->cw_min;
3133
3134 memset(&params, 0, sizeof(params));
3135
3136 params[B43_QOSPARAM_TXOP] = p->txop * 32;
3137 params[B43_QOSPARAM_CWMIN] = p->cw_min;
3138 params[B43_QOSPARAM_CWMAX] = p->cw_max;
3139 params[B43_QOSPARAM_CWCUR] = p->cw_min;
3140 params[B43_QOSPARAM_AIFS] = p->aifs;
3141 params[B43_QOSPARAM_BSLOTS] = bslots;
3142 params[B43_QOSPARAM_REGGAP] = bslots + p->aifs;
3143
3144 for (i = 0; i < ARRAY_SIZE(params); i++) {
3145 if (i == B43_QOSPARAM_STATUS) {
3146 tmp = b43_shm_read16(dev, B43_SHM_SHARED,
3147 shm_offset + (i * 2));
3148 /* Mark the parameters as updated. */
3149 tmp |= 0x100;
3150 b43_shm_write16(dev, B43_SHM_SHARED,
3151 shm_offset + (i * 2),
3152 tmp);
3153 } else {
3154 b43_shm_write16(dev, B43_SHM_SHARED,
3155 shm_offset + (i * 2),
3156 params[i]);
3157 }
3158 }
3159 }
3160
3161 /* Mapping of mac80211 queue numbers to b43 QoS SHM offsets. */
3162 static const u16 b43_qos_shm_offsets[] = {
3163 /* [mac80211-queue-nr] = SHM_OFFSET, */
3164 [0] = B43_QOS_VOICE,
3165 [1] = B43_QOS_VIDEO,
3166 [2] = B43_QOS_BESTEFFORT,
3167 [3] = B43_QOS_BACKGROUND,
3168 };
3169
3170 /* Update all QOS parameters in hardware. */
3171 static void b43_qos_upload_all(struct b43_wldev *dev)
3172 {
3173 struct b43_wl *wl = dev->wl;
3174 struct b43_qos_params *params;
3175 unsigned int i;
3176
3177 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3178 ARRAY_SIZE(wl->qos_params));
3179
3180 b43_mac_suspend(dev);
3181 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
3182 params = &(wl->qos_params[i]);
3183 b43_qos_params_upload(dev, &(params->p),
3184 b43_qos_shm_offsets[i]);
3185 }
3186 b43_mac_enable(dev);
3187 }
3188
3189 static void b43_qos_clear(struct b43_wl *wl)
3190 {
3191 struct b43_qos_params *params;
3192 unsigned int i;
3193
3194 /* Initialize QoS parameters to sane defaults. */
3195
3196 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3197 ARRAY_SIZE(wl->qos_params));
3198
3199 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
3200 params = &(wl->qos_params[i]);
3201
3202 switch (b43_qos_shm_offsets[i]) {
3203 case B43_QOS_VOICE:
3204 params->p.txop = 0;
3205 params->p.aifs = 2;
3206 params->p.cw_min = 0x0001;
3207 params->p.cw_max = 0x0001;
3208 break;
3209 case B43_QOS_VIDEO:
3210 params->p.txop = 0;
3211 params->p.aifs = 2;
3212 params->p.cw_min = 0x0001;
3213 params->p.cw_max = 0x0001;
3214 break;
3215 case B43_QOS_BESTEFFORT:
3216 params->p.txop = 0;
3217 params->p.aifs = 3;
3218 params->p.cw_min = 0x0001;
3219 params->p.cw_max = 0x03FF;
3220 break;
3221 case B43_QOS_BACKGROUND:
3222 params->p.txop = 0;
3223 params->p.aifs = 7;
3224 params->p.cw_min = 0x0001;
3225 params->p.cw_max = 0x03FF;
3226 break;
3227 default:
3228 B43_WARN_ON(1);
3229 }
3230 }
3231 }
3232
3233 /* Initialize the core's QOS capabilities */
3234 static void b43_qos_init(struct b43_wldev *dev)
3235 {
3236 /* Upload the current QOS parameters. */
3237 b43_qos_upload_all(dev);
3238
3239 /* Enable QOS support. */
3240 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_EDCF);
3241 b43_write16(dev, B43_MMIO_IFSCTL,
3242 b43_read16(dev, B43_MMIO_IFSCTL)
3243 | B43_MMIO_IFSCTL_USE_EDCF);
3244 }
3245
3246 static int b43_op_conf_tx(struct ieee80211_hw *hw, u16 _queue,
3247 const struct ieee80211_tx_queue_params *params)
3248 {
3249 struct b43_wl *wl = hw_to_b43_wl(hw);
3250 struct b43_wldev *dev;
3251 unsigned int queue = (unsigned int)_queue;
3252 int err = -ENODEV;
3253
3254 if (queue >= ARRAY_SIZE(wl->qos_params)) {
3255 /* Queue not available or don't support setting
3256 * params on this queue. Return success to not
3257 * confuse mac80211. */
3258 return 0;
3259 }
3260 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3261 ARRAY_SIZE(wl->qos_params));
3262
3263 mutex_lock(&wl->mutex);
3264 dev = wl->current_dev;
3265 if (unlikely(!dev || (b43_status(dev) < B43_STAT_INITIALIZED)))
3266 goto out_unlock;
3267
3268 memcpy(&(wl->qos_params[queue].p), params, sizeof(*params));
3269 b43_mac_suspend(dev);
3270 b43_qos_params_upload(dev, &(wl->qos_params[queue].p),
3271 b43_qos_shm_offsets[queue]);
3272 b43_mac_enable(dev);
3273 err = 0;
3274
3275 out_unlock:
3276 mutex_unlock(&wl->mutex);
3277
3278 return err;
3279 }
3280
3281 static int b43_op_get_tx_stats(struct ieee80211_hw *hw,
3282 struct ieee80211_tx_queue_stats *stats)
3283 {
3284 struct b43_wl *wl = hw_to_b43_wl(hw);
3285 struct b43_wldev *dev = wl->current_dev;
3286 unsigned long flags;
3287 int err = -ENODEV;
3288
3289 if (!dev)
3290 goto out;
3291 spin_lock_irqsave(&wl->irq_lock, flags);
3292 if (likely(b43_status(dev) >= B43_STAT_STARTED)) {
3293 if (b43_using_pio_transfers(dev))
3294 b43_pio_get_tx_stats(dev, stats);
3295 else
3296 b43_dma_get_tx_stats(dev, stats);
3297 err = 0;
3298 }
3299 spin_unlock_irqrestore(&wl->irq_lock, flags);
3300 out:
3301 return err;
3302 }
3303
3304 static int b43_op_get_stats(struct ieee80211_hw *hw,
3305 struct ieee80211_low_level_stats *stats)
3306 {
3307 struct b43_wl *wl = hw_to_b43_wl(hw);
3308 unsigned long flags;
3309
3310 spin_lock_irqsave(&wl->irq_lock, flags);
3311 memcpy(stats, &wl->ieee_stats, sizeof(*stats));
3312 spin_unlock_irqrestore(&wl->irq_lock, flags);
3313
3314 return 0;
3315 }
3316
3317 static u64 b43_op_get_tsf(struct ieee80211_hw *hw)
3318 {
3319 struct b43_wl *wl = hw_to_b43_wl(hw);
3320 struct b43_wldev *dev;
3321 u64 tsf;
3322
3323 mutex_lock(&wl->mutex);
3324 spin_lock_irq(&wl->irq_lock);
3325 dev = wl->current_dev;
3326
3327 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED))
3328 b43_tsf_read(dev, &tsf);
3329 else
3330 tsf = 0;
3331
3332 spin_unlock_irq(&wl->irq_lock);
3333 mutex_unlock(&wl->mutex);
3334
3335 return tsf;
3336 }
3337
3338 static void b43_op_set_tsf(struct ieee80211_hw *hw, u64 tsf)
3339 {
3340 struct b43_wl *wl = hw_to_b43_wl(hw);
3341 struct b43_wldev *dev;
3342
3343 mutex_lock(&wl->mutex);
3344 spin_lock_irq(&wl->irq_lock);
3345 dev = wl->current_dev;
3346
3347 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED))
3348 b43_tsf_write(dev, tsf);
3349
3350 spin_unlock_irq(&wl->irq_lock);
3351 mutex_unlock(&wl->mutex);
3352 }
3353
3354 static void b43_put_phy_into_reset(struct b43_wldev *dev)
3355 {
3356 struct ssb_device *sdev = dev->dev;
3357 u32 tmslow;
3358
3359 tmslow = ssb_read32(sdev, SSB_TMSLOW);
3360 tmslow &= ~B43_TMSLOW_GMODE;
3361 tmslow |= B43_TMSLOW_PHYRESET;
3362 tmslow |= SSB_TMSLOW_FGC;
3363 ssb_write32(sdev, SSB_TMSLOW, tmslow);
3364 msleep(1);
3365
3366 tmslow = ssb_read32(sdev, SSB_TMSLOW);
3367 tmslow &= ~SSB_TMSLOW_FGC;
3368 tmslow |= B43_TMSLOW_PHYRESET;
3369 ssb_write32(sdev, SSB_TMSLOW, tmslow);
3370 msleep(1);
3371 }
3372
3373 static const char *band_to_string(enum ieee80211_band band)
3374 {
3375 switch (band) {
3376 case IEEE80211_BAND_5GHZ:
3377 return "5";
3378 case IEEE80211_BAND_2GHZ:
3379 return "2.4";
3380 default:
3381 break;
3382 }
3383 B43_WARN_ON(1);
3384 return "";
3385 }
3386
3387 /* Expects wl->mutex locked */
3388 static int b43_switch_band(struct b43_wl *wl, struct ieee80211_channel *chan)
3389 {
3390 struct b43_wldev *up_dev = NULL;
3391 struct b43_wldev *down_dev;
3392 struct b43_wldev *d;
3393 int err;
3394 bool uninitialized_var(gmode);
3395 int prev_status;
3396
3397 /* Find a device and PHY which supports the band. */
3398 list_for_each_entry(d, &wl->devlist, list) {
3399 switch (chan->band) {
3400 case IEEE80211_BAND_5GHZ:
3401 if (d->phy.supports_5ghz) {
3402 up_dev = d;
3403 gmode = 0;
3404 }
3405 break;
3406 case IEEE80211_BAND_2GHZ:
3407 if (d->phy.supports_2ghz) {
3408 up_dev = d;
3409 gmode = 1;
3410 }
3411 break;
3412 default:
3413 B43_WARN_ON(1);
3414 return -EINVAL;
3415 }
3416 if (up_dev)
3417 break;
3418 }
3419 if (!up_dev) {
3420 b43err(wl, "Could not find a device for %s-GHz band operation\n",
3421 band_to_string(chan->band));
3422 return -ENODEV;
3423 }
3424 if ((up_dev == wl->current_dev) &&
3425 (!!wl->current_dev->phy.gmode == !!gmode)) {
3426 /* This device is already running. */
3427 return 0;
3428 }
3429 b43dbg(wl, "Switching to %s-GHz band\n",
3430 band_to_string(chan->band));
3431 down_dev = wl->current_dev;
3432
3433 prev_status = b43_status(down_dev);
3434 /* Shutdown the currently running core. */
3435 if (prev_status >= B43_STAT_STARTED)
3436 b43_wireless_core_stop(down_dev);
3437 if (prev_status >= B43_STAT_INITIALIZED)
3438 b43_wireless_core_exit(down_dev);
3439
3440 if (down_dev != up_dev) {
3441 /* We switch to a different core, so we put PHY into
3442 * RESET on the old core. */
3443 b43_put_phy_into_reset(down_dev);
3444 }
3445
3446 /* Now start the new core. */
3447 up_dev->phy.gmode = gmode;
3448 if (prev_status >= B43_STAT_INITIALIZED) {
3449 err = b43_wireless_core_init(up_dev);
3450 if (err) {
3451 b43err(wl, "Fatal: Could not initialize device for "
3452 "selected %s-GHz band\n",
3453 band_to_string(chan->band));
3454 goto init_failure;
3455 }
3456 }
3457 if (prev_status >= B43_STAT_STARTED) {
3458 err = b43_wireless_core_start(up_dev);
3459 if (err) {
3460 b43err(wl, "Fatal: Coult not start device for "
3461 "selected %s-GHz band\n",
3462 band_to_string(chan->band));
3463 b43_wireless_core_exit(up_dev);
3464 goto init_failure;
3465 }
3466 }
3467 B43_WARN_ON(b43_status(up_dev) != prev_status);
3468
3469 wl->current_dev = up_dev;
3470
3471 return 0;
3472 init_failure:
3473 /* Whoops, failed to init the new core. No core is operating now. */
3474 wl->current_dev = NULL;
3475 return err;
3476 }
3477
3478 /* Write the short and long frame retry limit values. */
3479 static void b43_set_retry_limits(struct b43_wldev *dev,
3480 unsigned int short_retry,
3481 unsigned int long_retry)
3482 {
3483 /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing
3484 * the chip-internal counter. */
3485 short_retry = min(short_retry, (unsigned int)0xF);
3486 long_retry = min(long_retry, (unsigned int)0xF);
3487
3488 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_SRLIMIT,
3489 short_retry);
3490 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_LRLIMIT,
3491 long_retry);
3492 }
3493
3494 static int b43_op_config(struct ieee80211_hw *hw, u32 changed)
3495 {
3496 struct b43_wl *wl = hw_to_b43_wl(hw);
3497 struct b43_wldev *dev;
3498 struct b43_phy *phy;
3499 struct ieee80211_conf *conf = &hw->conf;
3500 unsigned long flags;
3501 int antenna;
3502 int err = 0;
3503
3504 mutex_lock(&wl->mutex);
3505
3506 /* Switch the band (if necessary). This might change the active core. */
3507 err = b43_switch_band(wl, conf->channel);
3508 if (err)
3509 goto out_unlock_mutex;
3510 dev = wl->current_dev;
3511 phy = &dev->phy;
3512
3513 b43_mac_suspend(dev);
3514
3515 if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
3516 b43_set_retry_limits(dev, conf->short_frame_max_tx_count,
3517 conf->long_frame_max_tx_count);
3518 changed &= ~IEEE80211_CONF_CHANGE_RETRY_LIMITS;
3519 if (!changed)
3520 goto out_mac_enable;
3521
3522 /* Switch to the requested channel.
3523 * The firmware takes care of races with the TX handler. */
3524 if (conf->channel->hw_value != phy->channel)
3525 b43_switch_channel(dev, conf->channel->hw_value);
3526
3527 dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_RADIOTAP);
3528
3529 /* Adjust the desired TX power level. */
3530 if (conf->power_level != 0) {
3531 spin_lock_irqsave(&wl->irq_lock, flags);
3532 if (conf->power_level != phy->desired_txpower) {
3533 phy->desired_txpower = conf->power_level;
3534 b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME |
3535 B43_TXPWR_IGNORE_TSSI);
3536 }
3537 spin_unlock_irqrestore(&wl->irq_lock, flags);
3538 }
3539
3540 /* Antennas for RX and management frame TX. */
3541 antenna = B43_ANTENNA_DEFAULT;
3542 b43_mgmtframe_txantenna(dev, antenna);
3543 antenna = B43_ANTENNA_DEFAULT;
3544 if (phy->ops->set_rx_antenna)
3545 phy->ops->set_rx_antenna(dev, antenna);
3546
3547 if (wl->radio_enabled != phy->radio_on) {
3548 if (wl->radio_enabled) {
3549 b43_software_rfkill(dev, false);
3550 b43info(dev->wl, "Radio turned on by software\n");
3551 if (!dev->radio_hw_enable) {
3552 b43info(dev->wl, "The hardware RF-kill button "
3553 "still turns the radio physically off. "
3554 "Press the button to turn it on.\n");
3555 }
3556 } else {
3557 b43_software_rfkill(dev, true);
3558 b43info(dev->wl, "Radio turned off by software\n");
3559 }
3560 }
3561
3562 out_mac_enable:
3563 b43_mac_enable(dev);
3564 out_unlock_mutex:
3565 mutex_unlock(&wl->mutex);
3566
3567 return err;
3568 }
3569
3570 static void b43_update_basic_rates(struct b43_wldev *dev, u32 brates)
3571 {
3572 struct ieee80211_supported_band *sband =
3573 dev->wl->hw->wiphy->bands[b43_current_band(dev->wl)];
3574 struct ieee80211_rate *rate;
3575 int i;
3576 u16 basic, direct, offset, basic_offset, rateptr;
3577
3578 for (i = 0; i < sband->n_bitrates; i++) {
3579 rate = &sband->bitrates[i];
3580
3581 if (b43_is_cck_rate(rate->hw_value)) {
3582 direct = B43_SHM_SH_CCKDIRECT;
3583 basic = B43_SHM_SH_CCKBASIC;
3584 offset = b43_plcp_get_ratecode_cck(rate->hw_value);
3585 offset &= 0xF;
3586 } else {
3587 direct = B43_SHM_SH_OFDMDIRECT;
3588 basic = B43_SHM_SH_OFDMBASIC;
3589 offset = b43_plcp_get_ratecode_ofdm(rate->hw_value);
3590 offset &= 0xF;
3591 }
3592
3593 rate = ieee80211_get_response_rate(sband, brates, rate->bitrate);
3594
3595 if (b43_is_cck_rate(rate->hw_value)) {
3596 basic_offset = b43_plcp_get_ratecode_cck(rate->hw_value);
3597 basic_offset &= 0xF;
3598 } else {
3599 basic_offset = b43_plcp_get_ratecode_ofdm(rate->hw_value);
3600 basic_offset &= 0xF;
3601 }
3602
3603 /*
3604 * Get the pointer that we need to point to
3605 * from the direct map
3606 */
3607 rateptr = b43_shm_read16(dev, B43_SHM_SHARED,
3608 direct + 2 * basic_offset);
3609 /* and write it to the basic map */
3610 b43_shm_write16(dev, B43_SHM_SHARED, basic + 2 * offset,
3611 rateptr);
3612 }
3613 }
3614
3615 static void b43_op_bss_info_changed(struct ieee80211_hw *hw,
3616 struct ieee80211_vif *vif,
3617 struct ieee80211_bss_conf *conf,
3618 u32 changed)
3619 {
3620 struct b43_wl *wl = hw_to_b43_wl(hw);
3621 struct b43_wldev *dev;
3622 unsigned long flags;
3623
3624 mutex_lock(&wl->mutex);
3625
3626 dev = wl->current_dev;
3627 if (!dev || b43_status(dev) < B43_STAT_STARTED)
3628 goto out_unlock_mutex;
3629
3630 B43_WARN_ON(wl->vif != vif);
3631
3632 spin_lock_irqsave(&wl->irq_lock, flags);
3633 if (changed & BSS_CHANGED_BSSID) {
3634 if (conf->bssid)
3635 memcpy(wl->bssid, conf->bssid, ETH_ALEN);
3636 else
3637 memset(wl->bssid, 0, ETH_ALEN);
3638 }
3639
3640 if (b43_status(dev) >= B43_STAT_INITIALIZED) {
3641 if (changed & BSS_CHANGED_BEACON &&
3642 (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
3643 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) ||
3644 b43_is_mode(wl, NL80211_IFTYPE_ADHOC)))
3645 b43_update_templates(wl);
3646
3647 if (changed & BSS_CHANGED_BSSID)
3648 b43_write_mac_bssid_templates(dev);
3649 }
3650 spin_unlock_irqrestore(&wl->irq_lock, flags);
3651
3652 b43_mac_suspend(dev);
3653
3654 /* Update templates for AP/mesh mode. */
3655 if (changed & BSS_CHANGED_BEACON_INT &&
3656 (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
3657 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) ||
3658 b43_is_mode(wl, NL80211_IFTYPE_ADHOC)))
3659 b43_set_beacon_int(dev, conf->beacon_int);
3660
3661 if (changed & BSS_CHANGED_BASIC_RATES)
3662 b43_update_basic_rates(dev, conf->basic_rates);
3663
3664 if (changed & BSS_CHANGED_ERP_SLOT) {
3665 if (conf->use_short_slot)
3666 b43_short_slot_timing_enable(dev);
3667 else
3668 b43_short_slot_timing_disable(dev);
3669 }
3670
3671 b43_mac_enable(dev);
3672 out_unlock_mutex:
3673 mutex_unlock(&wl->mutex);
3674 }
3675
3676 static int b43_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
3677 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
3678 struct ieee80211_key_conf *key)
3679 {
3680 struct b43_wl *wl = hw_to_b43_wl(hw);
3681 struct b43_wldev *dev;
3682 u8 algorithm;
3683 u8 index;
3684 int err;
3685 static const u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
3686
3687 if (modparam_nohwcrypt)
3688 return -ENOSPC; /* User disabled HW-crypto */
3689
3690 mutex_lock(&wl->mutex);
3691 spin_lock_irq(&wl->irq_lock);
3692 write_lock(&wl->tx_lock);
3693 /* Why do we need all this locking here?
3694 * mutex -> Every config operation must take it.
3695 * irq_lock -> We modify the dev->key array, which is accessed
3696 * in the IRQ handlers.
3697 * tx_lock -> We modify the dev->key array, which is accessed
3698 * in the TX handler.
3699 */
3700
3701 dev = wl->current_dev;
3702 err = -ENODEV;
3703 if (!dev || b43_status(dev) < B43_STAT_INITIALIZED)
3704 goto out_unlock;
3705
3706 if (dev->fw.pcm_request_failed || !dev->hwcrypto_enabled) {
3707 /* We don't have firmware for the crypto engine.
3708 * Must use software-crypto. */
3709 err = -EOPNOTSUPP;
3710 goto out_unlock;
3711 }
3712
3713 err = -EINVAL;
3714 switch (key->alg) {
3715 case ALG_WEP:
3716 if (key->keylen == WLAN_KEY_LEN_WEP40)
3717 algorithm = B43_SEC_ALGO_WEP40;
3718 else
3719 algorithm = B43_SEC_ALGO_WEP104;
3720 break;
3721 case ALG_TKIP:
3722 algorithm = B43_SEC_ALGO_TKIP;
3723 break;
3724 case ALG_CCMP:
3725 algorithm = B43_SEC_ALGO_AES;
3726 break;
3727 default:
3728 B43_WARN_ON(1);
3729 goto out_unlock;
3730 }
3731 index = (u8) (key->keyidx);
3732 if (index > 3)
3733 goto out_unlock;
3734
3735 switch (cmd) {
3736 case SET_KEY:
3737 if (algorithm == B43_SEC_ALGO_TKIP &&
3738 (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE) ||
3739 !modparam_hwtkip)) {
3740 /* We support only pairwise key */
3741 err = -EOPNOTSUPP;
3742 goto out_unlock;
3743 }
3744
3745 if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) {
3746 if (WARN_ON(!sta)) {
3747 err = -EOPNOTSUPP;
3748 goto out_unlock;
3749 }
3750 /* Pairwise key with an assigned MAC address. */
3751 err = b43_key_write(dev, -1, algorithm,
3752 key->key, key->keylen,
3753 sta->addr, key);
3754 } else {
3755 /* Group key */
3756 err = b43_key_write(dev, index, algorithm,
3757 key->key, key->keylen, NULL, key);
3758 }
3759 if (err)
3760 goto out_unlock;
3761
3762 if (algorithm == B43_SEC_ALGO_WEP40 ||
3763 algorithm == B43_SEC_ALGO_WEP104) {
3764 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_USEDEFKEYS);
3765 } else {
3766 b43_hf_write(dev,
3767 b43_hf_read(dev) & ~B43_HF_USEDEFKEYS);
3768 }
3769 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
3770 if (algorithm == B43_SEC_ALGO_TKIP)
3771 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
3772 break;
3773 case DISABLE_KEY: {
3774 err = b43_key_clear(dev, key->hw_key_idx);
3775 if (err)
3776 goto out_unlock;
3777 break;
3778 }
3779 default:
3780 B43_WARN_ON(1);
3781 }
3782
3783 out_unlock:
3784 if (!err) {
3785 b43dbg(wl, "%s hardware based encryption for keyidx: %d, "
3786 "mac: %pM\n",
3787 cmd == SET_KEY ? "Using" : "Disabling", key->keyidx,
3788 sta ? sta->addr : bcast_addr);
3789 b43_dump_keymemory(dev);
3790 }
3791 write_unlock(&wl->tx_lock);
3792 spin_unlock_irq(&wl->irq_lock);
3793 mutex_unlock(&wl->mutex);
3794
3795 return err;
3796 }
3797
3798 static void b43_op_configure_filter(struct ieee80211_hw *hw,
3799 unsigned int changed, unsigned int *fflags,
3800 u64 multicast)
3801 {
3802 struct b43_wl *wl = hw_to_b43_wl(hw);
3803 struct b43_wldev *dev = wl->current_dev;
3804 unsigned long flags;
3805
3806 if (!dev) {
3807 *fflags = 0;
3808 return;
3809 }
3810
3811 spin_lock_irqsave(&wl->irq_lock, flags);
3812 *fflags &= FIF_PROMISC_IN_BSS |
3813 FIF_ALLMULTI |
3814 FIF_FCSFAIL |
3815 FIF_PLCPFAIL |
3816 FIF_CONTROL |
3817 FIF_OTHER_BSS |
3818 FIF_BCN_PRBRESP_PROMISC;
3819
3820 changed &= FIF_PROMISC_IN_BSS |
3821 FIF_ALLMULTI |
3822 FIF_FCSFAIL |
3823 FIF_PLCPFAIL |
3824 FIF_CONTROL |
3825 FIF_OTHER_BSS |
3826 FIF_BCN_PRBRESP_PROMISC;
3827
3828 wl->filter_flags = *fflags;
3829
3830 if (changed && b43_status(dev) >= B43_STAT_INITIALIZED)
3831 b43_adjust_opmode(dev);
3832 spin_unlock_irqrestore(&wl->irq_lock, flags);
3833 }
3834
3835 /* Locking: wl->mutex */
3836 static void b43_wireless_core_stop(struct b43_wldev *dev)
3837 {
3838 struct b43_wl *wl = dev->wl;
3839 unsigned long flags;
3840
3841 if (b43_status(dev) < B43_STAT_STARTED)
3842 return;
3843
3844 /* Disable and sync interrupts. We must do this before than
3845 * setting the status to INITIALIZED, as the interrupt handler
3846 * won't care about IRQs then. */
3847 spin_lock_irqsave(&wl->irq_lock, flags);
3848 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
3849 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* flush */
3850 spin_unlock_irqrestore(&wl->irq_lock, flags);
3851 b43_synchronize_irq(dev);
3852
3853 write_lock_irqsave(&wl->tx_lock, flags);
3854 b43_set_status(dev, B43_STAT_INITIALIZED);
3855 write_unlock_irqrestore(&wl->tx_lock, flags);
3856
3857 b43_pio_stop(dev);
3858 mutex_unlock(&wl->mutex);
3859 /* Must unlock as it would otherwise deadlock. No races here.
3860 * Cancel the possibly running self-rearming periodic work. */
3861 cancel_delayed_work_sync(&dev->periodic_work);
3862 mutex_lock(&wl->mutex);
3863
3864 b43_mac_suspend(dev);
3865 free_irq(dev->dev->irq, dev);
3866 b43dbg(wl, "Wireless interface stopped\n");
3867 }
3868
3869 /* Locking: wl->mutex */
3870 static int b43_wireless_core_start(struct b43_wldev *dev)
3871 {
3872 int err;
3873
3874 B43_WARN_ON(b43_status(dev) != B43_STAT_INITIALIZED);
3875
3876 drain_txstatus_queue(dev);
3877 err = request_irq(dev->dev->irq, b43_interrupt_handler,
3878 IRQF_SHARED, KBUILD_MODNAME, dev);
3879 if (err) {
3880 b43err(dev->wl, "Cannot request IRQ-%d\n", dev->dev->irq);
3881 goto out;
3882 }
3883
3884 /* We are ready to run. */
3885 b43_set_status(dev, B43_STAT_STARTED);
3886
3887 /* Start data flow (TX/RX). */
3888 b43_mac_enable(dev);
3889 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
3890
3891 /* Start maintainance work */
3892 b43_periodic_tasks_setup(dev);
3893
3894 b43dbg(dev->wl, "Wireless interface started\n");
3895 out:
3896 return err;
3897 }
3898
3899 /* Get PHY and RADIO versioning numbers */
3900 static int b43_phy_versioning(struct b43_wldev *dev)
3901 {
3902 struct b43_phy *phy = &dev->phy;
3903 u32 tmp;
3904 u8 analog_type;
3905 u8 phy_type;
3906 u8 phy_rev;
3907 u16 radio_manuf;
3908 u16 radio_ver;
3909 u16 radio_rev;
3910 int unsupported = 0;
3911
3912 /* Get PHY versioning */
3913 tmp = b43_read16(dev, B43_MMIO_PHY_VER);
3914 analog_type = (tmp & B43_PHYVER_ANALOG) >> B43_PHYVER_ANALOG_SHIFT;
3915 phy_type = (tmp & B43_PHYVER_TYPE) >> B43_PHYVER_TYPE_SHIFT;
3916 phy_rev = (tmp & B43_PHYVER_VERSION);
3917 switch (phy_type) {
3918 case B43_PHYTYPE_A:
3919 if (phy_rev >= 4)
3920 unsupported = 1;
3921 break;
3922 case B43_PHYTYPE_B:
3923 if (phy_rev != 2 && phy_rev != 4 && phy_rev != 6
3924 && phy_rev != 7)
3925 unsupported = 1;
3926 break;
3927 case B43_PHYTYPE_G:
3928 if (phy_rev > 9)
3929 unsupported = 1;
3930 break;
3931 #ifdef CONFIG_B43_NPHY
3932 case B43_PHYTYPE_N:
3933 if (phy_rev > 4)
3934 unsupported = 1;
3935 break;
3936 #endif
3937 #ifdef CONFIG_B43_PHY_LP
3938 case B43_PHYTYPE_LP:
3939 if (phy_rev > 2)
3940 unsupported = 1;
3941 break;
3942 #endif
3943 default:
3944 unsupported = 1;
3945 };
3946 if (unsupported) {
3947 b43err(dev->wl, "FOUND UNSUPPORTED PHY "
3948 "(Analog %u, Type %u, Revision %u)\n",
3949 analog_type, phy_type, phy_rev);
3950 return -EOPNOTSUPP;
3951 }
3952 b43dbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n",
3953 analog_type, phy_type, phy_rev);
3954
3955 /* Get RADIO versioning */
3956 if (dev->dev->bus->chip_id == 0x4317) {
3957 if (dev->dev->bus->chip_rev == 0)
3958 tmp = 0x3205017F;
3959 else if (dev->dev->bus->chip_rev == 1)
3960 tmp = 0x4205017F;
3961 else
3962 tmp = 0x5205017F;
3963 } else {
3964 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
3965 tmp = b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
3966 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
3967 tmp |= (u32)b43_read16(dev, B43_MMIO_RADIO_DATA_HIGH) << 16;
3968 }
3969 radio_manuf = (tmp & 0x00000FFF);
3970 radio_ver = (tmp & 0x0FFFF000) >> 12;
3971 radio_rev = (tmp & 0xF0000000) >> 28;
3972 if (radio_manuf != 0x17F /* Broadcom */)
3973 unsupported = 1;
3974 switch (phy_type) {
3975 case B43_PHYTYPE_A:
3976 if (radio_ver != 0x2060)
3977 unsupported = 1;
3978 if (radio_rev != 1)
3979 unsupported = 1;
3980 if (radio_manuf != 0x17F)
3981 unsupported = 1;
3982 break;
3983 case B43_PHYTYPE_B:
3984 if ((radio_ver & 0xFFF0) != 0x2050)
3985 unsupported = 1;
3986 break;
3987 case B43_PHYTYPE_G:
3988 if (radio_ver != 0x2050)
3989 unsupported = 1;
3990 break;
3991 case B43_PHYTYPE_N:
3992 if (radio_ver != 0x2055 && radio_ver != 0x2056)
3993 unsupported = 1;
3994 break;
3995 case B43_PHYTYPE_LP:
3996 if (radio_ver != 0x2062 && radio_ver != 0x2063)
3997 unsupported = 1;
3998 break;
3999 default:
4000 B43_WARN_ON(1);
4001 }
4002 if (unsupported) {
4003 b43err(dev->wl, "FOUND UNSUPPORTED RADIO "
4004 "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
4005 radio_manuf, radio_ver, radio_rev);
4006 return -EOPNOTSUPP;
4007 }
4008 b43dbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X, Revision %u\n",
4009 radio_manuf, radio_ver, radio_rev);
4010
4011 phy->radio_manuf = radio_manuf;
4012 phy->radio_ver = radio_ver;
4013 phy->radio_rev = radio_rev;
4014
4015 phy->analog = analog_type;
4016 phy->type = phy_type;
4017 phy->rev = phy_rev;
4018
4019 return 0;
4020 }
4021
4022 static void setup_struct_phy_for_init(struct b43_wldev *dev,
4023 struct b43_phy *phy)
4024 {
4025 phy->hardware_power_control = !!modparam_hwpctl;
4026 phy->next_txpwr_check_time = jiffies;
4027 /* PHY TX errors counter. */
4028 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
4029
4030 #if B43_DEBUG
4031 phy->phy_locked = 0;
4032 phy->radio_locked = 0;
4033 #endif
4034 }
4035
4036 static void setup_struct_wldev_for_init(struct b43_wldev *dev)
4037 {
4038 dev->dfq_valid = 0;
4039
4040 /* Assume the radio is enabled. If it's not enabled, the state will
4041 * immediately get fixed on the first periodic work run. */
4042 dev->radio_hw_enable = 1;
4043
4044 /* Stats */
4045 memset(&dev->stats, 0, sizeof(dev->stats));
4046
4047 setup_struct_phy_for_init(dev, &dev->phy);
4048
4049 /* IRQ related flags */
4050 dev->irq_reason = 0;
4051 memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
4052 dev->irq_mask = B43_IRQ_MASKTEMPLATE;
4053 if (b43_modparam_verbose < B43_VERBOSITY_DEBUG)
4054 dev->irq_mask &= ~B43_IRQ_PHY_TXERR;
4055
4056 dev->mac_suspended = 1;
4057
4058 /* Noise calculation context */
4059 memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
4060 }
4061
4062 static void b43_bluetooth_coext_enable(struct b43_wldev *dev)
4063 {
4064 struct ssb_sprom *sprom = &dev->dev->bus->sprom;
4065 u64 hf;
4066
4067 if (!modparam_btcoex)
4068 return;
4069 if (!(sprom->boardflags_lo & B43_BFL_BTCOEXIST))
4070 return;
4071 if (dev->phy.type != B43_PHYTYPE_B && !dev->phy.gmode)
4072 return;
4073
4074 hf = b43_hf_read(dev);
4075 if (sprom->boardflags_lo & B43_BFL_BTCMOD)
4076 hf |= B43_HF_BTCOEXALT;
4077 else
4078 hf |= B43_HF_BTCOEX;
4079 b43_hf_write(dev, hf);
4080 }
4081
4082 static void b43_bluetooth_coext_disable(struct b43_wldev *dev)
4083 {
4084 if (!modparam_btcoex)
4085 return;
4086 //TODO
4087 }
4088
4089 static void b43_imcfglo_timeouts_workaround(struct b43_wldev *dev)
4090 {
4091 #ifdef CONFIG_SSB_DRIVER_PCICORE
4092 struct ssb_bus *bus = dev->dev->bus;
4093 u32 tmp;
4094
4095 if (bus->pcicore.dev &&
4096 bus->pcicore.dev->id.coreid == SSB_DEV_PCI &&
4097 bus->pcicore.dev->id.revision <= 5) {
4098 /* IMCFGLO timeouts workaround. */
4099 tmp = ssb_read32(dev->dev, SSB_IMCFGLO);
4100 tmp &= ~SSB_IMCFGLO_REQTO;
4101 tmp &= ~SSB_IMCFGLO_SERTO;
4102 switch (bus->bustype) {
4103 case SSB_BUSTYPE_PCI:
4104 case SSB_BUSTYPE_PCMCIA:
4105 tmp |= 0x32;
4106 break;
4107 case SSB_BUSTYPE_SSB:
4108 tmp |= 0x53;
4109 break;
4110 }
4111 ssb_write32(dev->dev, SSB_IMCFGLO, tmp);
4112 }
4113 #endif /* CONFIG_SSB_DRIVER_PCICORE */
4114 }
4115
4116 static void b43_set_synth_pu_delay(struct b43_wldev *dev, bool idle)
4117 {
4118 u16 pu_delay;
4119
4120 /* The time value is in microseconds. */
4121 if (dev->phy.type == B43_PHYTYPE_A)
4122 pu_delay = 3700;
4123 else
4124 pu_delay = 1050;
4125 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC) || idle)
4126 pu_delay = 500;
4127 if ((dev->phy.radio_ver == 0x2050) && (dev->phy.radio_rev == 8))
4128 pu_delay = max(pu_delay, (u16)2400);
4129
4130 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SPUWKUP, pu_delay);
4131 }
4132
4133 /* Set the TSF CFP pre-TargetBeaconTransmissionTime. */
4134 static void b43_set_pretbtt(struct b43_wldev *dev)
4135 {
4136 u16 pretbtt;
4137
4138 /* The time value is in microseconds. */
4139 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC)) {
4140 pretbtt = 2;
4141 } else {
4142 if (dev->phy.type == B43_PHYTYPE_A)
4143 pretbtt = 120;
4144 else
4145 pretbtt = 250;
4146 }
4147 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRETBTT, pretbtt);
4148 b43_write16(dev, B43_MMIO_TSF_CFP_PRETBTT, pretbtt);
4149 }
4150
4151 /* Shutdown a wireless core */
4152 /* Locking: wl->mutex */
4153 static void b43_wireless_core_exit(struct b43_wldev *dev)
4154 {
4155 u32 macctl;
4156
4157 B43_WARN_ON(b43_status(dev) > B43_STAT_INITIALIZED);
4158 if (b43_status(dev) != B43_STAT_INITIALIZED)
4159 return;
4160 b43_set_status(dev, B43_STAT_UNINIT);
4161
4162 /* Stop the microcode PSM. */
4163 macctl = b43_read32(dev, B43_MMIO_MACCTL);
4164 macctl &= ~B43_MACCTL_PSM_RUN;
4165 macctl |= B43_MACCTL_PSM_JMP0;
4166 b43_write32(dev, B43_MMIO_MACCTL, macctl);
4167
4168 if (!dev->suspend_in_progress) {
4169 b43_leds_exit(dev);
4170 b43_rng_exit(dev->wl);
4171 }
4172 b43_dma_free(dev);
4173 b43_pio_free(dev);
4174 b43_chip_exit(dev);
4175 dev->phy.ops->switch_analog(dev, 0);
4176 if (dev->wl->current_beacon) {
4177 dev_kfree_skb_any(dev->wl->current_beacon);
4178 dev->wl->current_beacon = NULL;
4179 }
4180
4181 ssb_device_disable(dev->dev, 0);
4182 ssb_bus_may_powerdown(dev->dev->bus);
4183 }
4184
4185 /* Initialize a wireless core */
4186 static int b43_wireless_core_init(struct b43_wldev *dev)
4187 {
4188 struct b43_wl *wl = dev->wl;
4189 struct ssb_bus *bus = dev->dev->bus;
4190 struct ssb_sprom *sprom = &bus->sprom;
4191 struct b43_phy *phy = &dev->phy;
4192 int err;
4193 u64 hf;
4194 u32 tmp;
4195
4196 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
4197
4198 err = ssb_bus_powerup(bus, 0);
4199 if (err)
4200 goto out;
4201 if (!ssb_device_is_enabled(dev->dev)) {
4202 tmp = phy->gmode ? B43_TMSLOW_GMODE : 0;
4203 b43_wireless_core_reset(dev, tmp);
4204 }
4205
4206 /* Reset all data structures. */
4207 setup_struct_wldev_for_init(dev);
4208 phy->ops->prepare_structs(dev);
4209
4210 /* Enable IRQ routing to this device. */
4211 ssb_pcicore_dev_irqvecs_enable(&bus->pcicore, dev->dev);
4212
4213 b43_imcfglo_timeouts_workaround(dev);
4214 b43_bluetooth_coext_disable(dev);
4215 if (phy->ops->prepare_hardware) {
4216 err = phy->ops->prepare_hardware(dev);
4217 if (err)
4218 goto err_busdown;
4219 }
4220 err = b43_chip_init(dev);
4221 if (err)
4222 goto err_busdown;
4223 b43_shm_write16(dev, B43_SHM_SHARED,
4224 B43_SHM_SH_WLCOREREV, dev->dev->id.revision);
4225 hf = b43_hf_read(dev);
4226 if (phy->type == B43_PHYTYPE_G) {
4227 hf |= B43_HF_SYMW;
4228 if (phy->rev == 1)
4229 hf |= B43_HF_GDCW;
4230 if (sprom->boardflags_lo & B43_BFL_PACTRL)
4231 hf |= B43_HF_OFDMPABOOST;
4232 }
4233 if (phy->radio_ver == 0x2050) {
4234 if (phy->radio_rev == 6)
4235 hf |= B43_HF_4318TSSI;
4236 if (phy->radio_rev < 6)
4237 hf |= B43_HF_VCORECALC;
4238 }
4239 if (sprom->boardflags_lo & B43_BFL_XTAL_NOSLOW)
4240 hf |= B43_HF_DSCRQ; /* Disable slowclock requests from ucode. */
4241 #ifdef CONFIG_SSB_DRIVER_PCICORE
4242 if ((bus->bustype == SSB_BUSTYPE_PCI) &&
4243 (bus->pcicore.dev->id.revision <= 10))
4244 hf |= B43_HF_PCISCW; /* PCI slow clock workaround. */
4245 #endif
4246 hf &= ~B43_HF_SKCFPUP;
4247 b43_hf_write(dev, hf);
4248
4249 b43_set_retry_limits(dev, B43_DEFAULT_SHORT_RETRY_LIMIT,
4250 B43_DEFAULT_LONG_RETRY_LIMIT);
4251 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SFFBLIM, 3);
4252 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_LFFBLIM, 2);
4253
4254 /* Disable sending probe responses from firmware.
4255 * Setting the MaxTime to one usec will always trigger
4256 * a timeout, so we never send any probe resp.
4257 * A timeout of zero is infinite. */
4258 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 1);
4259
4260 b43_rate_memory_init(dev);
4261 b43_set_phytxctl_defaults(dev);
4262
4263 /* Minimum Contention Window */
4264 if (phy->type == B43_PHYTYPE_B) {
4265 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0x1F);
4266 } else {
4267 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0xF);
4268 }
4269 /* Maximum Contention Window */
4270 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MAXCONT, 0x3FF);
4271
4272 if ((dev->dev->bus->bustype == SSB_BUSTYPE_PCMCIA) || B43_FORCE_PIO) {
4273 dev->__using_pio_transfers = 1;
4274 err = b43_pio_init(dev);
4275 } else {
4276 dev->__using_pio_transfers = 0;
4277 err = b43_dma_init(dev);
4278 }
4279 if (err)
4280 goto err_chip_exit;
4281 b43_qos_init(dev);
4282 b43_set_synth_pu_delay(dev, 1);
4283 b43_bluetooth_coext_enable(dev);
4284
4285 ssb_bus_powerup(bus, !(sprom->boardflags_lo & B43_BFL_XTAL_NOSLOW));
4286 b43_upload_card_macaddress(dev);
4287 b43_security_init(dev);
4288 if (!dev->suspend_in_progress)
4289 b43_rng_init(wl);
4290
4291 b43_set_status(dev, B43_STAT_INITIALIZED);
4292
4293 if (!dev->suspend_in_progress)
4294 b43_leds_init(dev);
4295 out:
4296 return err;
4297
4298 err_chip_exit:
4299 b43_chip_exit(dev);
4300 err_busdown:
4301 ssb_bus_may_powerdown(bus);
4302 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
4303 return err;
4304 }
4305
4306 static int b43_op_add_interface(struct ieee80211_hw *hw,
4307 struct ieee80211_if_init_conf *conf)
4308 {
4309 struct b43_wl *wl = hw_to_b43_wl(hw);
4310 struct b43_wldev *dev;
4311 unsigned long flags;
4312 int err = -EOPNOTSUPP;
4313
4314 /* TODO: allow WDS/AP devices to coexist */
4315
4316 if (conf->type != NL80211_IFTYPE_AP &&
4317 conf->type != NL80211_IFTYPE_MESH_POINT &&
4318 conf->type != NL80211_IFTYPE_STATION &&
4319 conf->type != NL80211_IFTYPE_WDS &&
4320 conf->type != NL80211_IFTYPE_ADHOC)
4321 return -EOPNOTSUPP;
4322
4323 mutex_lock(&wl->mutex);
4324 if (wl->operating)
4325 goto out_mutex_unlock;
4326
4327 b43dbg(wl, "Adding Interface type %d\n", conf->type);
4328
4329 dev = wl->current_dev;
4330 wl->operating = 1;
4331 wl->vif = conf->vif;
4332 wl->if_type = conf->type;
4333 memcpy(wl->mac_addr, conf->mac_addr, ETH_ALEN);
4334
4335 spin_lock_irqsave(&wl->irq_lock, flags);
4336 b43_adjust_opmode(dev);
4337 b43_set_pretbtt(dev);
4338 b43_set_synth_pu_delay(dev, 0);
4339 b43_upload_card_macaddress(dev);
4340 spin_unlock_irqrestore(&wl->irq_lock, flags);
4341
4342 err = 0;
4343 out_mutex_unlock:
4344 mutex_unlock(&wl->mutex);
4345
4346 return err;
4347 }
4348
4349 static void b43_op_remove_interface(struct ieee80211_hw *hw,
4350 struct ieee80211_if_init_conf *conf)
4351 {
4352 struct b43_wl *wl = hw_to_b43_wl(hw);
4353 struct b43_wldev *dev = wl->current_dev;
4354 unsigned long flags;
4355
4356 b43dbg(wl, "Removing Interface type %d\n", conf->type);
4357
4358 mutex_lock(&wl->mutex);
4359
4360 B43_WARN_ON(!wl->operating);
4361 B43_WARN_ON(wl->vif != conf->vif);
4362 wl->vif = NULL;
4363
4364 wl->operating = 0;
4365
4366 spin_lock_irqsave(&wl->irq_lock, flags);
4367 b43_adjust_opmode(dev);
4368 memset(wl->mac_addr, 0, ETH_ALEN);
4369 b43_upload_card_macaddress(dev);
4370 spin_unlock_irqrestore(&wl->irq_lock, flags);
4371
4372 mutex_unlock(&wl->mutex);
4373 }
4374
4375 static int b43_op_start(struct ieee80211_hw *hw)
4376 {
4377 struct b43_wl *wl = hw_to_b43_wl(hw);
4378 struct b43_wldev *dev = wl->current_dev;
4379 int did_init = 0;
4380 int err = 0;
4381
4382 /* Kill all old instance specific information to make sure
4383 * the card won't use it in the short timeframe between start
4384 * and mac80211 reconfiguring it. */
4385 memset(wl->bssid, 0, ETH_ALEN);
4386 memset(wl->mac_addr, 0, ETH_ALEN);
4387 wl->filter_flags = 0;
4388 wl->radiotap_enabled = 0;
4389 b43_qos_clear(wl);
4390 wl->beacon0_uploaded = 0;
4391 wl->beacon1_uploaded = 0;
4392 wl->beacon_templates_virgin = 1;
4393 wl->radio_enabled = 1;
4394
4395 mutex_lock(&wl->mutex);
4396
4397 if (b43_status(dev) < B43_STAT_INITIALIZED) {
4398 err = b43_wireless_core_init(dev);
4399 if (err)
4400 goto out_mutex_unlock;
4401 did_init = 1;
4402 }
4403
4404 if (b43_status(dev) < B43_STAT_STARTED) {
4405 err = b43_wireless_core_start(dev);
4406 if (err) {
4407 if (did_init)
4408 b43_wireless_core_exit(dev);
4409 goto out_mutex_unlock;
4410 }
4411 }
4412
4413 /* XXX: only do if device doesn't support rfkill irq */
4414 wiphy_rfkill_start_polling(hw->wiphy);
4415
4416 out_mutex_unlock:
4417 mutex_unlock(&wl->mutex);
4418
4419 return err;
4420 }
4421
4422 static void b43_op_stop(struct ieee80211_hw *hw)
4423 {
4424 struct b43_wl *wl = hw_to_b43_wl(hw);
4425 struct b43_wldev *dev = wl->current_dev;
4426
4427 cancel_work_sync(&(wl->beacon_update_trigger));
4428
4429 mutex_lock(&wl->mutex);
4430 if (b43_status(dev) >= B43_STAT_STARTED)
4431 b43_wireless_core_stop(dev);
4432 b43_wireless_core_exit(dev);
4433 wl->radio_enabled = 0;
4434 mutex_unlock(&wl->mutex);
4435
4436 cancel_work_sync(&(wl->txpower_adjust_work));
4437 }
4438
4439 static int b43_op_beacon_set_tim(struct ieee80211_hw *hw,
4440 struct ieee80211_sta *sta, bool set)
4441 {
4442 struct b43_wl *wl = hw_to_b43_wl(hw);
4443 unsigned long flags;
4444
4445 spin_lock_irqsave(&wl->irq_lock, flags);
4446 b43_update_templates(wl);
4447 spin_unlock_irqrestore(&wl->irq_lock, flags);
4448
4449 return 0;
4450 }
4451
4452 static void b43_op_sta_notify(struct ieee80211_hw *hw,
4453 struct ieee80211_vif *vif,
4454 enum sta_notify_cmd notify_cmd,
4455 struct ieee80211_sta *sta)
4456 {
4457 struct b43_wl *wl = hw_to_b43_wl(hw);
4458
4459 B43_WARN_ON(!vif || wl->vif != vif);
4460 }
4461
4462 static void b43_op_sw_scan_start_notifier(struct ieee80211_hw *hw)
4463 {
4464 struct b43_wl *wl = hw_to_b43_wl(hw);
4465 struct b43_wldev *dev;
4466
4467 mutex_lock(&wl->mutex);
4468 dev = wl->current_dev;
4469 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) {
4470 /* Disable CFP update during scan on other channels. */
4471 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_SKCFPUP);
4472 }
4473 mutex_unlock(&wl->mutex);
4474 }
4475
4476 static void b43_op_sw_scan_complete_notifier(struct ieee80211_hw *hw)
4477 {
4478 struct b43_wl *wl = hw_to_b43_wl(hw);
4479 struct b43_wldev *dev;
4480
4481 mutex_lock(&wl->mutex);
4482 dev = wl->current_dev;
4483 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) {
4484 /* Re-enable CFP update. */
4485 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_SKCFPUP);
4486 }
4487 mutex_unlock(&wl->mutex);
4488 }
4489
4490 static const struct ieee80211_ops b43_hw_ops = {
4491 .tx = b43_op_tx,
4492 .conf_tx = b43_op_conf_tx,
4493 .add_interface = b43_op_add_interface,
4494 .remove_interface = b43_op_remove_interface,
4495 .config = b43_op_config,
4496 .bss_info_changed = b43_op_bss_info_changed,
4497 .configure_filter = b43_op_configure_filter,
4498 .set_key = b43_op_set_key,
4499 .update_tkip_key = b43_op_update_tkip_key,
4500 .get_stats = b43_op_get_stats,
4501 .get_tx_stats = b43_op_get_tx_stats,
4502 .get_tsf = b43_op_get_tsf,
4503 .set_tsf = b43_op_set_tsf,
4504 .start = b43_op_start,
4505 .stop = b43_op_stop,
4506 .set_tim = b43_op_beacon_set_tim,
4507 .sta_notify = b43_op_sta_notify,
4508 .sw_scan_start = b43_op_sw_scan_start_notifier,
4509 .sw_scan_complete = b43_op_sw_scan_complete_notifier,
4510 .rfkill_poll = b43_rfkill_poll,
4511 };
4512
4513 /* Hard-reset the chip. Do not call this directly.
4514 * Use b43_controller_restart()
4515 */
4516 static void b43_chip_reset(struct work_struct *work)
4517 {
4518 struct b43_wldev *dev =
4519 container_of(work, struct b43_wldev, restart_work);
4520 struct b43_wl *wl = dev->wl;
4521 int err = 0;
4522 int prev_status;
4523
4524 mutex_lock(&wl->mutex);
4525
4526 prev_status = b43_status(dev);
4527 /* Bring the device down... */
4528 if (prev_status >= B43_STAT_STARTED)
4529 b43_wireless_core_stop(dev);
4530 if (prev_status >= B43_STAT_INITIALIZED)
4531 b43_wireless_core_exit(dev);
4532
4533 /* ...and up again. */
4534 if (prev_status >= B43_STAT_INITIALIZED) {
4535 err = b43_wireless_core_init(dev);
4536 if (err)
4537 goto out;
4538 }
4539 if (prev_status >= B43_STAT_STARTED) {
4540 err = b43_wireless_core_start(dev);
4541 if (err) {
4542 b43_wireless_core_exit(dev);
4543 goto out;
4544 }
4545 }
4546 out:
4547 if (err)
4548 wl->current_dev = NULL; /* Failed to init the dev. */
4549 mutex_unlock(&wl->mutex);
4550 if (err)
4551 b43err(wl, "Controller restart FAILED\n");
4552 else
4553 b43info(wl, "Controller restarted\n");
4554 }
4555
4556 static int b43_setup_bands(struct b43_wldev *dev,
4557 bool have_2ghz_phy, bool have_5ghz_phy)
4558 {
4559 struct ieee80211_hw *hw = dev->wl->hw;
4560
4561 if (have_2ghz_phy)
4562 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &b43_band_2GHz;
4563 if (dev->phy.type == B43_PHYTYPE_N) {
4564 if (have_5ghz_phy)
4565 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_nphy;
4566 } else {
4567 if (have_5ghz_phy)
4568 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_aphy;
4569 }
4570
4571 dev->phy.supports_2ghz = have_2ghz_phy;
4572 dev->phy.supports_5ghz = have_5ghz_phy;
4573
4574 return 0;
4575 }
4576
4577 static void b43_wireless_core_detach(struct b43_wldev *dev)
4578 {
4579 /* We release firmware that late to not be required to re-request
4580 * is all the time when we reinit the core. */
4581 b43_release_firmware(dev);
4582 b43_phy_free(dev);
4583 }
4584
4585 static int b43_wireless_core_attach(struct b43_wldev *dev)
4586 {
4587 struct b43_wl *wl = dev->wl;
4588 struct ssb_bus *bus = dev->dev->bus;
4589 struct pci_dev *pdev = bus->host_pci;
4590 int err;
4591 bool have_2ghz_phy = 0, have_5ghz_phy = 0;
4592 u32 tmp;
4593
4594 /* Do NOT do any device initialization here.
4595 * Do it in wireless_core_init() instead.
4596 * This function is for gathering basic information about the HW, only.
4597 * Also some structs may be set up here. But most likely you want to have
4598 * that in core_init(), too.
4599 */
4600
4601 err = ssb_bus_powerup(bus, 0);
4602 if (err) {
4603 b43err(wl, "Bus powerup failed\n");
4604 goto out;
4605 }
4606 /* Get the PHY type. */
4607 if (dev->dev->id.revision >= 5) {
4608 u32 tmshigh;
4609
4610 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
4611 have_2ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY);
4612 have_5ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_5GHZ_PHY);
4613 } else
4614 B43_WARN_ON(1);
4615
4616 dev->phy.gmode = have_2ghz_phy;
4617 dev->phy.radio_on = 1;
4618 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
4619 b43_wireless_core_reset(dev, tmp);
4620
4621 err = b43_phy_versioning(dev);
4622 if (err)
4623 goto err_powerdown;
4624 /* Check if this device supports multiband. */
4625 if (!pdev ||
4626 (pdev->device != 0x4312 &&
4627 pdev->device != 0x4319 && pdev->device != 0x4324)) {
4628 /* No multiband support. */
4629 have_2ghz_phy = 0;
4630 have_5ghz_phy = 0;
4631 switch (dev->phy.type) {
4632 case B43_PHYTYPE_A:
4633 have_5ghz_phy = 1;
4634 break;
4635 case B43_PHYTYPE_LP: //FIXME not always!
4636 #if 0 //FIXME enabling 5GHz causes a NULL pointer dereference
4637 have_5ghz_phy = 1;
4638 #endif
4639 case B43_PHYTYPE_G:
4640 case B43_PHYTYPE_N:
4641 have_2ghz_phy = 1;
4642 break;
4643 default:
4644 B43_WARN_ON(1);
4645 }
4646 }
4647 if (dev->phy.type == B43_PHYTYPE_A) {
4648 /* FIXME */
4649 b43err(wl, "IEEE 802.11a devices are unsupported\n");
4650 err = -EOPNOTSUPP;
4651 goto err_powerdown;
4652 }
4653 if (1 /* disable A-PHY */) {
4654 /* FIXME: For now we disable the A-PHY on multi-PHY devices. */
4655 if (dev->phy.type != B43_PHYTYPE_N &&
4656 dev->phy.type != B43_PHYTYPE_LP) {
4657 have_2ghz_phy = 1;
4658 have_5ghz_phy = 0;
4659 }
4660 }
4661
4662 err = b43_phy_allocate(dev);
4663 if (err)
4664 goto err_powerdown;
4665
4666 dev->phy.gmode = have_2ghz_phy;
4667 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
4668 b43_wireless_core_reset(dev, tmp);
4669
4670 err = b43_validate_chipaccess(dev);
4671 if (err)
4672 goto err_phy_free;
4673 err = b43_setup_bands(dev, have_2ghz_phy, have_5ghz_phy);
4674 if (err)
4675 goto err_phy_free;
4676
4677 /* Now set some default "current_dev" */
4678 if (!wl->current_dev)
4679 wl->current_dev = dev;
4680 INIT_WORK(&dev->restart_work, b43_chip_reset);
4681
4682 dev->phy.ops->switch_analog(dev, 0);
4683 ssb_device_disable(dev->dev, 0);
4684 ssb_bus_may_powerdown(bus);
4685
4686 out:
4687 return err;
4688
4689 err_phy_free:
4690 b43_phy_free(dev);
4691 err_powerdown:
4692 ssb_bus_may_powerdown(bus);
4693 return err;
4694 }
4695
4696 static void b43_one_core_detach(struct ssb_device *dev)
4697 {
4698 struct b43_wldev *wldev;
4699 struct b43_wl *wl;
4700
4701 /* Do not cancel ieee80211-workqueue based work here.
4702 * See comment in b43_remove(). */
4703
4704 wldev = ssb_get_drvdata(dev);
4705 wl = wldev->wl;
4706 b43_debugfs_remove_device(wldev);
4707 b43_wireless_core_detach(wldev);
4708 list_del(&wldev->list);
4709 wl->nr_devs--;
4710 ssb_set_drvdata(dev, NULL);
4711 kfree(wldev);
4712 }
4713
4714 static int b43_one_core_attach(struct ssb_device *dev, struct b43_wl *wl)
4715 {
4716 struct b43_wldev *wldev;
4717 struct pci_dev *pdev;
4718 int err = -ENOMEM;
4719
4720 if (!list_empty(&wl->devlist)) {
4721 /* We are not the first core on this chip. */
4722 pdev = dev->bus->host_pci;
4723 /* Only special chips support more than one wireless
4724 * core, although some of the other chips have more than
4725 * one wireless core as well. Check for this and
4726 * bail out early.
4727 */
4728 if (!pdev ||
4729 ((pdev->device != 0x4321) &&
4730 (pdev->device != 0x4313) && (pdev->device != 0x431A))) {
4731 b43dbg(wl, "Ignoring unconnected 802.11 core\n");
4732 return -ENODEV;
4733 }
4734 }
4735
4736 wldev = kzalloc(sizeof(*wldev), GFP_KERNEL);
4737 if (!wldev)
4738 goto out;
4739
4740 wldev->dev = dev;
4741 wldev->wl = wl;
4742 b43_set_status(wldev, B43_STAT_UNINIT);
4743 wldev->bad_frames_preempt = modparam_bad_frames_preempt;
4744 tasklet_init(&wldev->isr_tasklet,
4745 (void (*)(unsigned long))b43_interrupt_tasklet,
4746 (unsigned long)wldev);
4747 INIT_LIST_HEAD(&wldev->list);
4748
4749 err = b43_wireless_core_attach(wldev);
4750 if (err)
4751 goto err_kfree_wldev;
4752
4753 list_add(&wldev->list, &wl->devlist);
4754 wl->nr_devs++;
4755 ssb_set_drvdata(dev, wldev);
4756 b43_debugfs_add_device(wldev);
4757
4758 out:
4759 return err;
4760
4761 err_kfree_wldev:
4762 kfree(wldev);
4763 return err;
4764 }
4765
4766 #define IS_PDEV(pdev, _vendor, _device, _subvendor, _subdevice) ( \
4767 (pdev->vendor == PCI_VENDOR_ID_##_vendor) && \
4768 (pdev->device == _device) && \
4769 (pdev->subsystem_vendor == PCI_VENDOR_ID_##_subvendor) && \
4770 (pdev->subsystem_device == _subdevice) )
4771
4772 static void b43_sprom_fixup(struct ssb_bus *bus)
4773 {
4774 struct pci_dev *pdev;
4775
4776 /* boardflags workarounds */
4777 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_DELL &&
4778 bus->chip_id == 0x4301 && bus->boardinfo.rev == 0x74)
4779 bus->sprom.boardflags_lo |= B43_BFL_BTCOEXIST;
4780 if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
4781 bus->boardinfo.type == 0x4E && bus->boardinfo.rev > 0x40)
4782 bus->sprom.boardflags_lo |= B43_BFL_PACTRL;
4783 if (bus->bustype == SSB_BUSTYPE_PCI) {
4784 pdev = bus->host_pci;
4785 if (IS_PDEV(pdev, BROADCOM, 0x4318, ASUSTEK, 0x100F) ||
4786 IS_PDEV(pdev, BROADCOM, 0x4320, DELL, 0x0003) ||
4787 IS_PDEV(pdev, BROADCOM, 0x4320, HP, 0x12f8) ||
4788 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0015) ||
4789 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0014) ||
4790 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0013) ||
4791 IS_PDEV(pdev, BROADCOM, 0x4320, MOTOROLA, 0x7010))
4792 bus->sprom.boardflags_lo &= ~B43_BFL_BTCOEXIST;
4793 }
4794 }
4795
4796 static void b43_wireless_exit(struct ssb_device *dev, struct b43_wl *wl)
4797 {
4798 struct ieee80211_hw *hw = wl->hw;
4799
4800 ssb_set_devtypedata(dev, NULL);
4801 ieee80211_free_hw(hw);
4802 }
4803
4804 static int b43_wireless_init(struct ssb_device *dev)
4805 {
4806 struct ssb_sprom *sprom = &dev->bus->sprom;
4807 struct ieee80211_hw *hw;
4808 struct b43_wl *wl;
4809 int err = -ENOMEM;
4810
4811 b43_sprom_fixup(dev->bus);
4812
4813 hw = ieee80211_alloc_hw(sizeof(*wl), &b43_hw_ops);
4814 if (!hw) {
4815 b43err(NULL, "Could not allocate ieee80211 device\n");
4816 goto out;
4817 }
4818 wl = hw_to_b43_wl(hw);
4819
4820 /* fill hw info */
4821 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
4822 IEEE80211_HW_SIGNAL_DBM |
4823 IEEE80211_HW_NOISE_DBM;
4824
4825 hw->wiphy->interface_modes =
4826 BIT(NL80211_IFTYPE_AP) |
4827 BIT(NL80211_IFTYPE_MESH_POINT) |
4828 BIT(NL80211_IFTYPE_STATION) |
4829 BIT(NL80211_IFTYPE_WDS) |
4830 BIT(NL80211_IFTYPE_ADHOC);
4831
4832 hw->queues = modparam_qos ? 4 : 1;
4833 wl->mac80211_initially_registered_queues = hw->queues;
4834 hw->max_rates = 2;
4835 SET_IEEE80211_DEV(hw, dev->dev);
4836 if (is_valid_ether_addr(sprom->et1mac))
4837 SET_IEEE80211_PERM_ADDR(hw, sprom->et1mac);
4838 else
4839 SET_IEEE80211_PERM_ADDR(hw, sprom->il0mac);
4840
4841 /* Initialize struct b43_wl */
4842 wl->hw = hw;
4843 spin_lock_init(&wl->irq_lock);
4844 rwlock_init(&wl->tx_lock);
4845 spin_lock_init(&wl->leds_lock);
4846 spin_lock_init(&wl->shm_lock);
4847 mutex_init(&wl->mutex);
4848 INIT_LIST_HEAD(&wl->devlist);
4849 INIT_WORK(&wl->beacon_update_trigger, b43_beacon_update_trigger_work);
4850 INIT_WORK(&wl->txpower_adjust_work, b43_phy_txpower_adjust_work);
4851
4852 ssb_set_devtypedata(dev, wl);
4853 b43info(wl, "Broadcom %04X WLAN found (core revision %u)\n",
4854 dev->bus->chip_id, dev->id.revision);
4855 err = 0;
4856 out:
4857 return err;
4858 }
4859
4860 static int b43_probe(struct ssb_device *dev, const struct ssb_device_id *id)
4861 {
4862 struct b43_wl *wl;
4863 int err;
4864 int first = 0;
4865
4866 wl = ssb_get_devtypedata(dev);
4867 if (!wl) {
4868 /* Probing the first core. Must setup common struct b43_wl */
4869 first = 1;
4870 err = b43_wireless_init(dev);
4871 if (err)
4872 goto out;
4873 wl = ssb_get_devtypedata(dev);
4874 B43_WARN_ON(!wl);
4875 }
4876 err = b43_one_core_attach(dev, wl);
4877 if (err)
4878 goto err_wireless_exit;
4879
4880 if (first) {
4881 err = ieee80211_register_hw(wl->hw);
4882 if (err)
4883 goto err_one_core_detach;
4884 }
4885
4886 out:
4887 return err;
4888
4889 err_one_core_detach:
4890 b43_one_core_detach(dev);
4891 err_wireless_exit:
4892 if (first)
4893 b43_wireless_exit(dev, wl);
4894 return err;
4895 }
4896
4897 static void b43_remove(struct ssb_device *dev)
4898 {
4899 struct b43_wl *wl = ssb_get_devtypedata(dev);
4900 struct b43_wldev *wldev = ssb_get_drvdata(dev);
4901
4902 /* We must cancel any work here before unregistering from ieee80211,
4903 * as the ieee80211 unreg will destroy the workqueue. */
4904 cancel_work_sync(&wldev->restart_work);
4905
4906 B43_WARN_ON(!wl);
4907 if (wl->current_dev == wldev) {
4908 /* Restore the queues count before unregistering, because firmware detect
4909 * might have modified it. Restoring is important, so the networking
4910 * stack can properly free resources. */
4911 wl->hw->queues = wl->mac80211_initially_registered_queues;
4912 ieee80211_unregister_hw(wl->hw);
4913 }
4914
4915 b43_one_core_detach(dev);
4916
4917 if (list_empty(&wl->devlist)) {
4918 /* Last core on the chip unregistered.
4919 * We can destroy common struct b43_wl.
4920 */
4921 b43_wireless_exit(dev, wl);
4922 }
4923 }
4924
4925 /* Perform a hardware reset. This can be called from any context. */
4926 void b43_controller_restart(struct b43_wldev *dev, const char *reason)
4927 {
4928 /* Must avoid requeueing, if we are in shutdown. */
4929 if (b43_status(dev) < B43_STAT_INITIALIZED)
4930 return;
4931 b43info(dev->wl, "Controller RESET (%s) ...\n", reason);
4932 ieee80211_queue_work(dev->wl->hw, &dev->restart_work);
4933 }
4934
4935 #ifdef CONFIG_PM
4936
4937 static int b43_suspend(struct ssb_device *dev, pm_message_t state)
4938 {
4939 struct b43_wldev *wldev = ssb_get_drvdata(dev);
4940 struct b43_wl *wl = wldev->wl;
4941
4942 b43dbg(wl, "Suspending...\n");
4943
4944 mutex_lock(&wl->mutex);
4945 wldev->suspend_in_progress = true;
4946 wldev->suspend_init_status = b43_status(wldev);
4947 if (wldev->suspend_init_status >= B43_STAT_STARTED)
4948 b43_wireless_core_stop(wldev);
4949 if (wldev->suspend_init_status >= B43_STAT_INITIALIZED)
4950 b43_wireless_core_exit(wldev);
4951 mutex_unlock(&wl->mutex);
4952
4953 b43dbg(wl, "Device suspended.\n");
4954
4955 return 0;
4956 }
4957
4958 static int b43_resume(struct ssb_device *dev)
4959 {
4960 struct b43_wldev *wldev = ssb_get_drvdata(dev);
4961 struct b43_wl *wl = wldev->wl;
4962 int err = 0;
4963
4964 b43dbg(wl, "Resuming...\n");
4965
4966 mutex_lock(&wl->mutex);
4967 if (wldev->suspend_init_status >= B43_STAT_INITIALIZED) {
4968 err = b43_wireless_core_init(wldev);
4969 if (err) {
4970 b43err(wl, "Resume failed at core init\n");
4971 goto out;
4972 }
4973 }
4974 if (wldev->suspend_init_status >= B43_STAT_STARTED) {
4975 err = b43_wireless_core_start(wldev);
4976 if (err) {
4977 b43_leds_exit(wldev);
4978 b43_rng_exit(wldev->wl);
4979 b43_wireless_core_exit(wldev);
4980 b43err(wl, "Resume failed at core start\n");
4981 goto out;
4982 }
4983 }
4984 b43dbg(wl, "Device resumed.\n");
4985 out:
4986 wldev->suspend_in_progress = false;
4987 mutex_unlock(&wl->mutex);
4988 return err;
4989 }
4990
4991 #else /* CONFIG_PM */
4992 # define b43_suspend NULL
4993 # define b43_resume NULL
4994 #endif /* CONFIG_PM */
4995
4996 static struct ssb_driver b43_ssb_driver = {
4997 .name = KBUILD_MODNAME,
4998 .id_table = b43_ssb_tbl,
4999 .probe = b43_probe,
5000 .remove = b43_remove,
5001 .suspend = b43_suspend,
5002 .resume = b43_resume,
5003 };
5004
5005 static void b43_print_driverinfo(void)
5006 {
5007 const char *feat_pci = "", *feat_pcmcia = "", *feat_nphy = "",
5008 *feat_leds = "";
5009
5010 #ifdef CONFIG_B43_PCI_AUTOSELECT
5011 feat_pci = "P";
5012 #endif
5013 #ifdef CONFIG_B43_PCMCIA
5014 feat_pcmcia = "M";
5015 #endif
5016 #ifdef CONFIG_B43_NPHY
5017 feat_nphy = "N";
5018 #endif
5019 #ifdef CONFIG_B43_LEDS
5020 feat_leds = "L";
5021 #endif
5022 printk(KERN_INFO "Broadcom 43xx driver loaded "
5023 "[ Features: %s%s%s%s, Firmware-ID: "
5024 B43_SUPPORTED_FIRMWARE_ID " ]\n",
5025 feat_pci, feat_pcmcia, feat_nphy,
5026 feat_leds);
5027 }
5028
5029 static int __init b43_init(void)
5030 {
5031 int err;
5032
5033 b43_debugfs_init();
5034 err = b43_pcmcia_init();
5035 if (err)
5036 goto err_dfs_exit;
5037 err = ssb_driver_register(&b43_ssb_driver);
5038 if (err)
5039 goto err_pcmcia_exit;
5040 b43_print_driverinfo();
5041
5042 return err;
5043
5044 err_pcmcia_exit:
5045 b43_pcmcia_exit();
5046 err_dfs_exit:
5047 b43_debugfs_exit();
5048 return err;
5049 }
5050
5051 static void __exit b43_exit(void)
5052 {
5053 ssb_driver_unregister(&b43_ssb_driver);
5054 b43_pcmcia_exit();
5055 b43_debugfs_exit();
5056 }
5057
5058 module_init(b43_init)
5059 module_exit(b43_exit)
Linux kernel - Deliverables
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