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[B43]: add mac80211-based driver for modern BCM43xx devices
[deliverable/linux.git] / drivers / net / wireless / b43 / phy.c
1 /*
2
3 Broadcom B43 wireless driver
4
5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>,
6 Copyright (c) 2005, 2006 Stefano Brivio <st3@riseup.net>
7 Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de>
8 Copyright (c) 2005, 2006 Danny van Dyk <kugelfang@gentoo.org>
9 Copyright (c) 2005, 2006 Andreas Jaggi <andreas.jaggi@waterwave.ch>
10
11 This program is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2 of the License, or
14 (at your option) any later version.
15
16 This program is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
20
21 You should have received a copy of the GNU General Public License
22 along with this program; see the file COPYING. If not, write to
23 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
24 Boston, MA 02110-1301, USA.
25
26 */
27
28 #include <linux/delay.h>
29 #include <linux/types.h>
30
31 #include "b43.h"
32 #include "phy.h"
33 #include "main.h"
34 #include "tables.h"
35 #include "lo.h"
36
37 static const s8 b43_tssi2dbm_b_table[] = {
38 0x4D, 0x4C, 0x4B, 0x4A,
39 0x4A, 0x49, 0x48, 0x47,
40 0x47, 0x46, 0x45, 0x45,
41 0x44, 0x43, 0x42, 0x42,
42 0x41, 0x40, 0x3F, 0x3E,
43 0x3D, 0x3C, 0x3B, 0x3A,
44 0x39, 0x38, 0x37, 0x36,
45 0x35, 0x34, 0x32, 0x31,
46 0x30, 0x2F, 0x2D, 0x2C,
47 0x2B, 0x29, 0x28, 0x26,
48 0x25, 0x23, 0x21, 0x1F,
49 0x1D, 0x1A, 0x17, 0x14,
50 0x10, 0x0C, 0x06, 0x00,
51 -7, -7, -7, -7,
52 -7, -7, -7, -7,
53 -7, -7, -7, -7,
54 };
55
56 static const s8 b43_tssi2dbm_g_table[] = {
57 77, 77, 77, 76,
58 76, 76, 75, 75,
59 74, 74, 73, 73,
60 73, 72, 72, 71,
61 71, 70, 70, 69,
62 68, 68, 67, 67,
63 66, 65, 65, 64,
64 63, 63, 62, 61,
65 60, 59, 58, 57,
66 56, 55, 54, 53,
67 52, 50, 49, 47,
68 45, 43, 40, 37,
69 33, 28, 22, 14,
70 5, -7, -20, -20,
71 -20, -20, -20, -20,
72 -20, -20, -20, -20,
73 };
74
75 const u8 b43_radio_channel_codes_bg[] = {
76 12, 17, 22, 27,
77 32, 37, 42, 47,
78 52, 57, 62, 67,
79 72, 84,
80 };
81
82 static void b43_phy_initg(struct b43_wldev *dev);
83
84 /* Reverse the bits of a 4bit value.
85 * Example: 1101 is flipped 1011
86 */
87 static u16 flip_4bit(u16 value)
88 {
89 u16 flipped = 0x0000;
90
91 B43_WARN_ON(value & ~0x000F);
92
93 flipped |= (value & 0x0001) << 3;
94 flipped |= (value & 0x0002) << 1;
95 flipped |= (value & 0x0004) >> 1;
96 flipped |= (value & 0x0008) >> 3;
97
98 return flipped;
99 }
100
101 static void generate_rfatt_list(struct b43_wldev *dev,
102 struct b43_rfatt_list *list)
103 {
104 struct b43_phy *phy = &dev->phy;
105
106 /* APHY.rev < 5 || GPHY.rev < 6 */
107 static const struct b43_rfatt rfatt_0[] = {
108 {.att = 3,.with_padmix = 0,},
109 {.att = 1,.with_padmix = 0,},
110 {.att = 5,.with_padmix = 0,},
111 {.att = 7,.with_padmix = 0,},
112 {.att = 9,.with_padmix = 0,},
113 {.att = 2,.with_padmix = 0,},
114 {.att = 0,.with_padmix = 0,},
115 {.att = 4,.with_padmix = 0,},
116 {.att = 6,.with_padmix = 0,},
117 {.att = 8,.with_padmix = 0,},
118 {.att = 1,.with_padmix = 1,},
119 {.att = 2,.with_padmix = 1,},
120 {.att = 3,.with_padmix = 1,},
121 {.att = 4,.with_padmix = 1,},
122 };
123 /* Radio.rev == 8 && Radio.version == 0x2050 */
124 static const struct b43_rfatt rfatt_1[] = {
125 {.att = 2,.with_padmix = 1,},
126 {.att = 4,.with_padmix = 1,},
127 {.att = 6,.with_padmix = 1,},
128 {.att = 8,.with_padmix = 1,},
129 {.att = 10,.with_padmix = 1,},
130 {.att = 12,.with_padmix = 1,},
131 {.att = 14,.with_padmix = 1,},
132 };
133 /* Otherwise */
134 static const struct b43_rfatt rfatt_2[] = {
135 {.att = 0,.with_padmix = 1,},
136 {.att = 2,.with_padmix = 1,},
137 {.att = 4,.with_padmix = 1,},
138 {.att = 6,.with_padmix = 1,},
139 {.att = 8,.with_padmix = 1,},
140 {.att = 9,.with_padmix = 1,},
141 {.att = 9,.with_padmix = 1,},
142 };
143
144 if ((phy->type == B43_PHYTYPE_A && phy->rev < 5) ||
145 (phy->type == B43_PHYTYPE_G && phy->rev < 6)) {
146 /* Software pctl */
147 list->list = rfatt_0;
148 list->len = ARRAY_SIZE(rfatt_0);
149 list->min_val = 0;
150 list->max_val = 9;
151 return;
152 }
153 if (phy->radio_ver == 0x2050 && phy->radio_rev == 8) {
154 /* Hardware pctl */
155 list->list = rfatt_1;
156 list->len = ARRAY_SIZE(rfatt_1);
157 list->min_val = 2;
158 list->max_val = 14;
159 return;
160 }
161 /* Hardware pctl */
162 list->list = rfatt_2;
163 list->len = ARRAY_SIZE(rfatt_2);
164 list->min_val = 0;
165 list->max_val = 9;
166 }
167
168 static void generate_bbatt_list(struct b43_wldev *dev,
169 struct b43_bbatt_list *list)
170 {
171 static const struct b43_bbatt bbatt_0[] = {
172 {.att = 0,},
173 {.att = 1,},
174 {.att = 2,},
175 {.att = 3,},
176 {.att = 4,},
177 {.att = 5,},
178 {.att = 6,},
179 {.att = 7,},
180 {.att = 8,},
181 };
182
183 list->list = bbatt_0;
184 list->len = ARRAY_SIZE(bbatt_0);
185 list->min_val = 0;
186 list->max_val = 8;
187 }
188
189 bool b43_has_hardware_pctl(struct b43_phy *phy)
190 {
191 if (!phy->hardware_power_control)
192 return 0;
193 switch (phy->type) {
194 case B43_PHYTYPE_A:
195 if (phy->rev >= 5)
196 return 1;
197 break;
198 case B43_PHYTYPE_G:
199 if (phy->rev >= 6)
200 return 1;
201 break;
202 default:
203 B43_WARN_ON(1);
204 }
205 return 0;
206 }
207
208 static void b43_shm_clear_tssi(struct b43_wldev *dev)
209 {
210 struct b43_phy *phy = &dev->phy;
211
212 switch (phy->type) {
213 case B43_PHYTYPE_A:
214 b43_shm_write16(dev, B43_SHM_SHARED, 0x0068, 0x7F7F);
215 b43_shm_write16(dev, B43_SHM_SHARED, 0x006a, 0x7F7F);
216 break;
217 case B43_PHYTYPE_B:
218 case B43_PHYTYPE_G:
219 b43_shm_write16(dev, B43_SHM_SHARED, 0x0058, 0x7F7F);
220 b43_shm_write16(dev, B43_SHM_SHARED, 0x005a, 0x7F7F);
221 b43_shm_write16(dev, B43_SHM_SHARED, 0x0070, 0x7F7F);
222 b43_shm_write16(dev, B43_SHM_SHARED, 0x0072, 0x7F7F);
223 break;
224 }
225 }
226
227 void b43_raw_phy_lock(struct b43_wldev *dev)
228 {
229 struct b43_phy *phy = &dev->phy;
230
231 B43_WARN_ON(!irqs_disabled());
232
233 /* We had a check for MACCTL==0 here, but I think that doesn't
234 * make sense, as MACCTL is never 0 when this is called.
235 * --mb */
236 B43_WARN_ON(b43_read32(dev, B43_MMIO_MACCTL) == 0);
237
238 if (dev->dev->id.revision < 3) {
239 b43_mac_suspend(dev);
240 spin_lock(&phy->lock);
241 } else {
242 if (!b43_is_mode(dev->wl, IEEE80211_IF_TYPE_AP))
243 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
244 }
245 phy->locked = 1;
246 }
247
248 void b43_raw_phy_unlock(struct b43_wldev *dev)
249 {
250 struct b43_phy *phy = &dev->phy;
251
252 B43_WARN_ON(!irqs_disabled());
253 if (dev->dev->id.revision < 3) {
254 if (phy->locked) {
255 spin_unlock(&phy->lock);
256 b43_mac_enable(dev);
257 }
258 } else {
259 if (!b43_is_mode(dev->wl, IEEE80211_IF_TYPE_AP))
260 b43_power_saving_ctl_bits(dev, 0);
261 }
262 phy->locked = 0;
263 }
264
265 /* Different PHYs require different register routing flags.
266 * This adjusts (and does sanity checks on) the routing flags.
267 */
268 static inline u16 adjust_phyreg_for_phytype(struct b43_phy *phy,
269 u16 offset, struct b43_wldev *dev)
270 {
271 if (phy->type == B43_PHYTYPE_A) {
272 /* OFDM registers are base-registers for the A-PHY. */
273 offset &= ~B43_PHYROUTE_OFDM_GPHY;
274 }
275 if (offset & B43_PHYROUTE_EXT_GPHY) {
276 /* Ext-G registers are only available on G-PHYs */
277 if (phy->type != B43_PHYTYPE_G) {
278 b43dbg(dev->wl, "EXT-G PHY access at "
279 "0x%04X on %u type PHY\n", offset, phy->type);
280 }
281 }
282
283 return offset;
284 }
285
286 u16 b43_phy_read(struct b43_wldev * dev, u16 offset)
287 {
288 struct b43_phy *phy = &dev->phy;
289
290 offset = adjust_phyreg_for_phytype(phy, offset, dev);
291 b43_write16(dev, B43_MMIO_PHY_CONTROL, offset);
292 return b43_read16(dev, B43_MMIO_PHY_DATA);
293 }
294
295 void b43_phy_write(struct b43_wldev *dev, u16 offset, u16 val)
296 {
297 struct b43_phy *phy = &dev->phy;
298
299 offset = adjust_phyreg_for_phytype(phy, offset, dev);
300 b43_write16(dev, B43_MMIO_PHY_CONTROL, offset);
301 mmiowb();
302 b43_write16(dev, B43_MMIO_PHY_DATA, val);
303 }
304
305 static void b43_radio_set_txpower_a(struct b43_wldev *dev, u16 txpower);
306
307 /* Adjust the transmission power output (G-PHY) */
308 void b43_set_txpower_g(struct b43_wldev *dev,
309 const struct b43_bbatt *bbatt,
310 const struct b43_rfatt *rfatt, u8 tx_control)
311 {
312 struct b43_phy *phy = &dev->phy;
313 struct b43_txpower_lo_control *lo = phy->lo_control;
314 u16 bb, rf;
315 u16 tx_bias, tx_magn;
316
317 bb = bbatt->att;
318 rf = rfatt->att;
319 tx_bias = lo->tx_bias;
320 tx_magn = lo->tx_magn;
321 if (unlikely(tx_bias == 0xFF))
322 tx_bias = 0;
323
324 /* Save the values for later */
325 phy->tx_control = tx_control;
326 memcpy(&phy->rfatt, rfatt, sizeof(*rfatt));
327 memcpy(&phy->bbatt, bbatt, sizeof(*bbatt));
328
329 if (b43_debug(dev, B43_DBG_XMITPOWER)) {
330 b43dbg(dev->wl, "Tuning TX-power to bbatt(%u), "
331 "rfatt(%u), tx_control(0x%02X), "
332 "tx_bias(0x%02X), tx_magn(0x%02X)\n",
333 bb, rf, tx_control, tx_bias, tx_magn);
334 }
335
336 b43_phy_set_baseband_attenuation(dev, bb);
337 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_RFATT, rf);
338 if (phy->radio_ver == 0x2050 && phy->radio_rev == 8) {
339 b43_radio_write16(dev, 0x43,
340 (rf & 0x000F) | (tx_control & 0x0070));
341 } else {
342 b43_radio_write16(dev, 0x43, (b43_radio_read16(dev, 0x43)
343 & 0xFFF0) | (rf & 0x000F));
344 b43_radio_write16(dev, 0x52, (b43_radio_read16(dev, 0x52)
345 & ~0x0070) | (tx_control &
346 0x0070));
347 }
348 if (has_tx_magnification(phy)) {
349 b43_radio_write16(dev, 0x52, tx_magn | tx_bias);
350 } else {
351 b43_radio_write16(dev, 0x52, (b43_radio_read16(dev, 0x52)
352 & 0xFFF0) | (tx_bias & 0x000F));
353 }
354 if (phy->type == B43_PHYTYPE_G)
355 b43_lo_g_adjust(dev);
356 }
357
358 static void default_baseband_attenuation(struct b43_wldev *dev,
359 struct b43_bbatt *bb)
360 {
361 struct b43_phy *phy = &dev->phy;
362
363 if (phy->radio_ver == 0x2050 && phy->radio_rev < 6)
364 bb->att = 0;
365 else
366 bb->att = 2;
367 }
368
369 static void default_radio_attenuation(struct b43_wldev *dev,
370 struct b43_rfatt *rf)
371 {
372 struct ssb_bus *bus = dev->dev->bus;
373 struct b43_phy *phy = &dev->phy;
374
375 rf->with_padmix = 0;
376
377 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM &&
378 bus->boardinfo.type == SSB_BOARD_BCM4309G) {
379 if (bus->boardinfo.rev < 0x43) {
380 rf->att = 2;
381 return;
382 } else if (bus->boardinfo.rev < 0x51) {
383 rf->att = 3;
384 return;
385 }
386 }
387
388 if (phy->type == B43_PHYTYPE_A) {
389 rf->att = 0x60;
390 return;
391 }
392
393 switch (phy->radio_ver) {
394 case 0x2053:
395 switch (phy->radio_rev) {
396 case 1:
397 rf->att = 6;
398 return;
399 }
400 break;
401 case 0x2050:
402 switch (phy->radio_rev) {
403 case 0:
404 rf->att = 5;
405 return;
406 case 1:
407 if (phy->type == B43_PHYTYPE_G) {
408 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM
409 && bus->boardinfo.type == SSB_BOARD_BCM4309G
410 && bus->boardinfo.rev >= 30)
411 rf->att = 3;
412 else if (bus->boardinfo.vendor ==
413 SSB_BOARDVENDOR_BCM
414 && bus->boardinfo.type ==
415 SSB_BOARD_BU4306)
416 rf->att = 3;
417 else
418 rf->att = 1;
419 } else {
420 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM
421 && bus->boardinfo.type == SSB_BOARD_BCM4309G
422 && bus->boardinfo.rev >= 30)
423 rf->att = 7;
424 else
425 rf->att = 6;
426 }
427 return;
428 case 2:
429 if (phy->type == B43_PHYTYPE_G) {
430 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM
431 && bus->boardinfo.type == SSB_BOARD_BCM4309G
432 && bus->boardinfo.rev >= 30)
433 rf->att = 3;
434 else if (bus->boardinfo.vendor ==
435 SSB_BOARDVENDOR_BCM
436 && bus->boardinfo.type ==
437 SSB_BOARD_BU4306)
438 rf->att = 5;
439 else if (bus->chip_id == 0x4320)
440 rf->att = 4;
441 else
442 rf->att = 3;
443 } else
444 rf->att = 6;
445 return;
446 case 3:
447 rf->att = 5;
448 return;
449 case 4:
450 case 5:
451 rf->att = 1;
452 return;
453 case 6:
454 case 7:
455 rf->att = 5;
456 return;
457 case 8:
458 rf->att = 0xA;
459 rf->with_padmix = 1;
460 return;
461 case 9:
462 default:
463 rf->att = 5;
464 return;
465 }
466 }
467 rf->att = 5;
468 }
469
470 static u16 default_tx_control(struct b43_wldev *dev)
471 {
472 struct b43_phy *phy = &dev->phy;
473
474 if (phy->radio_ver != 0x2050)
475 return 0;
476 if (phy->radio_rev == 1)
477 return B43_TXCTL_PA2DB | B43_TXCTL_TXMIX;
478 if (phy->radio_rev < 6)
479 return B43_TXCTL_PA2DB;
480 if (phy->radio_rev == 8)
481 return B43_TXCTL_TXMIX;
482 return 0;
483 }
484
485 /* This func is called "PHY calibrate" in the specs... */
486 void b43_phy_early_init(struct b43_wldev *dev)
487 {
488 struct b43_phy *phy = &dev->phy;
489 struct b43_txpower_lo_control *lo = phy->lo_control;
490
491 default_baseband_attenuation(dev, &phy->bbatt);
492 default_radio_attenuation(dev, &phy->rfatt);
493 phy->tx_control = (default_tx_control(dev) << 4);
494
495 /* Commit previous writes */
496 b43_read32(dev, B43_MMIO_MACCTL);
497
498 if (phy->type == B43_PHYTYPE_B || phy->type == B43_PHYTYPE_G) {
499 generate_rfatt_list(dev, &lo->rfatt_list);
500 generate_bbatt_list(dev, &lo->bbatt_list);
501 }
502 if (phy->type == B43_PHYTYPE_G && phy->rev == 1) {
503 /* Workaround: Temporarly disable gmode through the early init
504 * phase, as the gmode stuff is not needed for phy rev 1 */
505 phy->gmode = 0;
506 b43_wireless_core_reset(dev, 0);
507 b43_phy_initg(dev);
508 phy->gmode = 1;
509 b43_wireless_core_reset(dev, B43_TMSLOW_GMODE);
510 }
511 }
512
513 /* GPHY_TSSI_Power_Lookup_Table_Init */
514 static void b43_gphy_tssi_power_lt_init(struct b43_wldev *dev)
515 {
516 struct b43_phy *phy = &dev->phy;
517 int i;
518 u16 value;
519
520 for (i = 0; i < 32; i++)
521 b43_ofdmtab_write16(dev, 0x3C20, i, phy->tssi2dbm[i]);
522 for (i = 32; i < 64; i++)
523 b43_ofdmtab_write16(dev, 0x3C00, i - 32, phy->tssi2dbm[i]);
524 for (i = 0; i < 64; i += 2) {
525 value = (u16) phy->tssi2dbm[i];
526 value |= ((u16) phy->tssi2dbm[i + 1]) << 8;
527 b43_phy_write(dev, 0x380 + (i / 2), value);
528 }
529 }
530
531 /* GPHY_Gain_Lookup_Table_Init */
532 static void b43_gphy_gain_lt_init(struct b43_wldev *dev)
533 {
534 struct b43_phy *phy = &dev->phy;
535 struct b43_txpower_lo_control *lo = phy->lo_control;
536 u16 nr_written = 0;
537 u16 tmp;
538 u8 rf, bb;
539
540 if (!lo->lo_measured) {
541 b43_phy_write(dev, 0x3FF, 0);
542 return;
543 }
544
545 for (rf = 0; rf < lo->rfatt_list.len; rf++) {
546 for (bb = 0; bb < lo->bbatt_list.len; bb++) {
547 if (nr_written >= 0x40)
548 return;
549 tmp = lo->bbatt_list.list[bb].att;
550 tmp <<= 8;
551 if (phy->radio_rev == 8)
552 tmp |= 0x50;
553 else
554 tmp |= 0x40;
555 tmp |= lo->rfatt_list.list[rf].att;
556 b43_phy_write(dev, 0x3C0 + nr_written, tmp);
557 nr_written++;
558 }
559 }
560 }
561
562 /* GPHY_DC_Lookup_Table */
563 void b43_gphy_dc_lt_init(struct b43_wldev *dev)
564 {
565 struct b43_phy *phy = &dev->phy;
566 struct b43_txpower_lo_control *lo = phy->lo_control;
567 struct b43_loctl *loctl0;
568 struct b43_loctl *loctl1;
569 int i;
570 int rf_offset, bb_offset;
571 u16 tmp;
572
573 for (i = 0; i < lo->rfatt_list.len + lo->bbatt_list.len; i += 2) {
574 rf_offset = i / lo->rfatt_list.len;
575 bb_offset = i % lo->rfatt_list.len;
576
577 loctl0 = b43_get_lo_g_ctl(dev, &lo->rfatt_list.list[rf_offset],
578 &lo->bbatt_list.list[bb_offset]);
579 if (i + 1 < lo->rfatt_list.len * lo->bbatt_list.len) {
580 rf_offset = (i + 1) / lo->rfatt_list.len;
581 bb_offset = (i + 1) % lo->rfatt_list.len;
582
583 loctl1 =
584 b43_get_lo_g_ctl(dev,
585 &lo->rfatt_list.list[rf_offset],
586 &lo->bbatt_list.list[bb_offset]);
587 } else
588 loctl1 = loctl0;
589
590 tmp = ((u16) loctl0->q & 0xF);
591 tmp |= ((u16) loctl0->i & 0xF) << 4;
592 tmp |= ((u16) loctl1->q & 0xF) << 8;
593 tmp |= ((u16) loctl1->i & 0xF) << 12; //FIXME?
594 b43_phy_write(dev, 0x3A0 + (i / 2), tmp);
595 }
596 }
597
598 static void hardware_pctl_init_aphy(struct b43_wldev *dev)
599 {
600 //TODO
601 }
602
603 static void hardware_pctl_init_gphy(struct b43_wldev *dev)
604 {
605 struct b43_phy *phy = &dev->phy;
606
607 b43_phy_write(dev, 0x0036, (b43_phy_read(dev, 0x0036) & 0xFFC0)
608 | (phy->tgt_idle_tssi - phy->cur_idle_tssi));
609 b43_phy_write(dev, 0x0478, (b43_phy_read(dev, 0x0478) & 0xFF00)
610 | (phy->tgt_idle_tssi - phy->cur_idle_tssi));
611 b43_gphy_tssi_power_lt_init(dev);
612 b43_gphy_gain_lt_init(dev);
613 b43_phy_write(dev, 0x0060, b43_phy_read(dev, 0x0060) & 0xFFBF);
614 b43_phy_write(dev, 0x0014, 0x0000);
615
616 B43_WARN_ON(phy->rev < 6);
617 b43_phy_write(dev, 0x0478, b43_phy_read(dev, 0x0478)
618 | 0x0800);
619 b43_phy_write(dev, 0x0478, b43_phy_read(dev, 0x0478)
620 & 0xFEFF);
621 b43_phy_write(dev, 0x0801, b43_phy_read(dev, 0x0801)
622 & 0xFFBF);
623
624 b43_gphy_dc_lt_init(dev);
625 }
626
627 /* HardwarePowerControl init for A and G PHY */
628 static void b43_hardware_pctl_init(struct b43_wldev *dev)
629 {
630 struct b43_phy *phy = &dev->phy;
631
632 if (!b43_has_hardware_pctl(phy)) {
633 /* No hardware power control */
634 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_HWPCTL);
635 return;
636 }
637 /* Init the hwpctl related hardware */
638 switch (phy->type) {
639 case B43_PHYTYPE_A:
640 hardware_pctl_init_aphy(dev);
641 break;
642 case B43_PHYTYPE_G:
643 hardware_pctl_init_gphy(dev);
644 break;
645 default:
646 B43_WARN_ON(1);
647 }
648 /* Enable hardware pctl in firmware. */
649 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_HWPCTL);
650 }
651
652 static void b43_hardware_pctl_early_init(struct b43_wldev *dev)
653 {
654 struct b43_phy *phy = &dev->phy;
655
656 if (!b43_has_hardware_pctl(phy)) {
657 b43_phy_write(dev, 0x047A, 0xC111);
658 return;
659 }
660
661 b43_phy_write(dev, 0x0036, b43_phy_read(dev, 0x0036) & 0xFEFF);
662 b43_phy_write(dev, 0x002F, 0x0202);
663 b43_phy_write(dev, 0x047C, b43_phy_read(dev, 0x047C) | 0x0002);
664 b43_phy_write(dev, 0x047A, b43_phy_read(dev, 0x047A) | 0xF000);
665 if (phy->radio_ver == 0x2050 && phy->radio_rev == 8) {
666 b43_phy_write(dev, 0x047A, (b43_phy_read(dev, 0x047A)
667 & 0xFF0F) | 0x0010);
668 b43_phy_write(dev, 0x005D, b43_phy_read(dev, 0x005D)
669 | 0x8000);
670 b43_phy_write(dev, 0x004E, (b43_phy_read(dev, 0x004E)
671 & 0xFFC0) | 0x0010);
672 b43_phy_write(dev, 0x002E, 0xC07F);
673 b43_phy_write(dev, 0x0036, b43_phy_read(dev, 0x0036)
674 | 0x0400);
675 } else {
676 b43_phy_write(dev, 0x0036, b43_phy_read(dev, 0x0036)
677 | 0x0200);
678 b43_phy_write(dev, 0x0036, b43_phy_read(dev, 0x0036)
679 | 0x0400);
680 b43_phy_write(dev, 0x005D, b43_phy_read(dev, 0x005D)
681 & 0x7FFF);
682 b43_phy_write(dev, 0x004F, b43_phy_read(dev, 0x004F)
683 & 0xFFFE);
684 b43_phy_write(dev, 0x004E, (b43_phy_read(dev, 0x004E)
685 & 0xFFC0) | 0x0010);
686 b43_phy_write(dev, 0x002E, 0xC07F);
687 b43_phy_write(dev, 0x047A, (b43_phy_read(dev, 0x047A)
688 & 0xFF0F) | 0x0010);
689 }
690 }
691
692 /* Intialize B/G PHY power control
693 * as described in http://bcm-specs.sipsolutions.net/InitPowerControl
694 */
695 static void b43_phy_init_pctl(struct b43_wldev *dev)
696 {
697 struct ssb_bus *bus = dev->dev->bus;
698 struct b43_phy *phy = &dev->phy;
699 struct b43_rfatt old_rfatt;
700 struct b43_bbatt old_bbatt;
701 u8 old_tx_control = 0;
702
703 if ((bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM) &&
704 (bus->boardinfo.type == SSB_BOARD_BU4306))
705 return;
706
707 b43_phy_write(dev, 0x0028, 0x8018);
708
709 /* This does something with the Analog... */
710 b43_write16(dev, B43_MMIO_PHY0, b43_read16(dev, B43_MMIO_PHY0)
711 & 0xFFDF);
712
713 if (phy->type == B43_PHYTYPE_G && !phy->gmode)
714 return;
715 b43_hardware_pctl_early_init(dev);
716 if (phy->cur_idle_tssi == 0) {
717 if (phy->radio_ver == 0x2050 && phy->analog == 0) {
718 b43_radio_write16(dev, 0x0076,
719 (b43_radio_read16(dev, 0x0076)
720 & 0x00F7) | 0x0084);
721 } else {
722 struct b43_rfatt rfatt;
723 struct b43_bbatt bbatt;
724
725 memcpy(&old_rfatt, &phy->rfatt, sizeof(old_rfatt));
726 memcpy(&old_bbatt, &phy->bbatt, sizeof(old_bbatt));
727 old_tx_control = phy->tx_control;
728
729 bbatt.att = 11;
730 if (phy->radio_rev == 8) {
731 rfatt.att = 15;
732 rfatt.with_padmix = 1;
733 } else {
734 rfatt.att = 9;
735 rfatt.with_padmix = 0;
736 }
737 b43_set_txpower_g(dev, &bbatt, &rfatt, 0);
738 }
739 b43_dummy_transmission(dev);
740 phy->cur_idle_tssi = b43_phy_read(dev, B43_PHY_ITSSI);
741 if (B43_DEBUG) {
742 /* Current-Idle-TSSI sanity check. */
743 if (abs(phy->cur_idle_tssi - phy->tgt_idle_tssi) >= 20) {
744 b43dbg(dev->wl,
745 "!WARNING! Idle-TSSI phy->cur_idle_tssi "
746 "measuring failed. (cur=%d, tgt=%d). Disabling TX power "
747 "adjustment.\n", phy->cur_idle_tssi,
748 phy->tgt_idle_tssi);
749 phy->cur_idle_tssi = 0;
750 }
751 }
752 if (phy->radio_ver == 0x2050 && phy->analog == 0) {
753 b43_radio_write16(dev, 0x0076,
754 b43_radio_read16(dev, 0x0076)
755 & 0xFF7B);
756 } else {
757 b43_set_txpower_g(dev, &old_bbatt,
758 &old_rfatt, old_tx_control);
759 }
760 }
761 b43_hardware_pctl_init(dev);
762 b43_shm_clear_tssi(dev);
763 }
764
765 static void b43_phy_agcsetup(struct b43_wldev *dev)
766 {
767 struct b43_phy *phy = &dev->phy;
768 u16 offset = 0x0000;
769
770 if (phy->rev == 1)
771 offset = 0x4C00;
772
773 b43_ofdmtab_write16(dev, offset, 0, 0x00FE);
774 b43_ofdmtab_write16(dev, offset, 1, 0x000D);
775 b43_ofdmtab_write16(dev, offset, 2, 0x0013);
776 b43_ofdmtab_write16(dev, offset, 3, 0x0019);
777
778 if (phy->rev == 1) {
779 b43_ofdmtab_write16(dev, 0x1800, 0, 0x2710);
780 b43_ofdmtab_write16(dev, 0x1801, 0, 0x9B83);
781 b43_ofdmtab_write16(dev, 0x1802, 0, 0x9B83);
782 b43_ofdmtab_write16(dev, 0x1803, 0, 0x0F8D);
783 b43_phy_write(dev, 0x0455, 0x0004);
784 }
785
786 b43_phy_write(dev, 0x04A5, (b43_phy_read(dev, 0x04A5)
787 & 0x00FF) | 0x5700);
788 b43_phy_write(dev, 0x041A, (b43_phy_read(dev, 0x041A)
789 & 0xFF80) | 0x000F);
790 b43_phy_write(dev, 0x041A, (b43_phy_read(dev, 0x041A)
791 & 0xC07F) | 0x2B80);
792 b43_phy_write(dev, 0x048C, (b43_phy_read(dev, 0x048C)
793 & 0xF0FF) | 0x0300);
794
795 b43_radio_write16(dev, 0x007A, b43_radio_read16(dev, 0x007A)
796 | 0x0008);
797
798 b43_phy_write(dev, 0x04A0, (b43_phy_read(dev, 0x04A0)
799 & 0xFFF0) | 0x0008);
800 b43_phy_write(dev, 0x04A1, (b43_phy_read(dev, 0x04A1)
801 & 0xF0FF) | 0x0600);
802 b43_phy_write(dev, 0x04A2, (b43_phy_read(dev, 0x04A2)
803 & 0xF0FF) | 0x0700);
804 b43_phy_write(dev, 0x04A0, (b43_phy_read(dev, 0x04A0)
805 & 0xF0FF) | 0x0100);
806
807 if (phy->rev == 1) {
808 b43_phy_write(dev, 0x04A2, (b43_phy_read(dev, 0x04A2)
809 & 0xFFF0) | 0x0007);
810 }
811
812 b43_phy_write(dev, 0x0488, (b43_phy_read(dev, 0x0488)
813 & 0xFF00) | 0x001C);
814 b43_phy_write(dev, 0x0488, (b43_phy_read(dev, 0x0488)
815 & 0xC0FF) | 0x0200);
816 b43_phy_write(dev, 0x0496, (b43_phy_read(dev, 0x0496)
817 & 0xFF00) | 0x001C);
818 b43_phy_write(dev, 0x0489, (b43_phy_read(dev, 0x0489)
819 & 0xFF00) | 0x0020);
820 b43_phy_write(dev, 0x0489, (b43_phy_read(dev, 0x0489)
821 & 0xC0FF) | 0x0200);
822 b43_phy_write(dev, 0x0482, (b43_phy_read(dev, 0x0482)
823 & 0xFF00) | 0x002E);
824 b43_phy_write(dev, 0x0496, (b43_phy_read(dev, 0x0496)
825 & 0x00FF) | 0x1A00);
826 b43_phy_write(dev, 0x0481, (b43_phy_read(dev, 0x0481)
827 & 0xFF00) | 0x0028);
828 b43_phy_write(dev, 0x0481, (b43_phy_read(dev, 0x0481)
829 & 0x00FF) | 0x2C00);
830
831 if (phy->rev == 1) {
832 b43_phy_write(dev, 0x0430, 0x092B);
833 b43_phy_write(dev, 0x041B, (b43_phy_read(dev, 0x041B)
834 & 0xFFE1) | 0x0002);
835 } else {
836 b43_phy_write(dev, 0x041B, b43_phy_read(dev, 0x041B)
837 & 0xFFE1);
838 b43_phy_write(dev, 0x041F, 0x287A);
839 b43_phy_write(dev, 0x0420, (b43_phy_read(dev, 0x0420)
840 & 0xFFF0) | 0x0004);
841 }
842
843 if (phy->rev >= 6) {
844 b43_phy_write(dev, 0x0422, 0x287A);
845 b43_phy_write(dev, 0x0420, (b43_phy_read(dev, 0x0420)
846 & 0x0FFF) | 0x3000);
847 }
848
849 b43_phy_write(dev, 0x04A8, (b43_phy_read(dev, 0x04A8)
850 & 0x8080) | 0x7874);
851 b43_phy_write(dev, 0x048E, 0x1C00);
852
853 offset = 0x0800;
854 if (phy->rev == 1) {
855 offset = 0x5400;
856 b43_phy_write(dev, 0x04AB, (b43_phy_read(dev, 0x04AB)
857 & 0xF0FF) | 0x0600);
858 b43_phy_write(dev, 0x048B, 0x005E);
859 b43_phy_write(dev, 0x048C, (b43_phy_read(dev, 0x048C)
860 & 0xFF00) | 0x001E);
861 b43_phy_write(dev, 0x048D, 0x0002);
862 }
863 b43_ofdmtab_write16(dev, offset, 0, 0x00);
864 b43_ofdmtab_write16(dev, offset, 1, 0x07);
865 b43_ofdmtab_write16(dev, offset, 2, 0x10);
866 b43_ofdmtab_write16(dev, offset, 3, 0x1C);
867
868 if (phy->rev >= 6) {
869 b43_phy_write(dev, 0x0426, b43_phy_read(dev, 0x0426)
870 & 0xFFFC);
871 b43_phy_write(dev, 0x0426, b43_phy_read(dev, 0x0426)
872 & 0xEFFF);
873 }
874 }
875
876 static void b43_phy_setupg(struct b43_wldev *dev)
877 {
878 struct ssb_bus *bus = dev->dev->bus;
879 struct b43_phy *phy = &dev->phy;
880 u16 i;
881
882 B43_WARN_ON(phy->type != B43_PHYTYPE_G);
883 if (phy->rev == 1) {
884 b43_phy_write(dev, 0x0406, 0x4F19);
885 b43_phy_write(dev, B43_PHY_G_CRS,
886 (b43_phy_read(dev, B43_PHY_G_CRS) & 0xFC3F) |
887 0x0340);
888 b43_phy_write(dev, 0x042C, 0x005A);
889 b43_phy_write(dev, 0x0427, 0x001A);
890
891 for (i = 0; i < B43_TAB_FINEFREQG_SIZE; i++)
892 b43_ofdmtab_write16(dev, 0x5800, i,
893 b43_tab_finefreqg[i]);
894 for (i = 0; i < B43_TAB_NOISEG1_SIZE; i++)
895 b43_ofdmtab_write16(dev, 0x1800, i, b43_tab_noiseg1[i]);
896 for (i = 0; i < B43_TAB_ROTOR_SIZE; i++)
897 b43_ofdmtab_write16(dev, 0x2000, i, b43_tab_rotor[i]);
898 } else {
899 /* nrssi values are signed 6-bit values. Not sure why we write 0x7654 here... */
900 b43_nrssi_hw_write(dev, 0xBA98, (s16) 0x7654);
901
902 if (phy->rev == 2) {
903 b43_phy_write(dev, 0x04C0, 0x1861);
904 b43_phy_write(dev, 0x04C1, 0x0271);
905 } else if (phy->rev > 2) {
906 b43_phy_write(dev, 0x04C0, 0x0098);
907 b43_phy_write(dev, 0x04C1, 0x0070);
908 b43_phy_write(dev, 0x04C9, 0x0080);
909 }
910 b43_phy_write(dev, 0x042B, b43_phy_read(dev, 0x042B) | 0x800);
911
912 for (i = 0; i < 64; i++)
913 b43_ofdmtab_write16(dev, 0x4000, i, i);
914 for (i = 0; i < B43_TAB_NOISEG2_SIZE; i++)
915 b43_ofdmtab_write16(dev, 0x1800, i, b43_tab_noiseg2[i]);
916 }
917
918 if (phy->rev <= 2)
919 for (i = 0; i < B43_TAB_NOISESCALEG_SIZE; i++)
920 b43_ofdmtab_write16(dev, 0x1400, i,
921 b43_tab_noisescaleg1[i]);
922 else if ((phy->rev >= 7) && (b43_phy_read(dev, 0x0449) & 0x0200))
923 for (i = 0; i < B43_TAB_NOISESCALEG_SIZE; i++)
924 b43_ofdmtab_write16(dev, 0x1400, i,
925 b43_tab_noisescaleg3[i]);
926 else
927 for (i = 0; i < B43_TAB_NOISESCALEG_SIZE; i++)
928 b43_ofdmtab_write16(dev, 0x1400, i,
929 b43_tab_noisescaleg2[i]);
930
931 if (phy->rev == 2)
932 for (i = 0; i < B43_TAB_SIGMASQR_SIZE; i++)
933 b43_ofdmtab_write16(dev, 0x5000, i,
934 b43_tab_sigmasqr1[i]);
935 else if ((phy->rev > 2) && (phy->rev <= 8))
936 for (i = 0; i < B43_TAB_SIGMASQR_SIZE; i++)
937 b43_ofdmtab_write16(dev, 0x5000, i,
938 b43_tab_sigmasqr2[i]);
939
940 if (phy->rev == 1) {
941 for (i = 0; i < B43_TAB_RETARD_SIZE; i++)
942 b43_ofdmtab_write32(dev, 0x2400, i, b43_tab_retard[i]);
943 for (i = 4; i < 20; i++)
944 b43_ofdmtab_write16(dev, 0x5400, i, 0x0020);
945 b43_phy_agcsetup(dev);
946
947 if ((bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM) &&
948 (bus->boardinfo.type == SSB_BOARD_BU4306) &&
949 (bus->boardinfo.rev == 0x17))
950 return;
951
952 b43_ofdmtab_write16(dev, 0x5001, 0, 0x0002);
953 b43_ofdmtab_write16(dev, 0x5002, 0, 0x0001);
954 } else {
955 for (i = 0; i < 0x20; i++)
956 b43_ofdmtab_write16(dev, 0x1000, i, 0x0820);
957 b43_phy_agcsetup(dev);
958 b43_phy_read(dev, 0x0400); /* dummy read */
959 b43_phy_write(dev, 0x0403, 0x1000);
960 b43_ofdmtab_write16(dev, 0x3C02, 0, 0x000F);
961 b43_ofdmtab_write16(dev, 0x3C03, 0, 0x0014);
962
963 if ((bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM) &&
964 (bus->boardinfo.type == SSB_BOARD_BU4306) &&
965 (bus->boardinfo.rev == 0x17))
966 return;
967
968 b43_ofdmtab_write16(dev, 0x0401, 0, 0x0002);
969 b43_ofdmtab_write16(dev, 0x0402, 0, 0x0001);
970 }
971 }
972
973 /* Initialize the noisescaletable for APHY */
974 static void b43_phy_init_noisescaletbl(struct b43_wldev *dev)
975 {
976 struct b43_phy *phy = &dev->phy;
977 int i;
978
979 for (i = 0; i < 12; i++) {
980 if (phy->rev == 2)
981 b43_ofdmtab_write16(dev, 0x1400, i, 0x6767);
982 else
983 b43_ofdmtab_write16(dev, 0x1400, i, 0x2323);
984 }
985 if (phy->rev == 2)
986 b43_ofdmtab_write16(dev, 0x1400, i, 0x6700);
987 else
988 b43_ofdmtab_write16(dev, 0x1400, i, 0x2300);
989 for (i = 0; i < 11; i++) {
990 if (phy->rev == 2)
991 b43_ofdmtab_write16(dev, 0x1400, i, 0x6767);
992 else
993 b43_ofdmtab_write16(dev, 0x1400, i, 0x2323);
994 }
995 if (phy->rev == 2)
996 b43_ofdmtab_write16(dev, 0x1400, i, 0x0067);
997 else
998 b43_ofdmtab_write16(dev, 0x1400, i, 0x0023);
999 }
1000
1001 static void b43_phy_setupa(struct b43_wldev *dev)
1002 {
1003 struct b43_phy *phy = &dev->phy;
1004 u16 i;
1005
1006 B43_WARN_ON(phy->type != B43_PHYTYPE_A);
1007 switch (phy->rev) {
1008 case 2:
1009 b43_phy_write(dev, 0x008E, 0x3800);
1010 b43_phy_write(dev, 0x0035, 0x03FF);
1011 b43_phy_write(dev, 0x0036, 0x0400);
1012
1013 b43_ofdmtab_write16(dev, 0x3807, 0, 0x0051);
1014
1015 b43_phy_write(dev, 0x001C, 0x0FF9);
1016 b43_phy_write(dev, 0x0020, b43_phy_read(dev, 0x0020) & 0xFF0F);
1017 b43_ofdmtab_write16(dev, 0x3C0C, 0, 0x07BF);
1018 b43_radio_write16(dev, 0x0002, 0x07BF);
1019
1020 b43_phy_write(dev, 0x0024, 0x4680);
1021 b43_phy_write(dev, 0x0020, 0x0003);
1022 b43_phy_write(dev, 0x001D, 0x0F40);
1023 b43_phy_write(dev, 0x001F, 0x1C00);
1024
1025 b43_phy_write(dev, 0x002A, (b43_phy_read(dev, 0x002A)
1026 & 0x00FF) | 0x0400);
1027 b43_phy_write(dev, 0x002B, b43_phy_read(dev, 0x002B)
1028 & 0xFBFF);
1029 b43_phy_write(dev, 0x008E, 0x58C1);
1030
1031 b43_ofdmtab_write16(dev, 0x0803, 0, 0x000F);
1032 b43_ofdmtab_write16(dev, 0x0804, 0, 0x001F);
1033 b43_ofdmtab_write16(dev, 0x0805, 0, 0x002A);
1034 b43_ofdmtab_write16(dev, 0x0805, 0, 0x0030);
1035 b43_ofdmtab_write16(dev, 0x0807, 0, 0x003A);
1036
1037 b43_ofdmtab_write16(dev, 0x0000, 0, 0x0013);
1038 b43_ofdmtab_write16(dev, 0x0000, 1, 0x0013);
1039 b43_ofdmtab_write16(dev, 0x0000, 2, 0x0013);
1040 b43_ofdmtab_write16(dev, 0x0000, 3, 0x0013);
1041 b43_ofdmtab_write16(dev, 0x0000, 4, 0x0015);
1042 b43_ofdmtab_write16(dev, 0x0000, 5, 0x0015);
1043 b43_ofdmtab_write16(dev, 0x0000, 6, 0x0019);
1044
1045 b43_ofdmtab_write16(dev, 0x0404, 0, 0x0003);
1046 b43_ofdmtab_write16(dev, 0x0405, 0, 0x0003);
1047 b43_ofdmtab_write16(dev, 0x0406, 0, 0x0007);
1048
1049 for (i = 0; i < 16; i++)
1050 b43_ofdmtab_write16(dev, 0x4000, i, (0x8 + i) & 0x000F);
1051
1052 b43_ofdmtab_write16(dev, 0x3003, 0, 0x1044);
1053 b43_ofdmtab_write16(dev, 0x3004, 0, 0x7201);
1054 b43_ofdmtab_write16(dev, 0x3006, 0, 0x0040);
1055 b43_ofdmtab_write16(dev, 0x3001, 0,
1056 (b43_ofdmtab_read16(dev, 0x3001, 0) &
1057 0x0010) | 0x0008);
1058
1059 for (i = 0; i < B43_TAB_FINEFREQA_SIZE; i++)
1060 b43_ofdmtab_write16(dev, 0x5800, i,
1061 b43_tab_finefreqa[i]);
1062 for (i = 0; i < B43_TAB_NOISEA2_SIZE; i++)
1063 b43_ofdmtab_write16(dev, 0x1800, i, b43_tab_noisea2[i]);
1064 for (i = 0; i < B43_TAB_ROTOR_SIZE; i++)
1065 b43_ofdmtab_write32(dev, 0x2000, i, b43_tab_rotor[i]);
1066 b43_phy_init_noisescaletbl(dev);
1067 for (i = 0; i < B43_TAB_RETARD_SIZE; i++)
1068 b43_ofdmtab_write32(dev, 0x2400, i, b43_tab_retard[i]);
1069 break;
1070 case 3:
1071 for (i = 0; i < 64; i++)
1072 b43_ofdmtab_write16(dev, 0x4000, i, i);
1073
1074 b43_ofdmtab_write16(dev, 0x3807, 0, 0x0051);
1075
1076 b43_phy_write(dev, 0x001C, 0x0FF9);
1077 b43_phy_write(dev, 0x0020, b43_phy_read(dev, 0x0020) & 0xFF0F);
1078 b43_radio_write16(dev, 0x0002, 0x07BF);
1079
1080 b43_phy_write(dev, 0x0024, 0x4680);
1081 b43_phy_write(dev, 0x0020, 0x0003);
1082 b43_phy_write(dev, 0x001D, 0x0F40);
1083 b43_phy_write(dev, 0x001F, 0x1C00);
1084 b43_phy_write(dev, 0x002A, (b43_phy_read(dev, 0x002A)
1085 & 0x00FF) | 0x0400);
1086
1087 b43_ofdmtab_write16(dev, 0x3000, 1,
1088 (b43_ofdmtab_read16(dev, 0x3000, 1)
1089 & 0x0010) | 0x0008);
1090 for (i = 0; i < B43_TAB_NOISEA3_SIZE; i++) {
1091 b43_ofdmtab_write16(dev, 0x1800, i, b43_tab_noisea3[i]);
1092 }
1093 b43_phy_init_noisescaletbl(dev);
1094 for (i = 0; i < B43_TAB_SIGMASQR_SIZE; i++) {
1095 b43_ofdmtab_write16(dev, 0x5000, i,
1096 b43_tab_sigmasqr1[i]);
1097 }
1098
1099 b43_phy_write(dev, 0x0003, 0x1808);
1100
1101 b43_ofdmtab_write16(dev, 0x0803, 0, 0x000F);
1102 b43_ofdmtab_write16(dev, 0x0804, 0, 0x001F);
1103 b43_ofdmtab_write16(dev, 0x0805, 0, 0x002A);
1104 b43_ofdmtab_write16(dev, 0x0805, 0, 0x0030);
1105 b43_ofdmtab_write16(dev, 0x0807, 0, 0x003A);
1106
1107 b43_ofdmtab_write16(dev, 0x0000, 0, 0x0013);
1108 b43_ofdmtab_write16(dev, 0x0001, 0, 0x0013);
1109 b43_ofdmtab_write16(dev, 0x0002, 0, 0x0013);
1110 b43_ofdmtab_write16(dev, 0x0003, 0, 0x0013);
1111 b43_ofdmtab_write16(dev, 0x0004, 0, 0x0015);
1112 b43_ofdmtab_write16(dev, 0x0005, 0, 0x0015);
1113 b43_ofdmtab_write16(dev, 0x0006, 0, 0x0019);
1114
1115 b43_ofdmtab_write16(dev, 0x0404, 0, 0x0003);
1116 b43_ofdmtab_write16(dev, 0x0405, 0, 0x0003);
1117 b43_ofdmtab_write16(dev, 0x0406, 0, 0x0007);
1118
1119 b43_ofdmtab_write16(dev, 0x3C02, 0, 0x000F);
1120 b43_ofdmtab_write16(dev, 0x3C03, 0, 0x0014);
1121 break;
1122 default:
1123 B43_WARN_ON(1);
1124 }
1125 }
1126
1127 /* Initialize APHY. This is also called for the GPHY in some cases. */
1128 static void b43_phy_inita(struct b43_wldev *dev)
1129 {
1130 struct ssb_bus *bus = dev->dev->bus;
1131 struct b43_phy *phy = &dev->phy;
1132 u16 tval;
1133
1134 might_sleep();
1135
1136 if (phy->type == B43_PHYTYPE_A) {
1137 b43_phy_setupa(dev);
1138 } else {
1139 b43_phy_setupg(dev);
1140 if (phy->gmode &&
1141 (dev->dev->bus->sprom.r1.boardflags_lo & B43_BFL_PACTRL))
1142 b43_phy_write(dev, 0x046E, 0x03CF);
1143 return;
1144 }
1145
1146 b43_phy_write(dev, B43_PHY_A_CRS,
1147 (b43_phy_read(dev, B43_PHY_A_CRS) & 0xF83C) | 0x0340);
1148 b43_phy_write(dev, 0x0034, 0x0001);
1149
1150 //TODO: RSSI AGC
1151 b43_phy_write(dev, B43_PHY_A_CRS,
1152 b43_phy_read(dev, B43_PHY_A_CRS) | (1 << 14));
1153 b43_radio_init2060(dev);
1154
1155 if ((bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM) &&
1156 ((bus->boardinfo.type == SSB_BOARD_BU4306) ||
1157 (bus->boardinfo.type == SSB_BOARD_BU4309))) {
1158 if (phy->lofcal == 0xFFFF) {
1159 //TODO: LOF Cal
1160 b43_radio_set_tx_iq(dev);
1161 } else
1162 b43_radio_write16(dev, 0x001E, phy->lofcal);
1163 }
1164
1165 b43_phy_write(dev, 0x007A, 0xF111);
1166
1167 if (phy->cur_idle_tssi == 0) {
1168 b43_radio_write16(dev, 0x0019, 0x0000);
1169 b43_radio_write16(dev, 0x0017, 0x0020);
1170
1171 tval = b43_ofdmtab_read16(dev, 0x3001, 0);
1172 if (phy->rev == 1) {
1173 b43_ofdmtab_write16(dev, 0x3001, 0,
1174 (b43_ofdmtab_read16(dev, 0x3001, 0)
1175 & 0xFF87)
1176 | 0x0058);
1177 } else {
1178 b43_ofdmtab_write16(dev, 0x3001, 0,
1179 (b43_ofdmtab_read16(dev, 0x3001, 0)
1180 & 0xFFC3)
1181 | 0x002C);
1182 }
1183 b43_dummy_transmission(dev);
1184 phy->cur_idle_tssi = b43_phy_read(dev, B43_PHY_A_PCTL);
1185 b43_ofdmtab_write16(dev, 0x3001, 0, tval);
1186
1187 b43_radio_set_txpower_a(dev, 0x0018);
1188 }
1189 b43_shm_clear_tssi(dev);
1190 }
1191
1192 static void b43_phy_initb2(struct b43_wldev *dev)
1193 {
1194 struct b43_phy *phy = &dev->phy;
1195 u16 offset, val;
1196
1197 b43_write16(dev, 0x03EC, 0x3F22);
1198 b43_phy_write(dev, 0x0020, 0x301C);
1199 b43_phy_write(dev, 0x0026, 0x0000);
1200 b43_phy_write(dev, 0x0030, 0x00C6);
1201 b43_phy_write(dev, 0x0088, 0x3E00);
1202 val = 0x3C3D;
1203 for (offset = 0x0089; offset < 0x00A7; offset++) {
1204 b43_phy_write(dev, offset, val);
1205 val -= 0x0202;
1206 }
1207 b43_phy_write(dev, 0x03E4, 0x3000);
1208 if (phy->channel == 0xFF)
1209 b43_radio_selectchannel(dev, B43_DEFAULT_CHANNEL_BG, 0);
1210 else
1211 b43_radio_selectchannel(dev, phy->channel, 0);
1212 if (phy->radio_ver != 0x2050) {
1213 b43_radio_write16(dev, 0x0075, 0x0080);
1214 b43_radio_write16(dev, 0x0079, 0x0081);
1215 }
1216 b43_radio_write16(dev, 0x0050, 0x0020);
1217 b43_radio_write16(dev, 0x0050, 0x0023);
1218 if (phy->radio_ver == 0x2050) {
1219 b43_radio_write16(dev, 0x0050, 0x0020);
1220 b43_radio_write16(dev, 0x005A, 0x0070);
1221 b43_radio_write16(dev, 0x005B, 0x007B);
1222 b43_radio_write16(dev, 0x005C, 0x00B0);
1223 b43_radio_write16(dev, 0x007A, 0x000F);
1224 b43_phy_write(dev, 0x0038, 0x0677);
1225 b43_radio_init2050(dev);
1226 }
1227 b43_phy_write(dev, 0x0014, 0x0080);
1228 b43_phy_write(dev, 0x0032, 0x00CA);
1229 b43_phy_write(dev, 0x0032, 0x00CC);
1230 b43_phy_write(dev, 0x0035, 0x07C2);
1231 b43_lo_b_measure(dev);
1232 b43_phy_write(dev, 0x0026, 0xCC00);
1233 if (phy->radio_ver != 0x2050)
1234 b43_phy_write(dev, 0x0026, 0xCE00);
1235 b43_write16(dev, B43_MMIO_CHANNEL_EXT, 0x1000);
1236 b43_phy_write(dev, 0x002A, 0x88A3);
1237 if (phy->radio_ver != 0x2050)
1238 b43_phy_write(dev, 0x002A, 0x88C2);
1239 b43_set_txpower_g(dev, &phy->bbatt, &phy->rfatt, phy->tx_control);
1240 b43_phy_init_pctl(dev);
1241 }
1242
1243 static void b43_phy_initb4(struct b43_wldev *dev)
1244 {
1245 struct b43_phy *phy = &dev->phy;
1246 u16 offset, val;
1247
1248 b43_write16(dev, 0x03EC, 0x3F22);
1249 b43_phy_write(dev, 0x0020, 0x301C);
1250 b43_phy_write(dev, 0x0026, 0x0000);
1251 b43_phy_write(dev, 0x0030, 0x00C6);
1252 b43_phy_write(dev, 0x0088, 0x3E00);
1253 val = 0x3C3D;
1254 for (offset = 0x0089; offset < 0x00A7; offset++) {
1255 b43_phy_write(dev, offset, val);
1256 val -= 0x0202;
1257 }
1258 b43_phy_write(dev, 0x03E4, 0x3000);
1259 if (phy->channel == 0xFF)
1260 b43_radio_selectchannel(dev, B43_DEFAULT_CHANNEL_BG, 0);
1261 else
1262 b43_radio_selectchannel(dev, phy->channel, 0);
1263 if (phy->radio_ver != 0x2050) {
1264 b43_radio_write16(dev, 0x0075, 0x0080);
1265 b43_radio_write16(dev, 0x0079, 0x0081);
1266 }
1267 b43_radio_write16(dev, 0x0050, 0x0020);
1268 b43_radio_write16(dev, 0x0050, 0x0023);
1269 if (phy->radio_ver == 0x2050) {
1270 b43_radio_write16(dev, 0x0050, 0x0020);
1271 b43_radio_write16(dev, 0x005A, 0x0070);
1272 b43_radio_write16(dev, 0x005B, 0x007B);
1273 b43_radio_write16(dev, 0x005C, 0x00B0);
1274 b43_radio_write16(dev, 0x007A, 0x000F);
1275 b43_phy_write(dev, 0x0038, 0x0677);
1276 b43_radio_init2050(dev);
1277 }
1278 b43_phy_write(dev, 0x0014, 0x0080);
1279 b43_phy_write(dev, 0x0032, 0x00CA);
1280 if (phy->radio_ver == 0x2050)
1281 b43_phy_write(dev, 0x0032, 0x00E0);
1282 b43_phy_write(dev, 0x0035, 0x07C2);
1283
1284 b43_lo_b_measure(dev);
1285
1286 b43_phy_write(dev, 0x0026, 0xCC00);
1287 if (phy->radio_ver == 0x2050)
1288 b43_phy_write(dev, 0x0026, 0xCE00);
1289 b43_write16(dev, B43_MMIO_CHANNEL_EXT, 0x1100);
1290 b43_phy_write(dev, 0x002A, 0x88A3);
1291 if (phy->radio_ver == 0x2050)
1292 b43_phy_write(dev, 0x002A, 0x88C2);
1293 b43_set_txpower_g(dev, &phy->bbatt, &phy->rfatt, phy->tx_control);
1294 if (dev->dev->bus->sprom.r1.boardflags_lo & B43_BFL_RSSI) {
1295 b43_calc_nrssi_slope(dev);
1296 b43_calc_nrssi_threshold(dev);
1297 }
1298 b43_phy_init_pctl(dev);
1299 }
1300
1301 static void b43_phy_initb5(struct b43_wldev *dev)
1302 {
1303 struct ssb_bus *bus = dev->dev->bus;
1304 struct b43_phy *phy = &dev->phy;
1305 u16 offset, value;
1306 u8 old_channel;
1307
1308 if (phy->analog == 1) {
1309 b43_radio_write16(dev, 0x007A, b43_radio_read16(dev, 0x007A)
1310 | 0x0050);
1311 }
1312 if ((bus->boardinfo.vendor != SSB_BOARDVENDOR_BCM) &&
1313 (bus->boardinfo.type != SSB_BOARD_BU4306)) {
1314 value = 0x2120;
1315 for (offset = 0x00A8; offset < 0x00C7; offset++) {
1316 b43_phy_write(dev, offset, value);
1317 value += 0x202;
1318 }
1319 }
1320 b43_phy_write(dev, 0x0035, (b43_phy_read(dev, 0x0035) & 0xF0FF)
1321 | 0x0700);
1322 if (phy->radio_ver == 0x2050)
1323 b43_phy_write(dev, 0x0038, 0x0667);
1324
1325 if (phy->gmode || phy->rev >= 2) {
1326 if (phy->radio_ver == 0x2050) {
1327 b43_radio_write16(dev, 0x007A,
1328 b43_radio_read16(dev, 0x007A)
1329 | 0x0020);
1330 b43_radio_write16(dev, 0x0051,
1331 b43_radio_read16(dev, 0x0051)
1332 | 0x0004);
1333 }
1334 b43_write16(dev, B43_MMIO_PHY_RADIO, 0x0000);
1335
1336 b43_phy_write(dev, 0x0802, b43_phy_read(dev, 0x0802) | 0x0100);
1337 b43_phy_write(dev, 0x042B, b43_phy_read(dev, 0x042B) | 0x2000);
1338
1339 b43_phy_write(dev, 0x001C, 0x186A);
1340
1341 b43_phy_write(dev, 0x0013,
1342 (b43_phy_read(dev, 0x0013) & 0x00FF) | 0x1900);
1343 b43_phy_write(dev, 0x0035,
1344 (b43_phy_read(dev, 0x0035) & 0xFFC0) | 0x0064);
1345 b43_phy_write(dev, 0x005D,
1346 (b43_phy_read(dev, 0x005D) & 0xFF80) | 0x000A);
1347 }
1348
1349 if (dev->bad_frames_preempt) {
1350 b43_phy_write(dev, B43_PHY_RADIO_BITFIELD,
1351 b43_phy_read(dev,
1352 B43_PHY_RADIO_BITFIELD) | (1 << 11));
1353 }
1354
1355 if (phy->analog == 1) {
1356 b43_phy_write(dev, 0x0026, 0xCE00);
1357 b43_phy_write(dev, 0x0021, 0x3763);
1358 b43_phy_write(dev, 0x0022, 0x1BC3);
1359 b43_phy_write(dev, 0x0023, 0x06F9);
1360 b43_phy_write(dev, 0x0024, 0x037E);
1361 } else
1362 b43_phy_write(dev, 0x0026, 0xCC00);
1363 b43_phy_write(dev, 0x0030, 0x00C6);
1364 b43_write16(dev, 0x03EC, 0x3F22);
1365
1366 if (phy->analog == 1)
1367 b43_phy_write(dev, 0x0020, 0x3E1C);
1368 else
1369 b43_phy_write(dev, 0x0020, 0x301C);
1370
1371 if (phy->analog == 0)
1372 b43_write16(dev, 0x03E4, 0x3000);
1373
1374 old_channel = phy->channel;
1375 /* Force to channel 7, even if not supported. */
1376 b43_radio_selectchannel(dev, 7, 0);
1377
1378 if (phy->radio_ver != 0x2050) {
1379 b43_radio_write16(dev, 0x0075, 0x0080);
1380 b43_radio_write16(dev, 0x0079, 0x0081);
1381 }
1382
1383 b43_radio_write16(dev, 0x0050, 0x0020);
1384 b43_radio_write16(dev, 0x0050, 0x0023);
1385
1386 if (phy->radio_ver == 0x2050) {
1387 b43_radio_write16(dev, 0x0050, 0x0020);
1388 b43_radio_write16(dev, 0x005A, 0x0070);
1389 }
1390
1391 b43_radio_write16(dev, 0x005B, 0x007B);
1392 b43_radio_write16(dev, 0x005C, 0x00B0);
1393
1394 b43_radio_write16(dev, 0x007A, b43_radio_read16(dev, 0x007A) | 0x0007);
1395
1396 b43_radio_selectchannel(dev, old_channel, 0);
1397
1398 b43_phy_write(dev, 0x0014, 0x0080);
1399 b43_phy_write(dev, 0x0032, 0x00CA);
1400 b43_phy_write(dev, 0x002A, 0x88A3);
1401
1402 b43_set_txpower_g(dev, &phy->bbatt, &phy->rfatt, phy->tx_control);
1403
1404 if (phy->radio_ver == 0x2050)
1405 b43_radio_write16(dev, 0x005D, 0x000D);
1406
1407 b43_write16(dev, 0x03E4, (b43_read16(dev, 0x03E4) & 0xFFC0) | 0x0004);
1408 }
1409
1410 static void b43_phy_initb6(struct b43_wldev *dev)
1411 {
1412 struct b43_phy *phy = &dev->phy;
1413 u16 offset, val;
1414 u8 old_channel;
1415
1416 b43_phy_write(dev, 0x003E, 0x817A);
1417 b43_radio_write16(dev, 0x007A,
1418 (b43_radio_read16(dev, 0x007A) | 0x0058));
1419 if (phy->radio_rev == 4 || phy->radio_rev == 5) {
1420 b43_radio_write16(dev, 0x51, 0x37);
1421 b43_radio_write16(dev, 0x52, 0x70);
1422 b43_radio_write16(dev, 0x53, 0xB3);
1423 b43_radio_write16(dev, 0x54, 0x9B);
1424 b43_radio_write16(dev, 0x5A, 0x88);
1425 b43_radio_write16(dev, 0x5B, 0x88);
1426 b43_radio_write16(dev, 0x5D, 0x88);
1427 b43_radio_write16(dev, 0x5E, 0x88);
1428 b43_radio_write16(dev, 0x7D, 0x88);
1429 b43_hf_write(dev, b43_hf_read(dev)
1430 | B43_HF_TSSIRPSMW);
1431 }
1432 B43_WARN_ON(phy->radio_rev == 6 || phy->radio_rev == 7); /* We had code for these revs here... */
1433 if (phy->radio_rev == 8) {
1434 b43_radio_write16(dev, 0x51, 0);
1435 b43_radio_write16(dev, 0x52, 0x40);
1436 b43_radio_write16(dev, 0x53, 0xB7);
1437 b43_radio_write16(dev, 0x54, 0x98);
1438 b43_radio_write16(dev, 0x5A, 0x88);
1439 b43_radio_write16(dev, 0x5B, 0x6B);
1440 b43_radio_write16(dev, 0x5C, 0x0F);
1441 if (dev->dev->bus->sprom.r1.boardflags_lo & B43_BFL_ALTIQ) {
1442 b43_radio_write16(dev, 0x5D, 0xFA);
1443 b43_radio_write16(dev, 0x5E, 0xD8);
1444 } else {
1445 b43_radio_write16(dev, 0x5D, 0xF5);
1446 b43_radio_write16(dev, 0x5E, 0xB8);
1447 }
1448 b43_radio_write16(dev, 0x0073, 0x0003);
1449 b43_radio_write16(dev, 0x007D, 0x00A8);
1450 b43_radio_write16(dev, 0x007C, 0x0001);
1451 b43_radio_write16(dev, 0x007E, 0x0008);
1452 }
1453 val = 0x1E1F;
1454 for (offset = 0x0088; offset < 0x0098; offset++) {
1455 b43_phy_write(dev, offset, val);
1456 val -= 0x0202;
1457 }
1458 val = 0x3E3F;
1459 for (offset = 0x0098; offset < 0x00A8; offset++) {
1460 b43_phy_write(dev, offset, val);
1461 val -= 0x0202;
1462 }
1463 val = 0x2120;
1464 for (offset = 0x00A8; offset < 0x00C8; offset++) {
1465 b43_phy_write(dev, offset, (val & 0x3F3F));
1466 val += 0x0202;
1467 }
1468 if (phy->type == B43_PHYTYPE_G) {
1469 b43_radio_write16(dev, 0x007A,
1470 b43_radio_read16(dev, 0x007A) | 0x0020);
1471 b43_radio_write16(dev, 0x0051,
1472 b43_radio_read16(dev, 0x0051) | 0x0004);
1473 b43_phy_write(dev, 0x0802, b43_phy_read(dev, 0x0802) | 0x0100);
1474 b43_phy_write(dev, 0x042B, b43_phy_read(dev, 0x042B) | 0x2000);
1475 b43_phy_write(dev, 0x5B, 0);
1476 b43_phy_write(dev, 0x5C, 0);
1477 }
1478
1479 old_channel = phy->channel;
1480 if (old_channel >= 8)
1481 b43_radio_selectchannel(dev, 1, 0);
1482 else
1483 b43_radio_selectchannel(dev, 13, 0);
1484
1485 b43_radio_write16(dev, 0x0050, 0x0020);
1486 b43_radio_write16(dev, 0x0050, 0x0023);
1487 udelay(40);
1488 if (phy->radio_rev < 6 || phy->radio_rev == 8) {
1489 b43_radio_write16(dev, 0x7C, (b43_radio_read16(dev, 0x7C)
1490 | 0x0002));
1491 b43_radio_write16(dev, 0x50, 0x20);
1492 }
1493 if (phy->radio_rev <= 2) {
1494 b43_radio_write16(dev, 0x7C, 0x20);
1495 b43_radio_write16(dev, 0x5A, 0x70);
1496 b43_radio_write16(dev, 0x5B, 0x7B);
1497 b43_radio_write16(dev, 0x5C, 0xB0);
1498 }
1499 b43_radio_write16(dev, 0x007A,
1500 (b43_radio_read16(dev, 0x007A) & 0x00F8) | 0x0007);
1501
1502 b43_radio_selectchannel(dev, old_channel, 0);
1503
1504 b43_phy_write(dev, 0x0014, 0x0200);
1505 if (phy->radio_rev >= 6)
1506 b43_phy_write(dev, 0x2A, 0x88C2);
1507 else
1508 b43_phy_write(dev, 0x2A, 0x8AC0);
1509 b43_phy_write(dev, 0x0038, 0x0668);
1510 b43_set_txpower_g(dev, &phy->bbatt, &phy->rfatt, phy->tx_control);
1511 if (phy->radio_rev <= 5) {
1512 b43_phy_write(dev, 0x5D, (b43_phy_read(dev, 0x5D)
1513 & 0xFF80) | 0x0003);
1514 }
1515 if (phy->radio_rev <= 2)
1516 b43_radio_write16(dev, 0x005D, 0x000D);
1517
1518 if (phy->analog == 4) {
1519 b43_write16(dev, 0x3E4, 9);
1520 b43_phy_write(dev, 0x61, b43_phy_read(dev, 0x61)
1521 & 0x0FFF);
1522 } else {
1523 b43_phy_write(dev, 0x0002, (b43_phy_read(dev, 0x0002) & 0xFFC0)
1524 | 0x0004);
1525 }
1526 if (phy->type == B43_PHYTYPE_B) {
1527 b43_write16(dev, 0x03E6, 0x8140);
1528 b43_phy_write(dev, 0x0016, 0x0410);
1529 b43_phy_write(dev, 0x0017, 0x0820);
1530 b43_phy_write(dev, 0x0062, 0x0007);
1531 b43_radio_init2050(dev);
1532 b43_lo_g_measure(dev);
1533 if (dev->dev->bus->sprom.r1.boardflags_lo & B43_BFL_RSSI) {
1534 b43_calc_nrssi_slope(dev);
1535 b43_calc_nrssi_threshold(dev);
1536 }
1537 b43_phy_init_pctl(dev);
1538 } else if (phy->type == B43_PHYTYPE_G)
1539 b43_write16(dev, 0x03E6, 0x0);
1540 }
1541
1542 static void b43_calc_loopback_gain(struct b43_wldev *dev)
1543 {
1544 struct b43_phy *phy = &dev->phy;
1545 u16 backup_phy[16] = { 0 };
1546 u16 backup_radio[3];
1547 u16 backup_bband;
1548 u16 i, j, loop_i_max;
1549 u16 trsw_rx;
1550 u16 loop1_outer_done, loop1_inner_done;
1551
1552 backup_phy[0] = b43_phy_read(dev, B43_PHY_CRS0);
1553 backup_phy[1] = b43_phy_read(dev, B43_PHY_CCKBBANDCFG);
1554 backup_phy[2] = b43_phy_read(dev, B43_PHY_RFOVER);
1555 backup_phy[3] = b43_phy_read(dev, B43_PHY_RFOVERVAL);
1556 if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */
1557 backup_phy[4] = b43_phy_read(dev, B43_PHY_ANALOGOVER);
1558 backup_phy[5] = b43_phy_read(dev, B43_PHY_ANALOGOVERVAL);
1559 }
1560 backup_phy[6] = b43_phy_read(dev, B43_PHY_BASE(0x5A));
1561 backup_phy[7] = b43_phy_read(dev, B43_PHY_BASE(0x59));
1562 backup_phy[8] = b43_phy_read(dev, B43_PHY_BASE(0x58));
1563 backup_phy[9] = b43_phy_read(dev, B43_PHY_BASE(0x0A));
1564 backup_phy[10] = b43_phy_read(dev, B43_PHY_BASE(0x03));
1565 backup_phy[11] = b43_phy_read(dev, B43_PHY_LO_MASK);
1566 backup_phy[12] = b43_phy_read(dev, B43_PHY_LO_CTL);
1567 backup_phy[13] = b43_phy_read(dev, B43_PHY_BASE(0x2B));
1568 backup_phy[14] = b43_phy_read(dev, B43_PHY_PGACTL);
1569 backup_phy[15] = b43_phy_read(dev, B43_PHY_LO_LEAKAGE);
1570 backup_bband = phy->bbatt.att;
1571 backup_radio[0] = b43_radio_read16(dev, 0x52);
1572 backup_radio[1] = b43_radio_read16(dev, 0x43);
1573 backup_radio[2] = b43_radio_read16(dev, 0x7A);
1574
1575 b43_phy_write(dev, B43_PHY_CRS0,
1576 b43_phy_read(dev, B43_PHY_CRS0) & 0x3FFF);
1577 b43_phy_write(dev, B43_PHY_CCKBBANDCFG,
1578 b43_phy_read(dev, B43_PHY_CCKBBANDCFG) | 0x8000);
1579 b43_phy_write(dev, B43_PHY_RFOVER,
1580 b43_phy_read(dev, B43_PHY_RFOVER) | 0x0002);
1581 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1582 b43_phy_read(dev, B43_PHY_RFOVERVAL) & 0xFFFD);
1583 b43_phy_write(dev, B43_PHY_RFOVER,
1584 b43_phy_read(dev, B43_PHY_RFOVER) | 0x0001);
1585 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1586 b43_phy_read(dev, B43_PHY_RFOVERVAL) & 0xFFFE);
1587 if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */
1588 b43_phy_write(dev, B43_PHY_ANALOGOVER,
1589 b43_phy_read(dev, B43_PHY_ANALOGOVER) | 0x0001);
1590 b43_phy_write(dev, B43_PHY_ANALOGOVERVAL,
1591 b43_phy_read(dev,
1592 B43_PHY_ANALOGOVERVAL) & 0xFFFE);
1593 b43_phy_write(dev, B43_PHY_ANALOGOVER,
1594 b43_phy_read(dev, B43_PHY_ANALOGOVER) | 0x0002);
1595 b43_phy_write(dev, B43_PHY_ANALOGOVERVAL,
1596 b43_phy_read(dev,
1597 B43_PHY_ANALOGOVERVAL) & 0xFFFD);
1598 }
1599 b43_phy_write(dev, B43_PHY_RFOVER,
1600 b43_phy_read(dev, B43_PHY_RFOVER) | 0x000C);
1601 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1602 b43_phy_read(dev, B43_PHY_RFOVERVAL) | 0x000C);
1603 b43_phy_write(dev, B43_PHY_RFOVER,
1604 b43_phy_read(dev, B43_PHY_RFOVER) | 0x0030);
1605 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1606 (b43_phy_read(dev, B43_PHY_RFOVERVAL)
1607 & 0xFFCF) | 0x10);
1608
1609 b43_phy_write(dev, B43_PHY_BASE(0x5A), 0x0780);
1610 b43_phy_write(dev, B43_PHY_BASE(0x59), 0xC810);
1611 b43_phy_write(dev, B43_PHY_BASE(0x58), 0x000D);
1612
1613 b43_phy_write(dev, B43_PHY_BASE(0x0A),
1614 b43_phy_read(dev, B43_PHY_BASE(0x0A)) | 0x2000);
1615 if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */
1616 b43_phy_write(dev, B43_PHY_ANALOGOVER,
1617 b43_phy_read(dev, B43_PHY_ANALOGOVER) | 0x0004);
1618 b43_phy_write(dev, B43_PHY_ANALOGOVERVAL,
1619 b43_phy_read(dev,
1620 B43_PHY_ANALOGOVERVAL) & 0xFFFB);
1621 }
1622 b43_phy_write(dev, B43_PHY_BASE(0x03),
1623 (b43_phy_read(dev, B43_PHY_BASE(0x03))
1624 & 0xFF9F) | 0x40);
1625
1626 if (phy->radio_rev == 8) {
1627 b43_radio_write16(dev, 0x43, 0x000F);
1628 } else {
1629 b43_radio_write16(dev, 0x52, 0);
1630 b43_radio_write16(dev, 0x43, (b43_radio_read16(dev, 0x43)
1631 & 0xFFF0) | 0x9);
1632 }
1633 b43_phy_set_baseband_attenuation(dev, 11);
1634
1635 if (phy->rev >= 3)
1636 b43_phy_write(dev, B43_PHY_LO_MASK, 0xC020);
1637 else
1638 b43_phy_write(dev, B43_PHY_LO_MASK, 0x8020);
1639 b43_phy_write(dev, B43_PHY_LO_CTL, 0);
1640
1641 b43_phy_write(dev, B43_PHY_BASE(0x2B),
1642 (b43_phy_read(dev, B43_PHY_BASE(0x2B))
1643 & 0xFFC0) | 0x01);
1644 b43_phy_write(dev, B43_PHY_BASE(0x2B),
1645 (b43_phy_read(dev, B43_PHY_BASE(0x2B))
1646 & 0xC0FF) | 0x800);
1647
1648 b43_phy_write(dev, B43_PHY_RFOVER,
1649 b43_phy_read(dev, B43_PHY_RFOVER) | 0x0100);
1650 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1651 b43_phy_read(dev, B43_PHY_RFOVERVAL) & 0xCFFF);
1652
1653 if (dev->dev->bus->sprom.r1.boardflags_lo & B43_BFL_EXTLNA) {
1654 if (phy->rev >= 7) {
1655 b43_phy_write(dev, B43_PHY_RFOVER,
1656 b43_phy_read(dev, B43_PHY_RFOVER)
1657 | 0x0800);
1658 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1659 b43_phy_read(dev, B43_PHY_RFOVERVAL)
1660 | 0x8000);
1661 }
1662 }
1663 b43_radio_write16(dev, 0x7A, b43_radio_read16(dev, 0x7A)
1664 & 0x00F7);
1665
1666 j = 0;
1667 loop_i_max = (phy->radio_rev == 8) ? 15 : 9;
1668 for (i = 0; i < loop_i_max; i++) {
1669 for (j = 0; j < 16; j++) {
1670 b43_radio_write16(dev, 0x43, i);
1671 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1672 (b43_phy_read(dev, B43_PHY_RFOVERVAL)
1673 & 0xF0FF) | (j << 8));
1674 b43_phy_write(dev, B43_PHY_PGACTL,
1675 (b43_phy_read(dev, B43_PHY_PGACTL)
1676 & 0x0FFF) | 0xA000);
1677 b43_phy_write(dev, B43_PHY_PGACTL,
1678 b43_phy_read(dev, B43_PHY_PGACTL)
1679 | 0xF000);
1680 udelay(20);
1681 if (b43_phy_read(dev, B43_PHY_LO_LEAKAGE) >= 0xDFC)
1682 goto exit_loop1;
1683 }
1684 }
1685 exit_loop1:
1686 loop1_outer_done = i;
1687 loop1_inner_done = j;
1688 if (j >= 8) {
1689 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1690 b43_phy_read(dev, B43_PHY_RFOVERVAL)
1691 | 0x30);
1692 trsw_rx = 0x1B;
1693 for (j = j - 8; j < 16; j++) {
1694 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1695 (b43_phy_read(dev, B43_PHY_RFOVERVAL)
1696 & 0xF0FF) | (j << 8));
1697 b43_phy_write(dev, B43_PHY_PGACTL,
1698 (b43_phy_read(dev, B43_PHY_PGACTL)
1699 & 0x0FFF) | 0xA000);
1700 b43_phy_write(dev, B43_PHY_PGACTL,
1701 b43_phy_read(dev, B43_PHY_PGACTL)
1702 | 0xF000);
1703 udelay(20);
1704 trsw_rx -= 3;
1705 if (b43_phy_read(dev, B43_PHY_LO_LEAKAGE) >= 0xDFC)
1706 goto exit_loop2;
1707 }
1708 } else
1709 trsw_rx = 0x18;
1710 exit_loop2:
1711
1712 if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */
1713 b43_phy_write(dev, B43_PHY_ANALOGOVER, backup_phy[4]);
1714 b43_phy_write(dev, B43_PHY_ANALOGOVERVAL, backup_phy[5]);
1715 }
1716 b43_phy_write(dev, B43_PHY_BASE(0x5A), backup_phy[6]);
1717 b43_phy_write(dev, B43_PHY_BASE(0x59), backup_phy[7]);
1718 b43_phy_write(dev, B43_PHY_BASE(0x58), backup_phy[8]);
1719 b43_phy_write(dev, B43_PHY_BASE(0x0A), backup_phy[9]);
1720 b43_phy_write(dev, B43_PHY_BASE(0x03), backup_phy[10]);
1721 b43_phy_write(dev, B43_PHY_LO_MASK, backup_phy[11]);
1722 b43_phy_write(dev, B43_PHY_LO_CTL, backup_phy[12]);
1723 b43_phy_write(dev, B43_PHY_BASE(0x2B), backup_phy[13]);
1724 b43_phy_write(dev, B43_PHY_PGACTL, backup_phy[14]);
1725
1726 b43_phy_set_baseband_attenuation(dev, backup_bband);
1727
1728 b43_radio_write16(dev, 0x52, backup_radio[0]);
1729 b43_radio_write16(dev, 0x43, backup_radio[1]);
1730 b43_radio_write16(dev, 0x7A, backup_radio[2]);
1731
1732 b43_phy_write(dev, B43_PHY_RFOVER, backup_phy[2] | 0x0003);
1733 udelay(10);
1734 b43_phy_write(dev, B43_PHY_RFOVER, backup_phy[2]);
1735 b43_phy_write(dev, B43_PHY_RFOVERVAL, backup_phy[3]);
1736 b43_phy_write(dev, B43_PHY_CRS0, backup_phy[0]);
1737 b43_phy_write(dev, B43_PHY_CCKBBANDCFG, backup_phy[1]);
1738
1739 phy->max_lb_gain =
1740 ((loop1_inner_done * 6) - (loop1_outer_done * 4)) - 11;
1741 phy->trsw_rx_gain = trsw_rx * 2;
1742 }
1743
1744 static void b43_phy_initg(struct b43_wldev *dev)
1745 {
1746 struct b43_phy *phy = &dev->phy;
1747 u16 tmp;
1748
1749 if (phy->rev == 1)
1750 b43_phy_initb5(dev);
1751 else
1752 b43_phy_initb6(dev);
1753
1754 if (phy->rev >= 2 || phy->gmode)
1755 b43_phy_inita(dev);
1756
1757 if (phy->rev >= 2) {
1758 b43_phy_write(dev, B43_PHY_ANALOGOVER, 0);
1759 b43_phy_write(dev, B43_PHY_ANALOGOVERVAL, 0);
1760 }
1761 if (phy->rev == 2) {
1762 b43_phy_write(dev, B43_PHY_RFOVER, 0);
1763 b43_phy_write(dev, B43_PHY_PGACTL, 0xC0);
1764 }
1765 if (phy->rev > 5) {
1766 b43_phy_write(dev, B43_PHY_RFOVER, 0x400);
1767 b43_phy_write(dev, B43_PHY_PGACTL, 0xC0);
1768 }
1769 if (phy->gmode || phy->rev >= 2) {
1770 tmp = b43_phy_read(dev, B43_PHY_VERSION_OFDM);
1771 tmp &= B43_PHYVER_VERSION;
1772 if (tmp == 3 || tmp == 5) {
1773 b43_phy_write(dev, B43_PHY_OFDM(0xC2), 0x1816);
1774 b43_phy_write(dev, B43_PHY_OFDM(0xC3), 0x8006);
1775 }
1776 if (tmp == 5) {
1777 b43_phy_write(dev, B43_PHY_OFDM(0xCC),
1778 (b43_phy_read(dev, B43_PHY_OFDM(0xCC))
1779 & 0x00FF) | 0x1F00);
1780 }
1781 }
1782 if ((phy->rev <= 2 && phy->gmode) || phy->rev >= 2)
1783 b43_phy_write(dev, B43_PHY_OFDM(0x7E), 0x78);
1784 if (phy->radio_rev == 8) {
1785 b43_phy_write(dev, B43_PHY_EXTG(0x01),
1786 b43_phy_read(dev, B43_PHY_EXTG(0x01))
1787 | 0x80);
1788 b43_phy_write(dev, B43_PHY_OFDM(0x3E),
1789 b43_phy_read(dev, B43_PHY_OFDM(0x3E))
1790 | 0x4);
1791 }
1792 if (has_loopback_gain(phy))
1793 b43_calc_loopback_gain(dev);
1794
1795 if (phy->radio_rev != 8) {
1796 if (phy->initval == 0xFFFF)
1797 phy->initval = b43_radio_init2050(dev);
1798 else
1799 b43_radio_write16(dev, 0x0078, phy->initval);
1800 }
1801 if (phy->lo_control->tx_bias == 0xFF) {
1802 b43_lo_g_measure(dev);
1803 } else {
1804 if (has_tx_magnification(phy)) {
1805 b43_radio_write16(dev, 0x52,
1806 (b43_radio_read16(dev, 0x52) & 0xFF00)
1807 | phy->lo_control->tx_bias | phy->
1808 lo_control->tx_magn);
1809 } else {
1810 b43_radio_write16(dev, 0x52,
1811 (b43_radio_read16(dev, 0x52) & 0xFFF0)
1812 | phy->lo_control->tx_bias);
1813 }
1814 if (phy->rev >= 6) {
1815 b43_phy_write(dev, B43_PHY_BASE(0x36),
1816 (b43_phy_read(dev, B43_PHY_BASE(0x36))
1817 & 0x0FFF) | (phy->lo_control->
1818 tx_bias << 12));
1819 }
1820 if (dev->dev->bus->sprom.r1.boardflags_lo & B43_BFL_PACTRL)
1821 b43_phy_write(dev, B43_PHY_BASE(0x2E), 0x8075);
1822 else
1823 b43_phy_write(dev, B43_PHY_BASE(0x2E), 0x807F);
1824 if (phy->rev < 2)
1825 b43_phy_write(dev, B43_PHY_BASE(0x2F), 0x101);
1826 else
1827 b43_phy_write(dev, B43_PHY_BASE(0x2F), 0x202);
1828 }
1829 if (phy->gmode || phy->rev >= 2) {
1830 b43_lo_g_adjust(dev);
1831 b43_phy_write(dev, B43_PHY_LO_MASK, 0x8078);
1832 }
1833
1834 if (!(dev->dev->bus->sprom.r1.boardflags_lo & B43_BFL_RSSI)) {
1835 /* The specs state to update the NRSSI LT with
1836 * the value 0x7FFFFFFF here. I think that is some weird
1837 * compiler optimization in the original driver.
1838 * Essentially, what we do here is resetting all NRSSI LT
1839 * entries to -32 (see the limit_value() in nrssi_hw_update())
1840 */
1841 b43_nrssi_hw_update(dev, 0xFFFF); //FIXME?
1842 b43_calc_nrssi_threshold(dev);
1843 } else if (phy->gmode || phy->rev >= 2) {
1844 if (phy->nrssi[0] == -1000) {
1845 B43_WARN_ON(phy->nrssi[1] != -1000);
1846 b43_calc_nrssi_slope(dev);
1847 } else
1848 b43_calc_nrssi_threshold(dev);
1849 }
1850 if (phy->radio_rev == 8)
1851 b43_phy_write(dev, B43_PHY_EXTG(0x05), 0x3230);
1852 b43_phy_init_pctl(dev);
1853 /* FIXME: The spec says in the following if, the 0 should be replaced
1854 'if OFDM may not be used in the current locale'
1855 but OFDM is legal everywhere */
1856 if ((dev->dev->bus->chip_id == 0x4306
1857 && dev->dev->bus->chip_package == 2) || 0) {
1858 b43_phy_write(dev, B43_PHY_CRS0, b43_phy_read(dev, B43_PHY_CRS0)
1859 & 0xBFFF);
1860 b43_phy_write(dev, B43_PHY_OFDM(0xC3),
1861 b43_phy_read(dev, B43_PHY_OFDM(0xC3))
1862 & 0x7FFF);
1863 }
1864 }
1865
1866 /* Set the baseband attenuation value on chip. */
1867 void b43_phy_set_baseband_attenuation(struct b43_wldev *dev,
1868 u16 baseband_attenuation)
1869 {
1870 struct b43_phy *phy = &dev->phy;
1871
1872 if (phy->analog == 0) {
1873 b43_write16(dev, B43_MMIO_PHY0, (b43_read16(dev, B43_MMIO_PHY0)
1874 & 0xFFF0) |
1875 baseband_attenuation);
1876 } else if (phy->analog > 1) {
1877 b43_phy_write(dev, B43_PHY_DACCTL,
1878 (b43_phy_read(dev, B43_PHY_DACCTL)
1879 & 0xFFC3) | (baseband_attenuation << 2));
1880 } else {
1881 b43_phy_write(dev, B43_PHY_DACCTL,
1882 (b43_phy_read(dev, B43_PHY_DACCTL)
1883 & 0xFF87) | (baseband_attenuation << 3));
1884 }
1885 }
1886
1887 /* http://bcm-specs.sipsolutions.net/EstimatePowerOut
1888 * This function converts a TSSI value to dBm in Q5.2
1889 */
1890 static s8 b43_phy_estimate_power_out(struct b43_wldev *dev, s8 tssi)
1891 {
1892 struct b43_phy *phy = &dev->phy;
1893 s8 dbm = 0;
1894 s32 tmp;
1895
1896 tmp = (phy->tgt_idle_tssi - phy->cur_idle_tssi + tssi);
1897
1898 switch (phy->type) {
1899 case B43_PHYTYPE_A:
1900 tmp += 0x80;
1901 tmp = limit_value(tmp, 0x00, 0xFF);
1902 dbm = phy->tssi2dbm[tmp];
1903 //TODO: There's a FIXME on the specs
1904 break;
1905 case B43_PHYTYPE_B:
1906 case B43_PHYTYPE_G:
1907 tmp = limit_value(tmp, 0x00, 0x3F);
1908 dbm = phy->tssi2dbm[tmp];
1909 break;
1910 default:
1911 B43_WARN_ON(1);
1912 }
1913
1914 return dbm;
1915 }
1916
1917 void b43_put_attenuation_into_ranges(struct b43_wldev *dev,
1918 int *_bbatt, int *_rfatt)
1919 {
1920 int rfatt = *_rfatt;
1921 int bbatt = *_bbatt;
1922 struct b43_txpower_lo_control *lo = dev->phy.lo_control;
1923
1924 /* Get baseband and radio attenuation values into their permitted ranges.
1925 * Radio attenuation affects power level 4 times as much as baseband. */
1926
1927 /* Range constants */
1928 const int rf_min = lo->rfatt_list.min_val;
1929 const int rf_max = lo->rfatt_list.max_val;
1930 const int bb_min = lo->bbatt_list.min_val;
1931 const int bb_max = lo->bbatt_list.max_val;
1932
1933 while (1) {
1934 if (rfatt > rf_max && bbatt > bb_max - 4)
1935 break; /* Can not get it into ranges */
1936 if (rfatt < rf_min && bbatt < bb_min + 4)
1937 break; /* Can not get it into ranges */
1938 if (bbatt > bb_max && rfatt > rf_max - 1)
1939 break; /* Can not get it into ranges */
1940 if (bbatt < bb_min && rfatt < rf_min + 1)
1941 break; /* Can not get it into ranges */
1942
1943 if (bbatt > bb_max) {
1944 bbatt -= 4;
1945 rfatt += 1;
1946 continue;
1947 }
1948 if (bbatt < bb_min) {
1949 bbatt += 4;
1950 rfatt -= 1;
1951 continue;
1952 }
1953 if (rfatt > rf_max) {
1954 rfatt -= 1;
1955 bbatt += 4;
1956 continue;
1957 }
1958 if (rfatt < rf_min) {
1959 rfatt += 1;
1960 bbatt -= 4;
1961 continue;
1962 }
1963 break;
1964 }
1965
1966 *_rfatt = limit_value(rfatt, rf_min, rf_max);
1967 *_bbatt = limit_value(bbatt, bb_min, bb_max);
1968 }
1969
1970 /* http://bcm-specs.sipsolutions.net/RecalculateTransmissionPower */
1971 void b43_phy_xmitpower(struct b43_wldev *dev)
1972 {
1973 struct ssb_bus *bus = dev->dev->bus;
1974 struct b43_phy *phy = &dev->phy;
1975
1976 if (phy->cur_idle_tssi == 0)
1977 return;
1978 if ((bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM) &&
1979 (bus->boardinfo.type == SSB_BOARD_BU4306))
1980 return;
1981 #ifdef CONFIG_B43_DEBUG
1982 if (phy->manual_txpower_control)
1983 return;
1984 #endif
1985
1986 switch (phy->type) {
1987 case B43_PHYTYPE_A:{
1988
1989 //TODO: Nothing for A PHYs yet :-/
1990
1991 break;
1992 }
1993 case B43_PHYTYPE_B:
1994 case B43_PHYTYPE_G:{
1995 u16 tmp;
1996 s8 v0, v1, v2, v3;
1997 s8 average;
1998 int max_pwr;
1999 int desired_pwr, estimated_pwr, pwr_adjust;
2000 int rfatt_delta, bbatt_delta;
2001 int rfatt, bbatt;
2002 u8 tx_control;
2003 unsigned long phylock_flags;
2004
2005 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x0058);
2006 v0 = (s8) (tmp & 0x00FF);
2007 v1 = (s8) ((tmp & 0xFF00) >> 8);
2008 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x005A);
2009 v2 = (s8) (tmp & 0x00FF);
2010 v3 = (s8) ((tmp & 0xFF00) >> 8);
2011 tmp = 0;
2012
2013 if (v0 == 0x7F || v1 == 0x7F || v2 == 0x7F
2014 || v3 == 0x7F) {
2015 tmp =
2016 b43_shm_read16(dev, B43_SHM_SHARED, 0x0070);
2017 v0 = (s8) (tmp & 0x00FF);
2018 v1 = (s8) ((tmp & 0xFF00) >> 8);
2019 tmp =
2020 b43_shm_read16(dev, B43_SHM_SHARED, 0x0072);
2021 v2 = (s8) (tmp & 0x00FF);
2022 v3 = (s8) ((tmp & 0xFF00) >> 8);
2023 if (v0 == 0x7F || v1 == 0x7F || v2 == 0x7F
2024 || v3 == 0x7F)
2025 return;
2026 v0 = (v0 + 0x20) & 0x3F;
2027 v1 = (v1 + 0x20) & 0x3F;
2028 v2 = (v2 + 0x20) & 0x3F;
2029 v3 = (v3 + 0x20) & 0x3F;
2030 tmp = 1;
2031 }
2032 b43_shm_clear_tssi(dev);
2033
2034 average = (v0 + v1 + v2 + v3 + 2) / 4;
2035
2036 if (tmp
2037 && (b43_shm_read16(dev, B43_SHM_SHARED, 0x005E) &
2038 0x8))
2039 average -= 13;
2040
2041 estimated_pwr =
2042 b43_phy_estimate_power_out(dev, average);
2043
2044 max_pwr = dev->dev->bus->sprom.r1.maxpwr_bg;
2045 if ((dev->dev->bus->sprom.r1.
2046 boardflags_lo & B43_BFL_PACTRL)
2047 && (phy->type == B43_PHYTYPE_G))
2048 max_pwr -= 0x3;
2049 if (unlikely(max_pwr <= 0)) {
2050 b43warn(dev->wl,
2051 "Invalid max-TX-power value in SPROM.\n");
2052 max_pwr = 60; /* fake it */
2053 dev->dev->bus->sprom.r1.maxpwr_bg = max_pwr;
2054 }
2055
2056 /*TODO:
2057 max_pwr = min(REG - dev->dev->bus->sprom.antennagain_bgphy - 0x6, max_pwr)
2058 where REG is the max power as per the regulatory domain
2059 */
2060
2061 /* Get desired power (in Q5.2) */
2062 desired_pwr = INT_TO_Q52(phy->power_level);
2063 /* And limit it. max_pwr already is Q5.2 */
2064 desired_pwr = limit_value(desired_pwr, 0, max_pwr);
2065 if (b43_debug(dev, B43_DBG_XMITPOWER)) {
2066 b43dbg(dev->wl,
2067 "Current TX power output: " Q52_FMT
2068 " dBm, " "Desired TX power output: "
2069 Q52_FMT " dBm\n", Q52_ARG(estimated_pwr),
2070 Q52_ARG(desired_pwr));
2071 }
2072
2073 /* Calculate the adjustment delta. */
2074 pwr_adjust = desired_pwr - estimated_pwr;
2075
2076 /* RF attenuation delta. */
2077 rfatt_delta = ((pwr_adjust + 7) / 8);
2078 /* Lower attenuation => Bigger power output. Negate it. */
2079 rfatt_delta = -rfatt_delta;
2080
2081 /* Baseband attenuation delta. */
2082 bbatt_delta = pwr_adjust / 2;
2083 /* Lower attenuation => Bigger power output. Negate it. */
2084 bbatt_delta = -bbatt_delta;
2085 /* RF att affects power level 4 times as much as
2086 * Baseband attennuation. Subtract it. */
2087 bbatt_delta -= 4 * rfatt_delta;
2088
2089 /* So do we finally need to adjust something? */
2090 if ((rfatt_delta == 0) && (bbatt_delta == 0)) {
2091 b43_lo_g_ctl_mark_cur_used(dev);
2092 return;
2093 }
2094
2095 /* Calculate the new attenuation values. */
2096 bbatt = phy->bbatt.att;
2097 bbatt += bbatt_delta;
2098 rfatt = phy->rfatt.att;
2099 rfatt += rfatt_delta;
2100
2101 b43_put_attenuation_into_ranges(dev, &bbatt, &rfatt);
2102 tx_control = phy->tx_control;
2103 if ((phy->radio_ver == 0x2050) && (phy->radio_rev == 2)) {
2104 if (rfatt <= 1) {
2105 if (tx_control == 0) {
2106 tx_control =
2107 B43_TXCTL_PA2DB |
2108 B43_TXCTL_TXMIX;
2109 rfatt += 2;
2110 bbatt += 2;
2111 } else if (dev->dev->bus->sprom.r1.
2112 boardflags_lo &
2113 B43_BFL_PACTRL) {
2114 bbatt += 4 * (rfatt - 2);
2115 rfatt = 2;
2116 }
2117 } else if (rfatt > 4 && tx_control) {
2118 tx_control = 0;
2119 if (bbatt < 3) {
2120 rfatt -= 3;
2121 bbatt += 2;
2122 } else {
2123 rfatt -= 2;
2124 bbatt -= 2;
2125 }
2126 }
2127 }
2128 /* Save the control values */
2129 phy->tx_control = tx_control;
2130 b43_put_attenuation_into_ranges(dev, &bbatt, &rfatt);
2131 phy->rfatt.att = rfatt;
2132 phy->bbatt.att = bbatt;
2133
2134 /* Adjust the hardware */
2135 b43_phy_lock(dev, phylock_flags);
2136 b43_radio_lock(dev);
2137 b43_set_txpower_g(dev, &phy->bbatt, &phy->rfatt,
2138 phy->tx_control);
2139 b43_lo_g_ctl_mark_cur_used(dev);
2140 b43_radio_unlock(dev);
2141 b43_phy_unlock(dev, phylock_flags);
2142 break;
2143 }
2144 default:
2145 B43_WARN_ON(1);
2146 }
2147 }
2148
2149 static inline s32 b43_tssi2dbm_ad(s32 num, s32 den)
2150 {
2151 if (num < 0)
2152 return num / den;
2153 else
2154 return (num + den / 2) / den;
2155 }
2156
2157 static inline
2158 s8 b43_tssi2dbm_entry(s8 entry[], u8 index, s16 pab0, s16 pab1, s16 pab2)
2159 {
2160 s32 m1, m2, f = 256, q, delta;
2161 s8 i = 0;
2162
2163 m1 = b43_tssi2dbm_ad(16 * pab0 + index * pab1, 32);
2164 m2 = max(b43_tssi2dbm_ad(32768 + index * pab2, 256), 1);
2165 do {
2166 if (i > 15)
2167 return -EINVAL;
2168 q = b43_tssi2dbm_ad(f * 4096 -
2169 b43_tssi2dbm_ad(m2 * f, 16) * f, 2048);
2170 delta = abs(q - f);
2171 f = q;
2172 i++;
2173 } while (delta >= 2);
2174 entry[index] = limit_value(b43_tssi2dbm_ad(m1 * f, 8192), -127, 128);
2175 return 0;
2176 }
2177
2178 /* http://bcm-specs.sipsolutions.net/TSSI_to_DBM_Table */
2179 int b43_phy_init_tssi2dbm_table(struct b43_wldev *dev)
2180 {
2181 struct b43_phy *phy = &dev->phy;
2182 s16 pab0, pab1, pab2;
2183 u8 idx;
2184 s8 *dyn_tssi2dbm;
2185
2186 if (phy->type == B43_PHYTYPE_A) {
2187 pab0 = (s16) (dev->dev->bus->sprom.r1.pa1b0);
2188 pab1 = (s16) (dev->dev->bus->sprom.r1.pa1b1);
2189 pab2 = (s16) (dev->dev->bus->sprom.r1.pa1b2);
2190 } else {
2191 pab0 = (s16) (dev->dev->bus->sprom.r1.pa0b0);
2192 pab1 = (s16) (dev->dev->bus->sprom.r1.pa0b1);
2193 pab2 = (s16) (dev->dev->bus->sprom.r1.pa0b2);
2194 }
2195
2196 if ((dev->dev->bus->chip_id == 0x4301) && (phy->radio_ver != 0x2050)) {
2197 phy->tgt_idle_tssi = 0x34;
2198 phy->tssi2dbm = b43_tssi2dbm_b_table;
2199 return 0;
2200 }
2201
2202 if (pab0 != 0 && pab1 != 0 && pab2 != 0 &&
2203 pab0 != -1 && pab1 != -1 && pab2 != -1) {
2204 /* The pabX values are set in SPROM. Use them. */
2205 if (phy->type == B43_PHYTYPE_A) {
2206 if ((s8) dev->dev->bus->sprom.r1.itssi_a != 0 &&
2207 (s8) dev->dev->bus->sprom.r1.itssi_a != -1)
2208 phy->tgt_idle_tssi =
2209 (s8) (dev->dev->bus->sprom.r1.itssi_a);
2210 else
2211 phy->tgt_idle_tssi = 62;
2212 } else {
2213 if ((s8) dev->dev->bus->sprom.r1.itssi_bg != 0 &&
2214 (s8) dev->dev->bus->sprom.r1.itssi_bg != -1)
2215 phy->tgt_idle_tssi =
2216 (s8) (dev->dev->bus->sprom.r1.itssi_bg);
2217 else
2218 phy->tgt_idle_tssi = 62;
2219 }
2220 dyn_tssi2dbm = kmalloc(64, GFP_KERNEL);
2221 if (dyn_tssi2dbm == NULL) {
2222 b43err(dev->wl, "Could not allocate memory"
2223 "for tssi2dbm table\n");
2224 return -ENOMEM;
2225 }
2226 for (idx = 0; idx < 64; idx++)
2227 if (b43_tssi2dbm_entry
2228 (dyn_tssi2dbm, idx, pab0, pab1, pab2)) {
2229 phy->tssi2dbm = NULL;
2230 b43err(dev->wl, "Could not generate "
2231 "tssi2dBm table\n");
2232 kfree(dyn_tssi2dbm);
2233 return -ENODEV;
2234 }
2235 phy->tssi2dbm = dyn_tssi2dbm;
2236 phy->dyn_tssi_tbl = 1;
2237 } else {
2238 /* pabX values not set in SPROM. */
2239 switch (phy->type) {
2240 case B43_PHYTYPE_A:
2241 /* APHY needs a generated table. */
2242 phy->tssi2dbm = NULL;
2243 b43err(dev->wl, "Could not generate tssi2dBm "
2244 "table (wrong SPROM info)!\n");
2245 return -ENODEV;
2246 case B43_PHYTYPE_B:
2247 phy->tgt_idle_tssi = 0x34;
2248 phy->tssi2dbm = b43_tssi2dbm_b_table;
2249 break;
2250 case B43_PHYTYPE_G:
2251 phy->tgt_idle_tssi = 0x34;
2252 phy->tssi2dbm = b43_tssi2dbm_g_table;
2253 break;
2254 }
2255 }
2256
2257 return 0;
2258 }
2259
2260 int b43_phy_init(struct b43_wldev *dev)
2261 {
2262 struct b43_phy *phy = &dev->phy;
2263 int err = -ENODEV;
2264
2265 switch (phy->type) {
2266 case B43_PHYTYPE_A:
2267 if (phy->rev == 2 || phy->rev == 3) {
2268 b43_phy_inita(dev);
2269 err = 0;
2270 }
2271 break;
2272 case B43_PHYTYPE_B:
2273 switch (phy->rev) {
2274 case 2:
2275 b43_phy_initb2(dev);
2276 err = 0;
2277 break;
2278 case 4:
2279 b43_phy_initb4(dev);
2280 err = 0;
2281 break;
2282 case 5:
2283 b43_phy_initb5(dev);
2284 err = 0;
2285 break;
2286 case 6:
2287 b43_phy_initb6(dev);
2288 err = 0;
2289 break;
2290 }
2291 break;
2292 case B43_PHYTYPE_G:
2293 b43_phy_initg(dev);
2294 err = 0;
2295 break;
2296 }
2297 if (err)
2298 b43err(dev->wl, "Unknown PHYTYPE found\n");
2299
2300 return err;
2301 }
2302
2303 void b43_set_rx_antenna(struct b43_wldev *dev, int antenna)
2304 {
2305 struct b43_phy *phy = &dev->phy;
2306 u32 hf;
2307 u16 tmp;
2308 int autodiv = 0;
2309
2310 if (antenna == B43_ANTENNA_AUTO0 || antenna == B43_ANTENNA_AUTO1)
2311 autodiv = 1;
2312
2313 hf = b43_hf_read(dev);
2314 hf &= ~B43_HF_ANTDIVHELP;
2315 b43_hf_write(dev, hf);
2316
2317 switch (phy->type) {
2318 case B43_PHYTYPE_A:
2319 case B43_PHYTYPE_G:
2320 tmp = b43_phy_read(dev, B43_PHY_BBANDCFG);
2321 tmp &= ~B43_PHY_BBANDCFG_RXANT;
2322 tmp |= (autodiv ? B43_ANTENNA_AUTO0 : antenna)
2323 << B43_PHY_BBANDCFG_RXANT_SHIFT;
2324 b43_phy_write(dev, B43_PHY_BBANDCFG, tmp);
2325
2326 if (autodiv) {
2327 tmp = b43_phy_read(dev, B43_PHY_ANTDWELL);
2328 if (antenna == B43_ANTENNA_AUTO0)
2329 tmp &= ~B43_PHY_ANTDWELL_AUTODIV1;
2330 else
2331 tmp |= B43_PHY_ANTDWELL_AUTODIV1;
2332 b43_phy_write(dev, B43_PHY_ANTDWELL, tmp);
2333 }
2334 if (phy->type == B43_PHYTYPE_G) {
2335 tmp = b43_phy_read(dev, B43_PHY_ANTWRSETT);
2336 if (autodiv)
2337 tmp |= B43_PHY_ANTWRSETT_ARXDIV;
2338 else
2339 tmp &= ~B43_PHY_ANTWRSETT_ARXDIV;
2340 b43_phy_write(dev, B43_PHY_ANTWRSETT, tmp);
2341 if (phy->rev >= 2) {
2342 tmp = b43_phy_read(dev, B43_PHY_OFDM61);
2343 tmp |= B43_PHY_OFDM61_10;
2344 b43_phy_write(dev, B43_PHY_OFDM61, tmp);
2345
2346 tmp =
2347 b43_phy_read(dev, B43_PHY_DIVSRCHGAINBACK);
2348 tmp = (tmp & 0xFF00) | 0x15;
2349 b43_phy_write(dev, B43_PHY_DIVSRCHGAINBACK,
2350 tmp);
2351
2352 if (phy->rev == 2) {
2353 b43_phy_write(dev, B43_PHY_ADIVRELATED,
2354 8);
2355 } else {
2356 tmp =
2357 b43_phy_read(dev,
2358 B43_PHY_ADIVRELATED);
2359 tmp = (tmp & 0xFF00) | 8;
2360 b43_phy_write(dev, B43_PHY_ADIVRELATED,
2361 tmp);
2362 }
2363 }
2364 if (phy->rev >= 6)
2365 b43_phy_write(dev, B43_PHY_OFDM9B, 0xDC);
2366 } else {
2367 if (phy->rev < 3) {
2368 tmp = b43_phy_read(dev, B43_PHY_ANTDWELL);
2369 tmp = (tmp & 0xFF00) | 0x24;
2370 b43_phy_write(dev, B43_PHY_ANTDWELL, tmp);
2371 } else {
2372 tmp = b43_phy_read(dev, B43_PHY_OFDM61);
2373 tmp |= 0x10;
2374 b43_phy_write(dev, B43_PHY_OFDM61, tmp);
2375 if (phy->analog == 3) {
2376 b43_phy_write(dev, B43_PHY_CLIPPWRDOWNT,
2377 0x1D);
2378 b43_phy_write(dev, B43_PHY_ADIVRELATED,
2379 8);
2380 } else {
2381 b43_phy_write(dev, B43_PHY_CLIPPWRDOWNT,
2382 0x3A);
2383 tmp =
2384 b43_phy_read(dev,
2385 B43_PHY_ADIVRELATED);
2386 tmp = (tmp & 0xFF00) | 8;
2387 b43_phy_write(dev, B43_PHY_ADIVRELATED,
2388 tmp);
2389 }
2390 }
2391 }
2392 break;
2393 case B43_PHYTYPE_B:
2394 tmp = b43_phy_read(dev, B43_PHY_CCKBBANDCFG);
2395 tmp &= ~B43_PHY_BBANDCFG_RXANT;
2396 tmp |= (autodiv ? B43_ANTENNA_AUTO0 : antenna)
2397 << B43_PHY_BBANDCFG_RXANT_SHIFT;
2398 b43_phy_write(dev, B43_PHY_CCKBBANDCFG, tmp);
2399 break;
2400 default:
2401 B43_WARN_ON(1);
2402 }
2403
2404 hf |= B43_HF_ANTDIVHELP;
2405 b43_hf_write(dev, hf);
2406 }
2407
2408 /* Get the freq, as it has to be written to the device. */
2409 static inline u16 channel2freq_bg(u8 channel)
2410 {
2411 B43_WARN_ON(!(channel >= 1 && channel <= 14));
2412
2413 return b43_radio_channel_codes_bg[channel - 1];
2414 }
2415
2416 /* Get the freq, as it has to be written to the device. */
2417 static inline u16 channel2freq_a(u8 channel)
2418 {
2419 B43_WARN_ON(channel > 200);
2420
2421 return (5000 + 5 * channel);
2422 }
2423
2424 void b43_radio_lock(struct b43_wldev *dev)
2425 {
2426 u32 macctl;
2427
2428 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2429 macctl |= B43_MACCTL_RADIOLOCK;
2430 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2431 /* Commit the write and wait for the device
2432 * to exit any radio register access. */
2433 b43_read32(dev, B43_MMIO_MACCTL);
2434 udelay(10);
2435 }
2436
2437 void b43_radio_unlock(struct b43_wldev *dev)
2438 {
2439 u32 macctl;
2440
2441 /* Commit any write */
2442 b43_read16(dev, B43_MMIO_PHY_VER);
2443 /* unlock */
2444 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2445 macctl &= ~B43_MACCTL_RADIOLOCK;
2446 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2447 }
2448
2449 u16 b43_radio_read16(struct b43_wldev *dev, u16 offset)
2450 {
2451 struct b43_phy *phy = &dev->phy;
2452
2453 switch (phy->type) {
2454 case B43_PHYTYPE_A:
2455 offset |= 0x0040;
2456 break;
2457 case B43_PHYTYPE_B:
2458 if (phy->radio_ver == 0x2053) {
2459 if (offset < 0x70)
2460 offset += 0x80;
2461 else if (offset < 0x80)
2462 offset += 0x70;
2463 } else if (phy->radio_ver == 0x2050) {
2464 offset |= 0x80;
2465 } else
2466 B43_WARN_ON(1);
2467 break;
2468 case B43_PHYTYPE_G:
2469 offset |= 0x80;
2470 break;
2471 }
2472
2473 b43_write16(dev, B43_MMIO_RADIO_CONTROL, offset);
2474 return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
2475 }
2476
2477 void b43_radio_write16(struct b43_wldev *dev, u16 offset, u16 val)
2478 {
2479 b43_write16(dev, B43_MMIO_RADIO_CONTROL, offset);
2480 mmiowb();
2481 b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, val);
2482 }
2483
2484 static void b43_set_all_gains(struct b43_wldev *dev,
2485 s16 first, s16 second, s16 third)
2486 {
2487 struct b43_phy *phy = &dev->phy;
2488 u16 i;
2489 u16 start = 0x08, end = 0x18;
2490 u16 tmp;
2491 u16 table;
2492
2493 if (phy->rev <= 1) {
2494 start = 0x10;
2495 end = 0x20;
2496 }
2497
2498 table = B43_OFDMTAB_GAINX;
2499 if (phy->rev <= 1)
2500 table = B43_OFDMTAB_GAINX_R1;
2501 for (i = 0; i < 4; i++)
2502 b43_ofdmtab_write16(dev, table, i, first);
2503
2504 for (i = start; i < end; i++)
2505 b43_ofdmtab_write16(dev, table, i, second);
2506
2507 if (third != -1) {
2508 tmp = ((u16) third << 14) | ((u16) third << 6);
2509 b43_phy_write(dev, 0x04A0,
2510 (b43_phy_read(dev, 0x04A0) & 0xBFBF) | tmp);
2511 b43_phy_write(dev, 0x04A1,
2512 (b43_phy_read(dev, 0x04A1) & 0xBFBF) | tmp);
2513 b43_phy_write(dev, 0x04A2,
2514 (b43_phy_read(dev, 0x04A2) & 0xBFBF) | tmp);
2515 }
2516 b43_dummy_transmission(dev);
2517 }
2518
2519 static void b43_set_original_gains(struct b43_wldev *dev)
2520 {
2521 struct b43_phy *phy = &dev->phy;
2522 u16 i, tmp;
2523 u16 table;
2524 u16 start = 0x0008, end = 0x0018;
2525
2526 if (phy->rev <= 1) {
2527 start = 0x0010;
2528 end = 0x0020;
2529 }
2530
2531 table = B43_OFDMTAB_GAINX;
2532 if (phy->rev <= 1)
2533 table = B43_OFDMTAB_GAINX_R1;
2534 for (i = 0; i < 4; i++) {
2535 tmp = (i & 0xFFFC);
2536 tmp |= (i & 0x0001) << 1;
2537 tmp |= (i & 0x0002) >> 1;
2538
2539 b43_ofdmtab_write16(dev, table, i, tmp);
2540 }
2541
2542 for (i = start; i < end; i++)
2543 b43_ofdmtab_write16(dev, table, i, i - start);
2544
2545 b43_phy_write(dev, 0x04A0,
2546 (b43_phy_read(dev, 0x04A0) & 0xBFBF) | 0x4040);
2547 b43_phy_write(dev, 0x04A1,
2548 (b43_phy_read(dev, 0x04A1) & 0xBFBF) | 0x4040);
2549 b43_phy_write(dev, 0x04A2,
2550 (b43_phy_read(dev, 0x04A2) & 0xBFBF) | 0x4000);
2551 b43_dummy_transmission(dev);
2552 }
2553
2554 /* Synthetic PU workaround */
2555 static void b43_synth_pu_workaround(struct b43_wldev *dev, u8 channel)
2556 {
2557 struct b43_phy *phy = &dev->phy;
2558
2559 might_sleep();
2560
2561 if (phy->radio_ver != 0x2050 || phy->radio_rev >= 6) {
2562 /* We do not need the workaround. */
2563 return;
2564 }
2565
2566 if (channel <= 10) {
2567 b43_write16(dev, B43_MMIO_CHANNEL,
2568 channel2freq_bg(channel + 4));
2569 } else {
2570 b43_write16(dev, B43_MMIO_CHANNEL, channel2freq_bg(1));
2571 }
2572 msleep(1);
2573 b43_write16(dev, B43_MMIO_CHANNEL, channel2freq_bg(channel));
2574 }
2575
2576 u8 b43_radio_aci_detect(struct b43_wldev *dev, u8 channel)
2577 {
2578 struct b43_phy *phy = &dev->phy;
2579 u8 ret = 0;
2580 u16 saved, rssi, temp;
2581 int i, j = 0;
2582
2583 saved = b43_phy_read(dev, 0x0403);
2584 b43_radio_selectchannel(dev, channel, 0);
2585 b43_phy_write(dev, 0x0403, (saved & 0xFFF8) | 5);
2586 if (phy->aci_hw_rssi)
2587 rssi = b43_phy_read(dev, 0x048A) & 0x3F;
2588 else
2589 rssi = saved & 0x3F;
2590 /* clamp temp to signed 5bit */
2591 if (rssi > 32)
2592 rssi -= 64;
2593 for (i = 0; i < 100; i++) {
2594 temp = (b43_phy_read(dev, 0x047F) >> 8) & 0x3F;
2595 if (temp > 32)
2596 temp -= 64;
2597 if (temp < rssi)
2598 j++;
2599 if (j >= 20)
2600 ret = 1;
2601 }
2602 b43_phy_write(dev, 0x0403, saved);
2603
2604 return ret;
2605 }
2606
2607 u8 b43_radio_aci_scan(struct b43_wldev * dev)
2608 {
2609 struct b43_phy *phy = &dev->phy;
2610 u8 ret[13];
2611 unsigned int channel = phy->channel;
2612 unsigned int i, j, start, end;
2613 unsigned long phylock_flags;
2614
2615 if (!((phy->type == B43_PHYTYPE_G) && (phy->rev > 0)))
2616 return 0;
2617
2618 b43_phy_lock(dev, phylock_flags);
2619 b43_radio_lock(dev);
2620 b43_phy_write(dev, 0x0802, b43_phy_read(dev, 0x0802) & 0xFFFC);
2621 b43_phy_write(dev, B43_PHY_G_CRS,
2622 b43_phy_read(dev, B43_PHY_G_CRS) & 0x7FFF);
2623 b43_set_all_gains(dev, 3, 8, 1);
2624
2625 start = (channel - 5 > 0) ? channel - 5 : 1;
2626 end = (channel + 5 < 14) ? channel + 5 : 13;
2627
2628 for (i = start; i <= end; i++) {
2629 if (abs(channel - i) > 2)
2630 ret[i - 1] = b43_radio_aci_detect(dev, i);
2631 }
2632 b43_radio_selectchannel(dev, channel, 0);
2633 b43_phy_write(dev, 0x0802,
2634 (b43_phy_read(dev, 0x0802) & 0xFFFC) | 0x0003);
2635 b43_phy_write(dev, 0x0403, b43_phy_read(dev, 0x0403) & 0xFFF8);
2636 b43_phy_write(dev, B43_PHY_G_CRS,
2637 b43_phy_read(dev, B43_PHY_G_CRS) | 0x8000);
2638 b43_set_original_gains(dev);
2639 for (i = 0; i < 13; i++) {
2640 if (!ret[i])
2641 continue;
2642 end = (i + 5 < 13) ? i + 5 : 13;
2643 for (j = i; j < end; j++)
2644 ret[j] = 1;
2645 }
2646 b43_radio_unlock(dev);
2647 b43_phy_unlock(dev, phylock_flags);
2648
2649 return ret[channel - 1];
2650 }
2651
2652 /* http://bcm-specs.sipsolutions.net/NRSSILookupTable */
2653 void b43_nrssi_hw_write(struct b43_wldev *dev, u16 offset, s16 val)
2654 {
2655 b43_phy_write(dev, B43_PHY_NRSSILT_CTRL, offset);
2656 mmiowb();
2657 b43_phy_write(dev, B43_PHY_NRSSILT_DATA, (u16) val);
2658 }
2659
2660 /* http://bcm-specs.sipsolutions.net/NRSSILookupTable */
2661 s16 b43_nrssi_hw_read(struct b43_wldev *dev, u16 offset)
2662 {
2663 u16 val;
2664
2665 b43_phy_write(dev, B43_PHY_NRSSILT_CTRL, offset);
2666 val = b43_phy_read(dev, B43_PHY_NRSSILT_DATA);
2667
2668 return (s16) val;
2669 }
2670
2671 /* http://bcm-specs.sipsolutions.net/NRSSILookupTable */
2672 void b43_nrssi_hw_update(struct b43_wldev *dev, u16 val)
2673 {
2674 u16 i;
2675 s16 tmp;
2676
2677 for (i = 0; i < 64; i++) {
2678 tmp = b43_nrssi_hw_read(dev, i);
2679 tmp -= val;
2680 tmp = limit_value(tmp, -32, 31);
2681 b43_nrssi_hw_write(dev, i, tmp);
2682 }
2683 }
2684
2685 /* http://bcm-specs.sipsolutions.net/NRSSILookupTable */
2686 void b43_nrssi_mem_update(struct b43_wldev *dev)
2687 {
2688 struct b43_phy *phy = &dev->phy;
2689 s16 i, delta;
2690 s32 tmp;
2691
2692 delta = 0x1F - phy->nrssi[0];
2693 for (i = 0; i < 64; i++) {
2694 tmp = (i - delta) * phy->nrssislope;
2695 tmp /= 0x10000;
2696 tmp += 0x3A;
2697 tmp = limit_value(tmp, 0, 0x3F);
2698 phy->nrssi_lt[i] = tmp;
2699 }
2700 }
2701
2702 static void b43_calc_nrssi_offset(struct b43_wldev *dev)
2703 {
2704 struct b43_phy *phy = &dev->phy;
2705 u16 backup[20] = { 0 };
2706 s16 v47F;
2707 u16 i;
2708 u16 saved = 0xFFFF;
2709
2710 backup[0] = b43_phy_read(dev, 0x0001);
2711 backup[1] = b43_phy_read(dev, 0x0811);
2712 backup[2] = b43_phy_read(dev, 0x0812);
2713 if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */
2714 backup[3] = b43_phy_read(dev, 0x0814);
2715 backup[4] = b43_phy_read(dev, 0x0815);
2716 }
2717 backup[5] = b43_phy_read(dev, 0x005A);
2718 backup[6] = b43_phy_read(dev, 0x0059);
2719 backup[7] = b43_phy_read(dev, 0x0058);
2720 backup[8] = b43_phy_read(dev, 0x000A);
2721 backup[9] = b43_phy_read(dev, 0x0003);
2722 backup[10] = b43_radio_read16(dev, 0x007A);
2723 backup[11] = b43_radio_read16(dev, 0x0043);
2724
2725 b43_phy_write(dev, 0x0429, b43_phy_read(dev, 0x0429) & 0x7FFF);
2726 b43_phy_write(dev, 0x0001,
2727 (b43_phy_read(dev, 0x0001) & 0x3FFF) | 0x4000);
2728 b43_phy_write(dev, 0x0811, b43_phy_read(dev, 0x0811) | 0x000C);
2729 b43_phy_write(dev, 0x0812,
2730 (b43_phy_read(dev, 0x0812) & 0xFFF3) | 0x0004);
2731 b43_phy_write(dev, 0x0802, b43_phy_read(dev, 0x0802) & ~(0x1 | 0x2));
2732 if (phy->rev >= 6) {
2733 backup[12] = b43_phy_read(dev, 0x002E);
2734 backup[13] = b43_phy_read(dev, 0x002F);
2735 backup[14] = b43_phy_read(dev, 0x080F);
2736 backup[15] = b43_phy_read(dev, 0x0810);
2737 backup[16] = b43_phy_read(dev, 0x0801);
2738 backup[17] = b43_phy_read(dev, 0x0060);
2739 backup[18] = b43_phy_read(dev, 0x0014);
2740 backup[19] = b43_phy_read(dev, 0x0478);
2741
2742 b43_phy_write(dev, 0x002E, 0);
2743 b43_phy_write(dev, 0x002F, 0);
2744 b43_phy_write(dev, 0x080F, 0);
2745 b43_phy_write(dev, 0x0810, 0);
2746 b43_phy_write(dev, 0x0478, b43_phy_read(dev, 0x0478) | 0x0100);
2747 b43_phy_write(dev, 0x0801, b43_phy_read(dev, 0x0801) | 0x0040);
2748 b43_phy_write(dev, 0x0060, b43_phy_read(dev, 0x0060) | 0x0040);
2749 b43_phy_write(dev, 0x0014, b43_phy_read(dev, 0x0014) | 0x0200);
2750 }
2751 b43_radio_write16(dev, 0x007A, b43_radio_read16(dev, 0x007A) | 0x0070);
2752 b43_radio_write16(dev, 0x007A, b43_radio_read16(dev, 0x007A) | 0x0080);
2753 udelay(30);
2754
2755 v47F = (s16) ((b43_phy_read(dev, 0x047F) >> 8) & 0x003F);
2756 if (v47F >= 0x20)
2757 v47F -= 0x40;
2758 if (v47F == 31) {
2759 for (i = 7; i >= 4; i--) {
2760 b43_radio_write16(dev, 0x007B, i);
2761 udelay(20);
2762 v47F =
2763 (s16) ((b43_phy_read(dev, 0x047F) >> 8) & 0x003F);
2764 if (v47F >= 0x20)
2765 v47F -= 0x40;
2766 if (v47F < 31 && saved == 0xFFFF)
2767 saved = i;
2768 }
2769 if (saved == 0xFFFF)
2770 saved = 4;
2771 } else {
2772 b43_radio_write16(dev, 0x007A,
2773 b43_radio_read16(dev, 0x007A) & 0x007F);
2774 if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */
2775 b43_phy_write(dev, 0x0814,
2776 b43_phy_read(dev, 0x0814) | 0x0001);
2777 b43_phy_write(dev, 0x0815,
2778 b43_phy_read(dev, 0x0815) & 0xFFFE);
2779 }
2780 b43_phy_write(dev, 0x0811, b43_phy_read(dev, 0x0811) | 0x000C);
2781 b43_phy_write(dev, 0x0812, b43_phy_read(dev, 0x0812) | 0x000C);
2782 b43_phy_write(dev, 0x0811, b43_phy_read(dev, 0x0811) | 0x0030);
2783 b43_phy_write(dev, 0x0812, b43_phy_read(dev, 0x0812) | 0x0030);
2784 b43_phy_write(dev, 0x005A, 0x0480);
2785 b43_phy_write(dev, 0x0059, 0x0810);
2786 b43_phy_write(dev, 0x0058, 0x000D);
2787 if (phy->rev == 0) {
2788 b43_phy_write(dev, 0x0003, 0x0122);
2789 } else {
2790 b43_phy_write(dev, 0x000A, b43_phy_read(dev, 0x000A)
2791 | 0x2000);
2792 }
2793 if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */
2794 b43_phy_write(dev, 0x0814,
2795 b43_phy_read(dev, 0x0814) | 0x0004);
2796 b43_phy_write(dev, 0x0815,
2797 b43_phy_read(dev, 0x0815) & 0xFFFB);
2798 }
2799 b43_phy_write(dev, 0x0003, (b43_phy_read(dev, 0x0003) & 0xFF9F)
2800 | 0x0040);
2801 b43_radio_write16(dev, 0x007A,
2802 b43_radio_read16(dev, 0x007A) | 0x000F);
2803 b43_set_all_gains(dev, 3, 0, 1);
2804 b43_radio_write16(dev, 0x0043, (b43_radio_read16(dev, 0x0043)
2805 & 0x00F0) | 0x000F);
2806 udelay(30);
2807 v47F = (s16) ((b43_phy_read(dev, 0x047F) >> 8) & 0x003F);
2808 if (v47F >= 0x20)
2809 v47F -= 0x40;
2810 if (v47F == -32) {
2811 for (i = 0; i < 4; i++) {
2812 b43_radio_write16(dev, 0x007B, i);
2813 udelay(20);
2814 v47F =
2815 (s16) ((b43_phy_read(dev, 0x047F) >> 8) &
2816 0x003F);
2817 if (v47F >= 0x20)
2818 v47F -= 0x40;
2819 if (v47F > -31 && saved == 0xFFFF)
2820 saved = i;
2821 }
2822 if (saved == 0xFFFF)
2823 saved = 3;
2824 } else
2825 saved = 0;
2826 }
2827 b43_radio_write16(dev, 0x007B, saved);
2828
2829 if (phy->rev >= 6) {
2830 b43_phy_write(dev, 0x002E, backup[12]);
2831 b43_phy_write(dev, 0x002F, backup[13]);
2832 b43_phy_write(dev, 0x080F, backup[14]);
2833 b43_phy_write(dev, 0x0810, backup[15]);
2834 }
2835 if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */
2836 b43_phy_write(dev, 0x0814, backup[3]);
2837 b43_phy_write(dev, 0x0815, backup[4]);
2838 }
2839 b43_phy_write(dev, 0x005A, backup[5]);
2840 b43_phy_write(dev, 0x0059, backup[6]);
2841 b43_phy_write(dev, 0x0058, backup[7]);
2842 b43_phy_write(dev, 0x000A, backup[8]);
2843 b43_phy_write(dev, 0x0003, backup[9]);
2844 b43_radio_write16(dev, 0x0043, backup[11]);
2845 b43_radio_write16(dev, 0x007A, backup[10]);
2846 b43_phy_write(dev, 0x0802, b43_phy_read(dev, 0x0802) | 0x1 | 0x2);
2847 b43_phy_write(dev, 0x0429, b43_phy_read(dev, 0x0429) | 0x8000);
2848 b43_set_original_gains(dev);
2849 if (phy->rev >= 6) {
2850 b43_phy_write(dev, 0x0801, backup[16]);
2851 b43_phy_write(dev, 0x0060, backup[17]);
2852 b43_phy_write(dev, 0x0014, backup[18]);
2853 b43_phy_write(dev, 0x0478, backup[19]);
2854 }
2855 b43_phy_write(dev, 0x0001, backup[0]);
2856 b43_phy_write(dev, 0x0812, backup[2]);
2857 b43_phy_write(dev, 0x0811, backup[1]);
2858 }
2859
2860 void b43_calc_nrssi_slope(struct b43_wldev *dev)
2861 {
2862 struct b43_phy *phy = &dev->phy;
2863 u16 backup[18] = { 0 };
2864 u16 tmp;
2865 s16 nrssi0, nrssi1;
2866
2867 switch (phy->type) {
2868 case B43_PHYTYPE_B:
2869 backup[0] = b43_radio_read16(dev, 0x007A);
2870 backup[1] = b43_radio_read16(dev, 0x0052);
2871 backup[2] = b43_radio_read16(dev, 0x0043);
2872 backup[3] = b43_phy_read(dev, 0x0030);
2873 backup[4] = b43_phy_read(dev, 0x0026);
2874 backup[5] = b43_phy_read(dev, 0x0015);
2875 backup[6] = b43_phy_read(dev, 0x002A);
2876 backup[7] = b43_phy_read(dev, 0x0020);
2877 backup[8] = b43_phy_read(dev, 0x005A);
2878 backup[9] = b43_phy_read(dev, 0x0059);
2879 backup[10] = b43_phy_read(dev, 0x0058);
2880 backup[11] = b43_read16(dev, 0x03E2);
2881 backup[12] = b43_read16(dev, 0x03E6);
2882 backup[13] = b43_read16(dev, B43_MMIO_CHANNEL_EXT);
2883
2884 tmp = b43_radio_read16(dev, 0x007A);
2885 tmp &= (phy->rev >= 5) ? 0x007F : 0x000F;
2886 b43_radio_write16(dev, 0x007A, tmp);
2887 b43_phy_write(dev, 0x0030, 0x00FF);
2888 b43_write16(dev, 0x03EC, 0x7F7F);
2889 b43_phy_write(dev, 0x0026, 0x0000);
2890 b43_phy_write(dev, 0x0015, b43_phy_read(dev, 0x0015) | 0x0020);
2891 b43_phy_write(dev, 0x002A, 0x08A3);
2892 b43_radio_write16(dev, 0x007A,
2893 b43_radio_read16(dev, 0x007A) | 0x0080);
2894
2895 nrssi0 = (s16) b43_phy_read(dev, 0x0027);
2896 b43_radio_write16(dev, 0x007A,
2897 b43_radio_read16(dev, 0x007A) & 0x007F);
2898 if (phy->rev >= 2) {
2899 b43_write16(dev, 0x03E6, 0x0040);
2900 } else if (phy->rev == 0) {
2901 b43_write16(dev, 0x03E6, 0x0122);
2902 } else {
2903 b43_write16(dev, B43_MMIO_CHANNEL_EXT,
2904 b43_read16(dev,
2905 B43_MMIO_CHANNEL_EXT) & 0x2000);
2906 }
2907 b43_phy_write(dev, 0x0020, 0x3F3F);
2908 b43_phy_write(dev, 0x0015, 0xF330);
2909 b43_radio_write16(dev, 0x005A, 0x0060);
2910 b43_radio_write16(dev, 0x0043,
2911 b43_radio_read16(dev, 0x0043) & 0x00F0);
2912 b43_phy_write(dev, 0x005A, 0x0480);
2913 b43_phy_write(dev, 0x0059, 0x0810);
2914 b43_phy_write(dev, 0x0058, 0x000D);
2915 udelay(20);
2916
2917 nrssi1 = (s16) b43_phy_read(dev, 0x0027);
2918 b43_phy_write(dev, 0x0030, backup[3]);
2919 b43_radio_write16(dev, 0x007A, backup[0]);
2920 b43_write16(dev, 0x03E2, backup[11]);
2921 b43_phy_write(dev, 0x0026, backup[4]);
2922 b43_phy_write(dev, 0x0015, backup[5]);
2923 b43_phy_write(dev, 0x002A, backup[6]);
2924 b43_synth_pu_workaround(dev, phy->channel);
2925 if (phy->rev != 0)
2926 b43_write16(dev, 0x03F4, backup[13]);
2927
2928 b43_phy_write(dev, 0x0020, backup[7]);
2929 b43_phy_write(dev, 0x005A, backup[8]);
2930 b43_phy_write(dev, 0x0059, backup[9]);
2931 b43_phy_write(dev, 0x0058, backup[10]);
2932 b43_radio_write16(dev, 0x0052, backup[1]);
2933 b43_radio_write16(dev, 0x0043, backup[2]);
2934
2935 if (nrssi0 == nrssi1)
2936 phy->nrssislope = 0x00010000;
2937 else
2938 phy->nrssislope = 0x00400000 / (nrssi0 - nrssi1);
2939
2940 if (nrssi0 <= -4) {
2941 phy->nrssi[0] = nrssi0;
2942 phy->nrssi[1] = nrssi1;
2943 }
2944 break;
2945 case B43_PHYTYPE_G:
2946 if (phy->radio_rev >= 9)
2947 return;
2948 if (phy->radio_rev == 8)
2949 b43_calc_nrssi_offset(dev);
2950
2951 b43_phy_write(dev, B43_PHY_G_CRS,
2952 b43_phy_read(dev, B43_PHY_G_CRS) & 0x7FFF);
2953 b43_phy_write(dev, 0x0802, b43_phy_read(dev, 0x0802) & 0xFFFC);
2954 backup[7] = b43_read16(dev, 0x03E2);
2955 b43_write16(dev, 0x03E2, b43_read16(dev, 0x03E2) | 0x8000);
2956 backup[0] = b43_radio_read16(dev, 0x007A);
2957 backup[1] = b43_radio_read16(dev, 0x0052);
2958 backup[2] = b43_radio_read16(dev, 0x0043);
2959 backup[3] = b43_phy_read(dev, 0x0015);
2960 backup[4] = b43_phy_read(dev, 0x005A);
2961 backup[5] = b43_phy_read(dev, 0x0059);
2962 backup[6] = b43_phy_read(dev, 0x0058);
2963 backup[8] = b43_read16(dev, 0x03E6);
2964 backup[9] = b43_read16(dev, B43_MMIO_CHANNEL_EXT);
2965 if (phy->rev >= 3) {
2966 backup[10] = b43_phy_read(dev, 0x002E);
2967 backup[11] = b43_phy_read(dev, 0x002F);
2968 backup[12] = b43_phy_read(dev, 0x080F);
2969 backup[13] = b43_phy_read(dev, B43_PHY_G_LO_CONTROL);
2970 backup[14] = b43_phy_read(dev, 0x0801);
2971 backup[15] = b43_phy_read(dev, 0x0060);
2972 backup[16] = b43_phy_read(dev, 0x0014);
2973 backup[17] = b43_phy_read(dev, 0x0478);
2974 b43_phy_write(dev, 0x002E, 0);
2975 b43_phy_write(dev, B43_PHY_G_LO_CONTROL, 0);
2976 switch (phy->rev) {
2977 case 4:
2978 case 6:
2979 case 7:
2980 b43_phy_write(dev, 0x0478,
2981 b43_phy_read(dev, 0x0478)
2982 | 0x0100);
2983 b43_phy_write(dev, 0x0801,
2984 b43_phy_read(dev, 0x0801)
2985 | 0x0040);
2986 break;
2987 case 3:
2988 case 5:
2989 b43_phy_write(dev, 0x0801,
2990 b43_phy_read(dev, 0x0801)
2991 & 0xFFBF);
2992 break;
2993 }
2994 b43_phy_write(dev, 0x0060, b43_phy_read(dev, 0x0060)
2995 | 0x0040);
2996 b43_phy_write(dev, 0x0014, b43_phy_read(dev, 0x0014)
2997 | 0x0200);
2998 }
2999 b43_radio_write16(dev, 0x007A,
3000 b43_radio_read16(dev, 0x007A) | 0x0070);
3001 b43_set_all_gains(dev, 0, 8, 0);
3002 b43_radio_write16(dev, 0x007A,
3003 b43_radio_read16(dev, 0x007A) & 0x00F7);
3004 if (phy->rev >= 2) {
3005 b43_phy_write(dev, 0x0811,
3006 (b43_phy_read(dev, 0x0811) & 0xFFCF) |
3007 0x0030);
3008 b43_phy_write(dev, 0x0812,
3009 (b43_phy_read(dev, 0x0812) & 0xFFCF) |
3010 0x0010);
3011 }
3012 b43_radio_write16(dev, 0x007A,
3013 b43_radio_read16(dev, 0x007A) | 0x0080);
3014 udelay(20);
3015
3016 nrssi0 = (s16) ((b43_phy_read(dev, 0x047F) >> 8) & 0x003F);
3017 if (nrssi0 >= 0x0020)
3018 nrssi0 -= 0x0040;
3019
3020 b43_radio_write16(dev, 0x007A,
3021 b43_radio_read16(dev, 0x007A) & 0x007F);
3022 if (phy->rev >= 2) {
3023 b43_phy_write(dev, 0x0003, (b43_phy_read(dev, 0x0003)
3024 & 0xFF9F) | 0x0040);
3025 }
3026
3027 b43_write16(dev, B43_MMIO_CHANNEL_EXT,
3028 b43_read16(dev, B43_MMIO_CHANNEL_EXT)
3029 | 0x2000);
3030 b43_radio_write16(dev, 0x007A,
3031 b43_radio_read16(dev, 0x007A) | 0x000F);
3032 b43_phy_write(dev, 0x0015, 0xF330);
3033 if (phy->rev >= 2) {
3034 b43_phy_write(dev, 0x0812,
3035 (b43_phy_read(dev, 0x0812) & 0xFFCF) |
3036 0x0020);
3037 b43_phy_write(dev, 0x0811,
3038 (b43_phy_read(dev, 0x0811) & 0xFFCF) |
3039 0x0020);
3040 }
3041
3042 b43_set_all_gains(dev, 3, 0, 1);
3043 if (phy->radio_rev == 8) {
3044 b43_radio_write16(dev, 0x0043, 0x001F);
3045 } else {
3046 tmp = b43_radio_read16(dev, 0x0052) & 0xFF0F;
3047 b43_radio_write16(dev, 0x0052, tmp | 0x0060);
3048 tmp = b43_radio_read16(dev, 0x0043) & 0xFFF0;
3049 b43_radio_write16(dev, 0x0043, tmp | 0x0009);
3050 }
3051 b43_phy_write(dev, 0x005A, 0x0480);
3052 b43_phy_write(dev, 0x0059, 0x0810);
3053 b43_phy_write(dev, 0x0058, 0x000D);
3054 udelay(20);
3055 nrssi1 = (s16) ((b43_phy_read(dev, 0x047F) >> 8) & 0x003F);
3056 if (nrssi1 >= 0x0020)
3057 nrssi1 -= 0x0040;
3058 if (nrssi0 == nrssi1)
3059 phy->nrssislope = 0x00010000;
3060 else
3061 phy->nrssislope = 0x00400000 / (nrssi0 - nrssi1);
3062 if (nrssi0 >= -4) {
3063 phy->nrssi[0] = nrssi1;
3064 phy->nrssi[1] = nrssi0;
3065 }
3066 if (phy->rev >= 3) {
3067 b43_phy_write(dev, 0x002E, backup[10]);
3068 b43_phy_write(dev, 0x002F, backup[11]);
3069 b43_phy_write(dev, 0x080F, backup[12]);
3070 b43_phy_write(dev, B43_PHY_G_LO_CONTROL, backup[13]);
3071 }
3072 if (phy->rev >= 2) {
3073 b43_phy_write(dev, 0x0812,
3074 b43_phy_read(dev, 0x0812) & 0xFFCF);
3075 b43_phy_write(dev, 0x0811,
3076 b43_phy_read(dev, 0x0811) & 0xFFCF);
3077 }
3078
3079 b43_radio_write16(dev, 0x007A, backup[0]);
3080 b43_radio_write16(dev, 0x0052, backup[1]);
3081 b43_radio_write16(dev, 0x0043, backup[2]);
3082 b43_write16(dev, 0x03E2, backup[7]);
3083 b43_write16(dev, 0x03E6, backup[8]);
3084 b43_write16(dev, B43_MMIO_CHANNEL_EXT, backup[9]);
3085 b43_phy_write(dev, 0x0015, backup[3]);
3086 b43_phy_write(dev, 0x005A, backup[4]);
3087 b43_phy_write(dev, 0x0059, backup[5]);
3088 b43_phy_write(dev, 0x0058, backup[6]);
3089 b43_synth_pu_workaround(dev, phy->channel);
3090 b43_phy_write(dev, 0x0802,
3091 b43_phy_read(dev, 0x0802) | (0x0001 | 0x0002));
3092 b43_set_original_gains(dev);
3093 b43_phy_write(dev, B43_PHY_G_CRS,
3094 b43_phy_read(dev, B43_PHY_G_CRS) | 0x8000);
3095 if (phy->rev >= 3) {
3096 b43_phy_write(dev, 0x0801, backup[14]);
3097 b43_phy_write(dev, 0x0060, backup[15]);
3098 b43_phy_write(dev, 0x0014, backup[16]);
3099 b43_phy_write(dev, 0x0478, backup[17]);
3100 }
3101 b43_nrssi_mem_update(dev);
3102 b43_calc_nrssi_threshold(dev);
3103 break;
3104 default:
3105 B43_WARN_ON(1);
3106 }
3107 }
3108
3109 void b43_calc_nrssi_threshold(struct b43_wldev *dev)
3110 {
3111 struct b43_phy *phy = &dev->phy;
3112 s32 threshold;
3113 s32 a, b;
3114 s16 tmp16;
3115 u16 tmp_u16;
3116
3117 switch (phy->type) {
3118 case B43_PHYTYPE_B:{
3119 if (phy->radio_ver != 0x2050)
3120 return;
3121 if (!
3122 (dev->dev->bus->sprom.r1.
3123 boardflags_lo & B43_BFL_RSSI))
3124 return;
3125
3126 if (phy->radio_rev >= 6) {
3127 threshold =
3128 (phy->nrssi[1] - phy->nrssi[0]) * 32;
3129 threshold += 20 * (phy->nrssi[0] + 1);
3130 threshold /= 40;
3131 } else
3132 threshold = phy->nrssi[1] - 5;
3133
3134 threshold = limit_value(threshold, 0, 0x3E);
3135 b43_phy_read(dev, 0x0020); /* dummy read */
3136 b43_phy_write(dev, 0x0020,
3137 (((u16) threshold) << 8) | 0x001C);
3138
3139 if (phy->radio_rev >= 6) {
3140 b43_phy_write(dev, 0x0087, 0x0E0D);
3141 b43_phy_write(dev, 0x0086, 0x0C0B);
3142 b43_phy_write(dev, 0x0085, 0x0A09);
3143 b43_phy_write(dev, 0x0084, 0x0808);
3144 b43_phy_write(dev, 0x0083, 0x0808);
3145 b43_phy_write(dev, 0x0082, 0x0604);
3146 b43_phy_write(dev, 0x0081, 0x0302);
3147 b43_phy_write(dev, 0x0080, 0x0100);
3148 }
3149 break;
3150 }
3151 case B43_PHYTYPE_G:
3152 if (!phy->gmode ||
3153 !(dev->dev->bus->sprom.r1.boardflags_lo & B43_BFL_RSSI)) {
3154 tmp16 = b43_nrssi_hw_read(dev, 0x20);
3155 if (tmp16 >= 0x20)
3156 tmp16 -= 0x40;
3157 if (tmp16 < 3) {
3158 b43_phy_write(dev, 0x048A,
3159 (b43_phy_read(dev, 0x048A)
3160 & 0xF000) | 0x09EB);
3161 } else {
3162 b43_phy_write(dev, 0x048A,
3163 (b43_phy_read(dev, 0x048A)
3164 & 0xF000) | 0x0AED);
3165 }
3166 } else {
3167 if (phy->interfmode == B43_INTERFMODE_NONWLAN) {
3168 a = 0xE;
3169 b = 0xA;
3170 } else if (!phy->aci_wlan_automatic && phy->aci_enable) {
3171 a = 0x13;
3172 b = 0x12;
3173 } else {
3174 a = 0xE;
3175 b = 0x11;
3176 }
3177
3178 a = a * (phy->nrssi[1] - phy->nrssi[0]);
3179 a += (phy->nrssi[0] << 6);
3180 if (a < 32)
3181 a += 31;
3182 else
3183 a += 32;
3184 a = a >> 6;
3185 a = limit_value(a, -31, 31);
3186
3187 b = b * (phy->nrssi[1] - phy->nrssi[0]);
3188 b += (phy->nrssi[0] << 6);
3189 if (b < 32)
3190 b += 31;
3191 else
3192 b += 32;
3193 b = b >> 6;
3194 b = limit_value(b, -31, 31);
3195
3196 tmp_u16 = b43_phy_read(dev, 0x048A) & 0xF000;
3197 tmp_u16 |= ((u32) b & 0x0000003F);
3198 tmp_u16 |= (((u32) a & 0x0000003F) << 6);
3199 b43_phy_write(dev, 0x048A, tmp_u16);
3200 }
3201 break;
3202 default:
3203 B43_WARN_ON(1);
3204 }
3205 }
3206
3207 /* Stack implementation to save/restore values from the
3208 * interference mitigation code.
3209 * It is save to restore values in random order.
3210 */
3211 static void _stack_save(u32 * _stackptr, size_t * stackidx,
3212 u8 id, u16 offset, u16 value)
3213 {
3214 u32 *stackptr = &(_stackptr[*stackidx]);
3215
3216 B43_WARN_ON(offset & 0xF000);
3217 B43_WARN_ON(id & 0xF0);
3218 *stackptr = offset;
3219 *stackptr |= ((u32) id) << 12;
3220 *stackptr |= ((u32) value) << 16;
3221 (*stackidx)++;
3222 B43_WARN_ON(*stackidx >= B43_INTERFSTACK_SIZE);
3223 }
3224
3225 static u16 _stack_restore(u32 * stackptr, u8 id, u16 offset)
3226 {
3227 size_t i;
3228
3229 B43_WARN_ON(offset & 0xF000);
3230 B43_WARN_ON(id & 0xF0);
3231 for (i = 0; i < B43_INTERFSTACK_SIZE; i++, stackptr++) {
3232 if ((*stackptr & 0x00000FFF) != offset)
3233 continue;
3234 if (((*stackptr & 0x0000F000) >> 12) != id)
3235 continue;
3236 return ((*stackptr & 0xFFFF0000) >> 16);
3237 }
3238 B43_WARN_ON(1);
3239
3240 return 0;
3241 }
3242
3243 #define phy_stacksave(offset) \
3244 do { \
3245 _stack_save(stack, &stackidx, 0x1, (offset), \
3246 b43_phy_read(dev, (offset))); \
3247 } while (0)
3248 #define phy_stackrestore(offset) \
3249 do { \
3250 b43_phy_write(dev, (offset), \
3251 _stack_restore(stack, 0x1, \
3252 (offset))); \
3253 } while (0)
3254 #define radio_stacksave(offset) \
3255 do { \
3256 _stack_save(stack, &stackidx, 0x2, (offset), \
3257 b43_radio_read16(dev, (offset))); \
3258 } while (0)
3259 #define radio_stackrestore(offset) \
3260 do { \
3261 b43_radio_write16(dev, (offset), \
3262 _stack_restore(stack, 0x2, \
3263 (offset))); \
3264 } while (0)
3265 #define ofdmtab_stacksave(table, offset) \
3266 do { \
3267 _stack_save(stack, &stackidx, 0x3, (offset)|(table), \
3268 b43_ofdmtab_read16(dev, (table), (offset))); \
3269 } while (0)
3270 #define ofdmtab_stackrestore(table, offset) \
3271 do { \
3272 b43_ofdmtab_write16(dev, (table), (offset), \
3273 _stack_restore(stack, 0x3, \
3274 (offset)|(table))); \
3275 } while (0)
3276
3277 static void
3278 b43_radio_interference_mitigation_enable(struct b43_wldev *dev, int mode)
3279 {
3280 struct b43_phy *phy = &dev->phy;
3281 u16 tmp, flipped;
3282 size_t stackidx = 0;
3283 u32 *stack = phy->interfstack;
3284
3285 switch (mode) {
3286 case B43_INTERFMODE_NONWLAN:
3287 if (phy->rev != 1) {
3288 b43_phy_write(dev, 0x042B,
3289 b43_phy_read(dev, 0x042B) | 0x0800);
3290 b43_phy_write(dev, B43_PHY_G_CRS,
3291 b43_phy_read(dev,
3292 B43_PHY_G_CRS) & ~0x4000);
3293 break;
3294 }
3295 radio_stacksave(0x0078);
3296 tmp = (b43_radio_read16(dev, 0x0078) & 0x001E);
3297 flipped = flip_4bit(tmp);
3298 if (flipped < 10 && flipped >= 8)
3299 flipped = 7;
3300 else if (flipped >= 10)
3301 flipped -= 3;
3302 flipped = flip_4bit(flipped);
3303 flipped = (flipped << 1) | 0x0020;
3304 b43_radio_write16(dev, 0x0078, flipped);
3305
3306 b43_calc_nrssi_threshold(dev);
3307
3308 phy_stacksave(0x0406);
3309 b43_phy_write(dev, 0x0406, 0x7E28);
3310
3311 b43_phy_write(dev, 0x042B, b43_phy_read(dev, 0x042B) | 0x0800);
3312 b43_phy_write(dev, B43_PHY_RADIO_BITFIELD,
3313 b43_phy_read(dev,
3314 B43_PHY_RADIO_BITFIELD) | 0x1000);
3315
3316 phy_stacksave(0x04A0);
3317 b43_phy_write(dev, 0x04A0,
3318 (b43_phy_read(dev, 0x04A0) & 0xC0C0) | 0x0008);
3319 phy_stacksave(0x04A1);
3320 b43_phy_write(dev, 0x04A1,
3321 (b43_phy_read(dev, 0x04A1) & 0xC0C0) | 0x0605);
3322 phy_stacksave(0x04A2);
3323 b43_phy_write(dev, 0x04A2,
3324 (b43_phy_read(dev, 0x04A2) & 0xC0C0) | 0x0204);
3325 phy_stacksave(0x04A8);
3326 b43_phy_write(dev, 0x04A8,
3327 (b43_phy_read(dev, 0x04A8) & 0xC0C0) | 0x0803);
3328 phy_stacksave(0x04AB);
3329 b43_phy_write(dev, 0x04AB,
3330 (b43_phy_read(dev, 0x04AB) & 0xC0C0) | 0x0605);
3331
3332 phy_stacksave(0x04A7);
3333 b43_phy_write(dev, 0x04A7, 0x0002);
3334 phy_stacksave(0x04A3);
3335 b43_phy_write(dev, 0x04A3, 0x287A);
3336 phy_stacksave(0x04A9);
3337 b43_phy_write(dev, 0x04A9, 0x2027);
3338 phy_stacksave(0x0493);
3339 b43_phy_write(dev, 0x0493, 0x32F5);
3340 phy_stacksave(0x04AA);
3341 b43_phy_write(dev, 0x04AA, 0x2027);
3342 phy_stacksave(0x04AC);
3343 b43_phy_write(dev, 0x04AC, 0x32F5);
3344 break;
3345 case B43_INTERFMODE_MANUALWLAN:
3346 if (b43_phy_read(dev, 0x0033) & 0x0800)
3347 break;
3348
3349 phy->aci_enable = 1;
3350
3351 phy_stacksave(B43_PHY_RADIO_BITFIELD);
3352 phy_stacksave(B43_PHY_G_CRS);
3353 if (phy->rev < 2) {
3354 phy_stacksave(0x0406);
3355 } else {
3356 phy_stacksave(0x04C0);
3357 phy_stacksave(0x04C1);
3358 }
3359 phy_stacksave(0x0033);
3360 phy_stacksave(0x04A7);
3361 phy_stacksave(0x04A3);
3362 phy_stacksave(0x04A9);
3363 phy_stacksave(0x04AA);
3364 phy_stacksave(0x04AC);
3365 phy_stacksave(0x0493);
3366 phy_stacksave(0x04A1);
3367 phy_stacksave(0x04A0);
3368 phy_stacksave(0x04A2);
3369 phy_stacksave(0x048A);
3370 phy_stacksave(0x04A8);
3371 phy_stacksave(0x04AB);
3372 if (phy->rev == 2) {
3373 phy_stacksave(0x04AD);
3374 phy_stacksave(0x04AE);
3375 } else if (phy->rev >= 3) {
3376 phy_stacksave(0x04AD);
3377 phy_stacksave(0x0415);
3378 phy_stacksave(0x0416);
3379 phy_stacksave(0x0417);
3380 ofdmtab_stacksave(0x1A00, 0x2);
3381 ofdmtab_stacksave(0x1A00, 0x3);
3382 }
3383 phy_stacksave(0x042B);
3384 phy_stacksave(0x048C);
3385
3386 b43_phy_write(dev, B43_PHY_RADIO_BITFIELD,
3387 b43_phy_read(dev, B43_PHY_RADIO_BITFIELD)
3388 & ~0x1000);
3389 b43_phy_write(dev, B43_PHY_G_CRS,
3390 (b43_phy_read(dev, B43_PHY_G_CRS)
3391 & 0xFFFC) | 0x0002);
3392
3393 b43_phy_write(dev, 0x0033, 0x0800);
3394 b43_phy_write(dev, 0x04A3, 0x2027);
3395 b43_phy_write(dev, 0x04A9, 0x1CA8);
3396 b43_phy_write(dev, 0x0493, 0x287A);
3397 b43_phy_write(dev, 0x04AA, 0x1CA8);
3398 b43_phy_write(dev, 0x04AC, 0x287A);
3399
3400 b43_phy_write(dev, 0x04A0, (b43_phy_read(dev, 0x04A0)
3401 & 0xFFC0) | 0x001A);
3402 b43_phy_write(dev, 0x04A7, 0x000D);
3403
3404 if (phy->rev < 2) {
3405 b43_phy_write(dev, 0x0406, 0xFF0D);
3406 } else if (phy->rev == 2) {
3407 b43_phy_write(dev, 0x04C0, 0xFFFF);
3408 b43_phy_write(dev, 0x04C1, 0x00A9);
3409 } else {
3410 b43_phy_write(dev, 0x04C0, 0x00C1);
3411 b43_phy_write(dev, 0x04C1, 0x0059);
3412 }
3413
3414 b43_phy_write(dev, 0x04A1, (b43_phy_read(dev, 0x04A1)
3415 & 0xC0FF) | 0x1800);
3416 b43_phy_write(dev, 0x04A1, (b43_phy_read(dev, 0x04A1)
3417 & 0xFFC0) | 0x0015);
3418 b43_phy_write(dev, 0x04A8, (b43_phy_read(dev, 0x04A8)
3419 & 0xCFFF) | 0x1000);
3420 b43_phy_write(dev, 0x04A8, (b43_phy_read(dev, 0x04A8)
3421 & 0xF0FF) | 0x0A00);
3422 b43_phy_write(dev, 0x04AB, (b43_phy_read(dev, 0x04AB)
3423 & 0xCFFF) | 0x1000);
3424 b43_phy_write(dev, 0x04AB, (b43_phy_read(dev, 0x04AB)
3425 & 0xF0FF) | 0x0800);
3426 b43_phy_write(dev, 0x04AB, (b43_phy_read(dev, 0x04AB)
3427 & 0xFFCF) | 0x0010);
3428 b43_phy_write(dev, 0x04AB, (b43_phy_read(dev, 0x04AB)
3429 & 0xFFF0) | 0x0005);
3430 b43_phy_write(dev, 0x04A8, (b43_phy_read(dev, 0x04A8)
3431 & 0xFFCF) | 0x0010);
3432 b43_phy_write(dev, 0x04A8, (b43_phy_read(dev, 0x04A8)
3433 & 0xFFF0) | 0x0006);
3434 b43_phy_write(dev, 0x04A2, (b43_phy_read(dev, 0x04A2)
3435 & 0xF0FF) | 0x0800);
3436 b43_phy_write(dev, 0x04A0, (b43_phy_read(dev, 0x04A0)
3437 & 0xF0FF) | 0x0500);
3438 b43_phy_write(dev, 0x04A2, (b43_phy_read(dev, 0x04A2)
3439 & 0xFFF0) | 0x000B);
3440
3441 if (phy->rev >= 3) {
3442 b43_phy_write(dev, 0x048A, b43_phy_read(dev, 0x048A)
3443 & ~0x8000);
3444 b43_phy_write(dev, 0x0415, (b43_phy_read(dev, 0x0415)
3445 & 0x8000) | 0x36D8);
3446 b43_phy_write(dev, 0x0416, (b43_phy_read(dev, 0x0416)
3447 & 0x8000) | 0x36D8);
3448 b43_phy_write(dev, 0x0417, (b43_phy_read(dev, 0x0417)
3449 & 0xFE00) | 0x016D);
3450 } else {
3451 b43_phy_write(dev, 0x048A, b43_phy_read(dev, 0x048A)
3452 | 0x1000);
3453 b43_phy_write(dev, 0x048A, (b43_phy_read(dev, 0x048A)
3454 & 0x9FFF) | 0x2000);
3455 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_ACIW);
3456 }
3457 if (phy->rev >= 2) {
3458 b43_phy_write(dev, 0x042B, b43_phy_read(dev, 0x042B)
3459 | 0x0800);
3460 }
3461 b43_phy_write(dev, 0x048C, (b43_phy_read(dev, 0x048C)
3462 & 0xF0FF) | 0x0200);
3463 if (phy->rev == 2) {
3464 b43_phy_write(dev, 0x04AE, (b43_phy_read(dev, 0x04AE)
3465 & 0xFF00) | 0x007F);
3466 b43_phy_write(dev, 0x04AD, (b43_phy_read(dev, 0x04AD)
3467 & 0x00FF) | 0x1300);
3468 } else if (phy->rev >= 6) {
3469 b43_ofdmtab_write16(dev, 0x1A00, 0x3, 0x007F);
3470 b43_ofdmtab_write16(dev, 0x1A00, 0x2, 0x007F);
3471 b43_phy_write(dev, 0x04AD, b43_phy_read(dev, 0x04AD)
3472 & 0x00FF);
3473 }
3474 b43_calc_nrssi_slope(dev);
3475 break;
3476 default:
3477 B43_WARN_ON(1);
3478 }
3479 }
3480
3481 static void
3482 b43_radio_interference_mitigation_disable(struct b43_wldev *dev, int mode)
3483 {
3484 struct b43_phy *phy = &dev->phy;
3485 u32 *stack = phy->interfstack;
3486
3487 switch (mode) {
3488 case B43_INTERFMODE_NONWLAN:
3489 if (phy->rev != 1) {
3490 b43_phy_write(dev, 0x042B,
3491 b43_phy_read(dev, 0x042B) & ~0x0800);
3492 b43_phy_write(dev, B43_PHY_G_CRS,
3493 b43_phy_read(dev,
3494 B43_PHY_G_CRS) | 0x4000);
3495 break;
3496 }
3497 radio_stackrestore(0x0078);
3498 b43_calc_nrssi_threshold(dev);
3499 phy_stackrestore(0x0406);
3500 b43_phy_write(dev, 0x042B, b43_phy_read(dev, 0x042B) & ~0x0800);
3501 if (!dev->bad_frames_preempt) {
3502 b43_phy_write(dev, B43_PHY_RADIO_BITFIELD,
3503 b43_phy_read(dev, B43_PHY_RADIO_BITFIELD)
3504 & ~(1 << 11));
3505 }
3506 b43_phy_write(dev, B43_PHY_G_CRS,
3507 b43_phy_read(dev, B43_PHY_G_CRS) | 0x4000);
3508 phy_stackrestore(0x04A0);
3509 phy_stackrestore(0x04A1);
3510 phy_stackrestore(0x04A2);
3511 phy_stackrestore(0x04A8);
3512 phy_stackrestore(0x04AB);
3513 phy_stackrestore(0x04A7);
3514 phy_stackrestore(0x04A3);
3515 phy_stackrestore(0x04A9);
3516 phy_stackrestore(0x0493);
3517 phy_stackrestore(0x04AA);
3518 phy_stackrestore(0x04AC);
3519 break;
3520 case B43_INTERFMODE_MANUALWLAN:
3521 if (!(b43_phy_read(dev, 0x0033) & 0x0800))
3522 break;
3523
3524 phy->aci_enable = 0;
3525
3526 phy_stackrestore(B43_PHY_RADIO_BITFIELD);
3527 phy_stackrestore(B43_PHY_G_CRS);
3528 phy_stackrestore(0x0033);
3529 phy_stackrestore(0x04A3);
3530 phy_stackrestore(0x04A9);
3531 phy_stackrestore(0x0493);
3532 phy_stackrestore(0x04AA);
3533 phy_stackrestore(0x04AC);
3534 phy_stackrestore(0x04A0);
3535 phy_stackrestore(0x04A7);
3536 if (phy->rev >= 2) {
3537 phy_stackrestore(0x04C0);
3538 phy_stackrestore(0x04C1);
3539 } else
3540 phy_stackrestore(0x0406);
3541 phy_stackrestore(0x04A1);
3542 phy_stackrestore(0x04AB);
3543 phy_stackrestore(0x04A8);
3544 if (phy->rev == 2) {
3545 phy_stackrestore(0x04AD);
3546 phy_stackrestore(0x04AE);
3547 } else if (phy->rev >= 3) {
3548 phy_stackrestore(0x04AD);
3549 phy_stackrestore(0x0415);
3550 phy_stackrestore(0x0416);
3551 phy_stackrestore(0x0417);
3552 ofdmtab_stackrestore(0x1A00, 0x2);
3553 ofdmtab_stackrestore(0x1A00, 0x3);
3554 }
3555 phy_stackrestore(0x04A2);
3556 phy_stackrestore(0x048A);
3557 phy_stackrestore(0x042B);
3558 phy_stackrestore(0x048C);
3559 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_ACIW);
3560 b43_calc_nrssi_slope(dev);
3561 break;
3562 default:
3563 B43_WARN_ON(1);
3564 }
3565 }
3566
3567 #undef phy_stacksave
3568 #undef phy_stackrestore
3569 #undef radio_stacksave
3570 #undef radio_stackrestore
3571 #undef ofdmtab_stacksave
3572 #undef ofdmtab_stackrestore
3573
3574 int b43_radio_set_interference_mitigation(struct b43_wldev *dev, int mode)
3575 {
3576 struct b43_phy *phy = &dev->phy;
3577 int currentmode;
3578
3579 if ((phy->type != B43_PHYTYPE_G) || (phy->rev == 0) || (!phy->gmode))
3580 return -ENODEV;
3581
3582 phy->aci_wlan_automatic = 0;
3583 switch (mode) {
3584 case B43_INTERFMODE_AUTOWLAN:
3585 phy->aci_wlan_automatic = 1;
3586 if (phy->aci_enable)
3587 mode = B43_INTERFMODE_MANUALWLAN;
3588 else
3589 mode = B43_INTERFMODE_NONE;
3590 break;
3591 case B43_INTERFMODE_NONE:
3592 case B43_INTERFMODE_NONWLAN:
3593 case B43_INTERFMODE_MANUALWLAN:
3594 break;
3595 default:
3596 return -EINVAL;
3597 }
3598
3599 currentmode = phy->interfmode;
3600 if (currentmode == mode)
3601 return 0;
3602 if (currentmode != B43_INTERFMODE_NONE)
3603 b43_radio_interference_mitigation_disable(dev, currentmode);
3604
3605 if (mode == B43_INTERFMODE_NONE) {
3606 phy->aci_enable = 0;
3607 phy->aci_hw_rssi = 0;
3608 } else
3609 b43_radio_interference_mitigation_enable(dev, mode);
3610 phy->interfmode = mode;
3611
3612 return 0;
3613 }
3614
3615 static u16 b43_radio_core_calibration_value(struct b43_wldev *dev)
3616 {
3617 u16 reg, index, ret;
3618
3619 static const u8 rcc_table[] = {
3620 0x02, 0x03, 0x01, 0x0F,
3621 0x06, 0x07, 0x05, 0x0F,
3622 0x0A, 0x0B, 0x09, 0x0F,
3623 0x0E, 0x0F, 0x0D, 0x0F,
3624 };
3625
3626 reg = b43_radio_read16(dev, 0x60);
3627 index = (reg & 0x001E) >> 1;
3628 ret = rcc_table[index] << 1;
3629 ret |= (reg & 0x0001);
3630 ret |= 0x0020;
3631
3632 return ret;
3633 }
3634
3635 #define LPD(L, P, D) (((L) << 2) | ((P) << 1) | ((D) << 0))
3636 static u16 radio2050_rfover_val(struct b43_wldev *dev,
3637 u16 phy_register, unsigned int lpd)
3638 {
3639 struct b43_phy *phy = &dev->phy;
3640 struct ssb_sprom *sprom = &(dev->dev->bus->sprom);
3641
3642 if (!phy->gmode)
3643 return 0;
3644
3645 if (has_loopback_gain(phy)) {
3646 int max_lb_gain = phy->max_lb_gain;
3647 u16 extlna;
3648 u16 i;
3649
3650 if (phy->radio_rev == 8)
3651 max_lb_gain += 0x3E;
3652 else
3653 max_lb_gain += 0x26;
3654 if (max_lb_gain >= 0x46) {
3655 extlna = 0x3000;
3656 max_lb_gain -= 0x46;
3657 } else if (max_lb_gain >= 0x3A) {
3658 extlna = 0x1000;
3659 max_lb_gain -= 0x3A;
3660 } else if (max_lb_gain >= 0x2E) {
3661 extlna = 0x2000;
3662 max_lb_gain -= 0x2E;
3663 } else {
3664 extlna = 0;
3665 max_lb_gain -= 0x10;
3666 }
3667
3668 for (i = 0; i < 16; i++) {
3669 max_lb_gain -= (i * 6);
3670 if (max_lb_gain < 6)
3671 break;
3672 }
3673
3674 if ((phy->rev < 7) ||
3675 !(sprom->r1.boardflags_lo & B43_BFL_EXTLNA)) {
3676 if (phy_register == B43_PHY_RFOVER) {
3677 return 0x1B3;
3678 } else if (phy_register == B43_PHY_RFOVERVAL) {
3679 extlna |= (i << 8);
3680 switch (lpd) {
3681 case LPD(0, 1, 1):
3682 return 0x0F92;
3683 case LPD(0, 0, 1):
3684 case LPD(1, 0, 1):
3685 return (0x0092 | extlna);
3686 case LPD(1, 0, 0):
3687 return (0x0093 | extlna);
3688 }
3689 B43_WARN_ON(1);
3690 }
3691 B43_WARN_ON(1);
3692 } else {
3693 if (phy_register == B43_PHY_RFOVER) {
3694 return 0x9B3;
3695 } else if (phy_register == B43_PHY_RFOVERVAL) {
3696 if (extlna)
3697 extlna |= 0x8000;
3698 extlna |= (i << 8);
3699 switch (lpd) {
3700 case LPD(0, 1, 1):
3701 return 0x8F92;
3702 case LPD(0, 0, 1):
3703 return (0x8092 | extlna);
3704 case LPD(1, 0, 1):
3705 return (0x2092 | extlna);
3706 case LPD(1, 0, 0):
3707 return (0x2093 | extlna);
3708 }
3709 B43_WARN_ON(1);
3710 }
3711 B43_WARN_ON(1);
3712 }
3713 } else {
3714 if ((phy->rev < 7) ||
3715 !(sprom->r1.boardflags_lo & B43_BFL_EXTLNA)) {
3716 if (phy_register == B43_PHY_RFOVER) {
3717 return 0x1B3;
3718 } else if (phy_register == B43_PHY_RFOVERVAL) {
3719 switch (lpd) {
3720 case LPD(0, 1, 1):
3721 return 0x0FB2;
3722 case LPD(0, 0, 1):
3723 return 0x00B2;
3724 case LPD(1, 0, 1):
3725 return 0x30B2;
3726 case LPD(1, 0, 0):
3727 return 0x30B3;
3728 }
3729 B43_WARN_ON(1);
3730 }
3731 B43_WARN_ON(1);
3732 } else {
3733 if (phy_register == B43_PHY_RFOVER) {
3734 return 0x9B3;
3735 } else if (phy_register == B43_PHY_RFOVERVAL) {
3736 switch (lpd) {
3737 case LPD(0, 1, 1):
3738 return 0x8FB2;
3739 case LPD(0, 0, 1):
3740 return 0x80B2;
3741 case LPD(1, 0, 1):
3742 return 0x20B2;
3743 case LPD(1, 0, 0):
3744 return 0x20B3;
3745 }
3746 B43_WARN_ON(1);
3747 }
3748 B43_WARN_ON(1);
3749 }
3750 }
3751 return 0;
3752 }
3753
3754 struct init2050_saved_values {
3755 /* Core registers */
3756 u16 reg_3EC;
3757 u16 reg_3E6;
3758 u16 reg_3F4;
3759 /* Radio registers */
3760 u16 radio_43;
3761 u16 radio_51;
3762 u16 radio_52;
3763 /* PHY registers */
3764 u16 phy_pgactl;
3765 u16 phy_base_5A;
3766 u16 phy_base_59;
3767 u16 phy_base_58;
3768 u16 phy_base_30;
3769 u16 phy_rfover;
3770 u16 phy_rfoverval;
3771 u16 phy_analogover;
3772 u16 phy_analogoverval;
3773 u16 phy_crs0;
3774 u16 phy_classctl;
3775 u16 phy_lo_mask;
3776 u16 phy_lo_ctl;
3777 u16 phy_syncctl;
3778 };
3779
3780 u16 b43_radio_init2050(struct b43_wldev *dev)
3781 {
3782 struct b43_phy *phy = &dev->phy;
3783 struct init2050_saved_values sav;
3784 u16 rcc;
3785 u16 radio78;
3786 u16 ret;
3787 u16 i, j;
3788 u32 tmp1 = 0, tmp2 = 0;
3789
3790 memset(&sav, 0, sizeof(sav)); /* get rid of "may be used uninitialized..." */
3791
3792 sav.radio_43 = b43_radio_read16(dev, 0x43);
3793 sav.radio_51 = b43_radio_read16(dev, 0x51);
3794 sav.radio_52 = b43_radio_read16(dev, 0x52);
3795 sav.phy_pgactl = b43_phy_read(dev, B43_PHY_PGACTL);
3796 sav.phy_base_5A = b43_phy_read(dev, B43_PHY_BASE(0x5A));
3797 sav.phy_base_59 = b43_phy_read(dev, B43_PHY_BASE(0x59));
3798 sav.phy_base_58 = b43_phy_read(dev, B43_PHY_BASE(0x58));
3799
3800 if (phy->type == B43_PHYTYPE_B) {
3801 sav.phy_base_30 = b43_phy_read(dev, B43_PHY_BASE(0x30));
3802 sav.reg_3EC = b43_read16(dev, 0x3EC);
3803
3804 b43_phy_write(dev, B43_PHY_BASE(0x30), 0xFF);
3805 b43_write16(dev, 0x3EC, 0x3F3F);
3806 } else if (phy->gmode || phy->rev >= 2) {
3807 sav.phy_rfover = b43_phy_read(dev, B43_PHY_RFOVER);
3808 sav.phy_rfoverval = b43_phy_read(dev, B43_PHY_RFOVERVAL);
3809 sav.phy_analogover = b43_phy_read(dev, B43_PHY_ANALOGOVER);
3810 sav.phy_analogoverval =
3811 b43_phy_read(dev, B43_PHY_ANALOGOVERVAL);
3812 sav.phy_crs0 = b43_phy_read(dev, B43_PHY_CRS0);
3813 sav.phy_classctl = b43_phy_read(dev, B43_PHY_CLASSCTL);
3814
3815 b43_phy_write(dev, B43_PHY_ANALOGOVER,
3816 b43_phy_read(dev, B43_PHY_ANALOGOVER)
3817 | 0x0003);
3818 b43_phy_write(dev, B43_PHY_ANALOGOVERVAL,
3819 b43_phy_read(dev, B43_PHY_ANALOGOVERVAL)
3820 & 0xFFFC);
3821 b43_phy_write(dev, B43_PHY_CRS0, b43_phy_read(dev, B43_PHY_CRS0)
3822 & 0x7FFF);
3823 b43_phy_write(dev, B43_PHY_CLASSCTL,
3824 b43_phy_read(dev, B43_PHY_CLASSCTL)
3825 & 0xFFFC);
3826 if (has_loopback_gain(phy)) {
3827 sav.phy_lo_mask = b43_phy_read(dev, B43_PHY_LO_MASK);
3828 sav.phy_lo_ctl = b43_phy_read(dev, B43_PHY_LO_CTL);
3829
3830 if (phy->rev >= 3)
3831 b43_phy_write(dev, B43_PHY_LO_MASK, 0xC020);
3832 else
3833 b43_phy_write(dev, B43_PHY_LO_MASK, 0x8020);
3834 b43_phy_write(dev, B43_PHY_LO_CTL, 0);
3835 }
3836
3837 b43_phy_write(dev, B43_PHY_RFOVERVAL,
3838 radio2050_rfover_val(dev, B43_PHY_RFOVERVAL,
3839 LPD(0, 1, 1)));
3840 b43_phy_write(dev, B43_PHY_RFOVER,
3841 radio2050_rfover_val(dev, B43_PHY_RFOVER, 0));
3842 }
3843 b43_write16(dev, 0x3E2, b43_read16(dev, 0x3E2) | 0x8000);
3844
3845 sav.phy_syncctl = b43_phy_read(dev, B43_PHY_SYNCCTL);
3846 b43_phy_write(dev, B43_PHY_SYNCCTL, b43_phy_read(dev, B43_PHY_SYNCCTL)
3847 & 0xFF7F);
3848 sav.reg_3E6 = b43_read16(dev, 0x3E6);
3849 sav.reg_3F4 = b43_read16(dev, 0x3F4);
3850
3851 if (phy->analog == 0) {
3852 b43_write16(dev, 0x03E6, 0x0122);
3853 } else {
3854 if (phy->analog >= 2) {
3855 b43_phy_write(dev, B43_PHY_BASE(0x03),
3856 (b43_phy_read(dev, B43_PHY_BASE(0x03))
3857 & 0xFFBF) | 0x40);
3858 }
3859 b43_write16(dev, B43_MMIO_CHANNEL_EXT,
3860 (b43_read16(dev, B43_MMIO_CHANNEL_EXT) | 0x2000));
3861 }
3862
3863 rcc = b43_radio_core_calibration_value(dev);
3864
3865 if (phy->type == B43_PHYTYPE_B)
3866 b43_radio_write16(dev, 0x78, 0x26);
3867 if (phy->gmode || phy->rev >= 2) {
3868 b43_phy_write(dev, B43_PHY_RFOVERVAL,
3869 radio2050_rfover_val(dev, B43_PHY_RFOVERVAL,
3870 LPD(0, 1, 1)));
3871 }
3872 b43_phy_write(dev, B43_PHY_PGACTL, 0xBFAF);
3873 b43_phy_write(dev, B43_PHY_BASE(0x2B), 0x1403);
3874 if (phy->gmode || phy->rev >= 2) {
3875 b43_phy_write(dev, B43_PHY_RFOVERVAL,
3876 radio2050_rfover_val(dev, B43_PHY_RFOVERVAL,
3877 LPD(0, 0, 1)));
3878 }
3879 b43_phy_write(dev, B43_PHY_PGACTL, 0xBFA0);
3880 b43_radio_write16(dev, 0x51, b43_radio_read16(dev, 0x51)
3881 | 0x0004);
3882 if (phy->radio_rev == 8) {
3883 b43_radio_write16(dev, 0x43, 0x1F);
3884 } else {
3885 b43_radio_write16(dev, 0x52, 0);
3886 b43_radio_write16(dev, 0x43, (b43_radio_read16(dev, 0x43)
3887 & 0xFFF0) | 0x0009);
3888 }
3889 b43_phy_write(dev, B43_PHY_BASE(0x58), 0);
3890
3891 for (i = 0; i < 16; i++) {
3892 b43_phy_write(dev, B43_PHY_BASE(0x5A), 0x0480);
3893 b43_phy_write(dev, B43_PHY_BASE(0x59), 0xC810);
3894 b43_phy_write(dev, B43_PHY_BASE(0x58), 0x000D);
3895 if (phy->gmode || phy->rev >= 2) {
3896 b43_phy_write(dev, B43_PHY_RFOVERVAL,
3897 radio2050_rfover_val(dev,
3898 B43_PHY_RFOVERVAL,
3899 LPD(1, 0, 1)));
3900 }
3901 b43_phy_write(dev, B43_PHY_PGACTL, 0xAFB0);
3902 udelay(10);
3903 if (phy->gmode || phy->rev >= 2) {
3904 b43_phy_write(dev, B43_PHY_RFOVERVAL,
3905 radio2050_rfover_val(dev,
3906 B43_PHY_RFOVERVAL,
3907 LPD(1, 0, 1)));
3908 }
3909 b43_phy_write(dev, B43_PHY_PGACTL, 0xEFB0);
3910 udelay(10);
3911 if (phy->gmode || phy->rev >= 2) {
3912 b43_phy_write(dev, B43_PHY_RFOVERVAL,
3913 radio2050_rfover_val(dev,
3914 B43_PHY_RFOVERVAL,
3915 LPD(1, 0, 0)));
3916 }
3917 b43_phy_write(dev, B43_PHY_PGACTL, 0xFFF0);
3918 udelay(20);
3919 tmp1 += b43_phy_read(dev, B43_PHY_LO_LEAKAGE);
3920 b43_phy_write(dev, B43_PHY_BASE(0x58), 0);
3921 if (phy->gmode || phy->rev >= 2) {
3922 b43_phy_write(dev, B43_PHY_RFOVERVAL,
3923 radio2050_rfover_val(dev,
3924 B43_PHY_RFOVERVAL,
3925 LPD(1, 0, 1)));
3926 }
3927 b43_phy_write(dev, B43_PHY_PGACTL, 0xAFB0);
3928 }
3929 udelay(10);
3930
3931 b43_phy_write(dev, B43_PHY_BASE(0x58), 0);
3932 tmp1++;
3933 tmp1 >>= 9;
3934
3935 for (i = 0; i < 16; i++) {
3936 radio78 = ((flip_4bit(i) << 1) | 0x20);
3937 b43_radio_write16(dev, 0x78, radio78);
3938 udelay(10);
3939 for (j = 0; j < 16; j++) {
3940 b43_phy_write(dev, B43_PHY_BASE(0x5A), 0x0D80);
3941 b43_phy_write(dev, B43_PHY_BASE(0x59), 0xC810);
3942 b43_phy_write(dev, B43_PHY_BASE(0x58), 0x000D);
3943 if (phy->gmode || phy->rev >= 2) {
3944 b43_phy_write(dev, B43_PHY_RFOVERVAL,
3945 radio2050_rfover_val(dev,
3946 B43_PHY_RFOVERVAL,
3947 LPD(1, 0,
3948 1)));
3949 }
3950 b43_phy_write(dev, B43_PHY_PGACTL, 0xAFB0);
3951 udelay(10);
3952 if (phy->gmode || phy->rev >= 2) {
3953 b43_phy_write(dev, B43_PHY_RFOVERVAL,
3954 radio2050_rfover_val(dev,
3955 B43_PHY_RFOVERVAL,
3956 LPD(1, 0,
3957 1)));
3958 }
3959 b43_phy_write(dev, B43_PHY_PGACTL, 0xEFB0);
3960 udelay(10);
3961 if (phy->gmode || phy->rev >= 2) {
3962 b43_phy_write(dev, B43_PHY_RFOVERVAL,
3963 radio2050_rfover_val(dev,
3964 B43_PHY_RFOVERVAL,
3965 LPD(1, 0,
3966 0)));
3967 }
3968 b43_phy_write(dev, B43_PHY_PGACTL, 0xFFF0);
3969 udelay(10);
3970 tmp2 += b43_phy_read(dev, B43_PHY_LO_LEAKAGE);
3971 b43_phy_write(dev, B43_PHY_BASE(0x58), 0);
3972 if (phy->gmode || phy->rev >= 2) {
3973 b43_phy_write(dev, B43_PHY_RFOVERVAL,
3974 radio2050_rfover_val(dev,
3975 B43_PHY_RFOVERVAL,
3976 LPD(1, 0,
3977 1)));
3978 }
3979 b43_phy_write(dev, B43_PHY_PGACTL, 0xAFB0);
3980 }
3981 tmp2++;
3982 tmp2 >>= 8;
3983 if (tmp1 < tmp2)
3984 break;
3985 }
3986
3987 /* Restore the registers */
3988 b43_phy_write(dev, B43_PHY_PGACTL, sav.phy_pgactl);
3989 b43_radio_write16(dev, 0x51, sav.radio_51);
3990 b43_radio_write16(dev, 0x52, sav.radio_52);
3991 b43_radio_write16(dev, 0x43, sav.radio_43);
3992 b43_phy_write(dev, B43_PHY_BASE(0x5A), sav.phy_base_5A);
3993 b43_phy_write(dev, B43_PHY_BASE(0x59), sav.phy_base_59);
3994 b43_phy_write(dev, B43_PHY_BASE(0x58), sav.phy_base_58);
3995 b43_write16(dev, 0x3E6, sav.reg_3E6);
3996 if (phy->analog != 0)
3997 b43_write16(dev, 0x3F4, sav.reg_3F4);
3998 b43_phy_write(dev, B43_PHY_SYNCCTL, sav.phy_syncctl);
3999 b43_synth_pu_workaround(dev, phy->channel);
4000 if (phy->type == B43_PHYTYPE_B) {
4001 b43_phy_write(dev, B43_PHY_BASE(0x30), sav.phy_base_30);
4002 b43_write16(dev, 0x3EC, sav.reg_3EC);
4003 } else if (phy->gmode) {
4004 b43_write16(dev, B43_MMIO_PHY_RADIO,
4005 b43_read16(dev, B43_MMIO_PHY_RADIO)
4006 & 0x7FFF);
4007 b43_phy_write(dev, B43_PHY_RFOVER, sav.phy_rfover);
4008 b43_phy_write(dev, B43_PHY_RFOVERVAL, sav.phy_rfoverval);
4009 b43_phy_write(dev, B43_PHY_ANALOGOVER, sav.phy_analogover);
4010 b43_phy_write(dev, B43_PHY_ANALOGOVERVAL,
4011 sav.phy_analogoverval);
4012 b43_phy_write(dev, B43_PHY_CRS0, sav.phy_crs0);
4013 b43_phy_write(dev, B43_PHY_CLASSCTL, sav.phy_classctl);
4014 if (has_loopback_gain(phy)) {
4015 b43_phy_write(dev, B43_PHY_LO_MASK, sav.phy_lo_mask);
4016 b43_phy_write(dev, B43_PHY_LO_CTL, sav.phy_lo_ctl);
4017 }
4018 }
4019 if (i > 15)
4020 ret = radio78;
4021 else
4022 ret = rcc;
4023
4024 return ret;
4025 }
4026
4027 void b43_radio_init2060(struct b43_wldev *dev)
4028 {
4029 int err;
4030
4031 b43_radio_write16(dev, 0x0004, 0x00C0);
4032 b43_radio_write16(dev, 0x0005, 0x0008);
4033 b43_radio_write16(dev, 0x0009, 0x0040);
4034 b43_radio_write16(dev, 0x0005, 0x00AA);
4035 b43_radio_write16(dev, 0x0032, 0x008F);
4036 b43_radio_write16(dev, 0x0006, 0x008F);
4037 b43_radio_write16(dev, 0x0034, 0x008F);
4038 b43_radio_write16(dev, 0x002C, 0x0007);
4039 b43_radio_write16(dev, 0x0082, 0x0080);
4040 b43_radio_write16(dev, 0x0080, 0x0000);
4041 b43_radio_write16(dev, 0x003F, 0x00DA);
4042 b43_radio_write16(dev, 0x0005, b43_radio_read16(dev, 0x0005) & ~0x0008);
4043 b43_radio_write16(dev, 0x0081, b43_radio_read16(dev, 0x0081) & ~0x0010);
4044 b43_radio_write16(dev, 0x0081, b43_radio_read16(dev, 0x0081) & ~0x0020);
4045 b43_radio_write16(dev, 0x0081, b43_radio_read16(dev, 0x0081) & ~0x0020);
4046 msleep(1); /* delay 400usec */
4047
4048 b43_radio_write16(dev, 0x0081,
4049 (b43_radio_read16(dev, 0x0081) & ~0x0020) | 0x0010);
4050 msleep(1); /* delay 400usec */
4051
4052 b43_radio_write16(dev, 0x0005,
4053 (b43_radio_read16(dev, 0x0005) & ~0x0008) | 0x0008);
4054 b43_radio_write16(dev, 0x0085, b43_radio_read16(dev, 0x0085) & ~0x0010);
4055 b43_radio_write16(dev, 0x0005, b43_radio_read16(dev, 0x0005) & ~0x0008);
4056 b43_radio_write16(dev, 0x0081, b43_radio_read16(dev, 0x0081) & ~0x0040);
4057 b43_radio_write16(dev, 0x0081,
4058 (b43_radio_read16(dev, 0x0081) & ~0x0040) | 0x0040);
4059 b43_radio_write16(dev, 0x0005,
4060 (b43_radio_read16(dev, 0x0081) & ~0x0008) | 0x0008);
4061 b43_phy_write(dev, 0x0063, 0xDDC6);
4062 b43_phy_write(dev, 0x0069, 0x07BE);
4063 b43_phy_write(dev, 0x006A, 0x0000);
4064
4065 err = b43_radio_selectchannel(dev, B43_DEFAULT_CHANNEL_A, 0);
4066 B43_WARN_ON(err);
4067
4068 msleep(1);
4069 }
4070
4071 static inline u16 freq_r3A_value(u16 frequency)
4072 {
4073 u16 value;
4074
4075 if (frequency < 5091)
4076 value = 0x0040;
4077 else if (frequency < 5321)
4078 value = 0x0000;
4079 else if (frequency < 5806)
4080 value = 0x0080;
4081 else
4082 value = 0x0040;
4083
4084 return value;
4085 }
4086
4087 void b43_radio_set_tx_iq(struct b43_wldev *dev)
4088 {
4089 static const u8 data_high[5] = { 0x00, 0x40, 0x80, 0x90, 0xD0 };
4090 static const u8 data_low[5] = { 0x00, 0x01, 0x05, 0x06, 0x0A };
4091 u16 tmp = b43_radio_read16(dev, 0x001E);
4092 int i, j;
4093
4094 for (i = 0; i < 5; i++) {
4095 for (j = 0; j < 5; j++) {
4096 if (tmp == (data_high[i] << 4 | data_low[j])) {
4097 b43_phy_write(dev, 0x0069,
4098 (i - j) << 8 | 0x00C0);
4099 return;
4100 }
4101 }
4102 }
4103 }
4104
4105 int b43_radio_selectchannel(struct b43_wldev *dev,
4106 u8 channel, int synthetic_pu_workaround)
4107 {
4108 struct b43_phy *phy = &dev->phy;
4109 u16 r8, tmp;
4110 u16 freq;
4111 u16 channelcookie;
4112
4113 /* First we set the channel radio code to prevent the
4114 * firmware from sending ghost packets.
4115 */
4116 channelcookie = channel;
4117 if (phy->type == B43_PHYTYPE_A)
4118 channelcookie |= 0x100;
4119 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_CHAN, channelcookie);
4120
4121 if (phy->type == B43_PHYTYPE_A) {
4122 if (channel > 200)
4123 return -EINVAL;
4124 freq = channel2freq_a(channel);
4125
4126 r8 = b43_radio_read16(dev, 0x0008);
4127 b43_write16(dev, 0x03F0, freq);
4128 b43_radio_write16(dev, 0x0008, r8);
4129
4130 //TODO: write max channel TX power? to Radio 0x2D
4131 tmp = b43_radio_read16(dev, 0x002E);
4132 tmp &= 0x0080;
4133 //TODO: OR tmp with the Power out estimation for this channel?
4134 b43_radio_write16(dev, 0x002E, tmp);
4135
4136 if (freq >= 4920 && freq <= 5500) {
4137 /*
4138 * r8 = (((freq * 15 * 0xE1FC780F) >> 32) / 29) & 0x0F;
4139 * = (freq * 0.025862069
4140 */
4141 r8 = 3 * freq / 116; /* is equal to r8 = freq * 0.025862 */
4142 }
4143 b43_radio_write16(dev, 0x0007, (r8 << 4) | r8);
4144 b43_radio_write16(dev, 0x0020, (r8 << 4) | r8);
4145 b43_radio_write16(dev, 0x0021, (r8 << 4) | r8);
4146 b43_radio_write16(dev, 0x0022, (b43_radio_read16(dev, 0x0022)
4147 & 0x000F) | (r8 << 4));
4148 b43_radio_write16(dev, 0x002A, (r8 << 4));
4149 b43_radio_write16(dev, 0x002B, (r8 << 4));
4150 b43_radio_write16(dev, 0x0008, (b43_radio_read16(dev, 0x0008)
4151 & 0x00F0) | (r8 << 4));
4152 b43_radio_write16(dev, 0x0029, (b43_radio_read16(dev, 0x0029)
4153 & 0xFF0F) | 0x00B0);
4154 b43_radio_write16(dev, 0x0035, 0x00AA);
4155 b43_radio_write16(dev, 0x0036, 0x0085);
4156 b43_radio_write16(dev, 0x003A, (b43_radio_read16(dev, 0x003A)
4157 & 0xFF20) |
4158 freq_r3A_value(freq));
4159 b43_radio_write16(dev, 0x003D,
4160 b43_radio_read16(dev, 0x003D) & 0x00FF);
4161 b43_radio_write16(dev, 0x0081, (b43_radio_read16(dev, 0x0081)
4162 & 0xFF7F) | 0x0080);
4163 b43_radio_write16(dev, 0x0035,
4164 b43_radio_read16(dev, 0x0035) & 0xFFEF);
4165 b43_radio_write16(dev, 0x0035, (b43_radio_read16(dev, 0x0035)
4166 & 0xFFEF) | 0x0010);
4167 b43_radio_set_tx_iq(dev);
4168 //TODO: TSSI2dbm workaround
4169 b43_phy_xmitpower(dev); //FIXME correct?
4170 } else {
4171 if ((channel < 1) || (channel > 14))
4172 return -EINVAL;
4173
4174 if (synthetic_pu_workaround)
4175 b43_synth_pu_workaround(dev, channel);
4176
4177 b43_write16(dev, B43_MMIO_CHANNEL, channel2freq_bg(channel));
4178
4179 if (channel == 14) {
4180 if (dev->dev->bus->sprom.r1.country_code ==
4181 SSB_SPROM1CCODE_JAPAN)
4182 b43_hf_write(dev,
4183 b43_hf_read(dev) & ~B43_HF_ACPR);
4184 else
4185 b43_hf_write(dev,
4186 b43_hf_read(dev) | B43_HF_ACPR);
4187 b43_write16(dev, B43_MMIO_CHANNEL_EXT,
4188 b43_read16(dev, B43_MMIO_CHANNEL_EXT)
4189 | (1 << 11));
4190 } else {
4191 b43_write16(dev, B43_MMIO_CHANNEL_EXT,
4192 b43_read16(dev, B43_MMIO_CHANNEL_EXT)
4193 & 0xF7BF);
4194 }
4195 }
4196
4197 phy->channel = channel;
4198 /* Wait for the radio to tune to the channel and stabilize. */
4199 msleep(8);
4200
4201 return 0;
4202 }
4203
4204 /* http://bcm-specs.sipsolutions.net/TX_Gain_Base_Band */
4205 static u16 b43_get_txgain_base_band(u16 txpower)
4206 {
4207 u16 ret;
4208
4209 B43_WARN_ON(txpower > 63);
4210
4211 if (txpower >= 54)
4212 ret = 2;
4213 else if (txpower >= 49)
4214 ret = 4;
4215 else if (txpower >= 44)
4216 ret = 5;
4217 else
4218 ret = 6;
4219
4220 return ret;
4221 }
4222
4223 /* http://bcm-specs.sipsolutions.net/TX_Gain_Radio_Frequency_Power_Amplifier */
4224 static u16 b43_get_txgain_freq_power_amp(u16 txpower)
4225 {
4226 u16 ret;
4227
4228 B43_WARN_ON(txpower > 63);
4229
4230 if (txpower >= 32)
4231 ret = 0;
4232 else if (txpower >= 25)
4233 ret = 1;
4234 else if (txpower >= 20)
4235 ret = 2;
4236 else if (txpower >= 12)
4237 ret = 3;
4238 else
4239 ret = 4;
4240
4241 return ret;
4242 }
4243
4244 /* http://bcm-specs.sipsolutions.net/TX_Gain_Digital_Analog_Converter */
4245 static u16 b43_get_txgain_dac(u16 txpower)
4246 {
4247 u16 ret;
4248
4249 B43_WARN_ON(txpower > 63);
4250
4251 if (txpower >= 54)
4252 ret = txpower - 53;
4253 else if (txpower >= 49)
4254 ret = txpower - 42;
4255 else if (txpower >= 44)
4256 ret = txpower - 37;
4257 else if (txpower >= 32)
4258 ret = txpower - 32;
4259 else if (txpower >= 25)
4260 ret = txpower - 20;
4261 else if (txpower >= 20)
4262 ret = txpower - 13;
4263 else if (txpower >= 12)
4264 ret = txpower - 8;
4265 else
4266 ret = txpower;
4267
4268 return ret;
4269 }
4270
4271 static void b43_radio_set_txpower_a(struct b43_wldev *dev, u16 txpower)
4272 {
4273 struct b43_phy *phy = &dev->phy;
4274 u16 pamp, base, dac, t;
4275
4276 txpower = limit_value(txpower, 0, 63);
4277
4278 pamp = b43_get_txgain_freq_power_amp(txpower);
4279 pamp <<= 5;
4280 pamp &= 0x00E0;
4281 b43_phy_write(dev, 0x0019, pamp);
4282
4283 base = b43_get_txgain_base_band(txpower);
4284 base &= 0x000F;
4285 b43_phy_write(dev, 0x0017, base | 0x0020);
4286
4287 t = b43_ofdmtab_read16(dev, 0x3000, 1);
4288 t &= 0x0007;
4289
4290 dac = b43_get_txgain_dac(txpower);
4291 dac <<= 3;
4292 dac |= t;
4293
4294 b43_ofdmtab_write16(dev, 0x3000, 1, dac);
4295
4296 phy->txpwr_offset = txpower;
4297
4298 //TODO: FuncPlaceholder (Adjust BB loft cancel)
4299 }
4300
4301 void b43_radio_turn_on(struct b43_wldev *dev)
4302 {
4303 struct b43_phy *phy = &dev->phy;
4304 int err;
4305
4306 might_sleep();
4307
4308 if (phy->radio_on)
4309 return;
4310
4311 switch (phy->type) {
4312 case B43_PHYTYPE_A:
4313 b43_radio_write16(dev, 0x0004, 0x00C0);
4314 b43_radio_write16(dev, 0x0005, 0x0008);
4315 b43_phy_write(dev, 0x0010, b43_phy_read(dev, 0x0010) & 0xFFF7);
4316 b43_phy_write(dev, 0x0011, b43_phy_read(dev, 0x0011) & 0xFFF7);
4317 b43_radio_init2060(dev);
4318 break;
4319 case B43_PHYTYPE_B:
4320 case B43_PHYTYPE_G:
4321 b43_phy_write(dev, 0x0015, 0x8000);
4322 b43_phy_write(dev, 0x0015, 0xCC00);
4323 b43_phy_write(dev, 0x0015, (phy->gmode ? 0x00C0 : 0x0000));
4324 err = b43_radio_selectchannel(dev, B43_DEFAULT_CHANNEL_BG, 1);
4325 B43_WARN_ON(err);
4326 break;
4327 default:
4328 B43_WARN_ON(1);
4329 }
4330 phy->radio_on = 1;
4331 b43dbg(dev->wl, "Radio turned on\n");
4332 }
4333
4334 void b43_radio_turn_off(struct b43_wldev *dev)
4335 {
4336 struct b43_phy *phy = &dev->phy;
4337
4338 if (phy->type == B43_PHYTYPE_A) {
4339 b43_radio_write16(dev, 0x0004, 0x00FF);
4340 b43_radio_write16(dev, 0x0005, 0x00FB);
4341 b43_phy_write(dev, 0x0010, b43_phy_read(dev, 0x0010) | 0x0008);
4342 b43_phy_write(dev, 0x0011, b43_phy_read(dev, 0x0011) | 0x0008);
4343 }
4344 if (phy->type == B43_PHYTYPE_G && dev->dev->id.revision >= 5) {
4345 b43_phy_write(dev, 0x0811, b43_phy_read(dev, 0x0811) | 0x008C);
4346 b43_phy_write(dev, 0x0812, b43_phy_read(dev, 0x0812) & 0xFF73);
4347 } else
4348 b43_phy_write(dev, 0x0015, 0xAA00);
4349 phy->radio_on = 0;
4350 b43dbg(dev->wl, "Radio turned off\n");
4351 }
Linux kernel - Deliverables
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