3 Broadcom B43 wireless driver
4 IEEE 802.11g PHY driver
6 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>,
7 Copyright (c) 2005-2007 Stefano Brivio <stefano.brivio@polimi.it>
8 Copyright (c) 2005-2008 Michael Buesch <mb@bu3sch.de>
9 Copyright (c) 2005, 2006 Danny van Dyk <kugelfang@gentoo.org>
10 Copyright (c) 2005, 2006 Andreas Jaggi <andreas.jaggi@waterwave.ch>
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with this program; see the file COPYING. If not, write to
24 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
25 Boston, MA 02110-1301, USA.
31 #include "phy_common.h"
35 #include <linux/bitrev.h>
38 static const s8 b43_tssi2dbm_g_table
[] = {
57 const u8 b43_radio_channel_codes_bg
[] = {
65 static void b43_calc_nrssi_threshold(struct b43_wldev
*dev
);
68 #define bitrev4(tmp) (bitrev8(tmp) >> 4)
71 /* Get the freq, as it has to be written to the device. */
72 static inline u16
channel2freq_bg(u8 channel
)
74 B43_WARN_ON(!(channel
>= 1 && channel
<= 14));
76 return b43_radio_channel_codes_bg
[channel
- 1];
79 static void generate_rfatt_list(struct b43_wldev
*dev
,
80 struct b43_rfatt_list
*list
)
82 struct b43_phy
*phy
= &dev
->phy
;
84 /* APHY.rev < 5 || GPHY.rev < 6 */
85 static const struct b43_rfatt rfatt_0
[] = {
86 {.att
= 3,.with_padmix
= 0,},
87 {.att
= 1,.with_padmix
= 0,},
88 {.att
= 5,.with_padmix
= 0,},
89 {.att
= 7,.with_padmix
= 0,},
90 {.att
= 9,.with_padmix
= 0,},
91 {.att
= 2,.with_padmix
= 0,},
92 {.att
= 0,.with_padmix
= 0,},
93 {.att
= 4,.with_padmix
= 0,},
94 {.att
= 6,.with_padmix
= 0,},
95 {.att
= 8,.with_padmix
= 0,},
96 {.att
= 1,.with_padmix
= 1,},
97 {.att
= 2,.with_padmix
= 1,},
98 {.att
= 3,.with_padmix
= 1,},
99 {.att
= 4,.with_padmix
= 1,},
101 /* Radio.rev == 8 && Radio.version == 0x2050 */
102 static const struct b43_rfatt rfatt_1
[] = {
103 {.att
= 2,.with_padmix
= 1,},
104 {.att
= 4,.with_padmix
= 1,},
105 {.att
= 6,.with_padmix
= 1,},
106 {.att
= 8,.with_padmix
= 1,},
107 {.att
= 10,.with_padmix
= 1,},
108 {.att
= 12,.with_padmix
= 1,},
109 {.att
= 14,.with_padmix
= 1,},
112 static const struct b43_rfatt rfatt_2
[] = {
113 {.att
= 0,.with_padmix
= 1,},
114 {.att
= 2,.with_padmix
= 1,},
115 {.att
= 4,.with_padmix
= 1,},
116 {.att
= 6,.with_padmix
= 1,},
117 {.att
= 8,.with_padmix
= 1,},
118 {.att
= 9,.with_padmix
= 1,},
119 {.att
= 9,.with_padmix
= 1,},
122 if (!b43_has_hardware_pctl(dev
)) {
124 list
->list
= rfatt_0
;
125 list
->len
= ARRAY_SIZE(rfatt_0
);
130 if (phy
->radio_ver
== 0x2050 && phy
->radio_rev
== 8) {
132 list
->list
= rfatt_1
;
133 list
->len
= ARRAY_SIZE(rfatt_1
);
139 list
->list
= rfatt_2
;
140 list
->len
= ARRAY_SIZE(rfatt_2
);
145 static void generate_bbatt_list(struct b43_wldev
*dev
,
146 struct b43_bbatt_list
*list
)
148 static const struct b43_bbatt bbatt_0
[] = {
160 list
->list
= bbatt_0
;
161 list
->len
= ARRAY_SIZE(bbatt_0
);
166 static void b43_shm_clear_tssi(struct b43_wldev
*dev
)
168 b43_shm_write16(dev
, B43_SHM_SHARED
, 0x0058, 0x7F7F);
169 b43_shm_write16(dev
, B43_SHM_SHARED
, 0x005a, 0x7F7F);
170 b43_shm_write16(dev
, B43_SHM_SHARED
, 0x0070, 0x7F7F);
171 b43_shm_write16(dev
, B43_SHM_SHARED
, 0x0072, 0x7F7F);
174 /* Synthetic PU workaround */
175 static void b43_synth_pu_workaround(struct b43_wldev
*dev
, u8 channel
)
177 struct b43_phy
*phy
= &dev
->phy
;
181 if (phy
->radio_ver
!= 0x2050 || phy
->radio_rev
>= 6) {
182 /* We do not need the workaround. */
187 b43_write16(dev
, B43_MMIO_CHANNEL
,
188 channel2freq_bg(channel
+ 4));
190 b43_write16(dev
, B43_MMIO_CHANNEL
, channel2freq_bg(1));
193 b43_write16(dev
, B43_MMIO_CHANNEL
, channel2freq_bg(channel
));
196 /* Set the baseband attenuation value on chip. */
197 void b43_gphy_set_baseband_attenuation(struct b43_wldev
*dev
,
198 u16 baseband_attenuation
)
200 struct b43_phy
*phy
= &dev
->phy
;
202 if (phy
->analog
== 0) {
203 b43_write16(dev
, B43_MMIO_PHY0
, (b43_read16(dev
, B43_MMIO_PHY0
)
205 baseband_attenuation
);
206 } else if (phy
->analog
> 1) {
207 b43_phy_write(dev
, B43_PHY_DACCTL
,
208 (b43_phy_read(dev
, B43_PHY_DACCTL
)
209 & 0xFFC3) | (baseband_attenuation
<< 2));
211 b43_phy_write(dev
, B43_PHY_DACCTL
,
212 (b43_phy_read(dev
, B43_PHY_DACCTL
)
213 & 0xFF87) | (baseband_attenuation
<< 3));
217 /* Adjust the transmission power output (G-PHY) */
218 void b43_set_txpower_g(struct b43_wldev
*dev
,
219 const struct b43_bbatt
*bbatt
,
220 const struct b43_rfatt
*rfatt
, u8 tx_control
)
222 struct b43_phy
*phy
= &dev
->phy
;
223 struct b43_phy_g
*gphy
= phy
->g
;
224 struct b43_txpower_lo_control
*lo
= gphy
->lo_control
;
226 u16 tx_bias
, tx_magn
;
230 tx_bias
= lo
->tx_bias
;
231 tx_magn
= lo
->tx_magn
;
232 if (unlikely(tx_bias
== 0xFF))
235 /* Save the values for later. Use memmove, because it's valid
236 * to pass &gphy->rfatt as rfatt pointer argument. Same for bbatt. */
237 gphy
->tx_control
= tx_control
;
238 memmove(&gphy
->rfatt
, rfatt
, sizeof(*rfatt
));
239 gphy
->rfatt
.with_padmix
= !!(tx_control
& B43_TXCTL_TXMIX
);
240 memmove(&gphy
->bbatt
, bbatt
, sizeof(*bbatt
));
242 if (b43_debug(dev
, B43_DBG_XMITPOWER
)) {
243 b43dbg(dev
->wl
, "Tuning TX-power to bbatt(%u), "
244 "rfatt(%u), tx_control(0x%02X), "
245 "tx_bias(0x%02X), tx_magn(0x%02X)\n",
246 bb
, rf
, tx_control
, tx_bias
, tx_magn
);
249 b43_gphy_set_baseband_attenuation(dev
, bb
);
250 b43_shm_write16(dev
, B43_SHM_SHARED
, B43_SHM_SH_RFATT
, rf
);
251 if (phy
->radio_ver
== 0x2050 && phy
->radio_rev
== 8) {
252 b43_radio_write16(dev
, 0x43,
253 (rf
& 0x000F) | (tx_control
& 0x0070));
255 b43_radio_write16(dev
, 0x43, (b43_radio_read16(dev
, 0x43)
256 & 0xFFF0) | (rf
& 0x000F));
257 b43_radio_write16(dev
, 0x52, (b43_radio_read16(dev
, 0x52)
258 & ~0x0070) | (tx_control
&
261 if (has_tx_magnification(phy
)) {
262 b43_radio_write16(dev
, 0x52, tx_magn
| tx_bias
);
264 b43_radio_write16(dev
, 0x52, (b43_radio_read16(dev
, 0x52)
265 & 0xFFF0) | (tx_bias
& 0x000F));
267 b43_lo_g_adjust(dev
);
270 /* GPHY_TSSI_Power_Lookup_Table_Init */
271 static void b43_gphy_tssi_power_lt_init(struct b43_wldev
*dev
)
273 struct b43_phy_g
*gphy
= dev
->phy
.g
;
277 for (i
= 0; i
< 32; i
++)
278 b43_ofdmtab_write16(dev
, 0x3C20, i
, gphy
->tssi2dbm
[i
]);
279 for (i
= 32; i
< 64; i
++)
280 b43_ofdmtab_write16(dev
, 0x3C00, i
- 32, gphy
->tssi2dbm
[i
]);
281 for (i
= 0; i
< 64; i
+= 2) {
282 value
= (u16
) gphy
->tssi2dbm
[i
];
283 value
|= ((u16
) gphy
->tssi2dbm
[i
+ 1]) << 8;
284 b43_phy_write(dev
, 0x380 + (i
/ 2), value
);
288 /* GPHY_Gain_Lookup_Table_Init */
289 static void b43_gphy_gain_lt_init(struct b43_wldev
*dev
)
291 struct b43_phy
*phy
= &dev
->phy
;
292 struct b43_phy_g
*gphy
= phy
->g
;
293 struct b43_txpower_lo_control
*lo
= gphy
->lo_control
;
298 for (rf
= 0; rf
< lo
->rfatt_list
.len
; rf
++) {
299 for (bb
= 0; bb
< lo
->bbatt_list
.len
; bb
++) {
300 if (nr_written
>= 0x40)
302 tmp
= lo
->bbatt_list
.list
[bb
].att
;
304 if (phy
->radio_rev
== 8)
308 tmp
|= lo
->rfatt_list
.list
[rf
].att
;
309 b43_phy_write(dev
, 0x3C0 + nr_written
, tmp
);
315 static void b43_set_all_gains(struct b43_wldev
*dev
,
316 s16 first
, s16 second
, s16 third
)
318 struct b43_phy
*phy
= &dev
->phy
;
320 u16 start
= 0x08, end
= 0x18;
329 table
= B43_OFDMTAB_GAINX
;
331 table
= B43_OFDMTAB_GAINX_R1
;
332 for (i
= 0; i
< 4; i
++)
333 b43_ofdmtab_write16(dev
, table
, i
, first
);
335 for (i
= start
; i
< end
; i
++)
336 b43_ofdmtab_write16(dev
, table
, i
, second
);
339 tmp
= ((u16
) third
<< 14) | ((u16
) third
<< 6);
340 b43_phy_write(dev
, 0x04A0,
341 (b43_phy_read(dev
, 0x04A0) & 0xBFBF) | tmp
);
342 b43_phy_write(dev
, 0x04A1,
343 (b43_phy_read(dev
, 0x04A1) & 0xBFBF) | tmp
);
344 b43_phy_write(dev
, 0x04A2,
345 (b43_phy_read(dev
, 0x04A2) & 0xBFBF) | tmp
);
347 b43_dummy_transmission(dev
);
350 static void b43_set_original_gains(struct b43_wldev
*dev
)
352 struct b43_phy
*phy
= &dev
->phy
;
355 u16 start
= 0x0008, end
= 0x0018;
362 table
= B43_OFDMTAB_GAINX
;
364 table
= B43_OFDMTAB_GAINX_R1
;
365 for (i
= 0; i
< 4; i
++) {
367 tmp
|= (i
& 0x0001) << 1;
368 tmp
|= (i
& 0x0002) >> 1;
370 b43_ofdmtab_write16(dev
, table
, i
, tmp
);
373 for (i
= start
; i
< end
; i
++)
374 b43_ofdmtab_write16(dev
, table
, i
, i
- start
);
376 b43_phy_write(dev
, 0x04A0,
377 (b43_phy_read(dev
, 0x04A0) & 0xBFBF) | 0x4040);
378 b43_phy_write(dev
, 0x04A1,
379 (b43_phy_read(dev
, 0x04A1) & 0xBFBF) | 0x4040);
380 b43_phy_write(dev
, 0x04A2,
381 (b43_phy_read(dev
, 0x04A2) & 0xBFBF) | 0x4000);
382 b43_dummy_transmission(dev
);
385 /* http://bcm-specs.sipsolutions.net/NRSSILookupTable */
386 void b43_nrssi_hw_write(struct b43_wldev
*dev
, u16 offset
, s16 val
)
388 b43_phy_write(dev
, B43_PHY_NRSSILT_CTRL
, offset
);
389 b43_phy_write(dev
, B43_PHY_NRSSILT_DATA
, (u16
) val
);
392 /* http://bcm-specs.sipsolutions.net/NRSSILookupTable */
393 s16
b43_nrssi_hw_read(struct b43_wldev
*dev
, u16 offset
)
397 b43_phy_write(dev
, B43_PHY_NRSSILT_CTRL
, offset
);
398 val
= b43_phy_read(dev
, B43_PHY_NRSSILT_DATA
);
403 /* http://bcm-specs.sipsolutions.net/NRSSILookupTable */
404 void b43_nrssi_hw_update(struct b43_wldev
*dev
, u16 val
)
409 for (i
= 0; i
< 64; i
++) {
410 tmp
= b43_nrssi_hw_read(dev
, i
);
412 tmp
= clamp_val(tmp
, -32, 31);
413 b43_nrssi_hw_write(dev
, i
, tmp
);
417 /* http://bcm-specs.sipsolutions.net/NRSSILookupTable */
418 void b43_nrssi_mem_update(struct b43_wldev
*dev
)
420 struct b43_phy_g
*gphy
= dev
->phy
.g
;
424 delta
= 0x1F - gphy
->nrssi
[0];
425 for (i
= 0; i
< 64; i
++) {
426 tmp
= (i
- delta
) * gphy
->nrssislope
;
429 tmp
= clamp_val(tmp
, 0, 0x3F);
430 gphy
->nrssi_lt
[i
] = tmp
;
434 static void b43_calc_nrssi_offset(struct b43_wldev
*dev
)
436 struct b43_phy
*phy
= &dev
->phy
;
437 u16 backup
[20] = { 0 };
442 backup
[0] = b43_phy_read(dev
, 0x0001);
443 backup
[1] = b43_phy_read(dev
, 0x0811);
444 backup
[2] = b43_phy_read(dev
, 0x0812);
445 if (phy
->rev
!= 1) { /* Not in specs, but needed to prevent PPC machine check */
446 backup
[3] = b43_phy_read(dev
, 0x0814);
447 backup
[4] = b43_phy_read(dev
, 0x0815);
449 backup
[5] = b43_phy_read(dev
, 0x005A);
450 backup
[6] = b43_phy_read(dev
, 0x0059);
451 backup
[7] = b43_phy_read(dev
, 0x0058);
452 backup
[8] = b43_phy_read(dev
, 0x000A);
453 backup
[9] = b43_phy_read(dev
, 0x0003);
454 backup
[10] = b43_radio_read16(dev
, 0x007A);
455 backup
[11] = b43_radio_read16(dev
, 0x0043);
457 b43_phy_write(dev
, 0x0429, b43_phy_read(dev
, 0x0429) & 0x7FFF);
458 b43_phy_write(dev
, 0x0001,
459 (b43_phy_read(dev
, 0x0001) & 0x3FFF) | 0x4000);
460 b43_phy_write(dev
, 0x0811, b43_phy_read(dev
, 0x0811) | 0x000C);
461 b43_phy_write(dev
, 0x0812,
462 (b43_phy_read(dev
, 0x0812) & 0xFFF3) | 0x0004);
463 b43_phy_write(dev
, 0x0802, b43_phy_read(dev
, 0x0802) & ~(0x1 | 0x2));
465 backup
[12] = b43_phy_read(dev
, 0x002E);
466 backup
[13] = b43_phy_read(dev
, 0x002F);
467 backup
[14] = b43_phy_read(dev
, 0x080F);
468 backup
[15] = b43_phy_read(dev
, 0x0810);
469 backup
[16] = b43_phy_read(dev
, 0x0801);
470 backup
[17] = b43_phy_read(dev
, 0x0060);
471 backup
[18] = b43_phy_read(dev
, 0x0014);
472 backup
[19] = b43_phy_read(dev
, 0x0478);
474 b43_phy_write(dev
, 0x002E, 0);
475 b43_phy_write(dev
, 0x002F, 0);
476 b43_phy_write(dev
, 0x080F, 0);
477 b43_phy_write(dev
, 0x0810, 0);
478 b43_phy_write(dev
, 0x0478, b43_phy_read(dev
, 0x0478) | 0x0100);
479 b43_phy_write(dev
, 0x0801, b43_phy_read(dev
, 0x0801) | 0x0040);
480 b43_phy_write(dev
, 0x0060, b43_phy_read(dev
, 0x0060) | 0x0040);
481 b43_phy_write(dev
, 0x0014, b43_phy_read(dev
, 0x0014) | 0x0200);
483 b43_radio_write16(dev
, 0x007A, b43_radio_read16(dev
, 0x007A) | 0x0070);
484 b43_radio_write16(dev
, 0x007A, b43_radio_read16(dev
, 0x007A) | 0x0080);
487 v47F
= (s16
) ((b43_phy_read(dev
, 0x047F) >> 8) & 0x003F);
491 for (i
= 7; i
>= 4; i
--) {
492 b43_radio_write16(dev
, 0x007B, i
);
495 (s16
) ((b43_phy_read(dev
, 0x047F) >> 8) & 0x003F);
498 if (v47F
< 31 && saved
== 0xFFFF)
504 b43_radio_write16(dev
, 0x007A,
505 b43_radio_read16(dev
, 0x007A) & 0x007F);
506 if (phy
->rev
!= 1) { /* Not in specs, but needed to prevent PPC machine check */
507 b43_phy_write(dev
, 0x0814,
508 b43_phy_read(dev
, 0x0814) | 0x0001);
509 b43_phy_write(dev
, 0x0815,
510 b43_phy_read(dev
, 0x0815) & 0xFFFE);
512 b43_phy_write(dev
, 0x0811, b43_phy_read(dev
, 0x0811) | 0x000C);
513 b43_phy_write(dev
, 0x0812, b43_phy_read(dev
, 0x0812) | 0x000C);
514 b43_phy_write(dev
, 0x0811, b43_phy_read(dev
, 0x0811) | 0x0030);
515 b43_phy_write(dev
, 0x0812, b43_phy_read(dev
, 0x0812) | 0x0030);
516 b43_phy_write(dev
, 0x005A, 0x0480);
517 b43_phy_write(dev
, 0x0059, 0x0810);
518 b43_phy_write(dev
, 0x0058, 0x000D);
520 b43_phy_write(dev
, 0x0003, 0x0122);
522 b43_phy_write(dev
, 0x000A, b43_phy_read(dev
, 0x000A)
525 if (phy
->rev
!= 1) { /* Not in specs, but needed to prevent PPC machine check */
526 b43_phy_write(dev
, 0x0814,
527 b43_phy_read(dev
, 0x0814) | 0x0004);
528 b43_phy_write(dev
, 0x0815,
529 b43_phy_read(dev
, 0x0815) & 0xFFFB);
531 b43_phy_write(dev
, 0x0003, (b43_phy_read(dev
, 0x0003) & 0xFF9F)
533 b43_radio_write16(dev
, 0x007A,
534 b43_radio_read16(dev
, 0x007A) | 0x000F);
535 b43_set_all_gains(dev
, 3, 0, 1);
536 b43_radio_write16(dev
, 0x0043, (b43_radio_read16(dev
, 0x0043)
539 v47F
= (s16
) ((b43_phy_read(dev
, 0x047F) >> 8) & 0x003F);
543 for (i
= 0; i
< 4; i
++) {
544 b43_radio_write16(dev
, 0x007B, i
);
547 (s16
) ((b43_phy_read(dev
, 0x047F) >> 8) &
551 if (v47F
> -31 && saved
== 0xFFFF)
559 b43_radio_write16(dev
, 0x007B, saved
);
562 b43_phy_write(dev
, 0x002E, backup
[12]);
563 b43_phy_write(dev
, 0x002F, backup
[13]);
564 b43_phy_write(dev
, 0x080F, backup
[14]);
565 b43_phy_write(dev
, 0x0810, backup
[15]);
567 if (phy
->rev
!= 1) { /* Not in specs, but needed to prevent PPC machine check */
568 b43_phy_write(dev
, 0x0814, backup
[3]);
569 b43_phy_write(dev
, 0x0815, backup
[4]);
571 b43_phy_write(dev
, 0x005A, backup
[5]);
572 b43_phy_write(dev
, 0x0059, backup
[6]);
573 b43_phy_write(dev
, 0x0058, backup
[7]);
574 b43_phy_write(dev
, 0x000A, backup
[8]);
575 b43_phy_write(dev
, 0x0003, backup
[9]);
576 b43_radio_write16(dev
, 0x0043, backup
[11]);
577 b43_radio_write16(dev
, 0x007A, backup
[10]);
578 b43_phy_write(dev
, 0x0802, b43_phy_read(dev
, 0x0802) | 0x1 | 0x2);
579 b43_phy_write(dev
, 0x0429, b43_phy_read(dev
, 0x0429) | 0x8000);
580 b43_set_original_gains(dev
);
582 b43_phy_write(dev
, 0x0801, backup
[16]);
583 b43_phy_write(dev
, 0x0060, backup
[17]);
584 b43_phy_write(dev
, 0x0014, backup
[18]);
585 b43_phy_write(dev
, 0x0478, backup
[19]);
587 b43_phy_write(dev
, 0x0001, backup
[0]);
588 b43_phy_write(dev
, 0x0812, backup
[2]);
589 b43_phy_write(dev
, 0x0811, backup
[1]);
592 void b43_calc_nrssi_slope(struct b43_wldev
*dev
)
594 struct b43_phy
*phy
= &dev
->phy
;
595 struct b43_phy_g
*gphy
= phy
->g
;
596 u16 backup
[18] = { 0 };
600 B43_WARN_ON(phy
->type
!= B43_PHYTYPE_G
);
602 if (phy
->radio_rev
>= 9)
604 if (phy
->radio_rev
== 8)
605 b43_calc_nrssi_offset(dev
);
607 b43_phy_write(dev
, B43_PHY_G_CRS
,
608 b43_phy_read(dev
, B43_PHY_G_CRS
) & 0x7FFF);
609 b43_phy_write(dev
, 0x0802, b43_phy_read(dev
, 0x0802) & 0xFFFC);
610 backup
[7] = b43_read16(dev
, 0x03E2);
611 b43_write16(dev
, 0x03E2, b43_read16(dev
, 0x03E2) | 0x8000);
612 backup
[0] = b43_radio_read16(dev
, 0x007A);
613 backup
[1] = b43_radio_read16(dev
, 0x0052);
614 backup
[2] = b43_radio_read16(dev
, 0x0043);
615 backup
[3] = b43_phy_read(dev
, 0x0015);
616 backup
[4] = b43_phy_read(dev
, 0x005A);
617 backup
[5] = b43_phy_read(dev
, 0x0059);
618 backup
[6] = b43_phy_read(dev
, 0x0058);
619 backup
[8] = b43_read16(dev
, 0x03E6);
620 backup
[9] = b43_read16(dev
, B43_MMIO_CHANNEL_EXT
);
622 backup
[10] = b43_phy_read(dev
, 0x002E);
623 backup
[11] = b43_phy_read(dev
, 0x002F);
624 backup
[12] = b43_phy_read(dev
, 0x080F);
625 backup
[13] = b43_phy_read(dev
, B43_PHY_G_LO_CONTROL
);
626 backup
[14] = b43_phy_read(dev
, 0x0801);
627 backup
[15] = b43_phy_read(dev
, 0x0060);
628 backup
[16] = b43_phy_read(dev
, 0x0014);
629 backup
[17] = b43_phy_read(dev
, 0x0478);
630 b43_phy_write(dev
, 0x002E, 0);
631 b43_phy_write(dev
, B43_PHY_G_LO_CONTROL
, 0);
636 b43_phy_write(dev
, 0x0478,
637 b43_phy_read(dev
, 0x0478)
639 b43_phy_write(dev
, 0x0801,
640 b43_phy_read(dev
, 0x0801)
645 b43_phy_write(dev
, 0x0801,
646 b43_phy_read(dev
, 0x0801)
650 b43_phy_write(dev
, 0x0060, b43_phy_read(dev
, 0x0060)
652 b43_phy_write(dev
, 0x0014, b43_phy_read(dev
, 0x0014)
655 b43_radio_write16(dev
, 0x007A,
656 b43_radio_read16(dev
, 0x007A) | 0x0070);
657 b43_set_all_gains(dev
, 0, 8, 0);
658 b43_radio_write16(dev
, 0x007A,
659 b43_radio_read16(dev
, 0x007A) & 0x00F7);
661 b43_phy_write(dev
, 0x0811,
662 (b43_phy_read(dev
, 0x0811) & 0xFFCF) |
664 b43_phy_write(dev
, 0x0812,
665 (b43_phy_read(dev
, 0x0812) & 0xFFCF) |
668 b43_radio_write16(dev
, 0x007A,
669 b43_radio_read16(dev
, 0x007A) | 0x0080);
672 nrssi0
= (s16
) ((b43_phy_read(dev
, 0x047F) >> 8) & 0x003F);
673 if (nrssi0
>= 0x0020)
676 b43_radio_write16(dev
, 0x007A,
677 b43_radio_read16(dev
, 0x007A) & 0x007F);
679 b43_phy_write(dev
, 0x0003, (b43_phy_read(dev
, 0x0003)
683 b43_write16(dev
, B43_MMIO_CHANNEL_EXT
,
684 b43_read16(dev
, B43_MMIO_CHANNEL_EXT
)
686 b43_radio_write16(dev
, 0x007A,
687 b43_radio_read16(dev
, 0x007A) | 0x000F);
688 b43_phy_write(dev
, 0x0015, 0xF330);
690 b43_phy_write(dev
, 0x0812,
691 (b43_phy_read(dev
, 0x0812) & 0xFFCF) |
693 b43_phy_write(dev
, 0x0811,
694 (b43_phy_read(dev
, 0x0811) & 0xFFCF) |
698 b43_set_all_gains(dev
, 3, 0, 1);
699 if (phy
->radio_rev
== 8) {
700 b43_radio_write16(dev
, 0x0043, 0x001F);
702 tmp
= b43_radio_read16(dev
, 0x0052) & 0xFF0F;
703 b43_radio_write16(dev
, 0x0052, tmp
| 0x0060);
704 tmp
= b43_radio_read16(dev
, 0x0043) & 0xFFF0;
705 b43_radio_write16(dev
, 0x0043, tmp
| 0x0009);
707 b43_phy_write(dev
, 0x005A, 0x0480);
708 b43_phy_write(dev
, 0x0059, 0x0810);
709 b43_phy_write(dev
, 0x0058, 0x000D);
711 nrssi1
= (s16
) ((b43_phy_read(dev
, 0x047F) >> 8) & 0x003F);
712 if (nrssi1
>= 0x0020)
714 if (nrssi0
== nrssi1
)
715 gphy
->nrssislope
= 0x00010000;
717 gphy
->nrssislope
= 0x00400000 / (nrssi0
- nrssi1
);
719 gphy
->nrssi
[0] = nrssi1
;
720 gphy
->nrssi
[1] = nrssi0
;
723 b43_phy_write(dev
, 0x002E, backup
[10]);
724 b43_phy_write(dev
, 0x002F, backup
[11]);
725 b43_phy_write(dev
, 0x080F, backup
[12]);
726 b43_phy_write(dev
, B43_PHY_G_LO_CONTROL
, backup
[13]);
729 b43_phy_write(dev
, 0x0812,
730 b43_phy_read(dev
, 0x0812) & 0xFFCF);
731 b43_phy_write(dev
, 0x0811,
732 b43_phy_read(dev
, 0x0811) & 0xFFCF);
735 b43_radio_write16(dev
, 0x007A, backup
[0]);
736 b43_radio_write16(dev
, 0x0052, backup
[1]);
737 b43_radio_write16(dev
, 0x0043, backup
[2]);
738 b43_write16(dev
, 0x03E2, backup
[7]);
739 b43_write16(dev
, 0x03E6, backup
[8]);
740 b43_write16(dev
, B43_MMIO_CHANNEL_EXT
, backup
[9]);
741 b43_phy_write(dev
, 0x0015, backup
[3]);
742 b43_phy_write(dev
, 0x005A, backup
[4]);
743 b43_phy_write(dev
, 0x0059, backup
[5]);
744 b43_phy_write(dev
, 0x0058, backup
[6]);
745 b43_synth_pu_workaround(dev
, phy
->channel
);
746 b43_phy_write(dev
, 0x0802,
747 b43_phy_read(dev
, 0x0802) | (0x0001 | 0x0002));
748 b43_set_original_gains(dev
);
749 b43_phy_write(dev
, B43_PHY_G_CRS
,
750 b43_phy_read(dev
, B43_PHY_G_CRS
) | 0x8000);
752 b43_phy_write(dev
, 0x0801, backup
[14]);
753 b43_phy_write(dev
, 0x0060, backup
[15]);
754 b43_phy_write(dev
, 0x0014, backup
[16]);
755 b43_phy_write(dev
, 0x0478, backup
[17]);
757 b43_nrssi_mem_update(dev
);
758 b43_calc_nrssi_threshold(dev
);
761 static void b43_calc_nrssi_threshold(struct b43_wldev
*dev
)
763 struct b43_phy
*phy
= &dev
->phy
;
764 struct b43_phy_g
*gphy
= phy
->g
;
769 B43_WARN_ON(phy
->type
!= B43_PHYTYPE_G
);
772 !(dev
->dev
->bus
->sprom
.boardflags_lo
& B43_BFL_RSSI
)) {
773 tmp16
= b43_nrssi_hw_read(dev
, 0x20);
777 b43_phy_write(dev
, 0x048A,
778 (b43_phy_read(dev
, 0x048A)
781 b43_phy_write(dev
, 0x048A,
782 (b43_phy_read(dev
, 0x048A)
786 if (gphy
->interfmode
== B43_INTERFMODE_NONWLAN
) {
789 } else if (!gphy
->aci_wlan_automatic
&& gphy
->aci_enable
) {
797 a
= a
* (gphy
->nrssi
[1] - gphy
->nrssi
[0]);
798 a
+= (gphy
->nrssi
[0] << 6);
804 a
= clamp_val(a
, -31, 31);
806 b
= b
* (gphy
->nrssi
[1] - gphy
->nrssi
[0]);
807 b
+= (gphy
->nrssi
[0] << 6);
813 b
= clamp_val(b
, -31, 31);
815 tmp_u16
= b43_phy_read(dev
, 0x048A) & 0xF000;
816 tmp_u16
|= ((u32
) b
& 0x0000003F);
817 tmp_u16
|= (((u32
) a
& 0x0000003F) << 6);
818 b43_phy_write(dev
, 0x048A, tmp_u16
);
822 /* Stack implementation to save/restore values from the
823 * interference mitigation code.
824 * It is save to restore values in random order.
826 static void _stack_save(u32
* _stackptr
, size_t * stackidx
,
827 u8 id
, u16 offset
, u16 value
)
829 u32
*stackptr
= &(_stackptr
[*stackidx
]);
831 B43_WARN_ON(offset
& 0xF000);
832 B43_WARN_ON(id
& 0xF0);
834 *stackptr
|= ((u32
) id
) << 12;
835 *stackptr
|= ((u32
) value
) << 16;
837 B43_WARN_ON(*stackidx
>= B43_INTERFSTACK_SIZE
);
840 static u16
_stack_restore(u32
* stackptr
, u8 id
, u16 offset
)
844 B43_WARN_ON(offset
& 0xF000);
845 B43_WARN_ON(id
& 0xF0);
846 for (i
= 0; i
< B43_INTERFSTACK_SIZE
; i
++, stackptr
++) {
847 if ((*stackptr
& 0x00000FFF) != offset
)
849 if (((*stackptr
& 0x0000F000) >> 12) != id
)
851 return ((*stackptr
& 0xFFFF0000) >> 16);
858 #define phy_stacksave(offset) \
860 _stack_save(stack, &stackidx, 0x1, (offset), \
861 b43_phy_read(dev, (offset))); \
863 #define phy_stackrestore(offset) \
865 b43_phy_write(dev, (offset), \
866 _stack_restore(stack, 0x1, \
869 #define radio_stacksave(offset) \
871 _stack_save(stack, &stackidx, 0x2, (offset), \
872 b43_radio_read16(dev, (offset))); \
874 #define radio_stackrestore(offset) \
876 b43_radio_write16(dev, (offset), \
877 _stack_restore(stack, 0x2, \
880 #define ofdmtab_stacksave(table, offset) \
882 _stack_save(stack, &stackidx, 0x3, (offset)|(table), \
883 b43_ofdmtab_read16(dev, (table), (offset))); \
885 #define ofdmtab_stackrestore(table, offset) \
887 b43_ofdmtab_write16(dev, (table), (offset), \
888 _stack_restore(stack, 0x3, \
889 (offset)|(table))); \
893 b43_radio_interference_mitigation_enable(struct b43_wldev
*dev
, int mode
)
895 struct b43_phy
*phy
= &dev
->phy
;
896 struct b43_phy_g
*gphy
= phy
->g
;
899 u32
*stack
= gphy
->interfstack
;
902 case B43_INTERFMODE_NONWLAN
:
904 b43_phy_write(dev
, 0x042B,
905 b43_phy_read(dev
, 0x042B) | 0x0800);
906 b43_phy_write(dev
, B43_PHY_G_CRS
,
908 B43_PHY_G_CRS
) & ~0x4000);
911 radio_stacksave(0x0078);
912 tmp
= (b43_radio_read16(dev
, 0x0078) & 0x001E);
913 B43_WARN_ON(tmp
> 15);
914 flipped
= bitrev4(tmp
);
915 if (flipped
< 10 && flipped
>= 8)
917 else if (flipped
>= 10)
919 flipped
= (bitrev4(flipped
) << 1) | 0x0020;
920 b43_radio_write16(dev
, 0x0078, flipped
);
922 b43_calc_nrssi_threshold(dev
);
924 phy_stacksave(0x0406);
925 b43_phy_write(dev
, 0x0406, 0x7E28);
927 b43_phy_write(dev
, 0x042B, b43_phy_read(dev
, 0x042B) | 0x0800);
928 b43_phy_write(dev
, B43_PHY_RADIO_BITFIELD
,
930 B43_PHY_RADIO_BITFIELD
) | 0x1000);
932 phy_stacksave(0x04A0);
933 b43_phy_write(dev
, 0x04A0,
934 (b43_phy_read(dev
, 0x04A0) & 0xC0C0) | 0x0008);
935 phy_stacksave(0x04A1);
936 b43_phy_write(dev
, 0x04A1,
937 (b43_phy_read(dev
, 0x04A1) & 0xC0C0) | 0x0605);
938 phy_stacksave(0x04A2);
939 b43_phy_write(dev
, 0x04A2,
940 (b43_phy_read(dev
, 0x04A2) & 0xC0C0) | 0x0204);
941 phy_stacksave(0x04A8);
942 b43_phy_write(dev
, 0x04A8,
943 (b43_phy_read(dev
, 0x04A8) & 0xC0C0) | 0x0803);
944 phy_stacksave(0x04AB);
945 b43_phy_write(dev
, 0x04AB,
946 (b43_phy_read(dev
, 0x04AB) & 0xC0C0) | 0x0605);
948 phy_stacksave(0x04A7);
949 b43_phy_write(dev
, 0x04A7, 0x0002);
950 phy_stacksave(0x04A3);
951 b43_phy_write(dev
, 0x04A3, 0x287A);
952 phy_stacksave(0x04A9);
953 b43_phy_write(dev
, 0x04A9, 0x2027);
954 phy_stacksave(0x0493);
955 b43_phy_write(dev
, 0x0493, 0x32F5);
956 phy_stacksave(0x04AA);
957 b43_phy_write(dev
, 0x04AA, 0x2027);
958 phy_stacksave(0x04AC);
959 b43_phy_write(dev
, 0x04AC, 0x32F5);
961 case B43_INTERFMODE_MANUALWLAN
:
962 if (b43_phy_read(dev
, 0x0033) & 0x0800)
965 gphy
->aci_enable
= 1;
967 phy_stacksave(B43_PHY_RADIO_BITFIELD
);
968 phy_stacksave(B43_PHY_G_CRS
);
970 phy_stacksave(0x0406);
972 phy_stacksave(0x04C0);
973 phy_stacksave(0x04C1);
975 phy_stacksave(0x0033);
976 phy_stacksave(0x04A7);
977 phy_stacksave(0x04A3);
978 phy_stacksave(0x04A9);
979 phy_stacksave(0x04AA);
980 phy_stacksave(0x04AC);
981 phy_stacksave(0x0493);
982 phy_stacksave(0x04A1);
983 phy_stacksave(0x04A0);
984 phy_stacksave(0x04A2);
985 phy_stacksave(0x048A);
986 phy_stacksave(0x04A8);
987 phy_stacksave(0x04AB);
989 phy_stacksave(0x04AD);
990 phy_stacksave(0x04AE);
991 } else if (phy
->rev
>= 3) {
992 phy_stacksave(0x04AD);
993 phy_stacksave(0x0415);
994 phy_stacksave(0x0416);
995 phy_stacksave(0x0417);
996 ofdmtab_stacksave(0x1A00, 0x2);
997 ofdmtab_stacksave(0x1A00, 0x3);
999 phy_stacksave(0x042B);
1000 phy_stacksave(0x048C);
1002 b43_phy_write(dev
, B43_PHY_RADIO_BITFIELD
,
1003 b43_phy_read(dev
, B43_PHY_RADIO_BITFIELD
)
1005 b43_phy_write(dev
, B43_PHY_G_CRS
,
1006 (b43_phy_read(dev
, B43_PHY_G_CRS
)
1007 & 0xFFFC) | 0x0002);
1009 b43_phy_write(dev
, 0x0033, 0x0800);
1010 b43_phy_write(dev
, 0x04A3, 0x2027);
1011 b43_phy_write(dev
, 0x04A9, 0x1CA8);
1012 b43_phy_write(dev
, 0x0493, 0x287A);
1013 b43_phy_write(dev
, 0x04AA, 0x1CA8);
1014 b43_phy_write(dev
, 0x04AC, 0x287A);
1016 b43_phy_write(dev
, 0x04A0, (b43_phy_read(dev
, 0x04A0)
1017 & 0xFFC0) | 0x001A);
1018 b43_phy_write(dev
, 0x04A7, 0x000D);
1021 b43_phy_write(dev
, 0x0406, 0xFF0D);
1022 } else if (phy
->rev
== 2) {
1023 b43_phy_write(dev
, 0x04C0, 0xFFFF);
1024 b43_phy_write(dev
, 0x04C1, 0x00A9);
1026 b43_phy_write(dev
, 0x04C0, 0x00C1);
1027 b43_phy_write(dev
, 0x04C1, 0x0059);
1030 b43_phy_write(dev
, 0x04A1, (b43_phy_read(dev
, 0x04A1)
1031 & 0xC0FF) | 0x1800);
1032 b43_phy_write(dev
, 0x04A1, (b43_phy_read(dev
, 0x04A1)
1033 & 0xFFC0) | 0x0015);
1034 b43_phy_write(dev
, 0x04A8, (b43_phy_read(dev
, 0x04A8)
1035 & 0xCFFF) | 0x1000);
1036 b43_phy_write(dev
, 0x04A8, (b43_phy_read(dev
, 0x04A8)
1037 & 0xF0FF) | 0x0A00);
1038 b43_phy_write(dev
, 0x04AB, (b43_phy_read(dev
, 0x04AB)
1039 & 0xCFFF) | 0x1000);
1040 b43_phy_write(dev
, 0x04AB, (b43_phy_read(dev
, 0x04AB)
1041 & 0xF0FF) | 0x0800);
1042 b43_phy_write(dev
, 0x04AB, (b43_phy_read(dev
, 0x04AB)
1043 & 0xFFCF) | 0x0010);
1044 b43_phy_write(dev
, 0x04AB, (b43_phy_read(dev
, 0x04AB)
1045 & 0xFFF0) | 0x0005);
1046 b43_phy_write(dev
, 0x04A8, (b43_phy_read(dev
, 0x04A8)
1047 & 0xFFCF) | 0x0010);
1048 b43_phy_write(dev
, 0x04A8, (b43_phy_read(dev
, 0x04A8)
1049 & 0xFFF0) | 0x0006);
1050 b43_phy_write(dev
, 0x04A2, (b43_phy_read(dev
, 0x04A2)
1051 & 0xF0FF) | 0x0800);
1052 b43_phy_write(dev
, 0x04A0, (b43_phy_read(dev
, 0x04A0)
1053 & 0xF0FF) | 0x0500);
1054 b43_phy_write(dev
, 0x04A2, (b43_phy_read(dev
, 0x04A2)
1055 & 0xFFF0) | 0x000B);
1057 if (phy
->rev
>= 3) {
1058 b43_phy_write(dev
, 0x048A, b43_phy_read(dev
, 0x048A)
1060 b43_phy_write(dev
, 0x0415, (b43_phy_read(dev
, 0x0415)
1061 & 0x8000) | 0x36D8);
1062 b43_phy_write(dev
, 0x0416, (b43_phy_read(dev
, 0x0416)
1063 & 0x8000) | 0x36D8);
1064 b43_phy_write(dev
, 0x0417, (b43_phy_read(dev
, 0x0417)
1065 & 0xFE00) | 0x016D);
1067 b43_phy_write(dev
, 0x048A, b43_phy_read(dev
, 0x048A)
1069 b43_phy_write(dev
, 0x048A, (b43_phy_read(dev
, 0x048A)
1070 & 0x9FFF) | 0x2000);
1071 b43_hf_write(dev
, b43_hf_read(dev
) | B43_HF_ACIW
);
1073 if (phy
->rev
>= 2) {
1074 b43_phy_write(dev
, 0x042B, b43_phy_read(dev
, 0x042B)
1077 b43_phy_write(dev
, 0x048C, (b43_phy_read(dev
, 0x048C)
1078 & 0xF0FF) | 0x0200);
1079 if (phy
->rev
== 2) {
1080 b43_phy_write(dev
, 0x04AE, (b43_phy_read(dev
, 0x04AE)
1081 & 0xFF00) | 0x007F);
1082 b43_phy_write(dev
, 0x04AD, (b43_phy_read(dev
, 0x04AD)
1083 & 0x00FF) | 0x1300);
1084 } else if (phy
->rev
>= 6) {
1085 b43_ofdmtab_write16(dev
, 0x1A00, 0x3, 0x007F);
1086 b43_ofdmtab_write16(dev
, 0x1A00, 0x2, 0x007F);
1087 b43_phy_write(dev
, 0x04AD, b43_phy_read(dev
, 0x04AD)
1090 b43_calc_nrssi_slope(dev
);
1098 b43_radio_interference_mitigation_disable(struct b43_wldev
*dev
, int mode
)
1100 struct b43_phy
*phy
= &dev
->phy
;
1101 struct b43_phy_g
*gphy
= phy
->g
;
1102 u32
*stack
= gphy
->interfstack
;
1105 case B43_INTERFMODE_NONWLAN
:
1106 if (phy
->rev
!= 1) {
1107 b43_phy_write(dev
, 0x042B,
1108 b43_phy_read(dev
, 0x042B) & ~0x0800);
1109 b43_phy_write(dev
, B43_PHY_G_CRS
,
1111 B43_PHY_G_CRS
) | 0x4000);
1114 radio_stackrestore(0x0078);
1115 b43_calc_nrssi_threshold(dev
);
1116 phy_stackrestore(0x0406);
1117 b43_phy_write(dev
, 0x042B, b43_phy_read(dev
, 0x042B) & ~0x0800);
1118 if (!dev
->bad_frames_preempt
) {
1119 b43_phy_write(dev
, B43_PHY_RADIO_BITFIELD
,
1120 b43_phy_read(dev
, B43_PHY_RADIO_BITFIELD
)
1123 b43_phy_write(dev
, B43_PHY_G_CRS
,
1124 b43_phy_read(dev
, B43_PHY_G_CRS
) | 0x4000);
1125 phy_stackrestore(0x04A0);
1126 phy_stackrestore(0x04A1);
1127 phy_stackrestore(0x04A2);
1128 phy_stackrestore(0x04A8);
1129 phy_stackrestore(0x04AB);
1130 phy_stackrestore(0x04A7);
1131 phy_stackrestore(0x04A3);
1132 phy_stackrestore(0x04A9);
1133 phy_stackrestore(0x0493);
1134 phy_stackrestore(0x04AA);
1135 phy_stackrestore(0x04AC);
1137 case B43_INTERFMODE_MANUALWLAN
:
1138 if (!(b43_phy_read(dev
, 0x0033) & 0x0800))
1141 gphy
->aci_enable
= 0;
1143 phy_stackrestore(B43_PHY_RADIO_BITFIELD
);
1144 phy_stackrestore(B43_PHY_G_CRS
);
1145 phy_stackrestore(0x0033);
1146 phy_stackrestore(0x04A3);
1147 phy_stackrestore(0x04A9);
1148 phy_stackrestore(0x0493);
1149 phy_stackrestore(0x04AA);
1150 phy_stackrestore(0x04AC);
1151 phy_stackrestore(0x04A0);
1152 phy_stackrestore(0x04A7);
1153 if (phy
->rev
>= 2) {
1154 phy_stackrestore(0x04C0);
1155 phy_stackrestore(0x04C1);
1157 phy_stackrestore(0x0406);
1158 phy_stackrestore(0x04A1);
1159 phy_stackrestore(0x04AB);
1160 phy_stackrestore(0x04A8);
1161 if (phy
->rev
== 2) {
1162 phy_stackrestore(0x04AD);
1163 phy_stackrestore(0x04AE);
1164 } else if (phy
->rev
>= 3) {
1165 phy_stackrestore(0x04AD);
1166 phy_stackrestore(0x0415);
1167 phy_stackrestore(0x0416);
1168 phy_stackrestore(0x0417);
1169 ofdmtab_stackrestore(0x1A00, 0x2);
1170 ofdmtab_stackrestore(0x1A00, 0x3);
1172 phy_stackrestore(0x04A2);
1173 phy_stackrestore(0x048A);
1174 phy_stackrestore(0x042B);
1175 phy_stackrestore(0x048C);
1176 b43_hf_write(dev
, b43_hf_read(dev
) & ~B43_HF_ACIW
);
1177 b43_calc_nrssi_slope(dev
);
1184 #undef phy_stacksave
1185 #undef phy_stackrestore
1186 #undef radio_stacksave
1187 #undef radio_stackrestore
1188 #undef ofdmtab_stacksave
1189 #undef ofdmtab_stackrestore
1191 static u16
b43_radio_core_calibration_value(struct b43_wldev
*dev
)
1193 u16 reg
, index
, ret
;
1195 static const u8 rcc_table
[] = {
1196 0x02, 0x03, 0x01, 0x0F,
1197 0x06, 0x07, 0x05, 0x0F,
1198 0x0A, 0x0B, 0x09, 0x0F,
1199 0x0E, 0x0F, 0x0D, 0x0F,
1202 reg
= b43_radio_read16(dev
, 0x60);
1203 index
= (reg
& 0x001E) >> 1;
1204 ret
= rcc_table
[index
] << 1;
1205 ret
|= (reg
& 0x0001);
1211 #define LPD(L, P, D) (((L) << 2) | ((P) << 1) | ((D) << 0))
1212 static u16
radio2050_rfover_val(struct b43_wldev
*dev
,
1213 u16 phy_register
, unsigned int lpd
)
1215 struct b43_phy
*phy
= &dev
->phy
;
1216 struct b43_phy_g
*gphy
= phy
->g
;
1217 struct ssb_sprom
*sprom
= &(dev
->dev
->bus
->sprom
);
1222 if (has_loopback_gain(phy
)) {
1223 int max_lb_gain
= gphy
->max_lb_gain
;
1227 if (phy
->radio_rev
== 8)
1228 max_lb_gain
+= 0x3E;
1230 max_lb_gain
+= 0x26;
1231 if (max_lb_gain
>= 0x46) {
1233 max_lb_gain
-= 0x46;
1234 } else if (max_lb_gain
>= 0x3A) {
1236 max_lb_gain
-= 0x3A;
1237 } else if (max_lb_gain
>= 0x2E) {
1239 max_lb_gain
-= 0x2E;
1242 max_lb_gain
-= 0x10;
1245 for (i
= 0; i
< 16; i
++) {
1246 max_lb_gain
-= (i
* 6);
1247 if (max_lb_gain
< 6)
1251 if ((phy
->rev
< 7) ||
1252 !(sprom
->boardflags_lo
& B43_BFL_EXTLNA
)) {
1253 if (phy_register
== B43_PHY_RFOVER
) {
1255 } else if (phy_register
== B43_PHY_RFOVERVAL
) {
1262 return (0x0092 | extlna
);
1264 return (0x0093 | extlna
);
1270 if (phy_register
== B43_PHY_RFOVER
) {
1272 } else if (phy_register
== B43_PHY_RFOVERVAL
) {
1280 return (0x8092 | extlna
);
1282 return (0x2092 | extlna
);
1284 return (0x2093 | extlna
);
1291 if ((phy
->rev
< 7) ||
1292 !(sprom
->boardflags_lo
& B43_BFL_EXTLNA
)) {
1293 if (phy_register
== B43_PHY_RFOVER
) {
1295 } else if (phy_register
== B43_PHY_RFOVERVAL
) {
1310 if (phy_register
== B43_PHY_RFOVER
) {
1312 } else if (phy_register
== B43_PHY_RFOVERVAL
) {
1331 struct init2050_saved_values
{
1332 /* Core registers */
1336 /* Radio registers */
1349 u16 phy_analogoverval
;
1357 u16
b43_radio_init2050(struct b43_wldev
*dev
)
1359 struct b43_phy
*phy
= &dev
->phy
;
1360 struct init2050_saved_values sav
;
1365 u32 tmp1
= 0, tmp2
= 0;
1367 memset(&sav
, 0, sizeof(sav
)); /* get rid of "may be used uninitialized..." */
1369 sav
.radio_43
= b43_radio_read16(dev
, 0x43);
1370 sav
.radio_51
= b43_radio_read16(dev
, 0x51);
1371 sav
.radio_52
= b43_radio_read16(dev
, 0x52);
1372 sav
.phy_pgactl
= b43_phy_read(dev
, B43_PHY_PGACTL
);
1373 sav
.phy_cck_5A
= b43_phy_read(dev
, B43_PHY_CCK(0x5A));
1374 sav
.phy_cck_59
= b43_phy_read(dev
, B43_PHY_CCK(0x59));
1375 sav
.phy_cck_58
= b43_phy_read(dev
, B43_PHY_CCK(0x58));
1377 if (phy
->type
== B43_PHYTYPE_B
) {
1378 sav
.phy_cck_30
= b43_phy_read(dev
, B43_PHY_CCK(0x30));
1379 sav
.reg_3EC
= b43_read16(dev
, 0x3EC);
1381 b43_phy_write(dev
, B43_PHY_CCK(0x30), 0xFF);
1382 b43_write16(dev
, 0x3EC, 0x3F3F);
1383 } else if (phy
->gmode
|| phy
->rev
>= 2) {
1384 sav
.phy_rfover
= b43_phy_read(dev
, B43_PHY_RFOVER
);
1385 sav
.phy_rfoverval
= b43_phy_read(dev
, B43_PHY_RFOVERVAL
);
1386 sav
.phy_analogover
= b43_phy_read(dev
, B43_PHY_ANALOGOVER
);
1387 sav
.phy_analogoverval
=
1388 b43_phy_read(dev
, B43_PHY_ANALOGOVERVAL
);
1389 sav
.phy_crs0
= b43_phy_read(dev
, B43_PHY_CRS0
);
1390 sav
.phy_classctl
= b43_phy_read(dev
, B43_PHY_CLASSCTL
);
1392 b43_phy_write(dev
, B43_PHY_ANALOGOVER
,
1393 b43_phy_read(dev
, B43_PHY_ANALOGOVER
)
1395 b43_phy_write(dev
, B43_PHY_ANALOGOVERVAL
,
1396 b43_phy_read(dev
, B43_PHY_ANALOGOVERVAL
)
1398 b43_phy_write(dev
, B43_PHY_CRS0
, b43_phy_read(dev
, B43_PHY_CRS0
)
1400 b43_phy_write(dev
, B43_PHY_CLASSCTL
,
1401 b43_phy_read(dev
, B43_PHY_CLASSCTL
)
1403 if (has_loopback_gain(phy
)) {
1404 sav
.phy_lo_mask
= b43_phy_read(dev
, B43_PHY_LO_MASK
);
1405 sav
.phy_lo_ctl
= b43_phy_read(dev
, B43_PHY_LO_CTL
);
1408 b43_phy_write(dev
, B43_PHY_LO_MASK
, 0xC020);
1410 b43_phy_write(dev
, B43_PHY_LO_MASK
, 0x8020);
1411 b43_phy_write(dev
, B43_PHY_LO_CTL
, 0);
1414 b43_phy_write(dev
, B43_PHY_RFOVERVAL
,
1415 radio2050_rfover_val(dev
, B43_PHY_RFOVERVAL
,
1417 b43_phy_write(dev
, B43_PHY_RFOVER
,
1418 radio2050_rfover_val(dev
, B43_PHY_RFOVER
, 0));
1420 b43_write16(dev
, 0x3E2, b43_read16(dev
, 0x3E2) | 0x8000);
1422 sav
.phy_syncctl
= b43_phy_read(dev
, B43_PHY_SYNCCTL
);
1423 b43_phy_write(dev
, B43_PHY_SYNCCTL
, b43_phy_read(dev
, B43_PHY_SYNCCTL
)
1425 sav
.reg_3E6
= b43_read16(dev
, 0x3E6);
1426 sav
.reg_3F4
= b43_read16(dev
, 0x3F4);
1428 if (phy
->analog
== 0) {
1429 b43_write16(dev
, 0x03E6, 0x0122);
1431 if (phy
->analog
>= 2) {
1432 b43_phy_write(dev
, B43_PHY_CCK(0x03),
1433 (b43_phy_read(dev
, B43_PHY_CCK(0x03))
1436 b43_write16(dev
, B43_MMIO_CHANNEL_EXT
,
1437 (b43_read16(dev
, B43_MMIO_CHANNEL_EXT
) | 0x2000));
1440 rcc
= b43_radio_core_calibration_value(dev
);
1442 if (phy
->type
== B43_PHYTYPE_B
)
1443 b43_radio_write16(dev
, 0x78, 0x26);
1444 if (phy
->gmode
|| phy
->rev
>= 2) {
1445 b43_phy_write(dev
, B43_PHY_RFOVERVAL
,
1446 radio2050_rfover_val(dev
, B43_PHY_RFOVERVAL
,
1449 b43_phy_write(dev
, B43_PHY_PGACTL
, 0xBFAF);
1450 b43_phy_write(dev
, B43_PHY_CCK(0x2B), 0x1403);
1451 if (phy
->gmode
|| phy
->rev
>= 2) {
1452 b43_phy_write(dev
, B43_PHY_RFOVERVAL
,
1453 radio2050_rfover_val(dev
, B43_PHY_RFOVERVAL
,
1456 b43_phy_write(dev
, B43_PHY_PGACTL
, 0xBFA0);
1457 b43_radio_write16(dev
, 0x51, b43_radio_read16(dev
, 0x51)
1459 if (phy
->radio_rev
== 8) {
1460 b43_radio_write16(dev
, 0x43, 0x1F);
1462 b43_radio_write16(dev
, 0x52, 0);
1463 b43_radio_write16(dev
, 0x43, (b43_radio_read16(dev
, 0x43)
1464 & 0xFFF0) | 0x0009);
1466 b43_phy_write(dev
, B43_PHY_CCK(0x58), 0);
1468 for (i
= 0; i
< 16; i
++) {
1469 b43_phy_write(dev
, B43_PHY_CCK(0x5A), 0x0480);
1470 b43_phy_write(dev
, B43_PHY_CCK(0x59), 0xC810);
1471 b43_phy_write(dev
, B43_PHY_CCK(0x58), 0x000D);
1472 if (phy
->gmode
|| phy
->rev
>= 2) {
1473 b43_phy_write(dev
, B43_PHY_RFOVERVAL
,
1474 radio2050_rfover_val(dev
,
1478 b43_phy_write(dev
, B43_PHY_PGACTL
, 0xAFB0);
1480 if (phy
->gmode
|| phy
->rev
>= 2) {
1481 b43_phy_write(dev
, B43_PHY_RFOVERVAL
,
1482 radio2050_rfover_val(dev
,
1486 b43_phy_write(dev
, B43_PHY_PGACTL
, 0xEFB0);
1488 if (phy
->gmode
|| phy
->rev
>= 2) {
1489 b43_phy_write(dev
, B43_PHY_RFOVERVAL
,
1490 radio2050_rfover_val(dev
,
1494 b43_phy_write(dev
, B43_PHY_PGACTL
, 0xFFF0);
1496 tmp1
+= b43_phy_read(dev
, B43_PHY_LO_LEAKAGE
);
1497 b43_phy_write(dev
, B43_PHY_CCK(0x58), 0);
1498 if (phy
->gmode
|| phy
->rev
>= 2) {
1499 b43_phy_write(dev
, B43_PHY_RFOVERVAL
,
1500 radio2050_rfover_val(dev
,
1504 b43_phy_write(dev
, B43_PHY_PGACTL
, 0xAFB0);
1508 b43_phy_write(dev
, B43_PHY_CCK(0x58), 0);
1512 for (i
= 0; i
< 16; i
++) {
1513 radio78
= (bitrev4(i
) << 1) | 0x0020;
1514 b43_radio_write16(dev
, 0x78, radio78
);
1516 for (j
= 0; j
< 16; j
++) {
1517 b43_phy_write(dev
, B43_PHY_CCK(0x5A), 0x0D80);
1518 b43_phy_write(dev
, B43_PHY_CCK(0x59), 0xC810);
1519 b43_phy_write(dev
, B43_PHY_CCK(0x58), 0x000D);
1520 if (phy
->gmode
|| phy
->rev
>= 2) {
1521 b43_phy_write(dev
, B43_PHY_RFOVERVAL
,
1522 radio2050_rfover_val(dev
,
1527 b43_phy_write(dev
, B43_PHY_PGACTL
, 0xAFB0);
1529 if (phy
->gmode
|| phy
->rev
>= 2) {
1530 b43_phy_write(dev
, B43_PHY_RFOVERVAL
,
1531 radio2050_rfover_val(dev
,
1536 b43_phy_write(dev
, B43_PHY_PGACTL
, 0xEFB0);
1538 if (phy
->gmode
|| phy
->rev
>= 2) {
1539 b43_phy_write(dev
, B43_PHY_RFOVERVAL
,
1540 radio2050_rfover_val(dev
,
1545 b43_phy_write(dev
, B43_PHY_PGACTL
, 0xFFF0);
1547 tmp2
+= b43_phy_read(dev
, B43_PHY_LO_LEAKAGE
);
1548 b43_phy_write(dev
, B43_PHY_CCK(0x58), 0);
1549 if (phy
->gmode
|| phy
->rev
>= 2) {
1550 b43_phy_write(dev
, B43_PHY_RFOVERVAL
,
1551 radio2050_rfover_val(dev
,
1556 b43_phy_write(dev
, B43_PHY_PGACTL
, 0xAFB0);
1564 /* Restore the registers */
1565 b43_phy_write(dev
, B43_PHY_PGACTL
, sav
.phy_pgactl
);
1566 b43_radio_write16(dev
, 0x51, sav
.radio_51
);
1567 b43_radio_write16(dev
, 0x52, sav
.radio_52
);
1568 b43_radio_write16(dev
, 0x43, sav
.radio_43
);
1569 b43_phy_write(dev
, B43_PHY_CCK(0x5A), sav
.phy_cck_5A
);
1570 b43_phy_write(dev
, B43_PHY_CCK(0x59), sav
.phy_cck_59
);
1571 b43_phy_write(dev
, B43_PHY_CCK(0x58), sav
.phy_cck_58
);
1572 b43_write16(dev
, 0x3E6, sav
.reg_3E6
);
1573 if (phy
->analog
!= 0)
1574 b43_write16(dev
, 0x3F4, sav
.reg_3F4
);
1575 b43_phy_write(dev
, B43_PHY_SYNCCTL
, sav
.phy_syncctl
);
1576 b43_synth_pu_workaround(dev
, phy
->channel
);
1577 if (phy
->type
== B43_PHYTYPE_B
) {
1578 b43_phy_write(dev
, B43_PHY_CCK(0x30), sav
.phy_cck_30
);
1579 b43_write16(dev
, 0x3EC, sav
.reg_3EC
);
1580 } else if (phy
->gmode
) {
1581 b43_write16(dev
, B43_MMIO_PHY_RADIO
,
1582 b43_read16(dev
, B43_MMIO_PHY_RADIO
)
1584 b43_phy_write(dev
, B43_PHY_RFOVER
, sav
.phy_rfover
);
1585 b43_phy_write(dev
, B43_PHY_RFOVERVAL
, sav
.phy_rfoverval
);
1586 b43_phy_write(dev
, B43_PHY_ANALOGOVER
, sav
.phy_analogover
);
1587 b43_phy_write(dev
, B43_PHY_ANALOGOVERVAL
,
1588 sav
.phy_analogoverval
);
1589 b43_phy_write(dev
, B43_PHY_CRS0
, sav
.phy_crs0
);
1590 b43_phy_write(dev
, B43_PHY_CLASSCTL
, sav
.phy_classctl
);
1591 if (has_loopback_gain(phy
)) {
1592 b43_phy_write(dev
, B43_PHY_LO_MASK
, sav
.phy_lo_mask
);
1593 b43_phy_write(dev
, B43_PHY_LO_CTL
, sav
.phy_lo_ctl
);
1604 static void b43_phy_initb5(struct b43_wldev
*dev
)
1606 struct ssb_bus
*bus
= dev
->dev
->bus
;
1607 struct b43_phy
*phy
= &dev
->phy
;
1608 struct b43_phy_g
*gphy
= phy
->g
;
1612 if (phy
->analog
== 1) {
1613 b43_radio_write16(dev
, 0x007A, b43_radio_read16(dev
, 0x007A)
1616 if ((bus
->boardinfo
.vendor
!= SSB_BOARDVENDOR_BCM
) &&
1617 (bus
->boardinfo
.type
!= SSB_BOARD_BU4306
)) {
1619 for (offset
= 0x00A8; offset
< 0x00C7; offset
++) {
1620 b43_phy_write(dev
, offset
, value
);
1624 b43_phy_write(dev
, 0x0035, (b43_phy_read(dev
, 0x0035) & 0xF0FF)
1626 if (phy
->radio_ver
== 0x2050)
1627 b43_phy_write(dev
, 0x0038, 0x0667);
1629 if (phy
->gmode
|| phy
->rev
>= 2) {
1630 if (phy
->radio_ver
== 0x2050) {
1631 b43_radio_write16(dev
, 0x007A,
1632 b43_radio_read16(dev
, 0x007A)
1634 b43_radio_write16(dev
, 0x0051,
1635 b43_radio_read16(dev
, 0x0051)
1638 b43_write16(dev
, B43_MMIO_PHY_RADIO
, 0x0000);
1640 b43_phy_write(dev
, 0x0802, b43_phy_read(dev
, 0x0802) | 0x0100);
1641 b43_phy_write(dev
, 0x042B, b43_phy_read(dev
, 0x042B) | 0x2000);
1643 b43_phy_write(dev
, 0x001C, 0x186A);
1645 b43_phy_write(dev
, 0x0013,
1646 (b43_phy_read(dev
, 0x0013) & 0x00FF) | 0x1900);
1647 b43_phy_write(dev
, 0x0035,
1648 (b43_phy_read(dev
, 0x0035) & 0xFFC0) | 0x0064);
1649 b43_phy_write(dev
, 0x005D,
1650 (b43_phy_read(dev
, 0x005D) & 0xFF80) | 0x000A);
1653 if (dev
->bad_frames_preempt
) {
1654 b43_phy_write(dev
, B43_PHY_RADIO_BITFIELD
,
1656 B43_PHY_RADIO_BITFIELD
) | (1 << 11));
1659 if (phy
->analog
== 1) {
1660 b43_phy_write(dev
, 0x0026, 0xCE00);
1661 b43_phy_write(dev
, 0x0021, 0x3763);
1662 b43_phy_write(dev
, 0x0022, 0x1BC3);
1663 b43_phy_write(dev
, 0x0023, 0x06F9);
1664 b43_phy_write(dev
, 0x0024, 0x037E);
1666 b43_phy_write(dev
, 0x0026, 0xCC00);
1667 b43_phy_write(dev
, 0x0030, 0x00C6);
1668 b43_write16(dev
, 0x03EC, 0x3F22);
1670 if (phy
->analog
== 1)
1671 b43_phy_write(dev
, 0x0020, 0x3E1C);
1673 b43_phy_write(dev
, 0x0020, 0x301C);
1675 if (phy
->analog
== 0)
1676 b43_write16(dev
, 0x03E4, 0x3000);
1678 old_channel
= phy
->channel
;
1679 /* Force to channel 7, even if not supported. */
1680 b43_gphy_channel_switch(dev
, 7, 0);
1682 if (phy
->radio_ver
!= 0x2050) {
1683 b43_radio_write16(dev
, 0x0075, 0x0080);
1684 b43_radio_write16(dev
, 0x0079, 0x0081);
1687 b43_radio_write16(dev
, 0x0050, 0x0020);
1688 b43_radio_write16(dev
, 0x0050, 0x0023);
1690 if (phy
->radio_ver
== 0x2050) {
1691 b43_radio_write16(dev
, 0x0050, 0x0020);
1692 b43_radio_write16(dev
, 0x005A, 0x0070);
1695 b43_radio_write16(dev
, 0x005B, 0x007B);
1696 b43_radio_write16(dev
, 0x005C, 0x00B0);
1698 b43_radio_write16(dev
, 0x007A, b43_radio_read16(dev
, 0x007A) | 0x0007);
1700 b43_gphy_channel_switch(dev
, old_channel
, 0);
1702 b43_phy_write(dev
, 0x0014, 0x0080);
1703 b43_phy_write(dev
, 0x0032, 0x00CA);
1704 b43_phy_write(dev
, 0x002A, 0x88A3);
1706 b43_set_txpower_g(dev
, &gphy
->bbatt
, &gphy
->rfatt
, gphy
->tx_control
);
1708 if (phy
->radio_ver
== 0x2050)
1709 b43_radio_write16(dev
, 0x005D, 0x000D);
1711 b43_write16(dev
, 0x03E4, (b43_read16(dev
, 0x03E4) & 0xFFC0) | 0x0004);
1714 static void b43_phy_initb6(struct b43_wldev
*dev
)
1716 struct b43_phy
*phy
= &dev
->phy
;
1717 struct b43_phy_g
*gphy
= phy
->g
;
1721 b43_phy_write(dev
, 0x003E, 0x817A);
1722 b43_radio_write16(dev
, 0x007A,
1723 (b43_radio_read16(dev
, 0x007A) | 0x0058));
1724 if (phy
->radio_rev
== 4 || phy
->radio_rev
== 5) {
1725 b43_radio_write16(dev
, 0x51, 0x37);
1726 b43_radio_write16(dev
, 0x52, 0x70);
1727 b43_radio_write16(dev
, 0x53, 0xB3);
1728 b43_radio_write16(dev
, 0x54, 0x9B);
1729 b43_radio_write16(dev
, 0x5A, 0x88);
1730 b43_radio_write16(dev
, 0x5B, 0x88);
1731 b43_radio_write16(dev
, 0x5D, 0x88);
1732 b43_radio_write16(dev
, 0x5E, 0x88);
1733 b43_radio_write16(dev
, 0x7D, 0x88);
1734 b43_hf_write(dev
, b43_hf_read(dev
)
1735 | B43_HF_TSSIRPSMW
);
1737 B43_WARN_ON(phy
->radio_rev
== 6 || phy
->radio_rev
== 7); /* We had code for these revs here... */
1738 if (phy
->radio_rev
== 8) {
1739 b43_radio_write16(dev
, 0x51, 0);
1740 b43_radio_write16(dev
, 0x52, 0x40);
1741 b43_radio_write16(dev
, 0x53, 0xB7);
1742 b43_radio_write16(dev
, 0x54, 0x98);
1743 b43_radio_write16(dev
, 0x5A, 0x88);
1744 b43_radio_write16(dev
, 0x5B, 0x6B);
1745 b43_radio_write16(dev
, 0x5C, 0x0F);
1746 if (dev
->dev
->bus
->sprom
.boardflags_lo
& B43_BFL_ALTIQ
) {
1747 b43_radio_write16(dev
, 0x5D, 0xFA);
1748 b43_radio_write16(dev
, 0x5E, 0xD8);
1750 b43_radio_write16(dev
, 0x5D, 0xF5);
1751 b43_radio_write16(dev
, 0x5E, 0xB8);
1753 b43_radio_write16(dev
, 0x0073, 0x0003);
1754 b43_radio_write16(dev
, 0x007D, 0x00A8);
1755 b43_radio_write16(dev
, 0x007C, 0x0001);
1756 b43_radio_write16(dev
, 0x007E, 0x0008);
1759 for (offset
= 0x0088; offset
< 0x0098; offset
++) {
1760 b43_phy_write(dev
, offset
, val
);
1764 for (offset
= 0x0098; offset
< 0x00A8; offset
++) {
1765 b43_phy_write(dev
, offset
, val
);
1769 for (offset
= 0x00A8; offset
< 0x00C8; offset
++) {
1770 b43_phy_write(dev
, offset
, (val
& 0x3F3F));
1773 if (phy
->type
== B43_PHYTYPE_G
) {
1774 b43_radio_write16(dev
, 0x007A,
1775 b43_radio_read16(dev
, 0x007A) | 0x0020);
1776 b43_radio_write16(dev
, 0x0051,
1777 b43_radio_read16(dev
, 0x0051) | 0x0004);
1778 b43_phy_write(dev
, 0x0802, b43_phy_read(dev
, 0x0802) | 0x0100);
1779 b43_phy_write(dev
, 0x042B, b43_phy_read(dev
, 0x042B) | 0x2000);
1780 b43_phy_write(dev
, 0x5B, 0);
1781 b43_phy_write(dev
, 0x5C, 0);
1784 old_channel
= phy
->channel
;
1785 if (old_channel
>= 8)
1786 b43_gphy_channel_switch(dev
, 1, 0);
1788 b43_gphy_channel_switch(dev
, 13, 0);
1790 b43_radio_write16(dev
, 0x0050, 0x0020);
1791 b43_radio_write16(dev
, 0x0050, 0x0023);
1793 if (phy
->radio_rev
< 6 || phy
->radio_rev
== 8) {
1794 b43_radio_write16(dev
, 0x7C, (b43_radio_read16(dev
, 0x7C)
1796 b43_radio_write16(dev
, 0x50, 0x20);
1798 if (phy
->radio_rev
<= 2) {
1799 b43_radio_write16(dev
, 0x7C, 0x20);
1800 b43_radio_write16(dev
, 0x5A, 0x70);
1801 b43_radio_write16(dev
, 0x5B, 0x7B);
1802 b43_radio_write16(dev
, 0x5C, 0xB0);
1804 b43_radio_write16(dev
, 0x007A,
1805 (b43_radio_read16(dev
, 0x007A) & 0x00F8) | 0x0007);
1807 b43_gphy_channel_switch(dev
, old_channel
, 0);
1809 b43_phy_write(dev
, 0x0014, 0x0200);
1810 if (phy
->radio_rev
>= 6)
1811 b43_phy_write(dev
, 0x2A, 0x88C2);
1813 b43_phy_write(dev
, 0x2A, 0x8AC0);
1814 b43_phy_write(dev
, 0x0038, 0x0668);
1815 b43_set_txpower_g(dev
, &gphy
->bbatt
, &gphy
->rfatt
, gphy
->tx_control
);
1816 if (phy
->radio_rev
<= 5) {
1817 b43_phy_write(dev
, 0x5D, (b43_phy_read(dev
, 0x5D)
1818 & 0xFF80) | 0x0003);
1820 if (phy
->radio_rev
<= 2)
1821 b43_radio_write16(dev
, 0x005D, 0x000D);
1823 if (phy
->analog
== 4) {
1824 b43_write16(dev
, 0x3E4, 9);
1825 b43_phy_write(dev
, 0x61, b43_phy_read(dev
, 0x61)
1828 b43_phy_write(dev
, 0x0002, (b43_phy_read(dev
, 0x0002) & 0xFFC0)
1831 if (phy
->type
== B43_PHYTYPE_B
)
1833 else if (phy
->type
== B43_PHYTYPE_G
)
1834 b43_write16(dev
, 0x03E6, 0x0);
1837 static void b43_calc_loopback_gain(struct b43_wldev
*dev
)
1839 struct b43_phy
*phy
= &dev
->phy
;
1840 struct b43_phy_g
*gphy
= phy
->g
;
1841 u16 backup_phy
[16] = { 0 };
1842 u16 backup_radio
[3];
1844 u16 i
, j
, loop_i_max
;
1846 u16 loop1_outer_done
, loop1_inner_done
;
1848 backup_phy
[0] = b43_phy_read(dev
, B43_PHY_CRS0
);
1849 backup_phy
[1] = b43_phy_read(dev
, B43_PHY_CCKBBANDCFG
);
1850 backup_phy
[2] = b43_phy_read(dev
, B43_PHY_RFOVER
);
1851 backup_phy
[3] = b43_phy_read(dev
, B43_PHY_RFOVERVAL
);
1852 if (phy
->rev
!= 1) { /* Not in specs, but needed to prevent PPC machine check */
1853 backup_phy
[4] = b43_phy_read(dev
, B43_PHY_ANALOGOVER
);
1854 backup_phy
[5] = b43_phy_read(dev
, B43_PHY_ANALOGOVERVAL
);
1856 backup_phy
[6] = b43_phy_read(dev
, B43_PHY_CCK(0x5A));
1857 backup_phy
[7] = b43_phy_read(dev
, B43_PHY_CCK(0x59));
1858 backup_phy
[8] = b43_phy_read(dev
, B43_PHY_CCK(0x58));
1859 backup_phy
[9] = b43_phy_read(dev
, B43_PHY_CCK(0x0A));
1860 backup_phy
[10] = b43_phy_read(dev
, B43_PHY_CCK(0x03));
1861 backup_phy
[11] = b43_phy_read(dev
, B43_PHY_LO_MASK
);
1862 backup_phy
[12] = b43_phy_read(dev
, B43_PHY_LO_CTL
);
1863 backup_phy
[13] = b43_phy_read(dev
, B43_PHY_CCK(0x2B));
1864 backup_phy
[14] = b43_phy_read(dev
, B43_PHY_PGACTL
);
1865 backup_phy
[15] = b43_phy_read(dev
, B43_PHY_LO_LEAKAGE
);
1866 backup_bband
= gphy
->bbatt
.att
;
1867 backup_radio
[0] = b43_radio_read16(dev
, 0x52);
1868 backup_radio
[1] = b43_radio_read16(dev
, 0x43);
1869 backup_radio
[2] = b43_radio_read16(dev
, 0x7A);
1871 b43_phy_write(dev
, B43_PHY_CRS0
,
1872 b43_phy_read(dev
, B43_PHY_CRS0
) & 0x3FFF);
1873 b43_phy_write(dev
, B43_PHY_CCKBBANDCFG
,
1874 b43_phy_read(dev
, B43_PHY_CCKBBANDCFG
) | 0x8000);
1875 b43_phy_write(dev
, B43_PHY_RFOVER
,
1876 b43_phy_read(dev
, B43_PHY_RFOVER
) | 0x0002);
1877 b43_phy_write(dev
, B43_PHY_RFOVERVAL
,
1878 b43_phy_read(dev
, B43_PHY_RFOVERVAL
) & 0xFFFD);
1879 b43_phy_write(dev
, B43_PHY_RFOVER
,
1880 b43_phy_read(dev
, B43_PHY_RFOVER
) | 0x0001);
1881 b43_phy_write(dev
, B43_PHY_RFOVERVAL
,
1882 b43_phy_read(dev
, B43_PHY_RFOVERVAL
) & 0xFFFE);
1883 if (phy
->rev
!= 1) { /* Not in specs, but needed to prevent PPC machine check */
1884 b43_phy_write(dev
, B43_PHY_ANALOGOVER
,
1885 b43_phy_read(dev
, B43_PHY_ANALOGOVER
) | 0x0001);
1886 b43_phy_write(dev
, B43_PHY_ANALOGOVERVAL
,
1888 B43_PHY_ANALOGOVERVAL
) & 0xFFFE);
1889 b43_phy_write(dev
, B43_PHY_ANALOGOVER
,
1890 b43_phy_read(dev
, B43_PHY_ANALOGOVER
) | 0x0002);
1891 b43_phy_write(dev
, B43_PHY_ANALOGOVERVAL
,
1893 B43_PHY_ANALOGOVERVAL
) & 0xFFFD);
1895 b43_phy_write(dev
, B43_PHY_RFOVER
,
1896 b43_phy_read(dev
, B43_PHY_RFOVER
) | 0x000C);
1897 b43_phy_write(dev
, B43_PHY_RFOVERVAL
,
1898 b43_phy_read(dev
, B43_PHY_RFOVERVAL
) | 0x000C);
1899 b43_phy_write(dev
, B43_PHY_RFOVER
,
1900 b43_phy_read(dev
, B43_PHY_RFOVER
) | 0x0030);
1901 b43_phy_write(dev
, B43_PHY_RFOVERVAL
,
1902 (b43_phy_read(dev
, B43_PHY_RFOVERVAL
)
1905 b43_phy_write(dev
, B43_PHY_CCK(0x5A), 0x0780);
1906 b43_phy_write(dev
, B43_PHY_CCK(0x59), 0xC810);
1907 b43_phy_write(dev
, B43_PHY_CCK(0x58), 0x000D);
1909 b43_phy_write(dev
, B43_PHY_CCK(0x0A),
1910 b43_phy_read(dev
, B43_PHY_CCK(0x0A)) | 0x2000);
1911 if (phy
->rev
!= 1) { /* Not in specs, but needed to prevent PPC machine check */
1912 b43_phy_write(dev
, B43_PHY_ANALOGOVER
,
1913 b43_phy_read(dev
, B43_PHY_ANALOGOVER
) | 0x0004);
1914 b43_phy_write(dev
, B43_PHY_ANALOGOVERVAL
,
1916 B43_PHY_ANALOGOVERVAL
) & 0xFFFB);
1918 b43_phy_write(dev
, B43_PHY_CCK(0x03),
1919 (b43_phy_read(dev
, B43_PHY_CCK(0x03))
1922 if (phy
->radio_rev
== 8) {
1923 b43_radio_write16(dev
, 0x43, 0x000F);
1925 b43_radio_write16(dev
, 0x52, 0);
1926 b43_radio_write16(dev
, 0x43, (b43_radio_read16(dev
, 0x43)
1929 b43_gphy_set_baseband_attenuation(dev
, 11);
1932 b43_phy_write(dev
, B43_PHY_LO_MASK
, 0xC020);
1934 b43_phy_write(dev
, B43_PHY_LO_MASK
, 0x8020);
1935 b43_phy_write(dev
, B43_PHY_LO_CTL
, 0);
1937 b43_phy_write(dev
, B43_PHY_CCK(0x2B),
1938 (b43_phy_read(dev
, B43_PHY_CCK(0x2B))
1940 b43_phy_write(dev
, B43_PHY_CCK(0x2B),
1941 (b43_phy_read(dev
, B43_PHY_CCK(0x2B))
1944 b43_phy_write(dev
, B43_PHY_RFOVER
,
1945 b43_phy_read(dev
, B43_PHY_RFOVER
) | 0x0100);
1946 b43_phy_write(dev
, B43_PHY_RFOVERVAL
,
1947 b43_phy_read(dev
, B43_PHY_RFOVERVAL
) & 0xCFFF);
1949 if (dev
->dev
->bus
->sprom
.boardflags_lo
& B43_BFL_EXTLNA
) {
1950 if (phy
->rev
>= 7) {
1951 b43_phy_write(dev
, B43_PHY_RFOVER
,
1952 b43_phy_read(dev
, B43_PHY_RFOVER
)
1954 b43_phy_write(dev
, B43_PHY_RFOVERVAL
,
1955 b43_phy_read(dev
, B43_PHY_RFOVERVAL
)
1959 b43_radio_write16(dev
, 0x7A, b43_radio_read16(dev
, 0x7A)
1963 loop_i_max
= (phy
->radio_rev
== 8) ? 15 : 9;
1964 for (i
= 0; i
< loop_i_max
; i
++) {
1965 for (j
= 0; j
< 16; j
++) {
1966 b43_radio_write16(dev
, 0x43, i
);
1967 b43_phy_write(dev
, B43_PHY_RFOVERVAL
,
1968 (b43_phy_read(dev
, B43_PHY_RFOVERVAL
)
1969 & 0xF0FF) | (j
<< 8));
1970 b43_phy_write(dev
, B43_PHY_PGACTL
,
1971 (b43_phy_read(dev
, B43_PHY_PGACTL
)
1972 & 0x0FFF) | 0xA000);
1973 b43_phy_write(dev
, B43_PHY_PGACTL
,
1974 b43_phy_read(dev
, B43_PHY_PGACTL
)
1977 if (b43_phy_read(dev
, B43_PHY_LO_LEAKAGE
) >= 0xDFC)
1982 loop1_outer_done
= i
;
1983 loop1_inner_done
= j
;
1985 b43_phy_write(dev
, B43_PHY_RFOVERVAL
,
1986 b43_phy_read(dev
, B43_PHY_RFOVERVAL
)
1989 for (j
= j
- 8; j
< 16; j
++) {
1990 b43_phy_write(dev
, B43_PHY_RFOVERVAL
,
1991 (b43_phy_read(dev
, B43_PHY_RFOVERVAL
)
1992 & 0xF0FF) | (j
<< 8));
1993 b43_phy_write(dev
, B43_PHY_PGACTL
,
1994 (b43_phy_read(dev
, B43_PHY_PGACTL
)
1995 & 0x0FFF) | 0xA000);
1996 b43_phy_write(dev
, B43_PHY_PGACTL
,
1997 b43_phy_read(dev
, B43_PHY_PGACTL
)
2001 if (b43_phy_read(dev
, B43_PHY_LO_LEAKAGE
) >= 0xDFC)
2008 if (phy
->rev
!= 1) { /* Not in specs, but needed to prevent PPC machine check */
2009 b43_phy_write(dev
, B43_PHY_ANALOGOVER
, backup_phy
[4]);
2010 b43_phy_write(dev
, B43_PHY_ANALOGOVERVAL
, backup_phy
[5]);
2012 b43_phy_write(dev
, B43_PHY_CCK(0x5A), backup_phy
[6]);
2013 b43_phy_write(dev
, B43_PHY_CCK(0x59), backup_phy
[7]);
2014 b43_phy_write(dev
, B43_PHY_CCK(0x58), backup_phy
[8]);
2015 b43_phy_write(dev
, B43_PHY_CCK(0x0A), backup_phy
[9]);
2016 b43_phy_write(dev
, B43_PHY_CCK(0x03), backup_phy
[10]);
2017 b43_phy_write(dev
, B43_PHY_LO_MASK
, backup_phy
[11]);
2018 b43_phy_write(dev
, B43_PHY_LO_CTL
, backup_phy
[12]);
2019 b43_phy_write(dev
, B43_PHY_CCK(0x2B), backup_phy
[13]);
2020 b43_phy_write(dev
, B43_PHY_PGACTL
, backup_phy
[14]);
2022 b43_gphy_set_baseband_attenuation(dev
, backup_bband
);
2024 b43_radio_write16(dev
, 0x52, backup_radio
[0]);
2025 b43_radio_write16(dev
, 0x43, backup_radio
[1]);
2026 b43_radio_write16(dev
, 0x7A, backup_radio
[2]);
2028 b43_phy_write(dev
, B43_PHY_RFOVER
, backup_phy
[2] | 0x0003);
2030 b43_phy_write(dev
, B43_PHY_RFOVER
, backup_phy
[2]);
2031 b43_phy_write(dev
, B43_PHY_RFOVERVAL
, backup_phy
[3]);
2032 b43_phy_write(dev
, B43_PHY_CRS0
, backup_phy
[0]);
2033 b43_phy_write(dev
, B43_PHY_CCKBBANDCFG
, backup_phy
[1]);
2036 ((loop1_inner_done
* 6) - (loop1_outer_done
* 4)) - 11;
2037 gphy
->trsw_rx_gain
= trsw_rx
* 2;
2040 static void b43_hardware_pctl_early_init(struct b43_wldev
*dev
)
2042 struct b43_phy
*phy
= &dev
->phy
;
2044 if (!b43_has_hardware_pctl(dev
)) {
2045 b43_phy_write(dev
, 0x047A, 0xC111);
2049 b43_phy_write(dev
, 0x0036, b43_phy_read(dev
, 0x0036) & 0xFEFF);
2050 b43_phy_write(dev
, 0x002F, 0x0202);
2051 b43_phy_write(dev
, 0x047C, b43_phy_read(dev
, 0x047C) | 0x0002);
2052 b43_phy_write(dev
, 0x047A, b43_phy_read(dev
, 0x047A) | 0xF000);
2053 if (phy
->radio_ver
== 0x2050 && phy
->radio_rev
== 8) {
2054 b43_phy_write(dev
, 0x047A, (b43_phy_read(dev
, 0x047A)
2055 & 0xFF0F) | 0x0010);
2056 b43_phy_write(dev
, 0x005D, b43_phy_read(dev
, 0x005D)
2058 b43_phy_write(dev
, 0x004E, (b43_phy_read(dev
, 0x004E)
2059 & 0xFFC0) | 0x0010);
2060 b43_phy_write(dev
, 0x002E, 0xC07F);
2061 b43_phy_write(dev
, 0x0036, b43_phy_read(dev
, 0x0036)
2064 b43_phy_write(dev
, 0x0036, b43_phy_read(dev
, 0x0036)
2066 b43_phy_write(dev
, 0x0036, b43_phy_read(dev
, 0x0036)
2068 b43_phy_write(dev
, 0x005D, b43_phy_read(dev
, 0x005D)
2070 b43_phy_write(dev
, 0x004F, b43_phy_read(dev
, 0x004F)
2072 b43_phy_write(dev
, 0x004E, (b43_phy_read(dev
, 0x004E)
2073 & 0xFFC0) | 0x0010);
2074 b43_phy_write(dev
, 0x002E, 0xC07F);
2075 b43_phy_write(dev
, 0x047A, (b43_phy_read(dev
, 0x047A)
2076 & 0xFF0F) | 0x0010);
2080 /* Hardware power control for G-PHY */
2081 static void b43_hardware_pctl_init_gphy(struct b43_wldev
*dev
)
2083 struct b43_phy
*phy
= &dev
->phy
;
2084 struct b43_phy_g
*gphy
= phy
->g
;
2086 if (!b43_has_hardware_pctl(dev
)) {
2087 /* No hardware power control */
2088 b43_hf_write(dev
, b43_hf_read(dev
) & ~B43_HF_HWPCTL
);
2092 b43_phy_write(dev
, 0x0036, (b43_phy_read(dev
, 0x0036) & 0xFFC0)
2093 | (gphy
->tgt_idle_tssi
- gphy
->cur_idle_tssi
));
2094 b43_phy_write(dev
, 0x0478, (b43_phy_read(dev
, 0x0478) & 0xFF00)
2095 | (gphy
->tgt_idle_tssi
- gphy
->cur_idle_tssi
));
2096 b43_gphy_tssi_power_lt_init(dev
);
2097 b43_gphy_gain_lt_init(dev
);
2098 b43_phy_write(dev
, 0x0060, b43_phy_read(dev
, 0x0060) & 0xFFBF);
2099 b43_phy_write(dev
, 0x0014, 0x0000);
2101 B43_WARN_ON(phy
->rev
< 6);
2102 b43_phy_write(dev
, 0x0478, b43_phy_read(dev
, 0x0478)
2104 b43_phy_write(dev
, 0x0478, b43_phy_read(dev
, 0x0478)
2106 b43_phy_write(dev
, 0x0801, b43_phy_read(dev
, 0x0801)
2109 b43_gphy_dc_lt_init(dev
, 1);
2111 /* Enable hardware pctl in firmware. */
2112 b43_hf_write(dev
, b43_hf_read(dev
) | B43_HF_HWPCTL
);
2115 /* Intialize B/G PHY power control */
2116 static void b43_phy_init_pctl(struct b43_wldev
*dev
)
2118 struct ssb_bus
*bus
= dev
->dev
->bus
;
2119 struct b43_phy
*phy
= &dev
->phy
;
2120 struct b43_phy_g
*gphy
= phy
->g
;
2121 struct b43_rfatt old_rfatt
;
2122 struct b43_bbatt old_bbatt
;
2123 u8 old_tx_control
= 0;
2125 B43_WARN_ON(phy
->type
!= B43_PHYTYPE_G
);
2127 if ((bus
->boardinfo
.vendor
== SSB_BOARDVENDOR_BCM
) &&
2128 (bus
->boardinfo
.type
== SSB_BOARD_BU4306
))
2131 b43_phy_write(dev
, 0x0028, 0x8018);
2133 /* This does something with the Analog... */
2134 b43_write16(dev
, B43_MMIO_PHY0
, b43_read16(dev
, B43_MMIO_PHY0
)
2139 b43_hardware_pctl_early_init(dev
);
2140 if (gphy
->cur_idle_tssi
== 0) {
2141 if (phy
->radio_ver
== 0x2050 && phy
->analog
== 0) {
2142 b43_radio_write16(dev
, 0x0076,
2143 (b43_radio_read16(dev
, 0x0076)
2144 & 0x00F7) | 0x0084);
2146 struct b43_rfatt rfatt
;
2147 struct b43_bbatt bbatt
;
2149 memcpy(&old_rfatt
, &gphy
->rfatt
, sizeof(old_rfatt
));
2150 memcpy(&old_bbatt
, &gphy
->bbatt
, sizeof(old_bbatt
));
2151 old_tx_control
= gphy
->tx_control
;
2154 if (phy
->radio_rev
== 8) {
2156 rfatt
.with_padmix
= 1;
2159 rfatt
.with_padmix
= 0;
2161 b43_set_txpower_g(dev
, &bbatt
, &rfatt
, 0);
2163 b43_dummy_transmission(dev
);
2164 gphy
->cur_idle_tssi
= b43_phy_read(dev
, B43_PHY_ITSSI
);
2166 /* Current-Idle-TSSI sanity check. */
2167 if (abs(gphy
->cur_idle_tssi
- gphy
->tgt_idle_tssi
) >= 20) {
2169 "!WARNING! Idle-TSSI phy->cur_idle_tssi "
2170 "measuring failed. (cur=%d, tgt=%d). Disabling TX power "
2171 "adjustment.\n", gphy
->cur_idle_tssi
,
2172 gphy
->tgt_idle_tssi
);
2173 gphy
->cur_idle_tssi
= 0;
2176 if (phy
->radio_ver
== 0x2050 && phy
->analog
== 0) {
2177 b43_radio_write16(dev
, 0x0076,
2178 b43_radio_read16(dev
, 0x0076)
2181 b43_set_txpower_g(dev
, &old_bbatt
,
2182 &old_rfatt
, old_tx_control
);
2185 b43_hardware_pctl_init_gphy(dev
);
2186 b43_shm_clear_tssi(dev
);
2189 static void b43_phy_initg(struct b43_wldev
*dev
)
2191 struct b43_phy
*phy
= &dev
->phy
;
2192 struct b43_phy_g
*gphy
= phy
->g
;
2196 b43_phy_initb5(dev
);
2198 b43_phy_initb6(dev
);
2200 if (phy
->rev
>= 2 || phy
->gmode
)
2203 if (phy
->rev
>= 2) {
2204 b43_phy_write(dev
, B43_PHY_ANALOGOVER
, 0);
2205 b43_phy_write(dev
, B43_PHY_ANALOGOVERVAL
, 0);
2207 if (phy
->rev
== 2) {
2208 b43_phy_write(dev
, B43_PHY_RFOVER
, 0);
2209 b43_phy_write(dev
, B43_PHY_PGACTL
, 0xC0);
2212 b43_phy_write(dev
, B43_PHY_RFOVER
, 0x400);
2213 b43_phy_write(dev
, B43_PHY_PGACTL
, 0xC0);
2215 if (phy
->gmode
|| phy
->rev
>= 2) {
2216 tmp
= b43_phy_read(dev
, B43_PHY_VERSION_OFDM
);
2217 tmp
&= B43_PHYVER_VERSION
;
2218 if (tmp
== 3 || tmp
== 5) {
2219 b43_phy_write(dev
, B43_PHY_OFDM(0xC2), 0x1816);
2220 b43_phy_write(dev
, B43_PHY_OFDM(0xC3), 0x8006);
2223 b43_phy_write(dev
, B43_PHY_OFDM(0xCC),
2224 (b43_phy_read(dev
, B43_PHY_OFDM(0xCC))
2225 & 0x00FF) | 0x1F00);
2228 if ((phy
->rev
<= 2 && phy
->gmode
) || phy
->rev
>= 2)
2229 b43_phy_write(dev
, B43_PHY_OFDM(0x7E), 0x78);
2230 if (phy
->radio_rev
== 8) {
2231 b43_phy_write(dev
, B43_PHY_EXTG(0x01),
2232 b43_phy_read(dev
, B43_PHY_EXTG(0x01))
2234 b43_phy_write(dev
, B43_PHY_OFDM(0x3E),
2235 b43_phy_read(dev
, B43_PHY_OFDM(0x3E))
2238 if (has_loopback_gain(phy
))
2239 b43_calc_loopback_gain(dev
);
2241 if (phy
->radio_rev
!= 8) {
2242 if (gphy
->initval
== 0xFFFF)
2243 gphy
->initval
= b43_radio_init2050(dev
);
2245 b43_radio_write16(dev
, 0x0078, gphy
->initval
);
2248 if (has_tx_magnification(phy
)) {
2249 b43_radio_write16(dev
, 0x52,
2250 (b43_radio_read16(dev
, 0x52) & 0xFF00)
2251 | gphy
->lo_control
->tx_bias
| gphy
->
2252 lo_control
->tx_magn
);
2254 b43_radio_write16(dev
, 0x52,
2255 (b43_radio_read16(dev
, 0x52) & 0xFFF0)
2256 | gphy
->lo_control
->tx_bias
);
2258 if (phy
->rev
>= 6) {
2259 b43_phy_write(dev
, B43_PHY_CCK(0x36),
2260 (b43_phy_read(dev
, B43_PHY_CCK(0x36))
2261 & 0x0FFF) | (gphy
->lo_control
->
2264 if (dev
->dev
->bus
->sprom
.boardflags_lo
& B43_BFL_PACTRL
)
2265 b43_phy_write(dev
, B43_PHY_CCK(0x2E), 0x8075);
2267 b43_phy_write(dev
, B43_PHY_CCK(0x2E), 0x807F);
2269 b43_phy_write(dev
, B43_PHY_CCK(0x2F), 0x101);
2271 b43_phy_write(dev
, B43_PHY_CCK(0x2F), 0x202);
2272 if (phy
->gmode
|| phy
->rev
>= 2) {
2273 b43_lo_g_adjust(dev
);
2274 b43_phy_write(dev
, B43_PHY_LO_MASK
, 0x8078);
2277 if (!(dev
->dev
->bus
->sprom
.boardflags_lo
& B43_BFL_RSSI
)) {
2278 /* The specs state to update the NRSSI LT with
2279 * the value 0x7FFFFFFF here. I think that is some weird
2280 * compiler optimization in the original driver.
2281 * Essentially, what we do here is resetting all NRSSI LT
2282 * entries to -32 (see the clamp_val() in nrssi_hw_update())
2284 b43_nrssi_hw_update(dev
, 0xFFFF); //FIXME?
2285 b43_calc_nrssi_threshold(dev
);
2286 } else if (phy
->gmode
|| phy
->rev
>= 2) {
2287 if (gphy
->nrssi
[0] == -1000) {
2288 B43_WARN_ON(gphy
->nrssi
[1] != -1000);
2289 b43_calc_nrssi_slope(dev
);
2291 b43_calc_nrssi_threshold(dev
);
2293 if (phy
->radio_rev
== 8)
2294 b43_phy_write(dev
, B43_PHY_EXTG(0x05), 0x3230);
2295 b43_phy_init_pctl(dev
);
2296 /* FIXME: The spec says in the following if, the 0 should be replaced
2297 'if OFDM may not be used in the current locale'
2298 but OFDM is legal everywhere */
2299 if ((dev
->dev
->bus
->chip_id
== 0x4306
2300 && dev
->dev
->bus
->chip_package
== 2) || 0) {
2301 b43_phy_write(dev
, B43_PHY_CRS0
, b43_phy_read(dev
, B43_PHY_CRS0
)
2303 b43_phy_write(dev
, B43_PHY_OFDM(0xC3),
2304 b43_phy_read(dev
, B43_PHY_OFDM(0xC3))
2309 void b43_gphy_channel_switch(struct b43_wldev
*dev
,
2310 unsigned int channel
,
2311 bool synthetic_pu_workaround
)
2313 if (synthetic_pu_workaround
)
2314 b43_synth_pu_workaround(dev
, channel
);
2316 b43_write16(dev
, B43_MMIO_CHANNEL
, channel2freq_bg(channel
));
2318 if (channel
== 14) {
2319 if (dev
->dev
->bus
->sprom
.country_code
==
2320 SSB_SPROM1CCODE_JAPAN
)
2322 b43_hf_read(dev
) & ~B43_HF_ACPR
);
2325 b43_hf_read(dev
) | B43_HF_ACPR
);
2326 b43_write16(dev
, B43_MMIO_CHANNEL_EXT
,
2327 b43_read16(dev
, B43_MMIO_CHANNEL_EXT
)
2330 b43_write16(dev
, B43_MMIO_CHANNEL_EXT
,
2331 b43_read16(dev
, B43_MMIO_CHANNEL_EXT
)
2336 static void default_baseband_attenuation(struct b43_wldev
*dev
,
2337 struct b43_bbatt
*bb
)
2339 struct b43_phy
*phy
= &dev
->phy
;
2341 if (phy
->radio_ver
== 0x2050 && phy
->radio_rev
< 6)
2347 static void default_radio_attenuation(struct b43_wldev
*dev
,
2348 struct b43_rfatt
*rf
)
2350 struct ssb_bus
*bus
= dev
->dev
->bus
;
2351 struct b43_phy
*phy
= &dev
->phy
;
2353 rf
->with_padmix
= 0;
2355 if (bus
->boardinfo
.vendor
== SSB_BOARDVENDOR_BCM
&&
2356 bus
->boardinfo
.type
== SSB_BOARD_BCM4309G
) {
2357 if (bus
->boardinfo
.rev
< 0x43) {
2360 } else if (bus
->boardinfo
.rev
< 0x51) {
2366 if (phy
->type
== B43_PHYTYPE_A
) {
2371 switch (phy
->radio_ver
) {
2373 switch (phy
->radio_rev
) {
2380 switch (phy
->radio_rev
) {
2385 if (phy
->type
== B43_PHYTYPE_G
) {
2386 if (bus
->boardinfo
.vendor
== SSB_BOARDVENDOR_BCM
2387 && bus
->boardinfo
.type
== SSB_BOARD_BCM4309G
2388 && bus
->boardinfo
.rev
>= 30)
2390 else if (bus
->boardinfo
.vendor
==
2392 && bus
->boardinfo
.type
==
2398 if (bus
->boardinfo
.vendor
== SSB_BOARDVENDOR_BCM
2399 && bus
->boardinfo
.type
== SSB_BOARD_BCM4309G
2400 && bus
->boardinfo
.rev
>= 30)
2407 if (phy
->type
== B43_PHYTYPE_G
) {
2408 if (bus
->boardinfo
.vendor
== SSB_BOARDVENDOR_BCM
2409 && bus
->boardinfo
.type
== SSB_BOARD_BCM4309G
2410 && bus
->boardinfo
.rev
>= 30)
2412 else if (bus
->boardinfo
.vendor
==
2414 && bus
->boardinfo
.type
==
2417 else if (bus
->chip_id
== 0x4320)
2437 rf
->with_padmix
= 1;
2448 static u16
default_tx_control(struct b43_wldev
*dev
)
2450 struct b43_phy
*phy
= &dev
->phy
;
2452 if (phy
->radio_ver
!= 0x2050)
2454 if (phy
->radio_rev
== 1)
2455 return B43_TXCTL_PA2DB
| B43_TXCTL_TXMIX
;
2456 if (phy
->radio_rev
< 6)
2457 return B43_TXCTL_PA2DB
;
2458 if (phy
->radio_rev
== 8)
2459 return B43_TXCTL_TXMIX
;
2463 static u8
b43_gphy_aci_detect(struct b43_wldev
*dev
, u8 channel
)
2465 struct b43_phy
*phy
= &dev
->phy
;
2466 struct b43_phy_g
*gphy
= phy
->g
;
2468 u16 saved
, rssi
, temp
;
2471 saved
= b43_phy_read(dev
, 0x0403);
2472 b43_switch_channel(dev
, channel
);
2473 b43_phy_write(dev
, 0x0403, (saved
& 0xFFF8) | 5);
2474 if (gphy
->aci_hw_rssi
)
2475 rssi
= b43_phy_read(dev
, 0x048A) & 0x3F;
2477 rssi
= saved
& 0x3F;
2478 /* clamp temp to signed 5bit */
2481 for (i
= 0; i
< 100; i
++) {
2482 temp
= (b43_phy_read(dev
, 0x047F) >> 8) & 0x3F;
2490 b43_phy_write(dev
, 0x0403, saved
);
2495 static u8
b43_gphy_aci_scan(struct b43_wldev
*dev
)
2497 struct b43_phy
*phy
= &dev
->phy
;
2499 unsigned int channel
= phy
->channel
;
2500 unsigned int i
, j
, start
, end
;
2502 if (!((phy
->type
== B43_PHYTYPE_G
) && (phy
->rev
> 0)))
2506 b43_radio_lock(dev
);
2507 b43_phy_write(dev
, 0x0802, b43_phy_read(dev
, 0x0802) & 0xFFFC);
2508 b43_phy_write(dev
, B43_PHY_G_CRS
,
2509 b43_phy_read(dev
, B43_PHY_G_CRS
) & 0x7FFF);
2510 b43_set_all_gains(dev
, 3, 8, 1);
2512 start
= (channel
- 5 > 0) ? channel
- 5 : 1;
2513 end
= (channel
+ 5 < 14) ? channel
+ 5 : 13;
2515 for (i
= start
; i
<= end
; i
++) {
2516 if (abs(channel
- i
) > 2)
2517 ret
[i
- 1] = b43_gphy_aci_detect(dev
, i
);
2519 b43_switch_channel(dev
, channel
);
2520 b43_phy_write(dev
, 0x0802,
2521 (b43_phy_read(dev
, 0x0802) & 0xFFFC) | 0x0003);
2522 b43_phy_write(dev
, 0x0403, b43_phy_read(dev
, 0x0403) & 0xFFF8);
2523 b43_phy_write(dev
, B43_PHY_G_CRS
,
2524 b43_phy_read(dev
, B43_PHY_G_CRS
) | 0x8000);
2525 b43_set_original_gains(dev
);
2526 for (i
= 0; i
< 13; i
++) {
2529 end
= (i
+ 5 < 13) ? i
+ 5 : 13;
2530 for (j
= i
; j
< end
; j
++)
2533 b43_radio_unlock(dev
);
2534 b43_phy_unlock(dev
);
2536 return ret
[channel
- 1];
2539 static s32
b43_tssi2dbm_ad(s32 num
, s32 den
)
2544 return (num
+ den
/ 2) / den
;
2547 static s8
b43_tssi2dbm_entry(s8 entry
[], u8 index
,
2548 s16 pab0
, s16 pab1
, s16 pab2
)
2550 s32 m1
, m2
, f
= 256, q
, delta
;
2553 m1
= b43_tssi2dbm_ad(16 * pab0
+ index
* pab1
, 32);
2554 m2
= max(b43_tssi2dbm_ad(32768 + index
* pab2
, 256), 1);
2558 q
= b43_tssi2dbm_ad(f
* 4096 -
2559 b43_tssi2dbm_ad(m2
* f
, 16) * f
, 2048);
2563 } while (delta
>= 2);
2564 entry
[index
] = clamp_val(b43_tssi2dbm_ad(m1
* f
, 8192), -127, 128);
2568 u8
* b43_generate_dyn_tssi2dbm_tab(struct b43_wldev
*dev
,
2569 s16 pab0
, s16 pab1
, s16 pab2
)
2575 tab
= kmalloc(64, GFP_KERNEL
);
2577 b43err(dev
->wl
, "Could not allocate memory "
2578 "for tssi2dbm table\n");
2581 for (i
= 0; i
< 64; i
++) {
2582 err
= b43_tssi2dbm_entry(tab
, i
, pab0
, pab1
, pab2
);
2584 b43err(dev
->wl
, "Could not generate "
2585 "tssi2dBm table\n");
2594 /* Initialise the TSSI->dBm lookup table */
2595 static int b43_gphy_init_tssi2dbm_table(struct b43_wldev
*dev
)
2597 struct b43_phy
*phy
= &dev
->phy
;
2598 struct b43_phy_g
*gphy
= phy
->g
;
2599 s16 pab0
, pab1
, pab2
;
2601 pab0
= (s16
) (dev
->dev
->bus
->sprom
.pa0b0
);
2602 pab1
= (s16
) (dev
->dev
->bus
->sprom
.pa0b1
);
2603 pab2
= (s16
) (dev
->dev
->bus
->sprom
.pa0b2
);
2605 B43_WARN_ON((dev
->dev
->bus
->chip_id
== 0x4301) &&
2606 (phy
->radio_ver
!= 0x2050)); /* Not supported anymore */
2608 gphy
->dyn_tssi_tbl
= 0;
2610 if (pab0
!= 0 && pab1
!= 0 && pab2
!= 0 &&
2611 pab0
!= -1 && pab1
!= -1 && pab2
!= -1) {
2612 /* The pabX values are set in SPROM. Use them. */
2613 if ((s8
) dev
->dev
->bus
->sprom
.itssi_bg
!= 0 &&
2614 (s8
) dev
->dev
->bus
->sprom
.itssi_bg
!= -1) {
2615 gphy
->tgt_idle_tssi
=
2616 (s8
) (dev
->dev
->bus
->sprom
.itssi_bg
);
2618 gphy
->tgt_idle_tssi
= 62;
2619 gphy
->tssi2dbm
= b43_generate_dyn_tssi2dbm_tab(dev
, pab0
,
2621 if (!gphy
->tssi2dbm
)
2623 gphy
->dyn_tssi_tbl
= 1;
2625 /* pabX values not set in SPROM. */
2626 gphy
->tgt_idle_tssi
= 52;
2627 gphy
->tssi2dbm
= b43_tssi2dbm_g_table
;
2633 static int b43_gphy_op_allocate(struct b43_wldev
*dev
)
2635 struct b43_phy_g
*gphy
;
2636 struct b43_txpower_lo_control
*lo
;
2639 gphy
= kzalloc(sizeof(*gphy
), GFP_KERNEL
);
2646 lo
= kzalloc(sizeof(*lo
), GFP_KERNEL
);
2651 gphy
->lo_control
= lo
;
2653 err
= b43_gphy_init_tssi2dbm_table(dev
);
2667 static void b43_gphy_op_prepare_structs(struct b43_wldev
*dev
)
2669 struct b43_phy
*phy
= &dev
->phy
;
2670 struct b43_phy_g
*gphy
= phy
->g
;
2671 const void *tssi2dbm
;
2673 struct b43_txpower_lo_control
*lo
;
2676 /* tssi2dbm table is constant, so it is initialized at alloc time.
2677 * Save a copy of the pointer. */
2678 tssi2dbm
= gphy
->tssi2dbm
;
2679 tgt_idle_tssi
= gphy
->tgt_idle_tssi
;
2680 /* Save the LO pointer. */
2681 lo
= gphy
->lo_control
;
2683 /* Zero out the whole PHY structure. */
2684 memset(gphy
, 0, sizeof(*gphy
));
2686 /* Restore pointers. */
2687 gphy
->tssi2dbm
= tssi2dbm
;
2688 gphy
->tgt_idle_tssi
= tgt_idle_tssi
;
2689 gphy
->lo_control
= lo
;
2691 memset(gphy
->minlowsig
, 0xFF, sizeof(gphy
->minlowsig
));
2694 for (i
= 0; i
< ARRAY_SIZE(gphy
->nrssi
); i
++)
2695 gphy
->nrssi
[i
] = -1000;
2696 for (i
= 0; i
< ARRAY_SIZE(gphy
->nrssi_lt
); i
++)
2697 gphy
->nrssi_lt
[i
] = i
;
2699 gphy
->lofcal
= 0xFFFF;
2700 gphy
->initval
= 0xFFFF;
2702 gphy
->interfmode
= B43_INTERFMODE_NONE
;
2704 /* OFDM-table address caching. */
2705 gphy
->ofdmtab_addr_direction
= B43_OFDMTAB_DIRECTION_UNKNOWN
;
2707 gphy
->average_tssi
= 0xFF;
2709 /* Local Osciallator structure */
2711 INIT_LIST_HEAD(&lo
->calib_list
);
2714 static void b43_gphy_op_free(struct b43_wldev
*dev
)
2716 struct b43_phy
*phy
= &dev
->phy
;
2717 struct b43_phy_g
*gphy
= phy
->g
;
2719 kfree(gphy
->lo_control
);
2721 if (gphy
->dyn_tssi_tbl
)
2722 kfree(gphy
->tssi2dbm
);
2723 gphy
->dyn_tssi_tbl
= 0;
2724 gphy
->tssi2dbm
= NULL
;
2730 static int b43_gphy_op_prepare_hardware(struct b43_wldev
*dev
)
2732 struct b43_phy
*phy
= &dev
->phy
;
2733 struct b43_phy_g
*gphy
= phy
->g
;
2734 struct b43_txpower_lo_control
*lo
= gphy
->lo_control
;
2736 B43_WARN_ON(phy
->type
!= B43_PHYTYPE_G
);
2738 default_baseband_attenuation(dev
, &gphy
->bbatt
);
2739 default_radio_attenuation(dev
, &gphy
->rfatt
);
2740 gphy
->tx_control
= (default_tx_control(dev
) << 4);
2741 generate_rfatt_list(dev
, &lo
->rfatt_list
);
2742 generate_bbatt_list(dev
, &lo
->bbatt_list
);
2744 /* Commit previous writes */
2745 b43_read32(dev
, B43_MMIO_MACCTL
);
2747 if (phy
->rev
== 1) {
2748 /* Workaround: Temporarly disable gmode through the early init
2749 * phase, as the gmode stuff is not needed for phy rev 1 */
2751 b43_wireless_core_reset(dev
, 0);
2754 b43_wireless_core_reset(dev
, B43_TMSLOW_GMODE
);
2760 static int b43_gphy_op_init(struct b43_wldev
*dev
)
2767 static void b43_gphy_op_exit(struct b43_wldev
*dev
)
2769 b43_lo_g_cleanup(dev
);
2772 static u16
b43_gphy_op_read(struct b43_wldev
*dev
, u16 reg
)
2774 b43_write16(dev
, B43_MMIO_PHY_CONTROL
, reg
);
2775 return b43_read16(dev
, B43_MMIO_PHY_DATA
);
2778 static void b43_gphy_op_write(struct b43_wldev
*dev
, u16 reg
, u16 value
)
2780 b43_write16(dev
, B43_MMIO_PHY_CONTROL
, reg
);
2781 b43_write16(dev
, B43_MMIO_PHY_DATA
, value
);
2784 static u16
b43_gphy_op_radio_read(struct b43_wldev
*dev
, u16 reg
)
2786 /* Register 1 is a 32-bit register. */
2787 B43_WARN_ON(reg
== 1);
2788 /* G-PHY needs 0x80 for read access. */
2791 b43_write16(dev
, B43_MMIO_RADIO_CONTROL
, reg
);
2792 return b43_read16(dev
, B43_MMIO_RADIO_DATA_LOW
);
2795 static void b43_gphy_op_radio_write(struct b43_wldev
*dev
, u16 reg
, u16 value
)
2797 /* Register 1 is a 32-bit register. */
2798 B43_WARN_ON(reg
== 1);
2800 b43_write16(dev
, B43_MMIO_RADIO_CONTROL
, reg
);
2801 b43_write16(dev
, B43_MMIO_RADIO_DATA_LOW
, value
);
2804 static bool b43_gphy_op_supports_hwpctl(struct b43_wldev
*dev
)
2806 return (dev
->phy
.rev
>= 6);
2809 static void b43_gphy_op_software_rfkill(struct b43_wldev
*dev
,
2810 enum rfkill_state state
)
2812 struct b43_phy
*phy
= &dev
->phy
;
2813 struct b43_phy_g
*gphy
= phy
->g
;
2814 unsigned int channel
;
2818 if (state
== RFKILL_STATE_UNBLOCKED
) {
2823 b43_phy_write(dev
, 0x0015, 0x8000);
2824 b43_phy_write(dev
, 0x0015, 0xCC00);
2825 b43_phy_write(dev
, 0x0015, (phy
->gmode
? 0x00C0 : 0x0000));
2826 if (gphy
->radio_off_context
.valid
) {
2827 /* Restore the RFover values. */
2828 b43_phy_write(dev
, B43_PHY_RFOVER
,
2829 gphy
->radio_off_context
.rfover
);
2830 b43_phy_write(dev
, B43_PHY_RFOVERVAL
,
2831 gphy
->radio_off_context
.rfoverval
);
2832 gphy
->radio_off_context
.valid
= 0;
2834 channel
= phy
->channel
;
2835 b43_gphy_channel_switch(dev
, 6, 1);
2836 b43_gphy_channel_switch(dev
, channel
, 0);
2838 /* Turn radio OFF */
2839 u16 rfover
, rfoverval
;
2841 rfover
= b43_phy_read(dev
, B43_PHY_RFOVER
);
2842 rfoverval
= b43_phy_read(dev
, B43_PHY_RFOVERVAL
);
2843 gphy
->radio_off_context
.rfover
= rfover
;
2844 gphy
->radio_off_context
.rfoverval
= rfoverval
;
2845 gphy
->radio_off_context
.valid
= 1;
2846 b43_phy_write(dev
, B43_PHY_RFOVER
, rfover
| 0x008C);
2847 b43_phy_write(dev
, B43_PHY_RFOVERVAL
, rfoverval
& 0xFF73);
2851 static int b43_gphy_op_switch_channel(struct b43_wldev
*dev
,
2852 unsigned int new_channel
)
2854 if ((new_channel
< 1) || (new_channel
> 14))
2856 b43_gphy_channel_switch(dev
, new_channel
, 0);
2861 static unsigned int b43_gphy_op_get_default_chan(struct b43_wldev
*dev
)
2863 return 1; /* Default to channel 1 */
2866 static void b43_gphy_op_set_rx_antenna(struct b43_wldev
*dev
, int antenna
)
2868 struct b43_phy
*phy
= &dev
->phy
;
2873 if (antenna
== B43_ANTENNA_AUTO0
|| antenna
== B43_ANTENNA_AUTO1
)
2876 hf
= b43_hf_read(dev
);
2877 hf
&= ~B43_HF_ANTDIVHELP
;
2878 b43_hf_write(dev
, hf
);
2880 tmp
= b43_phy_read(dev
, B43_PHY_BBANDCFG
);
2881 tmp
&= ~B43_PHY_BBANDCFG_RXANT
;
2882 tmp
|= (autodiv
? B43_ANTENNA_AUTO0
: antenna
)
2883 << B43_PHY_BBANDCFG_RXANT_SHIFT
;
2884 b43_phy_write(dev
, B43_PHY_BBANDCFG
, tmp
);
2887 tmp
= b43_phy_read(dev
, B43_PHY_ANTDWELL
);
2888 if (antenna
== B43_ANTENNA_AUTO0
)
2889 tmp
&= ~B43_PHY_ANTDWELL_AUTODIV1
;
2891 tmp
|= B43_PHY_ANTDWELL_AUTODIV1
;
2892 b43_phy_write(dev
, B43_PHY_ANTDWELL
, tmp
);
2894 tmp
= b43_phy_read(dev
, B43_PHY_ANTWRSETT
);
2896 tmp
|= B43_PHY_ANTWRSETT_ARXDIV
;
2898 tmp
&= ~B43_PHY_ANTWRSETT_ARXDIV
;
2899 b43_phy_write(dev
, B43_PHY_ANTWRSETT
, tmp
);
2900 if (phy
->rev
>= 2) {
2901 tmp
= b43_phy_read(dev
, B43_PHY_OFDM61
);
2902 tmp
|= B43_PHY_OFDM61_10
;
2903 b43_phy_write(dev
, B43_PHY_OFDM61
, tmp
);
2906 b43_phy_read(dev
, B43_PHY_DIVSRCHGAINBACK
);
2907 tmp
= (tmp
& 0xFF00) | 0x15;
2908 b43_phy_write(dev
, B43_PHY_DIVSRCHGAINBACK
,
2911 if (phy
->rev
== 2) {
2912 b43_phy_write(dev
, B43_PHY_ADIVRELATED
,
2917 B43_PHY_ADIVRELATED
);
2918 tmp
= (tmp
& 0xFF00) | 8;
2919 b43_phy_write(dev
, B43_PHY_ADIVRELATED
,
2924 b43_phy_write(dev
, B43_PHY_OFDM9B
, 0xDC);
2926 hf
|= B43_HF_ANTDIVHELP
;
2927 b43_hf_write(dev
, hf
);
2930 static int b43_gphy_op_interf_mitigation(struct b43_wldev
*dev
,
2931 enum b43_interference_mitigation mode
)
2933 struct b43_phy
*phy
= &dev
->phy
;
2934 struct b43_phy_g
*gphy
= phy
->g
;
2937 B43_WARN_ON(phy
->type
!= B43_PHYTYPE_G
);
2938 if ((phy
->rev
== 0) || (!phy
->gmode
))
2941 gphy
->aci_wlan_automatic
= 0;
2943 case B43_INTERFMODE_AUTOWLAN
:
2944 gphy
->aci_wlan_automatic
= 1;
2945 if (gphy
->aci_enable
)
2946 mode
= B43_INTERFMODE_MANUALWLAN
;
2948 mode
= B43_INTERFMODE_NONE
;
2950 case B43_INTERFMODE_NONE
:
2951 case B43_INTERFMODE_NONWLAN
:
2952 case B43_INTERFMODE_MANUALWLAN
:
2958 currentmode
= gphy
->interfmode
;
2959 if (currentmode
== mode
)
2961 if (currentmode
!= B43_INTERFMODE_NONE
)
2962 b43_radio_interference_mitigation_disable(dev
, currentmode
);
2964 if (mode
== B43_INTERFMODE_NONE
) {
2965 gphy
->aci_enable
= 0;
2966 gphy
->aci_hw_rssi
= 0;
2968 b43_radio_interference_mitigation_enable(dev
, mode
);
2969 gphy
->interfmode
= mode
;
2974 /* http://bcm-specs.sipsolutions.net/EstimatePowerOut
2975 * This function converts a TSSI value to dBm in Q5.2
2977 static s8
b43_gphy_estimate_power_out(struct b43_wldev
*dev
, s8 tssi
)
2979 struct b43_phy_g
*gphy
= dev
->phy
.g
;
2983 tmp
= (gphy
->tgt_idle_tssi
- gphy
->cur_idle_tssi
+ tssi
);
2984 tmp
= clamp_val(tmp
, 0x00, 0x3F);
2985 dbm
= gphy
->tssi2dbm
[tmp
];
2990 static void b43_put_attenuation_into_ranges(struct b43_wldev
*dev
,
2991 int *_bbatt
, int *_rfatt
)
2993 int rfatt
= *_rfatt
;
2994 int bbatt
= *_bbatt
;
2995 struct b43_txpower_lo_control
*lo
= dev
->phy
.g
->lo_control
;
2997 /* Get baseband and radio attenuation values into their permitted ranges.
2998 * Radio attenuation affects power level 4 times as much as baseband. */
3000 /* Range constants */
3001 const int rf_min
= lo
->rfatt_list
.min_val
;
3002 const int rf_max
= lo
->rfatt_list
.max_val
;
3003 const int bb_min
= lo
->bbatt_list
.min_val
;
3004 const int bb_max
= lo
->bbatt_list
.max_val
;
3007 if (rfatt
> rf_max
&& bbatt
> bb_max
- 4)
3008 break; /* Can not get it into ranges */
3009 if (rfatt
< rf_min
&& bbatt
< bb_min
+ 4)
3010 break; /* Can not get it into ranges */
3011 if (bbatt
> bb_max
&& rfatt
> rf_max
- 1)
3012 break; /* Can not get it into ranges */
3013 if (bbatt
< bb_min
&& rfatt
< rf_min
+ 1)
3014 break; /* Can not get it into ranges */
3016 if (bbatt
> bb_max
) {
3021 if (bbatt
< bb_min
) {
3026 if (rfatt
> rf_max
) {
3031 if (rfatt
< rf_min
) {
3039 *_rfatt
= clamp_val(rfatt
, rf_min
, rf_max
);
3040 *_bbatt
= clamp_val(bbatt
, bb_min
, bb_max
);
3043 static void b43_gphy_op_adjust_txpower(struct b43_wldev
*dev
)
3045 struct b43_phy
*phy
= &dev
->phy
;
3046 struct b43_phy_g
*gphy
= phy
->g
;
3050 spin_lock_irq(&dev
->wl
->irq_lock
);
3052 /* Calculate the new attenuation values. */
3053 bbatt
= gphy
->bbatt
.att
;
3054 bbatt
+= gphy
->bbatt_delta
;
3055 rfatt
= gphy
->rfatt
.att
;
3056 rfatt
+= gphy
->rfatt_delta
;
3058 b43_put_attenuation_into_ranges(dev
, &bbatt
, &rfatt
);
3059 tx_control
= gphy
->tx_control
;
3060 if ((phy
->radio_ver
== 0x2050) && (phy
->radio_rev
== 2)) {
3062 if (tx_control
== 0) {
3068 } else if (dev
->dev
->bus
->sprom
.
3071 bbatt
+= 4 * (rfatt
- 2);
3074 } else if (rfatt
> 4 && tx_control
) {
3085 /* Save the control values */
3086 gphy
->tx_control
= tx_control
;
3087 b43_put_attenuation_into_ranges(dev
, &bbatt
, &rfatt
);
3088 gphy
->rfatt
.att
= rfatt
;
3089 gphy
->bbatt
.att
= bbatt
;
3091 /* We drop the lock early, so we can sleep during hardware
3092 * adjustment. Possible races with op_recalc_txpower are harmless,
3093 * as we will be called once again in case we raced. */
3094 spin_unlock_irq(&dev
->wl
->irq_lock
);
3096 if (b43_debug(dev
, B43_DBG_XMITPOWER
))
3097 b43dbg(dev
->wl
, "Adjusting TX power\n");
3099 /* Adjust the hardware */
3101 b43_radio_lock(dev
);
3102 b43_set_txpower_g(dev
, &gphy
->bbatt
, &gphy
->rfatt
,
3104 b43_radio_unlock(dev
);
3105 b43_phy_unlock(dev
);
3108 static enum b43_txpwr_result
b43_gphy_op_recalc_txpower(struct b43_wldev
*dev
,
3111 struct b43_phy
*phy
= &dev
->phy
;
3112 struct b43_phy_g
*gphy
= phy
->g
;
3113 unsigned int average_tssi
;
3114 int cck_result
, ofdm_result
;
3115 int estimated_pwr
, desired_pwr
, pwr_adjust
;
3116 int rfatt_delta
, bbatt_delta
;
3117 unsigned int max_pwr
;
3119 /* First get the average TSSI */
3120 cck_result
= b43_phy_shm_tssi_read(dev
, B43_SHM_SH_TSSI_CCK
);
3121 ofdm_result
= b43_phy_shm_tssi_read(dev
, B43_SHM_SH_TSSI_OFDM_G
);
3122 if ((cck_result
< 0) && (ofdm_result
< 0)) {
3123 /* No TSSI information available */
3125 goto no_adjustment_needed
;
3130 average_tssi
= ofdm_result
;
3131 else if (ofdm_result
< 0)
3132 average_tssi
= cck_result
;
3134 average_tssi
= (cck_result
+ ofdm_result
) / 2;
3135 /* Merge the average with the stored value. */
3136 if (likely(gphy
->average_tssi
!= 0xFF))
3137 average_tssi
= (average_tssi
+ gphy
->average_tssi
) / 2;
3138 gphy
->average_tssi
= average_tssi
;
3139 B43_WARN_ON(average_tssi
>= B43_TSSI_MAX
);
3141 /* Estimate the TX power emission based on the TSSI */
3142 estimated_pwr
= b43_gphy_estimate_power_out(dev
, average_tssi
);
3144 B43_WARN_ON(phy
->type
!= B43_PHYTYPE_G
);
3145 max_pwr
= dev
->dev
->bus
->sprom
.maxpwr_bg
;
3146 if (dev
->dev
->bus
->sprom
.boardflags_lo
& B43_BFL_PACTRL
)
3147 max_pwr
-= 3; /* minus 0.75 */
3148 if (unlikely(max_pwr
>= INT_TO_Q52(30/*dBm*/))) {
3150 "Invalid max-TX-power value in SPROM.\n");
3151 max_pwr
= INT_TO_Q52(20); /* fake it */
3152 dev
->dev
->bus
->sprom
.maxpwr_bg
= max_pwr
;
3155 /* Get desired power (in Q5.2) */
3156 if (phy
->desired_txpower
< 0)
3157 desired_pwr
= INT_TO_Q52(0);
3159 desired_pwr
= INT_TO_Q52(phy
->desired_txpower
);
3160 /* And limit it. max_pwr already is Q5.2 */
3161 desired_pwr
= clamp_val(desired_pwr
, 0, max_pwr
);
3162 if (b43_debug(dev
, B43_DBG_XMITPOWER
)) {
3164 "[TX power] current = " Q52_FMT
3165 " dBm, desired = " Q52_FMT
3166 " dBm, max = " Q52_FMT
"\n",
3167 Q52_ARG(estimated_pwr
),
3168 Q52_ARG(desired_pwr
),
3172 /* Calculate the adjustment delta. */
3173 pwr_adjust
= desired_pwr
- estimated_pwr
;
3174 if (pwr_adjust
== 0)
3175 goto no_adjustment_needed
;
3177 /* RF attenuation delta. */
3178 rfatt_delta
= ((pwr_adjust
+ 7) / 8);
3179 /* Lower attenuation => Bigger power output. Negate it. */
3180 rfatt_delta
= -rfatt_delta
;
3182 /* Baseband attenuation delta. */
3183 bbatt_delta
= pwr_adjust
/ 2;
3184 /* Lower attenuation => Bigger power output. Negate it. */
3185 bbatt_delta
= -bbatt_delta
;
3186 /* RF att affects power level 4 times as much as
3187 * Baseband attennuation. Subtract it. */
3188 bbatt_delta
-= 4 * rfatt_delta
;
3190 if (b43_debug(dev
, B43_DBG_XMITPOWER
)) {
3191 int dbm
= pwr_adjust
< 0 ? -pwr_adjust
: pwr_adjust
;
3193 "[TX power deltas] %s" Q52_FMT
" dBm => "
3194 "bbatt-delta = %d, rfatt-delta = %d\n",
3195 (pwr_adjust
< 0 ? "-" : ""), Q52_ARG(dbm
),
3196 bbatt_delta
, rfatt_delta
);
3198 /* So do we finally need to adjust something in hardware? */
3199 if ((rfatt_delta
== 0) && (bbatt_delta
== 0))
3200 goto no_adjustment_needed
;
3202 /* Save the deltas for later when we adjust the power. */
3203 gphy
->bbatt_delta
= bbatt_delta
;
3204 gphy
->rfatt_delta
= rfatt_delta
;
3206 /* We need to adjust the TX power on the device. */
3207 return B43_TXPWR_RES_NEED_ADJUST
;
3209 no_adjustment_needed
:
3210 return B43_TXPWR_RES_DONE
;
3213 static void b43_gphy_op_pwork_15sec(struct b43_wldev
*dev
)
3215 struct b43_phy
*phy
= &dev
->phy
;
3216 struct b43_phy_g
*gphy
= phy
->g
;
3218 //TODO: update_aci_moving_average
3219 if (gphy
->aci_enable
&& gphy
->aci_wlan_automatic
) {
3220 b43_mac_suspend(dev
);
3221 if (!gphy
->aci_enable
&& 1 /*TODO: not scanning? */ ) {
3222 if (0 /*TODO: bunch of conditions */ ) {
3223 phy
->ops
->interf_mitigation(dev
,
3224 B43_INTERFMODE_MANUALWLAN
);
3226 } else if (0 /*TODO*/) {
3227 if (/*(aci_average > 1000) &&*/ !b43_gphy_aci_scan(dev
))
3228 phy
->ops
->interf_mitigation(dev
, B43_INTERFMODE_NONE
);
3230 b43_mac_enable(dev
);
3231 } else if (gphy
->interfmode
== B43_INTERFMODE_NONWLAN
&&
3233 //TODO: implement rev1 workaround
3235 b43_lo_g_maintanance_work(dev
);
3238 static void b43_gphy_op_pwork_60sec(struct b43_wldev
*dev
)
3240 struct b43_phy
*phy
= &dev
->phy
;
3242 if (!(dev
->dev
->bus
->sprom
.boardflags_lo
& B43_BFL_RSSI
))
3245 b43_mac_suspend(dev
);
3246 b43_calc_nrssi_slope(dev
);
3247 if ((phy
->radio_ver
== 0x2050) && (phy
->radio_rev
== 8)) {
3248 u8 old_chan
= phy
->channel
;
3250 /* VCO Calibration */
3252 b43_switch_channel(dev
, 1);
3254 b43_switch_channel(dev
, 13);
3255 b43_switch_channel(dev
, old_chan
);
3257 b43_mac_enable(dev
);
3260 const struct b43_phy_operations b43_phyops_g
= {
3261 .allocate
= b43_gphy_op_allocate
,
3262 .free
= b43_gphy_op_free
,
3263 .prepare_structs
= b43_gphy_op_prepare_structs
,
3264 .prepare_hardware
= b43_gphy_op_prepare_hardware
,
3265 .init
= b43_gphy_op_init
,
3266 .exit
= b43_gphy_op_exit
,
3267 .phy_read
= b43_gphy_op_read
,
3268 .phy_write
= b43_gphy_op_write
,
3269 .radio_read
= b43_gphy_op_radio_read
,
3270 .radio_write
= b43_gphy_op_radio_write
,
3271 .supports_hwpctl
= b43_gphy_op_supports_hwpctl
,
3272 .software_rfkill
= b43_gphy_op_software_rfkill
,
3273 .switch_analog
= b43_phyop_switch_analog_generic
,
3274 .switch_channel
= b43_gphy_op_switch_channel
,
3275 .get_default_chan
= b43_gphy_op_get_default_chan
,
3276 .set_rx_antenna
= b43_gphy_op_set_rx_antenna
,
3277 .interf_mitigation
= b43_gphy_op_interf_mitigation
,
3278 .recalc_txpower
= b43_gphy_op_recalc_txpower
,
3279 .adjust_txpower
= b43_gphy_op_adjust_txpower
,
3280 .pwork_15sec
= b43_gphy_op_pwork_15sec
,
3281 .pwork_60sec
= b43_gphy_op_pwork_60sec
,