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Merge branch 'for-john' of git://git.kernel.org/pub/scm/linux/kernel/git/jberg/mac802...
[deliverable/linux.git] / drivers / net / wireless / b43 / phy_ht.c
1 /*
2
3 Broadcom B43 wireless driver
4 IEEE 802.11n HT-PHY support
5
6 Copyright (c) 2011 Rafał Miłecki <zajec5@gmail.com>
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING. If not, write to
20 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
21 Boston, MA 02110-1301, USA.
22
23 */
24
25 #include <linux/slab.h>
26
27 #include "b43.h"
28 #include "phy_ht.h"
29 #include "tables_phy_ht.h"
30 #include "radio_2059.h"
31 #include "main.h"
32
33 /**************************************************
34 * Radio 2059.
35 **************************************************/
36
37 static void b43_radio_2059_channel_setup(struct b43_wldev *dev,
38 const struct b43_phy_ht_channeltab_e_radio2059 *e)
39 {
40 u8 i;
41 u16 routing;
42
43 b43_radio_write(dev, 0x16, e->radio_syn16);
44 b43_radio_write(dev, 0x17, e->radio_syn17);
45 b43_radio_write(dev, 0x22, e->radio_syn22);
46 b43_radio_write(dev, 0x25, e->radio_syn25);
47 b43_radio_write(dev, 0x27, e->radio_syn27);
48 b43_radio_write(dev, 0x28, e->radio_syn28);
49 b43_radio_write(dev, 0x29, e->radio_syn29);
50 b43_radio_write(dev, 0x2c, e->radio_syn2c);
51 b43_radio_write(dev, 0x2d, e->radio_syn2d);
52 b43_radio_write(dev, 0x37, e->radio_syn37);
53 b43_radio_write(dev, 0x41, e->radio_syn41);
54 b43_radio_write(dev, 0x43, e->radio_syn43);
55 b43_radio_write(dev, 0x47, e->radio_syn47);
56 b43_radio_write(dev, 0x4a, e->radio_syn4a);
57 b43_radio_write(dev, 0x58, e->radio_syn58);
58 b43_radio_write(dev, 0x5a, e->radio_syn5a);
59 b43_radio_write(dev, 0x6a, e->radio_syn6a);
60 b43_radio_write(dev, 0x6d, e->radio_syn6d);
61 b43_radio_write(dev, 0x6e, e->radio_syn6e);
62 b43_radio_write(dev, 0x92, e->radio_syn92);
63 b43_radio_write(dev, 0x98, e->radio_syn98);
64
65 for (i = 0; i < 2; i++) {
66 routing = i ? R2059_RXRX1 : R2059_TXRX0;
67 b43_radio_write(dev, routing | 0x4a, e->radio_rxtx4a);
68 b43_radio_write(dev, routing | 0x58, e->radio_rxtx58);
69 b43_radio_write(dev, routing | 0x5a, e->radio_rxtx5a);
70 b43_radio_write(dev, routing | 0x6a, e->radio_rxtx6a);
71 b43_radio_write(dev, routing | 0x6d, e->radio_rxtx6d);
72 b43_radio_write(dev, routing | 0x6e, e->radio_rxtx6e);
73 b43_radio_write(dev, routing | 0x92, e->radio_rxtx92);
74 b43_radio_write(dev, routing | 0x98, e->radio_rxtx98);
75 }
76
77 udelay(50);
78
79 /* Calibration */
80 b43_radio_mask(dev, 0x2b, ~0x1);
81 b43_radio_mask(dev, 0x2e, ~0x4);
82 b43_radio_set(dev, 0x2e, 0x4);
83 b43_radio_set(dev, 0x2b, 0x1);
84
85 udelay(300);
86 }
87
88 static void b43_radio_2059_init(struct b43_wldev *dev)
89 {
90 const u16 routing[] = { R2059_SYN, R2059_TXRX0, R2059_RXRX1 };
91 const u16 radio_values[3][2] = {
92 { 0x61, 0xE9 }, { 0x69, 0xD5 }, { 0x73, 0x99 },
93 };
94 u16 i, j;
95
96 b43_radio_write(dev, R2059_ALL | 0x51, 0x0070);
97 b43_radio_write(dev, R2059_ALL | 0x5a, 0x0003);
98
99 for (i = 0; i < ARRAY_SIZE(routing); i++)
100 b43_radio_set(dev, routing[i] | 0x146, 0x3);
101
102 b43_radio_set(dev, 0x2e, 0x0078);
103 b43_radio_set(dev, 0xc0, 0x0080);
104 msleep(2);
105 b43_radio_mask(dev, 0x2e, ~0x0078);
106 b43_radio_mask(dev, 0xc0, ~0x0080);
107
108 if (1) { /* FIXME */
109 b43_radio_set(dev, R2059_RXRX1 | 0x4, 0x1);
110 udelay(10);
111 b43_radio_set(dev, R2059_RXRX1 | 0x0BF, 0x1);
112 b43_radio_maskset(dev, R2059_RXRX1 | 0x19B, 0x3, 0x2);
113
114 b43_radio_set(dev, R2059_RXRX1 | 0x4, 0x2);
115 udelay(100);
116 b43_radio_mask(dev, R2059_RXRX1 | 0x4, ~0x2);
117
118 for (i = 0; i < 10000; i++) {
119 if (b43_radio_read(dev, R2059_RXRX1 | 0x145) & 1) {
120 i = 0;
121 break;
122 }
123 udelay(100);
124 }
125 if (i)
126 b43err(dev->wl, "radio 0x945 timeout\n");
127
128 b43_radio_mask(dev, R2059_RXRX1 | 0x4, ~0x1);
129 b43_radio_set(dev, 0xa, 0x60);
130
131 for (i = 0; i < 3; i++) {
132 b43_radio_write(dev, 0x17F, radio_values[i][0]);
133 b43_radio_write(dev, 0x13D, 0x6E);
134 b43_radio_write(dev, 0x13E, radio_values[i][1]);
135 b43_radio_write(dev, 0x13C, 0x55);
136
137 for (j = 0; j < 10000; j++) {
138 if (b43_radio_read(dev, 0x140) & 2) {
139 j = 0;
140 break;
141 }
142 udelay(500);
143 }
144 if (j)
145 b43err(dev->wl, "radio 0x140 timeout\n");
146
147 b43_radio_write(dev, 0x13C, 0x15);
148 }
149
150 b43_radio_mask(dev, 0x17F, ~0x1);
151 }
152
153 b43_radio_mask(dev, 0x11, ~0x0008);
154 }
155
156 /**************************************************
157 * RF
158 **************************************************/
159
160 static void b43_phy_ht_force_rf_sequence(struct b43_wldev *dev, u16 rf_seq)
161 {
162 u8 i;
163
164 u16 save_seq_mode = b43_phy_read(dev, B43_PHY_HT_RF_SEQ_MODE);
165 b43_phy_set(dev, B43_PHY_HT_RF_SEQ_MODE, 0x3);
166
167 b43_phy_set(dev, B43_PHY_HT_RF_SEQ_TRIG, rf_seq);
168 for (i = 0; i < 200; i++) {
169 if (!(b43_phy_read(dev, B43_PHY_HT_RF_SEQ_STATUS) & rf_seq)) {
170 i = 0;
171 break;
172 }
173 msleep(1);
174 }
175 if (i)
176 b43err(dev->wl, "Forcing RF sequence timeout\n");
177
178 b43_phy_write(dev, B43_PHY_HT_RF_SEQ_MODE, save_seq_mode);
179 }
180
181 static void b43_phy_ht_pa_override(struct b43_wldev *dev, bool enable)
182 {
183 struct b43_phy_ht *htphy = dev->phy.ht;
184 static const u16 regs[3] = { B43_PHY_HT_RF_CTL_INT_C1,
185 B43_PHY_HT_RF_CTL_INT_C2,
186 B43_PHY_HT_RF_CTL_INT_C3 };
187 int i;
188
189 if (enable) {
190 for (i = 0; i < 3; i++)
191 b43_phy_write(dev, regs[i], htphy->rf_ctl_int_save[i]);
192 } else {
193 for (i = 0; i < 3; i++)
194 htphy->rf_ctl_int_save[i] = b43_phy_read(dev, regs[i]);
195 /* TODO: Does 5GHz band use different value (not 0x0400)? */
196 for (i = 0; i < 3; i++)
197 b43_phy_write(dev, regs[i], 0x0400);
198 }
199 }
200
201 /**************************************************
202 * Various PHY ops
203 **************************************************/
204
205 static u16 b43_phy_ht_classifier(struct b43_wldev *dev, u16 mask, u16 val)
206 {
207 u16 tmp;
208 u16 allowed = B43_PHY_HT_CLASS_CTL_CCK_EN |
209 B43_PHY_HT_CLASS_CTL_OFDM_EN |
210 B43_PHY_HT_CLASS_CTL_WAITED_EN;
211
212 tmp = b43_phy_read(dev, B43_PHY_HT_CLASS_CTL);
213 tmp &= allowed;
214 tmp &= ~mask;
215 tmp |= (val & mask);
216 b43_phy_maskset(dev, B43_PHY_HT_CLASS_CTL, ~allowed, tmp);
217
218 return tmp;
219 }
220
221 static void b43_phy_ht_reset_cca(struct b43_wldev *dev)
222 {
223 u16 bbcfg;
224
225 b43_phy_force_clock(dev, true);
226 bbcfg = b43_phy_read(dev, B43_PHY_HT_BBCFG);
227 b43_phy_write(dev, B43_PHY_HT_BBCFG, bbcfg | B43_PHY_HT_BBCFG_RSTCCA);
228 udelay(1);
229 b43_phy_write(dev, B43_PHY_HT_BBCFG, bbcfg & ~B43_PHY_HT_BBCFG_RSTCCA);
230 b43_phy_force_clock(dev, false);
231
232 b43_phy_ht_force_rf_sequence(dev, B43_PHY_HT_RF_SEQ_TRIG_RST2RX);
233 }
234
235 static void b43_phy_ht_zero_extg(struct b43_wldev *dev)
236 {
237 u8 i, j;
238 u16 base[] = { 0x40, 0x60, 0x80 };
239
240 for (i = 0; i < ARRAY_SIZE(base); i++) {
241 for (j = 0; j < 4; j++)
242 b43_phy_write(dev, B43_PHY_EXTG(base[i] + j), 0);
243 }
244
245 for (i = 0; i < ARRAY_SIZE(base); i++)
246 b43_phy_write(dev, B43_PHY_EXTG(base[i] + 0xc), 0);
247 }
248
249 /* Some unknown AFE (Analog Frondned) op */
250 static void b43_phy_ht_afe_unk1(struct b43_wldev *dev)
251 {
252 u8 i;
253
254 static const u16 ctl_regs[3][2] = {
255 { B43_PHY_HT_AFE_C1_OVER, B43_PHY_HT_AFE_C1 },
256 { B43_PHY_HT_AFE_C2_OVER, B43_PHY_HT_AFE_C2 },
257 { B43_PHY_HT_AFE_C3_OVER, B43_PHY_HT_AFE_C3},
258 };
259
260 for (i = 0; i < 3; i++) {
261 /* TODO: verify masks&sets */
262 b43_phy_set(dev, ctl_regs[i][1], 0x4);
263 b43_phy_set(dev, ctl_regs[i][0], 0x4);
264 b43_phy_mask(dev, ctl_regs[i][1], ~0x1);
265 b43_phy_set(dev, ctl_regs[i][0], 0x1);
266 b43_httab_write(dev, B43_HTTAB16(8, 5 + (i * 0x10)), 0);
267 b43_phy_mask(dev, ctl_regs[i][0], ~0x4);
268 }
269 }
270
271 static void b43_phy_ht_read_clip_detection(struct b43_wldev *dev, u16 *clip_st)
272 {
273 clip_st[0] = b43_phy_read(dev, B43_PHY_HT_C1_CLIP1THRES);
274 clip_st[1] = b43_phy_read(dev, B43_PHY_HT_C2_CLIP1THRES);
275 clip_st[2] = b43_phy_read(dev, B43_PHY_HT_C3_CLIP1THRES);
276 }
277
278 static void b43_phy_ht_bphy_init(struct b43_wldev *dev)
279 {
280 unsigned int i;
281 u16 val;
282
283 val = 0x1E1F;
284 for (i = 0; i < 16; i++) {
285 b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val);
286 val -= 0x202;
287 }
288 val = 0x3E3F;
289 for (i = 0; i < 16; i++) {
290 b43_phy_write(dev, B43_PHY_N_BMODE(0x98 + i), val);
291 val -= 0x202;
292 }
293 b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668);
294 }
295
296 /**************************************************
297 * Samples
298 **************************************************/
299
300 static void b43_phy_ht_stop_playback(struct b43_wldev *dev)
301 {
302 struct b43_phy_ht *phy_ht = dev->phy.ht;
303 u16 tmp;
304 int i;
305
306 tmp = b43_phy_read(dev, B43_PHY_HT_SAMP_STAT);
307 if (tmp & 0x1)
308 b43_phy_set(dev, B43_PHY_HT_SAMP_CMD, B43_PHY_HT_SAMP_CMD_STOP);
309 else if (tmp & 0x2)
310 b43_phy_mask(dev, B43_PHY_HT_IQLOCAL_CMDGCTL, 0x7FFF);
311
312 b43_phy_mask(dev, B43_PHY_HT_SAMP_CMD, ~0x0004);
313
314 for (i = 0; i < 3; i++) {
315 if (phy_ht->bb_mult_save[i] >= 0) {
316 b43_httab_write(dev, B43_HTTAB16(13, 0x63 + i * 4),
317 phy_ht->bb_mult_save[i]);
318 b43_httab_write(dev, B43_HTTAB16(13, 0x67 + i * 4),
319 phy_ht->bb_mult_save[i]);
320 }
321 }
322 }
323
324 static u16 b43_phy_ht_load_samples(struct b43_wldev *dev)
325 {
326 int i;
327 u16 len = 20 << 3;
328
329 b43_phy_write(dev, B43_PHY_HT_TABLE_ADDR, 0x4400);
330
331 for (i = 0; i < len; i++) {
332 b43_phy_write(dev, B43_PHY_HT_TABLE_DATAHI, 0);
333 b43_phy_write(dev, B43_PHY_HT_TABLE_DATALO, 0);
334 }
335
336 return len;
337 }
338
339 static void b43_phy_ht_run_samples(struct b43_wldev *dev, u16 samps, u16 loops,
340 u16 wait)
341 {
342 struct b43_phy_ht *phy_ht = dev->phy.ht;
343 u16 save_seq_mode;
344 int i;
345
346 for (i = 0; i < 3; i++) {
347 if (phy_ht->bb_mult_save[i] < 0)
348 phy_ht->bb_mult_save[i] = b43_httab_read(dev, B43_HTTAB16(13, 0x63 + i * 4));
349 }
350
351 b43_phy_write(dev, B43_PHY_HT_SAMP_DEP_CNT, samps - 1);
352 if (loops != 0xFFFF)
353 loops--;
354 b43_phy_write(dev, B43_PHY_HT_SAMP_LOOP_CNT, loops);
355 b43_phy_write(dev, B43_PHY_HT_SAMP_WAIT_CNT, wait);
356
357 save_seq_mode = b43_phy_read(dev, B43_PHY_HT_RF_SEQ_MODE);
358 b43_phy_set(dev, B43_PHY_HT_RF_SEQ_MODE,
359 B43_PHY_HT_RF_SEQ_MODE_CA_OVER);
360
361 /* TODO: find out mask bits! Do we need more function arguments? */
362 b43_phy_mask(dev, B43_PHY_HT_SAMP_CMD, ~0);
363 b43_phy_mask(dev, B43_PHY_HT_SAMP_CMD, ~0);
364 b43_phy_mask(dev, B43_PHY_HT_IQLOCAL_CMDGCTL, ~0);
365 b43_phy_set(dev, B43_PHY_HT_SAMP_CMD, 0x1);
366
367 for (i = 0; i < 100; i++) {
368 if (!(b43_phy_read(dev, B43_PHY_HT_RF_SEQ_STATUS) & 1)) {
369 i = 0;
370 break;
371 }
372 udelay(10);
373 }
374 if (i)
375 b43err(dev->wl, "run samples timeout\n");
376
377 b43_phy_write(dev, B43_PHY_HT_RF_SEQ_MODE, save_seq_mode);
378 }
379
380 static void b43_phy_ht_tx_tone(struct b43_wldev *dev)
381 {
382 u16 samp;
383
384 samp = b43_phy_ht_load_samples(dev);
385 b43_phy_ht_run_samples(dev, samp, 0xFFFF, 0);
386 }
387
388 /**************************************************
389 * RSSI
390 **************************************************/
391
392 static void b43_phy_ht_rssi_select(struct b43_wldev *dev, u8 core_sel,
393 u8 rssi_type)
394 {
395 static const u16 ctl_regs[3][2] = {
396 { B43_PHY_HT_AFE_C1, B43_PHY_HT_AFE_C1_OVER, },
397 { B43_PHY_HT_AFE_C2, B43_PHY_HT_AFE_C2_OVER, },
398 { B43_PHY_HT_AFE_C3, B43_PHY_HT_AFE_C3_OVER, },
399 };
400 static const u16 radio_r[] = { R2059_SYN, R2059_TXRX0, R2059_RXRX1, };
401 int core;
402
403 if (core_sel == 0) {
404 b43err(dev->wl, "RSSI selection for core off not implemented yet\n");
405 } else {
406 for (core = 0; core < 3; core++) {
407 /* Check if caller requested a one specific core */
408 if ((core_sel == 1 && core != 0) ||
409 (core_sel == 2 && core != 1) ||
410 (core_sel == 3 && core != 2))
411 continue;
412
413 switch (rssi_type) {
414 case 4:
415 b43_phy_set(dev, ctl_regs[core][0], 0x3 << 8);
416 b43_phy_set(dev, ctl_regs[core][0], 0x3 << 10);
417 b43_phy_set(dev, ctl_regs[core][1], 0x1 << 9);
418 b43_phy_set(dev, ctl_regs[core][1], 0x1 << 10);
419
420 b43_radio_set(dev, R2059_RXRX1 | 0xbf, 0x1);
421 b43_radio_write(dev, radio_r[core] | 0x159,
422 0x11);
423 break;
424 default:
425 b43err(dev->wl, "RSSI selection for type %d not implemented yet\n",
426 rssi_type);
427 }
428 }
429 }
430 }
431
432 static void b43_phy_ht_poll_rssi(struct b43_wldev *dev, u8 type, s32 *buf,
433 u8 nsamp)
434 {
435 u16 phy_regs_values[12];
436 static const u16 phy_regs_to_save[] = {
437 B43_PHY_HT_AFE_C1, B43_PHY_HT_AFE_C1_OVER,
438 0x848, 0x841,
439 B43_PHY_HT_AFE_C2, B43_PHY_HT_AFE_C2_OVER,
440 0x868, 0x861,
441 B43_PHY_HT_AFE_C3, B43_PHY_HT_AFE_C3_OVER,
442 0x888, 0x881,
443 };
444 u16 tmp[3];
445 int i;
446
447 for (i = 0; i < 12; i++)
448 phy_regs_values[i] = b43_phy_read(dev, phy_regs_to_save[i]);
449
450 b43_phy_ht_rssi_select(dev, 5, type);
451
452 for (i = 0; i < 6; i++)
453 buf[i] = 0;
454
455 for (i = 0; i < nsamp; i++) {
456 tmp[0] = b43_phy_read(dev, B43_PHY_HT_RSSI_C1);
457 tmp[1] = b43_phy_read(dev, B43_PHY_HT_RSSI_C2);
458 tmp[2] = b43_phy_read(dev, B43_PHY_HT_RSSI_C3);
459
460 buf[0] += ((s8)((tmp[0] & 0x3F) << 2)) >> 2;
461 buf[1] += ((s8)(((tmp[0] >> 8) & 0x3F) << 2)) >> 2;
462 buf[2] += ((s8)((tmp[1] & 0x3F) << 2)) >> 2;
463 buf[3] += ((s8)(((tmp[1] >> 8) & 0x3F) << 2)) >> 2;
464 buf[4] += ((s8)((tmp[2] & 0x3F) << 2)) >> 2;
465 buf[5] += ((s8)(((tmp[2] >> 8) & 0x3F) << 2)) >> 2;
466 }
467
468 for (i = 0; i < 12; i++)
469 b43_phy_write(dev, phy_regs_to_save[i], phy_regs_values[i]);
470 }
471
472 /**************************************************
473 * Tx/Rx
474 **************************************************/
475
476 static void b43_phy_ht_tx_power_fix(struct b43_wldev *dev)
477 {
478 int i;
479
480 for (i = 0; i < 3; i++) {
481 u16 mask;
482 u32 tmp = b43_httab_read(dev, B43_HTTAB32(26, 0xE8));
483
484 if (0) /* FIXME */
485 mask = 0x2 << (i * 4);
486 else
487 mask = 0;
488 b43_phy_mask(dev, B43_PHY_EXTG(0x108), mask);
489
490 b43_httab_write(dev, B43_HTTAB16(7, 0x110 + i), tmp >> 16);
491 b43_httab_write(dev, B43_HTTAB8(13, 0x63 + (i * 4)),
492 tmp & 0xFF);
493 b43_httab_write(dev, B43_HTTAB8(13, 0x73 + (i * 4)),
494 tmp & 0xFF);
495 }
496 }
497
498 static void b43_phy_ht_tx_power_ctl(struct b43_wldev *dev, bool enable)
499 {
500 struct b43_phy_ht *phy_ht = dev->phy.ht;
501 u16 en_bits = B43_PHY_HT_TXPCTL_CMD_C1_COEFF |
502 B43_PHY_HT_TXPCTL_CMD_C1_HWPCTLEN |
503 B43_PHY_HT_TXPCTL_CMD_C1_PCTLEN;
504 static const u16 cmd_regs[3] = { B43_PHY_HT_TXPCTL_CMD_C1,
505 B43_PHY_HT_TXPCTL_CMD_C2,
506 B43_PHY_HT_TXPCTL_CMD_C3 };
507 int i;
508
509 if (!enable) {
510 if (b43_phy_read(dev, B43_PHY_HT_TXPCTL_CMD_C1) & en_bits) {
511 /* We disable enabled TX pwr ctl, save it's state */
512 /*
513 * TODO: find the registers. On N-PHY they were 0x1ed
514 * and 0x1ee, we need 3 such a registers for HT-PHY
515 */
516 }
517 b43_phy_mask(dev, B43_PHY_HT_TXPCTL_CMD_C1, ~en_bits);
518 } else {
519 b43_phy_set(dev, B43_PHY_HT_TXPCTL_CMD_C1, en_bits);
520
521 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
522 for (i = 0; i < 3; i++)
523 b43_phy_write(dev, cmd_regs[i], 0x32);
524 }
525
526 for (i = 0; i < 3; i++)
527 if (phy_ht->tx_pwr_idx[i] <=
528 B43_PHY_HT_TXPCTL_CMD_C1_INIT)
529 b43_phy_write(dev, cmd_regs[i],
530 phy_ht->tx_pwr_idx[i]);
531 }
532
533 phy_ht->tx_pwr_ctl = enable;
534 }
535
536 static void b43_phy_ht_tx_power_ctl_idle_tssi(struct b43_wldev *dev)
537 {
538 struct b43_phy_ht *phy_ht = dev->phy.ht;
539 s32 rssi_buf[6];
540
541 /* TODO */
542
543 b43_phy_ht_tx_tone(dev);
544 udelay(20);
545 b43_phy_ht_poll_rssi(dev, 4, rssi_buf, 1);
546 b43_phy_ht_stop_playback(dev);
547 b43_phy_ht_reset_cca(dev);
548
549 phy_ht->idle_tssi[0] = rssi_buf[0] & 0xff;
550 phy_ht->idle_tssi[1] = rssi_buf[2] & 0xff;
551 phy_ht->idle_tssi[2] = rssi_buf[4] & 0xff;
552
553 /* TODO */
554 }
555
556 static void b43_phy_ht_tx_power_ctl_setup(struct b43_wldev *dev)
557 {
558 struct b43_phy_ht *phy_ht = dev->phy.ht;
559 struct ssb_sprom *sprom = dev->dev->bus_sprom;
560
561 u8 *idle = phy_ht->idle_tssi;
562 u8 target[3];
563 s16 a1[3], b0[3], b1[3];
564
565 u16 freq = dev->phy.channel_freq;
566 int i, c;
567
568 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
569 for (c = 0; c < 3; c++) {
570 target[c] = sprom->core_pwr_info[c].maxpwr_2g;
571 a1[c] = sprom->core_pwr_info[c].pa_2g[0];
572 b0[c] = sprom->core_pwr_info[c].pa_2g[1];
573 b1[c] = sprom->core_pwr_info[c].pa_2g[2];
574 }
575 } else if (freq >= 4900 && freq < 5100) {
576 for (c = 0; c < 3; c++) {
577 target[c] = sprom->core_pwr_info[c].maxpwr_5gl;
578 a1[c] = sprom->core_pwr_info[c].pa_5gl[0];
579 b0[c] = sprom->core_pwr_info[c].pa_5gl[1];
580 b1[c] = sprom->core_pwr_info[c].pa_5gl[2];
581 }
582 } else if (freq >= 5100 && freq < 5500) {
583 for (c = 0; c < 3; c++) {
584 target[c] = sprom->core_pwr_info[c].maxpwr_5g;
585 a1[c] = sprom->core_pwr_info[c].pa_5g[0];
586 b0[c] = sprom->core_pwr_info[c].pa_5g[1];
587 b1[c] = sprom->core_pwr_info[c].pa_5g[2];
588 }
589 } else if (freq >= 5500) {
590 for (c = 0; c < 3; c++) {
591 target[c] = sprom->core_pwr_info[c].maxpwr_5gh;
592 a1[c] = sprom->core_pwr_info[c].pa_5gh[0];
593 b0[c] = sprom->core_pwr_info[c].pa_5gh[1];
594 b1[c] = sprom->core_pwr_info[c].pa_5gh[2];
595 }
596 } else {
597 target[0] = target[1] = target[2] = 52;
598 a1[0] = a1[1] = a1[2] = -424;
599 b0[0] = b0[1] = b0[2] = 5612;
600 b1[0] = b1[1] = b1[2] = -1393;
601 }
602
603 b43_phy_set(dev, B43_PHY_HT_TSSIMODE, B43_PHY_HT_TSSIMODE_EN);
604 b43_phy_mask(dev, B43_PHY_HT_TXPCTL_CMD_C1,
605 ~B43_PHY_HT_TXPCTL_CMD_C1_PCTLEN & 0xFFFF);
606
607 /* TODO: Does it depend on sprom->fem.ghz2.tssipos? */
608 b43_phy_set(dev, B43_PHY_HT_TXPCTL_IDLE_TSSI, 0x4000);
609
610 b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_CMD_C1,
611 ~B43_PHY_HT_TXPCTL_CMD_C1_INIT, 0x19);
612 b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_CMD_C2,
613 ~B43_PHY_HT_TXPCTL_CMD_C2_INIT, 0x19);
614 b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_CMD_C3,
615 ~B43_PHY_HT_TXPCTL_CMD_C3_INIT, 0x19);
616
617 b43_phy_set(dev, B43_PHY_HT_TXPCTL_IDLE_TSSI,
618 B43_PHY_HT_TXPCTL_IDLE_TSSI_BINF);
619
620 b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_IDLE_TSSI,
621 ~B43_PHY_HT_TXPCTL_IDLE_TSSI_C1,
622 idle[0] << B43_PHY_HT_TXPCTL_IDLE_TSSI_C1_SHIFT);
623 b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_IDLE_TSSI,
624 ~B43_PHY_HT_TXPCTL_IDLE_TSSI_C2,
625 idle[1] << B43_PHY_HT_TXPCTL_IDLE_TSSI_C2_SHIFT);
626 b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_IDLE_TSSI2,
627 ~B43_PHY_HT_TXPCTL_IDLE_TSSI2_C3,
628 idle[2] << B43_PHY_HT_TXPCTL_IDLE_TSSI2_C3_SHIFT);
629
630 b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_N, ~B43_PHY_HT_TXPCTL_N_TSSID,
631 0xf0);
632 b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_N, ~B43_PHY_HT_TXPCTL_N_NPTIL2,
633 0x3 << B43_PHY_HT_TXPCTL_N_NPTIL2_SHIFT);
634 #if 0
635 /* TODO: what to mask/set? */
636 b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_CMD_C1, 0x800, 0)
637 b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_CMD_C1, 0x400, 0)
638 #endif
639
640 b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_TARG_PWR,
641 ~B43_PHY_HT_TXPCTL_TARG_PWR_C1,
642 target[0] << B43_PHY_HT_TXPCTL_TARG_PWR_C1_SHIFT);
643 b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_TARG_PWR,
644 ~B43_PHY_HT_TXPCTL_TARG_PWR_C2 & 0xFFFF,
645 target[1] << B43_PHY_HT_TXPCTL_TARG_PWR_C2_SHIFT);
646 b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_TARG_PWR2,
647 ~B43_PHY_HT_TXPCTL_TARG_PWR2_C3,
648 target[2] << B43_PHY_HT_TXPCTL_TARG_PWR2_C3_SHIFT);
649
650 for (c = 0; c < 3; c++) {
651 s32 num, den, pwr;
652 u32 regval[64];
653
654 for (i = 0; i < 64; i++) {
655 num = 8 * (16 * b0[c] + b1[c] * i);
656 den = 32768 + a1[c] * i;
657 pwr = max((4 * num + den / 2) / den, -8);
658 regval[i] = pwr;
659 }
660 b43_httab_write_bulk(dev, B43_HTTAB16(26 + c, 0), 64, regval);
661 }
662 }
663
664 /**************************************************
665 * Channel switching ops.
666 **************************************************/
667
668 static void b43_phy_ht_spur_avoid(struct b43_wldev *dev,
669 struct ieee80211_channel *new_channel)
670 {
671 struct bcma_device *core = dev->dev->bdev;
672 int spuravoid = 0;
673 u16 tmp;
674
675 /* Check for 13 and 14 is just a guess, we don't have enough logs. */
676 if (new_channel->hw_value == 13 || new_channel->hw_value == 14)
677 spuravoid = 1;
678 bcma_core_pll_ctl(core, B43_BCMA_CLKCTLST_PHY_PLL_REQ, 0, false);
679 bcma_pmu_spuravoid_pllupdate(&core->bus->drv_cc, spuravoid);
680 bcma_core_pll_ctl(core,
681 B43_BCMA_CLKCTLST_80211_PLL_REQ |
682 B43_BCMA_CLKCTLST_PHY_PLL_REQ,
683 B43_BCMA_CLKCTLST_80211_PLL_ST |
684 B43_BCMA_CLKCTLST_PHY_PLL_ST, false);
685
686 /* Values has been taken from wlc_bmac_switch_macfreq comments */
687 switch (spuravoid) {
688 case 2: /* 126MHz */
689 tmp = 0x2082;
690 break;
691 case 1: /* 123MHz */
692 tmp = 0x5341;
693 break;
694 default: /* 120MHz */
695 tmp = 0x8889;
696 }
697
698 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW, tmp);
699 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0x8);
700
701 /* TODO: reset PLL */
702
703 if (spuravoid)
704 b43_phy_set(dev, B43_PHY_HT_BBCFG, B43_PHY_HT_BBCFG_RSTRX);
705 else
706 b43_phy_mask(dev, B43_PHY_HT_BBCFG,
707 ~B43_PHY_HT_BBCFG_RSTRX & 0xFFFF);
708
709 b43_phy_ht_reset_cca(dev);
710 }
711
712 static void b43_phy_ht_channel_setup(struct b43_wldev *dev,
713 const struct b43_phy_ht_channeltab_e_phy *e,
714 struct ieee80211_channel *new_channel)
715 {
716 bool old_band_5ghz;
717
718 old_band_5ghz = b43_phy_read(dev, B43_PHY_HT_BANDCTL) & 0; /* FIXME */
719 if (new_channel->band == IEEE80211_BAND_5GHZ && !old_band_5ghz) {
720 /* TODO */
721 } else if (new_channel->band == IEEE80211_BAND_2GHZ && old_band_5ghz) {
722 /* TODO */
723 }
724
725 b43_phy_write(dev, B43_PHY_HT_BW1, e->bw1);
726 b43_phy_write(dev, B43_PHY_HT_BW2, e->bw2);
727 b43_phy_write(dev, B43_PHY_HT_BW3, e->bw3);
728 b43_phy_write(dev, B43_PHY_HT_BW4, e->bw4);
729 b43_phy_write(dev, B43_PHY_HT_BW5, e->bw5);
730 b43_phy_write(dev, B43_PHY_HT_BW6, e->bw6);
731
732 if (new_channel->hw_value == 14) {
733 b43_phy_ht_classifier(dev, B43_PHY_HT_CLASS_CTL_OFDM_EN, 0);
734 b43_phy_set(dev, B43_PHY_HT_TEST, 0x0800);
735 } else {
736 b43_phy_ht_classifier(dev, B43_PHY_HT_CLASS_CTL_OFDM_EN,
737 B43_PHY_HT_CLASS_CTL_OFDM_EN);
738 if (new_channel->band == IEEE80211_BAND_2GHZ)
739 b43_phy_mask(dev, B43_PHY_HT_TEST, ~0x840);
740 }
741
742 if (1) /* TODO: On N it's for early devices only, what about HT? */
743 b43_phy_ht_tx_power_fix(dev);
744
745 b43_phy_ht_spur_avoid(dev, new_channel);
746
747 b43_phy_write(dev, 0x017e, 0x3830);
748 }
749
750 static int b43_phy_ht_set_channel(struct b43_wldev *dev,
751 struct ieee80211_channel *channel,
752 enum nl80211_channel_type channel_type)
753 {
754 struct b43_phy *phy = &dev->phy;
755
756 const struct b43_phy_ht_channeltab_e_radio2059 *chent_r2059 = NULL;
757
758 if (phy->radio_ver == 0x2059) {
759 chent_r2059 = b43_phy_ht_get_channeltab_e_r2059(dev,
760 channel->center_freq);
761 if (!chent_r2059)
762 return -ESRCH;
763 } else {
764 return -ESRCH;
765 }
766
767 /* TODO: In case of N-PHY some bandwidth switching goes here */
768
769 if (phy->radio_ver == 0x2059) {
770 b43_radio_2059_channel_setup(dev, chent_r2059);
771 b43_phy_ht_channel_setup(dev, &(chent_r2059->phy_regs),
772 channel);
773 } else {
774 return -ESRCH;
775 }
776
777 return 0;
778 }
779
780 /**************************************************
781 * Basic PHY ops.
782 **************************************************/
783
784 static int b43_phy_ht_op_allocate(struct b43_wldev *dev)
785 {
786 struct b43_phy_ht *phy_ht;
787
788 phy_ht = kzalloc(sizeof(*phy_ht), GFP_KERNEL);
789 if (!phy_ht)
790 return -ENOMEM;
791 dev->phy.ht = phy_ht;
792
793 return 0;
794 }
795
796 static void b43_phy_ht_op_prepare_structs(struct b43_wldev *dev)
797 {
798 struct b43_phy *phy = &dev->phy;
799 struct b43_phy_ht *phy_ht = phy->ht;
800 int i;
801
802 memset(phy_ht, 0, sizeof(*phy_ht));
803
804 phy_ht->tx_pwr_ctl = true;
805 for (i = 0; i < 3; i++)
806 phy_ht->tx_pwr_idx[i] = B43_PHY_HT_TXPCTL_CMD_C1_INIT + 1;
807
808 for (i = 0; i < 3; i++)
809 phy_ht->bb_mult_save[i] = -1;
810 }
811
812 static int b43_phy_ht_op_init(struct b43_wldev *dev)
813 {
814 struct b43_phy_ht *phy_ht = dev->phy.ht;
815 u16 tmp;
816 u16 clip_state[3];
817 bool saved_tx_pwr_ctl;
818
819 if (dev->dev->bus_type != B43_BUS_BCMA) {
820 b43err(dev->wl, "HT-PHY is supported only on BCMA bus!\n");
821 return -EOPNOTSUPP;
822 }
823
824 b43_phy_ht_tables_init(dev);
825
826 b43_phy_mask(dev, 0x0be, ~0x2);
827 b43_phy_set(dev, 0x23f, 0x7ff);
828 b43_phy_set(dev, 0x240, 0x7ff);
829 b43_phy_set(dev, 0x241, 0x7ff);
830
831 b43_phy_ht_zero_extg(dev);
832
833 b43_phy_mask(dev, B43_PHY_EXTG(0), ~0x3);
834
835 b43_phy_write(dev, B43_PHY_HT_AFE_C1_OVER, 0);
836 b43_phy_write(dev, B43_PHY_HT_AFE_C2_OVER, 0);
837 b43_phy_write(dev, B43_PHY_HT_AFE_C3_OVER, 0);
838
839 b43_phy_write(dev, B43_PHY_EXTG(0x103), 0x20);
840 b43_phy_write(dev, B43_PHY_EXTG(0x101), 0x20);
841 b43_phy_write(dev, 0x20d, 0xb8);
842 b43_phy_write(dev, B43_PHY_EXTG(0x14f), 0xc8);
843 b43_phy_write(dev, 0x70, 0x50);
844 b43_phy_write(dev, 0x1ff, 0x30);
845
846 if (0) /* TODO: condition */
847 ; /* TODO: PHY op on reg 0x217 */
848
849 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
850 b43_phy_ht_classifier(dev, B43_PHY_HT_CLASS_CTL_CCK_EN, 0);
851 else
852 b43_phy_ht_classifier(dev, B43_PHY_HT_CLASS_CTL_CCK_EN,
853 B43_PHY_HT_CLASS_CTL_CCK_EN);
854
855 b43_phy_set(dev, 0xb1, 0x91);
856 b43_phy_write(dev, 0x32f, 0x0003);
857 b43_phy_write(dev, 0x077, 0x0010);
858 b43_phy_write(dev, 0x0b4, 0x0258);
859 b43_phy_mask(dev, 0x17e, ~0x4000);
860
861 b43_phy_write(dev, 0x0b9, 0x0072);
862
863 b43_httab_write_few(dev, B43_HTTAB16(7, 0x14e), 2, 0x010f, 0x010f);
864 b43_httab_write_few(dev, B43_HTTAB16(7, 0x15e), 2, 0x010f, 0x010f);
865 b43_httab_write_few(dev, B43_HTTAB16(7, 0x16e), 2, 0x010f, 0x010f);
866
867 b43_phy_ht_afe_unk1(dev);
868
869 b43_httab_write_few(dev, B43_HTTAB16(7, 0x130), 9, 0x777, 0x111, 0x111,
870 0x777, 0x111, 0x111, 0x777, 0x111, 0x111);
871
872 b43_httab_write(dev, B43_HTTAB16(7, 0x120), 0x0777);
873 b43_httab_write(dev, B43_HTTAB16(7, 0x124), 0x0777);
874
875 b43_httab_write(dev, B43_HTTAB16(8, 0x00), 0x02);
876 b43_httab_write(dev, B43_HTTAB16(8, 0x10), 0x02);
877 b43_httab_write(dev, B43_HTTAB16(8, 0x20), 0x02);
878
879 b43_httab_write_few(dev, B43_HTTAB16(8, 0x08), 4,
880 0x8e, 0x96, 0x96, 0x96);
881 b43_httab_write_few(dev, B43_HTTAB16(8, 0x18), 4,
882 0x8f, 0x9f, 0x9f, 0x9f);
883 b43_httab_write_few(dev, B43_HTTAB16(8, 0x28), 4,
884 0x8f, 0x9f, 0x9f, 0x9f);
885
886 b43_httab_write_few(dev, B43_HTTAB16(8, 0x0c), 4, 0x2, 0x2, 0x2, 0x2);
887 b43_httab_write_few(dev, B43_HTTAB16(8, 0x1c), 4, 0x2, 0x2, 0x2, 0x2);
888 b43_httab_write_few(dev, B43_HTTAB16(8, 0x2c), 4, 0x2, 0x2, 0x2, 0x2);
889
890 b43_phy_maskset(dev, 0x0280, 0xff00, 0x3e);
891 b43_phy_maskset(dev, 0x0283, 0xff00, 0x3e);
892 b43_phy_maskset(dev, B43_PHY_OFDM(0x0141), 0xff00, 0x46);
893 b43_phy_maskset(dev, 0x0283, 0xff00, 0x40);
894
895 b43_httab_write_few(dev, B43_HTTAB16(00, 0x8), 4,
896 0x09, 0x0e, 0x13, 0x18);
897 b43_httab_write_few(dev, B43_HTTAB16(01, 0x8), 4,
898 0x09, 0x0e, 0x13, 0x18);
899 /* TODO: Did wl mean 2 instead of 40? */
900 b43_httab_write_few(dev, B43_HTTAB16(40, 0x8), 4,
901 0x09, 0x0e, 0x13, 0x18);
902
903 b43_phy_maskset(dev, B43_PHY_OFDM(0x24), 0x3f, 0xd);
904 b43_phy_maskset(dev, B43_PHY_OFDM(0x64), 0x3f, 0xd);
905 b43_phy_maskset(dev, B43_PHY_OFDM(0xa4), 0x3f, 0xd);
906
907 b43_phy_set(dev, B43_PHY_EXTG(0x060), 0x1);
908 b43_phy_set(dev, B43_PHY_EXTG(0x064), 0x1);
909 b43_phy_set(dev, B43_PHY_EXTG(0x080), 0x1);
910 b43_phy_set(dev, B43_PHY_EXTG(0x084), 0x1);
911
912 /* Copy some tables entries */
913 tmp = b43_httab_read(dev, B43_HTTAB16(7, 0x144));
914 b43_httab_write(dev, B43_HTTAB16(7, 0x14a), tmp);
915 tmp = b43_httab_read(dev, B43_HTTAB16(7, 0x154));
916 b43_httab_write(dev, B43_HTTAB16(7, 0x15a), tmp);
917 tmp = b43_httab_read(dev, B43_HTTAB16(7, 0x164));
918 b43_httab_write(dev, B43_HTTAB16(7, 0x16a), tmp);
919
920 /* Reset CCA */
921 b43_phy_force_clock(dev, true);
922 tmp = b43_phy_read(dev, B43_PHY_HT_BBCFG);
923 b43_phy_write(dev, B43_PHY_HT_BBCFG, tmp | B43_PHY_HT_BBCFG_RSTCCA);
924 b43_phy_write(dev, B43_PHY_HT_BBCFG, tmp & ~B43_PHY_HT_BBCFG_RSTCCA);
925 b43_phy_force_clock(dev, false);
926
927 b43_mac_phy_clock_set(dev, true);
928
929 b43_phy_ht_pa_override(dev, false);
930 b43_phy_ht_force_rf_sequence(dev, B43_PHY_HT_RF_SEQ_TRIG_RX2TX);
931 b43_phy_ht_force_rf_sequence(dev, B43_PHY_HT_RF_SEQ_TRIG_RST2RX);
932 b43_phy_ht_pa_override(dev, true);
933
934 /* TODO: Should we restore it? Or store it in global PHY info? */
935 b43_phy_ht_classifier(dev, 0, 0);
936 b43_phy_ht_read_clip_detection(dev, clip_state);
937
938 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
939 b43_phy_ht_bphy_init(dev);
940
941 b43_httab_write_bulk(dev, B43_HTTAB32(0x1a, 0xc0),
942 B43_HTTAB_1A_C0_LATE_SIZE, b43_httab_0x1a_0xc0_late);
943
944 saved_tx_pwr_ctl = phy_ht->tx_pwr_ctl;
945 b43_phy_ht_tx_power_fix(dev);
946 b43_phy_ht_tx_power_ctl(dev, false);
947 b43_phy_ht_tx_power_ctl_idle_tssi(dev);
948 b43_phy_ht_tx_power_ctl_setup(dev);
949 b43_phy_ht_tx_power_ctl(dev, saved_tx_pwr_ctl);
950
951 return 0;
952 }
953
954 static void b43_phy_ht_op_free(struct b43_wldev *dev)
955 {
956 struct b43_phy *phy = &dev->phy;
957 struct b43_phy_ht *phy_ht = phy->ht;
958
959 kfree(phy_ht);
960 phy->ht = NULL;
961 }
962
963 /* http://bcm-v4.sipsolutions.net/802.11/Radio/Switch%20Radio */
964 static void b43_phy_ht_op_software_rfkill(struct b43_wldev *dev,
965 bool blocked)
966 {
967 if (b43_read32(dev, B43_MMIO_MACCTL) & B43_MACCTL_ENABLED)
968 b43err(dev->wl, "MAC not suspended\n");
969
970 /* In the following PHY ops we copy wl's dummy behaviour.
971 * TODO: Find out if reads (currently hidden in masks/masksets) are
972 * needed and replace following ops with just writes or w&r.
973 * Note: B43_PHY_HT_RF_CTL1 register is tricky, wrong operation can
974 * cause delayed (!) machine lock up. */
975 if (blocked) {
976 b43_phy_mask(dev, B43_PHY_HT_RF_CTL1, 0);
977 } else {
978 b43_phy_mask(dev, B43_PHY_HT_RF_CTL1, 0);
979 b43_phy_maskset(dev, B43_PHY_HT_RF_CTL1, 0, 0x1);
980 b43_phy_mask(dev, B43_PHY_HT_RF_CTL1, 0);
981 b43_phy_maskset(dev, B43_PHY_HT_RF_CTL1, 0, 0x2);
982
983 if (dev->phy.radio_ver == 0x2059)
984 b43_radio_2059_init(dev);
985 else
986 B43_WARN_ON(1);
987
988 b43_switch_channel(dev, dev->phy.channel);
989 }
990 }
991
992 static void b43_phy_ht_op_switch_analog(struct b43_wldev *dev, bool on)
993 {
994 if (on) {
995 b43_phy_write(dev, B43_PHY_HT_AFE_C1, 0x00cd);
996 b43_phy_write(dev, B43_PHY_HT_AFE_C1_OVER, 0x0000);
997 b43_phy_write(dev, B43_PHY_HT_AFE_C2, 0x00cd);
998 b43_phy_write(dev, B43_PHY_HT_AFE_C2_OVER, 0x0000);
999 b43_phy_write(dev, B43_PHY_HT_AFE_C3, 0x00cd);
1000 b43_phy_write(dev, B43_PHY_HT_AFE_C3_OVER, 0x0000);
1001 } else {
1002 b43_phy_write(dev, B43_PHY_HT_AFE_C1_OVER, 0x07ff);
1003 b43_phy_write(dev, B43_PHY_HT_AFE_C1, 0x00fd);
1004 b43_phy_write(dev, B43_PHY_HT_AFE_C2_OVER, 0x07ff);
1005 b43_phy_write(dev, B43_PHY_HT_AFE_C2, 0x00fd);
1006 b43_phy_write(dev, B43_PHY_HT_AFE_C3_OVER, 0x07ff);
1007 b43_phy_write(dev, B43_PHY_HT_AFE_C3, 0x00fd);
1008 }
1009 }
1010
1011 static int b43_phy_ht_op_switch_channel(struct b43_wldev *dev,
1012 unsigned int new_channel)
1013 {
1014 struct ieee80211_channel *channel = dev->wl->hw->conf.chandef.chan;
1015 enum nl80211_channel_type channel_type =
1016 cfg80211_get_chandef_type(&dev->wl->hw->conf.chandef);
1017
1018 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
1019 if ((new_channel < 1) || (new_channel > 14))
1020 return -EINVAL;
1021 } else {
1022 return -EINVAL;
1023 }
1024
1025 return b43_phy_ht_set_channel(dev, channel, channel_type);
1026 }
1027
1028 static unsigned int b43_phy_ht_op_get_default_chan(struct b43_wldev *dev)
1029 {
1030 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
1031 return 11;
1032 return 36;
1033 }
1034
1035 /**************************************************
1036 * R/W ops.
1037 **************************************************/
1038
1039 static u16 b43_phy_ht_op_read(struct b43_wldev *dev, u16 reg)
1040 {
1041 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
1042 return b43_read16(dev, B43_MMIO_PHY_DATA);
1043 }
1044
1045 static void b43_phy_ht_op_write(struct b43_wldev *dev, u16 reg, u16 value)
1046 {
1047 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
1048 b43_write16(dev, B43_MMIO_PHY_DATA, value);
1049 }
1050
1051 static void b43_phy_ht_op_maskset(struct b43_wldev *dev, u16 reg, u16 mask,
1052 u16 set)
1053 {
1054 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
1055 b43_write16(dev, B43_MMIO_PHY_DATA,
1056 (b43_read16(dev, B43_MMIO_PHY_DATA) & mask) | set);
1057 }
1058
1059 static u16 b43_phy_ht_op_radio_read(struct b43_wldev *dev, u16 reg)
1060 {
1061 /* HT-PHY needs 0x200 for read access */
1062 reg |= 0x200;
1063
1064 b43_write16(dev, B43_MMIO_RADIO24_CONTROL, reg);
1065 return b43_read16(dev, B43_MMIO_RADIO24_DATA);
1066 }
1067
1068 static void b43_phy_ht_op_radio_write(struct b43_wldev *dev, u16 reg,
1069 u16 value)
1070 {
1071 b43_write16(dev, B43_MMIO_RADIO24_CONTROL, reg);
1072 b43_write16(dev, B43_MMIO_RADIO24_DATA, value);
1073 }
1074
1075 static enum b43_txpwr_result
1076 b43_phy_ht_op_recalc_txpower(struct b43_wldev *dev, bool ignore_tssi)
1077 {
1078 return B43_TXPWR_RES_DONE;
1079 }
1080
1081 static void b43_phy_ht_op_adjust_txpower(struct b43_wldev *dev)
1082 {
1083 }
1084
1085 /**************************************************
1086 * PHY ops struct.
1087 **************************************************/
1088
1089 const struct b43_phy_operations b43_phyops_ht = {
1090 .allocate = b43_phy_ht_op_allocate,
1091 .free = b43_phy_ht_op_free,
1092 .prepare_structs = b43_phy_ht_op_prepare_structs,
1093 .init = b43_phy_ht_op_init,
1094 .phy_read = b43_phy_ht_op_read,
1095 .phy_write = b43_phy_ht_op_write,
1096 .phy_maskset = b43_phy_ht_op_maskset,
1097 .radio_read = b43_phy_ht_op_radio_read,
1098 .radio_write = b43_phy_ht_op_radio_write,
1099 .software_rfkill = b43_phy_ht_op_software_rfkill,
1100 .switch_analog = b43_phy_ht_op_switch_analog,
1101 .switch_channel = b43_phy_ht_op_switch_channel,
1102 .get_default_chan = b43_phy_ht_op_get_default_chan,
1103 .recalc_txpower = b43_phy_ht_op_recalc_txpower,
1104 .adjust_txpower = b43_phy_ht_op_adjust_txpower,
1105 };
Linux kernel - Deliverables
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