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4d14102821c8ef2e02b51bb7653c9b9153221761
[deliverable/linux.git] / drivers / net / wireless / b43 / phy_lp.c
1 /*
2
3 Broadcom B43 wireless driver
4 IEEE 802.11g LP-PHY driver
5
6 Copyright (c) 2008-2009 Michael Buesch <mb@bu3sch.de>
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING. If not, write to
20 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
21 Boston, MA 02110-1301, USA.
22
23 */
24
25 #include "b43.h"
26 #include "main.h"
27 #include "phy_lp.h"
28 #include "phy_common.h"
29 #include "tables_lpphy.h"
30
31
32 static inline u16 channel2freq_lp(u8 channel)
33 {
34 if (channel < 14)
35 return (2407 + 5 * channel);
36 else if (channel == 14)
37 return 2484;
38 else if (channel < 184)
39 return (5000 + 5 * channel);
40 else
41 return (4000 + 5 * channel);
42 }
43
44 static unsigned int b43_lpphy_op_get_default_chan(struct b43_wldev *dev)
45 {
46 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
47 return 1;
48 return 36;
49 }
50
51 static int b43_lpphy_op_allocate(struct b43_wldev *dev)
52 {
53 struct b43_phy_lp *lpphy;
54
55 lpphy = kzalloc(sizeof(*lpphy), GFP_KERNEL);
56 if (!lpphy)
57 return -ENOMEM;
58 dev->phy.lp = lpphy;
59
60 return 0;
61 }
62
63 static void b43_lpphy_op_prepare_structs(struct b43_wldev *dev)
64 {
65 struct b43_phy *phy = &dev->phy;
66 struct b43_phy_lp *lpphy = phy->lp;
67
68 memset(lpphy, 0, sizeof(*lpphy));
69
70 //TODO
71 }
72
73 static void b43_lpphy_op_free(struct b43_wldev *dev)
74 {
75 struct b43_phy_lp *lpphy = dev->phy.lp;
76
77 kfree(lpphy);
78 dev->phy.lp = NULL;
79 }
80
81 static void lpphy_read_band_sprom(struct b43_wldev *dev)
82 {
83 struct b43_phy_lp *lpphy = dev->phy.lp;
84 struct ssb_bus *bus = dev->dev->bus;
85 u16 cckpo, maxpwr;
86 u32 ofdmpo;
87 int i;
88
89 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
90 lpphy->tx_isolation_med_band = bus->sprom.tri2g;
91 lpphy->bx_arch = bus->sprom.bxa2g;
92 lpphy->rx_pwr_offset = bus->sprom.rxpo2g;
93 lpphy->rssi_vf = bus->sprom.rssismf2g;
94 lpphy->rssi_vc = bus->sprom.rssismc2g;
95 lpphy->rssi_gs = bus->sprom.rssisav2g;
96 lpphy->txpa[0] = bus->sprom.pa0b0;
97 lpphy->txpa[1] = bus->sprom.pa0b1;
98 lpphy->txpa[2] = bus->sprom.pa0b2;
99 maxpwr = bus->sprom.maxpwr_bg;
100 lpphy->max_tx_pwr_med_band = maxpwr;
101 cckpo = bus->sprom.cck2gpo;
102 ofdmpo = bus->sprom.ofdm2gpo;
103 if (cckpo) {
104 for (i = 0; i < 4; i++) {
105 lpphy->tx_max_rate[i] =
106 maxpwr - (ofdmpo & 0xF) * 2;
107 ofdmpo >>= 4;
108 }
109 ofdmpo = bus->sprom.ofdm2gpo;
110 for (i = 4; i < 15; i++) {
111 lpphy->tx_max_rate[i] =
112 maxpwr - (ofdmpo & 0xF) * 2;
113 ofdmpo >>= 4;
114 }
115 } else {
116 ofdmpo &= 0xFF;
117 for (i = 0; i < 4; i++)
118 lpphy->tx_max_rate[i] = maxpwr;
119 for (i = 4; i < 15; i++)
120 lpphy->tx_max_rate[i] = maxpwr - ofdmpo;
121 }
122 } else { /* 5GHz */
123 lpphy->tx_isolation_low_band = bus->sprom.tri5gl;
124 lpphy->tx_isolation_med_band = bus->sprom.tri5g;
125 lpphy->tx_isolation_hi_band = bus->sprom.tri5gh;
126 lpphy->bx_arch = bus->sprom.bxa5g;
127 lpphy->rx_pwr_offset = bus->sprom.rxpo5g;
128 lpphy->rssi_vf = bus->sprom.rssismf5g;
129 lpphy->rssi_vc = bus->sprom.rssismc5g;
130 lpphy->rssi_gs = bus->sprom.rssisav5g;
131 lpphy->txpa[0] = bus->sprom.pa1b0;
132 lpphy->txpa[1] = bus->sprom.pa1b1;
133 lpphy->txpa[2] = bus->sprom.pa1b2;
134 lpphy->txpal[0] = bus->sprom.pa1lob0;
135 lpphy->txpal[1] = bus->sprom.pa1lob1;
136 lpphy->txpal[2] = bus->sprom.pa1lob2;
137 lpphy->txpah[0] = bus->sprom.pa1hib0;
138 lpphy->txpah[1] = bus->sprom.pa1hib1;
139 lpphy->txpah[2] = bus->sprom.pa1hib2;
140 maxpwr = bus->sprom.maxpwr_al;
141 ofdmpo = bus->sprom.ofdm5glpo;
142 lpphy->max_tx_pwr_low_band = maxpwr;
143 for (i = 4; i < 12; i++) {
144 lpphy->tx_max_ratel[i] = maxpwr - (ofdmpo & 0xF) * 2;
145 ofdmpo >>= 4;
146 }
147 maxpwr = bus->sprom.maxpwr_a;
148 ofdmpo = bus->sprom.ofdm5gpo;
149 lpphy->max_tx_pwr_med_band = maxpwr;
150 for (i = 4; i < 12; i++) {
151 lpphy->tx_max_rate[i] = maxpwr - (ofdmpo & 0xF) * 2;
152 ofdmpo >>= 4;
153 }
154 maxpwr = bus->sprom.maxpwr_ah;
155 ofdmpo = bus->sprom.ofdm5ghpo;
156 lpphy->max_tx_pwr_hi_band = maxpwr;
157 for (i = 4; i < 12; i++) {
158 lpphy->tx_max_rateh[i] = maxpwr - (ofdmpo & 0xF) * 2;
159 ofdmpo >>= 4;
160 }
161 }
162 }
163
164 static void lpphy_adjust_gain_table(struct b43_wldev *dev, u32 freq)
165 {
166 struct b43_phy_lp *lpphy = dev->phy.lp;
167 u16 temp[3];
168 u16 isolation;
169
170 B43_WARN_ON(dev->phy.rev >= 2);
171
172 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
173 isolation = lpphy->tx_isolation_med_band;
174 else if (freq <= 5320)
175 isolation = lpphy->tx_isolation_low_band;
176 else if (freq <= 5700)
177 isolation = lpphy->tx_isolation_med_band;
178 else
179 isolation = lpphy->tx_isolation_hi_band;
180
181 temp[0] = ((isolation - 26) / 12) << 12;
182 temp[1] = temp[0] + 0x1000;
183 temp[2] = temp[0] + 0x2000;
184
185 b43_lptab_write_bulk(dev, B43_LPTAB16(12, 0), 3, temp);
186 b43_lptab_write_bulk(dev, B43_LPTAB16(13, 0), 3, temp);
187 }
188
189 static void lpphy_table_init(struct b43_wldev *dev)
190 {
191 u32 freq = channel2freq_lp(b43_lpphy_op_get_default_chan(dev));
192
193 if (dev->phy.rev < 2)
194 lpphy_rev0_1_table_init(dev);
195 else
196 lpphy_rev2plus_table_init(dev);
197
198 lpphy_init_tx_gain_table(dev);
199
200 if (dev->phy.rev < 2)
201 lpphy_adjust_gain_table(dev, freq);
202 }
203
204 static void lpphy_baseband_rev0_1_init(struct b43_wldev *dev)
205 {
206 struct ssb_bus *bus = dev->dev->bus;
207 struct b43_phy_lp *lpphy = dev->phy.lp;
208 u16 tmp, tmp2;
209
210 b43_phy_mask(dev, B43_LPPHY_AFE_DAC_CTL, 0xF7FF);
211 b43_phy_write(dev, B43_LPPHY_AFE_CTL, 0);
212 b43_phy_write(dev, B43_LPPHY_AFE_CTL_OVR, 0);
213 b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_0, 0);
214 b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_2, 0);
215 b43_phy_set(dev, B43_LPPHY_AFE_DAC_CTL, 0x0004);
216 b43_phy_maskset(dev, B43_LPPHY_OFDMSYNCTHRESH0, 0xFF00, 0x0078);
217 b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0x83FF, 0x5800);
218 b43_phy_write(dev, B43_LPPHY_ADC_COMPENSATION_CTL, 0x0016);
219 b43_phy_maskset(dev, B43_LPPHY_AFE_ADC_CTL_0, 0xFFF8, 0x0004);
220 b43_phy_maskset(dev, B43_LPPHY_VERYLOWGAINDB, 0x00FF, 0x5400);
221 b43_phy_maskset(dev, B43_LPPHY_HIGAINDB, 0x00FF, 0x2400);
222 b43_phy_maskset(dev, B43_LPPHY_LOWGAINDB, 0x00FF, 0x2100);
223 b43_phy_maskset(dev, B43_LPPHY_VERYLOWGAINDB, 0xFF00, 0x0006);
224 b43_phy_mask(dev, B43_LPPHY_RX_RADIO_CTL, 0xFFFE);
225 b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0xFFE0, 0x0005);
226 b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0xFC10, 0x0180);
227 b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0x83FF, 0x3800);
228 b43_phy_maskset(dev, B43_LPPHY_GAINDIRECTMISMATCH, 0xFFF0, 0x0005);
229 b43_phy_maskset(dev, B43_LPPHY_GAIN_MISMATCH_LIMIT, 0xFFC0, 0x001A);
230 b43_phy_maskset(dev, B43_LPPHY_CRS_ED_THRESH, 0xFF00, 0x00B3);
231 b43_phy_maskset(dev, B43_LPPHY_CRS_ED_THRESH, 0x00FF, 0xAD00);
232 b43_phy_maskset(dev, B43_LPPHY_INPUT_PWRDB,
233 0xFF00, lpphy->rx_pwr_offset);
234 if ((bus->sprom.boardflags_lo & B43_BFL_FEM) &&
235 ((b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ||
236 (bus->sprom.boardflags_hi & B43_BFH_PAREF))) {
237 /* TODO:
238 * Set the LDO voltage to 0x0028 - FIXME: What is this?
239 * Call sb_pmu_set_ldo_voltage with 4 and the LDO voltage
240 * as arguments
241 * Call sb_pmu_paref_ldo_enable with argument TRUE
242 */
243 if (dev->phy.rev == 0) {
244 b43_phy_maskset(dev, B43_LPPHY_LP_RF_SIGNAL_LUT,
245 0xFFCF, 0x0010);
246 }
247 b43_lptab_write(dev, B43_LPTAB16(11, 7), 60);
248 } else {
249 //TODO: Call ssb_pmu_paref_ldo_enable with argument FALSE
250 b43_phy_maskset(dev, B43_LPPHY_LP_RF_SIGNAL_LUT,
251 0xFFCF, 0x0020);
252 b43_lptab_write(dev, B43_LPTAB16(11, 7), 100);
253 }
254 tmp = lpphy->rssi_vf | lpphy->rssi_vc << 4 | 0xA000;
255 b43_phy_write(dev, B43_LPPHY_AFE_RSSI_CTL_0, tmp);
256 if (bus->sprom.boardflags_hi & B43_BFH_RSSIINV)
257 b43_phy_maskset(dev, B43_LPPHY_AFE_RSSI_CTL_1, 0xF000, 0x0AAA);
258 else
259 b43_phy_maskset(dev, B43_LPPHY_AFE_RSSI_CTL_1, 0xF000, 0x02AA);
260 b43_lptab_write(dev, B43_LPTAB16(11, 1), 24);
261 b43_phy_maskset(dev, B43_LPPHY_RX_RADIO_CTL,
262 0xFFF9, (lpphy->bx_arch << 1));
263 if (dev->phy.rev == 1 &&
264 (bus->sprom.boardflags_hi & B43_BFH_FEM_BT)) {
265 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xFFC0, 0x000A);
266 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0x3F00, 0x0900);
267 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xFFC0, 0x000A);
268 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xC0FF, 0x0B00);
269 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xFFC0, 0x000A);
270 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xC0FF, 0x0400);
271 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xFFC0, 0x000A);
272 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xC0FF, 0x0B00);
273 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_5, 0xFFC0, 0x000A);
274 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_5, 0xC0FF, 0x0900);
275 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_6, 0xFFC0, 0x000A);
276 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_6, 0xC0FF, 0x0B00);
277 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_7, 0xFFC0, 0x000A);
278 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_7, 0xC0FF, 0x0900);
279 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_8, 0xFFC0, 0x000A);
280 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_8, 0xC0FF, 0x0B00);
281 } else if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ ||
282 (bus->boardinfo.type == 0x048A) || ((dev->phy.rev == 0) &&
283 (bus->sprom.boardflags_lo & B43_BFL_FEM))) {
284 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xFFC0, 0x0001);
285 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xC0FF, 0x0400);
286 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xFFC0, 0x0001);
287 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xC0FF, 0x0500);
288 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xFFC0, 0x0002);
289 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xC0FF, 0x0800);
290 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xFFC0, 0x0002);
291 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xC0FF, 0x0A00);
292 } else if (dev->phy.rev == 1 ||
293 (bus->sprom.boardflags_lo & B43_BFL_FEM)) {
294 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xFFC0, 0x0004);
295 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xC0FF, 0x0800);
296 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xFFC0, 0x0004);
297 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xC0FF, 0x0C00);
298 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xFFC0, 0x0002);
299 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xC0FF, 0x0100);
300 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xFFC0, 0x0002);
301 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xC0FF, 0x0300);
302 } else {
303 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xFFC0, 0x000A);
304 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xC0FF, 0x0900);
305 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xFFC0, 0x000A);
306 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xC0FF, 0x0B00);
307 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xFFC0, 0x0006);
308 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xC0FF, 0x0500);
309 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xFFC0, 0x0006);
310 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xC0FF, 0x0700);
311 }
312 if (dev->phy.rev == 1 && (bus->sprom.boardflags_hi & B43_BFH_PAREF)) {
313 b43_phy_copy(dev, B43_LPPHY_TR_LOOKUP_5, B43_LPPHY_TR_LOOKUP_1);
314 b43_phy_copy(dev, B43_LPPHY_TR_LOOKUP_6, B43_LPPHY_TR_LOOKUP_2);
315 b43_phy_copy(dev, B43_LPPHY_TR_LOOKUP_7, B43_LPPHY_TR_LOOKUP_3);
316 b43_phy_copy(dev, B43_LPPHY_TR_LOOKUP_8, B43_LPPHY_TR_LOOKUP_4);
317 }
318 if ((bus->sprom.boardflags_hi & B43_BFH_FEM_BT) &&
319 (bus->chip_id == 0x5354) &&
320 (bus->chip_package == SSB_CHIPPACK_BCM4712S)) {
321 b43_phy_set(dev, B43_LPPHY_CRSGAIN_CTL, 0x0006);
322 b43_phy_write(dev, B43_LPPHY_GPIO_SELECT, 0x0005);
323 b43_phy_write(dev, B43_LPPHY_GPIO_OUTEN, 0xFFFF);
324 //FIXME the Broadcom driver caches & delays this HF write!
325 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_PR45960W);
326 }
327 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
328 b43_phy_set(dev, B43_LPPHY_LP_PHY_CTL, 0x8000);
329 b43_phy_set(dev, B43_LPPHY_CRSGAIN_CTL, 0x0040);
330 b43_phy_maskset(dev, B43_LPPHY_MINPWR_LEVEL, 0x00FF, 0xA400);
331 b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL, 0xF0FF, 0x0B00);
332 b43_phy_maskset(dev, B43_LPPHY_SYNCPEAKCNT, 0xFFF8, 0x0007);
333 b43_phy_maskset(dev, B43_LPPHY_DSSS_CONFIRM_CNT, 0xFFF8, 0x0003);
334 b43_phy_maskset(dev, B43_LPPHY_DSSS_CONFIRM_CNT, 0xFFC7, 0x0020);
335 b43_phy_mask(dev, B43_LPPHY_IDLEAFTERPKTRXTO, 0x00FF);
336 } else { /* 5GHz */
337 b43_phy_mask(dev, B43_LPPHY_LP_PHY_CTL, 0x7FFF);
338 b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, 0xFFBF);
339 }
340 if (dev->phy.rev == 1) {
341 tmp = b43_phy_read(dev, B43_LPPHY_CLIPCTRTHRESH);
342 tmp2 = (tmp & 0x03E0) >> 5;
343 tmp2 |= tmp << 5;
344 b43_phy_write(dev, B43_LPPHY_4C3, tmp2);
345 tmp = b43_phy_read(dev, B43_LPPHY_OFDMSYNCTHRESH0);
346 tmp2 = (tmp & 0x1F00) >> 8;
347 tmp2 |= tmp << 5;
348 b43_phy_write(dev, B43_LPPHY_4C4, tmp2);
349 tmp = b43_phy_read(dev, B43_LPPHY_VERYLOWGAINDB);
350 tmp2 = tmp & 0x00FF;
351 tmp2 |= tmp << 8;
352 b43_phy_write(dev, B43_LPPHY_4C5, tmp2);
353 }
354 }
355
356 static void lpphy_save_dig_flt_state(struct b43_wldev *dev)
357 {
358 static const u16 addr[] = {
359 B43_PHY_OFDM(0xC1),
360 B43_PHY_OFDM(0xC2),
361 B43_PHY_OFDM(0xC3),
362 B43_PHY_OFDM(0xC4),
363 B43_PHY_OFDM(0xC5),
364 B43_PHY_OFDM(0xC6),
365 B43_PHY_OFDM(0xC7),
366 B43_PHY_OFDM(0xC8),
367 B43_PHY_OFDM(0xCF),
368 };
369
370 static const u16 coefs[] = {
371 0xDE5E, 0xE832, 0xE331, 0x4D26,
372 0x0026, 0x1420, 0x0020, 0xFE08,
373 0x0008,
374 };
375
376 struct b43_phy_lp *lpphy = dev->phy.lp;
377 int i;
378
379 for (i = 0; i < ARRAY_SIZE(addr); i++) {
380 lpphy->dig_flt_state[i] = b43_phy_read(dev, addr[i]);
381 b43_phy_write(dev, addr[i], coefs[i]);
382 }
383 }
384
385 static void lpphy_restore_dig_flt_state(struct b43_wldev *dev)
386 {
387 static const u16 addr[] = {
388 B43_PHY_OFDM(0xC1),
389 B43_PHY_OFDM(0xC2),
390 B43_PHY_OFDM(0xC3),
391 B43_PHY_OFDM(0xC4),
392 B43_PHY_OFDM(0xC5),
393 B43_PHY_OFDM(0xC6),
394 B43_PHY_OFDM(0xC7),
395 B43_PHY_OFDM(0xC8),
396 B43_PHY_OFDM(0xCF),
397 };
398
399 struct b43_phy_lp *lpphy = dev->phy.lp;
400 int i;
401
402 for (i = 0; i < ARRAY_SIZE(addr); i++)
403 b43_phy_write(dev, addr[i], lpphy->dig_flt_state[i]);
404 }
405
406 static void lpphy_baseband_rev2plus_init(struct b43_wldev *dev)
407 {
408 struct ssb_bus *bus = dev->dev->bus;
409 struct b43_phy_lp *lpphy = dev->phy.lp;
410
411 b43_phy_write(dev, B43_LPPHY_AFE_DAC_CTL, 0x50);
412 b43_phy_write(dev, B43_LPPHY_AFE_CTL, 0x8800);
413 b43_phy_write(dev, B43_LPPHY_AFE_CTL_OVR, 0);
414 b43_phy_write(dev, B43_LPPHY_AFE_CTL_OVRVAL, 0);
415 b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_0, 0);
416 b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_2, 0);
417 b43_phy_write(dev, B43_PHY_OFDM(0xF9), 0);
418 b43_phy_write(dev, B43_LPPHY_TR_LOOKUP_1, 0);
419 b43_phy_set(dev, B43_LPPHY_ADC_COMPENSATION_CTL, 0x10);
420 b43_phy_maskset(dev, B43_LPPHY_OFDMSYNCTHRESH0, 0xFF00, 0xB4);
421 b43_phy_maskset(dev, B43_LPPHY_DCOFFSETTRANSIENT, 0xF8FF, 0x200);
422 b43_phy_maskset(dev, B43_LPPHY_DCOFFSETTRANSIENT, 0xFF00, 0x7F);
423 b43_phy_maskset(dev, B43_LPPHY_GAINDIRECTMISMATCH, 0xFF0F, 0x40);
424 b43_phy_maskset(dev, B43_LPPHY_PREAMBLECONFIRMTO, 0xFF00, 0x2);
425 b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, ~0x4000);
426 b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, ~0x2000);
427 b43_phy_set(dev, B43_PHY_OFDM(0x10A), 0x1);
428 if (bus->boardinfo.rev >= 0x18) {
429 b43_lptab_write(dev, B43_LPTAB32(17, 65), 0xEC);
430 b43_phy_maskset(dev, B43_PHY_OFDM(0x10A), 0xFF01, 0x14);
431 } else {
432 b43_phy_maskset(dev, B43_PHY_OFDM(0x10A), 0xFF01, 0x10);
433 }
434 b43_phy_maskset(dev, B43_PHY_OFDM(0xDF), 0xFF00, 0xF4);
435 b43_phy_maskset(dev, B43_PHY_OFDM(0xDF), 0x00FF, 0xF100);
436 b43_phy_write(dev, B43_LPPHY_CLIPTHRESH, 0x48);
437 b43_phy_maskset(dev, B43_LPPHY_HIGAINDB, 0xFF00, 0x46);
438 b43_phy_maskset(dev, B43_PHY_OFDM(0xE4), 0xFF00, 0x10);
439 b43_phy_maskset(dev, B43_LPPHY_PWR_THRESH1, 0xFFF0, 0x9);
440 b43_phy_mask(dev, B43_LPPHY_GAINDIRECTMISMATCH, ~0xF);
441 b43_phy_maskset(dev, B43_LPPHY_VERYLOWGAINDB, 0x00FF, 0x5500);
442 b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0xFC1F, 0xA0);
443 b43_phy_maskset(dev, B43_LPPHY_GAINDIRECTMISMATCH, 0xE0FF, 0x300);
444 b43_phy_maskset(dev, B43_LPPHY_HIGAINDB, 0x00FF, 0x2A00);
445 if ((bus->chip_id == 0x4325) && (bus->chip_rev == 0)) {
446 b43_phy_maskset(dev, B43_LPPHY_LOWGAINDB, 0x00FF, 0x2100);
447 b43_phy_maskset(dev, B43_LPPHY_VERYLOWGAINDB, 0xFF00, 0xA);
448 } else {
449 b43_phy_maskset(dev, B43_LPPHY_LOWGAINDB, 0x00FF, 0x1E00);
450 b43_phy_maskset(dev, B43_LPPHY_VERYLOWGAINDB, 0xFF00, 0xD);
451 }
452 b43_phy_maskset(dev, B43_PHY_OFDM(0xFE), 0xFFE0, 0x1F);
453 b43_phy_maskset(dev, B43_PHY_OFDM(0xFF), 0xFFE0, 0xC);
454 b43_phy_maskset(dev, B43_PHY_OFDM(0x100), 0xFF00, 0x19);
455 b43_phy_maskset(dev, B43_PHY_OFDM(0xFF), 0x03FF, 0x3C00);
456 b43_phy_maskset(dev, B43_PHY_OFDM(0xFE), 0xFC1F, 0x3E0);
457 b43_phy_maskset(dev, B43_PHY_OFDM(0xFF), 0xFFE0, 0xC);
458 b43_phy_maskset(dev, B43_PHY_OFDM(0x100), 0x00FF, 0x1900);
459 b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0x83FF, 0x5800);
460 b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0xFFE0, 0x12);
461 b43_phy_maskset(dev, B43_LPPHY_GAINMISMATCH, 0x0FFF, 0x9000);
462
463 if ((bus->chip_id == 0x4325) && (bus->chip_rev == 0)) {
464 b43_lptab_write(dev, B43_LPTAB16(0x08, 0x14), 0);
465 b43_lptab_write(dev, B43_LPTAB16(0x08, 0x12), 0x40);
466 }
467
468 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
469 b43_phy_set(dev, B43_LPPHY_CRSGAIN_CTL, 0x40);
470 b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL, 0xF0FF, 0xB00);
471 b43_phy_maskset(dev, B43_LPPHY_SYNCPEAKCNT, 0xFFF8, 0x6);
472 b43_phy_maskset(dev, B43_LPPHY_MINPWR_LEVEL, 0x00FF, 0x9D00);
473 b43_phy_maskset(dev, B43_LPPHY_MINPWR_LEVEL, 0xFF00, 0xA1);
474 b43_phy_mask(dev, B43_LPPHY_IDLEAFTERPKTRXTO, 0x00FF);
475 } else /* 5GHz */
476 b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, ~0x40);
477
478 b43_phy_maskset(dev, B43_LPPHY_CRS_ED_THRESH, 0xFF00, 0xB3);
479 b43_phy_maskset(dev, B43_LPPHY_CRS_ED_THRESH, 0x00FF, 0xAD00);
480 b43_phy_maskset(dev, B43_LPPHY_INPUT_PWRDB, 0xFF00, lpphy->rx_pwr_offset);
481 b43_phy_set(dev, B43_LPPHY_RESET_CTL, 0x44);
482 b43_phy_write(dev, B43_LPPHY_RESET_CTL, 0x80);
483 b43_phy_write(dev, B43_LPPHY_AFE_RSSI_CTL_0, 0xA954);
484 b43_phy_write(dev, B43_LPPHY_AFE_RSSI_CTL_1,
485 0x2000 | ((u16)lpphy->rssi_gs << 10) |
486 ((u16)lpphy->rssi_vc << 4) | lpphy->rssi_vf);
487
488 if ((bus->chip_id == 0x4325) && (bus->chip_rev == 0)) {
489 b43_phy_set(dev, B43_LPPHY_AFE_ADC_CTL_0, 0x1C);
490 b43_phy_maskset(dev, B43_LPPHY_AFE_CTL, 0x00FF, 0x8800);
491 b43_phy_maskset(dev, B43_LPPHY_AFE_ADC_CTL_1, 0xFC3C, 0x0400);
492 }
493
494 lpphy_save_dig_flt_state(dev);
495 }
496
497 static void lpphy_baseband_init(struct b43_wldev *dev)
498 {
499 lpphy_table_init(dev);
500 if (dev->phy.rev >= 2)
501 lpphy_baseband_rev2plus_init(dev);
502 else
503 lpphy_baseband_rev0_1_init(dev);
504 }
505
506 struct b2062_freqdata {
507 u16 freq;
508 u8 data[6];
509 };
510
511 /* Initialize the 2062 radio. */
512 static void lpphy_2062_init(struct b43_wldev *dev)
513 {
514 struct b43_phy_lp *lpphy = dev->phy.lp;
515 struct ssb_bus *bus = dev->dev->bus;
516 u32 crystalfreq, tmp, ref;
517 unsigned int i;
518 const struct b2062_freqdata *fd = NULL;
519
520 static const struct b2062_freqdata freqdata_tab[] = {
521 { .freq = 12000, .data[0] = 6, .data[1] = 6, .data[2] = 6,
522 .data[3] = 6, .data[4] = 10, .data[5] = 6, },
523 { .freq = 13000, .data[0] = 4, .data[1] = 4, .data[2] = 4,
524 .data[3] = 4, .data[4] = 11, .data[5] = 7, },
525 { .freq = 14400, .data[0] = 3, .data[1] = 3, .data[2] = 3,
526 .data[3] = 3, .data[4] = 12, .data[5] = 7, },
527 { .freq = 16200, .data[0] = 3, .data[1] = 3, .data[2] = 3,
528 .data[3] = 3, .data[4] = 13, .data[5] = 8, },
529 { .freq = 18000, .data[0] = 2, .data[1] = 2, .data[2] = 2,
530 .data[3] = 2, .data[4] = 14, .data[5] = 8, },
531 { .freq = 19200, .data[0] = 1, .data[1] = 1, .data[2] = 1,
532 .data[3] = 1, .data[4] = 14, .data[5] = 9, },
533 };
534
535 b2062_upload_init_table(dev);
536
537 b43_radio_write(dev, B2062_N_TX_CTL3, 0);
538 b43_radio_write(dev, B2062_N_TX_CTL4, 0);
539 b43_radio_write(dev, B2062_N_TX_CTL5, 0);
540 b43_radio_write(dev, B2062_N_PDN_CTL0, 0x40);
541 b43_radio_write(dev, B2062_N_PDN_CTL0, 0);
542 b43_radio_write(dev, B2062_N_CALIB_TS, 0x10);
543 b43_radio_write(dev, B2062_N_CALIB_TS, 0);
544 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
545 b43_radio_set(dev, B2062_N_TSSI_CTL0, 0x1);
546 else
547 b43_radio_mask(dev, B2062_N_TSSI_CTL0, ~0x1);
548
549 /* Get the crystal freq, in Hz. */
550 crystalfreq = bus->chipco.pmu.crystalfreq * 1000;
551
552 B43_WARN_ON(!(bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU));
553 B43_WARN_ON(crystalfreq == 0);
554
555 if (crystalfreq <= 30000000) {
556 lpphy->pdiv = 1;
557 b43_radio_mask(dev, B2062_S_RFPLL_CTL1, 0xFFFB);
558 } else {
559 lpphy->pdiv = 2;
560 b43_radio_set(dev, B2062_S_RFPLL_CTL1, 0x4);
561 }
562
563 tmp = (((800000000 * lpphy->pdiv + crystalfreq) /
564 (2 * crystalfreq)) - 8) & 0xFF;
565 b43_radio_write(dev, B2062_S_RFPLL_CTL7, tmp);
566
567 tmp = (((100 * crystalfreq + 16000000 * lpphy->pdiv) /
568 (32000000 * lpphy->pdiv)) - 1) & 0xFF;
569 b43_radio_write(dev, B2062_S_RFPLL_CTL18, tmp);
570
571 tmp = (((2 * crystalfreq + 1000000 * lpphy->pdiv) /
572 (2000000 * lpphy->pdiv)) - 1) & 0xFF;
573 b43_radio_write(dev, B2062_S_RFPLL_CTL19, tmp);
574
575 ref = (1000 * lpphy->pdiv + 2 * crystalfreq) / (2000 * lpphy->pdiv);
576 ref &= 0xFFFF;
577 for (i = 0; i < ARRAY_SIZE(freqdata_tab); i++) {
578 if (ref < freqdata_tab[i].freq) {
579 fd = &freqdata_tab[i];
580 break;
581 }
582 }
583 if (!fd)
584 fd = &freqdata_tab[ARRAY_SIZE(freqdata_tab) - 1];
585 b43dbg(dev->wl, "b2062: Using crystal tab entry %u kHz.\n",
586 fd->freq); /* FIXME: Keep this printk until the code is fully debugged. */
587
588 b43_radio_write(dev, B2062_S_RFPLL_CTL8,
589 ((u16)(fd->data[1]) << 4) | fd->data[0]);
590 b43_radio_write(dev, B2062_S_RFPLL_CTL9,
591 ((u16)(fd->data[3]) << 4) | fd->data[2]);
592 b43_radio_write(dev, B2062_S_RFPLL_CTL10, fd->data[4]);
593 b43_radio_write(dev, B2062_S_RFPLL_CTL11, fd->data[5]);
594 }
595
596 /* Initialize the 2063 radio. */
597 static void lpphy_2063_init(struct b43_wldev *dev)
598 {
599 b2063_upload_init_table(dev);
600 b43_radio_write(dev, B2063_LOGEN_SP5, 0);
601 b43_radio_set(dev, B2063_COMM8, 0x38);
602 b43_radio_write(dev, B2063_REG_SP1, 0x56);
603 b43_radio_mask(dev, B2063_RX_BB_CTL2, ~0x2);
604 b43_radio_write(dev, B2063_PA_SP7, 0);
605 b43_radio_write(dev, B2063_TX_RF_SP6, 0x20);
606 b43_radio_write(dev, B2063_TX_RF_SP9, 0x40);
607 b43_radio_write(dev, B2063_PA_SP3, 0xa0);
608 b43_radio_write(dev, B2063_PA_SP4, 0xa0);
609 b43_radio_write(dev, B2063_PA_SP2, 0x18);
610 }
611
612 struct lpphy_stx_table_entry {
613 u16 phy_offset;
614 u16 phy_shift;
615 u16 rf_addr;
616 u16 rf_shift;
617 u16 mask;
618 };
619
620 static const struct lpphy_stx_table_entry lpphy_stx_table[] = {
621 { .phy_offset = 2, .phy_shift = 6, .rf_addr = 0x3d, .rf_shift = 3, .mask = 0x01, },
622 { .phy_offset = 1, .phy_shift = 12, .rf_addr = 0x4c, .rf_shift = 1, .mask = 0x01, },
623 { .phy_offset = 1, .phy_shift = 8, .rf_addr = 0x50, .rf_shift = 0, .mask = 0x7f, },
624 { .phy_offset = 0, .phy_shift = 8, .rf_addr = 0x44, .rf_shift = 0, .mask = 0xff, },
625 { .phy_offset = 1, .phy_shift = 0, .rf_addr = 0x4a, .rf_shift = 0, .mask = 0xff, },
626 { .phy_offset = 0, .phy_shift = 4, .rf_addr = 0x4d, .rf_shift = 0, .mask = 0xff, },
627 { .phy_offset = 1, .phy_shift = 4, .rf_addr = 0x4e, .rf_shift = 0, .mask = 0xff, },
628 { .phy_offset = 0, .phy_shift = 12, .rf_addr = 0x4f, .rf_shift = 0, .mask = 0x0f, },
629 { .phy_offset = 1, .phy_shift = 0, .rf_addr = 0x4f, .rf_shift = 4, .mask = 0x0f, },
630 { .phy_offset = 3, .phy_shift = 0, .rf_addr = 0x49, .rf_shift = 0, .mask = 0x0f, },
631 { .phy_offset = 4, .phy_shift = 3, .rf_addr = 0x46, .rf_shift = 4, .mask = 0x07, },
632 { .phy_offset = 3, .phy_shift = 15, .rf_addr = 0x46, .rf_shift = 0, .mask = 0x01, },
633 { .phy_offset = 4, .phy_shift = 0, .rf_addr = 0x46, .rf_shift = 1, .mask = 0x07, },
634 { .phy_offset = 3, .phy_shift = 8, .rf_addr = 0x48, .rf_shift = 4, .mask = 0x07, },
635 { .phy_offset = 3, .phy_shift = 11, .rf_addr = 0x48, .rf_shift = 0, .mask = 0x0f, },
636 { .phy_offset = 3, .phy_shift = 4, .rf_addr = 0x49, .rf_shift = 4, .mask = 0x0f, },
637 { .phy_offset = 2, .phy_shift = 15, .rf_addr = 0x45, .rf_shift = 0, .mask = 0x01, },
638 { .phy_offset = 5, .phy_shift = 13, .rf_addr = 0x52, .rf_shift = 4, .mask = 0x07, },
639 { .phy_offset = 6, .phy_shift = 0, .rf_addr = 0x52, .rf_shift = 7, .mask = 0x01, },
640 { .phy_offset = 5, .phy_shift = 3, .rf_addr = 0x41, .rf_shift = 5, .mask = 0x07, },
641 { .phy_offset = 5, .phy_shift = 6, .rf_addr = 0x41, .rf_shift = 0, .mask = 0x0f, },
642 { .phy_offset = 5, .phy_shift = 10, .rf_addr = 0x42, .rf_shift = 5, .mask = 0x07, },
643 { .phy_offset = 4, .phy_shift = 15, .rf_addr = 0x42, .rf_shift = 0, .mask = 0x01, },
644 { .phy_offset = 5, .phy_shift = 0, .rf_addr = 0x42, .rf_shift = 1, .mask = 0x07, },
645 { .phy_offset = 4, .phy_shift = 11, .rf_addr = 0x43, .rf_shift = 4, .mask = 0x0f, },
646 { .phy_offset = 4, .phy_shift = 7, .rf_addr = 0x43, .rf_shift = 0, .mask = 0x0f, },
647 { .phy_offset = 4, .phy_shift = 6, .rf_addr = 0x45, .rf_shift = 1, .mask = 0x01, },
648 { .phy_offset = 2, .phy_shift = 7, .rf_addr = 0x40, .rf_shift = 4, .mask = 0x0f, },
649 { .phy_offset = 2, .phy_shift = 11, .rf_addr = 0x40, .rf_shift = 0, .mask = 0x0f, },
650 };
651
652 static void lpphy_sync_stx(struct b43_wldev *dev)
653 {
654 const struct lpphy_stx_table_entry *e;
655 unsigned int i;
656 u16 tmp;
657
658 for (i = 0; i < ARRAY_SIZE(lpphy_stx_table); i++) {
659 e = &lpphy_stx_table[i];
660 tmp = b43_radio_read(dev, e->rf_addr);
661 tmp >>= e->rf_shift;
662 tmp <<= e->phy_shift;
663 b43_phy_maskset(dev, B43_PHY_OFDM(0xF2 + e->phy_offset),
664 ~(e->mask << e->phy_shift), tmp);
665 }
666 }
667
668 static void lpphy_radio_init(struct b43_wldev *dev)
669 {
670 /* The radio is attached through the 4wire bus. */
671 b43_phy_set(dev, B43_LPPHY_FOURWIRE_CTL, 0x2);
672 udelay(1);
673 b43_phy_mask(dev, B43_LPPHY_FOURWIRE_CTL, 0xFFFD);
674 udelay(1);
675
676 if (dev->phy.radio_ver == 0x2062) {
677 lpphy_2062_init(dev);
678 } else {
679 lpphy_2063_init(dev);
680 lpphy_sync_stx(dev);
681 b43_phy_write(dev, B43_PHY_OFDM(0xF0), 0x5F80);
682 b43_phy_write(dev, B43_PHY_OFDM(0xF1), 0);
683 if (dev->dev->bus->chip_id == 0x4325) {
684 // TODO SSB PMU recalibration
685 }
686 }
687 }
688
689 struct lpphy_iq_est { u32 iq_prod, i_pwr, q_pwr; };
690
691 static void lpphy_set_rc_cap(struct b43_wldev *dev)
692 {
693 struct b43_phy_lp *lpphy = dev->phy.lp;
694
695 u8 rc_cap = (lpphy->rc_cap & 0x1F) >> 1;
696
697 if (dev->phy.rev == 1) //FIXME check channel 14!
698 rc_cap = max_t(u8, rc_cap + 5, 15);
699
700 b43_radio_write(dev, B2062_N_RXBB_CALIB2,
701 max_t(u8, lpphy->rc_cap - 4, 0x80));
702 b43_radio_write(dev, B2062_N_TX_CTL_A, rc_cap | 0x80);
703 b43_radio_write(dev, B2062_S_RXG_CNT16,
704 ((lpphy->rc_cap & 0x1F) >> 2) | 0x80);
705 }
706
707 static u8 lpphy_get_bb_mult(struct b43_wldev *dev)
708 {
709 return (b43_lptab_read(dev, B43_LPTAB16(0, 87)) & 0xFF00) >> 8;
710 }
711
712 static void lpphy_set_bb_mult(struct b43_wldev *dev, u8 bb_mult)
713 {
714 b43_lptab_write(dev, B43_LPTAB16(0, 87), (u16)bb_mult << 8);
715 }
716
717 static void lpphy_disable_crs(struct b43_wldev *dev)
718 {
719 b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL, 0xFF1F, 0x80);
720 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFFC, 0x1);
721 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x3);
722 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFFB);
723 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x4);
724 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFF7);
725 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x8);
726 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0x10);
727 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x10);
728 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFDF);
729 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x20);
730 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFBF);
731 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x40);
732 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0x7);
733 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0x38);
734 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xFF3F);
735 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0x100);
736 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xFDFF);
737 b43_phy_write(dev, B43_LPPHY_PS_CTL_OVERRIDE_VAL0, 0);
738 b43_phy_write(dev, B43_LPPHY_PS_CTL_OVERRIDE_VAL1, 1);
739 b43_phy_write(dev, B43_LPPHY_PS_CTL_OVERRIDE_VAL2, 0x20);
740 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xFBFF);
741 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xF7FF);
742 b43_phy_write(dev, B43_LPPHY_TX_GAIN_CTL_OVERRIDE_VAL, 0);
743 b43_phy_write(dev, B43_LPPHY_RX_GAIN_CTL_OVERRIDE_VAL, 0x45AF);
744 b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_2, 0x3FF);
745 }
746
747 static void lpphy_restore_crs(struct b43_wldev *dev)
748 {
749 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
750 b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL, 0xFF1F, 0x60);
751 else
752 b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL, 0xFF1F, 0x20);
753 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFF80);
754 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFC00);
755 }
756
757 struct lpphy_tx_gains { u16 gm, pga, pad, dac; };
758
759 static struct lpphy_tx_gains lpphy_get_tx_gains(struct b43_wldev *dev)
760 {
761 struct lpphy_tx_gains gains;
762 u16 tmp;
763
764 gains.dac = (b43_phy_read(dev, B43_LPPHY_AFE_DAC_CTL) & 0x380) >> 7;
765 if (dev->phy.rev < 2) {
766 tmp = b43_phy_read(dev,
767 B43_LPPHY_TX_GAIN_CTL_OVERRIDE_VAL) & 0x7FF;
768 gains.gm = tmp & 0x0007;
769 gains.pga = (tmp & 0x0078) >> 3;
770 gains.pad = (tmp & 0x780) >> 7;
771 } else {
772 tmp = b43_phy_read(dev, B43_LPPHY_TX_GAIN_CTL_OVERRIDE_VAL);
773 gains.pad = b43_phy_read(dev, B43_PHY_OFDM(0xFB)) & 0xFF;
774 gains.gm = tmp & 0xFF;
775 gains.pga = (tmp >> 8) & 0xFF;
776 }
777
778 return gains;
779 }
780
781 static void lpphy_set_dac_gain(struct b43_wldev *dev, u16 dac)
782 {
783 u16 ctl = b43_phy_read(dev, B43_LPPHY_AFE_DAC_CTL) & 0xC7F;
784 ctl |= dac << 7;
785 b43_phy_maskset(dev, B43_LPPHY_AFE_DAC_CTL, 0xF000, ctl);
786 }
787
788 static void lpphy_set_tx_gains(struct b43_wldev *dev,
789 struct lpphy_tx_gains gains)
790 {
791 u16 rf_gain, pa_gain;
792
793 if (dev->phy.rev < 2) {
794 rf_gain = (gains.pad << 7) | (gains.pga << 3) | gains.gm;
795 b43_phy_maskset(dev, B43_LPPHY_TX_GAIN_CTL_OVERRIDE_VAL,
796 0xF800, rf_gain);
797 } else {
798 pa_gain = b43_phy_read(dev, B43_PHY_OFDM(0xFB)) & 0x7F00;
799 b43_phy_write(dev, B43_LPPHY_TX_GAIN_CTL_OVERRIDE_VAL,
800 (gains.pga << 8) | gains.gm);
801 b43_phy_maskset(dev, B43_LPPHY_TX_GAIN_CTL_OVERRIDE_VAL,
802 0x8000, gains.pad | pa_gain);
803 b43_phy_write(dev, B43_PHY_OFDM(0xFC),
804 (gains.pga << 8) | gains.gm);
805 b43_phy_maskset(dev, B43_PHY_OFDM(0xFD),
806 0x8000, gains.pad | pa_gain);
807 }
808 lpphy_set_dac_gain(dev, gains.dac);
809 if (dev->phy.rev < 2) {
810 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFEFF, 1 << 8);
811 } else {
812 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFF7F, 1 << 7);
813 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2, 0xBFFF, 1 << 14);
814 }
815 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFFBF, 1 << 6);
816 }
817
818 static void lpphy_rev0_1_set_rx_gain(struct b43_wldev *dev, u32 gain)
819 {
820 u16 trsw = gain & 0x1;
821 u16 lna = (gain & 0xFFFC) | ((gain & 0xC) >> 2);
822 u16 ext_lna = (gain & 2) >> 1;
823
824 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFFE, trsw);
825 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL,
826 0xFBFF, ext_lna << 10);
827 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL,
828 0xF7FF, ext_lna << 11);
829 b43_phy_write(dev, B43_LPPHY_RX_GAIN_CTL_OVERRIDE_VAL, lna);
830 }
831
832 static void lpphy_rev2plus_set_rx_gain(struct b43_wldev *dev, u32 gain)
833 {
834 u16 low_gain = gain & 0xFFFF;
835 u16 high_gain = (gain >> 16) & 0xF;
836 u16 ext_lna = (gain >> 21) & 0x1;
837 u16 trsw = ~(gain >> 20) & 0x1;
838 u16 tmp;
839
840 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFFE, trsw);
841 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL,
842 0xFDFF, ext_lna << 9);
843 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL,
844 0xFBFF, ext_lna << 10);
845 b43_phy_write(dev, B43_LPPHY_RX_GAIN_CTL_OVERRIDE_VAL, low_gain);
846 b43_phy_maskset(dev, B43_LPPHY_AFE_DDFS, 0xFFF0, high_gain);
847 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
848 tmp = (gain >> 2) & 0x3;
849 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL,
850 0xE7FF, tmp<<11);
851 b43_phy_maskset(dev, B43_PHY_OFDM(0xE6), 0xFFE7, tmp << 3);
852 }
853 }
854
855 static void lpphy_enable_rx_gain_override(struct b43_wldev *dev)
856 {
857 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFFE);
858 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFEF);
859 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFBF);
860 if (dev->phy.rev >= 2) {
861 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFEFF);
862 if (b43_current_band(dev->wl) != IEEE80211_BAND_2GHZ)
863 return;
864 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFBFF);
865 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFFF7);
866 } else {
867 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFDFF);
868 }
869 }
870
871 static void lpphy_disable_rx_gain_override(struct b43_wldev *dev)
872 {
873 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x1);
874 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x10);
875 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x40);
876 if (dev->phy.rev >= 2) {
877 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x100);
878 if (b43_current_band(dev->wl) != IEEE80211_BAND_2GHZ)
879 return;
880 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x400);
881 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x8);
882 } else {
883 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x200);
884 }
885 }
886
887 static void lpphy_set_rx_gain(struct b43_wldev *dev, u32 gain)
888 {
889 if (dev->phy.rev < 2)
890 lpphy_rev0_1_set_rx_gain(dev, gain);
891 else
892 lpphy_rev2plus_set_rx_gain(dev, gain);
893 lpphy_enable_rx_gain_override(dev);
894 }
895
896 static void lpphy_set_rx_gain_by_index(struct b43_wldev *dev, u16 idx)
897 {
898 u32 gain = b43_lptab_read(dev, B43_LPTAB16(12, idx));
899 lpphy_set_rx_gain(dev, gain);
900 }
901
902 static void lpphy_stop_ddfs(struct b43_wldev *dev)
903 {
904 b43_phy_mask(dev, B43_LPPHY_AFE_DDFS, 0xFFFD);
905 b43_phy_mask(dev, B43_LPPHY_LP_PHY_CTL, 0xFFDF);
906 }
907
908 static void lpphy_run_ddfs(struct b43_wldev *dev, int i_on, int q_on,
909 int incr1, int incr2, int scale_idx)
910 {
911 lpphy_stop_ddfs(dev);
912 b43_phy_mask(dev, B43_LPPHY_AFE_DDFS_POINTER_INIT, 0xFF80);
913 b43_phy_mask(dev, B43_LPPHY_AFE_DDFS_POINTER_INIT, 0x80FF);
914 b43_phy_maskset(dev, B43_LPPHY_AFE_DDFS_INCR_INIT, 0xFF80, incr1);
915 b43_phy_maskset(dev, B43_LPPHY_AFE_DDFS_INCR_INIT, 0x80FF, incr2 << 8);
916 b43_phy_maskset(dev, B43_LPPHY_AFE_DDFS, 0xFFF7, i_on << 3);
917 b43_phy_maskset(dev, B43_LPPHY_AFE_DDFS, 0xFFEF, q_on << 4);
918 b43_phy_maskset(dev, B43_LPPHY_AFE_DDFS, 0xFF9F, scale_idx << 5);
919 b43_phy_mask(dev, B43_LPPHY_AFE_DDFS, 0xFFFB);
920 b43_phy_set(dev, B43_LPPHY_AFE_DDFS, 0x2);
921 b43_phy_set(dev, B43_LPPHY_AFE_DDFS, 0x20);
922 }
923
924 static bool lpphy_rx_iq_est(struct b43_wldev *dev, u16 samples, u8 time,
925 struct lpphy_iq_est *iq_est)
926 {
927 int i;
928
929 b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, 0xFFF7);
930 b43_phy_write(dev, B43_LPPHY_IQ_NUM_SMPLS_ADDR, samples);
931 b43_phy_maskset(dev, B43_LPPHY_IQ_ENABLE_WAIT_TIME_ADDR, 0xFF00, time);
932 b43_phy_mask(dev, B43_LPPHY_IQ_ENABLE_WAIT_TIME_ADDR, 0xFEFF);
933 b43_phy_set(dev, B43_LPPHY_IQ_ENABLE_WAIT_TIME_ADDR, 0xFDFF);
934
935 for (i = 0; i < 500; i++) {
936 if (!(b43_phy_read(dev,
937 B43_LPPHY_IQ_ENABLE_WAIT_TIME_ADDR) & 0x200))
938 break;
939 msleep(1);
940 }
941
942 if ((b43_phy_read(dev, B43_LPPHY_IQ_ENABLE_WAIT_TIME_ADDR) & 0x200)) {
943 b43_phy_set(dev, B43_LPPHY_CRSGAIN_CTL, 0x8);
944 return false;
945 }
946
947 iq_est->iq_prod = b43_phy_read(dev, B43_LPPHY_IQ_ACC_HI_ADDR);
948 iq_est->iq_prod <<= 16;
949 iq_est->iq_prod |= b43_phy_read(dev, B43_LPPHY_IQ_ACC_LO_ADDR);
950
951 iq_est->i_pwr = b43_phy_read(dev, B43_LPPHY_IQ_I_PWR_ACC_HI_ADDR);
952 iq_est->i_pwr <<= 16;
953 iq_est->i_pwr |= b43_phy_read(dev, B43_LPPHY_IQ_I_PWR_ACC_LO_ADDR);
954
955 iq_est->q_pwr = b43_phy_read(dev, B43_LPPHY_IQ_Q_PWR_ACC_HI_ADDR);
956 iq_est->q_pwr <<= 16;
957 iq_est->q_pwr |= b43_phy_read(dev, B43_LPPHY_IQ_Q_PWR_ACC_LO_ADDR);
958
959 b43_phy_set(dev, B43_LPPHY_CRSGAIN_CTL, 0x8);
960 return true;
961 }
962
963 static int lpphy_loopback(struct b43_wldev *dev)
964 {
965 struct lpphy_iq_est iq_est;
966 int i, index = -1;
967 u32 tmp;
968
969 memset(&iq_est, 0, sizeof(iq_est));
970
971 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFFC, 0x3);
972 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x3);
973 b43_phy_mask(dev, B43_LPPHY_AFE_CTL_OVRVAL, 0xFFFE);
974 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x800);
975 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0x800);
976 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x8);
977 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0x8);
978 b43_radio_write(dev, B2062_N_TX_CTL_A, 0x80);
979 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x80);
980 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0x80);
981 for (i = 0; i < 32; i++) {
982 lpphy_set_rx_gain_by_index(dev, i);
983 lpphy_run_ddfs(dev, 1, 1, 5, 5, 0);
984 if (!(lpphy_rx_iq_est(dev, 1000, 32, &iq_est)))
985 continue;
986 tmp = (iq_est.i_pwr + iq_est.q_pwr) / 1000;
987 if ((tmp > 4000) && (tmp < 10000)) {
988 index = i;
989 break;
990 }
991 }
992 lpphy_stop_ddfs(dev);
993 return index;
994 }
995
996 static u32 lpphy_qdiv_roundup(u32 dividend, u32 divisor, u8 precision)
997 {
998 u32 quotient, remainder, rbit, roundup, tmp;
999
1000 if (divisor == 0) {
1001 quotient = 0;
1002 remainder = 0;
1003 } else {
1004 quotient = dividend / divisor;
1005 remainder = dividend % divisor;
1006 }
1007
1008 rbit = divisor & 0x1;
1009 roundup = (divisor >> 1) + rbit;
1010 precision--;
1011
1012 while (precision != 0xFF) {
1013 tmp = remainder - roundup;
1014 quotient <<= 1;
1015 remainder <<= 1;
1016 if (remainder >= roundup) {
1017 remainder = (tmp << 1) + rbit;
1018 quotient--;
1019 }
1020 precision--;
1021 }
1022
1023 if (remainder >= roundup)
1024 quotient++;
1025
1026 return quotient;
1027 }
1028
1029 /* Read the TX power control mode from hardware. */
1030 static void lpphy_read_tx_pctl_mode_from_hardware(struct b43_wldev *dev)
1031 {
1032 struct b43_phy_lp *lpphy = dev->phy.lp;
1033 u16 ctl;
1034
1035 ctl = b43_phy_read(dev, B43_LPPHY_TX_PWR_CTL_CMD);
1036 switch (ctl & B43_LPPHY_TX_PWR_CTL_CMD_MODE) {
1037 case B43_LPPHY_TX_PWR_CTL_CMD_MODE_OFF:
1038 lpphy->txpctl_mode = B43_LPPHY_TXPCTL_OFF;
1039 break;
1040 case B43_LPPHY_TX_PWR_CTL_CMD_MODE_SW:
1041 lpphy->txpctl_mode = B43_LPPHY_TXPCTL_SW;
1042 break;
1043 case B43_LPPHY_TX_PWR_CTL_CMD_MODE_HW:
1044 lpphy->txpctl_mode = B43_LPPHY_TXPCTL_HW;
1045 break;
1046 default:
1047 lpphy->txpctl_mode = B43_LPPHY_TXPCTL_UNKNOWN;
1048 B43_WARN_ON(1);
1049 break;
1050 }
1051 }
1052
1053 /* Set the TX power control mode in hardware. */
1054 static void lpphy_write_tx_pctl_mode_to_hardware(struct b43_wldev *dev)
1055 {
1056 struct b43_phy_lp *lpphy = dev->phy.lp;
1057 u16 ctl;
1058
1059 switch (lpphy->txpctl_mode) {
1060 case B43_LPPHY_TXPCTL_OFF:
1061 ctl = B43_LPPHY_TX_PWR_CTL_CMD_MODE_OFF;
1062 break;
1063 case B43_LPPHY_TXPCTL_HW:
1064 ctl = B43_LPPHY_TX_PWR_CTL_CMD_MODE_HW;
1065 break;
1066 case B43_LPPHY_TXPCTL_SW:
1067 ctl = B43_LPPHY_TX_PWR_CTL_CMD_MODE_SW;
1068 break;
1069 default:
1070 ctl = 0;
1071 B43_WARN_ON(1);
1072 }
1073 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_CMD,
1074 (u16)~B43_LPPHY_TX_PWR_CTL_CMD_MODE, ctl);
1075 }
1076
1077 static void lpphy_set_tx_power_control(struct b43_wldev *dev,
1078 enum b43_lpphy_txpctl_mode mode)
1079 {
1080 struct b43_phy_lp *lpphy = dev->phy.lp;
1081 enum b43_lpphy_txpctl_mode oldmode;
1082
1083 oldmode = lpphy->txpctl_mode;
1084 lpphy_read_tx_pctl_mode_from_hardware(dev);
1085 if (lpphy->txpctl_mode == mode)
1086 return;
1087 lpphy->txpctl_mode = mode;
1088
1089 if (oldmode == B43_LPPHY_TXPCTL_HW) {
1090 //TODO Update TX Power NPT
1091 //TODO Clear all TX Power offsets
1092 } else {
1093 if (mode == B43_LPPHY_TXPCTL_HW) {
1094 //TODO Recalculate target TX power
1095 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_CMD,
1096 0xFF80, lpphy->tssi_idx);
1097 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_NNUM,
1098 0x8FFF, ((u16)lpphy->tssi_npt << 16));
1099 //TODO Set "TSSI Transmit Count" variable to total transmitted frame count
1100 //TODO Disable TX gain override
1101 lpphy->tx_pwr_idx_over = -1;
1102 }
1103 }
1104 if (dev->phy.rev >= 2) {
1105 if (mode == B43_LPPHY_TXPCTL_HW)
1106 b43_phy_maskset(dev, B43_PHY_OFDM(0xD0), 0xFD, 0x2);
1107 else
1108 b43_phy_maskset(dev, B43_PHY_OFDM(0xD0), 0xFD, 0);
1109 }
1110 lpphy_write_tx_pctl_mode_to_hardware(dev);
1111 }
1112
1113 static int b43_lpphy_op_switch_channel(struct b43_wldev *dev,
1114 unsigned int new_channel);
1115
1116 static void lpphy_rev0_1_rc_calib(struct b43_wldev *dev)
1117 {
1118 struct b43_phy_lp *lpphy = dev->phy.lp;
1119 struct lpphy_iq_est iq_est;
1120 struct lpphy_tx_gains tx_gains;
1121 static const u32 ideal_pwr_table[22] = {
1122 0x10000, 0x10557, 0x10e2d, 0x113e0, 0x10f22, 0x0ff64,
1123 0x0eda2, 0x0e5d4, 0x0efd1, 0x0fbe8, 0x0b7b8, 0x04b35,
1124 0x01a5e, 0x00a0b, 0x00444, 0x001fd, 0x000ff, 0x00088,
1125 0x0004c, 0x0002c, 0x0001a, 0xc0006,
1126 };
1127 bool old_txg_ovr;
1128 u8 old_bbmult;
1129 u16 old_rf_ovr, old_rf_ovrval, old_afe_ovr, old_afe_ovrval,
1130 old_rf2_ovr, old_rf2_ovrval, old_phy_ctl;
1131 enum b43_lpphy_txpctl_mode old_txpctl;
1132 u32 normal_pwr, ideal_pwr, mean_sq_pwr, tmp = 0, mean_sq_pwr_min = 0;
1133 int loopback, i, j, inner_sum, err;
1134
1135 memset(&iq_est, 0, sizeof(iq_est));
1136
1137 err = b43_lpphy_op_switch_channel(dev, 7);
1138 if (err) {
1139 b43dbg(dev->wl,
1140 "RC calib: Failed to switch to channel 7, error = %d",
1141 err);
1142 }
1143 old_txg_ovr = (b43_phy_read(dev, B43_LPPHY_AFE_CTL_OVR) >> 6) & 1;
1144 old_bbmult = lpphy_get_bb_mult(dev);
1145 if (old_txg_ovr)
1146 tx_gains = lpphy_get_tx_gains(dev);
1147 old_rf_ovr = b43_phy_read(dev, B43_LPPHY_RF_OVERRIDE_0);
1148 old_rf_ovrval = b43_phy_read(dev, B43_LPPHY_RF_OVERRIDE_VAL_0);
1149 old_afe_ovr = b43_phy_read(dev, B43_LPPHY_AFE_CTL_OVR);
1150 old_afe_ovrval = b43_phy_read(dev, B43_LPPHY_AFE_CTL_OVRVAL);
1151 old_rf2_ovr = b43_phy_read(dev, B43_LPPHY_RF_OVERRIDE_2);
1152 old_rf2_ovrval = b43_phy_read(dev, B43_LPPHY_RF_OVERRIDE_2_VAL);
1153 old_phy_ctl = b43_phy_read(dev, B43_LPPHY_LP_PHY_CTL);
1154 lpphy_read_tx_pctl_mode_from_hardware(dev);
1155 old_txpctl = lpphy->txpctl_mode;
1156
1157 lpphy_set_tx_power_control(dev, B43_LPPHY_TX_PWR_CTL_CMD_MODE_OFF);
1158 lpphy_disable_crs(dev);
1159 loopback = lpphy_loopback(dev);
1160 if (loopback == -1)
1161 goto finish;
1162 lpphy_set_rx_gain_by_index(dev, loopback);
1163 b43_phy_maskset(dev, B43_LPPHY_LP_PHY_CTL, 0xFFBF, 0x40);
1164 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xFFF8, 0x1);
1165 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xFFC7, 0x8);
1166 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xFF3F, 0xC0);
1167 for (i = 128; i <= 159; i++) {
1168 b43_radio_write(dev, B2062_N_RXBB_CALIB2, i);
1169 inner_sum = 0;
1170 for (j = 5; j <= 25; j++) {
1171 lpphy_run_ddfs(dev, 1, 1, j, j, 0);
1172 if (!(lpphy_rx_iq_est(dev, 1000, 32, &iq_est)))
1173 goto finish;
1174 mean_sq_pwr = iq_est.i_pwr + iq_est.q_pwr;
1175 if (j == 5)
1176 tmp = mean_sq_pwr;
1177 ideal_pwr = ((ideal_pwr_table[j-5] >> 3) + 1) >> 1;
1178 normal_pwr = lpphy_qdiv_roundup(mean_sq_pwr, tmp, 12);
1179 mean_sq_pwr = ideal_pwr - normal_pwr;
1180 mean_sq_pwr *= mean_sq_pwr;
1181 inner_sum += mean_sq_pwr;
1182 if ((i = 128) || (inner_sum < mean_sq_pwr_min)) {
1183 lpphy->rc_cap = i;
1184 mean_sq_pwr_min = inner_sum;
1185 }
1186 }
1187 }
1188 lpphy_stop_ddfs(dev);
1189
1190 finish:
1191 lpphy_restore_crs(dev);
1192 b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, old_rf_ovrval);
1193 b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_0, old_rf_ovr);
1194 b43_phy_write(dev, B43_LPPHY_AFE_CTL_OVRVAL, old_afe_ovrval);
1195 b43_phy_write(dev, B43_LPPHY_AFE_CTL_OVR, old_afe_ovr);
1196 b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, old_rf2_ovrval);
1197 b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_2, old_rf2_ovr);
1198 b43_phy_write(dev, B43_LPPHY_LP_PHY_CTL, old_phy_ctl);
1199
1200 lpphy_set_bb_mult(dev, old_bbmult);
1201 if (old_txg_ovr) {
1202 /*
1203 * SPEC FIXME: The specs say "get_tx_gains" here, which is
1204 * illogical. According to lwfinger, vendor driver v4.150.10.5
1205 * has a Set here, while v4.174.64.19 has a Get - regression in
1206 * the vendor driver? This should be tested this once the code
1207 * is testable.
1208 */
1209 lpphy_set_tx_gains(dev, tx_gains);
1210 }
1211 lpphy_set_tx_power_control(dev, old_txpctl);
1212 if (lpphy->rc_cap)
1213 lpphy_set_rc_cap(dev);
1214 }
1215
1216 static void lpphy_rev2plus_rc_calib(struct b43_wldev *dev)
1217 {
1218 struct ssb_bus *bus = dev->dev->bus;
1219 u32 crystal_freq = bus->chipco.pmu.crystalfreq * 1000;
1220 u8 tmp = b43_radio_read(dev, B2063_RX_BB_SP8) & 0xFF;
1221 int i;
1222
1223 b43_radio_write(dev, B2063_RX_BB_SP8, 0x0);
1224 b43_radio_write(dev, B2063_RC_CALIB_CTL1, 0x7E);
1225 b43_radio_mask(dev, B2063_PLL_SP1, 0xF7);
1226 b43_radio_write(dev, B2063_RC_CALIB_CTL1, 0x7C);
1227 b43_radio_write(dev, B2063_RC_CALIB_CTL2, 0x15);
1228 b43_radio_write(dev, B2063_RC_CALIB_CTL3, 0x70);
1229 b43_radio_write(dev, B2063_RC_CALIB_CTL4, 0x52);
1230 b43_radio_write(dev, B2063_RC_CALIB_CTL5, 0x1);
1231 b43_radio_write(dev, B2063_RC_CALIB_CTL1, 0x7D);
1232
1233 for (i = 0; i < 10000; i++) {
1234 if (b43_radio_read(dev, B2063_RC_CALIB_CTL6) & 0x2)
1235 break;
1236 msleep(1);
1237 }
1238
1239 if (!(b43_radio_read(dev, B2063_RC_CALIB_CTL6) & 0x2))
1240 b43_radio_write(dev, B2063_RX_BB_SP8, tmp);
1241
1242 tmp = b43_radio_read(dev, B2063_TX_BB_SP3) & 0xFF;
1243
1244 b43_radio_write(dev, B2063_TX_BB_SP3, 0x0);
1245 b43_radio_write(dev, B2063_RC_CALIB_CTL1, 0x7E);
1246 b43_radio_write(dev, B2063_RC_CALIB_CTL1, 0x7C);
1247 b43_radio_write(dev, B2063_RC_CALIB_CTL2, 0x55);
1248 b43_radio_write(dev, B2063_RC_CALIB_CTL3, 0x76);
1249
1250 if (crystal_freq == 24000000) {
1251 b43_radio_write(dev, B2063_RC_CALIB_CTL4, 0xFC);
1252 b43_radio_write(dev, B2063_RC_CALIB_CTL5, 0x0);
1253 } else {
1254 b43_radio_write(dev, B2063_RC_CALIB_CTL4, 0x13);
1255 b43_radio_write(dev, B2063_RC_CALIB_CTL5, 0x1);
1256 }
1257
1258 b43_radio_write(dev, B2063_PA_SP7, 0x7D);
1259
1260 for (i = 0; i < 10000; i++) {
1261 if (b43_radio_read(dev, B2063_RC_CALIB_CTL6) & 0x2)
1262 break;
1263 msleep(1);
1264 }
1265
1266 if (!(b43_radio_read(dev, B2063_RC_CALIB_CTL6) & 0x2))
1267 b43_radio_write(dev, B2063_TX_BB_SP3, tmp);
1268
1269 b43_radio_write(dev, B2063_RC_CALIB_CTL1, 0x7E);
1270 }
1271
1272 static void lpphy_calibrate_rc(struct b43_wldev *dev)
1273 {
1274 struct b43_phy_lp *lpphy = dev->phy.lp;
1275
1276 if (dev->phy.rev >= 2) {
1277 lpphy_rev2plus_rc_calib(dev);
1278 } else if (!lpphy->rc_cap) {
1279 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
1280 lpphy_rev0_1_rc_calib(dev);
1281 } else {
1282 lpphy_set_rc_cap(dev);
1283 }
1284 }
1285
1286 static void lpphy_set_tx_power_by_index(struct b43_wldev *dev, u8 index)
1287 {
1288 struct b43_phy_lp *lpphy = dev->phy.lp;
1289
1290 lpphy->tx_pwr_idx_over = index;
1291 if (lpphy->txpctl_mode != B43_LPPHY_TXPCTL_OFF)
1292 lpphy_set_tx_power_control(dev, B43_LPPHY_TXPCTL_SW);
1293
1294 //TODO
1295 }
1296
1297 static void lpphy_btcoex_override(struct b43_wldev *dev)
1298 {
1299 b43_write16(dev, B43_MMIO_BTCOEX_CTL, 0x3);
1300 b43_write16(dev, B43_MMIO_BTCOEX_TXCTL, 0xFF);
1301 }
1302
1303 static void lpphy_pr41573_workaround(struct b43_wldev *dev)
1304 {
1305 struct b43_phy_lp *lpphy = dev->phy.lp;
1306 u32 *saved_tab;
1307 const unsigned int saved_tab_size = 256;
1308 enum b43_lpphy_txpctl_mode txpctl_mode;
1309 s8 tx_pwr_idx_over;
1310 u16 tssi_npt, tssi_idx;
1311
1312 saved_tab = kcalloc(saved_tab_size, sizeof(saved_tab[0]), GFP_KERNEL);
1313 if (!saved_tab) {
1314 b43err(dev->wl, "PR41573 failed. Out of memory!\n");
1315 return;
1316 }
1317
1318 lpphy_read_tx_pctl_mode_from_hardware(dev);
1319 txpctl_mode = lpphy->txpctl_mode;
1320 tx_pwr_idx_over = lpphy->tx_pwr_idx_over;
1321 tssi_npt = lpphy->tssi_npt;
1322 tssi_idx = lpphy->tssi_idx;
1323
1324 if (dev->phy.rev < 2) {
1325 b43_lptab_read_bulk(dev, B43_LPTAB32(10, 0x140),
1326 saved_tab_size, saved_tab);
1327 } else {
1328 b43_lptab_read_bulk(dev, B43_LPTAB32(7, 0x140),
1329 saved_tab_size, saved_tab);
1330 }
1331 //TODO
1332
1333 kfree(saved_tab);
1334 }
1335
1336 static void lpphy_calibration(struct b43_wldev *dev)
1337 {
1338 struct b43_phy_lp *lpphy = dev->phy.lp;
1339 enum b43_lpphy_txpctl_mode saved_pctl_mode;
1340
1341 b43_mac_suspend(dev);
1342
1343 lpphy_btcoex_override(dev);
1344 lpphy_read_tx_pctl_mode_from_hardware(dev);
1345 saved_pctl_mode = lpphy->txpctl_mode;
1346 lpphy_set_tx_power_control(dev, B43_LPPHY_TXPCTL_OFF);
1347 //TODO Perform transmit power table I/Q LO calibration
1348 if ((dev->phy.rev == 0) && (saved_pctl_mode != B43_LPPHY_TXPCTL_OFF))
1349 lpphy_pr41573_workaround(dev);
1350 //TODO If a full calibration has not been performed on this channel yet, perform PAPD TX-power calibration
1351 lpphy_set_tx_power_control(dev, saved_pctl_mode);
1352 //TODO Perform I/Q calibration with a single control value set
1353
1354 b43_mac_enable(dev);
1355 }
1356
1357 static void lpphy_set_tssi_mux(struct b43_wldev *dev, enum tssi_mux_mode mode)
1358 {
1359 if (mode != TSSI_MUX_EXT) {
1360 b43_radio_set(dev, B2063_PA_SP1, 0x2);
1361 b43_phy_set(dev, B43_PHY_OFDM(0xF3), 0x1000);
1362 b43_radio_write(dev, B2063_PA_CTL10, 0x51);
1363 if (mode == TSSI_MUX_POSTPA) {
1364 b43_radio_mask(dev, B2063_PA_SP1, 0xFFFE);
1365 b43_phy_mask(dev, B43_LPPHY_AFE_CTL_OVRVAL, 0xFFC7);
1366 } else {
1367 b43_radio_maskset(dev, B2063_PA_SP1, 0xFFFE, 0x1);
1368 b43_phy_maskset(dev, B43_LPPHY_AFE_CTL_OVRVAL,
1369 0xFFC7, 0x20);
1370 }
1371 } else {
1372 B43_WARN_ON(1);
1373 }
1374 }
1375
1376 static void lpphy_tx_pctl_init_hw(struct b43_wldev *dev)
1377 {
1378 u16 tmp;
1379 int i;
1380
1381 //SPEC TODO Call LP PHY Clear TX Power offsets
1382 for (i = 0; i < 64; i++) {
1383 if (dev->phy.rev >= 2)
1384 b43_lptab_write(dev, B43_LPTAB32(7, i + 1), i);
1385 else
1386 b43_lptab_write(dev, B43_LPTAB32(10, i + 1), i);
1387 }
1388
1389 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_NNUM, 0xFF00, 0xFF);
1390 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_NNUM, 0x8FFF, 0x5000);
1391 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_IDLETSSI, 0xFFC0, 0x1F);
1392 if (dev->phy.rev < 2) {
1393 b43_phy_mask(dev, B43_LPPHY_LP_PHY_CTL, 0xEFFF);
1394 b43_phy_maskset(dev, B43_LPPHY_LP_PHY_CTL, 0xDFFF, 0x2000);
1395 } else {
1396 b43_phy_mask(dev, B43_PHY_OFDM(0x103), 0xFFFE);
1397 b43_phy_maskset(dev, B43_PHY_OFDM(0x103), 0xFFFB, 0x4);
1398 b43_phy_maskset(dev, B43_PHY_OFDM(0x103), 0xFFEF, 0x10);
1399 b43_radio_maskset(dev, B2063_IQ_CALIB_CTL2, 0xF3, 0x1);
1400 lpphy_set_tssi_mux(dev, TSSI_MUX_POSTPA);
1401 }
1402 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_IDLETSSI, 0x7FFF, 0x8000);
1403 b43_phy_mask(dev, B43_LPPHY_TX_PWR_CTL_DELTAPWR_LIMIT, 0xFF);
1404 b43_phy_write(dev, B43_LPPHY_TX_PWR_CTL_DELTAPWR_LIMIT, 0xA);
1405 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_CMD,
1406 (u16)~B43_LPPHY_TX_PWR_CTL_CMD_MODE,
1407 B43_LPPHY_TX_PWR_CTL_CMD_MODE_OFF);
1408 b43_phy_mask(dev, B43_LPPHY_TX_PWR_CTL_NNUM, 0xF8FF);
1409 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_CMD,
1410 (u16)~B43_LPPHY_TX_PWR_CTL_CMD_MODE,
1411 B43_LPPHY_TX_PWR_CTL_CMD_MODE_SW);
1412
1413 if (dev->phy.rev < 2) {
1414 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_0, 0xEFFF, 0x1000);
1415 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xEFFF);
1416 } else {
1417 lpphy_set_tx_power_by_index(dev, 0x7F);
1418 }
1419
1420 b43_dummy_transmission(dev, true, true);
1421
1422 tmp = b43_phy_read(dev, B43_LPPHY_TX_PWR_CTL_STAT);
1423 if (tmp & 0x8000) {
1424 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_IDLETSSI,
1425 0xFFC0, (tmp & 0xFF) - 32);
1426 }
1427
1428 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xEFFF);
1429
1430 // (SPEC?) TODO Set "Target TX frequency" variable to 0
1431 // SPEC FIXME "Set BB Multiplier to 0xE000" impossible - bb_mult is u8!
1432 }
1433
1434 static void lpphy_tx_pctl_init_sw(struct b43_wldev *dev)
1435 {
1436 struct lpphy_tx_gains gains;
1437
1438 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
1439 gains.gm = 4;
1440 gains.pad = 12;
1441 gains.pga = 12;
1442 gains.dac = 0;
1443 } else {
1444 gains.gm = 7;
1445 gains.pad = 14;
1446 gains.pga = 15;
1447 gains.dac = 0;
1448 }
1449 lpphy_set_tx_gains(dev, gains);
1450 lpphy_set_bb_mult(dev, 150);
1451 }
1452
1453 /* Initialize TX power control */
1454 static void lpphy_tx_pctl_init(struct b43_wldev *dev)
1455 {
1456 if (0/*FIXME HWPCTL capable */) {
1457 lpphy_tx_pctl_init_hw(dev);
1458 } else { /* This device is only software TX power control capable. */
1459 lpphy_tx_pctl_init_sw(dev);
1460 }
1461 }
1462
1463 static u16 b43_lpphy_op_read(struct b43_wldev *dev, u16 reg)
1464 {
1465 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
1466 return b43_read16(dev, B43_MMIO_PHY_DATA);
1467 }
1468
1469 static void b43_lpphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
1470 {
1471 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
1472 b43_write16(dev, B43_MMIO_PHY_DATA, value);
1473 }
1474
1475 static u16 b43_lpphy_op_radio_read(struct b43_wldev *dev, u16 reg)
1476 {
1477 /* Register 1 is a 32-bit register. */
1478 B43_WARN_ON(reg == 1);
1479 /* LP-PHY needs a special bit set for read access */
1480 if (dev->phy.rev < 2) {
1481 if (reg != 0x4001)
1482 reg |= 0x100;
1483 } else
1484 reg |= 0x200;
1485
1486 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
1487 return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
1488 }
1489
1490 static void b43_lpphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
1491 {
1492 /* Register 1 is a 32-bit register. */
1493 B43_WARN_ON(reg == 1);
1494
1495 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
1496 b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
1497 }
1498
1499 static void b43_lpphy_op_software_rfkill(struct b43_wldev *dev,
1500 bool blocked)
1501 {
1502 //TODO
1503 }
1504
1505 struct b206x_channel {
1506 u8 channel;
1507 u16 freq;
1508 u8 data[12];
1509 };
1510
1511 static const struct b206x_channel b2062_chantbl[] = {
1512 { .channel = 1, .freq = 2412, .data[0] = 0xFF, .data[1] = 0xFF,
1513 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1514 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1515 { .channel = 2, .freq = 2417, .data[0] = 0xFF, .data[1] = 0xFF,
1516 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1517 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1518 { .channel = 3, .freq = 2422, .data[0] = 0xFF, .data[1] = 0xFF,
1519 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1520 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1521 { .channel = 4, .freq = 2427, .data[0] = 0xFF, .data[1] = 0xFF,
1522 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1523 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1524 { .channel = 5, .freq = 2432, .data[0] = 0xFF, .data[1] = 0xFF,
1525 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1526 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1527 { .channel = 6, .freq = 2437, .data[0] = 0xFF, .data[1] = 0xFF,
1528 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1529 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1530 { .channel = 7, .freq = 2442, .data[0] = 0xFF, .data[1] = 0xFF,
1531 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1532 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1533 { .channel = 8, .freq = 2447, .data[0] = 0xFF, .data[1] = 0xFF,
1534 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1535 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1536 { .channel = 9, .freq = 2452, .data[0] = 0xFF, .data[1] = 0xFF,
1537 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1538 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1539 { .channel = 10, .freq = 2457, .data[0] = 0xFF, .data[1] = 0xFF,
1540 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1541 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1542 { .channel = 11, .freq = 2462, .data[0] = 0xFF, .data[1] = 0xFF,
1543 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1544 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1545 { .channel = 12, .freq = 2467, .data[0] = 0xFF, .data[1] = 0xFF,
1546 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1547 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1548 { .channel = 13, .freq = 2472, .data[0] = 0xFF, .data[1] = 0xFF,
1549 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1550 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1551 { .channel = 14, .freq = 2484, .data[0] = 0xFF, .data[1] = 0xFF,
1552 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1553 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1554 { .channel = 34, .freq = 5170, .data[0] = 0x00, .data[1] = 0x22,
1555 .data[2] = 0x20, .data[3] = 0x84, .data[4] = 0x3C, .data[5] = 0x77,
1556 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1557 { .channel = 38, .freq = 5190, .data[0] = 0x00, .data[1] = 0x11,
1558 .data[2] = 0x10, .data[3] = 0x83, .data[4] = 0x3C, .data[5] = 0x77,
1559 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1560 { .channel = 42, .freq = 5210, .data[0] = 0x00, .data[1] = 0x11,
1561 .data[2] = 0x10, .data[3] = 0x83, .data[4] = 0x3C, .data[5] = 0x77,
1562 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1563 { .channel = 46, .freq = 5230, .data[0] = 0x00, .data[1] = 0x00,
1564 .data[2] = 0x00, .data[3] = 0x83, .data[4] = 0x3C, .data[5] = 0x77,
1565 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1566 { .channel = 36, .freq = 5180, .data[0] = 0x00, .data[1] = 0x11,
1567 .data[2] = 0x20, .data[3] = 0x83, .data[4] = 0x3C, .data[5] = 0x77,
1568 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1569 { .channel = 40, .freq = 5200, .data[0] = 0x00, .data[1] = 0x11,
1570 .data[2] = 0x10, .data[3] = 0x84, .data[4] = 0x3C, .data[5] = 0x77,
1571 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1572 { .channel = 44, .freq = 5220, .data[0] = 0x00, .data[1] = 0x11,
1573 .data[2] = 0x00, .data[3] = 0x83, .data[4] = 0x3C, .data[5] = 0x77,
1574 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1575 { .channel = 48, .freq = 5240, .data[0] = 0x00, .data[1] = 0x00,
1576 .data[2] = 0x00, .data[3] = 0x83, .data[4] = 0x3C, .data[5] = 0x77,
1577 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1578 { .channel = 52, .freq = 5260, .data[0] = 0x00, .data[1] = 0x00,
1579 .data[2] = 0x00, .data[3] = 0x83, .data[4] = 0x3C, .data[5] = 0x77,
1580 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1581 { .channel = 56, .freq = 5280, .data[0] = 0x00, .data[1] = 0x00,
1582 .data[2] = 0x00, .data[3] = 0x83, .data[4] = 0x3C, .data[5] = 0x77,
1583 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1584 { .channel = 60, .freq = 5300, .data[0] = 0x00, .data[1] = 0x00,
1585 .data[2] = 0x00, .data[3] = 0x63, .data[4] = 0x3C, .data[5] = 0x77,
1586 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1587 { .channel = 64, .freq = 5320, .data[0] = 0x00, .data[1] = 0x00,
1588 .data[2] = 0x00, .data[3] = 0x62, .data[4] = 0x3C, .data[5] = 0x77,
1589 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1590 { .channel = 100, .freq = 5500, .data[0] = 0x00, .data[1] = 0x00,
1591 .data[2] = 0x00, .data[3] = 0x30, .data[4] = 0x3C, .data[5] = 0x77,
1592 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1593 { .channel = 104, .freq = 5520, .data[0] = 0x00, .data[1] = 0x00,
1594 .data[2] = 0x00, .data[3] = 0x20, .data[4] = 0x3C, .data[5] = 0x77,
1595 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1596 { .channel = 108, .freq = 5540, .data[0] = 0x00, .data[1] = 0x00,
1597 .data[2] = 0x00, .data[3] = 0x20, .data[4] = 0x3C, .data[5] = 0x77,
1598 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1599 { .channel = 112, .freq = 5560, .data[0] = 0x00, .data[1] = 0x00,
1600 .data[2] = 0x00, .data[3] = 0x20, .data[4] = 0x3C, .data[5] = 0x77,
1601 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1602 { .channel = 116, .freq = 5580, .data[0] = 0x00, .data[1] = 0x00,
1603 .data[2] = 0x00, .data[3] = 0x10, .data[4] = 0x3C, .data[5] = 0x77,
1604 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1605 { .channel = 120, .freq = 5600, .data[0] = 0x00, .data[1] = 0x00,
1606 .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
1607 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1608 { .channel = 124, .freq = 5620, .data[0] = 0x00, .data[1] = 0x00,
1609 .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
1610 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1611 { .channel = 128, .freq = 5640, .data[0] = 0x00, .data[1] = 0x00,
1612 .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
1613 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1614 { .channel = 132, .freq = 5660, .data[0] = 0x00, .data[1] = 0x00,
1615 .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
1616 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1617 { .channel = 136, .freq = 5680, .data[0] = 0x00, .data[1] = 0x00,
1618 .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
1619 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1620 { .channel = 140, .freq = 5700, .data[0] = 0x00, .data[1] = 0x00,
1621 .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
1622 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1623 { .channel = 149, .freq = 5745, .data[0] = 0x00, .data[1] = 0x00,
1624 .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
1625 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1626 { .channel = 153, .freq = 5765, .data[0] = 0x00, .data[1] = 0x00,
1627 .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
1628 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1629 { .channel = 157, .freq = 5785, .data[0] = 0x00, .data[1] = 0x00,
1630 .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
1631 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1632 { .channel = 161, .freq = 5805, .data[0] = 0x00, .data[1] = 0x00,
1633 .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
1634 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1635 { .channel = 165, .freq = 5825, .data[0] = 0x00, .data[1] = 0x00,
1636 .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
1637 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1638 { .channel = 184, .freq = 4920, .data[0] = 0x55, .data[1] = 0x77,
1639 .data[2] = 0x90, .data[3] = 0xF7, .data[4] = 0x3C, .data[5] = 0x77,
1640 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0xFF, },
1641 { .channel = 188, .freq = 4940, .data[0] = 0x44, .data[1] = 0x77,
1642 .data[2] = 0x80, .data[3] = 0xE7, .data[4] = 0x3C, .data[5] = 0x77,
1643 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0xFF, },
1644 { .channel = 192, .freq = 4960, .data[0] = 0x44, .data[1] = 0x66,
1645 .data[2] = 0x80, .data[3] = 0xE7, .data[4] = 0x3C, .data[5] = 0x77,
1646 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0xFF, },
1647 { .channel = 196, .freq = 4980, .data[0] = 0x33, .data[1] = 0x66,
1648 .data[2] = 0x70, .data[3] = 0xC7, .data[4] = 0x3C, .data[5] = 0x77,
1649 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0xFF, },
1650 { .channel = 200, .freq = 5000, .data[0] = 0x22, .data[1] = 0x55,
1651 .data[2] = 0x60, .data[3] = 0xD7, .data[4] = 0x3C, .data[5] = 0x77,
1652 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0xFF, },
1653 { .channel = 204, .freq = 5020, .data[0] = 0x22, .data[1] = 0x55,
1654 .data[2] = 0x60, .data[3] = 0xC7, .data[4] = 0x3C, .data[5] = 0x77,
1655 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0xFF, },
1656 { .channel = 208, .freq = 5040, .data[0] = 0x22, .data[1] = 0x44,
1657 .data[2] = 0x50, .data[3] = 0xC7, .data[4] = 0x3C, .data[5] = 0x77,
1658 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0xFF, },
1659 { .channel = 212, .freq = 5060, .data[0] = 0x11, .data[1] = 0x44,
1660 .data[2] = 0x50, .data[3] = 0xA5, .data[4] = 0x3C, .data[5] = 0x77,
1661 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1662 { .channel = 216, .freq = 5080, .data[0] = 0x00, .data[1] = 0x44,
1663 .data[2] = 0x40, .data[3] = 0xB6, .data[4] = 0x3C, .data[5] = 0x77,
1664 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1665 };
1666
1667 static const struct b206x_channel b2063_chantbl[] = {
1668 { .channel = 1, .freq = 2412, .data[0] = 0x6F, .data[1] = 0x3C,
1669 .data[2] = 0x3C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1670 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1671 .data[10] = 0x80, .data[11] = 0x70, },
1672 { .channel = 2, .freq = 2417, .data[0] = 0x6F, .data[1] = 0x3C,
1673 .data[2] = 0x3C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1674 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1675 .data[10] = 0x80, .data[11] = 0x70, },
1676 { .channel = 3, .freq = 2422, .data[0] = 0x6F, .data[1] = 0x3C,
1677 .data[2] = 0x3C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1678 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1679 .data[10] = 0x80, .data[11] = 0x70, },
1680 { .channel = 4, .freq = 2427, .data[0] = 0x6F, .data[1] = 0x2C,
1681 .data[2] = 0x2C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1682 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1683 .data[10] = 0x80, .data[11] = 0x70, },
1684 { .channel = 5, .freq = 2432, .data[0] = 0x6F, .data[1] = 0x2C,
1685 .data[2] = 0x2C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1686 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1687 .data[10] = 0x80, .data[11] = 0x70, },
1688 { .channel = 6, .freq = 2437, .data[0] = 0x6F, .data[1] = 0x2C,
1689 .data[2] = 0x2C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1690 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1691 .data[10] = 0x80, .data[11] = 0x70, },
1692 { .channel = 7, .freq = 2442, .data[0] = 0x6F, .data[1] = 0x2C,
1693 .data[2] = 0x2C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1694 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1695 .data[10] = 0x80, .data[11] = 0x70, },
1696 { .channel = 8, .freq = 2447, .data[0] = 0x6F, .data[1] = 0x2C,
1697 .data[2] = 0x2C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1698 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1699 .data[10] = 0x80, .data[11] = 0x70, },
1700 { .channel = 9, .freq = 2452, .data[0] = 0x6F, .data[1] = 0x1C,
1701 .data[2] = 0x1C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1702 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1703 .data[10] = 0x80, .data[11] = 0x70, },
1704 { .channel = 10, .freq = 2457, .data[0] = 0x6F, .data[1] = 0x1C,
1705 .data[2] = 0x1C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1706 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1707 .data[10] = 0x80, .data[11] = 0x70, },
1708 { .channel = 11, .freq = 2462, .data[0] = 0x6E, .data[1] = 0x1C,
1709 .data[2] = 0x1C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1710 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1711 .data[10] = 0x80, .data[11] = 0x70, },
1712 { .channel = 12, .freq = 2467, .data[0] = 0x6E, .data[1] = 0x1C,
1713 .data[2] = 0x1C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1714 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1715 .data[10] = 0x80, .data[11] = 0x70, },
1716 { .channel = 13, .freq = 2472, .data[0] = 0x6E, .data[1] = 0x1C,
1717 .data[2] = 0x1C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1718 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1719 .data[10] = 0x80, .data[11] = 0x70, },
1720 { .channel = 14, .freq = 2484, .data[0] = 0x6E, .data[1] = 0x0C,
1721 .data[2] = 0x0C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1722 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1723 .data[10] = 0x80, .data[11] = 0x70, },
1724 { .channel = 34, .freq = 5170, .data[0] = 0x6A, .data[1] = 0x0C,
1725 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x02, .data[5] = 0x05,
1726 .data[6] = 0x0D, .data[7] = 0x0D, .data[8] = 0x77, .data[9] = 0x80,
1727 .data[10] = 0x20, .data[11] = 0x00, },
1728 { .channel = 36, .freq = 5180, .data[0] = 0x6A, .data[1] = 0x0C,
1729 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x01, .data[5] = 0x05,
1730 .data[6] = 0x0D, .data[7] = 0x0C, .data[8] = 0x77, .data[9] = 0x80,
1731 .data[10] = 0x20, .data[11] = 0x00, },
1732 { .channel = 38, .freq = 5190, .data[0] = 0x6A, .data[1] = 0x0C,
1733 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x01, .data[5] = 0x04,
1734 .data[6] = 0x0C, .data[7] = 0x0C, .data[8] = 0x77, .data[9] = 0x80,
1735 .data[10] = 0x20, .data[11] = 0x00, },
1736 { .channel = 40, .freq = 5200, .data[0] = 0x69, .data[1] = 0x0C,
1737 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x01, .data[5] = 0x04,
1738 .data[6] = 0x0C, .data[7] = 0x0C, .data[8] = 0x77, .data[9] = 0x70,
1739 .data[10] = 0x20, .data[11] = 0x00, },
1740 { .channel = 42, .freq = 5210, .data[0] = 0x69, .data[1] = 0x0C,
1741 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x01, .data[5] = 0x04,
1742 .data[6] = 0x0B, .data[7] = 0x0C, .data[8] = 0x77, .data[9] = 0x70,
1743 .data[10] = 0x20, .data[11] = 0x00, },
1744 { .channel = 44, .freq = 5220, .data[0] = 0x69, .data[1] = 0x0C,
1745 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x04,
1746 .data[6] = 0x0B, .data[7] = 0x0B, .data[8] = 0x77, .data[9] = 0x60,
1747 .data[10] = 0x20, .data[11] = 0x00, },
1748 { .channel = 46, .freq = 5230, .data[0] = 0x69, .data[1] = 0x0C,
1749 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x03,
1750 .data[6] = 0x0A, .data[7] = 0x0B, .data[8] = 0x77, .data[9] = 0x60,
1751 .data[10] = 0x20, .data[11] = 0x00, },
1752 { .channel = 48, .freq = 5240, .data[0] = 0x69, .data[1] = 0x0C,
1753 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x03,
1754 .data[6] = 0x0A, .data[7] = 0x0A, .data[8] = 0x77, .data[9] = 0x60,
1755 .data[10] = 0x20, .data[11] = 0x00, },
1756 { .channel = 52, .freq = 5260, .data[0] = 0x68, .data[1] = 0x0C,
1757 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x02,
1758 .data[6] = 0x09, .data[7] = 0x09, .data[8] = 0x77, .data[9] = 0x60,
1759 .data[10] = 0x20, .data[11] = 0x00, },
1760 { .channel = 56, .freq = 5280, .data[0] = 0x68, .data[1] = 0x0C,
1761 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x01,
1762 .data[6] = 0x08, .data[7] = 0x08, .data[8] = 0x77, .data[9] = 0x50,
1763 .data[10] = 0x10, .data[11] = 0x00, },
1764 { .channel = 60, .freq = 5300, .data[0] = 0x68, .data[1] = 0x0C,
1765 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x01,
1766 .data[6] = 0x08, .data[7] = 0x08, .data[8] = 0x77, .data[9] = 0x50,
1767 .data[10] = 0x10, .data[11] = 0x00, },
1768 { .channel = 64, .freq = 5320, .data[0] = 0x67, .data[1] = 0x0C,
1769 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1770 .data[6] = 0x08, .data[7] = 0x08, .data[8] = 0x77, .data[9] = 0x50,
1771 .data[10] = 0x10, .data[11] = 0x00, },
1772 { .channel = 100, .freq = 5500, .data[0] = 0x64, .data[1] = 0x0C,
1773 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1774 .data[6] = 0x02, .data[7] = 0x01, .data[8] = 0x77, .data[9] = 0x20,
1775 .data[10] = 0x00, .data[11] = 0x00, },
1776 { .channel = 104, .freq = 5520, .data[0] = 0x64, .data[1] = 0x0C,
1777 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1778 .data[6] = 0x01, .data[7] = 0x01, .data[8] = 0x77, .data[9] = 0x20,
1779 .data[10] = 0x00, .data[11] = 0x00, },
1780 { .channel = 108, .freq = 5540, .data[0] = 0x63, .data[1] = 0x0C,
1781 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1782 .data[6] = 0x01, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x10,
1783 .data[10] = 0x00, .data[11] = 0x00, },
1784 { .channel = 112, .freq = 5560, .data[0] = 0x63, .data[1] = 0x0C,
1785 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1786 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x10,
1787 .data[10] = 0x00, .data[11] = 0x00, },
1788 { .channel = 116, .freq = 5580, .data[0] = 0x62, .data[1] = 0x0C,
1789 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1790 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x10,
1791 .data[10] = 0x00, .data[11] = 0x00, },
1792 { .channel = 120, .freq = 5600, .data[0] = 0x62, .data[1] = 0x0C,
1793 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1794 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
1795 .data[10] = 0x00, .data[11] = 0x00, },
1796 { .channel = 124, .freq = 5620, .data[0] = 0x62, .data[1] = 0x0C,
1797 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1798 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
1799 .data[10] = 0x00, .data[11] = 0x00, },
1800 { .channel = 128, .freq = 5640, .data[0] = 0x61, .data[1] = 0x0C,
1801 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1802 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
1803 .data[10] = 0x00, .data[11] = 0x00, },
1804 { .channel = 132, .freq = 5660, .data[0] = 0x61, .data[1] = 0x0C,
1805 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1806 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
1807 .data[10] = 0x00, .data[11] = 0x00, },
1808 { .channel = 136, .freq = 5680, .data[0] = 0x61, .data[1] = 0x0C,
1809 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1810 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
1811 .data[10] = 0x00, .data[11] = 0x00, },
1812 { .channel = 140, .freq = 5700, .data[0] = 0x60, .data[1] = 0x0C,
1813 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1814 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
1815 .data[10] = 0x00, .data[11] = 0x00, },
1816 { .channel = 149, .freq = 5745, .data[0] = 0x60, .data[1] = 0x0C,
1817 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1818 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
1819 .data[10] = 0x00, .data[11] = 0x00, },
1820 { .channel = 153, .freq = 5765, .data[0] = 0x60, .data[1] = 0x0C,
1821 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1822 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
1823 .data[10] = 0x00, .data[11] = 0x00, },
1824 { .channel = 157, .freq = 5785, .data[0] = 0x60, .data[1] = 0x0C,
1825 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1826 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
1827 .data[10] = 0x00, .data[11] = 0x00, },
1828 { .channel = 161, .freq = 5805, .data[0] = 0x60, .data[1] = 0x0C,
1829 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1830 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
1831 .data[10] = 0x00, .data[11] = 0x00, },
1832 { .channel = 165, .freq = 5825, .data[0] = 0x60, .data[1] = 0x0C,
1833 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1834 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
1835 .data[10] = 0x00, .data[11] = 0x00, },
1836 { .channel = 184, .freq = 4920, .data[0] = 0x6E, .data[1] = 0x0C,
1837 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x09, .data[5] = 0x0E,
1838 .data[6] = 0x0F, .data[7] = 0x0F, .data[8] = 0x77, .data[9] = 0xC0,
1839 .data[10] = 0x50, .data[11] = 0x00, },
1840 { .channel = 188, .freq = 4940, .data[0] = 0x6E, .data[1] = 0x0C,
1841 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x09, .data[5] = 0x0D,
1842 .data[6] = 0x0F, .data[7] = 0x0F, .data[8] = 0x77, .data[9] = 0xB0,
1843 .data[10] = 0x50, .data[11] = 0x00, },
1844 { .channel = 192, .freq = 4960, .data[0] = 0x6E, .data[1] = 0x0C,
1845 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x08, .data[5] = 0x0C,
1846 .data[6] = 0x0F, .data[7] = 0x0F, .data[8] = 0x77, .data[9] = 0xB0,
1847 .data[10] = 0x50, .data[11] = 0x00, },
1848 { .channel = 196, .freq = 4980, .data[0] = 0x6D, .data[1] = 0x0C,
1849 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x08, .data[5] = 0x0C,
1850 .data[6] = 0x0F, .data[7] = 0x0F, .data[8] = 0x77, .data[9] = 0xA0,
1851 .data[10] = 0x40, .data[11] = 0x00, },
1852 { .channel = 200, .freq = 5000, .data[0] = 0x6D, .data[1] = 0x0C,
1853 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x08, .data[5] = 0x0B,
1854 .data[6] = 0x0F, .data[7] = 0x0F, .data[8] = 0x77, .data[9] = 0xA0,
1855 .data[10] = 0x40, .data[11] = 0x00, },
1856 { .channel = 204, .freq = 5020, .data[0] = 0x6D, .data[1] = 0x0C,
1857 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x08, .data[5] = 0x0A,
1858 .data[6] = 0x0F, .data[7] = 0x0F, .data[8] = 0x77, .data[9] = 0xA0,
1859 .data[10] = 0x40, .data[11] = 0x00, },
1860 { .channel = 208, .freq = 5040, .data[0] = 0x6C, .data[1] = 0x0C,
1861 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x07, .data[5] = 0x09,
1862 .data[6] = 0x0F, .data[7] = 0x0F, .data[8] = 0x77, .data[9] = 0x90,
1863 .data[10] = 0x40, .data[11] = 0x00, },
1864 { .channel = 212, .freq = 5060, .data[0] = 0x6C, .data[1] = 0x0C,
1865 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x06, .data[5] = 0x08,
1866 .data[6] = 0x0F, .data[7] = 0x0F, .data[8] = 0x77, .data[9] = 0x90,
1867 .data[10] = 0x40, .data[11] = 0x00, },
1868 { .channel = 216, .freq = 5080, .data[0] = 0x6C, .data[1] = 0x0C,
1869 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x05, .data[5] = 0x08,
1870 .data[6] = 0x0F, .data[7] = 0x0F, .data[8] = 0x77, .data[9] = 0x90,
1871 .data[10] = 0x40, .data[11] = 0x00, },
1872 };
1873
1874 static void lpphy_b2062_reset_pll_bias(struct b43_wldev *dev)
1875 {
1876 struct ssb_bus *bus = dev->dev->bus;
1877
1878 b43_radio_write(dev, B2062_S_RFPLL_CTL2, 0xFF);
1879 udelay(20);
1880 if (bus->chip_id == 0x5354) {
1881 b43_radio_write(dev, B2062_N_COMM1, 4);
1882 b43_radio_write(dev, B2062_S_RFPLL_CTL2, 4);
1883 } else {
1884 b43_radio_write(dev, B2062_S_RFPLL_CTL2, 0);
1885 }
1886 udelay(5);
1887 }
1888
1889 static void lpphy_b2062_vco_calib(struct b43_wldev *dev)
1890 {
1891 b43_phy_write(dev, B2062_S_RFPLL_CTL21, 0x42);
1892 b43_phy_write(dev, B2062_S_RFPLL_CTL21, 0x62);
1893 udelay(200);
1894 }
1895
1896 static int lpphy_b2062_tune(struct b43_wldev *dev,
1897 unsigned int channel)
1898 {
1899 struct b43_phy_lp *lpphy = dev->phy.lp;
1900 struct ssb_bus *bus = dev->dev->bus;
1901 const struct b206x_channel *chandata = NULL;
1902 u32 crystal_freq = bus->chipco.pmu.crystalfreq * 1000;
1903 u32 tmp1, tmp2, tmp3, tmp4, tmp5, tmp6, tmp7, tmp8, tmp9;
1904 int i, err = 0;
1905
1906 for (i = 0; i < ARRAY_SIZE(b2062_chantbl); i++) {
1907 if (b2062_chantbl[i].channel == channel) {
1908 chandata = &b2062_chantbl[i];
1909 break;
1910 }
1911 }
1912
1913 if (B43_WARN_ON(!chandata))
1914 return -EINVAL;
1915
1916 b43_radio_set(dev, B2062_S_RFPLL_CTL14, 0x04);
1917 b43_radio_write(dev, B2062_N_LGENA_TUNE0, chandata->data[0]);
1918 b43_radio_write(dev, B2062_N_LGENA_TUNE2, chandata->data[1]);
1919 b43_radio_write(dev, B2062_N_LGENA_TUNE3, chandata->data[2]);
1920 b43_radio_write(dev, B2062_N_TX_TUNE, chandata->data[3]);
1921 b43_radio_write(dev, B2062_S_LGENG_CTL1, chandata->data[4]);
1922 b43_radio_write(dev, B2062_N_LGENA_CTL5, chandata->data[5]);
1923 b43_radio_write(dev, B2062_N_LGENA_CTL6, chandata->data[6]);
1924 b43_radio_write(dev, B2062_N_TX_PGA, chandata->data[7]);
1925 b43_radio_write(dev, B2062_N_TX_PAD, chandata->data[8]);
1926
1927 tmp1 = crystal_freq / 1000;
1928 tmp2 = lpphy->pdiv * 1000;
1929 b43_radio_write(dev, B2062_S_RFPLL_CTL33, 0xCC);
1930 b43_radio_write(dev, B2062_S_RFPLL_CTL34, 0x07);
1931 lpphy_b2062_reset_pll_bias(dev);
1932 tmp3 = tmp2 * channel2freq_lp(channel);
1933 if (channel2freq_lp(channel) < 4000)
1934 tmp3 *= 2;
1935 tmp4 = 48 * tmp1;
1936 tmp6 = tmp3 / tmp4;
1937 tmp7 = tmp3 % tmp4;
1938 b43_radio_write(dev, B2062_S_RFPLL_CTL26, tmp6);
1939 tmp5 = tmp7 * 0x100;
1940 tmp6 = tmp5 / tmp4;
1941 tmp7 = tmp5 % tmp4;
1942 b43_radio_write(dev, B2062_S_RFPLL_CTL27, tmp6);
1943 tmp5 = tmp7 * 0x100;
1944 tmp6 = tmp5 / tmp4;
1945 tmp7 = tmp5 % tmp4;
1946 b43_radio_write(dev, B2062_S_RFPLL_CTL28, tmp6);
1947 tmp5 = tmp7 * 0x100;
1948 tmp6 = tmp5 / tmp4;
1949 tmp7 = tmp5 % tmp4;
1950 b43_radio_write(dev, B2062_S_RFPLL_CTL29, tmp6 + ((2 * tmp7) / tmp4));
1951 tmp8 = b43_phy_read(dev, B2062_S_RFPLL_CTL19);
1952 tmp9 = ((2 * tmp3 * (tmp8 + 1)) + (3 * tmp1)) / (6 * tmp1);
1953 b43_radio_write(dev, B2062_S_RFPLL_CTL23, tmp9 >> 8);
1954 b43_radio_write(dev, B2062_S_RFPLL_CTL24, tmp9 & 0xFF);
1955
1956 lpphy_b2062_vco_calib(dev);
1957 if (b43_radio_read(dev, B2062_S_RFPLL_CTL3) & 0x10) {
1958 b43_radio_write(dev, B2062_S_RFPLL_CTL33, 0xFC);
1959 b43_radio_write(dev, B2062_S_RFPLL_CTL34, 0);
1960 lpphy_b2062_reset_pll_bias(dev);
1961 lpphy_b2062_vco_calib(dev);
1962 if (b43_radio_read(dev, B2062_S_RFPLL_CTL3) & 0x10)
1963 err = -EIO;
1964 }
1965
1966 b43_radio_mask(dev, B2062_S_RFPLL_CTL14, ~0x04);
1967 return err;
1968 }
1969
1970 static void lpphy_japan_filter(struct b43_wldev *dev, int channel)
1971 {
1972 struct b43_phy_lp *lpphy = dev->phy.lp;
1973 u16 tmp = (channel == 14); //SPEC FIXME check japanwidefilter!
1974
1975 if (dev->phy.rev < 2) { //SPEC FIXME Isn't this rev0/1-specific?
1976 b43_phy_maskset(dev, B43_LPPHY_LP_PHY_CTL, 0xFCFF, tmp << 9);
1977 if ((dev->phy.rev == 1) && (lpphy->rc_cap))
1978 lpphy_set_rc_cap(dev);
1979 } else {
1980 b43_radio_write(dev, B2063_TX_BB_SP3, 0x3F);
1981 }
1982 }
1983
1984 static void lpphy_b2063_vco_calib(struct b43_wldev *dev)
1985 {
1986 u16 tmp;
1987
1988 b43_phy_mask(dev, B2063_PLL_SP1, ~0x40);
1989 tmp = b43_phy_read(dev, B2063_PLL_JTAG_CALNRST) & 0xF8;
1990 b43_phy_write(dev, B2063_PLL_JTAG_CALNRST, tmp);
1991 udelay(1);
1992 b43_phy_write(dev, B2063_PLL_JTAG_CALNRST, tmp | 0x4);
1993 udelay(1);
1994 b43_phy_write(dev, B2063_PLL_JTAG_CALNRST, tmp | 0x6);
1995 udelay(1);
1996 b43_phy_write(dev, B2063_PLL_JTAG_CALNRST, tmp | 0x7);
1997 udelay(300);
1998 b43_phy_set(dev, B2063_PLL_SP1, 0x40);
1999 }
2000
2001 static int lpphy_b2063_tune(struct b43_wldev *dev,
2002 unsigned int channel)
2003 {
2004 struct ssb_bus *bus = dev->dev->bus;
2005
2006 static const struct b206x_channel *chandata = NULL;
2007 u32 crystal_freq = bus->chipco.pmu.crystalfreq * 1000;
2008 u32 freqref, vco_freq, val1, val2, val3, timeout, timeoutref, count;
2009 u16 old_comm15, scale;
2010 u32 tmp1, tmp2, tmp3, tmp4, tmp5, tmp6;
2011 int i, div = (crystal_freq <= 26000000 ? 1 : 2);
2012
2013 for (i = 0; i < ARRAY_SIZE(b2063_chantbl); i++) {
2014 if (b2063_chantbl[i].channel == channel) {
2015 chandata = &b2063_chantbl[i];
2016 break;
2017 }
2018 }
2019
2020 if (B43_WARN_ON(!chandata))
2021 return -EINVAL;
2022
2023 b43_radio_write(dev, B2063_LOGEN_VCOBUF1, chandata->data[0]);
2024 b43_radio_write(dev, B2063_LOGEN_MIXER2, chandata->data[1]);
2025 b43_radio_write(dev, B2063_LOGEN_BUF2, chandata->data[2]);
2026 b43_radio_write(dev, B2063_LOGEN_RCCR1, chandata->data[3]);
2027 b43_radio_write(dev, B2063_A_RX_1ST3, chandata->data[4]);
2028 b43_radio_write(dev, B2063_A_RX_2ND1, chandata->data[5]);
2029 b43_radio_write(dev, B2063_A_RX_2ND4, chandata->data[6]);
2030 b43_radio_write(dev, B2063_A_RX_2ND7, chandata->data[7]);
2031 b43_radio_write(dev, B2063_A_RX_PS6, chandata->data[8]);
2032 b43_radio_write(dev, B2063_TX_RF_CTL2, chandata->data[9]);
2033 b43_radio_write(dev, B2063_TX_RF_CTL5, chandata->data[10]);
2034 b43_radio_write(dev, B2063_PA_CTL11, chandata->data[11]);
2035
2036 old_comm15 = b43_radio_read(dev, B2063_COMM15);
2037 b43_radio_set(dev, B2063_COMM15, 0x1E);
2038
2039 if (chandata->freq > 4000) /* spec says 2484, but 4000 is safer */
2040 vco_freq = chandata->freq << 1;
2041 else
2042 vco_freq = chandata->freq << 2;
2043
2044 freqref = crystal_freq * 3;
2045 val1 = lpphy_qdiv_roundup(crystal_freq, 1000000, 16);
2046 val2 = lpphy_qdiv_roundup(crystal_freq, 1000000 * div, 16);
2047 val3 = lpphy_qdiv_roundup(vco_freq, 3, 16);
2048 timeout = ((((8 * crystal_freq) / (div * 5000000)) + 1) >> 1) - 1;
2049 b43_radio_write(dev, B2063_PLL_JTAG_PLL_VCO_CALIB3, 0x2);
2050 b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_VCO_CALIB6,
2051 0xFFF8, timeout >> 2);
2052 b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_VCO_CALIB7,
2053 0xFF9F,timeout << 5);
2054
2055 timeoutref = ((((8 * crystal_freq) / (div * (timeout + 1))) +
2056 999999) / 1000000) + 1;
2057 b43_radio_write(dev, B2063_PLL_JTAG_PLL_VCO_CALIB5, timeoutref);
2058
2059 count = lpphy_qdiv_roundup(val3, val2 + 16, 16);
2060 count *= (timeout + 1) * (timeoutref + 1);
2061 count--;
2062 b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_VCO_CALIB7,
2063 0xF0, count >> 8);
2064 b43_radio_write(dev, B2063_PLL_JTAG_PLL_VCO_CALIB8, count & 0xFF);
2065
2066 tmp1 = ((val3 * 62500) / freqref) << 4;
2067 tmp2 = ((val3 * 62500) % freqref) << 4;
2068 while (tmp2 >= freqref) {
2069 tmp1++;
2070 tmp2 -= freqref;
2071 }
2072 b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_SG1, 0xFFE0, tmp1 >> 4);
2073 b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_SG2, 0xFE0F, tmp1 << 4);
2074 b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_SG2, 0xFFF0, tmp1 >> 16);
2075 b43_radio_write(dev, B2063_PLL_JTAG_PLL_SG3, (tmp2 >> 8) & 0xFF);
2076 b43_radio_write(dev, B2063_PLL_JTAG_PLL_SG4, tmp2 & 0xFF);
2077
2078 b43_radio_write(dev, B2063_PLL_JTAG_PLL_LF1, 0xB9);
2079 b43_radio_write(dev, B2063_PLL_JTAG_PLL_LF2, 0x88);
2080 b43_radio_write(dev, B2063_PLL_JTAG_PLL_LF3, 0x28);
2081 b43_radio_write(dev, B2063_PLL_JTAG_PLL_LF4, 0x63);
2082
2083 tmp3 = ((41 * (val3 - 3000)) /1200) + 27;
2084 tmp4 = lpphy_qdiv_roundup(132000 * tmp1, 8451, 16);
2085
2086 if ((tmp4 + tmp3 - 1) / tmp3 > 60) {
2087 scale = 1;
2088 tmp5 = ((tmp4 + tmp3) / (tmp3 << 1)) - 8;
2089 } else {
2090 scale = 0;
2091 tmp5 = ((tmp4 + (tmp3 >> 1)) / tmp3) - 8;
2092 }
2093 b43_phy_maskset(dev, B2063_PLL_JTAG_PLL_CP2, 0xFFC0, tmp5);
2094 b43_phy_maskset(dev, B2063_PLL_JTAG_PLL_CP2, 0xFFBF, scale << 6);
2095
2096 tmp6 = lpphy_qdiv_roundup(100 * val1, val3, 16);
2097 tmp6 *= (tmp5 * 8) * (scale + 1);
2098 if (tmp6 > 150)
2099 tmp6 = 0;
2100
2101 b43_phy_maskset(dev, B2063_PLL_JTAG_PLL_CP3, 0xFFE0, tmp6);
2102 b43_phy_maskset(dev, B2063_PLL_JTAG_PLL_CP3, 0xFFDF, scale << 5);
2103
2104 b43_phy_maskset(dev, B2063_PLL_JTAG_PLL_XTAL_12, 0xFFFB, 0x4);
2105 if (crystal_freq > 26000000)
2106 b43_phy_set(dev, B2063_PLL_JTAG_PLL_XTAL_12, 0x2);
2107 else
2108 b43_phy_mask(dev, B2063_PLL_JTAG_PLL_XTAL_12, 0xFD);
2109
2110 if (val1 == 45)
2111 b43_phy_set(dev, B2063_PLL_JTAG_PLL_VCO1, 0x2);
2112 else
2113 b43_phy_mask(dev, B2063_PLL_JTAG_PLL_VCO1, 0xFD);
2114
2115 b43_phy_set(dev, B2063_PLL_SP2, 0x3);
2116 udelay(1);
2117 b43_phy_mask(dev, B2063_PLL_SP2, 0xFFFC);
2118 lpphy_b2063_vco_calib(dev);
2119 b43_radio_write(dev, B2063_COMM15, old_comm15);
2120
2121 return 0;
2122 }
2123
2124 static int b43_lpphy_op_switch_channel(struct b43_wldev *dev,
2125 unsigned int new_channel)
2126 {
2127 int err;
2128
2129 b43_write16(dev, B43_MMIO_CHANNEL, new_channel);
2130
2131 if (dev->phy.radio_ver == 0x2063) {
2132 err = lpphy_b2063_tune(dev, new_channel);
2133 if (err)
2134 return err;
2135 } else {
2136 err = lpphy_b2062_tune(dev, new_channel);
2137 if (err)
2138 return err;
2139 lpphy_japan_filter(dev, new_channel);
2140 lpphy_adjust_gain_table(dev, channel2freq_lp(new_channel));
2141 }
2142
2143 return 0;
2144 }
2145
2146 static int b43_lpphy_op_init(struct b43_wldev *dev)
2147 {
2148 int err;
2149
2150 lpphy_read_band_sprom(dev); //FIXME should this be in prepare_structs?
2151 lpphy_baseband_init(dev);
2152 lpphy_radio_init(dev);
2153 lpphy_calibrate_rc(dev);
2154 err = b43_lpphy_op_switch_channel(dev,
2155 b43_lpphy_op_get_default_chan(dev));
2156 if (err) {
2157 b43dbg(dev->wl, "Switch to init channel failed, error = %d.\n",
2158 err);
2159 }
2160 lpphy_tx_pctl_init(dev);
2161 lpphy_calibration(dev);
2162 //TODO ACI init
2163
2164 return 0;
2165 }
2166
2167 static void b43_lpphy_op_set_rx_antenna(struct b43_wldev *dev, int antenna)
2168 {
2169 //TODO
2170 }
2171
2172 static void b43_lpphy_op_adjust_txpower(struct b43_wldev *dev)
2173 {
2174 //TODO
2175 }
2176
2177 static enum b43_txpwr_result b43_lpphy_op_recalc_txpower(struct b43_wldev *dev,
2178 bool ignore_tssi)
2179 {
2180 //TODO
2181 return B43_TXPWR_RES_DONE;
2182 }
2183
2184 const struct b43_phy_operations b43_phyops_lp = {
2185 .allocate = b43_lpphy_op_allocate,
2186 .free = b43_lpphy_op_free,
2187 .prepare_structs = b43_lpphy_op_prepare_structs,
2188 .init = b43_lpphy_op_init,
2189 .phy_read = b43_lpphy_op_read,
2190 .phy_write = b43_lpphy_op_write,
2191 .radio_read = b43_lpphy_op_radio_read,
2192 .radio_write = b43_lpphy_op_radio_write,
2193 .software_rfkill = b43_lpphy_op_software_rfkill,
2194 .switch_analog = b43_phyop_switch_analog_generic,
2195 .switch_channel = b43_lpphy_op_switch_channel,
2196 .get_default_chan = b43_lpphy_op_get_default_chan,
2197 .set_rx_antenna = b43_lpphy_op_set_rx_antenna,
2198 .recalc_txpower = b43_lpphy_op_recalc_txpower,
2199 .adjust_txpower = b43_lpphy_op_adjust_txpower,
2200 };
Linux kernel - Deliverables
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