3 Broadcom B43 wireless driver
4 IEEE 802.11n PHY support
6 Copyright (c) 2008 Michael Buesch <m@bues.ch>
7 Copyright (c) 2010-2011 Rafał Miłecki <zajec5@gmail.com>
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; see the file COPYING. If not, write to
21 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
22 Boston, MA 02110-1301, USA.
26 #include <linux/delay.h>
27 #include <linux/slab.h>
28 #include <linux/types.h>
32 #include "tables_nphy.h"
33 #include "radio_2055.h"
34 #include "radio_2056.h"
35 #include "radio_2057.h"
46 struct nphy_iqcal_params
{
65 enum b43_nphy_rf_sequence
{
69 B43_RFSEQ_UPDATE_GAINH
,
70 B43_RFSEQ_UPDATE_GAINL
,
71 B43_RFSEQ_UPDATE_GAINU
,
74 enum n_rf_ctl_over_cmd
{
75 N_RF_CTL_OVER_CMD_RXRF_PU
= 0,
76 N_RF_CTL_OVER_CMD_RX_PU
= 1,
77 N_RF_CTL_OVER_CMD_TX_PU
= 2,
78 N_RF_CTL_OVER_CMD_RX_GAIN
= 3,
79 N_RF_CTL_OVER_CMD_TX_GAIN
= 4,
82 enum n_intc_override
{
83 N_INTC_OVERRIDE_OFF
= 0,
84 N_INTC_OVERRIDE_TRSW
= 1,
85 N_INTC_OVERRIDE_PA
= 2,
86 N_INTC_OVERRIDE_EXT_LNA_PU
= 3,
87 N_INTC_OVERRIDE_EXT_LNA_GAIN
= 4,
105 static inline bool b43_nphy_ipa(struct b43_wldev
*dev
)
107 enum ieee80211_band band
= b43_current_band(dev
->wl
);
108 return ((dev
->phy
.n
->ipa2g_on
&& band
== IEEE80211_BAND_2GHZ
) ||
109 (dev
->phy
.n
->ipa5g_on
&& band
== IEEE80211_BAND_5GHZ
));
112 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCoreGetState */
113 static u8
b43_nphy_get_rx_core_state(struct b43_wldev
*dev
)
115 return (b43_phy_read(dev
, B43_NPHY_RFSEQCA
) & B43_NPHY_RFSEQCA_RXEN
) >>
116 B43_NPHY_RFSEQCA_RXEN_SHIFT
;
119 /**************************************************
120 * RF (just without b43_nphy_rf_ctl_intc_override)
121 **************************************************/
123 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ForceRFSeq */
124 static void b43_nphy_force_rf_sequence(struct b43_wldev
*dev
,
125 enum b43_nphy_rf_sequence seq
)
127 static const u16 trigger
[] = {
128 [B43_RFSEQ_RX2TX
] = B43_NPHY_RFSEQTR_RX2TX
,
129 [B43_RFSEQ_TX2RX
] = B43_NPHY_RFSEQTR_TX2RX
,
130 [B43_RFSEQ_RESET2RX
] = B43_NPHY_RFSEQTR_RST2RX
,
131 [B43_RFSEQ_UPDATE_GAINH
] = B43_NPHY_RFSEQTR_UPGH
,
132 [B43_RFSEQ_UPDATE_GAINL
] = B43_NPHY_RFSEQTR_UPGL
,
133 [B43_RFSEQ_UPDATE_GAINU
] = B43_NPHY_RFSEQTR_UPGU
,
136 u16 seq_mode
= b43_phy_read(dev
, B43_NPHY_RFSEQMODE
);
138 B43_WARN_ON(seq
>= ARRAY_SIZE(trigger
));
140 b43_phy_set(dev
, B43_NPHY_RFSEQMODE
,
141 B43_NPHY_RFSEQMODE_CAOVER
| B43_NPHY_RFSEQMODE_TROVER
);
142 b43_phy_set(dev
, B43_NPHY_RFSEQTR
, trigger
[seq
]);
143 for (i
= 0; i
< 200; i
++) {
144 if (!(b43_phy_read(dev
, B43_NPHY_RFSEQST
) & trigger
[seq
]))
148 b43err(dev
->wl
, "RF sequence status timeout\n");
150 b43_phy_write(dev
, B43_NPHY_RFSEQMODE
, seq_mode
);
153 static void b43_nphy_rf_ctl_override_rev19(struct b43_wldev
*dev
, u16 field
,
154 u16 value
, u8 core
, bool off
,
160 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverrideRev7 */
161 static void b43_nphy_rf_ctl_override_rev7(struct b43_wldev
*dev
, u16 field
,
162 u16 value
, u8 core
, bool off
,
165 struct b43_phy
*phy
= &dev
->phy
;
166 const struct nphy_rf_control_override_rev7
*e
;
167 u16 en_addrs
[3][2] = {
168 { 0x0E7, 0x0EC }, { 0x342, 0x343 }, { 0x346, 0x347 }
175 if (phy
->rev
>= 19 || phy
->rev
< 3) {
180 /* Remember: we can get NULL! */
181 e
= b43_nphy_get_rf_ctl_over_rev7(dev
, field
, override
);
183 for (i
= 0; i
< 2; i
++) {
184 if (override
>= ARRAY_SIZE(en_addrs
)) {
185 b43err(dev
->wl
, "Invalid override value %d\n", override
);
188 en_addr
= en_addrs
[override
][i
];
191 val_addr
= (i
== 0) ? e
->val_addr_core0
: e
->val_addr_core1
;
194 b43_phy_mask(dev
, en_addr
, ~en_mask
);
195 if (e
) /* Do it safer, better than wl */
196 b43_phy_mask(dev
, val_addr
, ~e
->val_mask
);
198 if (!core
|| (core
& (1 << i
))) {
199 b43_phy_set(dev
, en_addr
, en_mask
);
201 b43_phy_maskset(dev
, val_addr
, ~e
->val_mask
, (value
<< e
->val_shift
));
207 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverideOneToMany */
208 static void b43_nphy_rf_ctl_override_one_to_many(struct b43_wldev
*dev
,
209 enum n_rf_ctl_over_cmd cmd
,
210 u16 value
, u8 core
, bool off
)
212 struct b43_phy
*phy
= &dev
->phy
;
215 B43_WARN_ON(phy
->rev
< 7);
218 case N_RF_CTL_OVER_CMD_RXRF_PU
:
219 b43_nphy_rf_ctl_override_rev7(dev
, 0x20, value
, core
, off
, 1);
220 b43_nphy_rf_ctl_override_rev7(dev
, 0x10, value
, core
, off
, 1);
221 b43_nphy_rf_ctl_override_rev7(dev
, 0x08, value
, core
, off
, 1);
223 case N_RF_CTL_OVER_CMD_RX_PU
:
224 b43_nphy_rf_ctl_override_rev7(dev
, 0x4, value
, core
, off
, 1);
225 b43_nphy_rf_ctl_override_rev7(dev
, 0x2, value
, core
, off
, 1);
226 b43_nphy_rf_ctl_override_rev7(dev
, 0x1, value
, core
, off
, 1);
227 b43_nphy_rf_ctl_override_rev7(dev
, 0x2, value
, core
, off
, 2);
228 b43_nphy_rf_ctl_override_rev7(dev
, 0x0800, 0, core
, off
, 1);
230 case N_RF_CTL_OVER_CMD_TX_PU
:
231 b43_nphy_rf_ctl_override_rev7(dev
, 0x4, value
, core
, off
, 0);
232 b43_nphy_rf_ctl_override_rev7(dev
, 0x2, value
, core
, off
, 1);
233 b43_nphy_rf_ctl_override_rev7(dev
, 0x1, value
, core
, off
, 2);
234 b43_nphy_rf_ctl_override_rev7(dev
, 0x0800, 1, core
, off
, 1);
236 case N_RF_CTL_OVER_CMD_RX_GAIN
:
238 b43_nphy_rf_ctl_override_rev7(dev
, 0x0800, tmp
, core
, off
, 0);
240 b43_nphy_rf_ctl_override_rev7(dev
, 0x6000, tmp
, core
, off
, 0);
242 case N_RF_CTL_OVER_CMD_TX_GAIN
:
243 tmp
= value
& 0x7FFF;
244 b43_nphy_rf_ctl_override_rev7(dev
, 0x1000, tmp
, core
, off
, 0);
246 b43_nphy_rf_ctl_override_rev7(dev
, 0x4000, tmp
, core
, off
, 0);
251 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverride */
252 static void b43_nphy_rf_ctl_override(struct b43_wldev
*dev
, u16 field
,
253 u16 value
, u8 core
, bool off
)
256 u8 index
= fls(field
);
257 u8 addr
, en_addr
, val_addr
;
258 /* we expect only one bit set */
259 B43_WARN_ON(field
& (~(1 << (index
- 1))));
261 if (dev
->phy
.rev
>= 3) {
262 const struct nphy_rf_control_override_rev3
*rf_ctrl
;
263 for (i
= 0; i
< 2; i
++) {
264 if (index
== 0 || index
== 16) {
266 "Unsupported RF Ctrl Override call\n");
270 rf_ctrl
= &tbl_rf_control_override_rev3
[index
- 1];
271 en_addr
= B43_PHY_N((i
== 0) ?
272 rf_ctrl
->en_addr0
: rf_ctrl
->en_addr1
);
273 val_addr
= B43_PHY_N((i
== 0) ?
274 rf_ctrl
->val_addr0
: rf_ctrl
->val_addr1
);
277 b43_phy_mask(dev
, en_addr
, ~(field
));
278 b43_phy_mask(dev
, val_addr
,
279 ~(rf_ctrl
->val_mask
));
281 if (core
== 0 || ((1 << i
) & core
)) {
282 b43_phy_set(dev
, en_addr
, field
);
283 b43_phy_maskset(dev
, val_addr
,
284 ~(rf_ctrl
->val_mask
),
285 (value
<< rf_ctrl
->val_shift
));
290 const struct nphy_rf_control_override_rev2
*rf_ctrl
;
292 b43_phy_mask(dev
, B43_NPHY_RFCTL_OVER
, ~(field
));
295 b43_phy_set(dev
, B43_NPHY_RFCTL_OVER
, field
);
298 for (i
= 0; i
< 2; i
++) {
299 if (index
<= 1 || index
== 16) {
301 "Unsupported RF Ctrl Override call\n");
305 if (index
== 2 || index
== 10 ||
306 (index
>= 13 && index
<= 15)) {
310 rf_ctrl
= &tbl_rf_control_override_rev2
[index
- 2];
311 addr
= B43_PHY_N((i
== 0) ?
312 rf_ctrl
->addr0
: rf_ctrl
->addr1
);
315 b43_phy_maskset(dev
, addr
, ~(rf_ctrl
->bmask
),
316 (value
<< rf_ctrl
->shift
));
318 b43_phy_set(dev
, B43_NPHY_RFCTL_OVER
, 0x1);
319 b43_phy_set(dev
, B43_NPHY_RFCTL_CMD
,
320 B43_NPHY_RFCTL_CMD_START
);
322 b43_phy_mask(dev
, B43_NPHY_RFCTL_OVER
, 0xFFFE);
327 static void b43_nphy_rf_ctl_intc_override_rev7(struct b43_wldev
*dev
,
328 enum n_intc_override intc_override
,
329 u16 value
, u8 core_sel
)
331 u16 reg
, tmp
, tmp2
, val
;
334 /* TODO: What about rev19+? Revs 3+ and 7+ are a bit similar */
336 for (core
= 0; core
< 2; core
++) {
337 if ((core_sel
== 1 && core
!= 0) ||
338 (core_sel
== 2 && core
!= 1))
341 reg
= (core
== 0) ? B43_NPHY_RFCTL_INTC1
: B43_NPHY_RFCTL_INTC2
;
343 switch (intc_override
) {
344 case N_INTC_OVERRIDE_OFF
:
345 b43_phy_write(dev
, reg
, 0);
346 b43_phy_mask(dev
, 0x2ff, ~0x2000);
347 b43_nphy_force_rf_sequence(dev
, B43_RFSEQ_RESET2RX
);
349 case N_INTC_OVERRIDE_TRSW
:
350 b43_phy_maskset(dev
, reg
, ~0xC0, value
<< 6);
351 b43_phy_set(dev
, reg
, 0x400);
353 b43_phy_mask(dev
, 0x2ff, ~0xC000 & 0xFFFF);
354 b43_phy_set(dev
, 0x2ff, 0x2000);
355 b43_phy_set(dev
, 0x2ff, 0x0001);
357 case N_INTC_OVERRIDE_PA
:
359 if (b43_current_band(dev
->wl
) == IEEE80211_BAND_5GHZ
)
363 b43_phy_maskset(dev
, reg
, ~tmp
, val
);
364 b43_phy_set(dev
, reg
, 0x1000);
366 case N_INTC_OVERRIDE_EXT_LNA_PU
:
367 if (b43_current_band(dev
->wl
) == IEEE80211_BAND_5GHZ
) {
376 b43_phy_maskset(dev
, reg
, ~tmp
, val
);
377 b43_phy_mask(dev
, reg
, ~tmp2
);
379 case N_INTC_OVERRIDE_EXT_LNA_GAIN
:
380 if (b43_current_band(dev
->wl
) == IEEE80211_BAND_5GHZ
) {
389 b43_phy_maskset(dev
, reg
, ~tmp
, val
);
390 b43_phy_mask(dev
, reg
, ~tmp2
);
396 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlIntcOverride */
397 static void b43_nphy_rf_ctl_intc_override(struct b43_wldev
*dev
,
398 enum n_intc_override intc_override
,
404 if (dev
->phy
.rev
>= 7) {
405 b43_nphy_rf_ctl_intc_override_rev7(dev
, intc_override
, value
,
410 B43_WARN_ON(dev
->phy
.rev
< 3);
412 for (i
= 0; i
< 2; i
++) {
413 if ((core
== 1 && i
== 1) || (core
== 2 && !i
))
417 B43_NPHY_RFCTL_INTC1
: B43_NPHY_RFCTL_INTC2
;
418 b43_phy_set(dev
, reg
, 0x400);
420 switch (intc_override
) {
421 case N_INTC_OVERRIDE_OFF
:
422 b43_phy_write(dev
, reg
, 0);
423 b43_nphy_force_rf_sequence(dev
, B43_RFSEQ_RESET2RX
);
425 case N_INTC_OVERRIDE_TRSW
:
427 b43_phy_maskset(dev
, B43_NPHY_RFCTL_INTC1
,
428 0xFC3F, (value
<< 6));
429 b43_phy_maskset(dev
, B43_NPHY_TXF_40CO_B1S1
,
431 b43_phy_set(dev
, B43_NPHY_RFCTL_CMD
,
432 B43_NPHY_RFCTL_CMD_START
);
433 for (j
= 0; j
< 100; j
++) {
434 if (!(b43_phy_read(dev
, B43_NPHY_RFCTL_CMD
) & B43_NPHY_RFCTL_CMD_START
)) {
442 "intc override timeout\n");
443 b43_phy_mask(dev
, B43_NPHY_TXF_40CO_B1S1
,
446 b43_phy_maskset(dev
, B43_NPHY_RFCTL_INTC2
,
447 0xFC3F, (value
<< 6));
448 b43_phy_maskset(dev
, B43_NPHY_RFCTL_OVER
,
450 b43_phy_set(dev
, B43_NPHY_RFCTL_CMD
,
451 B43_NPHY_RFCTL_CMD_RXTX
);
452 for (j
= 0; j
< 100; j
++) {
453 if (!(b43_phy_read(dev
, B43_NPHY_RFCTL_CMD
) & B43_NPHY_RFCTL_CMD_RXTX
)) {
461 "intc override timeout\n");
462 b43_phy_mask(dev
, B43_NPHY_RFCTL_OVER
,
466 case N_INTC_OVERRIDE_PA
:
467 if (b43_current_band(dev
->wl
) == IEEE80211_BAND_5GHZ
) {
474 b43_phy_maskset(dev
, reg
, ~tmp
, val
);
476 case N_INTC_OVERRIDE_EXT_LNA_PU
:
477 if (b43_current_band(dev
->wl
) == IEEE80211_BAND_5GHZ
) {
484 b43_phy_maskset(dev
, reg
, ~tmp
, val
);
486 case N_INTC_OVERRIDE_EXT_LNA_GAIN
:
487 if (b43_current_band(dev
->wl
) == IEEE80211_BAND_5GHZ
) {
494 b43_phy_maskset(dev
, reg
, ~tmp
, val
);
500 /**************************************************
502 **************************************************/
504 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
505 static void b43_nphy_write_clip_detection(struct b43_wldev
*dev
,
508 b43_phy_write(dev
, B43_NPHY_C1_CLIP1THRES
, clip_st
[0]);
509 b43_phy_write(dev
, B43_NPHY_C2_CLIP1THRES
, clip_st
[1]);
512 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
513 static void b43_nphy_read_clip_detection(struct b43_wldev
*dev
, u16
*clip_st
)
515 clip_st
[0] = b43_phy_read(dev
, B43_NPHY_C1_CLIP1THRES
);
516 clip_st
[1] = b43_phy_read(dev
, B43_NPHY_C2_CLIP1THRES
);
519 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/classifier */
520 static u16
b43_nphy_classifier(struct b43_wldev
*dev
, u16 mask
, u16 val
)
524 if (dev
->dev
->core_rev
== 16)
525 b43_mac_suspend(dev
);
527 tmp
= b43_phy_read(dev
, B43_NPHY_CLASSCTL
);
528 tmp
&= (B43_NPHY_CLASSCTL_CCKEN
| B43_NPHY_CLASSCTL_OFDMEN
|
529 B43_NPHY_CLASSCTL_WAITEDEN
);
532 b43_phy_maskset(dev
, B43_NPHY_CLASSCTL
, 0xFFF8, tmp
);
534 if (dev
->dev
->core_rev
== 16)
540 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CCA */
541 static void b43_nphy_reset_cca(struct b43_wldev
*dev
)
545 b43_phy_force_clock(dev
, 1);
546 bbcfg
= b43_phy_read(dev
, B43_NPHY_BBCFG
);
547 b43_phy_write(dev
, B43_NPHY_BBCFG
, bbcfg
| B43_NPHY_BBCFG_RSTCCA
);
549 b43_phy_write(dev
, B43_NPHY_BBCFG
, bbcfg
& ~B43_NPHY_BBCFG_RSTCCA
);
550 b43_phy_force_clock(dev
, 0);
551 b43_nphy_force_rf_sequence(dev
, B43_RFSEQ_RESET2RX
);
554 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/carriersearch */
555 static void b43_nphy_stay_in_carrier_search(struct b43_wldev
*dev
, bool enable
)
557 struct b43_phy
*phy
= &dev
->phy
;
558 struct b43_phy_n
*nphy
= phy
->n
;
561 static const u16 clip
[] = { 0xFFFF, 0xFFFF };
562 if (nphy
->deaf_count
++ == 0) {
563 nphy
->classifier_state
= b43_nphy_classifier(dev
, 0, 0);
564 b43_nphy_classifier(dev
, 0x7,
565 B43_NPHY_CLASSCTL_WAITEDEN
);
566 b43_nphy_read_clip_detection(dev
, nphy
->clip_state
);
567 b43_nphy_write_clip_detection(dev
, clip
);
569 b43_nphy_reset_cca(dev
);
571 if (--nphy
->deaf_count
== 0) {
572 b43_nphy_classifier(dev
, 0x7, nphy
->classifier_state
);
573 b43_nphy_write_clip_detection(dev
, nphy
->clip_state
);
578 /* http://bcm-v4.sipsolutions.net/PHY/N/Read_Lpf_Bw_Ctl */
579 static u16
b43_nphy_read_lpf_ctl(struct b43_wldev
*dev
, u16 offset
)
582 offset
= b43_is_40mhz(dev
) ? 0x159 : 0x154;
583 return b43_ntab_read(dev
, B43_NTAB16(7, offset
)) & 0x7;
586 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/AdjustLnaGainTbl */
587 static void b43_nphy_adjust_lna_gain_table(struct b43_wldev
*dev
)
589 struct b43_phy_n
*nphy
= dev
->phy
.n
;
596 static const u16 lna_gain
[4] = { -2, 10, 19, 25 };
598 if (nphy
->hang_avoid
)
599 b43_nphy_stay_in_carrier_search(dev
, 1);
601 if (nphy
->gain_boost
) {
602 if (b43_current_band(dev
->wl
) == IEEE80211_BAND_2GHZ
) {
606 tmp
= 40370 - 315 * dev
->phy
.channel
;
607 gain
[0] = ((tmp
>> 13) + ((tmp
>> 12) & 1));
608 tmp
= 23242 - 224 * dev
->phy
.channel
;
609 gain
[1] = ((tmp
>> 13) + ((tmp
>> 12) & 1));
616 for (i
= 0; i
< 2; i
++) {
617 if (nphy
->elna_gain_config
) {
618 data
[0] = 19 + gain
[i
];
619 data
[1] = 25 + gain
[i
];
620 data
[2] = 25 + gain
[i
];
621 data
[3] = 25 + gain
[i
];
623 data
[0] = lna_gain
[0] + gain
[i
];
624 data
[1] = lna_gain
[1] + gain
[i
];
625 data
[2] = lna_gain
[2] + gain
[i
];
626 data
[3] = lna_gain
[3] + gain
[i
];
628 b43_ntab_write_bulk(dev
, B43_NTAB16(i
, 8), 4, data
);
630 minmax
[i
] = 23 + gain
[i
];
633 b43_phy_maskset(dev
, B43_NPHY_C1_MINMAX_GAIN
, ~B43_NPHY_C1_MINGAIN
,
634 minmax
[0] << B43_NPHY_C1_MINGAIN_SHIFT
);
635 b43_phy_maskset(dev
, B43_NPHY_C2_MINMAX_GAIN
, ~B43_NPHY_C2_MINGAIN
,
636 minmax
[1] << B43_NPHY_C2_MINGAIN_SHIFT
);
638 if (nphy
->hang_avoid
)
639 b43_nphy_stay_in_carrier_search(dev
, 0);
642 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRfSeq */
643 static void b43_nphy_set_rf_sequence(struct b43_wldev
*dev
, u8 cmd
,
644 u8
*events
, u8
*delays
, u8 length
)
646 struct b43_phy_n
*nphy
= dev
->phy
.n
;
648 u8 end
= (dev
->phy
.rev
>= 3) ? 0x1F : 0x0F;
649 u16 offset1
= cmd
<< 4;
650 u16 offset2
= offset1
+ 0x80;
652 if (nphy
->hang_avoid
)
653 b43_nphy_stay_in_carrier_search(dev
, true);
655 b43_ntab_write_bulk(dev
, B43_NTAB8(7, offset1
), length
, events
);
656 b43_ntab_write_bulk(dev
, B43_NTAB8(7, offset2
), length
, delays
);
658 for (i
= length
; i
< 16; i
++) {
659 b43_ntab_write(dev
, B43_NTAB8(7, offset1
+ i
), end
);
660 b43_ntab_write(dev
, B43_NTAB8(7, offset2
+ i
), 1);
663 if (nphy
->hang_avoid
)
664 b43_nphy_stay_in_carrier_search(dev
, false);
667 /**************************************************
669 **************************************************/
671 static void b43_radio_2057_chantab_upload(struct b43_wldev
*dev
,
672 const struct b43_nphy_chantabent_rev7
*e_r7
,
673 const struct b43_nphy_chantabent_rev7_2g
*e_r7_2g
)
676 b43_radio_write(dev
, R2057_VCOCAL_COUNTVAL0
, e_r7_2g
->radio_vcocal_countval0
);
677 b43_radio_write(dev
, R2057_VCOCAL_COUNTVAL1
, e_r7_2g
->radio_vcocal_countval1
);
678 b43_radio_write(dev
, R2057_RFPLL_REFMASTER_SPAREXTALSIZE
, e_r7_2g
->radio_rfpll_refmaster_sparextalsize
);
679 b43_radio_write(dev
, R2057_RFPLL_LOOPFILTER_R1
, e_r7_2g
->radio_rfpll_loopfilter_r1
);
680 b43_radio_write(dev
, R2057_RFPLL_LOOPFILTER_C2
, e_r7_2g
->radio_rfpll_loopfilter_c2
);
681 b43_radio_write(dev
, R2057_RFPLL_LOOPFILTER_C1
, e_r7_2g
->radio_rfpll_loopfilter_c1
);
682 b43_radio_write(dev
, R2057_CP_KPD_IDAC
, e_r7_2g
->radio_cp_kpd_idac
);
683 b43_radio_write(dev
, R2057_RFPLL_MMD0
, e_r7_2g
->radio_rfpll_mmd0
);
684 b43_radio_write(dev
, R2057_RFPLL_MMD1
, e_r7_2g
->radio_rfpll_mmd1
);
685 b43_radio_write(dev
, R2057_VCOBUF_TUNE
, e_r7_2g
->radio_vcobuf_tune
);
686 b43_radio_write(dev
, R2057_LOGEN_MX2G_TUNE
, e_r7_2g
->radio_logen_mx2g_tune
);
687 b43_radio_write(dev
, R2057_LOGEN_INDBUF2G_TUNE
, e_r7_2g
->radio_logen_indbuf2g_tune
);
688 b43_radio_write(dev
, R2057_TXMIX2G_TUNE_BOOST_PU_CORE0
, e_r7_2g
->radio_txmix2g_tune_boost_pu_core0
);
689 b43_radio_write(dev
, R2057_PAD2G_TUNE_PUS_CORE0
, e_r7_2g
->radio_pad2g_tune_pus_core0
);
690 b43_radio_write(dev
, R2057_LNA2G_TUNE_CORE0
, e_r7_2g
->radio_lna2g_tune_core0
);
691 b43_radio_write(dev
, R2057_TXMIX2G_TUNE_BOOST_PU_CORE1
, e_r7_2g
->radio_txmix2g_tune_boost_pu_core1
);
692 b43_radio_write(dev
, R2057_PAD2G_TUNE_PUS_CORE1
, e_r7_2g
->radio_pad2g_tune_pus_core1
);
693 b43_radio_write(dev
, R2057_LNA2G_TUNE_CORE1
, e_r7_2g
->radio_lna2g_tune_core1
);
696 b43_radio_write(dev
, R2057_VCOCAL_COUNTVAL0
, e_r7
->radio_vcocal_countval0
);
697 b43_radio_write(dev
, R2057_VCOCAL_COUNTVAL1
, e_r7
->radio_vcocal_countval1
);
698 b43_radio_write(dev
, R2057_RFPLL_REFMASTER_SPAREXTALSIZE
, e_r7
->radio_rfpll_refmaster_sparextalsize
);
699 b43_radio_write(dev
, R2057_RFPLL_LOOPFILTER_R1
, e_r7
->radio_rfpll_loopfilter_r1
);
700 b43_radio_write(dev
, R2057_RFPLL_LOOPFILTER_C2
, e_r7
->radio_rfpll_loopfilter_c2
);
701 b43_radio_write(dev
, R2057_RFPLL_LOOPFILTER_C1
, e_r7
->radio_rfpll_loopfilter_c1
);
702 b43_radio_write(dev
, R2057_CP_KPD_IDAC
, e_r7
->radio_cp_kpd_idac
);
703 b43_radio_write(dev
, R2057_RFPLL_MMD0
, e_r7
->radio_rfpll_mmd0
);
704 b43_radio_write(dev
, R2057_RFPLL_MMD1
, e_r7
->radio_rfpll_mmd1
);
705 b43_radio_write(dev
, R2057_VCOBUF_TUNE
, e_r7
->radio_vcobuf_tune
);
706 b43_radio_write(dev
, R2057_LOGEN_MX2G_TUNE
, e_r7
->radio_logen_mx2g_tune
);
707 b43_radio_write(dev
, R2057_LOGEN_MX5G_TUNE
, e_r7
->radio_logen_mx5g_tune
);
708 b43_radio_write(dev
, R2057_LOGEN_INDBUF2G_TUNE
, e_r7
->radio_logen_indbuf2g_tune
);
709 b43_radio_write(dev
, R2057_LOGEN_INDBUF5G_TUNE
, e_r7
->radio_logen_indbuf5g_tune
);
710 b43_radio_write(dev
, R2057_TXMIX2G_TUNE_BOOST_PU_CORE0
, e_r7
->radio_txmix2g_tune_boost_pu_core0
);
711 b43_radio_write(dev
, R2057_PAD2G_TUNE_PUS_CORE0
, e_r7
->radio_pad2g_tune_pus_core0
);
712 b43_radio_write(dev
, R2057_PGA_BOOST_TUNE_CORE0
, e_r7
->radio_pga_boost_tune_core0
);
713 b43_radio_write(dev
, R2057_TXMIX5G_BOOST_TUNE_CORE0
, e_r7
->radio_txmix5g_boost_tune_core0
);
714 b43_radio_write(dev
, R2057_PAD5G_TUNE_MISC_PUS_CORE0
, e_r7
->radio_pad5g_tune_misc_pus_core0
);
715 b43_radio_write(dev
, R2057_LNA2G_TUNE_CORE0
, e_r7
->radio_lna2g_tune_core0
);
716 b43_radio_write(dev
, R2057_LNA5G_TUNE_CORE0
, e_r7
->radio_lna5g_tune_core0
);
717 b43_radio_write(dev
, R2057_TXMIX2G_TUNE_BOOST_PU_CORE1
, e_r7
->radio_txmix2g_tune_boost_pu_core1
);
718 b43_radio_write(dev
, R2057_PAD2G_TUNE_PUS_CORE1
, e_r7
->radio_pad2g_tune_pus_core1
);
719 b43_radio_write(dev
, R2057_PGA_BOOST_TUNE_CORE1
, e_r7
->radio_pga_boost_tune_core1
);
720 b43_radio_write(dev
, R2057_TXMIX5G_BOOST_TUNE_CORE1
, e_r7
->radio_txmix5g_boost_tune_core1
);
721 b43_radio_write(dev
, R2057_PAD5G_TUNE_MISC_PUS_CORE1
, e_r7
->radio_pad5g_tune_misc_pus_core1
);
722 b43_radio_write(dev
, R2057_LNA2G_TUNE_CORE1
, e_r7
->radio_lna2g_tune_core1
);
723 b43_radio_write(dev
, R2057_LNA5G_TUNE_CORE1
, e_r7
->radio_lna5g_tune_core1
);
727 static void b43_radio_2057_setup(struct b43_wldev
*dev
,
728 const struct b43_nphy_chantabent_rev7
*tabent_r7
,
729 const struct b43_nphy_chantabent_rev7_2g
*tabent_r7_2g
)
731 struct b43_phy
*phy
= &dev
->phy
;
733 b43_radio_2057_chantab_upload(dev
, tabent_r7
, tabent_r7_2g
);
735 switch (phy
->radio_rev
) {
738 if (b43_current_band(dev
->wl
) == IEEE80211_BAND_2GHZ
) {
739 b43_radio_write(dev
, R2057_RFPLL_LOOPFILTER_R1
, 0x3f);
740 b43_radio_write(dev
, R2057_CP_KPD_IDAC
, 0x3f);
741 b43_radio_write(dev
, R2057_RFPLL_LOOPFILTER_C1
, 0x8);
742 b43_radio_write(dev
, R2057_RFPLL_LOOPFILTER_C2
, 0x8);
744 b43_radio_write(dev
, R2057_RFPLL_LOOPFILTER_R1
, 0x1f);
745 b43_radio_write(dev
, R2057_CP_KPD_IDAC
, 0x3f);
746 b43_radio_write(dev
, R2057_RFPLL_LOOPFILTER_C1
, 0x8);
747 b43_radio_write(dev
, R2057_RFPLL_LOOPFILTER_C2
, 0x8);
750 case 9: /* e.g. PHY rev 16 */
751 b43_radio_write(dev
, R2057_LOGEN_PTAT_RESETS
, 0x20);
752 b43_radio_write(dev
, R2057_VCOBUF_IDACS
, 0x18);
753 if (b43_current_band(dev
->wl
) == IEEE80211_BAND_5GHZ
) {
754 b43_radio_write(dev
, R2057_LOGEN_PTAT_RESETS
, 0x38);
755 b43_radio_write(dev
, R2057_VCOBUF_IDACS
, 0x0f);
757 if (b43_is_40mhz(dev
)) {
761 R2057_PAD_BIAS_FILTER_BWS_CORE0
,
764 R2057_PAD_BIAS_FILTER_BWS_CORE1
,
769 case 14: /* 2 GHz only */
770 b43_radio_write(dev
, R2057_RFPLL_LOOPFILTER_R1
, 0x1b);
771 b43_radio_write(dev
, R2057_CP_KPD_IDAC
, 0x3f);
772 b43_radio_write(dev
, R2057_RFPLL_LOOPFILTER_C1
, 0x1f);
773 b43_radio_write(dev
, R2057_RFPLL_LOOPFILTER_C2
, 0x1f);
777 if (b43_current_band(dev
->wl
) == IEEE80211_BAND_2GHZ
) {
778 u16 txmix2g_tune_boost_pu
= 0;
779 u16 pad2g_tune_pus
= 0;
781 if (b43_nphy_ipa(dev
)) {
782 switch (phy
->radio_rev
) {
784 txmix2g_tune_boost_pu
= 0x0041;
788 txmix2g_tune_boost_pu
= 0x21;
789 pad2g_tune_pus
= 0x23;
794 if (txmix2g_tune_boost_pu
)
795 b43_radio_write(dev
, R2057_TXMIX2G_TUNE_BOOST_PU_CORE0
,
796 txmix2g_tune_boost_pu
);
798 b43_radio_write(dev
, R2057_PAD2G_TUNE_PUS_CORE0
,
800 if (txmix2g_tune_boost_pu
)
801 b43_radio_write(dev
, R2057_TXMIX2G_TUNE_BOOST_PU_CORE1
,
802 txmix2g_tune_boost_pu
);
804 b43_radio_write(dev
, R2057_PAD2G_TUNE_PUS_CORE1
,
808 usleep_range(50, 100);
810 /* VCO calibration */
811 b43_radio_mask(dev
, R2057_RFPLL_MISC_EN
, ~0x01);
812 b43_radio_mask(dev
, R2057_RFPLL_MISC_CAL_RESETN
, ~0x04);
813 b43_radio_set(dev
, R2057_RFPLL_MISC_CAL_RESETN
, 0x4);
814 b43_radio_set(dev
, R2057_RFPLL_MISC_EN
, 0x01);
815 usleep_range(300, 600);
818 /* Calibrate resistors in LPF of PLL?
819 * http://bcm-v4.sipsolutions.net/PHY/radio205x_rcal
821 static u8
b43_radio_2057_rcal(struct b43_wldev
*dev
)
823 struct b43_phy
*phy
= &dev
->phy
;
824 u16 saved_regs_phy
[12];
825 u16 saved_regs_phy_rf
[6];
826 u16 saved_regs_radio
[2] = { };
827 static const u16 phy_to_store
[] = {
828 B43_NPHY_RFCTL_RSSIO1
, B43_NPHY_RFCTL_RSSIO2
,
829 B43_NPHY_RFCTL_LUT_TRSW_LO1
, B43_NPHY_RFCTL_LUT_TRSW_LO2
,
830 B43_NPHY_RFCTL_RXG1
, B43_NPHY_RFCTL_RXG2
,
831 B43_NPHY_RFCTL_TXG1
, B43_NPHY_RFCTL_TXG2
,
832 B43_NPHY_REV7_RF_CTL_MISC_REG3
, B43_NPHY_REV7_RF_CTL_MISC_REG4
,
833 B43_NPHY_REV7_RF_CTL_MISC_REG5
, B43_NPHY_REV7_RF_CTL_MISC_REG6
,
835 static const u16 phy_to_store_rf
[] = {
836 B43_NPHY_REV3_RFCTL_OVER0
, B43_NPHY_REV3_RFCTL_OVER1
,
837 B43_NPHY_REV7_RF_CTL_OVER3
, B43_NPHY_REV7_RF_CTL_OVER4
,
838 B43_NPHY_REV7_RF_CTL_OVER5
, B43_NPHY_REV7_RF_CTL_OVER6
,
844 for (i
= 0; i
< ARRAY_SIZE(phy_to_store
); i
++)
845 saved_regs_phy
[i
] = b43_phy_read(dev
, phy_to_store
[i
]);
846 for (i
= 0; i
< ARRAY_SIZE(phy_to_store_rf
); i
++)
847 saved_regs_phy_rf
[i
] = b43_phy_read(dev
, phy_to_store_rf
[i
]);
850 for (i
= 0; i
< ARRAY_SIZE(phy_to_store
); i
++)
851 b43_phy_write(dev
, phy_to_store
[i
], 0);
852 b43_phy_write(dev
, B43_NPHY_REV3_RFCTL_OVER0
, 0x07ff);
853 b43_phy_write(dev
, B43_NPHY_REV3_RFCTL_OVER1
, 0x07ff);
854 b43_phy_write(dev
, B43_NPHY_REV7_RF_CTL_OVER3
, 0x07ff);
855 b43_phy_write(dev
, B43_NPHY_REV7_RF_CTL_OVER4
, 0x07ff);
856 b43_phy_write(dev
, B43_NPHY_REV7_RF_CTL_OVER5
, 0x007f);
857 b43_phy_write(dev
, B43_NPHY_REV7_RF_CTL_OVER6
, 0x007f);
859 switch (phy
->radio_rev
) {
861 b43_phy_mask(dev
, B43_NPHY_REV7_RF_CTL_OVER3
, ~0x2);
863 b43_radio_set(dev
, R2057_IQTEST_SEL_PU
, 0x1);
864 b43_radio_maskset(dev
, R2057v7_IQTEST_SEL_PU2
, ~0x2, 0x1);
867 b43_phy_set(dev
, B43_NPHY_REV7_RF_CTL_OVER3
, 0x2);
868 b43_phy_set(dev
, B43_NPHY_REV7_RF_CTL_MISC_REG3
, 0x2);
869 saved_regs_radio
[0] = b43_radio_read(dev
, R2057_IQTEST_SEL_PU
);
870 b43_radio_write(dev
, R2057_IQTEST_SEL_PU
, 0x11);
873 saved_regs_radio
[0] = b43_radio_read(dev
, R2057_IQTEST_SEL_PU
);
874 saved_regs_radio
[1] = b43_radio_read(dev
, R2057v7_IQTEST_SEL_PU2
);
875 b43_phy_set(dev
, B43_NPHY_REV7_RF_CTL_MISC_REG3
, 0x2);
876 b43_phy_set(dev
, B43_NPHY_REV7_RF_CTL_OVER3
, 0x2);
877 b43_radio_write(dev
, R2057v7_IQTEST_SEL_PU2
, 0x2);
878 b43_radio_write(dev
, R2057_IQTEST_SEL_PU
, 0x1);
883 b43_radio_set(dev
, R2057_RCAL_CONFIG
, 0x1);
887 b43_radio_set(dev
, R2057_RCAL_CONFIG
, 0x2);
888 usleep_range(100, 200);
891 b43_radio_mask(dev
, R2057_RCAL_CONFIG
, ~0x2);
893 /* Wait and check for result */
894 if (!b43_radio_wait_value(dev
, R2057_RCAL_STATUS
, 1, 1, 100, 1000000)) {
895 b43err(dev
->wl
, "Radio 0x2057 rcal timeout\n");
898 tmp
= b43_radio_read(dev
, R2057_RCAL_STATUS
) & 0x3E;
901 b43_radio_mask(dev
, R2057_RCAL_CONFIG
, ~0x1);
904 for (i
= 0; i
< ARRAY_SIZE(phy_to_store_rf
); i
++)
905 b43_phy_write(dev
, phy_to_store_rf
[i
], saved_regs_phy_rf
[i
]);
906 for (i
= 0; i
< ARRAY_SIZE(phy_to_store
); i
++)
907 b43_phy_write(dev
, phy_to_store
[i
], saved_regs_phy
[i
]);
909 switch (phy
->radio_rev
) {
912 b43_radio_maskset(dev
, R2057_TEMPSENSE_CONFIG
, ~0x3C, tmp
);
913 b43_radio_maskset(dev
, R2057_BANDGAP_RCAL_TRIM
, ~0xF0,
917 b43_radio_mask(dev
, R2057_IPA2G_CASCONV_CORE0
, ~0x1);
918 b43_radio_mask(dev
, R2057v7_IQTEST_SEL_PU2
, ~0x2);
921 b43_radio_write(dev
, R2057_IQTEST_SEL_PU
, saved_regs_radio
[0]);
924 b43_radio_write(dev
, R2057_IQTEST_SEL_PU
, saved_regs_radio
[0]);
925 b43_radio_write(dev
, R2057v7_IQTEST_SEL_PU2
, saved_regs_radio
[1]);
932 /* Calibrate the internal RC oscillator?
933 * http://bcm-v4.sipsolutions.net/PHY/radio2057_rccal
935 static u16
b43_radio_2057_rccal(struct b43_wldev
*dev
)
937 struct b43_phy
*phy
= &dev
->phy
;
938 bool special
= (phy
->radio_rev
== 3 || phy
->radio_rev
== 4 ||
939 phy
->radio_rev
== 6);
944 b43_radio_write(dev
, R2057_RCCAL_MASTER
, 0x61);
945 b43_radio_write(dev
, R2057_RCCAL_TRC0
, 0xC0);
947 b43_radio_write(dev
, R2057v7_RCCAL_MASTER
, 0x61);
948 b43_radio_write(dev
, R2057_RCCAL_TRC0
, 0xE9);
950 b43_radio_write(dev
, R2057_RCCAL_X1
, 0x6E);
952 /* Start, wait, stop */
953 b43_radio_write(dev
, R2057_RCCAL_START_R1_Q1_P1
, 0x55);
954 if (!b43_radio_wait_value(dev
, R2057_RCCAL_DONE_OSCCAP
, 2, 2, 500,
956 b43dbg(dev
->wl
, "Radio 0x2057 rccal timeout\n");
957 usleep_range(35, 70);
958 b43_radio_write(dev
, R2057_RCCAL_START_R1_Q1_P1
, 0x15);
959 usleep_range(70, 140);
963 b43_radio_write(dev
, R2057_RCCAL_MASTER
, 0x69);
964 b43_radio_write(dev
, R2057_RCCAL_TRC0
, 0xB0);
966 b43_radio_write(dev
, R2057v7_RCCAL_MASTER
, 0x69);
967 b43_radio_write(dev
, R2057_RCCAL_TRC0
, 0xD5);
969 b43_radio_write(dev
, R2057_RCCAL_X1
, 0x6E);
971 /* Start, wait, stop */
972 usleep_range(35, 70);
973 b43_radio_write(dev
, R2057_RCCAL_START_R1_Q1_P1
, 0x55);
974 usleep_range(70, 140);
975 if (!b43_radio_wait_value(dev
, R2057_RCCAL_DONE_OSCCAP
, 2, 2, 500,
977 b43dbg(dev
->wl
, "Radio 0x2057 rccal timeout\n");
978 usleep_range(35, 70);
979 b43_radio_write(dev
, R2057_RCCAL_START_R1_Q1_P1
, 0x15);
980 usleep_range(70, 140);
984 b43_radio_write(dev
, R2057_RCCAL_MASTER
, 0x73);
985 b43_radio_write(dev
, R2057_RCCAL_X1
, 0x28);
986 b43_radio_write(dev
, R2057_RCCAL_TRC0
, 0xB0);
988 b43_radio_write(dev
, R2057v7_RCCAL_MASTER
, 0x73);
989 b43_radio_write(dev
, R2057_RCCAL_X1
, 0x6E);
990 b43_radio_write(dev
, R2057_RCCAL_TRC0
, 0x99);
993 /* Start, wait, stop */
994 usleep_range(35, 70);
995 b43_radio_write(dev
, R2057_RCCAL_START_R1_Q1_P1
, 0x55);
996 usleep_range(70, 140);
997 if (!b43_radio_wait_value(dev
, R2057_RCCAL_DONE_OSCCAP
, 2, 2, 500,
999 b43err(dev
->wl
, "Radio 0x2057 rcal timeout\n");
1002 tmp
= b43_radio_read(dev
, R2057_RCCAL_DONE_OSCCAP
);
1003 usleep_range(35, 70);
1004 b43_radio_write(dev
, R2057_RCCAL_START_R1_Q1_P1
, 0x15);
1005 usleep_range(70, 140);
1008 b43_radio_mask(dev
, R2057_RCCAL_MASTER
, ~0x1);
1010 b43_radio_mask(dev
, R2057v7_RCCAL_MASTER
, ~0x1);
1015 static void b43_radio_2057_init_pre(struct b43_wldev
*dev
)
1017 b43_phy_mask(dev
, B43_NPHY_RFCTL_CMD
, ~B43_NPHY_RFCTL_CMD_CHIP0PU
);
1018 /* Maybe wl meant to reset and set (order?) RFCTL_CMD_OEPORFORCE? */
1019 b43_phy_mask(dev
, B43_NPHY_RFCTL_CMD
, B43_NPHY_RFCTL_CMD_OEPORFORCE
);
1020 b43_phy_set(dev
, B43_NPHY_RFCTL_CMD
, ~B43_NPHY_RFCTL_CMD_OEPORFORCE
);
1021 b43_phy_set(dev
, B43_NPHY_RFCTL_CMD
, B43_NPHY_RFCTL_CMD_CHIP0PU
);
1024 static void b43_radio_2057_init_post(struct b43_wldev
*dev
)
1026 b43_radio_set(dev
, R2057_XTALPUOVR_PINCTRL
, 0x1);
1028 if (0) /* FIXME: Is this BCM43217 specific? */
1029 b43_radio_set(dev
, R2057_XTALPUOVR_PINCTRL
, 0x2);
1031 b43_radio_set(dev
, R2057_RFPLL_MISC_CAL_RESETN
, 0x78);
1032 b43_radio_set(dev
, R2057_XTAL_CONFIG2
, 0x80);
1034 b43_radio_mask(dev
, R2057_RFPLL_MISC_CAL_RESETN
, ~0x78);
1035 b43_radio_mask(dev
, R2057_XTAL_CONFIG2
, ~0x80);
1037 if (dev
->phy
.do_full_init
) {
1038 b43_radio_2057_rcal(dev
);
1039 b43_radio_2057_rccal(dev
);
1041 b43_radio_mask(dev
, R2057_RFPLL_MASTER
, ~0x8);
1044 /* http://bcm-v4.sipsolutions.net/802.11/Radio/2057/Init */
1045 static void b43_radio_2057_init(struct b43_wldev
*dev
)
1047 b43_radio_2057_init_pre(dev
);
1048 r2057_upload_inittabs(dev
);
1049 b43_radio_2057_init_post(dev
);
1052 /**************************************************
1054 **************************************************/
1056 static void b43_chantab_radio_2056_upload(struct b43_wldev
*dev
,
1057 const struct b43_nphy_channeltab_entry_rev3
*e
)
1059 b43_radio_write(dev
, B2056_SYN_PLL_VCOCAL1
, e
->radio_syn_pll_vcocal1
);
1060 b43_radio_write(dev
, B2056_SYN_PLL_VCOCAL2
, e
->radio_syn_pll_vcocal2
);
1061 b43_radio_write(dev
, B2056_SYN_PLL_REFDIV
, e
->radio_syn_pll_refdiv
);
1062 b43_radio_write(dev
, B2056_SYN_PLL_MMD2
, e
->radio_syn_pll_mmd2
);
1063 b43_radio_write(dev
, B2056_SYN_PLL_MMD1
, e
->radio_syn_pll_mmd1
);
1064 b43_radio_write(dev
, B2056_SYN_PLL_LOOPFILTER1
,
1065 e
->radio_syn_pll_loopfilter1
);
1066 b43_radio_write(dev
, B2056_SYN_PLL_LOOPFILTER2
,
1067 e
->radio_syn_pll_loopfilter2
);
1068 b43_radio_write(dev
, B2056_SYN_PLL_LOOPFILTER3
,
1069 e
->radio_syn_pll_loopfilter3
);
1070 b43_radio_write(dev
, B2056_SYN_PLL_LOOPFILTER4
,
1071 e
->radio_syn_pll_loopfilter4
);
1072 b43_radio_write(dev
, B2056_SYN_PLL_LOOPFILTER5
,
1073 e
->radio_syn_pll_loopfilter5
);
1074 b43_radio_write(dev
, B2056_SYN_RESERVED_ADDR27
,
1075 e
->radio_syn_reserved_addr27
);
1076 b43_radio_write(dev
, B2056_SYN_RESERVED_ADDR28
,
1077 e
->radio_syn_reserved_addr28
);
1078 b43_radio_write(dev
, B2056_SYN_RESERVED_ADDR29
,
1079 e
->radio_syn_reserved_addr29
);
1080 b43_radio_write(dev
, B2056_SYN_LOGEN_VCOBUF1
,
1081 e
->radio_syn_logen_vcobuf1
);
1082 b43_radio_write(dev
, B2056_SYN_LOGEN_MIXER2
, e
->radio_syn_logen_mixer2
);
1083 b43_radio_write(dev
, B2056_SYN_LOGEN_BUF3
, e
->radio_syn_logen_buf3
);
1084 b43_radio_write(dev
, B2056_SYN_LOGEN_BUF4
, e
->radio_syn_logen_buf4
);
1086 b43_radio_write(dev
, B2056_RX0
| B2056_RX_LNAA_TUNE
,
1087 e
->radio_rx0_lnaa_tune
);
1088 b43_radio_write(dev
, B2056_RX0
| B2056_RX_LNAG_TUNE
,
1089 e
->radio_rx0_lnag_tune
);
1091 b43_radio_write(dev
, B2056_TX0
| B2056_TX_INTPAA_BOOST_TUNE
,
1092 e
->radio_tx0_intpaa_boost_tune
);
1093 b43_radio_write(dev
, B2056_TX0
| B2056_TX_INTPAG_BOOST_TUNE
,
1094 e
->radio_tx0_intpag_boost_tune
);
1095 b43_radio_write(dev
, B2056_TX0
| B2056_TX_PADA_BOOST_TUNE
,
1096 e
->radio_tx0_pada_boost_tune
);
1097 b43_radio_write(dev
, B2056_TX0
| B2056_TX_PADG_BOOST_TUNE
,
1098 e
->radio_tx0_padg_boost_tune
);
1099 b43_radio_write(dev
, B2056_TX0
| B2056_TX_PGAA_BOOST_TUNE
,
1100 e
->radio_tx0_pgaa_boost_tune
);
1101 b43_radio_write(dev
, B2056_TX0
| B2056_TX_PGAG_BOOST_TUNE
,
1102 e
->radio_tx0_pgag_boost_tune
);
1103 b43_radio_write(dev
, B2056_TX0
| B2056_TX_MIXA_BOOST_TUNE
,
1104 e
->radio_tx0_mixa_boost_tune
);
1105 b43_radio_write(dev
, B2056_TX0
| B2056_TX_MIXG_BOOST_TUNE
,
1106 e
->radio_tx0_mixg_boost_tune
);
1108 b43_radio_write(dev
, B2056_RX1
| B2056_RX_LNAA_TUNE
,
1109 e
->radio_rx1_lnaa_tune
);
1110 b43_radio_write(dev
, B2056_RX1
| B2056_RX_LNAG_TUNE
,
1111 e
->radio_rx1_lnag_tune
);
1113 b43_radio_write(dev
, B2056_TX1
| B2056_TX_INTPAA_BOOST_TUNE
,
1114 e
->radio_tx1_intpaa_boost_tune
);
1115 b43_radio_write(dev
, B2056_TX1
| B2056_TX_INTPAG_BOOST_TUNE
,
1116 e
->radio_tx1_intpag_boost_tune
);
1117 b43_radio_write(dev
, B2056_TX1
| B2056_TX_PADA_BOOST_TUNE
,
1118 e
->radio_tx1_pada_boost_tune
);
1119 b43_radio_write(dev
, B2056_TX1
| B2056_TX_PADG_BOOST_TUNE
,
1120 e
->radio_tx1_padg_boost_tune
);
1121 b43_radio_write(dev
, B2056_TX1
| B2056_TX_PGAA_BOOST_TUNE
,
1122 e
->radio_tx1_pgaa_boost_tune
);
1123 b43_radio_write(dev
, B2056_TX1
| B2056_TX_PGAG_BOOST_TUNE
,
1124 e
->radio_tx1_pgag_boost_tune
);
1125 b43_radio_write(dev
, B2056_TX1
| B2056_TX_MIXA_BOOST_TUNE
,
1126 e
->radio_tx1_mixa_boost_tune
);
1127 b43_radio_write(dev
, B2056_TX1
| B2056_TX_MIXG_BOOST_TUNE
,
1128 e
->radio_tx1_mixg_boost_tune
);
1131 /* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2056Setup */
1132 static void b43_radio_2056_setup(struct b43_wldev
*dev
,
1133 const struct b43_nphy_channeltab_entry_rev3
*e
)
1135 struct b43_phy
*phy
= &dev
->phy
;
1136 struct ssb_sprom
*sprom
= dev
->dev
->bus_sprom
;
1137 enum ieee80211_band band
= b43_current_band(dev
->wl
);
1141 u16 pag_boost
, padg_boost
, pgag_boost
, mixg_boost
;
1142 u16 paa_boost
, pada_boost
, pgaa_boost
, mixa_boost
;
1143 bool is_pkg_fab_smic
;
1145 B43_WARN_ON(dev
->phy
.rev
< 3);
1148 ((dev
->dev
->chip_id
== BCMA_CHIP_ID_BCM43224
||
1149 dev
->dev
->chip_id
== BCMA_CHIP_ID_BCM43225
||
1150 dev
->dev
->chip_id
== BCMA_CHIP_ID_BCM43421
) &&
1151 dev
->dev
->chip_pkg
== BCMA_PKG_ID_BCM43224_FAB_SMIC
);
1153 b43_chantab_radio_2056_upload(dev
, e
);
1154 b2056_upload_syn_pll_cp2(dev
, band
== IEEE80211_BAND_5GHZ
);
1156 if (sprom
->boardflags2_lo
& B43_BFL2_GPLL_WAR
&&
1157 b43_current_band(dev
->wl
) == IEEE80211_BAND_2GHZ
) {
1158 b43_radio_write(dev
, B2056_SYN_PLL_LOOPFILTER1
, 0x1F);
1159 b43_radio_write(dev
, B2056_SYN_PLL_LOOPFILTER2
, 0x1F);
1160 if (dev
->dev
->chip_id
== BCMA_CHIP_ID_BCM4716
||
1161 dev
->dev
->chip_id
== BCMA_CHIP_ID_BCM47162
) {
1162 b43_radio_write(dev
, B2056_SYN_PLL_LOOPFILTER4
, 0x14);
1163 b43_radio_write(dev
, B2056_SYN_PLL_CP2
, 0);
1165 b43_radio_write(dev
, B2056_SYN_PLL_LOOPFILTER4
, 0x0B);
1166 b43_radio_write(dev
, B2056_SYN_PLL_CP2
, 0x14);
1169 if (sprom
->boardflags2_hi
& B43_BFH2_GPLL_WAR2
&&
1170 b43_current_band(dev
->wl
) == IEEE80211_BAND_2GHZ
) {
1171 b43_radio_write(dev
, B2056_SYN_PLL_LOOPFILTER1
, 0x1f);
1172 b43_radio_write(dev
, B2056_SYN_PLL_LOOPFILTER2
, 0x1f);
1173 b43_radio_write(dev
, B2056_SYN_PLL_LOOPFILTER4
, 0x0b);
1174 b43_radio_write(dev
, B2056_SYN_PLL_CP2
, 0x20);
1176 if (sprom
->boardflags2_lo
& B43_BFL2_APLL_WAR
&&
1177 b43_current_band(dev
->wl
) == IEEE80211_BAND_5GHZ
) {
1178 b43_radio_write(dev
, B2056_SYN_PLL_LOOPFILTER1
, 0x1F);
1179 b43_radio_write(dev
, B2056_SYN_PLL_LOOPFILTER2
, 0x1F);
1180 b43_radio_write(dev
, B2056_SYN_PLL_LOOPFILTER4
, 0x05);
1181 b43_radio_write(dev
, B2056_SYN_PLL_CP2
, 0x0C);
1184 if (dev
->phy
.n
->ipa2g_on
&& band
== IEEE80211_BAND_2GHZ
) {
1185 for (i
= 0; i
< 2; i
++) {
1186 offset
= i
? B2056_TX1
: B2056_TX0
;
1187 if (dev
->phy
.rev
>= 5) {
1188 b43_radio_write(dev
,
1189 offset
| B2056_TX_PADG_IDAC
, 0xcc);
1191 if (dev
->dev
->chip_id
== BCMA_CHIP_ID_BCM4716
||
1192 dev
->dev
->chip_id
== BCMA_CHIP_ID_BCM47162
) {
1201 if (is_pkg_fab_smic
) {
1211 b43_radio_write(dev
,
1212 offset
| B2056_TX_INTPAG_IMAIN_STAT
,
1214 b43_radio_write(dev
,
1215 offset
| B2056_TX_INTPAG_IAUX_STAT
,
1217 b43_radio_write(dev
,
1218 offset
| B2056_TX_INTPAG_CASCBIAS
,
1220 b43_radio_write(dev
,
1221 offset
| B2056_TX_INTPAG_BOOST_TUNE
,
1223 b43_radio_write(dev
,
1224 offset
| B2056_TX_PGAG_BOOST_TUNE
,
1226 b43_radio_write(dev
,
1227 offset
| B2056_TX_PADG_BOOST_TUNE
,
1229 b43_radio_write(dev
,
1230 offset
| B2056_TX_MIXG_BOOST_TUNE
,
1233 bias
= b43_is_40mhz(dev
) ? 0x40 : 0x20;
1234 b43_radio_write(dev
,
1235 offset
| B2056_TX_INTPAG_IMAIN_STAT
,
1237 b43_radio_write(dev
,
1238 offset
| B2056_TX_INTPAG_IAUX_STAT
,
1240 b43_radio_write(dev
,
1241 offset
| B2056_TX_INTPAG_CASCBIAS
,
1244 b43_radio_write(dev
, offset
| B2056_TX_PA_SPARE1
, 0xee);
1246 } else if (dev
->phy
.n
->ipa5g_on
&& band
== IEEE80211_BAND_5GHZ
) {
1247 u16 freq
= phy
->chandef
->chan
->center_freq
;
1253 } else if (freq
< 5340) {
1258 } else if (freq
< 5650) {
1267 pgaa_boost
= -(freq
- 18) / 36 + 168;
1273 cbias
= is_pkg_fab_smic
? 0x35 : 0x30;
1275 for (i
= 0; i
< 2; i
++) {
1276 offset
= i
? B2056_TX1
: B2056_TX0
;
1278 b43_radio_write(dev
,
1279 offset
| B2056_TX_INTPAA_BOOST_TUNE
, paa_boost
);
1280 b43_radio_write(dev
,
1281 offset
| B2056_TX_PADA_BOOST_TUNE
, pada_boost
);
1282 b43_radio_write(dev
,
1283 offset
| B2056_TX_PGAA_BOOST_TUNE
, pgaa_boost
);
1284 b43_radio_write(dev
,
1285 offset
| B2056_TX_MIXA_BOOST_TUNE
, mixa_boost
);
1286 b43_radio_write(dev
,
1287 offset
| B2056_TX_TXSPARE1
, 0x30);
1288 b43_radio_write(dev
,
1289 offset
| B2056_TX_PA_SPARE2
, 0xee);
1290 b43_radio_write(dev
,
1291 offset
| B2056_TX_PADA_CASCBIAS
, 0x03);
1292 b43_radio_write(dev
,
1293 offset
| B2056_TX_INTPAA_IAUX_STAT
, 0x30);
1294 b43_radio_write(dev
,
1295 offset
| B2056_TX_INTPAA_IMAIN_STAT
, 0x30);
1296 b43_radio_write(dev
,
1297 offset
| B2056_TX_INTPAA_CASCBIAS
, cbias
);
1302 /* VCO calibration */
1303 b43_radio_write(dev
, B2056_SYN_PLL_VCOCAL12
, 0x00);
1304 b43_radio_write(dev
, B2056_TX_INTPAA_PA_MISC
, 0x38);
1305 b43_radio_write(dev
, B2056_TX_INTPAA_PA_MISC
, 0x18);
1306 b43_radio_write(dev
, B2056_TX_INTPAA_PA_MISC
, 0x38);
1307 b43_radio_write(dev
, B2056_TX_INTPAA_PA_MISC
, 0x39);
1311 static u8
b43_radio_2056_rcal(struct b43_wldev
*dev
)
1313 struct b43_phy
*phy
= &dev
->phy
;
1319 mast2
= b43_radio_read(dev
, B2056_SYN_PLL_MAST2
);
1320 b43_radio_write(dev
, B2056_SYN_PLL_MAST2
, mast2
| 0x7);
1323 b43_radio_write(dev
, B2056_SYN_RCAL_MASTER
, 0x01);
1325 b43_radio_write(dev
, B2056_SYN_RCAL_MASTER
, 0x09);
1327 if (!b43_radio_wait_value(dev
, B2056_SYN_RCAL_CODE_OUT
, 0x80, 0x80, 100,
1329 b43err(dev
->wl
, "Radio recalibration timeout\n");
1333 b43_radio_write(dev
, B2056_SYN_RCAL_MASTER
, 0x01);
1334 tmp
= b43_radio_read(dev
, B2056_SYN_RCAL_CODE_OUT
);
1335 b43_radio_write(dev
, B2056_SYN_RCAL_MASTER
, 0x00);
1337 b43_radio_write(dev
, B2056_SYN_PLL_MAST2
, mast2
);
1342 static void b43_radio_init2056_pre(struct b43_wldev
*dev
)
1344 b43_phy_mask(dev
, B43_NPHY_RFCTL_CMD
,
1345 ~B43_NPHY_RFCTL_CMD_CHIP0PU
);
1346 /* Maybe wl meant to reset and set (order?) RFCTL_CMD_OEPORFORCE? */
1347 b43_phy_mask(dev
, B43_NPHY_RFCTL_CMD
,
1348 B43_NPHY_RFCTL_CMD_OEPORFORCE
);
1349 b43_phy_set(dev
, B43_NPHY_RFCTL_CMD
,
1350 ~B43_NPHY_RFCTL_CMD_OEPORFORCE
);
1351 b43_phy_set(dev
, B43_NPHY_RFCTL_CMD
,
1352 B43_NPHY_RFCTL_CMD_CHIP0PU
);
1355 static void b43_radio_init2056_post(struct b43_wldev
*dev
)
1357 b43_radio_set(dev
, B2056_SYN_COM_CTRL
, 0xB);
1358 b43_radio_set(dev
, B2056_SYN_COM_PU
, 0x2);
1359 b43_radio_set(dev
, B2056_SYN_COM_RESET
, 0x2);
1361 b43_radio_mask(dev
, B2056_SYN_COM_RESET
, ~0x2);
1362 b43_radio_mask(dev
, B2056_SYN_PLL_MAST2
, ~0xFC);
1363 b43_radio_mask(dev
, B2056_SYN_RCCAL_CTRL0
, ~0x1);
1364 if (dev
->phy
.do_full_init
)
1365 b43_radio_2056_rcal(dev
);
1369 * Initialize a Broadcom 2056 N-radio
1370 * http://bcm-v4.sipsolutions.net/802.11/Radio/2056/Init
1372 static void b43_radio_init2056(struct b43_wldev
*dev
)
1374 b43_radio_init2056_pre(dev
);
1375 b2056_upload_inittabs(dev
, 0, 0);
1376 b43_radio_init2056_post(dev
);
1379 /**************************************************
1381 **************************************************/
1383 static void b43_chantab_radio_upload(struct b43_wldev
*dev
,
1384 const struct b43_nphy_channeltab_entry_rev2
*e
)
1386 b43_radio_write(dev
, B2055_PLL_REF
, e
->radio_pll_ref
);
1387 b43_radio_write(dev
, B2055_RF_PLLMOD0
, e
->radio_rf_pllmod0
);
1388 b43_radio_write(dev
, B2055_RF_PLLMOD1
, e
->radio_rf_pllmod1
);
1389 b43_radio_write(dev
, B2055_VCO_CAPTAIL
, e
->radio_vco_captail
);
1390 b43_read32(dev
, B43_MMIO_MACCTL
); /* flush writes */
1392 b43_radio_write(dev
, B2055_VCO_CAL1
, e
->radio_vco_cal1
);
1393 b43_radio_write(dev
, B2055_VCO_CAL2
, e
->radio_vco_cal2
);
1394 b43_radio_write(dev
, B2055_PLL_LFC1
, e
->radio_pll_lfc1
);
1395 b43_radio_write(dev
, B2055_PLL_LFR1
, e
->radio_pll_lfr1
);
1396 b43_read32(dev
, B43_MMIO_MACCTL
); /* flush writes */
1398 b43_radio_write(dev
, B2055_PLL_LFC2
, e
->radio_pll_lfc2
);
1399 b43_radio_write(dev
, B2055_LGBUF_CENBUF
, e
->radio_lgbuf_cenbuf
);
1400 b43_radio_write(dev
, B2055_LGEN_TUNE1
, e
->radio_lgen_tune1
);
1401 b43_radio_write(dev
, B2055_LGEN_TUNE2
, e
->radio_lgen_tune2
);
1402 b43_read32(dev
, B43_MMIO_MACCTL
); /* flush writes */
1404 b43_radio_write(dev
, B2055_C1_LGBUF_ATUNE
, e
->radio_c1_lgbuf_atune
);
1405 b43_radio_write(dev
, B2055_C1_LGBUF_GTUNE
, e
->radio_c1_lgbuf_gtune
);
1406 b43_radio_write(dev
, B2055_C1_RX_RFR1
, e
->radio_c1_rx_rfr1
);
1407 b43_radio_write(dev
, B2055_C1_TX_PGAPADTN
, e
->radio_c1_tx_pgapadtn
);
1408 b43_read32(dev
, B43_MMIO_MACCTL
); /* flush writes */
1410 b43_radio_write(dev
, B2055_C1_TX_MXBGTRIM
, e
->radio_c1_tx_mxbgtrim
);
1411 b43_radio_write(dev
, B2055_C2_LGBUF_ATUNE
, e
->radio_c2_lgbuf_atune
);
1412 b43_radio_write(dev
, B2055_C2_LGBUF_GTUNE
, e
->radio_c2_lgbuf_gtune
);
1413 b43_radio_write(dev
, B2055_C2_RX_RFR1
, e
->radio_c2_rx_rfr1
);
1414 b43_read32(dev
, B43_MMIO_MACCTL
); /* flush writes */
1416 b43_radio_write(dev
, B2055_C2_TX_PGAPADTN
, e
->radio_c2_tx_pgapadtn
);
1417 b43_radio_write(dev
, B2055_C2_TX_MXBGTRIM
, e
->radio_c2_tx_mxbgtrim
);
1420 /* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2055Setup */
1421 static void b43_radio_2055_setup(struct b43_wldev
*dev
,
1422 const struct b43_nphy_channeltab_entry_rev2
*e
)
1424 B43_WARN_ON(dev
->phy
.rev
>= 3);
1426 b43_chantab_radio_upload(dev
, e
);
1428 b43_radio_write(dev
, B2055_VCO_CAL10
, 0x05);
1429 b43_radio_write(dev
, B2055_VCO_CAL10
, 0x45);
1430 b43_read32(dev
, B43_MMIO_MACCTL
); /* flush writes */
1431 b43_radio_write(dev
, B2055_VCO_CAL10
, 0x65);
1435 static void b43_radio_init2055_pre(struct b43_wldev
*dev
)
1437 b43_phy_mask(dev
, B43_NPHY_RFCTL_CMD
,
1438 ~B43_NPHY_RFCTL_CMD_PORFORCE
);
1439 b43_phy_set(dev
, B43_NPHY_RFCTL_CMD
,
1440 B43_NPHY_RFCTL_CMD_CHIP0PU
|
1441 B43_NPHY_RFCTL_CMD_OEPORFORCE
);
1442 b43_phy_set(dev
, B43_NPHY_RFCTL_CMD
,
1443 B43_NPHY_RFCTL_CMD_PORFORCE
);
1446 static void b43_radio_init2055_post(struct b43_wldev
*dev
)
1448 struct b43_phy_n
*nphy
= dev
->phy
.n
;
1449 struct ssb_sprom
*sprom
= dev
->dev
->bus_sprom
;
1450 bool workaround
= false;
1452 if (sprom
->revision
< 4)
1453 workaround
= (dev
->dev
->board_vendor
!= PCI_VENDOR_ID_BROADCOM
1454 && dev
->dev
->board_type
== SSB_BOARD_CB2_4321
1455 && dev
->dev
->board_rev
>= 0x41);
1458 !(sprom
->boardflags2_lo
& B43_BFL2_RXBB_INT_REG_DIS
);
1460 b43_radio_mask(dev
, B2055_MASTER1
, 0xFFF3);
1462 b43_radio_mask(dev
, B2055_C1_RX_BB_REG
, 0x7F);
1463 b43_radio_mask(dev
, B2055_C2_RX_BB_REG
, 0x7F);
1465 b43_radio_maskset(dev
, B2055_RRCCAL_NOPTSEL
, 0xFFC0, 0x2C);
1466 b43_radio_write(dev
, B2055_CAL_MISC
, 0x3C);
1467 b43_radio_mask(dev
, B2055_CAL_MISC
, 0xFFBE);
1468 b43_radio_set(dev
, B2055_CAL_LPOCTL
, 0x80);
1469 b43_radio_set(dev
, B2055_CAL_MISC
, 0x1);
1471 b43_radio_set(dev
, B2055_CAL_MISC
, 0x40);
1472 if (!b43_radio_wait_value(dev
, B2055_CAL_COUT2
, 0x80, 0x80, 10, 2000))
1473 b43err(dev
->wl
, "radio post init timeout\n");
1474 b43_radio_mask(dev
, B2055_CAL_LPOCTL
, 0xFF7F);
1475 b43_switch_channel(dev
, dev
->phy
.channel
);
1476 b43_radio_write(dev
, B2055_C1_RX_BB_LPF
, 0x9);
1477 b43_radio_write(dev
, B2055_C2_RX_BB_LPF
, 0x9);
1478 b43_radio_write(dev
, B2055_C1_RX_BB_MIDACHP
, 0x83);
1479 b43_radio_write(dev
, B2055_C2_RX_BB_MIDACHP
, 0x83);
1480 b43_radio_maskset(dev
, B2055_C1_LNA_GAINBST
, 0xFFF8, 0x6);
1481 b43_radio_maskset(dev
, B2055_C2_LNA_GAINBST
, 0xFFF8, 0x6);
1482 if (!nphy
->gain_boost
) {
1483 b43_radio_set(dev
, B2055_C1_RX_RFSPC1
, 0x2);
1484 b43_radio_set(dev
, B2055_C2_RX_RFSPC1
, 0x2);
1486 b43_radio_mask(dev
, B2055_C1_RX_RFSPC1
, 0xFFFD);
1487 b43_radio_mask(dev
, B2055_C2_RX_RFSPC1
, 0xFFFD);
1493 * Initialize a Broadcom 2055 N-radio
1494 * http://bcm-v4.sipsolutions.net/802.11/Radio/2055/Init
1496 static void b43_radio_init2055(struct b43_wldev
*dev
)
1498 b43_radio_init2055_pre(dev
);
1499 if (b43_status(dev
) < B43_STAT_INITIALIZED
) {
1500 /* Follow wl, not specs. Do not force uploading all regs */
1501 b2055_upload_inittab(dev
, 0, 0);
1503 bool ghz5
= b43_current_band(dev
->wl
) == IEEE80211_BAND_5GHZ
;
1504 b2055_upload_inittab(dev
, ghz5
, 0);
1506 b43_radio_init2055_post(dev
);
1509 /**************************************************
1511 **************************************************/
1513 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/LoadSampleTable */
1514 static int b43_nphy_load_samples(struct b43_wldev
*dev
,
1515 struct b43_c32
*samples
, u16 len
) {
1516 struct b43_phy_n
*nphy
= dev
->phy
.n
;
1520 data
= kzalloc(len
* sizeof(u32
), GFP_KERNEL
);
1522 b43err(dev
->wl
, "allocation for samples loading failed\n");
1525 if (nphy
->hang_avoid
)
1526 b43_nphy_stay_in_carrier_search(dev
, 1);
1528 for (i
= 0; i
< len
; i
++) {
1529 data
[i
] = (samples
[i
].i
& 0x3FF << 10);
1530 data
[i
] |= samples
[i
].q
& 0x3FF;
1532 b43_ntab_write_bulk(dev
, B43_NTAB32(17, 0), len
, data
);
1535 if (nphy
->hang_avoid
)
1536 b43_nphy_stay_in_carrier_search(dev
, 0);
1540 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GenLoadSamples */
1541 static u16
b43_nphy_gen_load_samples(struct b43_wldev
*dev
, u32 freq
, u16 max
,
1545 u16 bw
, len
, rot
, angle
;
1546 struct b43_c32
*samples
;
1548 bw
= b43_is_40mhz(dev
) ? 40 : 20;
1552 if (b43_phy_read(dev
, B43_NPHY_BBCFG
) & B43_NPHY_BBCFG_RSTRX
)
1557 if (b43_is_40mhz(dev
))
1563 samples
= kcalloc(len
, sizeof(struct b43_c32
), GFP_KERNEL
);
1565 b43err(dev
->wl
, "allocation for samples generation failed\n");
1568 rot
= (((freq
* 36) / bw
) << 16) / 100;
1571 for (i
= 0; i
< len
; i
++) {
1572 samples
[i
] = b43_cordic(angle
);
1574 samples
[i
].q
= CORDIC_CONVERT(samples
[i
].q
* max
);
1575 samples
[i
].i
= CORDIC_CONVERT(samples
[i
].i
* max
);
1578 i
= b43_nphy_load_samples(dev
, samples
, len
);
1580 return (i
< 0) ? 0 : len
;
1583 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RunSamples */
1584 static void b43_nphy_run_samples(struct b43_wldev
*dev
, u16 samps
, u16 loops
,
1585 u16 wait
, bool iqmode
, bool dac_test
,
1588 struct b43_phy
*phy
= &dev
->phy
;
1589 struct b43_phy_n
*nphy
= dev
->phy
.n
;
1594 b43_nphy_stay_in_carrier_search(dev
, true);
1596 if (phy
->rev
>= 7) {
1597 bool lpf_bw3
, lpf_bw4
;
1599 lpf_bw3
= b43_phy_read(dev
, B43_NPHY_REV7_RF_CTL_OVER3
) & 0x80;
1600 lpf_bw4
= b43_phy_read(dev
, B43_NPHY_REV7_RF_CTL_OVER4
) & 0x80;
1602 if (lpf_bw3
|| lpf_bw4
) {
1605 u16 value
= b43_nphy_read_lpf_ctl(dev
, 0);
1607 b43_nphy_rf_ctl_override_rev19(dev
, 0x80, value
,
1610 b43_nphy_rf_ctl_override_rev7(dev
, 0x80, value
,
1612 nphy
->lpf_bw_overrode_for_sample_play
= true;
1616 if ((nphy
->bb_mult_save
& 0x80000000) == 0) {
1617 tmp
= b43_ntab_read(dev
, B43_NTAB16(15, 87));
1618 nphy
->bb_mult_save
= (tmp
& 0xFFFF) | 0x80000000;
1621 if (modify_bbmult
) {
1622 tmp
= !b43_is_40mhz(dev
) ? 0x6464 : 0x4747;
1623 b43_ntab_write(dev
, B43_NTAB16(15, 87), tmp
);
1626 b43_phy_write(dev
, B43_NPHY_SAMP_DEPCNT
, (samps
- 1));
1628 if (loops
!= 0xFFFF)
1629 b43_phy_write(dev
, B43_NPHY_SAMP_LOOPCNT
, (loops
- 1));
1631 b43_phy_write(dev
, B43_NPHY_SAMP_LOOPCNT
, loops
);
1633 b43_phy_write(dev
, B43_NPHY_SAMP_WAITCNT
, wait
);
1635 seq_mode
= b43_phy_read(dev
, B43_NPHY_RFSEQMODE
);
1637 b43_phy_set(dev
, B43_NPHY_RFSEQMODE
, B43_NPHY_RFSEQMODE_CAOVER
);
1639 b43_phy_mask(dev
, B43_NPHY_IQLOCAL_CMDGCTL
, 0x7FFF);
1640 b43_phy_set(dev
, B43_NPHY_IQLOCAL_CMDGCTL
, 0x8000);
1642 tmp
= dac_test
? 5 : 1;
1643 b43_phy_write(dev
, B43_NPHY_SAMP_CMD
, tmp
);
1645 for (i
= 0; i
< 100; i
++) {
1646 if (!(b43_phy_read(dev
, B43_NPHY_RFSEQST
) & 1)) {
1653 b43err(dev
->wl
, "run samples timeout\n");
1655 b43_phy_write(dev
, B43_NPHY_RFSEQMODE
, seq_mode
);
1657 b43_nphy_stay_in_carrier_search(dev
, false);
1660 /**************************************************
1662 **************************************************/
1664 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ScaleOffsetRssi */
1665 static void b43_nphy_scale_offset_rssi(struct b43_wldev
*dev
, u16 scale
,
1667 enum n_rail_type rail
,
1668 enum n_rssi_type rssi_type
)
1671 bool core1or5
= (core
== 1) || (core
== 5);
1672 bool core2or5
= (core
== 2) || (core
== 5);
1674 offset
= clamp_val(offset
, -32, 31);
1675 tmp
= ((scale
& 0x3F) << 8) | (offset
& 0x3F);
1677 switch (rssi_type
) {
1679 if (core1or5
&& rail
== N_RAIL_I
)
1680 b43_phy_write(dev
, B43_NPHY_RSSIMC_0I_RSSI_Z
, tmp
);
1681 if (core1or5
&& rail
== N_RAIL_Q
)
1682 b43_phy_write(dev
, B43_NPHY_RSSIMC_0Q_RSSI_Z
, tmp
);
1683 if (core2or5
&& rail
== N_RAIL_I
)
1684 b43_phy_write(dev
, B43_NPHY_RSSIMC_1I_RSSI_Z
, tmp
);
1685 if (core2or5
&& rail
== N_RAIL_Q
)
1686 b43_phy_write(dev
, B43_NPHY_RSSIMC_1Q_RSSI_Z
, tmp
);
1689 if (core1or5
&& rail
== N_RAIL_I
)
1690 b43_phy_write(dev
, B43_NPHY_RSSIMC_0I_RSSI_X
, tmp
);
1691 if (core1or5
&& rail
== N_RAIL_Q
)
1692 b43_phy_write(dev
, B43_NPHY_RSSIMC_0Q_RSSI_X
, tmp
);
1693 if (core2or5
&& rail
== N_RAIL_I
)
1694 b43_phy_write(dev
, B43_NPHY_RSSIMC_1I_RSSI_X
, tmp
);
1695 if (core2or5
&& rail
== N_RAIL_Q
)
1696 b43_phy_write(dev
, B43_NPHY_RSSIMC_1Q_RSSI_X
, tmp
);
1699 if (core1or5
&& rail
== N_RAIL_I
)
1700 b43_phy_write(dev
, B43_NPHY_RSSIMC_0I_RSSI_Y
, tmp
);
1701 if (core1or5
&& rail
== N_RAIL_Q
)
1702 b43_phy_write(dev
, B43_NPHY_RSSIMC_0Q_RSSI_Y
, tmp
);
1703 if (core2or5
&& rail
== N_RAIL_I
)
1704 b43_phy_write(dev
, B43_NPHY_RSSIMC_1I_RSSI_Y
, tmp
);
1705 if (core2or5
&& rail
== N_RAIL_Q
)
1706 b43_phy_write(dev
, B43_NPHY_RSSIMC_1Q_RSSI_Y
, tmp
);
1709 if (core1or5
&& rail
== N_RAIL_I
)
1710 b43_phy_write(dev
, B43_NPHY_RSSIMC_0I_TBD
, tmp
);
1711 if (core1or5
&& rail
== N_RAIL_Q
)
1712 b43_phy_write(dev
, B43_NPHY_RSSIMC_0Q_TBD
, tmp
);
1713 if (core2or5
&& rail
== N_RAIL_I
)
1714 b43_phy_write(dev
, B43_NPHY_RSSIMC_1I_TBD
, tmp
);
1715 if (core2or5
&& rail
== N_RAIL_Q
)
1716 b43_phy_write(dev
, B43_NPHY_RSSIMC_1Q_TBD
, tmp
);
1719 if (core1or5
&& rail
== N_RAIL_I
)
1720 b43_phy_write(dev
, B43_NPHY_RSSIMC_0I_PWRDET
, tmp
);
1721 if (core1or5
&& rail
== N_RAIL_Q
)
1722 b43_phy_write(dev
, B43_NPHY_RSSIMC_0Q_PWRDET
, tmp
);
1723 if (core2or5
&& rail
== N_RAIL_I
)
1724 b43_phy_write(dev
, B43_NPHY_RSSIMC_1I_PWRDET
, tmp
);
1725 if (core2or5
&& rail
== N_RAIL_Q
)
1726 b43_phy_write(dev
, B43_NPHY_RSSIMC_1Q_PWRDET
, tmp
);
1728 case N_RSSI_TSSI_2G
:
1730 b43_phy_write(dev
, B43_NPHY_RSSIMC_0I_TSSI
, tmp
);
1732 b43_phy_write(dev
, B43_NPHY_RSSIMC_1I_TSSI
, tmp
);
1734 case N_RSSI_TSSI_5G
:
1736 b43_phy_write(dev
, B43_NPHY_RSSIMC_0Q_TSSI
, tmp
);
1738 b43_phy_write(dev
, B43_NPHY_RSSIMC_1Q_TSSI
, tmp
);
1743 static void b43_nphy_rssi_select_rev19(struct b43_wldev
*dev
, u8 code
,
1744 enum n_rssi_type rssi_type
)
1749 static void b43_nphy_rev3_rssi_select(struct b43_wldev
*dev
, u8 code
,
1750 enum n_rssi_type rssi_type
)
1756 b43_phy_mask(dev
, B43_NPHY_AFECTL_OVER1
, 0xFDFF);
1757 b43_phy_mask(dev
, B43_NPHY_AFECTL_OVER
, 0xFDFF);
1758 b43_phy_mask(dev
, B43_NPHY_AFECTL_C1
, 0xFCFF);
1759 b43_phy_mask(dev
, B43_NPHY_AFECTL_C2
, 0xFCFF);
1760 b43_phy_mask(dev
, B43_NPHY_TXF_40CO_B1S0
, 0xFFDF);
1761 b43_phy_mask(dev
, B43_NPHY_TXF_40CO_B32S1
, 0xFFDF);
1762 b43_phy_mask(dev
, B43_NPHY_RFCTL_LUT_TRSW_UP1
, 0xFFC3);
1763 b43_phy_mask(dev
, B43_NPHY_RFCTL_LUT_TRSW_UP2
, 0xFFC3);
1765 for (i
= 0; i
< 2; i
++) {
1766 if ((code
== 1 && i
== 1) || (code
== 2 && !i
))
1770 B43_NPHY_AFECTL_OVER1
: B43_NPHY_AFECTL_OVER
;
1771 b43_phy_maskset(dev
, reg
, 0xFDFF, 0x0200);
1773 if (rssi_type
== N_RSSI_W1
||
1774 rssi_type
== N_RSSI_W2
||
1775 rssi_type
== N_RSSI_NB
) {
1777 B43_NPHY_AFECTL_C1
:
1779 b43_phy_maskset(dev
, reg
, 0xFCFF, 0);
1782 B43_NPHY_RFCTL_LUT_TRSW_UP1
:
1783 B43_NPHY_RFCTL_LUT_TRSW_UP2
;
1784 b43_phy_maskset(dev
, reg
, 0xFFC3, 0);
1786 if (rssi_type
== N_RSSI_W1
)
1787 val
= (b43_current_band(dev
->wl
) == IEEE80211_BAND_5GHZ
) ? 4 : 8;
1788 else if (rssi_type
== N_RSSI_W2
)
1792 b43_phy_set(dev
, reg
, val
);
1795 B43_NPHY_TXF_40CO_B1S0
:
1796 B43_NPHY_TXF_40CO_B32S1
;
1797 b43_phy_set(dev
, reg
, 0x0020);
1799 if (rssi_type
== N_RSSI_TBD
)
1801 else if (rssi_type
== N_RSSI_IQ
)
1807 B43_NPHY_AFECTL_C1
:
1810 b43_phy_maskset(dev
, reg
, 0xFCFF, val
);
1811 b43_phy_maskset(dev
, reg
, 0xF3FF, val
<< 2);
1813 if (rssi_type
!= N_RSSI_IQ
&&
1814 rssi_type
!= N_RSSI_TBD
) {
1815 enum ieee80211_band band
=
1816 b43_current_band(dev
->wl
);
1818 if (dev
->phy
.rev
< 7) {
1819 if (b43_nphy_ipa(dev
))
1820 val
= (band
== IEEE80211_BAND_5GHZ
) ? 0xC : 0xE;
1823 reg
= (i
== 0) ? B2056_TX0
: B2056_TX1
;
1824 reg
|= B2056_TX_TX_SSI_MUX
;
1825 b43_radio_write(dev
, reg
, val
);
1829 B43_NPHY_AFECTL_OVER1
:
1830 B43_NPHY_AFECTL_OVER
;
1831 b43_phy_set(dev
, reg
, 0x0200);
1838 static void b43_nphy_rev2_rssi_select(struct b43_wldev
*dev
, u8 code
,
1839 enum n_rssi_type rssi_type
)
1842 bool rssi_w1_w2_nb
= false;
1844 switch (rssi_type
) {
1849 rssi_w1_w2_nb
= true;
1861 val
= (val
<< 12) | (val
<< 14);
1862 b43_phy_maskset(dev
, B43_NPHY_AFECTL_C1
, 0x0FFF, val
);
1863 b43_phy_maskset(dev
, B43_NPHY_AFECTL_C2
, 0x0FFF, val
);
1865 if (rssi_w1_w2_nb
) {
1866 b43_phy_maskset(dev
, B43_NPHY_RFCTL_RSSIO1
, 0xFFCF,
1867 (rssi_type
+ 1) << 4);
1868 b43_phy_maskset(dev
, B43_NPHY_RFCTL_RSSIO2
, 0xFFCF,
1869 (rssi_type
+ 1) << 4);
1873 b43_phy_mask(dev
, B43_NPHY_AFECTL_OVER
, ~0x3000);
1874 if (rssi_w1_w2_nb
) {
1875 b43_phy_mask(dev
, B43_NPHY_RFCTL_CMD
,
1876 ~(B43_NPHY_RFCTL_CMD_RXEN
|
1877 B43_NPHY_RFCTL_CMD_CORESEL
));
1878 b43_phy_mask(dev
, B43_NPHY_RFCTL_OVER
,
1883 b43_phy_mask(dev
, B43_NPHY_RFCTL_CMD
,
1884 ~B43_NPHY_RFCTL_CMD_START
);
1886 b43_phy_mask(dev
, B43_NPHY_RFCTL_OVER
, ~0x1);
1889 b43_phy_set(dev
, B43_NPHY_AFECTL_OVER
, 0x3000);
1890 if (rssi_w1_w2_nb
) {
1891 b43_phy_maskset(dev
, B43_NPHY_RFCTL_CMD
,
1892 ~(B43_NPHY_RFCTL_CMD_RXEN
|
1893 B43_NPHY_RFCTL_CMD_CORESEL
),
1894 (B43_NPHY_RFCTL_CMD_RXEN
|
1895 code
<< B43_NPHY_RFCTL_CMD_CORESEL_SHIFT
));
1896 b43_phy_set(dev
, B43_NPHY_RFCTL_OVER
,
1901 b43_phy_set(dev
, B43_NPHY_RFCTL_CMD
,
1902 B43_NPHY_RFCTL_CMD_START
);
1904 b43_phy_mask(dev
, B43_NPHY_RFCTL_OVER
, ~0x1);
1909 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSISel */
1910 static void b43_nphy_rssi_select(struct b43_wldev
*dev
, u8 code
,
1911 enum n_rssi_type type
)
1913 if (dev
->phy
.rev
>= 19)
1914 b43_nphy_rssi_select_rev19(dev
, code
, type
);
1915 else if (dev
->phy
.rev
>= 3)
1916 b43_nphy_rev3_rssi_select(dev
, code
, type
);
1918 b43_nphy_rev2_rssi_select(dev
, code
, type
);
1921 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRssi2055Vcm */
1922 static void b43_nphy_set_rssi_2055_vcm(struct b43_wldev
*dev
,
1923 enum n_rssi_type rssi_type
, u8
*buf
)
1926 for (i
= 0; i
< 2; i
++) {
1927 if (rssi_type
== N_RSSI_NB
) {
1929 b43_radio_maskset(dev
, B2055_C1_B0NB_RSSIVCM
,
1931 b43_radio_maskset(dev
, B2055_C1_RX_BB_RSSICTL5
,
1934 b43_radio_maskset(dev
, B2055_C2_B0NB_RSSIVCM
,
1936 b43_radio_maskset(dev
, B2055_C2_RX_BB_RSSICTL5
,
1937 0xFC, buf
[2 * i
+ 1]);
1941 b43_radio_maskset(dev
, B2055_C1_RX_BB_RSSICTL5
,
1944 b43_radio_maskset(dev
, B2055_C2_RX_BB_RSSICTL5
,
1945 0xF3, buf
[2 * i
+ 1] << 2);
1950 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PollRssi */
1951 static int b43_nphy_poll_rssi(struct b43_wldev
*dev
, enum n_rssi_type rssi_type
,
1956 u16 save_regs_phy
[9];
1959 /* TODO: rev7+ is treated like rev3+, what about rev19+? */
1961 if (dev
->phy
.rev
>= 3) {
1962 save_regs_phy
[0] = b43_phy_read(dev
, B43_NPHY_AFECTL_C1
);
1963 save_regs_phy
[1] = b43_phy_read(dev
, B43_NPHY_AFECTL_C2
);
1964 save_regs_phy
[2] = b43_phy_read(dev
,
1965 B43_NPHY_RFCTL_LUT_TRSW_UP1
);
1966 save_regs_phy
[3] = b43_phy_read(dev
,
1967 B43_NPHY_RFCTL_LUT_TRSW_UP2
);
1968 save_regs_phy
[4] = b43_phy_read(dev
, B43_NPHY_AFECTL_OVER1
);
1969 save_regs_phy
[5] = b43_phy_read(dev
, B43_NPHY_AFECTL_OVER
);
1970 save_regs_phy
[6] = b43_phy_read(dev
, B43_NPHY_TXF_40CO_B1S0
);
1971 save_regs_phy
[7] = b43_phy_read(dev
, B43_NPHY_TXF_40CO_B32S1
);
1972 save_regs_phy
[8] = 0;
1974 save_regs_phy
[0] = b43_phy_read(dev
, B43_NPHY_AFECTL_C1
);
1975 save_regs_phy
[1] = b43_phy_read(dev
, B43_NPHY_AFECTL_C2
);
1976 save_regs_phy
[2] = b43_phy_read(dev
, B43_NPHY_AFECTL_OVER
);
1977 save_regs_phy
[3] = b43_phy_read(dev
, B43_NPHY_RFCTL_CMD
);
1978 save_regs_phy
[4] = b43_phy_read(dev
, B43_NPHY_RFCTL_OVER
);
1979 save_regs_phy
[5] = b43_phy_read(dev
, B43_NPHY_RFCTL_RSSIO1
);
1980 save_regs_phy
[6] = b43_phy_read(dev
, B43_NPHY_RFCTL_RSSIO2
);
1981 save_regs_phy
[7] = 0;
1982 save_regs_phy
[8] = 0;
1985 b43_nphy_rssi_select(dev
, 5, rssi_type
);
1987 if (dev
->phy
.rev
< 2) {
1988 save_regs_phy
[8] = b43_phy_read(dev
, B43_NPHY_GPIO_SEL
);
1989 b43_phy_write(dev
, B43_NPHY_GPIO_SEL
, 5);
1992 for (i
= 0; i
< 4; i
++)
1995 for (i
= 0; i
< nsamp
; i
++) {
1996 if (dev
->phy
.rev
< 2) {
1997 s
[0] = b43_phy_read(dev
, B43_NPHY_GPIO_LOOUT
);
1998 s
[1] = b43_phy_read(dev
, B43_NPHY_GPIO_HIOUT
);
2000 s
[0] = b43_phy_read(dev
, B43_NPHY_RSSI1
);
2001 s
[1] = b43_phy_read(dev
, B43_NPHY_RSSI2
);
2004 buf
[0] += ((s8
)((s
[0] & 0x3F) << 2)) >> 2;
2005 buf
[1] += ((s8
)(((s
[0] >> 8) & 0x3F) << 2)) >> 2;
2006 buf
[2] += ((s8
)((s
[1] & 0x3F) << 2)) >> 2;
2007 buf
[3] += ((s8
)(((s
[1] >> 8) & 0x3F) << 2)) >> 2;
2009 out
= (buf
[0] & 0xFF) << 24 | (buf
[1] & 0xFF) << 16 |
2010 (buf
[2] & 0xFF) << 8 | (buf
[3] & 0xFF);
2012 if (dev
->phy
.rev
< 2)
2013 b43_phy_write(dev
, B43_NPHY_GPIO_SEL
, save_regs_phy
[8]);
2015 if (dev
->phy
.rev
>= 3) {
2016 b43_phy_write(dev
, B43_NPHY_AFECTL_C1
, save_regs_phy
[0]);
2017 b43_phy_write(dev
, B43_NPHY_AFECTL_C2
, save_regs_phy
[1]);
2018 b43_phy_write(dev
, B43_NPHY_RFCTL_LUT_TRSW_UP1
,
2020 b43_phy_write(dev
, B43_NPHY_RFCTL_LUT_TRSW_UP2
,
2022 b43_phy_write(dev
, B43_NPHY_AFECTL_OVER1
, save_regs_phy
[4]);
2023 b43_phy_write(dev
, B43_NPHY_AFECTL_OVER
, save_regs_phy
[5]);
2024 b43_phy_write(dev
, B43_NPHY_TXF_40CO_B1S0
, save_regs_phy
[6]);
2025 b43_phy_write(dev
, B43_NPHY_TXF_40CO_B32S1
, save_regs_phy
[7]);
2027 b43_phy_write(dev
, B43_NPHY_AFECTL_C1
, save_regs_phy
[0]);
2028 b43_phy_write(dev
, B43_NPHY_AFECTL_C2
, save_regs_phy
[1]);
2029 b43_phy_write(dev
, B43_NPHY_AFECTL_OVER
, save_regs_phy
[2]);
2030 b43_phy_write(dev
, B43_NPHY_RFCTL_CMD
, save_regs_phy
[3]);
2031 b43_phy_write(dev
, B43_NPHY_RFCTL_OVER
, save_regs_phy
[4]);
2032 b43_phy_write(dev
, B43_NPHY_RFCTL_RSSIO1
, save_regs_phy
[5]);
2033 b43_phy_write(dev
, B43_NPHY_RFCTL_RSSIO2
, save_regs_phy
[6]);
2039 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICalRev3 */
2040 static void b43_nphy_rev3_rssi_cal(struct b43_wldev
*dev
)
2042 struct b43_phy
*phy
= &dev
->phy
;
2043 struct b43_phy_n
*nphy
= dev
->phy
.n
;
2045 u16 saved_regs_phy_rfctl
[2];
2046 u16 saved_regs_phy
[22];
2047 u16 regs_to_store_rev3
[] = {
2048 B43_NPHY_AFECTL_OVER1
, B43_NPHY_AFECTL_OVER
,
2049 B43_NPHY_AFECTL_C1
, B43_NPHY_AFECTL_C2
,
2050 B43_NPHY_TXF_40CO_B1S1
, B43_NPHY_RFCTL_OVER
,
2051 B43_NPHY_TXF_40CO_B1S0
, B43_NPHY_TXF_40CO_B32S1
,
2053 B43_NPHY_RFCTL_LUT_TRSW_UP1
, B43_NPHY_RFCTL_LUT_TRSW_UP2
,
2054 B43_NPHY_RFCTL_RSSIO1
, B43_NPHY_RFCTL_RSSIO2
2056 u16 regs_to_store_rev7
[] = {
2057 B43_NPHY_AFECTL_OVER1
, B43_NPHY_AFECTL_OVER
,
2058 B43_NPHY_AFECTL_C1
, B43_NPHY_AFECTL_C2
,
2059 B43_NPHY_TXF_40CO_B1S1
, B43_NPHY_RFCTL_OVER
,
2060 B43_NPHY_REV7_RF_CTL_OVER3
, B43_NPHY_REV7_RF_CTL_OVER4
,
2061 B43_NPHY_REV7_RF_CTL_OVER5
, B43_NPHY_REV7_RF_CTL_OVER6
,
2063 B43_NPHY_TXF_40CO_B1S0
, B43_NPHY_TXF_40CO_B32S1
,
2065 B43_NPHY_RFCTL_LUT_TRSW_UP1
, B43_NPHY_RFCTL_LUT_TRSW_UP2
,
2066 B43_NPHY_REV7_RF_CTL_MISC_REG3
, B43_NPHY_REV7_RF_CTL_MISC_REG4
,
2067 B43_NPHY_REV7_RF_CTL_MISC_REG5
, B43_NPHY_REV7_RF_CTL_MISC_REG6
,
2068 B43_NPHY_RFCTL_RSSIO1
, B43_NPHY_RFCTL_RSSIO2
2076 u16 clip_off
[2] = { 0xFFFF, 0xFFFF };
2080 s32 results
[8][4] = { };
2081 s32 results_min
[4] = { };
2082 s32 poll_results
[4] = { };
2084 u16
*rssical_radio_regs
= NULL
;
2085 u16
*rssical_phy_regs
= NULL
;
2087 u16 r
; /* routing */
2089 int core
, i
, j
, vcm
;
2091 if (dev
->phy
.rev
>= 7) {
2092 regs_to_store
= regs_to_store_rev7
;
2093 regs_amount
= ARRAY_SIZE(regs_to_store_rev7
);
2095 regs_to_store
= regs_to_store_rev3
;
2096 regs_amount
= ARRAY_SIZE(regs_to_store_rev3
);
2098 BUG_ON(regs_amount
> ARRAY_SIZE(saved_regs_phy
));
2100 class = b43_nphy_classifier(dev
, 0, 0);
2101 b43_nphy_classifier(dev
, 7, 4);
2102 b43_nphy_read_clip_detection(dev
, clip_state
);
2103 b43_nphy_write_clip_detection(dev
, clip_off
);
2105 saved_regs_phy_rfctl
[0] = b43_phy_read(dev
, B43_NPHY_RFCTL_INTC1
);
2106 saved_regs_phy_rfctl
[1] = b43_phy_read(dev
, B43_NPHY_RFCTL_INTC2
);
2107 for (i
= 0; i
< regs_amount
; i
++)
2108 saved_regs_phy
[i
] = b43_phy_read(dev
, regs_to_store
[i
]);
2110 b43_nphy_rf_ctl_intc_override(dev
, N_INTC_OVERRIDE_OFF
, 0, 7);
2111 b43_nphy_rf_ctl_intc_override(dev
, N_INTC_OVERRIDE_TRSW
, 1, 7);
2113 if (dev
->phy
.rev
>= 7) {
2114 b43_nphy_rf_ctl_override_one_to_many(dev
,
2115 N_RF_CTL_OVER_CMD_RXRF_PU
,
2117 b43_nphy_rf_ctl_override_one_to_many(dev
,
2118 N_RF_CTL_OVER_CMD_RX_PU
,
2120 b43_nphy_rf_ctl_override_rev7(dev
, 0x80, 1, 0, false, 0);
2121 b43_nphy_rf_ctl_override_rev7(dev
, 0x40, 1, 0, false, 0);
2122 if (b43_current_band(dev
->wl
) == IEEE80211_BAND_5GHZ
) {
2123 b43_nphy_rf_ctl_override_rev7(dev
, 0x20, 0, 0, false,
2125 b43_nphy_rf_ctl_override_rev7(dev
, 0x10, 1, 0, false,
2128 b43_nphy_rf_ctl_override_rev7(dev
, 0x10, 0, 0, false,
2130 b43_nphy_rf_ctl_override_rev7(dev
, 0x20, 1, 0, false,
2134 b43_nphy_rf_ctl_override(dev
, 0x1, 0, 0, false);
2135 b43_nphy_rf_ctl_override(dev
, 0x2, 1, 0, false);
2136 b43_nphy_rf_ctl_override(dev
, 0x80, 1, 0, false);
2137 b43_nphy_rf_ctl_override(dev
, 0x40, 1, 0, false);
2138 if (b43_current_band(dev
->wl
) == IEEE80211_BAND_5GHZ
) {
2139 b43_nphy_rf_ctl_override(dev
, 0x20, 0, 0, false);
2140 b43_nphy_rf_ctl_override(dev
, 0x10, 1, 0, false);
2142 b43_nphy_rf_ctl_override(dev
, 0x10, 0, 0, false);
2143 b43_nphy_rf_ctl_override(dev
, 0x20, 1, 0, false);
2147 rx_core_state
= b43_nphy_get_rx_core_state(dev
);
2148 for (core
= 0; core
< 2; core
++) {
2149 if (!(rx_core_state
& (1 << core
)))
2151 r
= core
? B2056_RX1
: B2056_RX0
;
2152 b43_nphy_scale_offset_rssi(dev
, 0, 0, core
+ 1, N_RAIL_I
,
2154 b43_nphy_scale_offset_rssi(dev
, 0, 0, core
+ 1, N_RAIL_Q
,
2157 /* Grab RSSI results for every possible VCM */
2158 for (vcm
= 0; vcm
< 8; vcm
++) {
2159 if (dev
->phy
.rev
>= 7)
2160 b43_radio_maskset(dev
,
2161 core
? R2057_NB_MASTER_CORE1
:
2162 R2057_NB_MASTER_CORE0
,
2163 ~R2057_VCM_MASK
, vcm
);
2165 b43_radio_maskset(dev
, r
| B2056_RX_RSSI_MISC
,
2167 b43_nphy_poll_rssi(dev
, N_RSSI_NB
, results
[vcm
], 8);
2170 /* Find out which VCM got the best results */
2171 for (i
= 0; i
< 4; i
+= 2) {
2173 s32 mind
= 0x100000;
2178 for (vcm
= 0; vcm
< 8; vcm
++) {
2179 currd
= results
[vcm
][i
] * results
[vcm
][i
] +
2180 results
[vcm
][i
+ 1] * results
[vcm
][i
];
2185 if (results
[vcm
][i
] < minpoll
)
2186 minpoll
= results
[vcm
][i
];
2189 results_min
[i
] = minpoll
;
2192 /* Select the best VCM */
2193 if (dev
->phy
.rev
>= 7)
2194 b43_radio_maskset(dev
,
2195 core
? R2057_NB_MASTER_CORE1
:
2196 R2057_NB_MASTER_CORE0
,
2197 ~R2057_VCM_MASK
, vcm
);
2199 b43_radio_maskset(dev
, r
| B2056_RX_RSSI_MISC
,
2200 0xE3, vcm_final
<< 2);
2202 for (i
= 0; i
< 4; i
++) {
2205 offset
[i
] = -results
[vcm_final
][i
];
2207 offset
[i
] = -((abs(offset
[i
]) + 4) / 8);
2209 offset
[i
] = (offset
[i
] + 4) / 8;
2210 if (results_min
[i
] == 248)
2212 b43_nphy_scale_offset_rssi(dev
, 0, offset
[i
],
2213 (i
/ 2 == 0) ? 1 : 2,
2214 (i
% 2 == 0) ? N_RAIL_I
: N_RAIL_Q
,
2219 for (core
= 0; core
< 2; core
++) {
2220 if (!(rx_core_state
& (1 << core
)))
2222 for (i
= 0; i
< 2; i
++) {
2223 b43_nphy_scale_offset_rssi(dev
, 0, 0, core
+ 1,
2225 b43_nphy_scale_offset_rssi(dev
, 0, 0, core
+ 1,
2227 b43_nphy_poll_rssi(dev
, i
, poll_results
, 8);
2228 for (j
= 0; j
< 4; j
++) {
2229 if (j
/ 2 == core
) {
2230 offset
[j
] = 232 - poll_results
[j
];
2232 offset
[j
] = -(abs(offset
[j
] + 4) / 8);
2234 offset
[j
] = (offset
[j
] + 4) / 8;
2235 b43_nphy_scale_offset_rssi(dev
, 0,
2236 offset
[2 * core
], core
+ 1, j
% 2, i
);
2242 b43_phy_write(dev
, B43_NPHY_RFCTL_INTC1
, saved_regs_phy_rfctl
[0]);
2243 b43_phy_write(dev
, B43_NPHY_RFCTL_INTC2
, saved_regs_phy_rfctl
[1]);
2245 b43_nphy_force_rf_sequence(dev
, B43_RFSEQ_RESET2RX
);
2247 b43_phy_set(dev
, B43_NPHY_TXF_40CO_B1S1
, 0x1);
2248 b43_phy_set(dev
, B43_NPHY_RFCTL_CMD
, B43_NPHY_RFCTL_CMD_START
);
2249 b43_phy_mask(dev
, B43_NPHY_TXF_40CO_B1S1
, ~0x1);
2251 b43_phy_set(dev
, B43_NPHY_RFCTL_OVER
, 0x1);
2252 b43_phy_set(dev
, B43_NPHY_RFCTL_CMD
, B43_NPHY_RFCTL_CMD_RXTX
);
2253 b43_phy_mask(dev
, B43_NPHY_RFCTL_OVER
, ~0x1);
2255 for (i
= 0; i
< regs_amount
; i
++)
2256 b43_phy_write(dev
, regs_to_store
[i
], saved_regs_phy
[i
]);
2258 /* Store for future configuration */
2259 if (b43_current_band(dev
->wl
) == IEEE80211_BAND_2GHZ
) {
2260 rssical_radio_regs
= nphy
->rssical_cache
.rssical_radio_regs_2G
;
2261 rssical_phy_regs
= nphy
->rssical_cache
.rssical_phy_regs_2G
;
2263 rssical_radio_regs
= nphy
->rssical_cache
.rssical_radio_regs_5G
;
2264 rssical_phy_regs
= nphy
->rssical_cache
.rssical_phy_regs_5G
;
2266 if (dev
->phy
.rev
>= 7) {
2267 rssical_radio_regs
[0] = b43_radio_read(dev
,
2268 R2057_NB_MASTER_CORE0
);
2269 rssical_radio_regs
[1] = b43_radio_read(dev
,
2270 R2057_NB_MASTER_CORE1
);
2272 rssical_radio_regs
[0] = b43_radio_read(dev
, B2056_RX0
|
2273 B2056_RX_RSSI_MISC
);
2274 rssical_radio_regs
[1] = b43_radio_read(dev
, B2056_RX1
|
2275 B2056_RX_RSSI_MISC
);
2277 rssical_phy_regs
[0] = b43_phy_read(dev
, B43_NPHY_RSSIMC_0I_RSSI_Z
);
2278 rssical_phy_regs
[1] = b43_phy_read(dev
, B43_NPHY_RSSIMC_0Q_RSSI_Z
);
2279 rssical_phy_regs
[2] = b43_phy_read(dev
, B43_NPHY_RSSIMC_1I_RSSI_Z
);
2280 rssical_phy_regs
[3] = b43_phy_read(dev
, B43_NPHY_RSSIMC_1Q_RSSI_Z
);
2281 rssical_phy_regs
[4] = b43_phy_read(dev
, B43_NPHY_RSSIMC_0I_RSSI_X
);
2282 rssical_phy_regs
[5] = b43_phy_read(dev
, B43_NPHY_RSSIMC_0Q_RSSI_X
);
2283 rssical_phy_regs
[6] = b43_phy_read(dev
, B43_NPHY_RSSIMC_1I_RSSI_X
);
2284 rssical_phy_regs
[7] = b43_phy_read(dev
, B43_NPHY_RSSIMC_1Q_RSSI_X
);
2285 rssical_phy_regs
[8] = b43_phy_read(dev
, B43_NPHY_RSSIMC_0I_RSSI_Y
);
2286 rssical_phy_regs
[9] = b43_phy_read(dev
, B43_NPHY_RSSIMC_0Q_RSSI_Y
);
2287 rssical_phy_regs
[10] = b43_phy_read(dev
, B43_NPHY_RSSIMC_1I_RSSI_Y
);
2288 rssical_phy_regs
[11] = b43_phy_read(dev
, B43_NPHY_RSSIMC_1Q_RSSI_Y
);
2290 /* Remember for which channel we store configuration */
2291 if (b43_current_band(dev
->wl
) == IEEE80211_BAND_2GHZ
)
2292 nphy
->rssical_chanspec_2G
.center_freq
= phy
->chandef
->chan
->center_freq
;
2294 nphy
->rssical_chanspec_5G
.center_freq
= phy
->chandef
->chan
->center_freq
;
2296 /* End of calibration, restore configuration */
2297 b43_nphy_classifier(dev
, 7, class);
2298 b43_nphy_write_clip_detection(dev
, clip_state
);
2301 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal */
2302 static void b43_nphy_rev2_rssi_cal(struct b43_wldev
*dev
, enum n_rssi_type type
)
2307 u16
class, override
;
2308 u8 regs_save_radio
[2];
2309 u16 regs_save_phy
[2];
2316 u16 clip_off
[2] = { 0xFFFF, 0xFFFF };
2317 s32 results_min
[4] = { };
2318 u8 vcm_final
[4] = { };
2319 s32 results
[4][4] = { };
2320 s32 miniq
[4][2] = { };
2322 if (type
== N_RSSI_NB
) {
2325 } else if (type
== N_RSSI_W1
|| type
== N_RSSI_W2
) {
2333 class = b43_nphy_classifier(dev
, 0, 0);
2334 b43_nphy_classifier(dev
, 7, 4);
2335 b43_nphy_read_clip_detection(dev
, clip_state
);
2336 b43_nphy_write_clip_detection(dev
, clip_off
);
2338 if (b43_current_band(dev
->wl
) == IEEE80211_BAND_5GHZ
)
2343 regs_save_phy
[0] = b43_phy_read(dev
, B43_NPHY_RFCTL_INTC1
);
2344 regs_save_radio
[0] = b43_radio_read(dev
, B2055_C1_PD_RXTX
);
2345 b43_phy_write(dev
, B43_NPHY_RFCTL_INTC1
, override
);
2346 b43_radio_write(dev
, B2055_C1_PD_RXTX
, val
);
2348 regs_save_phy
[1] = b43_phy_read(dev
, B43_NPHY_RFCTL_INTC2
);
2349 regs_save_radio
[1] = b43_radio_read(dev
, B2055_C2_PD_RXTX
);
2350 b43_phy_write(dev
, B43_NPHY_RFCTL_INTC2
, override
);
2351 b43_radio_write(dev
, B2055_C2_PD_RXTX
, val
);
2353 state
[0] = b43_radio_read(dev
, B2055_C1_PD_RSSIMISC
) & 0x07;
2354 state
[1] = b43_radio_read(dev
, B2055_C2_PD_RSSIMISC
) & 0x07;
2355 b43_radio_mask(dev
, B2055_C1_PD_RSSIMISC
, 0xF8);
2356 b43_radio_mask(dev
, B2055_C2_PD_RSSIMISC
, 0xF8);
2357 state
[2] = b43_radio_read(dev
, B2055_C1_SP_RSSI
) & 0x07;
2358 state
[3] = b43_radio_read(dev
, B2055_C2_SP_RSSI
) & 0x07;
2360 b43_nphy_rssi_select(dev
, 5, type
);
2361 b43_nphy_scale_offset_rssi(dev
, 0, 0, 5, N_RAIL_I
, type
);
2362 b43_nphy_scale_offset_rssi(dev
, 0, 0, 5, N_RAIL_Q
, type
);
2364 for (vcm
= 0; vcm
< 4; vcm
++) {
2366 for (j
= 0; j
< 4; j
++)
2368 if (type
!= N_RSSI_W2
)
2369 b43_nphy_set_rssi_2055_vcm(dev
, type
, tmp
);
2370 b43_nphy_poll_rssi(dev
, type
, results
[vcm
], 8);
2371 if (type
== N_RSSI_W1
|| type
== N_RSSI_W2
)
2372 for (j
= 0; j
< 2; j
++)
2373 miniq
[vcm
][j
] = min(results
[vcm
][2 * j
],
2374 results
[vcm
][2 * j
+ 1]);
2377 for (i
= 0; i
< 4; i
++) {
2378 s32 mind
= 0x100000;
2382 for (vcm
= 0; vcm
< 4; vcm
++) {
2383 if (type
== N_RSSI_NB
)
2384 currd
= abs(results
[vcm
][i
] - code
* 8);
2386 currd
= abs(miniq
[vcm
][i
/ 2] - code
* 8);
2393 if (results
[vcm
][i
] < minpoll
)
2394 minpoll
= results
[vcm
][i
];
2396 results_min
[i
] = minpoll
;
2397 vcm_final
[i
] = minvcm
;
2400 if (type
!= N_RSSI_W2
)
2401 b43_nphy_set_rssi_2055_vcm(dev
, type
, vcm_final
);
2403 for (i
= 0; i
< 4; i
++) {
2404 offset
[i
] = (code
* 8) - results
[vcm_final
[i
]][i
];
2407 offset
[i
] = -((abs(offset
[i
]) + 4) / 8);
2409 offset
[i
] = (offset
[i
] + 4) / 8;
2411 if (results_min
[i
] == 248)
2412 offset
[i
] = code
- 32;
2414 core
= (i
/ 2) ? 2 : 1;
2415 rail
= (i
% 2) ? N_RAIL_Q
: N_RAIL_I
;
2417 b43_nphy_scale_offset_rssi(dev
, 0, offset
[i
], core
, rail
,
2421 b43_radio_maskset(dev
, B2055_C1_PD_RSSIMISC
, 0xF8, state
[0]);
2422 b43_radio_maskset(dev
, B2055_C2_PD_RSSIMISC
, 0xF8, state
[1]);
2426 b43_nphy_rssi_select(dev
, 1, N_RSSI_NB
);
2429 b43_nphy_rssi_select(dev
, 1, N_RSSI_W1
);
2432 b43_nphy_rssi_select(dev
, 1, N_RSSI_W2
);
2435 b43_nphy_rssi_select(dev
, 1, N_RSSI_W2
);
2441 b43_nphy_rssi_select(dev
, 2, N_RSSI_NB
);
2444 b43_nphy_rssi_select(dev
, 2, N_RSSI_W1
);
2447 b43_nphy_rssi_select(dev
, 2, N_RSSI_W2
);
2451 b43_nphy_rssi_select(dev
, 0, type
);
2453 b43_phy_write(dev
, B43_NPHY_RFCTL_INTC1
, regs_save_phy
[0]);
2454 b43_radio_write(dev
, B2055_C1_PD_RXTX
, regs_save_radio
[0]);
2455 b43_phy_write(dev
, B43_NPHY_RFCTL_INTC2
, regs_save_phy
[1]);
2456 b43_radio_write(dev
, B2055_C2_PD_RXTX
, regs_save_radio
[1]);
2458 b43_nphy_classifier(dev
, 7, class);
2459 b43_nphy_write_clip_detection(dev
, clip_state
);
2460 /* Specs don't say about reset here, but it makes wl and b43 dumps
2461 identical, it really seems wl performs this */
2462 b43_nphy_reset_cca(dev
);
2467 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal
2469 static void b43_nphy_rssi_cal(struct b43_wldev
*dev
)
2471 if (dev
->phy
.rev
>= 19) {
2473 } else if (dev
->phy
.rev
>= 3) {
2474 b43_nphy_rev3_rssi_cal(dev
);
2476 b43_nphy_rev2_rssi_cal(dev
, N_RSSI_NB
);
2477 b43_nphy_rev2_rssi_cal(dev
, N_RSSI_W1
);
2478 b43_nphy_rev2_rssi_cal(dev
, N_RSSI_W2
);
2482 /**************************************************
2484 **************************************************/
2486 static void b43_nphy_gain_ctl_workarounds_rev19(struct b43_wldev
*dev
)
2491 static void b43_nphy_gain_ctl_workarounds_rev7(struct b43_wldev
*dev
)
2493 struct b43_phy
*phy
= &dev
->phy
;
2500 static void b43_nphy_gain_ctl_workarounds_rev3(struct b43_wldev
*dev
)
2502 struct ssb_sprom
*sprom
= dev
->dev
->bus_sprom
;
2507 struct nphy_gain_ctl_workaround_entry
*e
;
2508 u8 lpf_gain
[6] = { 0x00, 0x06, 0x0C, 0x12, 0x12, 0x12 };
2509 u8 lpf_bits
[6] = { 0, 1, 2, 3, 3, 3 };
2511 /* Prepare values */
2512 ghz5
= b43_phy_read(dev
, B43_NPHY_BANDCTL
)
2513 & B43_NPHY_BANDCTL_5GHZ
;
2514 ext_lna
= ghz5
? sprom
->boardflags_hi
& B43_BFH_EXTLNA_5GHZ
:
2515 sprom
->boardflags_lo
& B43_BFL_EXTLNA
;
2516 e
= b43_nphy_get_gain_ctl_workaround_ent(dev
, ghz5
, ext_lna
);
2517 if (ghz5
&& dev
->phy
.rev
>= 5)
2522 b43_phy_set(dev
, B43_NPHY_RXCTL
, 0x0040);
2524 /* Set Clip 2 detect */
2525 b43_phy_set(dev
, B43_NPHY_C1_CGAINI
, B43_NPHY_C1_CGAINI_CL2DETECT
);
2526 b43_phy_set(dev
, B43_NPHY_C2_CGAINI
, B43_NPHY_C2_CGAINI_CL2DETECT
);
2528 b43_radio_write(dev
, B2056_RX0
| B2056_RX_BIASPOLE_LNAG1_IDAC
,
2530 b43_radio_write(dev
, B2056_RX1
| B2056_RX_BIASPOLE_LNAG1_IDAC
,
2532 b43_radio_write(dev
, B2056_RX0
| B2056_RX_LNAG2_IDAC
, 0xF0);
2533 b43_radio_write(dev
, B2056_RX1
| B2056_RX_LNAG2_IDAC
, 0xF0);
2534 b43_radio_write(dev
, B2056_RX0
| B2056_RX_RSSI_POLE
, 0x00);
2535 b43_radio_write(dev
, B2056_RX1
| B2056_RX_RSSI_POLE
, 0x00);
2536 b43_radio_write(dev
, B2056_RX0
| B2056_RX_RSSI_GAIN
,
2538 b43_radio_write(dev
, B2056_RX1
| B2056_RX_RSSI_GAIN
,
2540 b43_radio_write(dev
, B2056_RX0
| B2056_RX_BIASPOLE_LNAA1_IDAC
,
2542 b43_radio_write(dev
, B2056_RX1
| B2056_RX_BIASPOLE_LNAA1_IDAC
,
2544 b43_radio_write(dev
, B2056_RX0
| B2056_RX_LNAA2_IDAC
, 0xFF);
2545 b43_radio_write(dev
, B2056_RX1
| B2056_RX_LNAA2_IDAC
, 0xFF);
2547 b43_ntab_write_bulk(dev
, B43_NTAB8(0, 8), 4, e
->lna1_gain
);
2548 b43_ntab_write_bulk(dev
, B43_NTAB8(1, 8), 4, e
->lna1_gain
);
2549 b43_ntab_write_bulk(dev
, B43_NTAB8(0, 16), 4, e
->lna2_gain
);
2550 b43_ntab_write_bulk(dev
, B43_NTAB8(1, 16), 4, e
->lna2_gain
);
2551 b43_ntab_write_bulk(dev
, B43_NTAB8(0, 32), 10, e
->gain_db
);
2552 b43_ntab_write_bulk(dev
, B43_NTAB8(1, 32), 10, e
->gain_db
);
2553 b43_ntab_write_bulk(dev
, B43_NTAB8(2, 32), 10, e
->gain_bits
);
2554 b43_ntab_write_bulk(dev
, B43_NTAB8(3, 32), 10, e
->gain_bits
);
2555 b43_ntab_write_bulk(dev
, B43_NTAB8(0, 0x40), 6, lpf_gain
);
2556 b43_ntab_write_bulk(dev
, B43_NTAB8(1, 0x40), 6, lpf_gain
);
2557 b43_ntab_write_bulk(dev
, B43_NTAB8(2, 0x40), 6, lpf_bits
);
2558 b43_ntab_write_bulk(dev
, B43_NTAB8(3, 0x40), 6, lpf_bits
);
2560 b43_phy_write(dev
, B43_NPHY_REV3_C1_INITGAIN_A
, e
->init_gain
);
2561 b43_phy_write(dev
, B43_NPHY_REV3_C2_INITGAIN_A
, e
->init_gain
);
2563 b43_ntab_write_bulk(dev
, B43_NTAB16(7, 0x106), 2,
2566 b43_phy_write(dev
, B43_NPHY_REV3_C1_CLIP_HIGAIN_A
, e
->cliphi_gain
);
2567 b43_phy_write(dev
, B43_NPHY_REV3_C2_CLIP_HIGAIN_A
, e
->cliphi_gain
);
2568 b43_phy_write(dev
, B43_NPHY_REV3_C1_CLIP_MEDGAIN_A
, e
->clipmd_gain
);
2569 b43_phy_write(dev
, B43_NPHY_REV3_C2_CLIP_MEDGAIN_A
, e
->clipmd_gain
);
2570 b43_phy_write(dev
, B43_NPHY_REV3_C1_CLIP_LOGAIN_A
, e
->cliplo_gain
);
2571 b43_phy_write(dev
, B43_NPHY_REV3_C2_CLIP_LOGAIN_A
, e
->cliplo_gain
);
2573 b43_phy_maskset(dev
, B43_NPHY_CRSMINPOWER0
, 0xFF00, e
->crsmin
);
2574 b43_phy_maskset(dev
, B43_NPHY_CRSMINPOWERL0
, 0xFF00, e
->crsminl
);
2575 b43_phy_maskset(dev
, B43_NPHY_CRSMINPOWERU0
, 0xFF00, e
->crsminu
);
2576 b43_phy_write(dev
, B43_NPHY_C1_NBCLIPTHRES
, e
->nbclip
);
2577 b43_phy_write(dev
, B43_NPHY_C2_NBCLIPTHRES
, e
->nbclip
);
2578 b43_phy_maskset(dev
, B43_NPHY_C1_CLIPWBTHRES
,
2579 ~B43_NPHY_C1_CLIPWBTHRES_CLIP2
, e
->wlclip
);
2580 b43_phy_maskset(dev
, B43_NPHY_C2_CLIPWBTHRES
,
2581 ~B43_NPHY_C2_CLIPWBTHRES_CLIP2
, e
->wlclip
);
2582 b43_phy_write(dev
, B43_NPHY_CCK_SHIFTB_REF
, 0x809C);
2585 static void b43_nphy_gain_ctl_workarounds_rev1_2(struct b43_wldev
*dev
)
2587 struct b43_phy_n
*nphy
= dev
->phy
.n
;
2592 u8 rfseq_events
[3] = { 6, 8, 7 };
2593 u8 rfseq_delays
[3] = { 10, 30, 1 };
2595 /* Set Clip 2 detect */
2596 b43_phy_set(dev
, B43_NPHY_C1_CGAINI
, B43_NPHY_C1_CGAINI_CL2DETECT
);
2597 b43_phy_set(dev
, B43_NPHY_C2_CGAINI
, B43_NPHY_C2_CGAINI_CL2DETECT
);
2599 /* Set narrowband clip threshold */
2600 b43_phy_write(dev
, B43_NPHY_C1_NBCLIPTHRES
, 0x84);
2601 b43_phy_write(dev
, B43_NPHY_C2_NBCLIPTHRES
, 0x84);
2603 if (!b43_is_40mhz(dev
)) {
2604 /* Set dwell lengths */
2605 b43_phy_write(dev
, B43_NPHY_CLIP1_NBDWELL_LEN
, 0x002B);
2606 b43_phy_write(dev
, B43_NPHY_CLIP2_NBDWELL_LEN
, 0x002B);
2607 b43_phy_write(dev
, B43_NPHY_W1CLIP1_DWELL_LEN
, 0x0009);
2608 b43_phy_write(dev
, B43_NPHY_W1CLIP2_DWELL_LEN
, 0x0009);
2611 /* Set wideband clip 2 threshold */
2612 b43_phy_maskset(dev
, B43_NPHY_C1_CLIPWBTHRES
,
2613 ~B43_NPHY_C1_CLIPWBTHRES_CLIP2
, 21);
2614 b43_phy_maskset(dev
, B43_NPHY_C2_CLIPWBTHRES
,
2615 ~B43_NPHY_C2_CLIPWBTHRES_CLIP2
, 21);
2617 if (!b43_is_40mhz(dev
)) {
2618 b43_phy_maskset(dev
, B43_NPHY_C1_CGAINI
,
2619 ~B43_NPHY_C1_CGAINI_GAINBKOFF
, 0x1);
2620 b43_phy_maskset(dev
, B43_NPHY_C2_CGAINI
,
2621 ~B43_NPHY_C2_CGAINI_GAINBKOFF
, 0x1);
2622 b43_phy_maskset(dev
, B43_NPHY_C1_CCK_CGAINI
,
2623 ~B43_NPHY_C1_CCK_CGAINI_GAINBKOFF
, 0x1);
2624 b43_phy_maskset(dev
, B43_NPHY_C2_CCK_CGAINI
,
2625 ~B43_NPHY_C2_CCK_CGAINI_GAINBKOFF
, 0x1);
2628 b43_phy_write(dev
, B43_NPHY_CCK_SHIFTB_REF
, 0x809C);
2630 if (nphy
->gain_boost
) {
2631 if (b43_current_band(dev
->wl
) == IEEE80211_BAND_2GHZ
&&
2637 code
= b43_is_40mhz(dev
) ? 6 : 7;
2640 /* Set HPVGA2 index */
2641 b43_phy_maskset(dev
, B43_NPHY_C1_INITGAIN
, ~B43_NPHY_C1_INITGAIN_HPVGA2
,
2642 code
<< B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT
);
2643 b43_phy_maskset(dev
, B43_NPHY_C2_INITGAIN
, ~B43_NPHY_C2_INITGAIN_HPVGA2
,
2644 code
<< B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT
);
2646 b43_phy_write(dev
, B43_NPHY_TABLE_ADDR
, 0x1D06);
2647 /* specs say about 2 loops, but wl does 4 */
2648 for (i
= 0; i
< 4; i
++)
2649 b43_phy_write(dev
, B43_NPHY_TABLE_DATALO
, (code
<< 8 | 0x7C));
2651 b43_nphy_adjust_lna_gain_table(dev
);
2653 if (nphy
->elna_gain_config
) {
2654 b43_phy_write(dev
, B43_NPHY_TABLE_ADDR
, 0x0808);
2655 b43_phy_write(dev
, B43_NPHY_TABLE_DATALO
, 0x0);
2656 b43_phy_write(dev
, B43_NPHY_TABLE_DATALO
, 0x1);
2657 b43_phy_write(dev
, B43_NPHY_TABLE_DATALO
, 0x1);
2658 b43_phy_write(dev
, B43_NPHY_TABLE_DATALO
, 0x1);
2660 b43_phy_write(dev
, B43_NPHY_TABLE_ADDR
, 0x0C08);
2661 b43_phy_write(dev
, B43_NPHY_TABLE_DATALO
, 0x0);
2662 b43_phy_write(dev
, B43_NPHY_TABLE_DATALO
, 0x1);
2663 b43_phy_write(dev
, B43_NPHY_TABLE_DATALO
, 0x1);
2664 b43_phy_write(dev
, B43_NPHY_TABLE_DATALO
, 0x1);
2666 b43_phy_write(dev
, B43_NPHY_TABLE_ADDR
, 0x1D06);
2667 /* specs say about 2 loops, but wl does 4 */
2668 for (i
= 0; i
< 4; i
++)
2669 b43_phy_write(dev
, B43_NPHY_TABLE_DATALO
,
2670 (code
<< 8 | 0x74));
2673 if (dev
->phy
.rev
== 2) {
2674 for (i
= 0; i
< 4; i
++) {
2675 b43_phy_write(dev
, B43_NPHY_TABLE_ADDR
,
2676 (0x0400 * i
) + 0x0020);
2677 for (j
= 0; j
< 21; j
++) {
2678 tmp
= j
* (i
< 2 ? 3 : 1);
2680 B43_NPHY_TABLE_DATALO
, tmp
);
2685 b43_nphy_set_rf_sequence(dev
, 5, rfseq_events
, rfseq_delays
, 3);
2686 b43_phy_maskset(dev
, B43_NPHY_OVER_DGAIN1
,
2687 ~B43_NPHY_OVER_DGAIN_CCKDGECV
& 0xFFFF,
2688 0x5A << B43_NPHY_OVER_DGAIN_CCKDGECV_SHIFT
);
2690 if (b43_current_band(dev
->wl
) == IEEE80211_BAND_2GHZ
)
2691 b43_phy_maskset(dev
, B43_PHY_N(0xC5D), 0xFF80, 4);
2694 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/WorkaroundsGainCtrl */
2695 static void b43_nphy_gain_ctl_workarounds(struct b43_wldev
*dev
)
2697 if (dev
->phy
.rev
>= 19)
2698 b43_nphy_gain_ctl_workarounds_rev19(dev
);
2699 else if (dev
->phy
.rev
>= 7)
2700 b43_nphy_gain_ctl_workarounds_rev7(dev
);
2701 else if (dev
->phy
.rev
>= 3)
2702 b43_nphy_gain_ctl_workarounds_rev3(dev
);
2704 b43_nphy_gain_ctl_workarounds_rev1_2(dev
);
2707 static void b43_nphy_workarounds_rev7plus(struct b43_wldev
*dev
)
2709 struct ssb_sprom
*sprom
= dev
->dev
->bus_sprom
;
2710 struct b43_phy
*phy
= &dev
->phy
;
2713 u8 tx2rx_events
[7] = { 4, 3, 5, 2, 1, 8, 31, };
2714 u8 tx2rx_delays
[7] = { 8, 4, 4, 4, 4, 6, 1, };
2716 u8 rx2tx_events_ipa
[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0xF, 0x3,
2718 u8 rx2tx_delays_ipa
[9] = { 8, 6, 6, 4, 4, 16, 43, 1, 1 };
2720 static const u16 ntab7_15e_16e
[] = { 0, 0x10f, 0x10f };
2721 u8 ntab7_138_146
[] = { 0x11, 0x11 };
2722 u8 ntab7_133
[] = { 0x77, 0x11, 0x11 };
2724 u16 lpf_ofdm_20mhz
[2], lpf_ofdm_40mhz
[2], lpf_11b
[2];
2726 s16 bcap_val_11b
[2], bcap_val_11n_20
[2], bcap_val_11n_40
[2];
2728 s16 scap_val_11b
[2], scap_val_11n_20
[2], scap_val_11n_40
[2];
2729 bool rccal_ovrd
= false;
2731 u16 bias
, conv
, filt
;
2738 b43_phy_write(dev
, B43_NPHY_PHASETR_A0
, 0x0125);
2739 b43_phy_write(dev
, B43_NPHY_PHASETR_A1
, 0x01b3);
2740 b43_phy_write(dev
, B43_NPHY_PHASETR_A2
, 0x0105);
2741 b43_phy_write(dev
, B43_NPHY_PHASETR_B0
, 0x016e);
2742 b43_phy_write(dev
, B43_NPHY_PHASETR_B1
, 0x00cd);
2743 b43_phy_write(dev
, B43_NPHY_PHASETR_B2
, 0x0020);
2745 if (phy
->rev
== 7) {
2746 b43_phy_set(dev
, B43_NPHY_FINERX2_CGC
, 0x10);
2747 b43_phy_maskset(dev
, B43_NPHY_FREQGAIN0
, 0xFF80, 0x0020);
2748 b43_phy_maskset(dev
, B43_NPHY_FREQGAIN0
, 0x80FF, 0x2700);
2749 b43_phy_maskset(dev
, B43_NPHY_FREQGAIN1
, 0xFF80, 0x002E);
2750 b43_phy_maskset(dev
, B43_NPHY_FREQGAIN1
, 0x80FF, 0x3300);
2751 b43_phy_maskset(dev
, B43_NPHY_FREQGAIN2
, 0xFF80, 0x0037);
2752 b43_phy_maskset(dev
, B43_NPHY_FREQGAIN2
, 0x80FF, 0x3A00);
2753 b43_phy_maskset(dev
, B43_NPHY_FREQGAIN3
, 0xFF80, 0x003C);
2754 b43_phy_maskset(dev
, B43_NPHY_FREQGAIN3
, 0x80FF, 0x3E00);
2755 b43_phy_maskset(dev
, B43_NPHY_FREQGAIN4
, 0xFF80, 0x003E);
2756 b43_phy_maskset(dev
, B43_NPHY_FREQGAIN4
, 0x80FF, 0x3F00);
2757 b43_phy_maskset(dev
, B43_NPHY_FREQGAIN5
, 0xFF80, 0x0040);
2758 b43_phy_maskset(dev
, B43_NPHY_FREQGAIN5
, 0x80FF, 0x4000);
2759 b43_phy_maskset(dev
, B43_NPHY_FREQGAIN6
, 0xFF80, 0x0040);
2760 b43_phy_maskset(dev
, B43_NPHY_FREQGAIN6
, 0x80FF, 0x4000);
2761 b43_phy_maskset(dev
, B43_NPHY_FREQGAIN7
, 0xFF80, 0x0040);
2762 b43_phy_maskset(dev
, B43_NPHY_FREQGAIN7
, 0x80FF, 0x4000);
2765 if (phy
->rev
>= 16) {
2766 b43_phy_write(dev
, B43_NPHY_FORCEFRONT0
, 0x7ff);
2767 b43_phy_write(dev
, B43_NPHY_FORCEFRONT1
, 0x7ff);
2768 } else if (phy
->rev
<= 8) {
2769 b43_phy_write(dev
, B43_NPHY_FORCEFRONT0
, 0x1B0);
2770 b43_phy_write(dev
, B43_NPHY_FORCEFRONT1
, 0x1B0);
2774 b43_phy_maskset(dev
, B43_NPHY_TXTAILCNT
, ~0xFF, 0xa0);
2775 else if (phy
->rev
>= 8)
2776 b43_phy_maskset(dev
, B43_NPHY_TXTAILCNT
, ~0xFF, 0x72);
2778 b43_ntab_write(dev
, B43_NTAB16(8, 0x00), 2);
2779 b43_ntab_write(dev
, B43_NTAB16(8, 0x10), 2);
2780 tmp32
= b43_ntab_read(dev
, B43_NTAB32(30, 0));
2782 b43_ntab_write(dev
, B43_NTAB32(30, 0), tmp32
);
2783 b43_ntab_write_bulk(dev
, B43_NTAB16(7, 0x15d), 3, ntab7_15e_16e
);
2784 b43_ntab_write_bulk(dev
, B43_NTAB16(7, 0x16d), 3, ntab7_15e_16e
);
2786 b43_nphy_set_rf_sequence(dev
, 1, tx2rx_events
, tx2rx_delays
,
2787 ARRAY_SIZE(tx2rx_events
));
2788 if (b43_nphy_ipa(dev
))
2789 b43_nphy_set_rf_sequence(dev
, 0, rx2tx_events_ipa
,
2790 rx2tx_delays_ipa
, ARRAY_SIZE(rx2tx_events_ipa
));
2792 b43_phy_maskset(dev
, B43_NPHY_EPS_OVERRIDEI_0
, 0x3FFF, 0x4000);
2793 b43_phy_maskset(dev
, B43_NPHY_EPS_OVERRIDEI_1
, 0x3FFF, 0x4000);
2795 for (core
= 0; core
< 2; core
++) {
2796 lpf_ofdm_20mhz
[core
] = b43_nphy_read_lpf_ctl(dev
, 0x154 + core
* 0x10);
2797 lpf_ofdm_40mhz
[core
] = b43_nphy_read_lpf_ctl(dev
, 0x159 + core
* 0x10);
2798 lpf_11b
[core
] = b43_nphy_read_lpf_ctl(dev
, 0x152 + core
* 0x10);
2801 bcap_val
= b43_radio_read(dev
, R2057_RCCAL_BCAP_VAL
);
2802 scap_val
= b43_radio_read(dev
, R2057_RCCAL_SCAP_VAL
);
2804 if (b43_nphy_ipa(dev
)) {
2805 bool ghz2
= b43_current_band(dev
->wl
) == IEEE80211_BAND_2GHZ
;
2807 switch (phy
->radio_rev
) {
2809 /* Check radio version (to be 0) by PHY rev for now */
2810 if (phy
->rev
== 8 && b43_is_40mhz(dev
)) {
2811 for (core
= 0; core
< 2; core
++) {
2812 scap_val_11b
[core
] = scap_val
;
2813 bcap_val_11b
[core
] = bcap_val
;
2814 scap_val_11n_20
[core
] = scap_val
;
2815 bcap_val_11n_20
[core
] = bcap_val
;
2816 scap_val_11n_40
[core
] = 0xc;
2817 bcap_val_11n_40
[core
] = 0xc;
2822 if (phy
->rev
== 9) {
2823 /* TODO: Radio version 1 (e.g. BCM5357B0) */
2828 for (core
= 0; core
< 2; core
++) {
2829 scap_val_11b
[core
] = scap_val
;
2830 bcap_val_11b
[core
] = bcap_val
;
2831 lpf_ofdm_20mhz
[core
] = 4;
2833 if (b43_current_band(dev
->wl
) == IEEE80211_BAND_2GHZ
) {
2834 scap_val_11n_20
[core
] = 0xc;
2835 bcap_val_11n_20
[core
] = 0xc;
2836 scap_val_11n_40
[core
] = 0xa;
2837 bcap_val_11n_40
[core
] = 0xa;
2839 scap_val_11n_20
[core
] = 0x14;
2840 bcap_val_11n_20
[core
] = 0x14;
2841 scap_val_11n_40
[core
] = 0xf;
2842 bcap_val_11n_40
[core
] = 0xf;
2849 for (core
= 0; core
< 2; core
++) {
2850 bcap_val_11b
[core
] = bcap_val
;
2851 scap_val_11b
[core
] = scap_val
;
2855 bcap_val_11n_20
[core
] = bcap_val
+ 13;
2856 scap_val_11n_20
[core
] = scap_val
+ 15;
2858 bcap_val_11n_20
[core
] = bcap_val
+ 14;
2859 scap_val_11n_20
[core
] = scap_val
+ 15;
2861 lpf_ofdm_20mhz
[core
] = 4;
2864 bcap_val_11n_40
[core
] = bcap_val
- 7;
2865 scap_val_11n_40
[core
] = scap_val
- 5;
2867 bcap_val_11n_40
[core
] = bcap_val
+ 2;
2868 scap_val_11n_40
[core
] = scap_val
+ 4;
2870 lpf_ofdm_40mhz
[core
] = 4;
2876 for (core
= 0; core
< 2; core
++) {
2877 bcap_val_11b
[core
] = bcap_val
;
2878 scap_val_11b
[core
] = scap_val
;
2882 bcap_val_11n_20
[0] = bcap_val
+ 20;
2883 scap_val_11n_20
[0] = scap_val
+ 20;
2884 lpf_ofdm_20mhz
[0] = 3;
2886 bcap_val_11n_20
[1] = bcap_val
+ 16;
2887 scap_val_11n_20
[1] = scap_val
+ 16;
2888 lpf_ofdm_20mhz
[1] = 3;
2890 bcap_val_11n_40
[0] = bcap_val
+ 20;
2891 scap_val_11n_40
[0] = scap_val
+ 20;
2892 lpf_ofdm_40mhz
[0] = 4;
2894 bcap_val_11n_40
[1] = bcap_val
+ 10;
2895 scap_val_11n_40
[1] = scap_val
+ 10;
2896 lpf_ofdm_40mhz
[1] = 4;
2902 if (phy
->radio_rev
== 5) {
2903 for (core
= 0; core
< 2; core
++) {
2904 lpf_ofdm_20mhz
[core
] = 1;
2905 lpf_ofdm_40mhz
[core
] = 3;
2906 scap_val_11b
[core
] = scap_val
;
2907 bcap_val_11b
[core
] = bcap_val
;
2908 scap_val_11n_20
[core
] = 0x11;
2909 scap_val_11n_40
[core
] = 0x11;
2910 bcap_val_11n_20
[core
] = 0x13;
2911 bcap_val_11n_40
[core
] = 0x13;
2918 u16 rx2tx_lut_20_11b
[2], rx2tx_lut_20_11n
[2], rx2tx_lut_40_11n
[2];
2919 u8 rx2tx_lut_extra
= 1;
2921 for (core
= 0; core
< 2; core
++) {
2922 bcap_val_11b
[core
] = clamp_val(bcap_val_11b
[core
], 0, 0x1f);
2923 scap_val_11b
[core
] = clamp_val(scap_val_11b
[core
], 0, 0x1f);
2924 bcap_val_11n_20
[core
] = clamp_val(bcap_val_11n_20
[core
], 0, 0x1f);
2925 scap_val_11n_20
[core
] = clamp_val(scap_val_11n_20
[core
], 0, 0x1f);
2926 bcap_val_11n_40
[core
] = clamp_val(bcap_val_11n_40
[core
], 0, 0x1f);
2927 scap_val_11n_40
[core
] = clamp_val(scap_val_11n_40
[core
], 0, 0x1f);
2929 rx2tx_lut_20_11b
[core
] = (rx2tx_lut_extra
<< 13) |
2930 (bcap_val_11b
[core
] << 8) |
2931 (scap_val_11b
[core
] << 3) |
2933 rx2tx_lut_20_11n
[core
] = (rx2tx_lut_extra
<< 13) |
2934 (bcap_val_11n_20
[core
] << 8) |
2935 (scap_val_11n_20
[core
] << 3) |
2936 lpf_ofdm_20mhz
[core
];
2937 rx2tx_lut_40_11n
[core
] = (rx2tx_lut_extra
<< 13) |
2938 (bcap_val_11n_40
[core
] << 8) |
2939 (scap_val_11n_40
[core
] << 3) |
2940 lpf_ofdm_40mhz
[core
];
2943 for (core
= 0; core
< 2; core
++) {
2944 b43_ntab_write(dev
, B43_NTAB16(7, 0x152 + core
* 16),
2945 rx2tx_lut_20_11b
[core
]);
2946 b43_ntab_write(dev
, B43_NTAB16(7, 0x153 + core
* 16),
2947 rx2tx_lut_20_11n
[core
]);
2948 b43_ntab_write(dev
, B43_NTAB16(7, 0x154 + core
* 16),
2949 rx2tx_lut_20_11n
[core
]);
2950 b43_ntab_write(dev
, B43_NTAB16(7, 0x155 + core
* 16),
2951 rx2tx_lut_40_11n
[core
]);
2952 b43_ntab_write(dev
, B43_NTAB16(7, 0x156 + core
* 16),
2953 rx2tx_lut_40_11n
[core
]);
2954 b43_ntab_write(dev
, B43_NTAB16(7, 0x157 + core
* 16),
2955 rx2tx_lut_40_11n
[core
]);
2956 b43_ntab_write(dev
, B43_NTAB16(7, 0x158 + core
* 16),
2957 rx2tx_lut_40_11n
[core
]);
2958 b43_ntab_write(dev
, B43_NTAB16(7, 0x159 + core
* 16),
2959 rx2tx_lut_40_11n
[core
]);
2963 b43_phy_write(dev
, 0x32F, 0x3);
2965 if (phy
->radio_rev
== 4 || phy
->radio_rev
== 6)
2966 b43_nphy_rf_ctl_override_rev7(dev
, 4, 1, 3, false, 0);
2968 if (phy
->radio_rev
== 3 || phy
->radio_rev
== 4 || phy
->radio_rev
== 6) {
2969 if (sprom
->revision
&&
2970 sprom
->boardflags2_hi
& B43_BFH2_IPALVLSHIFT_3P3
) {
2971 b43_radio_write(dev
, 0x5, 0x05);
2972 b43_radio_write(dev
, 0x6, 0x30);
2973 b43_radio_write(dev
, 0x7, 0x00);
2974 b43_radio_set(dev
, 0x4f, 0x1);
2975 b43_radio_set(dev
, 0xd4, 0x1);
2984 if (b43_current_band(dev
->wl
) == IEEE80211_BAND_2GHZ
) {
2985 for (core
= 0; core
< 2; core
++) {
2987 b43_radio_write(dev
, 0x5F, bias
);
2988 b43_radio_write(dev
, 0x64, conv
);
2989 b43_radio_write(dev
, 0x66, filt
);
2991 b43_radio_write(dev
, 0xE8, bias
);
2992 b43_radio_write(dev
, 0xE9, conv
);
2993 b43_radio_write(dev
, 0xEB, filt
);
2999 if (b43_nphy_ipa(dev
)) {
3000 if (b43_current_band(dev
->wl
) == IEEE80211_BAND_2GHZ
) {
3001 if (phy
->radio_rev
== 3 || phy
->radio_rev
== 4 ||
3002 phy
->radio_rev
== 6) {
3003 for (core
= 0; core
< 2; core
++) {
3005 b43_radio_write(dev
, 0x51,
3008 b43_radio_write(dev
, 0xd6,
3012 switch (phy
->radio_rev
) {
3014 for (core
= 0; core
< 2; core
++) {
3016 b43_radio_write(dev
, 0x64,
3018 b43_radio_write(dev
, 0x5F,
3020 b43_radio_write(dev
, 0x66,
3022 b43_radio_write(dev
, 0x59,
3024 b43_radio_write(dev
, 0x80,
3027 b43_radio_write(dev
, 0x69,
3029 b43_radio_write(dev
, 0xE8,
3031 b43_radio_write(dev
, 0xEB,
3033 b43_radio_write(dev
, 0xDE,
3035 b43_radio_write(dev
, 0x105,
3042 if (!b43_is_40mhz(dev
)) {
3043 b43_radio_write(dev
, 0x5F, 0x14);
3044 b43_radio_write(dev
, 0xE8, 0x12);
3046 b43_radio_write(dev
, 0x5F, 0x16);
3047 b43_radio_write(dev
, 0xE8, 0x16);
3051 for (core
= 0; core
< 2; core
++) {
3052 int o
= core
? 0x85 : 0;
3054 b43_radio_write(dev
, o
+ R2057_IPA2G_CASCONV_CORE0
, 0x13);
3055 b43_radio_write(dev
, o
+ R2057_TXMIX2G_TUNE_BOOST_PU_CORE0
, 0x21);
3056 b43_radio_write(dev
, o
+ R2057_IPA2G_BIAS_FILTER_CORE0
, 0xff);
3057 b43_radio_write(dev
, o
+ R2057_PAD2G_IDACS_CORE0
, 0x88);
3058 b43_radio_write(dev
, o
+ R2057_PAD2G_TUNE_PUS_CORE0
, 0x23);
3059 b43_radio_write(dev
, o
+ R2057_IPA2G_IMAIN_CORE0
, 0x16);
3060 b43_radio_write(dev
, o
+ R2057_PAD_BIAS_FILTER_BWS_CORE0
, 0x3e);
3061 b43_radio_write(dev
, o
+ R2057_BACKUP1_CORE0
, 0x10);
3066 u16 freq
= phy
->chandef
->chan
->center_freq
;
3067 if ((freq
>= 5180 && freq
<= 5230) ||
3068 (freq
>= 5745 && freq
<= 5805)) {
3069 b43_radio_write(dev
, 0x7D, 0xFF);
3070 b43_radio_write(dev
, 0xFE, 0xFF);
3074 if (phy
->radio_rev
!= 5) {
3075 for (core
= 0; core
< 2; core
++) {
3077 b43_radio_write(dev
, 0x5c, 0x61);
3078 b43_radio_write(dev
, 0x51, 0x70);
3080 b43_radio_write(dev
, 0xe1, 0x61);
3081 b43_radio_write(dev
, 0xd6, 0x70);
3087 if (phy
->radio_rev
== 4) {
3088 b43_ntab_write(dev
, B43_NTAB16(8, 0x05), 0x20);
3089 b43_ntab_write(dev
, B43_NTAB16(8, 0x15), 0x20);
3090 for (core
= 0; core
< 2; core
++) {
3092 b43_radio_write(dev
, 0x1a1, 0x00);
3093 b43_radio_write(dev
, 0x1a2, 0x3f);
3094 b43_radio_write(dev
, 0x1a6, 0x3f);
3096 b43_radio_write(dev
, 0x1a7, 0x00);
3097 b43_radio_write(dev
, 0x1ab, 0x3f);
3098 b43_radio_write(dev
, 0x1ac, 0x3f);
3102 b43_phy_set(dev
, B43_NPHY_AFECTL_C1
, 0x4);
3103 b43_phy_set(dev
, B43_NPHY_AFECTL_OVER1
, 0x4);
3104 b43_phy_set(dev
, B43_NPHY_AFECTL_C2
, 0x4);
3105 b43_phy_set(dev
, B43_NPHY_AFECTL_OVER
, 0x4);
3107 b43_phy_mask(dev
, B43_NPHY_AFECTL_C1
, ~0x1);
3108 b43_phy_set(dev
, B43_NPHY_AFECTL_OVER1
, 0x1);
3109 b43_phy_mask(dev
, B43_NPHY_AFECTL_C2
, ~0x1);
3110 b43_phy_set(dev
, B43_NPHY_AFECTL_OVER
, 0x1);
3111 b43_ntab_write(dev
, B43_NTAB16(8, 0x05), 0);
3112 b43_ntab_write(dev
, B43_NTAB16(8, 0x15), 0);
3114 b43_phy_mask(dev
, B43_NPHY_AFECTL_C1
, ~0x4);
3115 b43_phy_mask(dev
, B43_NPHY_AFECTL_OVER1
, ~0x4);
3116 b43_phy_mask(dev
, B43_NPHY_AFECTL_C2
, ~0x4);
3117 b43_phy_mask(dev
, B43_NPHY_AFECTL_OVER
, ~0x4);
3120 b43_phy_write(dev
, B43_NPHY_ENDROP_TLEN
, 0x2);
3122 b43_ntab_write(dev
, B43_NTAB32(16, 0x100), 20);
3123 b43_ntab_write_bulk(dev
, B43_NTAB8(7, 0x138), 2, ntab7_138_146
);
3124 b43_ntab_write(dev
, B43_NTAB16(7, 0x141), 0x77);
3125 b43_ntab_write_bulk(dev
, B43_NTAB8(7, 0x133), 3, ntab7_133
);
3126 b43_ntab_write_bulk(dev
, B43_NTAB8(7, 0x146), 2, ntab7_138_146
);
3127 b43_ntab_write(dev
, B43_NTAB16(7, 0x123), 0x77);
3128 b43_ntab_write(dev
, B43_NTAB16(7, 0x12A), 0x77);
3130 b43_ntab_read_bulk(dev
, B43_NTAB32(16, 0x02), 1, noise_tbl
);
3131 noise_tbl
[1] = b43_is_40mhz(dev
) ? 0x14D : 0x18D;
3132 b43_ntab_write_bulk(dev
, B43_NTAB32(16, 0x02), 2, noise_tbl
);
3134 b43_ntab_read_bulk(dev
, B43_NTAB32(16, 0x7E), 1, noise_tbl
);
3135 noise_tbl
[1] = b43_is_40mhz(dev
) ? 0x14D : 0x18D;
3136 b43_ntab_write_bulk(dev
, B43_NTAB32(16, 0x7E), 2, noise_tbl
);
3138 b43_nphy_gain_ctl_workarounds(dev
);
3141 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x08), 4,
3142 aux_adc_vmid_rev7_core0);
3143 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x18), 4,
3144 aux_adc_vmid_rev7_core1);
3145 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x0C), 4,
3147 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x1C), 4,
3152 static void b43_nphy_workarounds_rev3plus(struct b43_wldev
*dev
)
3154 struct b43_phy_n
*nphy
= dev
->phy
.n
;
3155 struct ssb_sprom
*sprom
= dev
->dev
->bus_sprom
;
3158 u8 tx2rx_events
[7] = { 0x4, 0x3, 0x5, 0x2, 0x1, 0x8, 0x1F };
3159 u8 tx2rx_delays
[7] = { 8, 4, 4, 4, 4, 6, 1 };
3161 u8 rx2tx_events_ipa
[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0xF, 0x3,
3163 u8 rx2tx_delays_ipa
[9] = { 8, 6, 6, 4, 4, 16, 43, 1, 1 };
3164 u8 rx2tx_events
[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0x3, 0x4, 0x1F };
3165 u8 rx2tx_delays
[9] = { 8, 6, 6, 4, 4, 18, 42, 1, 1 };
3168 { 0xa2, 0xb4, 0xb4, 0x89, }, /* 0 */
3169 { 0xb4, 0xb4, 0xb4, 0x24, }, /* 1 */
3170 { 0xa2, 0xb4, 0xb4, 0x74, }, /* 2 */
3171 { 0xa2, 0xb4, 0xb4, 0x270, }, /* 3 */
3172 { 0xa2, 0xb4, 0xb4, 0x00, }, /* 4 and 5 */
3175 { 0x02, 0x02, 0x02, 0x00, }, /* 0 */
3176 { 0x02, 0x02, 0x02, 0x02, }, /* 1 */
3177 { 0x02, 0x02, 0x02, 0x04, }, /* 2 */
3178 { 0x02, 0x02, 0x02, 0x00, }, /* 3 */
3179 { 0x02, 0x02, 0x02, 0x00, }, /* 4 and 5 */
3187 b43_phy_write(dev
, B43_NPHY_FORCEFRONT0
, 0x1f8);
3188 b43_phy_write(dev
, B43_NPHY_FORCEFRONT1
, 0x1f8);
3190 tmp32
= b43_ntab_read(dev
, B43_NTAB32(30, 0));
3192 b43_ntab_write(dev
, B43_NTAB32(30, 0), tmp32
);
3194 b43_phy_write(dev
, B43_NPHY_PHASETR_A0
, 0x0125);
3195 b43_phy_write(dev
, B43_NPHY_PHASETR_A1
, 0x01B3);
3196 b43_phy_write(dev
, B43_NPHY_PHASETR_A2
, 0x0105);
3197 b43_phy_write(dev
, B43_NPHY_PHASETR_B0
, 0x016E);
3198 b43_phy_write(dev
, B43_NPHY_PHASETR_B1
, 0x00CD);
3199 b43_phy_write(dev
, B43_NPHY_PHASETR_B2
, 0x0020);
3201 b43_phy_write(dev
, B43_NPHY_REV3_C1_CLIP_LOGAIN_B
, 0x000C);
3202 b43_phy_write(dev
, B43_NPHY_REV3_C2_CLIP_LOGAIN_B
, 0x000C);
3205 b43_nphy_set_rf_sequence(dev
, 1, tx2rx_events
, tx2rx_delays
,
3206 ARRAY_SIZE(tx2rx_events
));
3209 if (b43_nphy_ipa(dev
))
3210 b43_nphy_set_rf_sequence(dev
, 0, rx2tx_events_ipa
,
3211 rx2tx_delays_ipa
, ARRAY_SIZE(rx2tx_events_ipa
));
3212 if (nphy
->hw_phyrxchain
!= 3 &&
3213 nphy
->hw_phyrxchain
!= nphy
->hw_phytxchain
) {
3214 if (b43_nphy_ipa(dev
)) {
3215 rx2tx_delays
[5] = 59;
3216 rx2tx_delays
[6] = 1;
3217 rx2tx_events
[7] = 0x1F;
3219 b43_nphy_set_rf_sequence(dev
, 0, rx2tx_events
, rx2tx_delays
,
3220 ARRAY_SIZE(rx2tx_events
));
3223 tmp16
= (b43_current_band(dev
->wl
) == IEEE80211_BAND_2GHZ
) ?
3225 b43_phy_write(dev
, B43_NPHY_ENDROP_TLEN
, tmp16
);
3227 b43_phy_maskset(dev
, B43_NPHY_SGILTRNOFFSET
, 0xF0FF, 0x0700);
3229 if (!b43_is_40mhz(dev
)) {
3230 b43_ntab_write(dev
, B43_NTAB32(16, 3), 0x18D);
3231 b43_ntab_write(dev
, B43_NTAB32(16, 127), 0x18D);
3233 b43_ntab_write(dev
, B43_NTAB32(16, 3), 0x14D);
3234 b43_ntab_write(dev
, B43_NTAB32(16, 127), 0x14D);
3237 b43_nphy_gain_ctl_workarounds(dev
);
3239 b43_ntab_write(dev
, B43_NTAB16(8, 0), 2);
3240 b43_ntab_write(dev
, B43_NTAB16(8, 16), 2);
3242 if (b43_current_band(dev
->wl
) == IEEE80211_BAND_2GHZ
)
3243 pdet_range
= sprom
->fem
.ghz2
.pdet_range
;
3245 pdet_range
= sprom
->fem
.ghz5
.pdet_range
;
3246 vmid
= vmids
[min_t(u16
, pdet_range
, 4)];
3247 gain
= gains
[min_t(u16
, pdet_range
, 4)];
3248 switch (pdet_range
) {
3250 if (!(dev
->phy
.rev
>= 4 &&
3251 b43_current_band(dev
->wl
) == IEEE80211_BAND_2GHZ
))
3256 b43_ntab_write_bulk(dev
, B43_NTAB16(8, 0x08), 4, vmid
);
3257 b43_ntab_write_bulk(dev
, B43_NTAB16(8, 0x18), 4, vmid
);
3258 b43_ntab_write_bulk(dev
, B43_NTAB16(8, 0x0c), 4, gain
);
3259 b43_ntab_write_bulk(dev
, B43_NTAB16(8, 0x1c), 4, gain
);
3262 if (dev
->phy
.rev
>= 6) {
3263 if (b43_current_band(dev
->wl
) == IEEE80211_BAND_2GHZ
)
3268 } else if (dev
->phy
.rev
== 5) {
3272 b43_ntab_write_bulk(dev
, B43_NTAB16(8, 0x08), 4, vmid
);
3273 b43_ntab_write_bulk(dev
, B43_NTAB16(8, 0x18), 4, vmid
);
3274 b43_ntab_write_bulk(dev
, B43_NTAB16(8, 0x0c), 4, gain
);
3275 b43_ntab_write_bulk(dev
, B43_NTAB16(8, 0x1c), 4, gain
);
3279 if (b43_current_band(dev
->wl
) != IEEE80211_BAND_2GHZ
) {
3280 if (pdet_range
== 4) {
3290 if (pdet_range
== 4) {
3300 b43_ntab_write_bulk(dev
, B43_NTAB16(8, 0x08), 4, vmid
);
3301 b43_ntab_write_bulk(dev
, B43_NTAB16(8, 0x0c), 4, gain
);
3303 b43_ntab_write_bulk(dev
, B43_NTAB16(8, 0x18), 4, vmid
);
3304 b43_ntab_write_bulk(dev
, B43_NTAB16(8, 0x1c), 4, gain
);
3308 b43_radio_write(dev
, B2056_RX0
| B2056_RX_MIXA_MAST_BIAS
, 0x00);
3309 b43_radio_write(dev
, B2056_RX1
| B2056_RX_MIXA_MAST_BIAS
, 0x00);
3310 b43_radio_write(dev
, B2056_RX0
| B2056_RX_MIXA_BIAS_MAIN
, 0x06);
3311 b43_radio_write(dev
, B2056_RX1
| B2056_RX_MIXA_BIAS_MAIN
, 0x06);
3312 b43_radio_write(dev
, B2056_RX0
| B2056_RX_MIXA_BIAS_AUX
, 0x07);
3313 b43_radio_write(dev
, B2056_RX1
| B2056_RX_MIXA_BIAS_AUX
, 0x07);
3314 b43_radio_write(dev
, B2056_RX0
| B2056_RX_MIXA_LOB_BIAS
, 0x88);
3315 b43_radio_write(dev
, B2056_RX1
| B2056_RX_MIXA_LOB_BIAS
, 0x88);
3316 b43_radio_write(dev
, B2056_RX0
| B2056_RX_MIXA_CMFB_IDAC
, 0x00);
3317 b43_radio_write(dev
, B2056_RX1
| B2056_RX_MIXA_CMFB_IDAC
, 0x00);
3318 b43_radio_write(dev
, B2056_RX0
| B2056_RX_MIXG_CMFB_IDAC
, 0x00);
3319 b43_radio_write(dev
, B2056_RX1
| B2056_RX_MIXG_CMFB_IDAC
, 0x00);
3321 /* N PHY WAR TX Chain Update with hw_phytxchain as argument */
3323 if ((sprom
->boardflags2_lo
& B43_BFL2_APLL_WAR
&&
3324 b43_current_band(dev
->wl
) == IEEE80211_BAND_5GHZ
) ||
3325 (sprom
->boardflags2_lo
& B43_BFL2_GPLL_WAR
&&
3326 b43_current_band(dev
->wl
) == IEEE80211_BAND_2GHZ
))
3330 b43_ntab_write(dev
, B43_NTAB32(30, 1), tmp32
);
3331 b43_ntab_write(dev
, B43_NTAB32(30, 2), tmp32
);
3332 b43_ntab_write(dev
, B43_NTAB32(30, 3), tmp32
);
3334 if (dev
->phy
.rev
== 4 &&
3335 b43_current_band(dev
->wl
) == IEEE80211_BAND_5GHZ
) {
3336 b43_radio_write(dev
, B2056_TX0
| B2056_TX_GMBB_IDAC
,
3338 b43_radio_write(dev
, B2056_TX1
| B2056_TX_GMBB_IDAC
,
3342 /* Dropped probably-always-true condition */
3343 b43_phy_write(dev
, B43_NPHY_ED_CRS40ASSERTTHRESH0
, 0x03eb);
3344 b43_phy_write(dev
, B43_NPHY_ED_CRS40ASSERTTHRESH1
, 0x03eb);
3345 b43_phy_write(dev
, B43_NPHY_ED_CRS40DEASSERTTHRESH0
, 0x0341);
3346 b43_phy_write(dev
, B43_NPHY_ED_CRS40DEASSERTTHRESH1
, 0x0341);
3347 b43_phy_write(dev
, B43_NPHY_ED_CRS20LASSERTTHRESH0
, 0x042b);
3348 b43_phy_write(dev
, B43_NPHY_ED_CRS20LASSERTTHRESH1
, 0x042b);
3349 b43_phy_write(dev
, B43_NPHY_ED_CRS20LDEASSERTTHRESH0
, 0x0381);
3350 b43_phy_write(dev
, B43_NPHY_ED_CRS20LDEASSERTTHRESH1
, 0x0381);
3351 b43_phy_write(dev
, B43_NPHY_ED_CRS20UASSERTTHRESH0
, 0x042b);
3352 b43_phy_write(dev
, B43_NPHY_ED_CRS20UASSERTTHRESH1
, 0x042b);
3353 b43_phy_write(dev
, B43_NPHY_ED_CRS20UDEASSERTTHRESH0
, 0x0381);
3354 b43_phy_write(dev
, B43_NPHY_ED_CRS20UDEASSERTTHRESH1
, 0x0381);
3356 if (dev
->phy
.rev
>= 6 && sprom
->boardflags2_lo
& B43_BFL2_SINGLEANT_CCK
)
3357 ; /* TODO: 0x0080000000000000 HF */
3360 static void b43_nphy_workarounds_rev1_2(struct b43_wldev
*dev
)
3362 struct ssb_sprom
*sprom
= dev
->dev
->bus_sprom
;
3363 struct b43_phy
*phy
= &dev
->phy
;
3364 struct b43_phy_n
*nphy
= phy
->n
;
3366 u8 events1
[7] = { 0x0, 0x1, 0x2, 0x8, 0x4, 0x5, 0x3 };
3367 u8 delays1
[7] = { 0x8, 0x6, 0x6, 0x2, 0x4, 0x3C, 0x1 };
3369 u8 events2
[7] = { 0x0, 0x3, 0x5, 0x4, 0x2, 0x1, 0x8 };
3370 u8 delays2
[7] = { 0x8, 0x6, 0x2, 0x4, 0x4, 0x6, 0x1 };
3372 if (sprom
->boardflags2_lo
& B43_BFL2_SKWRKFEM_BRD
||
3373 dev
->dev
->board_type
== BCMA_BOARD_TYPE_BCM943224M93
) {
3378 if (b43_current_band(dev
->wl
) == IEEE80211_BAND_5GHZ
&&
3379 nphy
->band5g_pwrgain
) {
3380 b43_radio_mask(dev
, B2055_C1_TX_RF_SPARE
, ~0x8);
3381 b43_radio_mask(dev
, B2055_C2_TX_RF_SPARE
, ~0x8);
3383 b43_radio_set(dev
, B2055_C1_TX_RF_SPARE
, 0x8);
3384 b43_radio_set(dev
, B2055_C2_TX_RF_SPARE
, 0x8);
3387 b43_ntab_write(dev
, B43_NTAB16(8, 0x00), 0x000A);
3388 b43_ntab_write(dev
, B43_NTAB16(8, 0x10), 0x000A);
3389 if (dev
->phy
.rev
< 3) {
3390 b43_ntab_write(dev
, B43_NTAB16(8, 0x02), 0xCDAA);
3391 b43_ntab_write(dev
, B43_NTAB16(8, 0x12), 0xCDAA);
3394 if (dev
->phy
.rev
< 2) {
3395 b43_ntab_write(dev
, B43_NTAB16(8, 0x08), 0x0000);
3396 b43_ntab_write(dev
, B43_NTAB16(8, 0x18), 0x0000);
3397 b43_ntab_write(dev
, B43_NTAB16(8, 0x07), 0x7AAB);
3398 b43_ntab_write(dev
, B43_NTAB16(8, 0x17), 0x7AAB);
3399 b43_ntab_write(dev
, B43_NTAB16(8, 0x06), 0x0800);
3400 b43_ntab_write(dev
, B43_NTAB16(8, 0x16), 0x0800);
3403 b43_phy_write(dev
, B43_NPHY_RFCTL_LUT_TRSW_LO1
, 0x2D8);
3404 b43_phy_write(dev
, B43_NPHY_RFCTL_LUT_TRSW_UP1
, 0x301);
3405 b43_phy_write(dev
, B43_NPHY_RFCTL_LUT_TRSW_LO2
, 0x2D8);
3406 b43_phy_write(dev
, B43_NPHY_RFCTL_LUT_TRSW_UP2
, 0x301);
3408 b43_nphy_set_rf_sequence(dev
, 0, events1
, delays1
, 7);
3409 b43_nphy_set_rf_sequence(dev
, 1, events2
, delays2
, 7);
3411 b43_nphy_gain_ctl_workarounds(dev
);
3413 if (dev
->phy
.rev
< 2) {
3414 if (b43_phy_read(dev
, B43_NPHY_RXCTL
) & 0x2)
3415 b43_hf_write(dev
, b43_hf_read(dev
) |
3417 } else if (dev
->phy
.rev
== 2) {
3418 b43_phy_write(dev
, B43_NPHY_CRSCHECK2
, 0);
3419 b43_phy_write(dev
, B43_NPHY_CRSCHECK3
, 0);
3422 if (dev
->phy
.rev
< 2)
3423 b43_phy_mask(dev
, B43_NPHY_SCRAM_SIGCTL
,
3424 ~B43_NPHY_SCRAM_SIGCTL_SCM
);
3426 /* Set phase track alpha and beta */
3427 b43_phy_write(dev
, B43_NPHY_PHASETR_A0
, 0x125);
3428 b43_phy_write(dev
, B43_NPHY_PHASETR_A1
, 0x1B3);
3429 b43_phy_write(dev
, B43_NPHY_PHASETR_A2
, 0x105);
3430 b43_phy_write(dev
, B43_NPHY_PHASETR_B0
, 0x16E);
3431 b43_phy_write(dev
, B43_NPHY_PHASETR_B1
, 0xCD);
3432 b43_phy_write(dev
, B43_NPHY_PHASETR_B2
, 0x20);
3434 if (dev
->phy
.rev
< 3) {
3435 b43_phy_mask(dev
, B43_NPHY_PIL_DW1
,
3436 ~B43_NPHY_PIL_DW_64QAM
& 0xFFFF);
3437 b43_phy_write(dev
, B43_NPHY_TXF_20CO_S2B1
, 0xB5);
3438 b43_phy_write(dev
, B43_NPHY_TXF_20CO_S2B2
, 0xA4);
3439 b43_phy_write(dev
, B43_NPHY_TXF_20CO_S2B3
, 0x00);
3442 if (dev
->phy
.rev
== 2)
3443 b43_phy_set(dev
, B43_NPHY_FINERX2_CGC
,
3444 B43_NPHY_FINERX2_CGC_DECGC
);
3447 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Workarounds */
3448 static void b43_nphy_workarounds(struct b43_wldev
*dev
)
3450 struct b43_phy
*phy
= &dev
->phy
;
3451 struct b43_phy_n
*nphy
= phy
->n
;
3453 if (b43_current_band(dev
->wl
) == IEEE80211_BAND_5GHZ
)
3454 b43_nphy_classifier(dev
, 1, 0);
3456 b43_nphy_classifier(dev
, 1, 1);
3458 if (nphy
->hang_avoid
)
3459 b43_nphy_stay_in_carrier_search(dev
, 1);
3461 b43_phy_set(dev
, B43_NPHY_IQFLIP
,
3462 B43_NPHY_IQFLIP_ADC1
| B43_NPHY_IQFLIP_ADC2
);
3465 if (dev
->phy
.rev
>= 7)
3466 b43_nphy_workarounds_rev7plus(dev
);
3467 else if (dev
->phy
.rev
>= 3)
3468 b43_nphy_workarounds_rev3plus(dev
);
3470 b43_nphy_workarounds_rev1_2(dev
);
3472 if (nphy
->hang_avoid
)
3473 b43_nphy_stay_in_carrier_search(dev
, 0);
3476 /**************************************************
3478 **************************************************/
3481 * Transmits a known value for LO calibration
3482 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TXTone
3484 static int b43_nphy_tx_tone(struct b43_wldev
*dev
, u32 freq
, u16 max_val
,
3485 bool iqmode
, bool dac_test
, bool modify_bbmult
)
3487 u16 samp
= b43_nphy_gen_load_samples(dev
, freq
, max_val
, dac_test
);
3490 b43_nphy_run_samples(dev
, samp
, 0xFFFF, 0, iqmode
, dac_test
,
3495 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Chains */
3496 static void b43_nphy_update_txrx_chain(struct b43_wldev
*dev
)
3498 struct b43_phy_n
*nphy
= dev
->phy
.n
;
3500 bool override
= false;
3503 if (nphy
->txrx_chain
== 0) {
3506 } else if (nphy
->txrx_chain
== 1) {
3511 b43_phy_maskset(dev
, B43_NPHY_RFSEQCA
,
3512 ~(B43_NPHY_RFSEQCA_TXEN
| B43_NPHY_RFSEQCA_RXEN
),
3516 b43_phy_set(dev
, B43_NPHY_RFSEQMODE
,
3517 B43_NPHY_RFSEQMODE_CAOVER
);
3519 b43_phy_mask(dev
, B43_NPHY_RFSEQMODE
,
3520 ~B43_NPHY_RFSEQMODE_CAOVER
);
3523 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/stop-playback */
3524 static void b43_nphy_stop_playback(struct b43_wldev
*dev
)
3526 struct b43_phy
*phy
= &dev
->phy
;
3527 struct b43_phy_n
*nphy
= dev
->phy
.n
;
3530 if (nphy
->hang_avoid
)
3531 b43_nphy_stay_in_carrier_search(dev
, 1);
3533 tmp
= b43_phy_read(dev
, B43_NPHY_SAMP_STAT
);
3535 b43_phy_set(dev
, B43_NPHY_SAMP_CMD
, B43_NPHY_SAMP_CMD_STOP
);
3537 b43_phy_mask(dev
, B43_NPHY_IQLOCAL_CMDGCTL
, 0x7FFF);
3539 b43_phy_mask(dev
, B43_NPHY_SAMP_CMD
, ~0x0004);
3541 if (nphy
->bb_mult_save
& 0x80000000) {
3542 tmp
= nphy
->bb_mult_save
& 0xFFFF;
3543 b43_ntab_write(dev
, B43_NTAB16(15, 87), tmp
);
3544 nphy
->bb_mult_save
= 0;
3547 if (phy
->rev
>= 7 && nphy
->lpf_bw_overrode_for_sample_play
) {
3549 b43_nphy_rf_ctl_override_rev19(dev
, 0x80, 0, 0, true,
3552 b43_nphy_rf_ctl_override_rev7(dev
, 0x80, 0, 0, true, 1);
3553 nphy
->lpf_bw_overrode_for_sample_play
= false;
3556 if (nphy
->hang_avoid
)
3557 b43_nphy_stay_in_carrier_search(dev
, 0);
3560 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IqCalGainParams */
3561 static void b43_nphy_iq_cal_gain_params(struct b43_wldev
*dev
, u16 core
,
3562 struct nphy_txgains target
,
3563 struct nphy_iqcal_params
*params
)
3565 struct b43_phy
*phy
= &dev
->phy
;
3569 if (dev
->phy
.rev
>= 3) {
3570 params
->tx_lpf
= target
.tx_lpf
[core
]; /* Rev 7+ */
3571 params
->txgm
= target
.txgm
[core
];
3572 params
->pga
= target
.pga
[core
];
3573 params
->pad
= target
.pad
[core
];
3574 params
->ipa
= target
.ipa
[core
];
3575 if (phy
->rev
>= 19) {
3577 } else if (phy
->rev
>= 7) {
3578 params
->cal_gain
= (params
->txgm
<< 12) | (params
->pga
<< 8) | (params
->pad
<< 3) | (params
->ipa
) | (params
->tx_lpf
<< 15);
3580 params
->cal_gain
= (params
->txgm
<< 12) | (params
->pga
<< 8) | (params
->pad
<< 4) | (params
->ipa
);
3582 for (j
= 0; j
< 5; j
++)
3583 params
->ncorr
[j
] = 0x79;
3585 gain
= (target
.pad
[core
]) | (target
.pga
[core
] << 4) |
3586 (target
.txgm
[core
] << 8);
3588 indx
= (b43_current_band(dev
->wl
) == IEEE80211_BAND_5GHZ
) ?
3590 for (i
= 0; i
< 9; i
++)
3591 if (tbl_iqcal_gainparams
[indx
][i
][0] == gain
)
3595 params
->txgm
= tbl_iqcal_gainparams
[indx
][i
][1];
3596 params
->pga
= tbl_iqcal_gainparams
[indx
][i
][2];
3597 params
->pad
= tbl_iqcal_gainparams
[indx
][i
][3];
3598 params
->cal_gain
= (params
->txgm
<< 7) | (params
->pga
<< 4) |
3600 for (j
= 0; j
< 4; j
++)
3601 params
->ncorr
[j
] = tbl_iqcal_gainparams
[indx
][i
][4 + j
];
3605 /**************************************************
3607 **************************************************/
3609 static void b43_nphy_op_adjust_txpower(struct b43_wldev
*dev
)
3613 static enum b43_txpwr_result
b43_nphy_op_recalc_txpower(struct b43_wldev
*dev
,
3616 return B43_TXPWR_RES_DONE
;
3619 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlEnable */
3620 static void b43_nphy_tx_power_ctrl(struct b43_wldev
*dev
, bool enable
)
3622 struct b43_phy
*phy
= &dev
->phy
;
3623 struct b43_phy_n
*nphy
= dev
->phy
.n
;
3625 u16 bmask
, val
, tmp
;
3626 enum ieee80211_band band
= b43_current_band(dev
->wl
);
3628 if (nphy
->hang_avoid
)
3629 b43_nphy_stay_in_carrier_search(dev
, 1);
3631 nphy
->txpwrctrl
= enable
;
3633 if (dev
->phy
.rev
>= 3 &&
3634 (b43_phy_read(dev
, B43_NPHY_TXPCTL_CMD
) &
3635 (B43_NPHY_TXPCTL_CMD_COEFF
|
3636 B43_NPHY_TXPCTL_CMD_HWPCTLEN
|
3637 B43_NPHY_TXPCTL_CMD_PCTLEN
))) {
3638 /* We disable enabled TX pwr ctl, save it's state */
3639 nphy
->tx_pwr_idx
[0] = b43_phy_read(dev
,
3640 B43_NPHY_C1_TXPCTL_STAT
) & 0x7f;
3641 nphy
->tx_pwr_idx
[1] = b43_phy_read(dev
,
3642 B43_NPHY_C2_TXPCTL_STAT
) & 0x7f;
3645 b43_phy_write(dev
, B43_NPHY_TABLE_ADDR
, 0x6840);
3646 for (i
= 0; i
< 84; i
++)
3647 b43_phy_write(dev
, B43_NPHY_TABLE_DATALO
, 0);
3649 b43_phy_write(dev
, B43_NPHY_TABLE_ADDR
, 0x6C40);
3650 for (i
= 0; i
< 84; i
++)
3651 b43_phy_write(dev
, B43_NPHY_TABLE_DATALO
, 0);
3653 tmp
= B43_NPHY_TXPCTL_CMD_COEFF
| B43_NPHY_TXPCTL_CMD_HWPCTLEN
;
3654 if (dev
->phy
.rev
>= 3)
3655 tmp
|= B43_NPHY_TXPCTL_CMD_PCTLEN
;
3656 b43_phy_mask(dev
, B43_NPHY_TXPCTL_CMD
, ~tmp
);
3658 if (dev
->phy
.rev
>= 3) {
3659 b43_phy_set(dev
, B43_NPHY_AFECTL_OVER1
, 0x0100);
3660 b43_phy_set(dev
, B43_NPHY_AFECTL_OVER
, 0x0100);
3662 b43_phy_set(dev
, B43_NPHY_AFECTL_OVER
, 0x4000);
3665 if (dev
->phy
.rev
== 2)
3666 b43_phy_maskset(dev
, B43_NPHY_BPHY_CTL3
,
3667 ~B43_NPHY_BPHY_CTL3_SCALE
, 0x53);
3668 else if (dev
->phy
.rev
< 2)
3669 b43_phy_maskset(dev
, B43_NPHY_BPHY_CTL3
,
3670 ~B43_NPHY_BPHY_CTL3_SCALE
, 0x5A);
3672 if (dev
->phy
.rev
< 2 && b43_is_40mhz(dev
))
3673 b43_hf_write(dev
, b43_hf_read(dev
) | B43_HF_TSSIRPSMW
);
3675 b43_ntab_write_bulk(dev
, B43_NTAB16(26, 64), 84,
3677 b43_ntab_write_bulk(dev
, B43_NTAB16(27, 64), 84,
3680 bmask
= B43_NPHY_TXPCTL_CMD_COEFF
|
3681 B43_NPHY_TXPCTL_CMD_HWPCTLEN
;
3682 /* wl does useless check for "enable" param here */
3683 val
= B43_NPHY_TXPCTL_CMD_COEFF
| B43_NPHY_TXPCTL_CMD_HWPCTLEN
;
3684 if (dev
->phy
.rev
>= 3) {
3685 bmask
|= B43_NPHY_TXPCTL_CMD_PCTLEN
;
3687 val
|= B43_NPHY_TXPCTL_CMD_PCTLEN
;
3689 b43_phy_maskset(dev
, B43_NPHY_TXPCTL_CMD
, ~(bmask
), val
);
3691 if (band
== IEEE80211_BAND_5GHZ
) {
3692 if (phy
->rev
>= 19) {
3694 } else if (phy
->rev
>= 7) {
3695 b43_phy_maskset(dev
, B43_NPHY_TXPCTL_CMD
,
3696 ~B43_NPHY_TXPCTL_CMD_INIT
,
3698 b43_phy_maskset(dev
, B43_NPHY_TXPCTL_INIT
,
3699 ~B43_NPHY_TXPCTL_INIT_PIDXI1
,
3702 b43_phy_maskset(dev
, B43_NPHY_TXPCTL_CMD
,
3703 ~B43_NPHY_TXPCTL_CMD_INIT
,
3706 b43_phy_maskset(dev
,
3707 B43_NPHY_TXPCTL_INIT
,
3708 ~B43_NPHY_TXPCTL_INIT_PIDXI1
,
3713 if (dev
->phy
.rev
>= 3) {
3714 if (nphy
->tx_pwr_idx
[0] != 128 &&
3715 nphy
->tx_pwr_idx
[1] != 128) {
3716 /* Recover TX pwr ctl state */
3717 b43_phy_maskset(dev
, B43_NPHY_TXPCTL_CMD
,
3718 ~B43_NPHY_TXPCTL_CMD_INIT
,
3719 nphy
->tx_pwr_idx
[0]);
3720 if (dev
->phy
.rev
> 1)
3721 b43_phy_maskset(dev
,
3722 B43_NPHY_TXPCTL_INIT
,
3723 ~0xff, nphy
->tx_pwr_idx
[1]);
3727 if (phy
->rev
>= 7) {
3731 if (dev
->phy
.rev
>= 3) {
3732 b43_phy_mask(dev
, B43_NPHY_AFECTL_OVER1
, ~0x100);
3733 b43_phy_mask(dev
, B43_NPHY_AFECTL_OVER
, ~0x100);
3735 b43_phy_mask(dev
, B43_NPHY_AFECTL_OVER
, ~0x4000);
3738 if (dev
->phy
.rev
== 2)
3739 b43_phy_maskset(dev
, B43_NPHY_BPHY_CTL3
, ~0xFF, 0x3b);
3740 else if (dev
->phy
.rev
< 2)
3741 b43_phy_maskset(dev
, B43_NPHY_BPHY_CTL3
, ~0xFF, 0x40);
3743 if (dev
->phy
.rev
< 2 && b43_is_40mhz(dev
))
3744 b43_hf_write(dev
, b43_hf_read(dev
) & ~B43_HF_TSSIRPSMW
);
3746 if (b43_nphy_ipa(dev
)) {
3747 b43_phy_mask(dev
, B43_NPHY_PAPD_EN0
, ~0x4);
3748 b43_phy_mask(dev
, B43_NPHY_PAPD_EN1
, ~0x4);
3752 if (nphy
->hang_avoid
)
3753 b43_nphy_stay_in_carrier_search(dev
, 0);
3756 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrFix */
3757 static void b43_nphy_tx_power_fix(struct b43_wldev
*dev
)
3759 struct b43_phy
*phy
= &dev
->phy
;
3760 struct b43_phy_n
*nphy
= dev
->phy
.n
;
3761 struct ssb_sprom
*sprom
= dev
->dev
->bus_sprom
;
3763 u8 txpi
[2], bbmult
, i
;
3764 u16 tmp
, radio_gain
, dac_gain
;
3765 u16 freq
= phy
->chandef
->chan
->center_freq
;
3767 /* u32 gaintbl; rev3+ */
3769 if (nphy
->hang_avoid
)
3770 b43_nphy_stay_in_carrier_search(dev
, 1);
3773 if (dev
->phy
.rev
>= 7) {
3774 txpi
[0] = txpi
[1] = 30;
3775 } else if (dev
->phy
.rev
>= 3) {
3778 } else if (sprom
->revision
< 4) {
3782 if (b43_current_band(dev
->wl
) == IEEE80211_BAND_2GHZ
) {
3783 txpi
[0] = sprom
->txpid2g
[0];
3784 txpi
[1] = sprom
->txpid2g
[1];
3785 } else if (freq
>= 4900 && freq
< 5100) {
3786 txpi
[0] = sprom
->txpid5gl
[0];
3787 txpi
[1] = sprom
->txpid5gl
[1];
3788 } else if (freq
>= 5100 && freq
< 5500) {
3789 txpi
[0] = sprom
->txpid5g
[0];
3790 txpi
[1] = sprom
->txpid5g
[1];
3791 } else if (freq
>= 5500) {
3792 txpi
[0] = sprom
->txpid5gh
[0];
3793 txpi
[1] = sprom
->txpid5gh
[1];
3799 if (dev
->phy
.rev
< 7 &&
3800 (txpi
[0] < 40 || txpi
[0] > 100 || txpi
[1] < 40 || txpi
[1] > 100))
3801 txpi
[0] = txpi
[1] = 91;
3804 for (i = 0; i < 2; i++) {
3805 nphy->txpwrindex[i].index_internal = txpi[i];
3806 nphy->txpwrindex[i].index_internal_save = txpi[i];
3810 for (i
= 0; i
< 2; i
++) {
3811 const u32
*table
= b43_nphy_get_tx_gain_table(dev
);
3815 txgain
= *(table
+ txpi
[i
]);
3817 if (dev
->phy
.rev
>= 3)
3818 radio_gain
= (txgain
>> 16) & 0x1FFFF;
3820 radio_gain
= (txgain
>> 16) & 0x1FFF;
3822 if (dev
->phy
.rev
>= 7)
3823 dac_gain
= (txgain
>> 8) & 0x7;
3825 dac_gain
= (txgain
>> 8) & 0x3F;
3826 bbmult
= txgain
& 0xFF;
3828 if (dev
->phy
.rev
>= 3) {
3830 b43_phy_set(dev
, B43_NPHY_AFECTL_OVER1
, 0x0100);
3832 b43_phy_set(dev
, B43_NPHY_AFECTL_OVER
, 0x0100);
3834 b43_phy_set(dev
, B43_NPHY_AFECTL_OVER
, 0x4000);
3838 b43_phy_write(dev
, B43_NPHY_AFECTL_DACGAIN1
, dac_gain
);
3840 b43_phy_write(dev
, B43_NPHY_AFECTL_DACGAIN2
, dac_gain
);
3842 b43_ntab_write(dev
, B43_NTAB16(0x7, 0x110 + i
), radio_gain
);
3844 tmp
= b43_ntab_read(dev
, B43_NTAB16(0xF, 0x57));
3846 tmp
= (tmp
& 0x00FF) | (bbmult
<< 8);
3848 tmp
= (tmp
& 0xFF00) | bbmult
;
3849 b43_ntab_write(dev
, B43_NTAB16(0xF, 0x57), tmp
);
3851 if (b43_nphy_ipa(dev
)) {
3853 u16 reg
= (i
== 0) ?
3854 B43_NPHY_PAPD_EN0
: B43_NPHY_PAPD_EN1
;
3855 tmp32
= b43_ntab_read(dev
, B43_NTAB32(26 + i
,
3857 b43_phy_maskset(dev
, reg
, 0xE00F, (u32
) tmp32
<< 4);
3858 b43_phy_set(dev
, reg
, 0x4);
3862 b43_phy_mask(dev
, B43_NPHY_BPHY_CTL2
, ~B43_NPHY_BPHY_CTL2_LUT
);
3864 if (nphy
->hang_avoid
)
3865 b43_nphy_stay_in_carrier_search(dev
, 0);
3868 static void b43_nphy_ipa_internal_tssi_setup(struct b43_wldev
*dev
)
3870 struct b43_phy
*phy
= &dev
->phy
;
3873 u16 r
; /* routing */
3875 if (phy
->rev
>= 19) {
3877 } else if (phy
->rev
>= 7) {
3878 for (core
= 0; core
< 2; core
++) {
3879 r
= core
? 0x190 : 0x170;
3880 if (b43_current_band(dev
->wl
) == IEEE80211_BAND_2GHZ
) {
3881 b43_radio_write(dev
, r
+ 0x5, 0x5);
3882 b43_radio_write(dev
, r
+ 0x9, 0xE);
3884 b43_radio_write(dev
, r
+ 0xA, 0);
3886 b43_radio_write(dev
, r
+ 0xB, 1);
3888 b43_radio_write(dev
, r
+ 0xB, 0x31);
3890 b43_radio_write(dev
, r
+ 0x5, 0x9);
3891 b43_radio_write(dev
, r
+ 0x9, 0xC);
3892 b43_radio_write(dev
, r
+ 0xB, 0x0);
3894 b43_radio_write(dev
, r
+ 0xA, 1);
3896 b43_radio_write(dev
, r
+ 0xA, 0x31);
3898 b43_radio_write(dev
, r
+ 0x6, 0);
3899 b43_radio_write(dev
, r
+ 0x7, 0);
3900 b43_radio_write(dev
, r
+ 0x8, 3);
3901 b43_radio_write(dev
, r
+ 0xC, 0);
3904 if (b43_current_band(dev
->wl
) == IEEE80211_BAND_2GHZ
)
3905 b43_radio_write(dev
, B2056_SYN_RESERVED_ADDR31
, 0x128);
3907 b43_radio_write(dev
, B2056_SYN_RESERVED_ADDR31
, 0x80);
3908 b43_radio_write(dev
, B2056_SYN_RESERVED_ADDR30
, 0);
3909 b43_radio_write(dev
, B2056_SYN_GPIO_MASTER1
, 0x29);
3911 for (core
= 0; core
< 2; core
++) {
3912 r
= core
? B2056_TX1
: B2056_TX0
;
3914 b43_radio_write(dev
, r
| B2056_TX_IQCAL_VCM_HG
, 0);
3915 b43_radio_write(dev
, r
| B2056_TX_IQCAL_IDAC
, 0);
3916 b43_radio_write(dev
, r
| B2056_TX_TSSI_VCM
, 3);
3917 b43_radio_write(dev
, r
| B2056_TX_TX_AMP_DET
, 0);
3918 b43_radio_write(dev
, r
| B2056_TX_TSSI_MISC1
, 8);
3919 b43_radio_write(dev
, r
| B2056_TX_TSSI_MISC2
, 0);
3920 b43_radio_write(dev
, r
| B2056_TX_TSSI_MISC3
, 0);
3921 if (b43_current_band(dev
->wl
) == IEEE80211_BAND_2GHZ
) {
3922 b43_radio_write(dev
, r
| B2056_TX_TX_SSI_MASTER
,
3925 b43_radio_write(dev
, r
| B2056_TX_TSSIA
,
3928 b43_radio_write(dev
, r
| B2056_TX_TSSIG
,
3931 b43_radio_write(dev
, r
| B2056_TX_TSSIG
,
3933 b43_radio_write(dev
, r
| B2056_TX_TX_SSI_MUX
,
3936 b43_radio_write(dev
, r
| B2056_TX_TX_SSI_MASTER
,
3938 b43_radio_write(dev
, r
| B2056_TX_TSSIA
, 0x31);
3939 b43_radio_write(dev
, r
| B2056_TX_TSSIG
, 0x0);
3940 b43_radio_write(dev
, r
| B2056_TX_TX_SSI_MUX
,
3948 * Stop radio and transmit known signal. Then check received signal strength to
3949 * get TSSI (Transmit Signal Strength Indicator).
3950 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlIdleTssi
3952 static void b43_nphy_tx_power_ctl_idle_tssi(struct b43_wldev
*dev
)
3954 struct b43_phy
*phy
= &dev
->phy
;
3955 struct b43_phy_n
*nphy
= dev
->phy
.n
;
3960 if (phy
->chandef
->chan
->flags
& IEEE80211_CHAN_NO_IR
)
3963 if (b43_nphy_ipa(dev
))
3964 b43_nphy_ipa_internal_tssi_setup(dev
);
3967 b43_nphy_rf_ctl_override_rev19(dev
, 0x1000, 0, 3, false, 0);
3968 else if (phy
->rev
>= 7)
3969 b43_nphy_rf_ctl_override_rev7(dev
, 0x1000, 0, 3, false, 0);
3970 else if (phy
->rev
>= 3)
3971 b43_nphy_rf_ctl_override(dev
, 0x2000, 0, 3, false);
3973 b43_nphy_stop_playback(dev
);
3974 b43_nphy_tx_tone(dev
, 4000, 0, false, false, false);
3976 tmp
= b43_nphy_poll_rssi(dev
, N_RSSI_TSSI_2G
, rssi
, 1);
3977 b43_nphy_stop_playback(dev
);
3979 b43_nphy_rssi_select(dev
, 0, N_RSSI_W1
);
3982 b43_nphy_rf_ctl_override_rev19(dev
, 0x1000, 0, 3, true, 0);
3983 else if (phy
->rev
>= 7)
3984 b43_nphy_rf_ctl_override_rev7(dev
, 0x1000, 0, 3, true, 0);
3985 else if (phy
->rev
>= 3)
3986 b43_nphy_rf_ctl_override(dev
, 0x2000, 0, 3, true);
3988 if (phy
->rev
>= 19) {
3991 } else if (phy
->rev
>= 3) {
3992 nphy
->pwr_ctl_info
[0].idle_tssi_5g
= (tmp
>> 24) & 0xFF;
3993 nphy
->pwr_ctl_info
[1].idle_tssi_5g
= (tmp
>> 8) & 0xFF;
3995 nphy
->pwr_ctl_info
[0].idle_tssi_5g
= (tmp
>> 16) & 0xFF;
3996 nphy
->pwr_ctl_info
[1].idle_tssi_5g
= tmp
& 0xFF;
3998 nphy
->pwr_ctl_info
[0].idle_tssi_2g
= (tmp
>> 24) & 0xFF;
3999 nphy
->pwr_ctl_info
[1].idle_tssi_2g
= (tmp
>> 8) & 0xFF;
4002 /* http://bcm-v4.sipsolutions.net/PHY/N/TxPwrLimitToTbl */
4003 static void b43_nphy_tx_prepare_adjusted_power_table(struct b43_wldev
*dev
)
4005 struct b43_phy_n
*nphy
= dev
->phy
.n
;
4010 /* Array adj_pwr_tbl corresponds to the hardware table. It consists of
4011 * 21 groups, each containing 4 entries.
4013 * First group has entries for CCK modulation.
4014 * The rest of groups has 1 entry per modulation (SISO, CDD, STBC, SDM).
4016 * Group 0 is for CCK
4017 * Groups 1..4 use BPSK (group per coding rate)
4018 * Groups 5..8 use QPSK (group per coding rate)
4019 * Groups 9..12 use 16-QAM (group per coding rate)
4020 * Groups 13..16 use 64-QAM (group per coding rate)
4021 * Groups 17..20 are unknown
4024 for (i
= 0; i
< 4; i
++)
4025 nphy
->adj_pwr_tbl
[i
] = nphy
->tx_power_offset
[i
];
4027 for (stf_mode
= 0; stf_mode
< 4; stf_mode
++) {
4031 if (b43_is_40mhz(dev
) && dev
->phy
.rev
>= 5) {
4035 idx
= b43_is_40mhz(dev
) ? 52 : 4;
4039 idx
= b43_is_40mhz(dev
) ? 76 : 28;
4042 idx
= b43_is_40mhz(dev
) ? 84 : 36;
4045 idx
= b43_is_40mhz(dev
) ? 92 : 44;
4049 for (i
= 0; i
< 20; i
++) {
4050 nphy
->adj_pwr_tbl
[4 + 4 * i
+ stf_mode
] =
4051 nphy
->tx_power_offset
[idx
];
4056 if (i
== 3 || i
== 4 || i
== 7 || i
== 8 || i
== 11 ||
4063 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlSetup */
4064 static void b43_nphy_tx_power_ctl_setup(struct b43_wldev
*dev
)
4066 struct b43_phy
*phy
= &dev
->phy
;
4067 struct b43_phy_n
*nphy
= dev
->phy
.n
;
4068 struct ssb_sprom
*sprom
= dev
->dev
->bus_sprom
;
4070 s16 a1
[2], b0
[2], b1
[2];
4076 u16 freq
= phy
->chandef
->chan
->center_freq
;
4078 u16 r
; /* routing */
4081 if (dev
->dev
->core_rev
== 11 || dev
->dev
->core_rev
== 12) {
4082 b43_maskset32(dev
, B43_MMIO_MACCTL
, ~0, 0x200000);
4083 b43_read32(dev
, B43_MMIO_MACCTL
);
4087 if (nphy
->hang_avoid
)
4088 b43_nphy_stay_in_carrier_search(dev
, true);
4090 b43_phy_set(dev
, B43_NPHY_TSSIMODE
, B43_NPHY_TSSIMODE_EN
);
4091 if (dev
->phy
.rev
>= 3)
4092 b43_phy_mask(dev
, B43_NPHY_TXPCTL_CMD
,
4093 ~B43_NPHY_TXPCTL_CMD_PCTLEN
& 0xFFFF);
4095 b43_phy_set(dev
, B43_NPHY_TXPCTL_CMD
,
4096 B43_NPHY_TXPCTL_CMD_PCTLEN
);
4098 if (dev
->dev
->core_rev
== 11 || dev
->dev
->core_rev
== 12)
4099 b43_maskset32(dev
, B43_MMIO_MACCTL
, ~0x200000, 0);
4101 if (sprom
->revision
< 4) {
4102 idle
[0] = nphy
->pwr_ctl_info
[0].idle_tssi_2g
;
4103 idle
[1] = nphy
->pwr_ctl_info
[1].idle_tssi_2g
;
4104 target
[0] = target
[1] = 52;
4105 a1
[0] = a1
[1] = -424;
4106 b0
[0] = b0
[1] = 5612;
4107 b1
[0] = b1
[1] = -1393;
4109 if (b43_current_band(dev
->wl
) == IEEE80211_BAND_2GHZ
) {
4110 for (c
= 0; c
< 2; c
++) {
4111 idle
[c
] = nphy
->pwr_ctl_info
[c
].idle_tssi_2g
;
4112 target
[c
] = sprom
->core_pwr_info
[c
].maxpwr_2g
;
4113 a1
[c
] = sprom
->core_pwr_info
[c
].pa_2g
[0];
4114 b0
[c
] = sprom
->core_pwr_info
[c
].pa_2g
[1];
4115 b1
[c
] = sprom
->core_pwr_info
[c
].pa_2g
[2];
4117 } else if (freq
>= 4900 && freq
< 5100) {
4118 for (c
= 0; c
< 2; c
++) {
4119 idle
[c
] = nphy
->pwr_ctl_info
[c
].idle_tssi_5g
;
4120 target
[c
] = sprom
->core_pwr_info
[c
].maxpwr_5gl
;
4121 a1
[c
] = sprom
->core_pwr_info
[c
].pa_5gl
[0];
4122 b0
[c
] = sprom
->core_pwr_info
[c
].pa_5gl
[1];
4123 b1
[c
] = sprom
->core_pwr_info
[c
].pa_5gl
[2];
4125 } else if (freq
>= 5100 && freq
< 5500) {
4126 for (c
= 0; c
< 2; c
++) {
4127 idle
[c
] = nphy
->pwr_ctl_info
[c
].idle_tssi_5g
;
4128 target
[c
] = sprom
->core_pwr_info
[c
].maxpwr_5g
;
4129 a1
[c
] = sprom
->core_pwr_info
[c
].pa_5g
[0];
4130 b0
[c
] = sprom
->core_pwr_info
[c
].pa_5g
[1];
4131 b1
[c
] = sprom
->core_pwr_info
[c
].pa_5g
[2];
4133 } else if (freq
>= 5500) {
4134 for (c
= 0; c
< 2; c
++) {
4135 idle
[c
] = nphy
->pwr_ctl_info
[c
].idle_tssi_5g
;
4136 target
[c
] = sprom
->core_pwr_info
[c
].maxpwr_5gh
;
4137 a1
[c
] = sprom
->core_pwr_info
[c
].pa_5gh
[0];
4138 b0
[c
] = sprom
->core_pwr_info
[c
].pa_5gh
[1];
4139 b1
[c
] = sprom
->core_pwr_info
[c
].pa_5gh
[2];
4142 idle
[0] = nphy
->pwr_ctl_info
[0].idle_tssi_5g
;
4143 idle
[1] = nphy
->pwr_ctl_info
[1].idle_tssi_5g
;
4144 target
[0] = target
[1] = 52;
4145 a1
[0] = a1
[1] = -424;
4146 b0
[0] = b0
[1] = 5612;
4147 b1
[0] = b1
[1] = -1393;
4150 /* target[0] = target[1] = nphy->tx_power_max; */
4152 if (dev
->phy
.rev
>= 3) {
4153 if (sprom
->fem
.ghz2
.tssipos
)
4154 b43_phy_set(dev
, B43_NPHY_TXPCTL_ITSSI
, 0x4000);
4155 if (dev
->phy
.rev
>= 7) {
4156 for (c
= 0; c
< 2; c
++) {
4157 r
= c
? 0x190 : 0x170;
4158 if (b43_nphy_ipa(dev
))
4159 b43_radio_write(dev
, r
+ 0x9, (b43_current_band(dev
->wl
) == IEEE80211_BAND_2GHZ
) ? 0xE : 0xC);
4162 if (b43_nphy_ipa(dev
)) {
4163 tmp
= (b43_current_band(dev
->wl
) == IEEE80211_BAND_5GHZ
) ? 0xC : 0xE;
4164 b43_radio_write(dev
,
4165 B2056_TX0
| B2056_TX_TX_SSI_MUX
, tmp
);
4166 b43_radio_write(dev
,
4167 B2056_TX1
| B2056_TX_TX_SSI_MUX
, tmp
);
4169 b43_radio_write(dev
,
4170 B2056_TX0
| B2056_TX_TX_SSI_MUX
, 0x11);
4171 b43_radio_write(dev
,
4172 B2056_TX1
| B2056_TX_TX_SSI_MUX
, 0x11);
4177 if (dev
->dev
->core_rev
== 11 || dev
->dev
->core_rev
== 12) {
4178 b43_maskset32(dev
, B43_MMIO_MACCTL
, ~0, 0x200000);
4179 b43_read32(dev
, B43_MMIO_MACCTL
);
4183 if (phy
->rev
>= 19) {
4185 } else if (phy
->rev
>= 7) {
4186 b43_phy_maskset(dev
, B43_NPHY_TXPCTL_CMD
,
4187 ~B43_NPHY_TXPCTL_CMD_INIT
, 0x19);
4188 b43_phy_maskset(dev
, B43_NPHY_TXPCTL_INIT
,
4189 ~B43_NPHY_TXPCTL_INIT_PIDXI1
, 0x19);
4191 b43_phy_maskset(dev
, B43_NPHY_TXPCTL_CMD
,
4192 ~B43_NPHY_TXPCTL_CMD_INIT
, 0x40);
4193 if (dev
->phy
.rev
> 1)
4194 b43_phy_maskset(dev
, B43_NPHY_TXPCTL_INIT
,
4195 ~B43_NPHY_TXPCTL_INIT_PIDXI1
, 0x40);
4198 if (dev
->dev
->core_rev
== 11 || dev
->dev
->core_rev
== 12)
4199 b43_maskset32(dev
, B43_MMIO_MACCTL
, ~0x200000, 0);
4201 b43_phy_write(dev
, B43_NPHY_TXPCTL_N
,
4202 0xF0 << B43_NPHY_TXPCTL_N_TSSID_SHIFT
|
4203 3 << B43_NPHY_TXPCTL_N_NPTIL2_SHIFT
);
4204 b43_phy_write(dev
, B43_NPHY_TXPCTL_ITSSI
,
4205 idle
[0] << B43_NPHY_TXPCTL_ITSSI_0_SHIFT
|
4206 idle
[1] << B43_NPHY_TXPCTL_ITSSI_1_SHIFT
|
4207 B43_NPHY_TXPCTL_ITSSI_BINF
);
4208 b43_phy_write(dev
, B43_NPHY_TXPCTL_TPWR
,
4209 target
[0] << B43_NPHY_TXPCTL_TPWR_0_SHIFT
|
4210 target
[1] << B43_NPHY_TXPCTL_TPWR_1_SHIFT
);
4212 for (c
= 0; c
< 2; c
++) {
4213 for (i
= 0; i
< 64; i
++) {
4214 num
= 8 * (16 * b0
[c
] + b1
[c
] * i
);
4215 den
= 32768 + a1
[c
] * i
;
4216 pwr
= max((4 * num
+ den
/ 2) / den
, -8);
4217 if (dev
->phy
.rev
< 3 && (i
<= (31 - idle
[c
] + 1)))
4218 pwr
= max(pwr
, target
[c
] + 1);
4221 b43_ntab_write_bulk(dev
, B43_NTAB32(26 + c
, 0), 64, regval
);
4224 b43_nphy_tx_prepare_adjusted_power_table(dev
);
4225 b43_ntab_write_bulk(dev
, B43_NTAB16(26, 64), 84, nphy
->adj_pwr_tbl
);
4226 b43_ntab_write_bulk(dev
, B43_NTAB16(27, 64), 84, nphy
->adj_pwr_tbl
);
4228 if (nphy
->hang_avoid
)
4229 b43_nphy_stay_in_carrier_search(dev
, false);
4232 static void b43_nphy_tx_gain_table_upload(struct b43_wldev
*dev
)
4234 struct b43_phy
*phy
= &dev
->phy
;
4236 const u32
*table
= NULL
;
4241 table
= b43_nphy_get_tx_gain_table(dev
);
4245 b43_ntab_write_bulk(dev
, B43_NTAB32(26, 192), 128, table
);
4246 b43_ntab_write_bulk(dev
, B43_NTAB32(27, 192), 128, table
);
4252 nphy
->gmval
= (table
[0] >> 16) & 0x7000;
4255 for (i
= 0; i
< 128; i
++) {
4256 if (phy
->rev
>= 19) {
4259 } else if (phy
->rev
>= 7) {
4263 pga_gain
= (table
[i
] >> 24) & 0xF;
4264 if (b43_current_band(dev
->wl
) == IEEE80211_BAND_2GHZ
)
4265 rfpwr_offset
= b43_ntab_papd_pga_gain_delta_ipa_2g
[pga_gain
];
4267 rfpwr_offset
= 0; /* FIXME */
4270 b43_ntab_write(dev
, B43_NTAB32(26, 576 + i
), rfpwr_offset
);
4271 b43_ntab_write(dev
, B43_NTAB32(27, 576 + i
), rfpwr_offset
);
4275 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PA%20override */
4276 static void b43_nphy_pa_override(struct b43_wldev
*dev
, bool enable
)
4278 struct b43_phy_n
*nphy
= dev
->phy
.n
;
4279 enum ieee80211_band band
;
4283 nphy
->rfctrl_intc1_save
= b43_phy_read(dev
,
4284 B43_NPHY_RFCTL_INTC1
);
4285 nphy
->rfctrl_intc2_save
= b43_phy_read(dev
,
4286 B43_NPHY_RFCTL_INTC2
);
4287 band
= b43_current_band(dev
->wl
);
4288 if (dev
->phy
.rev
>= 7) {
4290 } else if (dev
->phy
.rev
>= 3) {
4291 if (band
== IEEE80211_BAND_5GHZ
)
4296 if (band
== IEEE80211_BAND_5GHZ
)
4301 b43_phy_write(dev
, B43_NPHY_RFCTL_INTC1
, tmp
);
4302 b43_phy_write(dev
, B43_NPHY_RFCTL_INTC2
, tmp
);
4304 b43_phy_write(dev
, B43_NPHY_RFCTL_INTC1
,
4305 nphy
->rfctrl_intc1_save
);
4306 b43_phy_write(dev
, B43_NPHY_RFCTL_INTC2
,
4307 nphy
->rfctrl_intc2_save
);
4312 * TX low-pass filter bandwidth setup
4313 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxLpFbw
4315 static void b43_nphy_tx_lpf_bw(struct b43_wldev
*dev
)
4319 if (dev
->phy
.rev
< 3 || dev
->phy
.rev
>= 7)
4322 if (b43_nphy_ipa(dev
))
4323 tmp
= b43_is_40mhz(dev
) ? 5 : 4;
4325 tmp
= b43_is_40mhz(dev
) ? 3 : 1;
4326 b43_phy_write(dev
, B43_NPHY_TXF_40CO_B32S2
,
4327 (tmp
<< 9) | (tmp
<< 6) | (tmp
<< 3) | tmp
);
4329 if (b43_nphy_ipa(dev
)) {
4330 tmp
= b43_is_40mhz(dev
) ? 4 : 1;
4331 b43_phy_write(dev
, B43_NPHY_TXF_40CO_B1S2
,
4332 (tmp
<< 9) | (tmp
<< 6) | (tmp
<< 3) | tmp
);
4336 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqEst */
4337 static void b43_nphy_rx_iq_est(struct b43_wldev
*dev
, struct nphy_iq_est
*est
,
4338 u16 samps
, u8 time
, bool wait
)
4343 b43_phy_write(dev
, B43_NPHY_IQEST_SAMCNT
, samps
);
4344 b43_phy_maskset(dev
, B43_NPHY_IQEST_WT
, ~B43_NPHY_IQEST_WT_VAL
, time
);
4346 b43_phy_set(dev
, B43_NPHY_IQEST_CMD
, B43_NPHY_IQEST_CMD_MODE
);
4348 b43_phy_mask(dev
, B43_NPHY_IQEST_CMD
, ~B43_NPHY_IQEST_CMD_MODE
);
4350 b43_phy_set(dev
, B43_NPHY_IQEST_CMD
, B43_NPHY_IQEST_CMD_START
);
4352 for (i
= 1000; i
; i
--) {
4353 tmp
= b43_phy_read(dev
, B43_NPHY_IQEST_CMD
);
4354 if (!(tmp
& B43_NPHY_IQEST_CMD_START
)) {
4355 est
->i0_pwr
= (b43_phy_read(dev
, B43_NPHY_IQEST_IPACC_HI0
) << 16) |
4356 b43_phy_read(dev
, B43_NPHY_IQEST_IPACC_LO0
);
4357 est
->q0_pwr
= (b43_phy_read(dev
, B43_NPHY_IQEST_QPACC_HI0
) << 16) |
4358 b43_phy_read(dev
, B43_NPHY_IQEST_QPACC_LO0
);
4359 est
->iq0_prod
= (b43_phy_read(dev
, B43_NPHY_IQEST_IQACC_HI0
) << 16) |
4360 b43_phy_read(dev
, B43_NPHY_IQEST_IQACC_LO0
);
4362 est
->i1_pwr
= (b43_phy_read(dev
, B43_NPHY_IQEST_IPACC_HI1
) << 16) |
4363 b43_phy_read(dev
, B43_NPHY_IQEST_IPACC_LO1
);
4364 est
->q1_pwr
= (b43_phy_read(dev
, B43_NPHY_IQEST_QPACC_HI1
) << 16) |
4365 b43_phy_read(dev
, B43_NPHY_IQEST_QPACC_LO1
);
4366 est
->iq1_prod
= (b43_phy_read(dev
, B43_NPHY_IQEST_IQACC_HI1
) << 16) |
4367 b43_phy_read(dev
, B43_NPHY_IQEST_IQACC_LO1
);
4372 memset(est
, 0, sizeof(*est
));
4375 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqCoeffs */
4376 static void b43_nphy_rx_iq_coeffs(struct b43_wldev
*dev
, bool write
,
4377 struct b43_phy_n_iq_comp
*pcomp
)
4380 b43_phy_write(dev
, B43_NPHY_C1_RXIQ_COMPA0
, pcomp
->a0
);
4381 b43_phy_write(dev
, B43_NPHY_C1_RXIQ_COMPB0
, pcomp
->b0
);
4382 b43_phy_write(dev
, B43_NPHY_C2_RXIQ_COMPA1
, pcomp
->a1
);
4383 b43_phy_write(dev
, B43_NPHY_C2_RXIQ_COMPB1
, pcomp
->b1
);
4385 pcomp
->a0
= b43_phy_read(dev
, B43_NPHY_C1_RXIQ_COMPA0
);
4386 pcomp
->b0
= b43_phy_read(dev
, B43_NPHY_C1_RXIQ_COMPB0
);
4387 pcomp
->a1
= b43_phy_read(dev
, B43_NPHY_C2_RXIQ_COMPA1
);
4388 pcomp
->b1
= b43_phy_read(dev
, B43_NPHY_C2_RXIQ_COMPB1
);
4393 /* Ready but not used anywhere */
4394 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhyCleanup */
4395 static void b43_nphy_rx_cal_phy_cleanup(struct b43_wldev
*dev
, u8 core
)
4397 u16
*regs
= dev
->phy
.n
->tx_rx_cal_phy_saveregs
;
4399 b43_phy_write(dev
, B43_NPHY_RFSEQCA
, regs
[0]);
4401 b43_phy_write(dev
, B43_NPHY_AFECTL_C1
, regs
[1]);
4402 b43_phy_write(dev
, B43_NPHY_AFECTL_OVER1
, regs
[2]);
4404 b43_phy_write(dev
, B43_NPHY_AFECTL_C2
, regs
[1]);
4405 b43_phy_write(dev
, B43_NPHY_AFECTL_OVER
, regs
[2]);
4407 b43_phy_write(dev
, B43_NPHY_RFCTL_INTC1
, regs
[3]);
4408 b43_phy_write(dev
, B43_NPHY_RFCTL_INTC2
, regs
[4]);
4409 b43_phy_write(dev
, B43_NPHY_RFCTL_RSSIO1
, regs
[5]);
4410 b43_phy_write(dev
, B43_NPHY_RFCTL_RSSIO2
, regs
[6]);
4411 b43_phy_write(dev
, B43_NPHY_TXF_40CO_B1S1
, regs
[7]);
4412 b43_phy_write(dev
, B43_NPHY_RFCTL_OVER
, regs
[8]);
4413 b43_phy_write(dev
, B43_NPHY_PAPD_EN0
, regs
[9]);
4414 b43_phy_write(dev
, B43_NPHY_PAPD_EN1
, regs
[10]);
4417 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhySetup */
4418 static void b43_nphy_rx_cal_phy_setup(struct b43_wldev
*dev
, u8 core
)
4421 u16
*regs
= dev
->phy
.n
->tx_rx_cal_phy_saveregs
;
4423 regs
[0] = b43_phy_read(dev
, B43_NPHY_RFSEQCA
);
4425 regs
[1] = b43_phy_read(dev
, B43_NPHY_AFECTL_C1
);
4426 regs
[2] = b43_phy_read(dev
, B43_NPHY_AFECTL_OVER1
);
4428 regs
[1] = b43_phy_read(dev
, B43_NPHY_AFECTL_C2
);
4429 regs
[2] = b43_phy_read(dev
, B43_NPHY_AFECTL_OVER
);
4431 regs
[3] = b43_phy_read(dev
, B43_NPHY_RFCTL_INTC1
);
4432 regs
[4] = b43_phy_read(dev
, B43_NPHY_RFCTL_INTC2
);
4433 regs
[5] = b43_phy_read(dev
, B43_NPHY_RFCTL_RSSIO1
);
4434 regs
[6] = b43_phy_read(dev
, B43_NPHY_RFCTL_RSSIO2
);
4435 regs
[7] = b43_phy_read(dev
, B43_NPHY_TXF_40CO_B1S1
);
4436 regs
[8] = b43_phy_read(dev
, B43_NPHY_RFCTL_OVER
);
4437 regs
[9] = b43_phy_read(dev
, B43_NPHY_PAPD_EN0
);
4438 regs
[10] = b43_phy_read(dev
, B43_NPHY_PAPD_EN1
);
4440 b43_phy_mask(dev
, B43_NPHY_PAPD_EN0
, ~0x0001);
4441 b43_phy_mask(dev
, B43_NPHY_PAPD_EN1
, ~0x0001);
4443 b43_phy_maskset(dev
, B43_NPHY_RFSEQCA
,
4444 ~B43_NPHY_RFSEQCA_RXDIS
& 0xFFFF,
4445 ((1 - core
) << B43_NPHY_RFSEQCA_RXDIS_SHIFT
));
4446 b43_phy_maskset(dev
, B43_NPHY_RFSEQCA
, ~B43_NPHY_RFSEQCA_TXEN
,
4447 ((1 - core
) << B43_NPHY_RFSEQCA_TXEN_SHIFT
));
4448 b43_phy_maskset(dev
, B43_NPHY_RFSEQCA
, ~B43_NPHY_RFSEQCA_RXEN
,
4449 (core
<< B43_NPHY_RFSEQCA_RXEN_SHIFT
));
4450 b43_phy_maskset(dev
, B43_NPHY_RFSEQCA
, ~B43_NPHY_RFSEQCA_TXDIS
,
4451 (core
<< B43_NPHY_RFSEQCA_TXDIS_SHIFT
));
4454 b43_phy_mask(dev
, B43_NPHY_AFECTL_C1
, ~0x0007);
4455 b43_phy_set(dev
, B43_NPHY_AFECTL_OVER1
, 0x0007);
4457 b43_phy_mask(dev
, B43_NPHY_AFECTL_C2
, ~0x0007);
4458 b43_phy_set(dev
, B43_NPHY_AFECTL_OVER
, 0x0007);
4461 b43_nphy_rf_ctl_intc_override(dev
, N_INTC_OVERRIDE_PA
, 0, 3);
4462 b43_nphy_rf_ctl_override(dev
, 8, 0, 3, false);
4463 b43_nphy_force_rf_sequence(dev
, B43_RFSEQ_RX2TX
);
4472 b43_nphy_rf_ctl_intc_override(dev
, N_INTC_OVERRIDE_TRSW
, rxval
,
4474 b43_nphy_rf_ctl_intc_override(dev
, N_INTC_OVERRIDE_TRSW
, txval
,
4479 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalcRxIqComp */
4480 static void b43_nphy_calc_rx_iq_comp(struct b43_wldev
*dev
, u8 mask
)
4486 int iq_nbits
, qq_nbits
;
4490 struct nphy_iq_est est
;
4491 struct b43_phy_n_iq_comp old
;
4492 struct b43_phy_n_iq_comp
new = { };
4498 b43_nphy_rx_iq_coeffs(dev
, false, &old
);
4499 b43_nphy_rx_iq_coeffs(dev
, true, &new);
4500 b43_nphy_rx_iq_est(dev
, &est
, 0x4000, 32, false);
4503 for (i
= 0; i
< 2; i
++) {
4504 if (i
== 0 && (mask
& 1)) {
4508 } else if (i
== 1 && (mask
& 2)) {
4521 iq_nbits
= fls(abs(iq
));
4524 arsh
= iq_nbits
- 20;
4526 a
= -((iq
<< (30 - iq_nbits
)) + (ii
>> (1 + arsh
)));
4529 a
= -((iq
<< (30 - iq_nbits
)) + (ii
<< (-1 - arsh
)));
4538 brsh
= qq_nbits
- 11;
4540 b
= (qq
<< (31 - qq_nbits
));
4543 b
= (qq
<< (31 - qq_nbits
));
4550 b
= int_sqrt(b
/ tmp
- a
* a
) - (1 << 10);
4552 if (i
== 0 && (mask
& 0x1)) {
4553 if (dev
->phy
.rev
>= 3) {
4560 } else if (i
== 1 && (mask
& 0x2)) {
4561 if (dev
->phy
.rev
>= 3) {
4574 b43_nphy_rx_iq_coeffs(dev
, true, &new);
4577 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxIqWar */
4578 static void b43_nphy_tx_iq_workaround(struct b43_wldev
*dev
)
4581 b43_ntab_read_bulk(dev
, B43_NTAB16(0xF, 0x50), 4, array
);
4583 b43_shm_write16(dev
, B43_SHM_SHARED
, B43_SHM_SH_NPHY_TXIQW0
, array
[0]);
4584 b43_shm_write16(dev
, B43_SHM_SHARED
, B43_SHM_SH_NPHY_TXIQW1
, array
[1]);
4585 b43_shm_write16(dev
, B43_SHM_SHARED
, B43_SHM_SH_NPHY_TXIQW2
, array
[2]);
4586 b43_shm_write16(dev
, B43_SHM_SHARED
, B43_SHM_SH_NPHY_TXIQW3
, array
[3]);
4589 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SpurWar */
4590 static void b43_nphy_spur_workaround(struct b43_wldev
*dev
)
4592 struct b43_phy_n
*nphy
= dev
->phy
.n
;
4594 u8 channel
= dev
->phy
.channel
;
4595 int tone
[2] = { 57, 58 };
4596 u32 noise
[2] = { 0x3FF, 0x3FF };
4598 B43_WARN_ON(dev
->phy
.rev
< 3);
4600 if (nphy
->hang_avoid
)
4601 b43_nphy_stay_in_carrier_search(dev
, 1);
4603 if (nphy
->gband_spurwar_en
) {
4604 /* TODO: N PHY Adjust Analog Pfbw (7) */
4605 if (channel
== 11 && b43_is_40mhz(dev
))
4606 ; /* TODO: N PHY Adjust Min Noise Var(2, tone, noise)*/
4608 ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
4609 /* TODO: N PHY Adjust CRS Min Power (0x1E) */
4612 if (nphy
->aband_spurwar_en
) {
4613 if (channel
== 54) {
4616 } else if (channel
== 38 || channel
== 102 || channel
== 118) {
4617 if (0 /* FIXME */) {
4624 } else if (channel
== 134) {
4627 } else if (channel
== 151) {
4630 } else if (channel
== 153 || channel
== 161) {
4638 if (!tone
[0] && !noise
[0])
4639 ; /* TODO: N PHY Adjust Min Noise Var(1, tone, noise)*/
4641 ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
4644 if (nphy
->hang_avoid
)
4645 b43_nphy_stay_in_carrier_search(dev
, 0);
4648 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlCoefSetup */
4649 static void b43_nphy_tx_pwr_ctrl_coef_setup(struct b43_wldev
*dev
)
4651 struct b43_phy_n
*nphy
= dev
->phy
.n
;
4654 u32 cur_real
, cur_imag
, real_part
, imag_part
;
4658 if (nphy
->hang_avoid
)
4659 b43_nphy_stay_in_carrier_search(dev
, true);
4661 b43_ntab_read_bulk(dev
, B43_NTAB16(15, 80), 7, buffer
);
4663 for (i
= 0; i
< 2; i
++) {
4664 tmp
= ((buffer
[i
* 2] & 0x3FF) << 10) |
4665 (buffer
[i
* 2 + 1] & 0x3FF);
4666 b43_phy_write(dev
, B43_NPHY_TABLE_ADDR
,
4667 (((i
+ 26) << 10) | 320));
4668 for (j
= 0; j
< 128; j
++) {
4669 b43_phy_write(dev
, B43_NPHY_TABLE_DATAHI
,
4670 ((tmp
>> 16) & 0xFFFF));
4671 b43_phy_write(dev
, B43_NPHY_TABLE_DATALO
,
4676 for (i
= 0; i
< 2; i
++) {
4677 tmp
= buffer
[5 + i
];
4678 real_part
= (tmp
>> 8) & 0xFF;
4679 imag_part
= (tmp
& 0xFF);
4680 b43_phy_write(dev
, B43_NPHY_TABLE_ADDR
,
4681 (((i
+ 26) << 10) | 448));
4683 if (dev
->phy
.rev
>= 3) {
4684 cur_real
= real_part
;
4685 cur_imag
= imag_part
;
4686 tmp
= ((cur_real
& 0xFF) << 8) | (cur_imag
& 0xFF);
4689 for (j
= 0; j
< 128; j
++) {
4690 if (dev
->phy
.rev
< 3) {
4691 cur_real
= (real_part
* loscale
[j
] + 128) >> 8;
4692 cur_imag
= (imag_part
* loscale
[j
] + 128) >> 8;
4693 tmp
= ((cur_real
& 0xFF) << 8) |
4696 b43_phy_write(dev
, B43_NPHY_TABLE_DATAHI
,
4697 ((tmp
>> 16) & 0xFFFF));
4698 b43_phy_write(dev
, B43_NPHY_TABLE_DATALO
,
4703 if (dev
->phy
.rev
>= 3) {
4704 b43_shm_write16(dev
, B43_SHM_SHARED
,
4705 B43_SHM_SH_NPHY_TXPWR_INDX0
, 0xFFFF);
4706 b43_shm_write16(dev
, B43_SHM_SHARED
,
4707 B43_SHM_SH_NPHY_TXPWR_INDX1
, 0xFFFF);
4710 if (nphy
->hang_avoid
)
4711 b43_nphy_stay_in_carrier_search(dev
, false);
4715 * Restore RSSI Calibration
4716 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreRssiCal
4718 static void b43_nphy_restore_rssi_cal(struct b43_wldev
*dev
)
4720 struct b43_phy_n
*nphy
= dev
->phy
.n
;
4722 u16
*rssical_radio_regs
= NULL
;
4723 u16
*rssical_phy_regs
= NULL
;
4725 if (b43_current_band(dev
->wl
) == IEEE80211_BAND_2GHZ
) {
4726 if (!nphy
->rssical_chanspec_2G
.center_freq
)
4728 rssical_radio_regs
= nphy
->rssical_cache
.rssical_radio_regs_2G
;
4729 rssical_phy_regs
= nphy
->rssical_cache
.rssical_phy_regs_2G
;
4731 if (!nphy
->rssical_chanspec_5G
.center_freq
)
4733 rssical_radio_regs
= nphy
->rssical_cache
.rssical_radio_regs_5G
;
4734 rssical_phy_regs
= nphy
->rssical_cache
.rssical_phy_regs_5G
;
4737 if (dev
->phy
.rev
>= 19) {
4739 } else if (dev
->phy
.rev
>= 7) {
4740 b43_radio_maskset(dev
, R2057_NB_MASTER_CORE0
, ~R2057_VCM_MASK
,
4741 rssical_radio_regs
[0]);
4742 b43_radio_maskset(dev
, R2057_NB_MASTER_CORE1
, ~R2057_VCM_MASK
,
4743 rssical_radio_regs
[1]);
4745 b43_radio_maskset(dev
, B2056_RX0
| B2056_RX_RSSI_MISC
, 0xE3,
4746 rssical_radio_regs
[0]);
4747 b43_radio_maskset(dev
, B2056_RX1
| B2056_RX_RSSI_MISC
, 0xE3,
4748 rssical_radio_regs
[1]);
4751 b43_phy_write(dev
, B43_NPHY_RSSIMC_0I_RSSI_Z
, rssical_phy_regs
[0]);
4752 b43_phy_write(dev
, B43_NPHY_RSSIMC_0Q_RSSI_Z
, rssical_phy_regs
[1]);
4753 b43_phy_write(dev
, B43_NPHY_RSSIMC_1I_RSSI_Z
, rssical_phy_regs
[2]);
4754 b43_phy_write(dev
, B43_NPHY_RSSIMC_1Q_RSSI_Z
, rssical_phy_regs
[3]);
4756 b43_phy_write(dev
, B43_NPHY_RSSIMC_0I_RSSI_X
, rssical_phy_regs
[4]);
4757 b43_phy_write(dev
, B43_NPHY_RSSIMC_0Q_RSSI_X
, rssical_phy_regs
[5]);
4758 b43_phy_write(dev
, B43_NPHY_RSSIMC_1I_RSSI_X
, rssical_phy_regs
[6]);
4759 b43_phy_write(dev
, B43_NPHY_RSSIMC_1Q_RSSI_X
, rssical_phy_regs
[7]);
4761 b43_phy_write(dev
, B43_NPHY_RSSIMC_0I_RSSI_Y
, rssical_phy_regs
[8]);
4762 b43_phy_write(dev
, B43_NPHY_RSSIMC_0Q_RSSI_Y
, rssical_phy_regs
[9]);
4763 b43_phy_write(dev
, B43_NPHY_RSSIMC_1I_RSSI_Y
, rssical_phy_regs
[10]);
4764 b43_phy_write(dev
, B43_NPHY_RSSIMC_1Q_RSSI_Y
, rssical_phy_regs
[11]);
4767 static void b43_nphy_tx_cal_radio_setup_rev19(struct b43_wldev
*dev
)
4772 static void b43_nphy_tx_cal_radio_setup_rev7(struct b43_wldev
*dev
)
4774 struct b43_phy
*phy
= &dev
->phy
;
4775 struct b43_phy_n
*nphy
= dev
->phy
.n
;
4776 u16
*save
= nphy
->tx_rx_cal_radio_saveregs
;
4780 for (core
= 0; core
< 2; core
++) {
4781 r
= core
? 0x20 : 0;
4784 save
[off
+ 0] = b43_radio_read(dev
, r
+ R2057_TX0_TX_SSI_MASTER
);
4785 save
[off
+ 1] = b43_radio_read(dev
, r
+ R2057_TX0_IQCAL_VCM_HG
);
4786 save
[off
+ 2] = b43_radio_read(dev
, r
+ R2057_TX0_IQCAL_IDAC
);
4787 save
[off
+ 3] = b43_radio_read(dev
, r
+ R2057_TX0_TSSI_VCM
);
4789 save
[off
+ 5] = b43_radio_read(dev
, r
+ R2057_TX0_TX_SSI_MUX
);
4790 if (phy
->radio_rev
!= 5)
4791 save
[off
+ 6] = b43_radio_read(dev
, r
+ R2057_TX0_TSSIA
);
4792 save
[off
+ 7] = b43_radio_read(dev
, r
+ R2057_TX0_TSSIG
);
4793 save
[off
+ 8] = b43_radio_read(dev
, r
+ R2057_TX0_TSSI_MISC1
);
4795 if (b43_current_band(dev
->wl
) == IEEE80211_BAND_5GHZ
) {
4796 b43_radio_write(dev
, r
+ R2057_TX0_TX_SSI_MASTER
, 0xA);
4797 b43_radio_write(dev
, r
+ R2057_TX0_IQCAL_VCM_HG
, 0x43);
4798 b43_radio_write(dev
, r
+ R2057_TX0_IQCAL_IDAC
, 0x55);
4799 b43_radio_write(dev
, r
+ R2057_TX0_TSSI_VCM
, 0);
4800 b43_radio_write(dev
, r
+ R2057_TX0_TSSIG
, 0);
4801 if (nphy
->use_int_tx_iq_lo_cal
) {
4802 b43_radio_write(dev
, r
+ R2057_TX0_TX_SSI_MUX
, 0x4);
4803 tmp
= true ? 0x31 : 0x21; /* TODO */
4804 b43_radio_write(dev
, r
+ R2057_TX0_TSSIA
, tmp
);
4806 b43_radio_write(dev
, r
+ R2057_TX0_TSSI_MISC1
, 0x00);
4808 b43_radio_write(dev
, r
+ R2057_TX0_TX_SSI_MASTER
, 0x6);
4809 b43_radio_write(dev
, r
+ R2057_TX0_IQCAL_VCM_HG
, 0x43);
4810 b43_radio_write(dev
, r
+ R2057_TX0_IQCAL_IDAC
, 0x55);
4811 b43_radio_write(dev
, r
+ R2057_TX0_TSSI_VCM
, 0);
4813 if (phy
->radio_rev
!= 5)
4814 b43_radio_write(dev
, r
+ R2057_TX0_TSSIA
, 0);
4815 if (nphy
->use_int_tx_iq_lo_cal
) {
4816 b43_radio_write(dev
, r
+ R2057_TX0_TX_SSI_MUX
, 0x6);
4817 tmp
= true ? 0x31 : 0x21; /* TODO */
4818 b43_radio_write(dev
, r
+ R2057_TX0_TSSIG
, tmp
);
4820 b43_radio_write(dev
, r
+ R2057_TX0_TSSI_MISC1
, 0);
4825 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalRadioSetup */
4826 static void b43_nphy_tx_cal_radio_setup(struct b43_wldev
*dev
)
4828 struct b43_phy
*phy
= &dev
->phy
;
4829 struct b43_phy_n
*nphy
= dev
->phy
.n
;
4830 u16
*save
= nphy
->tx_rx_cal_radio_saveregs
;
4834 if (phy
->rev
>= 19) {
4835 b43_nphy_tx_cal_radio_setup_rev19(dev
);
4836 } else if (phy
->rev
>= 7) {
4837 b43_nphy_tx_cal_radio_setup_rev7(dev
);
4838 } else if (phy
->rev
>= 3) {
4839 for (i
= 0; i
< 2; i
++) {
4840 tmp
= (i
== 0) ? 0x2000 : 0x3000;
4843 save
[offset
+ 0] = b43_radio_read(dev
, B2055_CAL_RVARCTL
);
4844 save
[offset
+ 1] = b43_radio_read(dev
, B2055_CAL_LPOCTL
);
4845 save
[offset
+ 2] = b43_radio_read(dev
, B2055_CAL_TS
);
4846 save
[offset
+ 3] = b43_radio_read(dev
, B2055_CAL_RCCALRTS
);
4847 save
[offset
+ 4] = b43_radio_read(dev
, B2055_CAL_RCALRTS
);
4848 save
[offset
+ 5] = b43_radio_read(dev
, B2055_PADDRV
);
4849 save
[offset
+ 6] = b43_radio_read(dev
, B2055_XOCTL1
);
4850 save
[offset
+ 7] = b43_radio_read(dev
, B2055_XOCTL2
);
4851 save
[offset
+ 8] = b43_radio_read(dev
, B2055_XOREGUL
);
4852 save
[offset
+ 9] = b43_radio_read(dev
, B2055_XOMISC
);
4853 save
[offset
+ 10] = b43_radio_read(dev
, B2055_PLL_LFC1
);
4855 if (b43_current_band(dev
->wl
) == IEEE80211_BAND_5GHZ
) {
4856 b43_radio_write(dev
, tmp
| B2055_CAL_RVARCTL
, 0x0A);
4857 b43_radio_write(dev
, tmp
| B2055_CAL_LPOCTL
, 0x40);
4858 b43_radio_write(dev
, tmp
| B2055_CAL_TS
, 0x55);
4859 b43_radio_write(dev
, tmp
| B2055_CAL_RCCALRTS
, 0);
4860 b43_radio_write(dev
, tmp
| B2055_CAL_RCALRTS
, 0);
4861 if (nphy
->ipa5g_on
) {
4862 b43_radio_write(dev
, tmp
| B2055_PADDRV
, 4);
4863 b43_radio_write(dev
, tmp
| B2055_XOCTL1
, 1);
4865 b43_radio_write(dev
, tmp
| B2055_PADDRV
, 0);
4866 b43_radio_write(dev
, tmp
| B2055_XOCTL1
, 0x2F);
4868 b43_radio_write(dev
, tmp
| B2055_XOCTL2
, 0);
4870 b43_radio_write(dev
, tmp
| B2055_CAL_RVARCTL
, 0x06);
4871 b43_radio_write(dev
, tmp
| B2055_CAL_LPOCTL
, 0x40);
4872 b43_radio_write(dev
, tmp
| B2055_CAL_TS
, 0x55);
4873 b43_radio_write(dev
, tmp
| B2055_CAL_RCCALRTS
, 0);
4874 b43_radio_write(dev
, tmp
| B2055_CAL_RCALRTS
, 0);
4875 b43_radio_write(dev
, tmp
| B2055_XOCTL1
, 0);
4876 if (nphy
->ipa2g_on
) {
4877 b43_radio_write(dev
, tmp
| B2055_PADDRV
, 6);
4878 b43_radio_write(dev
, tmp
| B2055_XOCTL2
,
4879 (dev
->phy
.rev
< 5) ? 0x11 : 0x01);
4881 b43_radio_write(dev
, tmp
| B2055_PADDRV
, 0);
4882 b43_radio_write(dev
, tmp
| B2055_XOCTL2
, 0);
4885 b43_radio_write(dev
, tmp
| B2055_XOREGUL
, 0);
4886 b43_radio_write(dev
, tmp
| B2055_XOMISC
, 0);
4887 b43_radio_write(dev
, tmp
| B2055_PLL_LFC1
, 0);
4890 save
[0] = b43_radio_read(dev
, B2055_C1_TX_RF_IQCAL1
);
4891 b43_radio_write(dev
, B2055_C1_TX_RF_IQCAL1
, 0x29);
4893 save
[1] = b43_radio_read(dev
, B2055_C1_TX_RF_IQCAL2
);
4894 b43_radio_write(dev
, B2055_C1_TX_RF_IQCAL2
, 0x54);
4896 save
[2] = b43_radio_read(dev
, B2055_C2_TX_RF_IQCAL1
);
4897 b43_radio_write(dev
, B2055_C2_TX_RF_IQCAL1
, 0x29);
4899 save
[3] = b43_radio_read(dev
, B2055_C2_TX_RF_IQCAL2
);
4900 b43_radio_write(dev
, B2055_C2_TX_RF_IQCAL2
, 0x54);
4902 save
[3] = b43_radio_read(dev
, B2055_C1_PWRDET_RXTX
);
4903 save
[4] = b43_radio_read(dev
, B2055_C2_PWRDET_RXTX
);
4905 if (!(b43_phy_read(dev
, B43_NPHY_BANDCTL
) &
4906 B43_NPHY_BANDCTL_5GHZ
)) {
4907 b43_radio_write(dev
, B2055_C1_PWRDET_RXTX
, 0x04);
4908 b43_radio_write(dev
, B2055_C2_PWRDET_RXTX
, 0x04);
4910 b43_radio_write(dev
, B2055_C1_PWRDET_RXTX
, 0x20);
4911 b43_radio_write(dev
, B2055_C2_PWRDET_RXTX
, 0x20);
4914 if (dev
->phy
.rev
< 2) {
4915 b43_radio_set(dev
, B2055_C1_TX_BB_MXGM
, 0x20);
4916 b43_radio_set(dev
, B2055_C2_TX_BB_MXGM
, 0x20);
4918 b43_radio_mask(dev
, B2055_C1_TX_BB_MXGM
, ~0x20);
4919 b43_radio_mask(dev
, B2055_C2_TX_BB_MXGM
, ~0x20);
4924 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/UpdateTxCalLadder */
4925 static void b43_nphy_update_tx_cal_ladder(struct b43_wldev
*dev
, u16 core
)
4927 struct b43_phy_n
*nphy
= dev
->phy
.n
;
4931 u16 tmp
= nphy
->txcal_bbmult
;
4936 for (i
= 0; i
< 18; i
++) {
4937 scale
= (ladder_lo
[i
].percent
* tmp
) / 100;
4938 entry
= ((scale
& 0xFF) << 8) | ladder_lo
[i
].g_env
;
4939 b43_ntab_write(dev
, B43_NTAB16(15, i
), entry
);
4941 scale
= (ladder_iq
[i
].percent
* tmp
) / 100;
4942 entry
= ((scale
& 0xFF) << 8) | ladder_iq
[i
].g_env
;
4943 b43_ntab_write(dev
, B43_NTAB16(15, i
+ 32), entry
);
4947 static void b43_nphy_pa_set_tx_dig_filter(struct b43_wldev
*dev
, u16 offset
,
4952 offset
= B43_PHY_N(offset
);
4954 for (i
= 0; i
< 15; i
++, offset
++)
4955 b43_phy_write(dev
, offset
, filter
[i
]);
4958 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ExtPaSetTxDigiFilts */
4959 static void b43_nphy_ext_pa_set_tx_dig_filters(struct b43_wldev
*dev
)
4961 b43_nphy_pa_set_tx_dig_filter(dev
, 0x2C5,
4962 tbl_tx_filter_coef_rev4
[2]);
4965 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IpaSetTxDigiFilts */
4966 static void b43_nphy_int_pa_set_tx_dig_filters(struct b43_wldev
*dev
)
4968 /* B43_NPHY_TXF_20CO_S0A1, B43_NPHY_TXF_40CO_S0A1, unknown */
4969 static const u16 offset
[] = { 0x186, 0x195, 0x2C5 };
4970 static const s16 dig_filter_phy_rev16
[] = {
4971 -375, 136, -407, 208, -1527,
4972 956, 93, 186, 93, 230,
4973 -44, 230, 201, -191, 201,
4977 for (i
= 0; i
< 3; i
++)
4978 b43_nphy_pa_set_tx_dig_filter(dev
, offset
[i
],
4979 tbl_tx_filter_coef_rev4
[i
]);
4981 /* Verified with BCM43227 and BCM43228 */
4982 if (dev
->phy
.rev
== 16)
4983 b43_nphy_pa_set_tx_dig_filter(dev
, 0x186, dig_filter_phy_rev16
);
4985 if (dev
->dev
->chip_id
== BCMA_CHIP_ID_BCM43217
) {
4986 b43_nphy_pa_set_tx_dig_filter(dev
, 0x186, dig_filter_phy_rev16
);
4987 b43_nphy_pa_set_tx_dig_filter(dev
, 0x195,
4988 tbl_tx_filter_coef_rev4
[1]);
4991 if (b43_is_40mhz(dev
)) {
4992 b43_nphy_pa_set_tx_dig_filter(dev
, 0x186,
4993 tbl_tx_filter_coef_rev4
[3]);
4995 if (b43_current_band(dev
->wl
) == IEEE80211_BAND_5GHZ
)
4996 b43_nphy_pa_set_tx_dig_filter(dev
, 0x186,
4997 tbl_tx_filter_coef_rev4
[5]);
4998 if (dev
->phy
.channel
== 14)
4999 b43_nphy_pa_set_tx_dig_filter(dev
, 0x186,
5000 tbl_tx_filter_coef_rev4
[6]);
5004 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetTxGain */
5005 static struct nphy_txgains
b43_nphy_get_tx_gains(struct b43_wldev
*dev
)
5007 struct b43_phy_n
*nphy
= dev
->phy
.n
;
5010 struct nphy_txgains target
;
5011 const u32
*table
= NULL
;
5013 if (!nphy
->txpwrctrl
) {
5016 if (nphy
->hang_avoid
)
5017 b43_nphy_stay_in_carrier_search(dev
, true);
5018 b43_ntab_read_bulk(dev
, B43_NTAB16(7, 0x110), 2, curr_gain
);
5019 if (nphy
->hang_avoid
)
5020 b43_nphy_stay_in_carrier_search(dev
, false);
5022 for (i
= 0; i
< 2; ++i
) {
5023 if (dev
->phy
.rev
>= 7) {
5024 target
.ipa
[i
] = curr_gain
[i
] & 0x0007;
5025 target
.pad
[i
] = (curr_gain
[i
] & 0x00F8) >> 3;
5026 target
.pga
[i
] = (curr_gain
[i
] & 0x0F00) >> 8;
5027 target
.txgm
[i
] = (curr_gain
[i
] & 0x7000) >> 12;
5028 target
.tx_lpf
[i
] = (curr_gain
[i
] & 0x8000) >> 15;
5029 } else if (dev
->phy
.rev
>= 3) {
5030 target
.ipa
[i
] = curr_gain
[i
] & 0x000F;
5031 target
.pad
[i
] = (curr_gain
[i
] & 0x00F0) >> 4;
5032 target
.pga
[i
] = (curr_gain
[i
] & 0x0F00) >> 8;
5033 target
.txgm
[i
] = (curr_gain
[i
] & 0x7000) >> 12;
5035 target
.ipa
[i
] = curr_gain
[i
] & 0x0003;
5036 target
.pad
[i
] = (curr_gain
[i
] & 0x000C) >> 2;
5037 target
.pga
[i
] = (curr_gain
[i
] & 0x0070) >> 4;
5038 target
.txgm
[i
] = (curr_gain
[i
] & 0x0380) >> 7;
5044 index
[0] = (b43_phy_read(dev
, B43_NPHY_C1_TXPCTL_STAT
) &
5045 B43_NPHY_TXPCTL_STAT_BIDX
) >>
5046 B43_NPHY_TXPCTL_STAT_BIDX_SHIFT
;
5047 index
[1] = (b43_phy_read(dev
, B43_NPHY_C2_TXPCTL_STAT
) &
5048 B43_NPHY_TXPCTL_STAT_BIDX
) >>
5049 B43_NPHY_TXPCTL_STAT_BIDX_SHIFT
;
5051 for (i
= 0; i
< 2; ++i
) {
5052 table
= b43_nphy_get_tx_gain_table(dev
);
5056 if (dev
->phy
.rev
>= 7) {
5057 target
.ipa
[i
] = (table
[index
[i
]] >> 16) & 0x7;
5058 target
.pad
[i
] = (table
[index
[i
]] >> 19) & 0x1F;
5059 target
.pga
[i
] = (table
[index
[i
]] >> 24) & 0xF;
5060 target
.txgm
[i
] = (table
[index
[i
]] >> 28) & 0x7;
5061 target
.tx_lpf
[i
] = (table
[index
[i
]] >> 31) & 0x1;
5062 } else if (dev
->phy
.rev
>= 3) {
5063 target
.ipa
[i
] = (table
[index
[i
]] >> 16) & 0xF;
5064 target
.pad
[i
] = (table
[index
[i
]] >> 20) & 0xF;
5065 target
.pga
[i
] = (table
[index
[i
]] >> 24) & 0xF;
5066 target
.txgm
[i
] = (table
[index
[i
]] >> 28) & 0xF;
5068 target
.ipa
[i
] = (table
[index
[i
]] >> 16) & 0x3;
5069 target
.pad
[i
] = (table
[index
[i
]] >> 18) & 0x3;
5070 target
.pga
[i
] = (table
[index
[i
]] >> 20) & 0x7;
5071 target
.txgm
[i
] = (table
[index
[i
]] >> 23) & 0x7;
5079 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhyCleanup */
5080 static void b43_nphy_tx_cal_phy_cleanup(struct b43_wldev
*dev
)
5082 u16
*regs
= dev
->phy
.n
->tx_rx_cal_phy_saveregs
;
5084 if (dev
->phy
.rev
>= 3) {
5085 b43_phy_write(dev
, B43_NPHY_AFECTL_C1
, regs
[0]);
5086 b43_phy_write(dev
, B43_NPHY_AFECTL_C2
, regs
[1]);
5087 b43_phy_write(dev
, B43_NPHY_AFECTL_OVER1
, regs
[2]);
5088 b43_phy_write(dev
, B43_NPHY_AFECTL_OVER
, regs
[3]);
5089 b43_phy_write(dev
, B43_NPHY_BBCFG
, regs
[4]);
5090 b43_ntab_write(dev
, B43_NTAB16(8, 3), regs
[5]);
5091 b43_ntab_write(dev
, B43_NTAB16(8, 19), regs
[6]);
5092 b43_phy_write(dev
, B43_NPHY_RFCTL_INTC1
, regs
[7]);
5093 b43_phy_write(dev
, B43_NPHY_RFCTL_INTC2
, regs
[8]);
5094 b43_phy_write(dev
, B43_NPHY_PAPD_EN0
, regs
[9]);
5095 b43_phy_write(dev
, B43_NPHY_PAPD_EN1
, regs
[10]);
5096 b43_nphy_reset_cca(dev
);
5098 b43_phy_maskset(dev
, B43_NPHY_AFECTL_C1
, 0x0FFF, regs
[0]);
5099 b43_phy_maskset(dev
, B43_NPHY_AFECTL_C2
, 0x0FFF, regs
[1]);
5100 b43_phy_write(dev
, B43_NPHY_AFECTL_OVER
, regs
[2]);
5101 b43_ntab_write(dev
, B43_NTAB16(8, 2), regs
[3]);
5102 b43_ntab_write(dev
, B43_NTAB16(8, 18), regs
[4]);
5103 b43_phy_write(dev
, B43_NPHY_RFCTL_INTC1
, regs
[5]);
5104 b43_phy_write(dev
, B43_NPHY_RFCTL_INTC2
, regs
[6]);
5108 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhySetup */
5109 static void b43_nphy_tx_cal_phy_setup(struct b43_wldev
*dev
)
5111 struct b43_phy
*phy
= &dev
->phy
;
5112 struct b43_phy_n
*nphy
= dev
->phy
.n
;
5113 u16
*regs
= dev
->phy
.n
->tx_rx_cal_phy_saveregs
;
5116 regs
[0] = b43_phy_read(dev
, B43_NPHY_AFECTL_C1
);
5117 regs
[1] = b43_phy_read(dev
, B43_NPHY_AFECTL_C2
);
5118 if (dev
->phy
.rev
>= 3) {
5119 b43_phy_maskset(dev
, B43_NPHY_AFECTL_C1
, 0xF0FF, 0x0A00);
5120 b43_phy_maskset(dev
, B43_NPHY_AFECTL_C2
, 0xF0FF, 0x0A00);
5122 tmp
= b43_phy_read(dev
, B43_NPHY_AFECTL_OVER1
);
5124 b43_phy_write(dev
, B43_NPHY_AFECTL_OVER1
, tmp
| 0x0600);
5126 tmp
= b43_phy_read(dev
, B43_NPHY_AFECTL_OVER
);
5128 b43_phy_write(dev
, B43_NPHY_AFECTL_OVER
, tmp
| 0x0600);
5130 regs
[4] = b43_phy_read(dev
, B43_NPHY_BBCFG
);
5131 b43_phy_mask(dev
, B43_NPHY_BBCFG
,
5132 ~B43_NPHY_BBCFG_RSTRX
& 0xFFFF);
5134 tmp
= b43_ntab_read(dev
, B43_NTAB16(8, 3));
5136 b43_ntab_write(dev
, B43_NTAB16(8, 3), 0);
5138 tmp
= b43_ntab_read(dev
, B43_NTAB16(8, 19));
5140 b43_ntab_write(dev
, B43_NTAB16(8, 19), 0);
5141 regs
[7] = b43_phy_read(dev
, B43_NPHY_RFCTL_INTC1
);
5142 regs
[8] = b43_phy_read(dev
, B43_NPHY_RFCTL_INTC2
);
5144 if (!nphy
->use_int_tx_iq_lo_cal
)
5145 b43_nphy_rf_ctl_intc_override(dev
, N_INTC_OVERRIDE_PA
,
5148 b43_nphy_rf_ctl_intc_override(dev
, N_INTC_OVERRIDE_PA
,
5150 b43_nphy_rf_ctl_intc_override(dev
, N_INTC_OVERRIDE_TRSW
, 2, 1);
5151 b43_nphy_rf_ctl_intc_override(dev
, N_INTC_OVERRIDE_TRSW
, 8, 2);
5153 regs
[9] = b43_phy_read(dev
, B43_NPHY_PAPD_EN0
);
5154 regs
[10] = b43_phy_read(dev
, B43_NPHY_PAPD_EN1
);
5155 b43_phy_mask(dev
, B43_NPHY_PAPD_EN0
, ~0x0001);
5156 b43_phy_mask(dev
, B43_NPHY_PAPD_EN1
, ~0x0001);
5158 tmp
= b43_nphy_read_lpf_ctl(dev
, 0);
5160 b43_nphy_rf_ctl_override_rev19(dev
, 0x80, tmp
, 0, false,
5162 else if (phy
->rev
>= 7)
5163 b43_nphy_rf_ctl_override_rev7(dev
, 0x80, tmp
, 0, false,
5166 if (nphy
->use_int_tx_iq_lo_cal
&& true /* FIXME */) {
5167 if (phy
->rev
>= 19) {
5168 b43_nphy_rf_ctl_override_rev19(dev
, 0x8, 0, 0x3,
5170 } else if (phy
->rev
>= 8) {
5171 b43_nphy_rf_ctl_override_rev7(dev
, 0x8, 0, 0x3,
5173 } else if (phy
->rev
== 7) {
5174 b43_radio_maskset(dev
, R2057_OVR_REG0
, 1 << 4, 1 << 4);
5175 if (b43_current_band(dev
->wl
) == IEEE80211_BAND_2GHZ
) {
5176 b43_radio_maskset(dev
, R2057_PAD2G_TUNE_PUS_CORE0
, ~1, 0);
5177 b43_radio_maskset(dev
, R2057_PAD2G_TUNE_PUS_CORE1
, ~1, 0);
5179 b43_radio_maskset(dev
, R2057_IPA5G_CASCOFFV_PU_CORE0
, ~1, 0);
5180 b43_radio_maskset(dev
, R2057_IPA5G_CASCOFFV_PU_CORE1
, ~1, 0);
5185 b43_phy_maskset(dev
, B43_NPHY_AFECTL_C1
, 0x0FFF, 0xA000);
5186 b43_phy_maskset(dev
, B43_NPHY_AFECTL_C2
, 0x0FFF, 0xA000);
5187 tmp
= b43_phy_read(dev
, B43_NPHY_AFECTL_OVER
);
5189 b43_phy_write(dev
, B43_NPHY_AFECTL_OVER
, tmp
| 0x3000);
5190 tmp
= b43_ntab_read(dev
, B43_NTAB16(8, 2));
5193 b43_ntab_write(dev
, B43_NTAB16(8, 2), tmp
);
5194 tmp
= b43_ntab_read(dev
, B43_NTAB16(8, 18));
5197 b43_ntab_write(dev
, B43_NTAB16(8, 18), tmp
);
5198 regs
[5] = b43_phy_read(dev
, B43_NPHY_RFCTL_INTC1
);
5199 regs
[6] = b43_phy_read(dev
, B43_NPHY_RFCTL_INTC2
);
5200 if (b43_current_band(dev
->wl
) == IEEE80211_BAND_5GHZ
)
5204 b43_phy_write(dev
, B43_NPHY_RFCTL_INTC1
, tmp
);
5205 b43_phy_write(dev
, B43_NPHY_RFCTL_INTC2
, tmp
);
5209 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SaveCal */
5210 static void b43_nphy_save_cal(struct b43_wldev
*dev
)
5212 struct b43_phy
*phy
= &dev
->phy
;
5213 struct b43_phy_n
*nphy
= dev
->phy
.n
;
5215 struct b43_phy_n_iq_comp
*rxcal_coeffs
= NULL
;
5216 u16
*txcal_radio_regs
= NULL
;
5217 struct b43_chanspec
*iqcal_chanspec
;
5220 if (nphy
->hang_avoid
)
5221 b43_nphy_stay_in_carrier_search(dev
, 1);
5223 if (b43_current_band(dev
->wl
) == IEEE80211_BAND_2GHZ
) {
5224 rxcal_coeffs
= &nphy
->cal_cache
.rxcal_coeffs_2G
;
5225 txcal_radio_regs
= nphy
->cal_cache
.txcal_radio_regs_2G
;
5226 iqcal_chanspec
= &nphy
->iqcal_chanspec_2G
;
5227 table
= nphy
->cal_cache
.txcal_coeffs_2G
;
5229 rxcal_coeffs
= &nphy
->cal_cache
.rxcal_coeffs_5G
;
5230 txcal_radio_regs
= nphy
->cal_cache
.txcal_radio_regs_5G
;
5231 iqcal_chanspec
= &nphy
->iqcal_chanspec_5G
;
5232 table
= nphy
->cal_cache
.txcal_coeffs_5G
;
5235 b43_nphy_rx_iq_coeffs(dev
, false, rxcal_coeffs
);
5236 /* TODO use some definitions */
5237 if (phy
->rev
>= 19) {
5239 } else if (phy
->rev
>= 7) {
5240 txcal_radio_regs
[0] = b43_radio_read(dev
,
5241 R2057_TX0_LOFT_FINE_I
);
5242 txcal_radio_regs
[1] = b43_radio_read(dev
,
5243 R2057_TX0_LOFT_FINE_Q
);
5244 txcal_radio_regs
[4] = b43_radio_read(dev
,
5245 R2057_TX0_LOFT_COARSE_I
);
5246 txcal_radio_regs
[5] = b43_radio_read(dev
,
5247 R2057_TX0_LOFT_COARSE_Q
);
5248 txcal_radio_regs
[2] = b43_radio_read(dev
,
5249 R2057_TX1_LOFT_FINE_I
);
5250 txcal_radio_regs
[3] = b43_radio_read(dev
,
5251 R2057_TX1_LOFT_FINE_Q
);
5252 txcal_radio_regs
[6] = b43_radio_read(dev
,
5253 R2057_TX1_LOFT_COARSE_I
);
5254 txcal_radio_regs
[7] = b43_radio_read(dev
,
5255 R2057_TX1_LOFT_COARSE_Q
);
5256 } else if (phy
->rev
>= 3) {
5257 txcal_radio_regs
[0] = b43_radio_read(dev
, 0x2021);
5258 txcal_radio_regs
[1] = b43_radio_read(dev
, 0x2022);
5259 txcal_radio_regs
[2] = b43_radio_read(dev
, 0x3021);
5260 txcal_radio_regs
[3] = b43_radio_read(dev
, 0x3022);
5261 txcal_radio_regs
[4] = b43_radio_read(dev
, 0x2023);
5262 txcal_radio_regs
[5] = b43_radio_read(dev
, 0x2024);
5263 txcal_radio_regs
[6] = b43_radio_read(dev
, 0x3023);
5264 txcal_radio_regs
[7] = b43_radio_read(dev
, 0x3024);
5266 txcal_radio_regs
[0] = b43_radio_read(dev
, 0x8B);
5267 txcal_radio_regs
[1] = b43_radio_read(dev
, 0xBA);
5268 txcal_radio_regs
[2] = b43_radio_read(dev
, 0x8D);
5269 txcal_radio_regs
[3] = b43_radio_read(dev
, 0xBC);
5271 iqcal_chanspec
->center_freq
= dev
->phy
.chandef
->chan
->center_freq
;
5272 iqcal_chanspec
->channel_type
=
5273 cfg80211_get_chandef_type(dev
->phy
.chandef
);
5274 b43_ntab_read_bulk(dev
, B43_NTAB16(15, 80), 8, table
);
5276 if (nphy
->hang_avoid
)
5277 b43_nphy_stay_in_carrier_search(dev
, 0);
5280 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreCal */
5281 static void b43_nphy_restore_cal(struct b43_wldev
*dev
)
5283 struct b43_phy
*phy
= &dev
->phy
;
5284 struct b43_phy_n
*nphy
= dev
->phy
.n
;
5291 u16
*txcal_radio_regs
= NULL
;
5292 struct b43_phy_n_iq_comp
*rxcal_coeffs
= NULL
;
5294 if (b43_current_band(dev
->wl
) == IEEE80211_BAND_2GHZ
) {
5295 if (!nphy
->iqcal_chanspec_2G
.center_freq
)
5297 table
= nphy
->cal_cache
.txcal_coeffs_2G
;
5298 loft
= &nphy
->cal_cache
.txcal_coeffs_2G
[5];
5300 if (!nphy
->iqcal_chanspec_5G
.center_freq
)
5302 table
= nphy
->cal_cache
.txcal_coeffs_5G
;
5303 loft
= &nphy
->cal_cache
.txcal_coeffs_5G
[5];
5306 b43_ntab_write_bulk(dev
, B43_NTAB16(15, 80), 4, table
);
5308 for (i
= 0; i
< 4; i
++) {
5309 if (dev
->phy
.rev
>= 3)
5315 b43_ntab_write_bulk(dev
, B43_NTAB16(15, 88), 4, coef
);
5316 b43_ntab_write_bulk(dev
, B43_NTAB16(15, 85), 2, loft
);
5317 b43_ntab_write_bulk(dev
, B43_NTAB16(15, 93), 2, loft
);
5319 if (dev
->phy
.rev
< 2)
5320 b43_nphy_tx_iq_workaround(dev
);
5322 if (b43_current_band(dev
->wl
) == IEEE80211_BAND_2GHZ
) {
5323 txcal_radio_regs
= nphy
->cal_cache
.txcal_radio_regs_2G
;
5324 rxcal_coeffs
= &nphy
->cal_cache
.rxcal_coeffs_2G
;
5326 txcal_radio_regs
= nphy
->cal_cache
.txcal_radio_regs_5G
;
5327 rxcal_coeffs
= &nphy
->cal_cache
.rxcal_coeffs_5G
;
5330 /* TODO use some definitions */
5331 if (phy
->rev
>= 19) {
5333 } else if (phy
->rev
>= 7) {
5334 b43_radio_write(dev
, R2057_TX0_LOFT_FINE_I
,
5335 txcal_radio_regs
[0]);
5336 b43_radio_write(dev
, R2057_TX0_LOFT_FINE_Q
,
5337 txcal_radio_regs
[1]);
5338 b43_radio_write(dev
, R2057_TX0_LOFT_COARSE_I
,
5339 txcal_radio_regs
[4]);
5340 b43_radio_write(dev
, R2057_TX0_LOFT_COARSE_Q
,
5341 txcal_radio_regs
[5]);
5342 b43_radio_write(dev
, R2057_TX1_LOFT_FINE_I
,
5343 txcal_radio_regs
[2]);
5344 b43_radio_write(dev
, R2057_TX1_LOFT_FINE_Q
,
5345 txcal_radio_regs
[3]);
5346 b43_radio_write(dev
, R2057_TX1_LOFT_COARSE_I
,
5347 txcal_radio_regs
[6]);
5348 b43_radio_write(dev
, R2057_TX1_LOFT_COARSE_Q
,
5349 txcal_radio_regs
[7]);
5350 } else if (phy
->rev
>= 3) {
5351 b43_radio_write(dev
, 0x2021, txcal_radio_regs
[0]);
5352 b43_radio_write(dev
, 0x2022, txcal_radio_regs
[1]);
5353 b43_radio_write(dev
, 0x3021, txcal_radio_regs
[2]);
5354 b43_radio_write(dev
, 0x3022, txcal_radio_regs
[3]);
5355 b43_radio_write(dev
, 0x2023, txcal_radio_regs
[4]);
5356 b43_radio_write(dev
, 0x2024, txcal_radio_regs
[5]);
5357 b43_radio_write(dev
, 0x3023, txcal_radio_regs
[6]);
5358 b43_radio_write(dev
, 0x3024, txcal_radio_regs
[7]);
5360 b43_radio_write(dev
, 0x8B, txcal_radio_regs
[0]);
5361 b43_radio_write(dev
, 0xBA, txcal_radio_regs
[1]);
5362 b43_radio_write(dev
, 0x8D, txcal_radio_regs
[2]);
5363 b43_radio_write(dev
, 0xBC, txcal_radio_regs
[3]);
5365 b43_nphy_rx_iq_coeffs(dev
, true, rxcal_coeffs
);
5368 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalTxIqlo */
5369 static int b43_nphy_cal_tx_iq_lo(struct b43_wldev
*dev
,
5370 struct nphy_txgains target
,
5371 bool full
, bool mphase
)
5373 struct b43_phy
*phy
= &dev
->phy
;
5374 struct b43_phy_n
*nphy
= dev
->phy
.n
;
5380 u16 tmp
, core
, type
, count
, max
, numb
, last
= 0, cmd
;
5388 struct nphy_iqcal_params params
[2];
5389 bool updated
[2] = { };
5391 b43_nphy_stay_in_carrier_search(dev
, true);
5393 if (dev
->phy
.rev
>= 4) {
5394 avoid
= nphy
->hang_avoid
;
5395 nphy
->hang_avoid
= false;
5398 b43_ntab_read_bulk(dev
, B43_NTAB16(7, 0x110), 2, save
);
5400 for (i
= 0; i
< 2; i
++) {
5401 b43_nphy_iq_cal_gain_params(dev
, i
, target
, ¶ms
[i
]);
5402 gain
[i
] = params
[i
].cal_gain
;
5405 b43_ntab_write_bulk(dev
, B43_NTAB16(7, 0x110), 2, gain
);
5407 b43_nphy_tx_cal_radio_setup(dev
);
5408 b43_nphy_tx_cal_phy_setup(dev
);
5410 phy6or5x
= dev
->phy
.rev
>= 6 ||
5411 (dev
->phy
.rev
== 5 && nphy
->ipa2g_on
&&
5412 b43_current_band(dev
->wl
) == IEEE80211_BAND_2GHZ
);
5414 if (b43_is_40mhz(dev
)) {
5415 b43_ntab_write_bulk(dev
, B43_NTAB16(15, 0), 18,
5416 tbl_tx_iqlo_cal_loft_ladder_40
);
5417 b43_ntab_write_bulk(dev
, B43_NTAB16(15, 32), 18,
5418 tbl_tx_iqlo_cal_iqimb_ladder_40
);
5420 b43_ntab_write_bulk(dev
, B43_NTAB16(15, 0), 18,
5421 tbl_tx_iqlo_cal_loft_ladder_20
);
5422 b43_ntab_write_bulk(dev
, B43_NTAB16(15, 32), 18,
5423 tbl_tx_iqlo_cal_iqimb_ladder_20
);
5427 if (phy
->rev
>= 19) {
5429 } else if (phy
->rev
>= 7) {
5430 b43_phy_write(dev
, B43_NPHY_IQLOCAL_CMDGCTL
, 0x8AD9);
5432 b43_phy_write(dev
, B43_NPHY_IQLOCAL_CMDGCTL
, 0x8AA9);
5435 if (!b43_is_40mhz(dev
))
5440 if (nphy
->mphase_cal_phase_id
> 2)
5441 b43_nphy_run_samples(dev
, (b43_is_40mhz(dev
) ? 40 : 20) * 8,
5442 0xFFFF, 0, true, false, false);
5444 error
= b43_nphy_tx_tone(dev
, freq
, 250, true, false, false);
5447 if (nphy
->mphase_cal_phase_id
> 2) {
5448 table
= nphy
->mphase_txcal_bestcoeffs
;
5450 if (dev
->phy
.rev
< 3)
5453 if (!full
&& nphy
->txiqlocal_coeffsvalid
) {
5454 table
= nphy
->txiqlocal_bestc
;
5456 if (dev
->phy
.rev
< 3)
5460 if (dev
->phy
.rev
>= 3) {
5461 table
= tbl_tx_iqlo_cal_startcoefs_nphyrev3
;
5462 length
= B43_NTAB_TX_IQLO_CAL_STARTCOEFS_REV3
;
5464 table
= tbl_tx_iqlo_cal_startcoefs
;
5465 length
= B43_NTAB_TX_IQLO_CAL_STARTCOEFS
;
5470 b43_ntab_write_bulk(dev
, B43_NTAB16(15, 64), length
, table
);
5473 if (dev
->phy
.rev
>= 3)
5474 max
= B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL_REV3
;
5476 max
= B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL
;
5478 if (dev
->phy
.rev
>= 3)
5479 max
= B43_NTAB_TX_IQLO_CAL_CMDS_RECAL_REV3
;
5481 max
= B43_NTAB_TX_IQLO_CAL_CMDS_RECAL
;
5485 count
= nphy
->mphase_txcal_cmdidx
;
5487 (u16
)(count
+ nphy
->mphase_txcal_numcmds
));
5493 for (; count
< numb
; count
++) {
5495 if (dev
->phy
.rev
>= 3)
5496 cmd
= tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3
[count
];
5498 cmd
= tbl_tx_iqlo_cal_cmds_fullcal
[count
];
5500 if (dev
->phy
.rev
>= 3)
5501 cmd
= tbl_tx_iqlo_cal_cmds_recal_nphyrev3
[count
];
5503 cmd
= tbl_tx_iqlo_cal_cmds_recal
[count
];
5506 core
= (cmd
& 0x3000) >> 12;
5507 type
= (cmd
& 0x0F00) >> 8;
5509 if (phy6or5x
&& updated
[core
] == 0) {
5510 b43_nphy_update_tx_cal_ladder(dev
, core
);
5511 updated
[core
] = true;
5514 tmp
= (params
[core
].ncorr
[type
] << 8) | 0x66;
5515 b43_phy_write(dev
, B43_NPHY_IQLOCAL_CMDNNUM
, tmp
);
5517 if (type
== 1 || type
== 3 || type
== 4) {
5518 buffer
[0] = b43_ntab_read(dev
,
5519 B43_NTAB16(15, 69 + core
));
5520 diq_start
= buffer
[0];
5522 b43_ntab_write(dev
, B43_NTAB16(15, 69 + core
),
5526 b43_phy_write(dev
, B43_NPHY_IQLOCAL_CMD
, cmd
);
5527 for (i
= 0; i
< 2000; i
++) {
5528 tmp
= b43_phy_read(dev
, B43_NPHY_IQLOCAL_CMD
);
5534 b43_ntab_read_bulk(dev
, B43_NTAB16(15, 96), length
,
5536 b43_ntab_write_bulk(dev
, B43_NTAB16(15, 64), length
,
5539 if (type
== 1 || type
== 3 || type
== 4)
5540 buffer
[0] = diq_start
;
5544 nphy
->mphase_txcal_cmdidx
= (numb
>= max
) ? 0 : numb
;
5546 last
= (dev
->phy
.rev
< 3) ? 6 : 7;
5548 if (!mphase
|| nphy
->mphase_cal_phase_id
== last
) {
5549 b43_ntab_write_bulk(dev
, B43_NTAB16(15, 96), 4, buffer
);
5550 b43_ntab_read_bulk(dev
, B43_NTAB16(15, 80), 4, buffer
);
5551 if (dev
->phy
.rev
< 3) {
5557 b43_ntab_write_bulk(dev
, B43_NTAB16(15, 88), 4,
5559 b43_ntab_read_bulk(dev
, B43_NTAB16(15, 101), 2,
5561 b43_ntab_write_bulk(dev
, B43_NTAB16(15, 85), 2,
5563 b43_ntab_write_bulk(dev
, B43_NTAB16(15, 93), 2,
5566 if (dev
->phy
.rev
< 3)
5568 b43_ntab_read_bulk(dev
, B43_NTAB16(15, 96), length
,
5569 nphy
->txiqlocal_bestc
);
5570 nphy
->txiqlocal_coeffsvalid
= true;
5571 nphy
->txiqlocal_chanspec
.center_freq
=
5572 phy
->chandef
->chan
->center_freq
;
5573 nphy
->txiqlocal_chanspec
.channel_type
=
5574 cfg80211_get_chandef_type(phy
->chandef
);
5577 if (dev
->phy
.rev
< 3)
5579 b43_ntab_read_bulk(dev
, B43_NTAB16(15, 96), length
,
5580 nphy
->mphase_txcal_bestcoeffs
);
5583 b43_nphy_stop_playback(dev
);
5584 b43_phy_write(dev
, B43_NPHY_IQLOCAL_CMDGCTL
, 0);
5587 b43_nphy_tx_cal_phy_cleanup(dev
);
5588 b43_ntab_write_bulk(dev
, B43_NTAB16(7, 0x110), 2, save
);
5590 if (dev
->phy
.rev
< 2 && (!mphase
|| nphy
->mphase_cal_phase_id
== last
))
5591 b43_nphy_tx_iq_workaround(dev
);
5593 if (dev
->phy
.rev
>= 4)
5594 nphy
->hang_avoid
= avoid
;
5596 b43_nphy_stay_in_carrier_search(dev
, false);
5601 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ReapplyTxCalCoeffs */
5602 static void b43_nphy_reapply_tx_cal_coeffs(struct b43_wldev
*dev
)
5604 struct b43_phy_n
*nphy
= dev
->phy
.n
;
5609 if (!nphy
->txiqlocal_coeffsvalid
||
5610 nphy
->txiqlocal_chanspec
.center_freq
!= dev
->phy
.chandef
->chan
->center_freq
||
5611 nphy
->txiqlocal_chanspec
.channel_type
!= cfg80211_get_chandef_type(dev
->phy
.chandef
))
5614 b43_ntab_read_bulk(dev
, B43_NTAB16(15, 80), 7, buffer
);
5615 for (i
= 0; i
< 4; i
++) {
5616 if (buffer
[i
] != nphy
->txiqlocal_bestc
[i
]) {
5623 b43_ntab_write_bulk(dev
, B43_NTAB16(15, 80), 4,
5624 nphy
->txiqlocal_bestc
);
5625 for (i
= 0; i
< 4; i
++)
5627 b43_ntab_write_bulk(dev
, B43_NTAB16(15, 88), 4,
5629 b43_ntab_write_bulk(dev
, B43_NTAB16(15, 85), 2,
5630 &nphy
->txiqlocal_bestc
[5]);
5631 b43_ntab_write_bulk(dev
, B43_NTAB16(15, 93), 2,
5632 &nphy
->txiqlocal_bestc
[5]);
5636 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIqRev2 */
5637 static int b43_nphy_rev2_cal_rx_iq(struct b43_wldev
*dev
,
5638 struct nphy_txgains target
, u8 type
, bool debug
)
5640 struct b43_phy_n
*nphy
= dev
->phy
.n
;
5645 u16
uninitialized_var(cur_hpf1
), uninitialized_var(cur_hpf2
), cur_lna
;
5647 enum ieee80211_band band
;
5651 u16 lna
[3] = { 3, 3, 1 };
5652 u16 hpf1
[3] = { 7, 2, 0 };
5653 u16 hpf2
[3] = { 2, 0, 0 };
5657 struct nphy_iqcal_params cal_params
[2];
5658 struct nphy_iq_est est
;
5660 bool playtone
= true;
5663 b43_nphy_stay_in_carrier_search(dev
, 1);
5665 if (dev
->phy
.rev
< 2)
5666 b43_nphy_reapply_tx_cal_coeffs(dev
);
5667 b43_ntab_read_bulk(dev
, B43_NTAB16(7, 0x110), 2, gain_save
);
5668 for (i
= 0; i
< 2; i
++) {
5669 b43_nphy_iq_cal_gain_params(dev
, i
, target
, &cal_params
[i
]);
5670 cal_gain
[i
] = cal_params
[i
].cal_gain
;
5672 b43_ntab_write_bulk(dev
, B43_NTAB16(7, 0x110), 2, cal_gain
);
5674 for (i
= 0; i
< 2; i
++) {
5676 rfctl
[0] = B43_NPHY_RFCTL_INTC1
;
5677 rfctl
[1] = B43_NPHY_RFCTL_INTC2
;
5678 afectl_core
= B43_NPHY_AFECTL_C1
;
5680 rfctl
[0] = B43_NPHY_RFCTL_INTC2
;
5681 rfctl
[1] = B43_NPHY_RFCTL_INTC1
;
5682 afectl_core
= B43_NPHY_AFECTL_C2
;
5685 tmp
[1] = b43_phy_read(dev
, B43_NPHY_RFSEQCA
);
5686 tmp
[2] = b43_phy_read(dev
, afectl_core
);
5687 tmp
[3] = b43_phy_read(dev
, B43_NPHY_AFECTL_OVER
);
5688 tmp
[4] = b43_phy_read(dev
, rfctl
[0]);
5689 tmp
[5] = b43_phy_read(dev
, rfctl
[1]);
5691 b43_phy_maskset(dev
, B43_NPHY_RFSEQCA
,
5692 ~B43_NPHY_RFSEQCA_RXDIS
& 0xFFFF,
5693 ((1 - i
) << B43_NPHY_RFSEQCA_RXDIS_SHIFT
));
5694 b43_phy_maskset(dev
, B43_NPHY_RFSEQCA
, ~B43_NPHY_RFSEQCA_TXEN
,
5696 b43_phy_set(dev
, afectl_core
, 0x0006);
5697 b43_phy_set(dev
, B43_NPHY_AFECTL_OVER
, 0x0006);
5699 band
= b43_current_band(dev
->wl
);
5701 if (nphy
->rxcalparams
& 0xFF000000) {
5702 if (band
== IEEE80211_BAND_5GHZ
)
5703 b43_phy_write(dev
, rfctl
[0], 0x140);
5705 b43_phy_write(dev
, rfctl
[0], 0x110);
5707 if (band
== IEEE80211_BAND_5GHZ
)
5708 b43_phy_write(dev
, rfctl
[0], 0x180);
5710 b43_phy_write(dev
, rfctl
[0], 0x120);
5713 if (band
== IEEE80211_BAND_5GHZ
)
5714 b43_phy_write(dev
, rfctl
[1], 0x148);
5716 b43_phy_write(dev
, rfctl
[1], 0x114);
5718 if (nphy
->rxcalparams
& 0x10000) {
5719 b43_radio_maskset(dev
, B2055_C1_GENSPARE2
, 0xFC,
5721 b43_radio_maskset(dev
, B2055_C2_GENSPARE2
, 0xFC,
5725 for (j
= 0; j
< 4; j
++) {
5731 if (power
[1] > 10000) {
5736 if (power
[0] > 10000) {
5746 cur_lna
= lna
[index
];
5747 cur_hpf1
= hpf1
[index
];
5748 cur_hpf2
= hpf2
[index
];
5749 cur_hpf
+= desired
- hweight32(power
[index
]);
5750 cur_hpf
= clamp_val(cur_hpf
, 0, 10);
5757 tmp
[0] = ((cur_hpf2
<< 8) | (cur_hpf1
<< 4) |
5759 b43_nphy_rf_ctl_override(dev
, 0x400, tmp
[0], 3,
5761 b43_nphy_force_rf_sequence(dev
, B43_RFSEQ_RESET2RX
);
5762 b43_nphy_stop_playback(dev
);
5765 ret
= b43_nphy_tx_tone(dev
, 4000,
5766 (nphy
->rxcalparams
& 0xFFFF),
5767 false, false, true);
5770 b43_nphy_run_samples(dev
, 160, 0xFFFF, 0, false,
5776 b43_nphy_rx_iq_est(dev
, &est
, 1024, 32,
5785 power
[i
] = ((real
+ imag
) / 1024) + 1;
5787 b43_nphy_calc_rx_iq_comp(dev
, 1 << i
);
5789 b43_nphy_stop_playback(dev
);
5796 b43_radio_mask(dev
, B2055_C1_GENSPARE2
, 0xFC);
5797 b43_radio_mask(dev
, B2055_C2_GENSPARE2
, 0xFC);
5798 b43_phy_write(dev
, rfctl
[1], tmp
[5]);
5799 b43_phy_write(dev
, rfctl
[0], tmp
[4]);
5800 b43_phy_write(dev
, B43_NPHY_AFECTL_OVER
, tmp
[3]);
5801 b43_phy_write(dev
, afectl_core
, tmp
[2]);
5802 b43_phy_write(dev
, B43_NPHY_RFSEQCA
, tmp
[1]);
5808 b43_nphy_rf_ctl_override(dev
, 0x400, 0, 3, true);
5809 b43_nphy_force_rf_sequence(dev
, B43_RFSEQ_RESET2RX
);
5810 b43_ntab_write_bulk(dev
, B43_NTAB16(7, 0x110), 2, gain_save
);
5812 b43_nphy_stay_in_carrier_search(dev
, 0);
5817 static int b43_nphy_rev3_cal_rx_iq(struct b43_wldev
*dev
,
5818 struct nphy_txgains target
, u8 type
, bool debug
)
5823 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIq */
5824 static int b43_nphy_cal_rx_iq(struct b43_wldev
*dev
,
5825 struct nphy_txgains target
, u8 type
, bool debug
)
5827 if (dev
->phy
.rev
>= 7)
5830 if (dev
->phy
.rev
>= 3)
5831 return b43_nphy_rev3_cal_rx_iq(dev
, target
, type
, debug
);
5833 return b43_nphy_rev2_cal_rx_iq(dev
, target
, type
, debug
);
5836 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCoreSetState */
5837 static void b43_nphy_set_rx_core_state(struct b43_wldev
*dev
, u8 mask
)
5839 struct b43_phy
*phy
= &dev
->phy
;
5840 struct b43_phy_n
*nphy
= phy
->n
;
5841 /* u16 buf[16]; it's rev3+ */
5843 nphy
->phyrxchain
= mask
;
5845 if (0 /* FIXME clk */)
5848 b43_mac_suspend(dev
);
5850 if (nphy
->hang_avoid
)
5851 b43_nphy_stay_in_carrier_search(dev
, true);
5853 b43_phy_maskset(dev
, B43_NPHY_RFSEQCA
, ~B43_NPHY_RFSEQCA_RXEN
,
5854 (mask
& 0x3) << B43_NPHY_RFSEQCA_RXEN_SHIFT
);
5856 if ((mask
& 0x3) != 0x3) {
5857 b43_phy_write(dev
, B43_NPHY_HPANT_SWTHRES
, 1);
5858 if (dev
->phy
.rev
>= 3) {
5862 b43_phy_write(dev
, B43_NPHY_HPANT_SWTHRES
, 0x1E);
5863 if (dev
->phy
.rev
>= 3) {
5868 b43_nphy_force_rf_sequence(dev
, B43_RFSEQ_RESET2RX
);
5870 if (nphy
->hang_avoid
)
5871 b43_nphy_stay_in_carrier_search(dev
, false);
5873 b43_mac_enable(dev
);
5876 /**************************************************
5878 **************************************************/
5880 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MIMOConfig */
5881 static void b43_nphy_update_mimo_config(struct b43_wldev
*dev
, s32 preamble
)
5883 u16 mimocfg
= b43_phy_read(dev
, B43_NPHY_MIMOCFG
);
5885 mimocfg
|= B43_NPHY_MIMOCFG_AUTO
;
5887 mimocfg
|= B43_NPHY_MIMOCFG_GFMIX
;
5889 mimocfg
&= ~B43_NPHY_MIMOCFG_GFMIX
;
5891 b43_phy_write(dev
, B43_NPHY_MIMOCFG
, mimocfg
);
5894 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BPHYInit */
5895 static void b43_nphy_bphy_init(struct b43_wldev
*dev
)
5901 for (i
= 0; i
< 16; i
++) {
5902 b43_phy_write(dev
, B43_PHY_N_BMODE(0x88 + i
), val
);
5906 for (i
= 0; i
< 16; i
++) {
5907 b43_phy_write(dev
, B43_PHY_N_BMODE(0x98 + i
), val
);
5910 b43_phy_write(dev
, B43_PHY_N_BMODE(0x38), 0x668);
5913 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SuperSwitchInit */
5914 static void b43_nphy_superswitch_init(struct b43_wldev
*dev
, bool init
)
5916 if (dev
->phy
.rev
>= 7)
5919 if (dev
->phy
.rev
>= 3) {
5922 if (0 /* FIXME */) {
5923 b43_ntab_write(dev
, B43_NTAB16(9, 2), 0x211);
5924 b43_ntab_write(dev
, B43_NTAB16(9, 3), 0x222);
5925 b43_ntab_write(dev
, B43_NTAB16(9, 8), 0x144);
5926 b43_ntab_write(dev
, B43_NTAB16(9, 12), 0x188);
5929 b43_phy_write(dev
, B43_NPHY_GPIO_LOOEN
, 0);
5930 b43_phy_write(dev
, B43_NPHY_GPIO_HIOEN
, 0);
5932 switch (dev
->dev
->bus_type
) {
5933 #ifdef CONFIG_B43_BCMA
5935 bcma_chipco_gpio_control(&dev
->dev
->bdev
->bus
->drv_cc
,
5939 #ifdef CONFIG_B43_SSB
5941 ssb_chipco_gpio_control(&dev
->dev
->sdev
->bus
->chipco
,
5947 b43_maskset32(dev
, B43_MMIO_MACCTL
, ~B43_MACCTL_GPOUTSMSK
, 0);
5948 b43_maskset16(dev
, B43_MMIO_GPIO_MASK
, ~0, 0xFC00);
5949 b43_maskset16(dev
, B43_MMIO_GPIO_CONTROL
, (~0xFC00 & 0xFFFF),
5953 b43_phy_write(dev
, B43_NPHY_RFCTL_LUT_TRSW_LO1
, 0x2D8);
5954 b43_phy_write(dev
, B43_NPHY_RFCTL_LUT_TRSW_UP1
, 0x301);
5955 b43_phy_write(dev
, B43_NPHY_RFCTL_LUT_TRSW_LO2
, 0x2D8);
5956 b43_phy_write(dev
, B43_NPHY_RFCTL_LUT_TRSW_UP2
, 0x301);
5961 /* http://bcm-v4.sipsolutions.net/802.11/PHY/Init/N */
5962 static int b43_phy_initn(struct b43_wldev
*dev
)
5964 struct ssb_sprom
*sprom
= dev
->dev
->bus_sprom
;
5965 struct b43_phy
*phy
= &dev
->phy
;
5966 struct b43_phy_n
*nphy
= phy
->n
;
5968 struct nphy_txgains target
;
5970 enum ieee80211_band tmp2
;
5974 bool do_cal
= false;
5976 if ((dev
->phy
.rev
>= 3) &&
5977 (sprom
->boardflags_lo
& B43_BFL_EXTLNA
) &&
5978 (b43_current_band(dev
->wl
) == IEEE80211_BAND_2GHZ
)) {
5979 switch (dev
->dev
->bus_type
) {
5980 #ifdef CONFIG_B43_BCMA
5982 bcma_cc_set32(&dev
->dev
->bdev
->bus
->drv_cc
,
5983 BCMA_CC_CHIPCTL
, 0x40);
5986 #ifdef CONFIG_B43_SSB
5988 chipco_set32(&dev
->dev
->sdev
->bus
->chipco
,
5989 SSB_CHIPCO_CHIPCTL
, 0x40);
5994 nphy
->use_int_tx_iq_lo_cal
= b43_nphy_ipa(dev
) ||
5997 sprom
->boardflags2_hi
& B43_BFH2_INTERNDET_TXIQCAL
);
5998 nphy
->deaf_count
= 0;
5999 b43_nphy_tables_init(dev
);
6000 nphy
->crsminpwr_adjusted
= false;
6001 nphy
->noisevars_adjusted
= false;
6003 /* Clear all overrides */
6004 if (dev
->phy
.rev
>= 3) {
6005 b43_phy_write(dev
, B43_NPHY_TXF_40CO_B1S1
, 0);
6006 b43_phy_write(dev
, B43_NPHY_RFCTL_OVER
, 0);
6007 if (phy
->rev
>= 7) {
6008 b43_phy_write(dev
, B43_NPHY_REV7_RF_CTL_OVER3
, 0);
6009 b43_phy_write(dev
, B43_NPHY_REV7_RF_CTL_OVER4
, 0);
6010 b43_phy_write(dev
, B43_NPHY_REV7_RF_CTL_OVER5
, 0);
6011 b43_phy_write(dev
, B43_NPHY_REV7_RF_CTL_OVER6
, 0);
6013 if (phy
->rev
>= 19) {
6017 b43_phy_write(dev
, B43_NPHY_TXF_40CO_B1S0
, 0);
6018 b43_phy_write(dev
, B43_NPHY_TXF_40CO_B32S1
, 0);
6020 b43_phy_write(dev
, B43_NPHY_RFCTL_OVER
, 0);
6022 b43_phy_write(dev
, B43_NPHY_RFCTL_INTC1
, 0);
6023 b43_phy_write(dev
, B43_NPHY_RFCTL_INTC2
, 0);
6024 if (dev
->phy
.rev
< 6) {
6025 b43_phy_write(dev
, B43_NPHY_RFCTL_INTC3
, 0);
6026 b43_phy_write(dev
, B43_NPHY_RFCTL_INTC4
, 0);
6028 b43_phy_mask(dev
, B43_NPHY_RFSEQMODE
,
6029 ~(B43_NPHY_RFSEQMODE_CAOVER
|
6030 B43_NPHY_RFSEQMODE_TROVER
));
6031 if (dev
->phy
.rev
>= 3)
6032 b43_phy_write(dev
, B43_NPHY_AFECTL_OVER1
, 0);
6033 b43_phy_write(dev
, B43_NPHY_AFECTL_OVER
, 0);
6035 if (dev
->phy
.rev
<= 2) {
6036 tmp
= (dev
->phy
.rev
== 2) ? 0x3B : 0x40;
6037 b43_phy_maskset(dev
, B43_NPHY_BPHY_CTL3
,
6038 ~B43_NPHY_BPHY_CTL3_SCALE
,
6039 tmp
<< B43_NPHY_BPHY_CTL3_SCALE_SHIFT
);
6041 b43_phy_write(dev
, B43_NPHY_AFESEQ_TX2RX_PUD_20M
, 0x20);
6042 b43_phy_write(dev
, B43_NPHY_AFESEQ_TX2RX_PUD_40M
, 0x20);
6044 if (sprom
->boardflags2_lo
& B43_BFL2_SKWRKFEM_BRD
||
6045 (dev
->dev
->board_vendor
== PCI_VENDOR_ID_APPLE
&&
6046 dev
->dev
->board_type
== BCMA_BOARD_TYPE_BCM943224M93
))
6047 b43_phy_write(dev
, B43_NPHY_TXREALFD
, 0xA0);
6049 b43_phy_write(dev
, B43_NPHY_TXREALFD
, 0xB8);
6050 b43_phy_write(dev
, B43_NPHY_MIMO_CRSTXEXT
, 0xC8);
6051 b43_phy_write(dev
, B43_NPHY_PLOAD_CSENSE_EXTLEN
, 0x50);
6052 b43_phy_write(dev
, B43_NPHY_TXRIFS_FRDEL
, 0x30);
6055 b43_nphy_update_mimo_config(dev
, nphy
->preamble_override
);
6057 b43_nphy_update_txrx_chain(dev
);
6060 b43_phy_write(dev
, B43_NPHY_DUP40_GFBL
, 0xAA8);
6061 b43_phy_write(dev
, B43_NPHY_DUP40_BL
, 0x9A4);
6064 tmp2
= b43_current_band(dev
->wl
);
6065 if (b43_nphy_ipa(dev
)) {
6066 b43_phy_set(dev
, B43_NPHY_PAPD_EN0
, 0x1);
6067 b43_phy_maskset(dev
, B43_NPHY_EPS_TABLE_ADJ0
, 0x007F,
6068 nphy
->papd_epsilon_offset
[0] << 7);
6069 b43_phy_set(dev
, B43_NPHY_PAPD_EN1
, 0x1);
6070 b43_phy_maskset(dev
, B43_NPHY_EPS_TABLE_ADJ1
, 0x007F,
6071 nphy
->papd_epsilon_offset
[1] << 7);
6072 b43_nphy_int_pa_set_tx_dig_filters(dev
);
6073 } else if (phy
->rev
>= 5) {
6074 b43_nphy_ext_pa_set_tx_dig_filters(dev
);
6077 b43_nphy_workarounds(dev
);
6079 /* Reset CCA, in init code it differs a little from standard way */
6080 b43_phy_force_clock(dev
, 1);
6081 tmp
= b43_phy_read(dev
, B43_NPHY_BBCFG
);
6082 b43_phy_write(dev
, B43_NPHY_BBCFG
, tmp
| B43_NPHY_BBCFG_RSTCCA
);
6083 b43_phy_write(dev
, B43_NPHY_BBCFG
, tmp
& ~B43_NPHY_BBCFG_RSTCCA
);
6084 b43_phy_force_clock(dev
, 0);
6086 b43_mac_phy_clock_set(dev
, true);
6089 b43_nphy_pa_override(dev
, false);
6090 b43_nphy_force_rf_sequence(dev
, B43_RFSEQ_RX2TX
);
6091 b43_nphy_force_rf_sequence(dev
, B43_RFSEQ_RESET2RX
);
6092 b43_nphy_pa_override(dev
, true);
6095 b43_nphy_classifier(dev
, 0, 0);
6096 b43_nphy_read_clip_detection(dev
, clip
);
6097 if (b43_current_band(dev
->wl
) == IEEE80211_BAND_2GHZ
)
6098 b43_nphy_bphy_init(dev
);
6100 tx_pwr_state
= nphy
->txpwrctrl
;
6101 b43_nphy_tx_power_ctrl(dev
, false);
6102 b43_nphy_tx_power_fix(dev
);
6103 b43_nphy_tx_power_ctl_idle_tssi(dev
);
6104 b43_nphy_tx_power_ctl_setup(dev
);
6105 b43_nphy_tx_gain_table_upload(dev
);
6107 if (nphy
->phyrxchain
!= 3)
6108 b43_nphy_set_rx_core_state(dev
, nphy
->phyrxchain
);
6109 if (nphy
->mphase_cal_phase_id
> 0)
6110 ;/* TODO PHY Periodic Calibration Multi-Phase Restart */
6112 do_rssi_cal
= false;
6113 if (phy
->rev
>= 3) {
6114 if (b43_current_band(dev
->wl
) == IEEE80211_BAND_2GHZ
)
6115 do_rssi_cal
= !nphy
->rssical_chanspec_2G
.center_freq
;
6117 do_rssi_cal
= !nphy
->rssical_chanspec_5G
.center_freq
;
6120 b43_nphy_rssi_cal(dev
);
6122 b43_nphy_restore_rssi_cal(dev
);
6124 b43_nphy_rssi_cal(dev
);
6127 if (!((nphy
->measure_hold
& 0x6) != 0)) {
6128 if (b43_current_band(dev
->wl
) == IEEE80211_BAND_2GHZ
)
6129 do_cal
= !nphy
->iqcal_chanspec_2G
.center_freq
;
6131 do_cal
= !nphy
->iqcal_chanspec_5G
.center_freq
;
6137 target
= b43_nphy_get_tx_gains(dev
);
6139 if (nphy
->antsel_type
== 2)
6140 b43_nphy_superswitch_init(dev
, true);
6141 if (nphy
->perical
!= 2) {
6142 b43_nphy_rssi_cal(dev
);
6143 if (phy
->rev
>= 3) {
6144 nphy
->cal_orig_pwr_idx
[0] =
6145 nphy
->txpwrindex
[0].index_internal
;
6146 nphy
->cal_orig_pwr_idx
[1] =
6147 nphy
->txpwrindex
[1].index_internal
;
6148 /* TODO N PHY Pre Calibrate TX Gain */
6149 target
= b43_nphy_get_tx_gains(dev
);
6151 if (!b43_nphy_cal_tx_iq_lo(dev
, target
, true, false))
6152 if (b43_nphy_cal_rx_iq(dev
, target
, 2, 0) == 0)
6153 b43_nphy_save_cal(dev
);
6154 } else if (nphy
->mphase_cal_phase_id
== 0)
6155 ;/* N PHY Periodic Calibration with arg 3 */
6157 b43_nphy_restore_cal(dev
);
6161 b43_nphy_tx_pwr_ctrl_coef_setup(dev
);
6162 b43_nphy_tx_power_ctrl(dev
, tx_pwr_state
);
6163 b43_phy_write(dev
, B43_NPHY_TXMACIF_HOLDOFF
, 0x0015);
6164 b43_phy_write(dev
, B43_NPHY_TXMACDELAY
, 0x0320);
6165 if (phy
->rev
>= 3 && phy
->rev
<= 6)
6166 b43_phy_write(dev
, B43_NPHY_PLOAD_CSENSE_EXTLEN
, 0x0032);
6167 b43_nphy_tx_lpf_bw(dev
);
6169 b43_nphy_spur_workaround(dev
);
6174 /**************************************************
6175 * Channel switching ops.
6176 **************************************************/
6178 static void b43_chantab_phy_upload(struct b43_wldev
*dev
,
6179 const struct b43_phy_n_sfo_cfg
*e
)
6181 b43_phy_write(dev
, B43_NPHY_BW1A
, e
->phy_bw1a
);
6182 b43_phy_write(dev
, B43_NPHY_BW2
, e
->phy_bw2
);
6183 b43_phy_write(dev
, B43_NPHY_BW3
, e
->phy_bw3
);
6184 b43_phy_write(dev
, B43_NPHY_BW4
, e
->phy_bw4
);
6185 b43_phy_write(dev
, B43_NPHY_BW5
, e
->phy_bw5
);
6186 b43_phy_write(dev
, B43_NPHY_BW6
, e
->phy_bw6
);
6189 /* http://bcm-v4.sipsolutions.net/802.11/PmuSpurAvoid */
6190 static void b43_nphy_pmu_spur_avoid(struct b43_wldev
*dev
, bool avoid
)
6192 switch (dev
->dev
->bus_type
) {
6193 #ifdef CONFIG_B43_BCMA
6195 bcma_pmu_spuravoid_pllupdate(&dev
->dev
->bdev
->bus
->drv_cc
,
6199 #ifdef CONFIG_B43_SSB
6201 ssb_pmu_spuravoid_pllupdate(&dev
->dev
->sdev
->bus
->chipco
,
6208 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ChanspecSetup */
6209 static void b43_nphy_channel_setup(struct b43_wldev
*dev
,
6210 const struct b43_phy_n_sfo_cfg
*e
,
6211 struct ieee80211_channel
*new_channel
)
6213 struct b43_phy
*phy
= &dev
->phy
;
6214 struct b43_phy_n
*nphy
= dev
->phy
.n
;
6215 int ch
= new_channel
->hw_value
;
6218 if (new_channel
->band
== IEEE80211_BAND_5GHZ
) {
6219 tmp16
= b43_read16(dev
, B43_MMIO_PSM_PHY_HDR
);
6220 b43_write16(dev
, B43_MMIO_PSM_PHY_HDR
, tmp16
| 4);
6221 /* Put BPHY in the reset */
6222 b43_phy_set(dev
, B43_PHY_B_BBCFG
,
6223 B43_PHY_B_BBCFG_RSTCCA
| B43_PHY_B_BBCFG_RSTRX
);
6224 b43_write16(dev
, B43_MMIO_PSM_PHY_HDR
, tmp16
);
6225 b43_phy_set(dev
, B43_NPHY_BANDCTL
, B43_NPHY_BANDCTL_5GHZ
);
6226 } else if (new_channel
->band
== IEEE80211_BAND_2GHZ
) {
6227 b43_phy_mask(dev
, B43_NPHY_BANDCTL
, ~B43_NPHY_BANDCTL_5GHZ
);
6228 tmp16
= b43_read16(dev
, B43_MMIO_PSM_PHY_HDR
);
6229 b43_write16(dev
, B43_MMIO_PSM_PHY_HDR
, tmp16
| 4);
6230 /* Take BPHY out of the reset */
6231 b43_phy_mask(dev
, B43_PHY_B_BBCFG
,
6232 (u16
)~(B43_PHY_B_BBCFG_RSTCCA
| B43_PHY_B_BBCFG_RSTRX
));
6233 b43_write16(dev
, B43_MMIO_PSM_PHY_HDR
, tmp16
);
6236 b43_chantab_phy_upload(dev
, e
);
6238 if (new_channel
->hw_value
== 14) {
6239 b43_nphy_classifier(dev
, 2, 0);
6240 b43_phy_set(dev
, B43_PHY_B_TEST
, 0x0800);
6242 b43_nphy_classifier(dev
, 2, 2);
6243 if (new_channel
->band
== IEEE80211_BAND_2GHZ
)
6244 b43_phy_mask(dev
, B43_PHY_B_TEST
, ~0x840);
6247 if (!nphy
->txpwrctrl
)
6248 b43_nphy_tx_power_fix(dev
);
6250 if (dev
->phy
.rev
< 3)
6251 b43_nphy_adjust_lna_gain_table(dev
);
6253 b43_nphy_tx_lpf_bw(dev
);
6255 if (dev
->phy
.rev
>= 3 &&
6256 dev
->phy
.n
->spur_avoid
!= B43_SPUR_AVOID_DISABLE
) {
6259 if (dev
->phy
.n
->spur_avoid
== B43_SPUR_AVOID_FORCE
) {
6261 } else if (phy
->rev
>= 19) {
6263 } else if (phy
->rev
>= 18) {
6265 } else if (phy
->rev
>= 17) {
6266 /* TODO: Off for channels 1-11, but check 12-14! */
6267 } else if (phy
->rev
>= 16) {
6268 /* TODO: Off for 2 GHz, but check 5 GHz! */
6269 } else if (phy
->rev
>= 7) {
6270 if (!b43_is_40mhz(dev
)) { /* 20MHz */
6271 if (ch
== 13 || ch
== 14 || ch
== 153)
6273 } else { /* 40 MHz */
6278 if (!b43_is_40mhz(dev
)) { /* 20MHz */
6279 if ((ch
>= 5 && ch
<= 8) || ch
== 13 || ch
== 14)
6281 } else { /* 40MHz */
6282 if (nphy
->aband_spurwar_en
&&
6283 (ch
== 38 || ch
== 102 || ch
== 118))
6284 spuravoid
= dev
->dev
->chip_id
== 0x4716;
6288 b43_nphy_pmu_spur_avoid(dev
, spuravoid
);
6290 b43_mac_switch_freq(dev
, spuravoid
);
6292 if (dev
->phy
.rev
== 3 || dev
->phy
.rev
== 4)
6293 ; /* TODO: reset PLL */
6296 b43_phy_set(dev
, B43_NPHY_BBCFG
, B43_NPHY_BBCFG_RSTRX
);
6298 b43_phy_mask(dev
, B43_NPHY_BBCFG
,
6299 ~B43_NPHY_BBCFG_RSTRX
& 0xFFFF);
6301 b43_nphy_reset_cca(dev
);
6303 /* wl sets useless phy_isspuravoid here */
6306 b43_phy_write(dev
, B43_NPHY_NDATAT_DUP40
, 0x3830);
6309 b43_nphy_spur_workaround(dev
);
6312 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetChanspec */
6313 static int b43_nphy_set_channel(struct b43_wldev
*dev
,
6314 struct ieee80211_channel
*channel
,
6315 enum nl80211_channel_type channel_type
)
6317 struct b43_phy
*phy
= &dev
->phy
;
6319 const struct b43_nphy_channeltab_entry_rev2
*tabent_r2
= NULL
;
6320 const struct b43_nphy_channeltab_entry_rev3
*tabent_r3
= NULL
;
6321 const struct b43_nphy_chantabent_rev7
*tabent_r7
= NULL
;
6322 const struct b43_nphy_chantabent_rev7_2g
*tabent_r7_2g
= NULL
;
6326 if (phy
->rev
>= 19) {
6329 } else if (phy
->rev
>= 7) {
6330 r2057_get_chantabent_rev7(dev
, channel
->center_freq
,
6331 &tabent_r7
, &tabent_r7_2g
);
6332 if (!tabent_r7
&& !tabent_r7_2g
)
6334 } else if (phy
->rev
>= 3) {
6335 tabent_r3
= b43_nphy_get_chantabent_rev3(dev
,
6336 channel
->center_freq
);
6340 tabent_r2
= b43_nphy_get_chantabent_rev2(dev
,
6346 /* Channel is set later in common code, but we need to set it on our
6347 own to let this function's subcalls work properly. */
6348 phy
->channel
= channel
->hw_value
;
6351 if (b43_channel_type_is_40mhz(phy
->channel_type
) !=
6352 b43_channel_type_is_40mhz(channel_type
))
6353 ; /* TODO: BMAC BW Set (channel_type) */
6356 if (channel_type
== NL80211_CHAN_HT40PLUS
) {
6357 b43_phy_set(dev
, B43_NPHY_RXCTL
, B43_NPHY_RXCTL_BSELU20
);
6359 b43_phy_set(dev
, 0x310, 0x8000);
6360 } else if (channel_type
== NL80211_CHAN_HT40MINUS
) {
6361 b43_phy_mask(dev
, B43_NPHY_RXCTL
, ~B43_NPHY_RXCTL_BSELU20
);
6363 b43_phy_mask(dev
, 0x310, (u16
)~0x8000);
6366 if (phy
->rev
>= 19) {
6368 } else if (phy
->rev
>= 7) {
6369 const struct b43_phy_n_sfo_cfg
*phy_regs
= tabent_r7
?
6370 &(tabent_r7
->phy_regs
) : &(tabent_r7_2g
->phy_regs
);
6372 if (phy
->radio_rev
<= 4 || phy
->radio_rev
== 6) {
6373 tmp
= (channel
->band
== IEEE80211_BAND_5GHZ
) ? 2 : 0;
6374 b43_radio_maskset(dev
, R2057_TIA_CONFIG_CORE0
, ~2, tmp
);
6375 b43_radio_maskset(dev
, R2057_TIA_CONFIG_CORE1
, ~2, tmp
);
6378 b43_radio_2057_setup(dev
, tabent_r7
, tabent_r7_2g
);
6379 b43_nphy_channel_setup(dev
, phy_regs
, channel
);
6380 } else if (phy
->rev
>= 3) {
6381 tmp
= (channel
->band
== IEEE80211_BAND_5GHZ
) ? 4 : 0;
6382 b43_radio_maskset(dev
, 0x08, 0xFFFB, tmp
);
6383 b43_radio_2056_setup(dev
, tabent_r3
);
6384 b43_nphy_channel_setup(dev
, &(tabent_r3
->phy_regs
), channel
);
6386 tmp
= (channel
->band
== IEEE80211_BAND_5GHZ
) ? 0x0020 : 0x0050;
6387 b43_radio_maskset(dev
, B2055_MASTER1
, 0xFF8F, tmp
);
6388 b43_radio_2055_setup(dev
, tabent_r2
);
6389 b43_nphy_channel_setup(dev
, &(tabent_r2
->phy_regs
), channel
);
6395 /**************************************************
6397 **************************************************/
6399 static int b43_nphy_op_allocate(struct b43_wldev
*dev
)
6401 struct b43_phy_n
*nphy
;
6403 nphy
= kzalloc(sizeof(*nphy
), GFP_KERNEL
);
6411 static void b43_nphy_op_prepare_structs(struct b43_wldev
*dev
)
6413 struct b43_phy
*phy
= &dev
->phy
;
6414 struct b43_phy_n
*nphy
= phy
->n
;
6415 struct ssb_sprom
*sprom
= dev
->dev
->bus_sprom
;
6417 memset(nphy
, 0, sizeof(*nphy
));
6419 nphy
->hang_avoid
= (phy
->rev
== 3 || phy
->rev
== 4);
6420 nphy
->spur_avoid
= (phy
->rev
>= 3) ?
6421 B43_SPUR_AVOID_AUTO
: B43_SPUR_AVOID_DISABLE
;
6422 nphy
->gain_boost
= true; /* this way we follow wl, assume it is true */
6423 nphy
->txrx_chain
= 2; /* sth different than 0 and 1 for now */
6424 nphy
->phyrxchain
= 3; /* to avoid b43_nphy_set_rx_core_state like wl */
6425 nphy
->perical
= 2; /* avoid additional rssi cal on init (like wl) */
6426 /* 128 can mean disabled-by-default state of TX pwr ctl. Max value is
6427 * 0x7f == 127 and we check for 128 when restoring TX pwr ctl. */
6428 nphy
->tx_pwr_idx
[0] = 128;
6429 nphy
->tx_pwr_idx
[1] = 128;
6431 /* Hardware TX power control and 5GHz power gain */
6432 nphy
->txpwrctrl
= false;
6433 nphy
->pwg_gain_5ghz
= false;
6434 if (dev
->phy
.rev
>= 3 ||
6435 (dev
->dev
->board_vendor
== PCI_VENDOR_ID_APPLE
&&
6436 (dev
->dev
->core_rev
== 11 || dev
->dev
->core_rev
== 12))) {
6437 nphy
->txpwrctrl
= true;
6438 nphy
->pwg_gain_5ghz
= true;
6439 } else if (sprom
->revision
>= 4) {
6440 if (dev
->phy
.rev
>= 2 &&
6441 (sprom
->boardflags2_lo
& B43_BFL2_TXPWRCTRL_EN
)) {
6442 nphy
->txpwrctrl
= true;
6443 #ifdef CONFIG_B43_SSB
6444 if (dev
->dev
->bus_type
== B43_BUS_SSB
&&
6445 dev
->dev
->sdev
->bus
->bustype
== SSB_BUSTYPE_PCI
) {
6446 struct pci_dev
*pdev
=
6447 dev
->dev
->sdev
->bus
->host_pci
;
6448 if (pdev
->device
== 0x4328 ||
6449 pdev
->device
== 0x432a)
6450 nphy
->pwg_gain_5ghz
= true;
6453 } else if (sprom
->boardflags2_lo
& B43_BFL2_5G_PWRGAIN
) {
6454 nphy
->pwg_gain_5ghz
= true;
6458 if (dev
->phy
.rev
>= 3) {
6459 nphy
->ipa2g_on
= sprom
->fem
.ghz2
.extpa_gain
== 2;
6460 nphy
->ipa5g_on
= sprom
->fem
.ghz5
.extpa_gain
== 2;
6464 static void b43_nphy_op_free(struct b43_wldev
*dev
)
6466 struct b43_phy
*phy
= &dev
->phy
;
6467 struct b43_phy_n
*nphy
= phy
->n
;
6473 static int b43_nphy_op_init(struct b43_wldev
*dev
)
6475 return b43_phy_initn(dev
);
6478 static inline void check_phyreg(struct b43_wldev
*dev
, u16 offset
)
6481 if ((offset
& B43_PHYROUTE
) == B43_PHYROUTE_OFDM_GPHY
) {
6482 /* OFDM registers are onnly available on A/G-PHYs */
6483 b43err(dev
->wl
, "Invalid OFDM PHY access at "
6484 "0x%04X on N-PHY\n", offset
);
6487 if ((offset
& B43_PHYROUTE
) == B43_PHYROUTE_EXT_GPHY
) {
6488 /* Ext-G registers are only available on G-PHYs */
6489 b43err(dev
->wl
, "Invalid EXT-G PHY access at "
6490 "0x%04X on N-PHY\n", offset
);
6493 #endif /* B43_DEBUG */
6496 static u16
b43_nphy_op_read(struct b43_wldev
*dev
, u16 reg
)
6498 check_phyreg(dev
, reg
);
6499 b43_write16(dev
, B43_MMIO_PHY_CONTROL
, reg
);
6500 return b43_read16(dev
, B43_MMIO_PHY_DATA
);
6503 static void b43_nphy_op_write(struct b43_wldev
*dev
, u16 reg
, u16 value
)
6505 check_phyreg(dev
, reg
);
6506 b43_write16(dev
, B43_MMIO_PHY_CONTROL
, reg
);
6507 b43_write16(dev
, B43_MMIO_PHY_DATA
, value
);
6510 static void b43_nphy_op_maskset(struct b43_wldev
*dev
, u16 reg
, u16 mask
,
6513 check_phyreg(dev
, reg
);
6514 b43_write16(dev
, B43_MMIO_PHY_CONTROL
, reg
);
6515 b43_maskset16(dev
, B43_MMIO_PHY_DATA
, mask
, set
);
6518 static u16
b43_nphy_op_radio_read(struct b43_wldev
*dev
, u16 reg
)
6520 /* Register 1 is a 32-bit register. */
6521 B43_WARN_ON(dev
->phy
.rev
< 7 && reg
== 1);
6523 if (dev
->phy
.rev
>= 7)
6524 reg
|= 0x200; /* Radio 0x2057 */
6528 b43_write16(dev
, B43_MMIO_RADIO_CONTROL
, reg
);
6529 return b43_read16(dev
, B43_MMIO_RADIO_DATA_LOW
);
6532 static void b43_nphy_op_radio_write(struct b43_wldev
*dev
, u16 reg
, u16 value
)
6534 /* Register 1 is a 32-bit register. */
6535 B43_WARN_ON(dev
->phy
.rev
< 7 && reg
== 1);
6537 b43_write16(dev
, B43_MMIO_RADIO_CONTROL
, reg
);
6538 b43_write16(dev
, B43_MMIO_RADIO_DATA_LOW
, value
);
6541 /* http://bcm-v4.sipsolutions.net/802.11/Radio/Switch%20Radio */
6542 static void b43_nphy_op_software_rfkill(struct b43_wldev
*dev
,
6545 struct b43_phy
*phy
= &dev
->phy
;
6547 if (b43_read32(dev
, B43_MMIO_MACCTL
) & B43_MACCTL_ENABLED
)
6548 b43err(dev
->wl
, "MAC not suspended\n");
6551 if (phy
->rev
>= 19) {
6553 } else if (phy
->rev
>= 8) {
6554 b43_phy_mask(dev
, B43_NPHY_RFCTL_CMD
,
6555 ~B43_NPHY_RFCTL_CMD_CHIP0PU
);
6556 } else if (phy
->rev
>= 7) {
6557 /* Nothing needed */
6558 } else if (phy
->rev
>= 3) {
6559 b43_phy_mask(dev
, B43_NPHY_RFCTL_CMD
,
6560 ~B43_NPHY_RFCTL_CMD_CHIP0PU
);
6562 b43_radio_mask(dev
, 0x09, ~0x2);
6564 b43_radio_write(dev
, 0x204D, 0);
6565 b43_radio_write(dev
, 0x2053, 0);
6566 b43_radio_write(dev
, 0x2058, 0);
6567 b43_radio_write(dev
, 0x205E, 0);
6568 b43_radio_mask(dev
, 0x2062, ~0xF0);
6569 b43_radio_write(dev
, 0x2064, 0);
6571 b43_radio_write(dev
, 0x304D, 0);
6572 b43_radio_write(dev
, 0x3053, 0);
6573 b43_radio_write(dev
, 0x3058, 0);
6574 b43_radio_write(dev
, 0x305E, 0);
6575 b43_radio_mask(dev
, 0x3062, ~0xF0);
6576 b43_radio_write(dev
, 0x3064, 0);
6579 if (phy
->rev
>= 19) {
6581 } else if (phy
->rev
>= 7) {
6582 if (!dev
->phy
.radio_on
)
6583 b43_radio_2057_init(dev
);
6584 b43_switch_channel(dev
, dev
->phy
.channel
);
6585 } else if (phy
->rev
>= 3) {
6586 if (!dev
->phy
.radio_on
)
6587 b43_radio_init2056(dev
);
6588 b43_switch_channel(dev
, dev
->phy
.channel
);
6590 b43_radio_init2055(dev
);
6595 /* http://bcm-v4.sipsolutions.net/802.11/PHY/Anacore */
6596 static void b43_nphy_op_switch_analog(struct b43_wldev
*dev
, bool on
)
6598 struct b43_phy
*phy
= &dev
->phy
;
6599 u16 override
= on
? 0x0 : 0x7FFF;
6600 u16 core
= on
? 0xD : 0x00FD;
6602 if (phy
->rev
>= 19) {
6604 } else if (phy
->rev
>= 3) {
6606 b43_phy_write(dev
, B43_NPHY_AFECTL_C1
, core
);
6607 b43_phy_write(dev
, B43_NPHY_AFECTL_OVER1
, override
);
6608 b43_phy_write(dev
, B43_NPHY_AFECTL_C2
, core
);
6609 b43_phy_write(dev
, B43_NPHY_AFECTL_OVER
, override
);
6611 b43_phy_write(dev
, B43_NPHY_AFECTL_OVER1
, override
);
6612 b43_phy_write(dev
, B43_NPHY_AFECTL_C1
, core
);
6613 b43_phy_write(dev
, B43_NPHY_AFECTL_OVER
, override
);
6614 b43_phy_write(dev
, B43_NPHY_AFECTL_C2
, core
);
6617 b43_phy_write(dev
, B43_NPHY_AFECTL_OVER
, override
);
6621 static int b43_nphy_op_switch_channel(struct b43_wldev
*dev
,
6622 unsigned int new_channel
)
6624 struct ieee80211_channel
*channel
= dev
->wl
->hw
->conf
.chandef
.chan
;
6625 enum nl80211_channel_type channel_type
=
6626 cfg80211_get_chandef_type(&dev
->wl
->hw
->conf
.chandef
);
6628 if (b43_current_band(dev
->wl
) == IEEE80211_BAND_2GHZ
) {
6629 if ((new_channel
< 1) || (new_channel
> 14))
6632 if (new_channel
> 200)
6636 return b43_nphy_set_channel(dev
, channel
, channel_type
);
6639 static unsigned int b43_nphy_op_get_default_chan(struct b43_wldev
*dev
)
6641 if (b43_current_band(dev
->wl
) == IEEE80211_BAND_2GHZ
)
6646 const struct b43_phy_operations b43_phyops_n
= {
6647 .allocate
= b43_nphy_op_allocate
,
6648 .free
= b43_nphy_op_free
,
6649 .prepare_structs
= b43_nphy_op_prepare_structs
,
6650 .init
= b43_nphy_op_init
,
6651 .phy_read
= b43_nphy_op_read
,
6652 .phy_write
= b43_nphy_op_write
,
6653 .phy_maskset
= b43_nphy_op_maskset
,
6654 .radio_read
= b43_nphy_op_radio_read
,
6655 .radio_write
= b43_nphy_op_radio_write
,
6656 .software_rfkill
= b43_nphy_op_software_rfkill
,
6657 .switch_analog
= b43_nphy_op_switch_analog
,
6658 .switch_channel
= b43_nphy_op_switch_channel
,
6659 .get_default_chan
= b43_nphy_op_get_default_chan
,
6660 .recalc_txpower
= b43_nphy_op_recalc_txpower
,
6661 .adjust_txpower
= b43_nphy_op_adjust_txpower
,