projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Merge tag 'omap-pm-v3.10/cleanup/pm' of git://git.kernel.org/pub/scm/linux/kernel...
[deliverable/linux.git] / drivers / net / wireless / b43legacy / dma.c
1 /*
2
3 Broadcom B43legacy wireless driver
4
5 DMA ringbuffer and descriptor allocation/management
6
7 Copyright (c) 2005, 2006 Michael Buesch <m@bues.ch>
8
9 Some code in this file is derived from the b44.c driver
10 Copyright (C) 2002 David S. Miller
11 Copyright (C) Pekka Pietikainen
12
13 This program is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 2 of the License, or
16 (at your option) any later version.
17
18 This program is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
22
23 You should have received a copy of the GNU General Public License
24 along with this program; see the file COPYING. If not, write to
25 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
26 Boston, MA 02110-1301, USA.
27
28 */
29
30 #include "b43legacy.h"
31 #include "dma.h"
32 #include "main.h"
33 #include "debugfs.h"
34 #include "xmit.h"
35
36 #include <linux/dma-mapping.h>
37 #include <linux/pci.h>
38 #include <linux/delay.h>
39 #include <linux/skbuff.h>
40 #include <linux/slab.h>
41 #include <net/dst.h>
42
43 /* 32bit DMA ops. */
44 static
45 struct b43legacy_dmadesc32 *op32_idx2desc(struct b43legacy_dmaring *ring,
46 int slot,
47 struct b43legacy_dmadesc_meta **meta)
48 {
49 struct b43legacy_dmadesc32 *desc;
50
51 *meta = &(ring->meta[slot]);
52 desc = ring->descbase;
53 desc = &(desc[slot]);
54
55 return desc;
56 }
57
58 static void op32_fill_descriptor(struct b43legacy_dmaring *ring,
59 struct b43legacy_dmadesc32 *desc,
60 dma_addr_t dmaaddr, u16 bufsize,
61 int start, int end, int irq)
62 {
63 struct b43legacy_dmadesc32 *descbase = ring->descbase;
64 int slot;
65 u32 ctl;
66 u32 addr;
67 u32 addrext;
68
69 slot = (int)(desc - descbase);
70 B43legacy_WARN_ON(!(slot >= 0 && slot < ring->nr_slots));
71
72 addr = (u32)(dmaaddr & ~SSB_DMA_TRANSLATION_MASK);
73 addrext = (u32)(dmaaddr & SSB_DMA_TRANSLATION_MASK)
74 >> SSB_DMA_TRANSLATION_SHIFT;
75 addr |= ring->dev->dma.translation;
76 ctl = (bufsize - ring->frameoffset)
77 & B43legacy_DMA32_DCTL_BYTECNT;
78 if (slot == ring->nr_slots - 1)
79 ctl |= B43legacy_DMA32_DCTL_DTABLEEND;
80 if (start)
81 ctl |= B43legacy_DMA32_DCTL_FRAMESTART;
82 if (end)
83 ctl |= B43legacy_DMA32_DCTL_FRAMEEND;
84 if (irq)
85 ctl |= B43legacy_DMA32_DCTL_IRQ;
86 ctl |= (addrext << B43legacy_DMA32_DCTL_ADDREXT_SHIFT)
87 & B43legacy_DMA32_DCTL_ADDREXT_MASK;
88
89 desc->control = cpu_to_le32(ctl);
90 desc->address = cpu_to_le32(addr);
91 }
92
93 static void op32_poke_tx(struct b43legacy_dmaring *ring, int slot)
94 {
95 b43legacy_dma_write(ring, B43legacy_DMA32_TXINDEX,
96 (u32)(slot * sizeof(struct b43legacy_dmadesc32)));
97 }
98
99 static void op32_tx_suspend(struct b43legacy_dmaring *ring)
100 {
101 b43legacy_dma_write(ring, B43legacy_DMA32_TXCTL,
102 b43legacy_dma_read(ring, B43legacy_DMA32_TXCTL)
103 | B43legacy_DMA32_TXSUSPEND);
104 }
105
106 static void op32_tx_resume(struct b43legacy_dmaring *ring)
107 {
108 b43legacy_dma_write(ring, B43legacy_DMA32_TXCTL,
109 b43legacy_dma_read(ring, B43legacy_DMA32_TXCTL)
110 & ~B43legacy_DMA32_TXSUSPEND);
111 }
112
113 static int op32_get_current_rxslot(struct b43legacy_dmaring *ring)
114 {
115 u32 val;
116
117 val = b43legacy_dma_read(ring, B43legacy_DMA32_RXSTATUS);
118 val &= B43legacy_DMA32_RXDPTR;
119
120 return (val / sizeof(struct b43legacy_dmadesc32));
121 }
122
123 static void op32_set_current_rxslot(struct b43legacy_dmaring *ring,
124 int slot)
125 {
126 b43legacy_dma_write(ring, B43legacy_DMA32_RXINDEX,
127 (u32)(slot * sizeof(struct b43legacy_dmadesc32)));
128 }
129
130 static inline int free_slots(struct b43legacy_dmaring *ring)
131 {
132 return (ring->nr_slots - ring->used_slots);
133 }
134
135 static inline int next_slot(struct b43legacy_dmaring *ring, int slot)
136 {
137 B43legacy_WARN_ON(!(slot >= -1 && slot <= ring->nr_slots - 1));
138 if (slot == ring->nr_slots - 1)
139 return 0;
140 return slot + 1;
141 }
142
143 static inline int prev_slot(struct b43legacy_dmaring *ring, int slot)
144 {
145 B43legacy_WARN_ON(!(slot >= 0 && slot <= ring->nr_slots - 1));
146 if (slot == 0)
147 return ring->nr_slots - 1;
148 return slot - 1;
149 }
150
151 #ifdef CONFIG_B43LEGACY_DEBUG
152 static void update_max_used_slots(struct b43legacy_dmaring *ring,
153 int current_used_slots)
154 {
155 if (current_used_slots <= ring->max_used_slots)
156 return;
157 ring->max_used_slots = current_used_slots;
158 if (b43legacy_debug(ring->dev, B43legacy_DBG_DMAVERBOSE))
159 b43legacydbg(ring->dev->wl,
160 "max_used_slots increased to %d on %s ring %d\n",
161 ring->max_used_slots,
162 ring->tx ? "TX" : "RX",
163 ring->index);
164 }
165 #else
166 static inline
167 void update_max_used_slots(struct b43legacy_dmaring *ring,
168 int current_used_slots)
169 { }
170 #endif /* DEBUG */
171
172 /* Request a slot for usage. */
173 static inline
174 int request_slot(struct b43legacy_dmaring *ring)
175 {
176 int slot;
177
178 B43legacy_WARN_ON(!ring->tx);
179 B43legacy_WARN_ON(ring->stopped);
180 B43legacy_WARN_ON(free_slots(ring) == 0);
181
182 slot = next_slot(ring, ring->current_slot);
183 ring->current_slot = slot;
184 ring->used_slots++;
185
186 update_max_used_slots(ring, ring->used_slots);
187
188 return slot;
189 }
190
191 /* Mac80211-queue to b43legacy-ring mapping */
192 static struct b43legacy_dmaring *priority_to_txring(
193 struct b43legacy_wldev *dev,
194 int queue_priority)
195 {
196 struct b43legacy_dmaring *ring;
197
198 /*FIXME: For now we always run on TX-ring-1 */
199 return dev->dma.tx_ring1;
200
201 /* 0 = highest priority */
202 switch (queue_priority) {
203 default:
204 B43legacy_WARN_ON(1);
205 /* fallthrough */
206 case 0:
207 ring = dev->dma.tx_ring3;
208 break;
209 case 1:
210 ring = dev->dma.tx_ring2;
211 break;
212 case 2:
213 ring = dev->dma.tx_ring1;
214 break;
215 case 3:
216 ring = dev->dma.tx_ring0;
217 break;
218 case 4:
219 ring = dev->dma.tx_ring4;
220 break;
221 case 5:
222 ring = dev->dma.tx_ring5;
223 break;
224 }
225
226 return ring;
227 }
228
229 /* Bcm4301-ring to mac80211-queue mapping */
230 static inline int txring_to_priority(struct b43legacy_dmaring *ring)
231 {
232 static const u8 idx_to_prio[] =
233 { 3, 2, 1, 0, 4, 5, };
234
235 /*FIXME: have only one queue, for now */
236 return 0;
237
238 return idx_to_prio[ring->index];
239 }
240
241
242 static u16 b43legacy_dmacontroller_base(enum b43legacy_dmatype type,
243 int controller_idx)
244 {
245 static const u16 map32[] = {
246 B43legacy_MMIO_DMA32_BASE0,
247 B43legacy_MMIO_DMA32_BASE1,
248 B43legacy_MMIO_DMA32_BASE2,
249 B43legacy_MMIO_DMA32_BASE3,
250 B43legacy_MMIO_DMA32_BASE4,
251 B43legacy_MMIO_DMA32_BASE5,
252 };
253
254 B43legacy_WARN_ON(!(controller_idx >= 0 &&
255 controller_idx < ARRAY_SIZE(map32)));
256 return map32[controller_idx];
257 }
258
259 static inline
260 dma_addr_t map_descbuffer(struct b43legacy_dmaring *ring,
261 unsigned char *buf,
262 size_t len,
263 int tx)
264 {
265 dma_addr_t dmaaddr;
266
267 if (tx)
268 dmaaddr = dma_map_single(ring->dev->dev->dma_dev,
269 buf, len,
270 DMA_TO_DEVICE);
271 else
272 dmaaddr = dma_map_single(ring->dev->dev->dma_dev,
273 buf, len,
274 DMA_FROM_DEVICE);
275
276 return dmaaddr;
277 }
278
279 static inline
280 void unmap_descbuffer(struct b43legacy_dmaring *ring,
281 dma_addr_t addr,
282 size_t len,
283 int tx)
284 {
285 if (tx)
286 dma_unmap_single(ring->dev->dev->dma_dev,
287 addr, len,
288 DMA_TO_DEVICE);
289 else
290 dma_unmap_single(ring->dev->dev->dma_dev,
291 addr, len,
292 DMA_FROM_DEVICE);
293 }
294
295 static inline
296 void sync_descbuffer_for_cpu(struct b43legacy_dmaring *ring,
297 dma_addr_t addr,
298 size_t len)
299 {
300 B43legacy_WARN_ON(ring->tx);
301
302 dma_sync_single_for_cpu(ring->dev->dev->dma_dev,
303 addr, len, DMA_FROM_DEVICE);
304 }
305
306 static inline
307 void sync_descbuffer_for_device(struct b43legacy_dmaring *ring,
308 dma_addr_t addr,
309 size_t len)
310 {
311 B43legacy_WARN_ON(ring->tx);
312
313 dma_sync_single_for_device(ring->dev->dev->dma_dev,
314 addr, len, DMA_FROM_DEVICE);
315 }
316
317 static inline
318 void free_descriptor_buffer(struct b43legacy_dmaring *ring,
319 struct b43legacy_dmadesc_meta *meta,
320 int irq_context)
321 {
322 if (meta->skb) {
323 if (irq_context)
324 dev_kfree_skb_irq(meta->skb);
325 else
326 dev_kfree_skb(meta->skb);
327 meta->skb = NULL;
328 }
329 }
330
331 static int alloc_ringmemory(struct b43legacy_dmaring *ring)
332 {
333 /* GFP flags must match the flags in free_ringmemory()! */
334 ring->descbase = dma_alloc_coherent(ring->dev->dev->dma_dev,
335 B43legacy_DMA_RINGMEMSIZE,
336 &(ring->dmabase),
337 GFP_KERNEL | __GFP_ZERO);
338 if (!ring->descbase)
339 return -ENOMEM;
340
341 return 0;
342 }
343
344 static void free_ringmemory(struct b43legacy_dmaring *ring)
345 {
346 dma_free_coherent(ring->dev->dev->dma_dev, B43legacy_DMA_RINGMEMSIZE,
347 ring->descbase, ring->dmabase);
348 }
349
350 /* Reset the RX DMA channel */
351 static int b43legacy_dmacontroller_rx_reset(struct b43legacy_wldev *dev,
352 u16 mmio_base,
353 enum b43legacy_dmatype type)
354 {
355 int i;
356 u32 value;
357 u16 offset;
358
359 might_sleep();
360
361 offset = B43legacy_DMA32_RXCTL;
362 b43legacy_write32(dev, mmio_base + offset, 0);
363 for (i = 0; i < 10; i++) {
364 offset = B43legacy_DMA32_RXSTATUS;
365 value = b43legacy_read32(dev, mmio_base + offset);
366 value &= B43legacy_DMA32_RXSTATE;
367 if (value == B43legacy_DMA32_RXSTAT_DISABLED) {
368 i = -1;
369 break;
370 }
371 msleep(1);
372 }
373 if (i != -1) {
374 b43legacyerr(dev->wl, "DMA RX reset timed out\n");
375 return -ENODEV;
376 }
377
378 return 0;
379 }
380
381 /* Reset the RX DMA channel */
382 static int b43legacy_dmacontroller_tx_reset(struct b43legacy_wldev *dev,
383 u16 mmio_base,
384 enum b43legacy_dmatype type)
385 {
386 int i;
387 u32 value;
388 u16 offset;
389
390 might_sleep();
391
392 for (i = 0; i < 10; i++) {
393 offset = B43legacy_DMA32_TXSTATUS;
394 value = b43legacy_read32(dev, mmio_base + offset);
395 value &= B43legacy_DMA32_TXSTATE;
396 if (value == B43legacy_DMA32_TXSTAT_DISABLED ||
397 value == B43legacy_DMA32_TXSTAT_IDLEWAIT ||
398 value == B43legacy_DMA32_TXSTAT_STOPPED)
399 break;
400 msleep(1);
401 }
402 offset = B43legacy_DMA32_TXCTL;
403 b43legacy_write32(dev, mmio_base + offset, 0);
404 for (i = 0; i < 10; i++) {
405 offset = B43legacy_DMA32_TXSTATUS;
406 value = b43legacy_read32(dev, mmio_base + offset);
407 value &= B43legacy_DMA32_TXSTATE;
408 if (value == B43legacy_DMA32_TXSTAT_DISABLED) {
409 i = -1;
410 break;
411 }
412 msleep(1);
413 }
414 if (i != -1) {
415 b43legacyerr(dev->wl, "DMA TX reset timed out\n");
416 return -ENODEV;
417 }
418 /* ensure the reset is completed. */
419 msleep(1);
420
421 return 0;
422 }
423
424 /* Check if a DMA mapping address is invalid. */
425 static bool b43legacy_dma_mapping_error(struct b43legacy_dmaring *ring,
426 dma_addr_t addr,
427 size_t buffersize,
428 bool dma_to_device)
429 {
430 if (unlikely(dma_mapping_error(ring->dev->dev->dma_dev, addr)))
431 return 1;
432
433 switch (ring->type) {
434 case B43legacy_DMA_30BIT:
435 if ((u64)addr + buffersize > (1ULL << 30))
436 goto address_error;
437 break;
438 case B43legacy_DMA_32BIT:
439 if ((u64)addr + buffersize > (1ULL << 32))
440 goto address_error;
441 break;
442 }
443
444 /* The address is OK. */
445 return 0;
446
447 address_error:
448 /* We can't support this address. Unmap it again. */
449 unmap_descbuffer(ring, addr, buffersize, dma_to_device);
450
451 return 1;
452 }
453
454 static int setup_rx_descbuffer(struct b43legacy_dmaring *ring,
455 struct b43legacy_dmadesc32 *desc,
456 struct b43legacy_dmadesc_meta *meta,
457 gfp_t gfp_flags)
458 {
459 struct b43legacy_rxhdr_fw3 *rxhdr;
460 struct b43legacy_hwtxstatus *txstat;
461 dma_addr_t dmaaddr;
462 struct sk_buff *skb;
463
464 B43legacy_WARN_ON(ring->tx);
465
466 skb = __dev_alloc_skb(ring->rx_buffersize, gfp_flags);
467 if (unlikely(!skb))
468 return -ENOMEM;
469 dmaaddr = map_descbuffer(ring, skb->data,
470 ring->rx_buffersize, 0);
471 if (b43legacy_dma_mapping_error(ring, dmaaddr, ring->rx_buffersize, 0)) {
472 /* ugh. try to realloc in zone_dma */
473 gfp_flags |= GFP_DMA;
474
475 dev_kfree_skb_any(skb);
476
477 skb = __dev_alloc_skb(ring->rx_buffersize, gfp_flags);
478 if (unlikely(!skb))
479 return -ENOMEM;
480 dmaaddr = map_descbuffer(ring, skb->data,
481 ring->rx_buffersize, 0);
482 }
483
484 if (b43legacy_dma_mapping_error(ring, dmaaddr, ring->rx_buffersize, 0)) {
485 dev_kfree_skb_any(skb);
486 return -EIO;
487 }
488
489 meta->skb = skb;
490 meta->dmaaddr = dmaaddr;
491 op32_fill_descriptor(ring, desc, dmaaddr, ring->rx_buffersize, 0, 0, 0);
492
493 rxhdr = (struct b43legacy_rxhdr_fw3 *)(skb->data);
494 rxhdr->frame_len = 0;
495 txstat = (struct b43legacy_hwtxstatus *)(skb->data);
496 txstat->cookie = 0;
497
498 return 0;
499 }
500
501 /* Allocate the initial descbuffers.
502 * This is used for an RX ring only.
503 */
504 static int alloc_initial_descbuffers(struct b43legacy_dmaring *ring)
505 {
506 int i;
507 int err = -ENOMEM;
508 struct b43legacy_dmadesc32 *desc;
509 struct b43legacy_dmadesc_meta *meta;
510
511 for (i = 0; i < ring->nr_slots; i++) {
512 desc = op32_idx2desc(ring, i, &meta);
513
514 err = setup_rx_descbuffer(ring, desc, meta, GFP_KERNEL);
515 if (err) {
516 b43legacyerr(ring->dev->wl,
517 "Failed to allocate initial descbuffers\n");
518 goto err_unwind;
519 }
520 }
521 mb(); /* all descbuffer setup before next line */
522 ring->used_slots = ring->nr_slots;
523 err = 0;
524 out:
525 return err;
526
527 err_unwind:
528 for (i--; i >= 0; i--) {
529 desc = op32_idx2desc(ring, i, &meta);
530
531 unmap_descbuffer(ring, meta->dmaaddr, ring->rx_buffersize, 0);
532 dev_kfree_skb(meta->skb);
533 }
534 goto out;
535 }
536
537 /* Do initial setup of the DMA controller.
538 * Reset the controller, write the ring busaddress
539 * and switch the "enable" bit on.
540 */
541 static int dmacontroller_setup(struct b43legacy_dmaring *ring)
542 {
543 int err = 0;
544 u32 value;
545 u32 addrext;
546 u32 trans = ring->dev->dma.translation;
547 u32 ringbase = (u32)(ring->dmabase);
548
549 if (ring->tx) {
550 addrext = (ringbase & SSB_DMA_TRANSLATION_MASK)
551 >> SSB_DMA_TRANSLATION_SHIFT;
552 value = B43legacy_DMA32_TXENABLE;
553 value |= (addrext << B43legacy_DMA32_TXADDREXT_SHIFT)
554 & B43legacy_DMA32_TXADDREXT_MASK;
555 b43legacy_dma_write(ring, B43legacy_DMA32_TXCTL, value);
556 b43legacy_dma_write(ring, B43legacy_DMA32_TXRING,
557 (ringbase & ~SSB_DMA_TRANSLATION_MASK)
558 | trans);
559 } else {
560 err = alloc_initial_descbuffers(ring);
561 if (err)
562 goto out;
563
564 addrext = (ringbase & SSB_DMA_TRANSLATION_MASK)
565 >> SSB_DMA_TRANSLATION_SHIFT;
566 value = (ring->frameoffset <<
567 B43legacy_DMA32_RXFROFF_SHIFT);
568 value |= B43legacy_DMA32_RXENABLE;
569 value |= (addrext << B43legacy_DMA32_RXADDREXT_SHIFT)
570 & B43legacy_DMA32_RXADDREXT_MASK;
571 b43legacy_dma_write(ring, B43legacy_DMA32_RXCTL, value);
572 b43legacy_dma_write(ring, B43legacy_DMA32_RXRING,
573 (ringbase & ~SSB_DMA_TRANSLATION_MASK)
574 | trans);
575 b43legacy_dma_write(ring, B43legacy_DMA32_RXINDEX, 200);
576 }
577
578 out:
579 return err;
580 }
581
582 /* Shutdown the DMA controller. */
583 static void dmacontroller_cleanup(struct b43legacy_dmaring *ring)
584 {
585 if (ring->tx) {
586 b43legacy_dmacontroller_tx_reset(ring->dev, ring->mmio_base,
587 ring->type);
588 b43legacy_dma_write(ring, B43legacy_DMA32_TXRING, 0);
589 } else {
590 b43legacy_dmacontroller_rx_reset(ring->dev, ring->mmio_base,
591 ring->type);
592 b43legacy_dma_write(ring, B43legacy_DMA32_RXRING, 0);
593 }
594 }
595
596 static void free_all_descbuffers(struct b43legacy_dmaring *ring)
597 {
598 struct b43legacy_dmadesc_meta *meta;
599 int i;
600
601 if (!ring->used_slots)
602 return;
603 for (i = 0; i < ring->nr_slots; i++) {
604 op32_idx2desc(ring, i, &meta);
605
606 if (!meta->skb) {
607 B43legacy_WARN_ON(!ring->tx);
608 continue;
609 }
610 if (ring->tx)
611 unmap_descbuffer(ring, meta->dmaaddr,
612 meta->skb->len, 1);
613 else
614 unmap_descbuffer(ring, meta->dmaaddr,
615 ring->rx_buffersize, 0);
616 free_descriptor_buffer(ring, meta, 0);
617 }
618 }
619
620 static u64 supported_dma_mask(struct b43legacy_wldev *dev)
621 {
622 u32 tmp;
623 u16 mmio_base;
624
625 mmio_base = b43legacy_dmacontroller_base(0, 0);
626 b43legacy_write32(dev,
627 mmio_base + B43legacy_DMA32_TXCTL,
628 B43legacy_DMA32_TXADDREXT_MASK);
629 tmp = b43legacy_read32(dev, mmio_base +
630 B43legacy_DMA32_TXCTL);
631 if (tmp & B43legacy_DMA32_TXADDREXT_MASK)
632 return DMA_BIT_MASK(32);
633
634 return DMA_BIT_MASK(30);
635 }
636
637 static enum b43legacy_dmatype dma_mask_to_engine_type(u64 dmamask)
638 {
639 if (dmamask == DMA_BIT_MASK(30))
640 return B43legacy_DMA_30BIT;
641 if (dmamask == DMA_BIT_MASK(32))
642 return B43legacy_DMA_32BIT;
643 B43legacy_WARN_ON(1);
644 return B43legacy_DMA_30BIT;
645 }
646
647 /* Main initialization function. */
648 static
649 struct b43legacy_dmaring *b43legacy_setup_dmaring(struct b43legacy_wldev *dev,
650 int controller_index,
651 int for_tx,
652 enum b43legacy_dmatype type)
653 {
654 struct b43legacy_dmaring *ring;
655 int err;
656 int nr_slots;
657 dma_addr_t dma_test;
658
659 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
660 if (!ring)
661 goto out;
662 ring->type = type;
663 ring->dev = dev;
664
665 nr_slots = B43legacy_RXRING_SLOTS;
666 if (for_tx)
667 nr_slots = B43legacy_TXRING_SLOTS;
668
669 ring->meta = kcalloc(nr_slots, sizeof(struct b43legacy_dmadesc_meta),
670 GFP_KERNEL);
671 if (!ring->meta)
672 goto err_kfree_ring;
673 if (for_tx) {
674 ring->txhdr_cache = kcalloc(nr_slots,
675 sizeof(struct b43legacy_txhdr_fw3),
676 GFP_KERNEL);
677 if (!ring->txhdr_cache)
678 goto err_kfree_meta;
679
680 /* test for ability to dma to txhdr_cache */
681 dma_test = dma_map_single(dev->dev->dma_dev, ring->txhdr_cache,
682 sizeof(struct b43legacy_txhdr_fw3),
683 DMA_TO_DEVICE);
684
685 if (b43legacy_dma_mapping_error(ring, dma_test,
686 sizeof(struct b43legacy_txhdr_fw3), 1)) {
687 /* ugh realloc */
688 kfree(ring->txhdr_cache);
689 ring->txhdr_cache = kcalloc(nr_slots,
690 sizeof(struct b43legacy_txhdr_fw3),
691 GFP_KERNEL | GFP_DMA);
692 if (!ring->txhdr_cache)
693 goto err_kfree_meta;
694
695 dma_test = dma_map_single(dev->dev->dma_dev,
696 ring->txhdr_cache,
697 sizeof(struct b43legacy_txhdr_fw3),
698 DMA_TO_DEVICE);
699
700 if (b43legacy_dma_mapping_error(ring, dma_test,
701 sizeof(struct b43legacy_txhdr_fw3), 1))
702 goto err_kfree_txhdr_cache;
703 }
704
705 dma_unmap_single(dev->dev->dma_dev, dma_test,
706 sizeof(struct b43legacy_txhdr_fw3),
707 DMA_TO_DEVICE);
708 }
709
710 ring->nr_slots = nr_slots;
711 ring->mmio_base = b43legacy_dmacontroller_base(type, controller_index);
712 ring->index = controller_index;
713 if (for_tx) {
714 ring->tx = true;
715 ring->current_slot = -1;
716 } else {
717 if (ring->index == 0) {
718 ring->rx_buffersize = B43legacy_DMA0_RX_BUFFERSIZE;
719 ring->frameoffset = B43legacy_DMA0_RX_FRAMEOFFSET;
720 } else if (ring->index == 3) {
721 ring->rx_buffersize = B43legacy_DMA3_RX_BUFFERSIZE;
722 ring->frameoffset = B43legacy_DMA3_RX_FRAMEOFFSET;
723 } else
724 B43legacy_WARN_ON(1);
725 }
726 #ifdef CONFIG_B43LEGACY_DEBUG
727 ring->last_injected_overflow = jiffies;
728 #endif
729
730 err = alloc_ringmemory(ring);
731 if (err)
732 goto err_kfree_txhdr_cache;
733 err = dmacontroller_setup(ring);
734 if (err)
735 goto err_free_ringmemory;
736
737 out:
738 return ring;
739
740 err_free_ringmemory:
741 free_ringmemory(ring);
742 err_kfree_txhdr_cache:
743 kfree(ring->txhdr_cache);
744 err_kfree_meta:
745 kfree(ring->meta);
746 err_kfree_ring:
747 kfree(ring);
748 ring = NULL;
749 goto out;
750 }
751
752 /* Main cleanup function. */
753 static void b43legacy_destroy_dmaring(struct b43legacy_dmaring *ring)
754 {
755 if (!ring)
756 return;
757
758 b43legacydbg(ring->dev->wl, "DMA-%u 0x%04X (%s) max used slots:"
759 " %d/%d\n", (unsigned int)(ring->type), ring->mmio_base,
760 (ring->tx) ? "TX" : "RX", ring->max_used_slots,
761 ring->nr_slots);
762 /* Device IRQs are disabled prior entering this function,
763 * so no need to take care of concurrency with rx handler stuff.
764 */
765 dmacontroller_cleanup(ring);
766 free_all_descbuffers(ring);
767 free_ringmemory(ring);
768
769 kfree(ring->txhdr_cache);
770 kfree(ring->meta);
771 kfree(ring);
772 }
773
774 void b43legacy_dma_free(struct b43legacy_wldev *dev)
775 {
776 struct b43legacy_dma *dma;
777
778 if (b43legacy_using_pio(dev))
779 return;
780 dma = &dev->dma;
781
782 b43legacy_destroy_dmaring(dma->rx_ring3);
783 dma->rx_ring3 = NULL;
784 b43legacy_destroy_dmaring(dma->rx_ring0);
785 dma->rx_ring0 = NULL;
786
787 b43legacy_destroy_dmaring(dma->tx_ring5);
788 dma->tx_ring5 = NULL;
789 b43legacy_destroy_dmaring(dma->tx_ring4);
790 dma->tx_ring4 = NULL;
791 b43legacy_destroy_dmaring(dma->tx_ring3);
792 dma->tx_ring3 = NULL;
793 b43legacy_destroy_dmaring(dma->tx_ring2);
794 dma->tx_ring2 = NULL;
795 b43legacy_destroy_dmaring(dma->tx_ring1);
796 dma->tx_ring1 = NULL;
797 b43legacy_destroy_dmaring(dma->tx_ring0);
798 dma->tx_ring0 = NULL;
799 }
800
801 static int b43legacy_dma_set_mask(struct b43legacy_wldev *dev, u64 mask)
802 {
803 u64 orig_mask = mask;
804 bool fallback = false;
805 int err;
806
807 /* Try to set the DMA mask. If it fails, try falling back to a
808 * lower mask, as we can always also support a lower one. */
809 while (1) {
810 err = dma_set_mask(dev->dev->dma_dev, mask);
811 if (!err) {
812 err = dma_set_coherent_mask(dev->dev->dma_dev, mask);
813 if (!err)
814 break;
815 }
816 if (mask == DMA_BIT_MASK(64)) {
817 mask = DMA_BIT_MASK(32);
818 fallback = true;
819 continue;
820 }
821 if (mask == DMA_BIT_MASK(32)) {
822 mask = DMA_BIT_MASK(30);
823 fallback = true;
824 continue;
825 }
826 b43legacyerr(dev->wl, "The machine/kernel does not support "
827 "the required %u-bit DMA mask\n",
828 (unsigned int)dma_mask_to_engine_type(orig_mask));
829 return -EOPNOTSUPP;
830 }
831 if (fallback) {
832 b43legacyinfo(dev->wl, "DMA mask fallback from %u-bit to %u-"
833 "bit\n",
834 (unsigned int)dma_mask_to_engine_type(orig_mask),
835 (unsigned int)dma_mask_to_engine_type(mask));
836 }
837
838 return 0;
839 }
840
841 int b43legacy_dma_init(struct b43legacy_wldev *dev)
842 {
843 struct b43legacy_dma *dma = &dev->dma;
844 struct b43legacy_dmaring *ring;
845 int err;
846 u64 dmamask;
847 enum b43legacy_dmatype type;
848
849 dmamask = supported_dma_mask(dev);
850 type = dma_mask_to_engine_type(dmamask);
851 err = b43legacy_dma_set_mask(dev, dmamask);
852 if (err) {
853 #ifdef CONFIG_B43LEGACY_PIO
854 b43legacywarn(dev->wl, "DMA for this device not supported. "
855 "Falling back to PIO\n");
856 dev->__using_pio = true;
857 return -EAGAIN;
858 #else
859 b43legacyerr(dev->wl, "DMA for this device not supported and "
860 "no PIO support compiled in\n");
861 return -EOPNOTSUPP;
862 #endif
863 }
864 dma->translation = ssb_dma_translation(dev->dev);
865
866 err = -ENOMEM;
867 /* setup TX DMA channels. */
868 ring = b43legacy_setup_dmaring(dev, 0, 1, type);
869 if (!ring)
870 goto out;
871 dma->tx_ring0 = ring;
872
873 ring = b43legacy_setup_dmaring(dev, 1, 1, type);
874 if (!ring)
875 goto err_destroy_tx0;
876 dma->tx_ring1 = ring;
877
878 ring = b43legacy_setup_dmaring(dev, 2, 1, type);
879 if (!ring)
880 goto err_destroy_tx1;
881 dma->tx_ring2 = ring;
882
883 ring = b43legacy_setup_dmaring(dev, 3, 1, type);
884 if (!ring)
885 goto err_destroy_tx2;
886 dma->tx_ring3 = ring;
887
888 ring = b43legacy_setup_dmaring(dev, 4, 1, type);
889 if (!ring)
890 goto err_destroy_tx3;
891 dma->tx_ring4 = ring;
892
893 ring = b43legacy_setup_dmaring(dev, 5, 1, type);
894 if (!ring)
895 goto err_destroy_tx4;
896 dma->tx_ring5 = ring;
897
898 /* setup RX DMA channels. */
899 ring = b43legacy_setup_dmaring(dev, 0, 0, type);
900 if (!ring)
901 goto err_destroy_tx5;
902 dma->rx_ring0 = ring;
903
904 if (dev->dev->id.revision < 5) {
905 ring = b43legacy_setup_dmaring(dev, 3, 0, type);
906 if (!ring)
907 goto err_destroy_rx0;
908 dma->rx_ring3 = ring;
909 }
910
911 b43legacydbg(dev->wl, "%u-bit DMA initialized\n", (unsigned int)type);
912 err = 0;
913 out:
914 return err;
915
916 err_destroy_rx0:
917 b43legacy_destroy_dmaring(dma->rx_ring0);
918 dma->rx_ring0 = NULL;
919 err_destroy_tx5:
920 b43legacy_destroy_dmaring(dma->tx_ring5);
921 dma->tx_ring5 = NULL;
922 err_destroy_tx4:
923 b43legacy_destroy_dmaring(dma->tx_ring4);
924 dma->tx_ring4 = NULL;
925 err_destroy_tx3:
926 b43legacy_destroy_dmaring(dma->tx_ring3);
927 dma->tx_ring3 = NULL;
928 err_destroy_tx2:
929 b43legacy_destroy_dmaring(dma->tx_ring2);
930 dma->tx_ring2 = NULL;
931 err_destroy_tx1:
932 b43legacy_destroy_dmaring(dma->tx_ring1);
933 dma->tx_ring1 = NULL;
934 err_destroy_tx0:
935 b43legacy_destroy_dmaring(dma->tx_ring0);
936 dma->tx_ring0 = NULL;
937 goto out;
938 }
939
940 /* Generate a cookie for the TX header. */
941 static u16 generate_cookie(struct b43legacy_dmaring *ring,
942 int slot)
943 {
944 u16 cookie = 0x1000;
945
946 /* Use the upper 4 bits of the cookie as
947 * DMA controller ID and store the slot number
948 * in the lower 12 bits.
949 * Note that the cookie must never be 0, as this
950 * is a special value used in RX path.
951 */
952 switch (ring->index) {
953 case 0:
954 cookie = 0xA000;
955 break;
956 case 1:
957 cookie = 0xB000;
958 break;
959 case 2:
960 cookie = 0xC000;
961 break;
962 case 3:
963 cookie = 0xD000;
964 break;
965 case 4:
966 cookie = 0xE000;
967 break;
968 case 5:
969 cookie = 0xF000;
970 break;
971 }
972 B43legacy_WARN_ON(!(((u16)slot & 0xF000) == 0x0000));
973 cookie |= (u16)slot;
974
975 return cookie;
976 }
977
978 /* Inspect a cookie and find out to which controller/slot it belongs. */
979 static
980 struct b43legacy_dmaring *parse_cookie(struct b43legacy_wldev *dev,
981 u16 cookie, int *slot)
982 {
983 struct b43legacy_dma *dma = &dev->dma;
984 struct b43legacy_dmaring *ring = NULL;
985
986 switch (cookie & 0xF000) {
987 case 0xA000:
988 ring = dma->tx_ring0;
989 break;
990 case 0xB000:
991 ring = dma->tx_ring1;
992 break;
993 case 0xC000:
994 ring = dma->tx_ring2;
995 break;
996 case 0xD000:
997 ring = dma->tx_ring3;
998 break;
999 case 0xE000:
1000 ring = dma->tx_ring4;
1001 break;
1002 case 0xF000:
1003 ring = dma->tx_ring5;
1004 break;
1005 default:
1006 B43legacy_WARN_ON(1);
1007 }
1008 *slot = (cookie & 0x0FFF);
1009 B43legacy_WARN_ON(!(ring && *slot >= 0 && *slot < ring->nr_slots));
1010
1011 return ring;
1012 }
1013
1014 static int dma_tx_fragment(struct b43legacy_dmaring *ring,
1015 struct sk_buff **in_skb)
1016 {
1017 struct sk_buff *skb = *in_skb;
1018 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1019 u8 *header;
1020 int slot, old_top_slot, old_used_slots;
1021 int err;
1022 struct b43legacy_dmadesc32 *desc;
1023 struct b43legacy_dmadesc_meta *meta;
1024 struct b43legacy_dmadesc_meta *meta_hdr;
1025 struct sk_buff *bounce_skb;
1026
1027 #define SLOTS_PER_PACKET 2
1028 B43legacy_WARN_ON(skb_shinfo(skb)->nr_frags != 0);
1029
1030 old_top_slot = ring->current_slot;
1031 old_used_slots = ring->used_slots;
1032
1033 /* Get a slot for the header. */
1034 slot = request_slot(ring);
1035 desc = op32_idx2desc(ring, slot, &meta_hdr);
1036 memset(meta_hdr, 0, sizeof(*meta_hdr));
1037
1038 header = &(ring->txhdr_cache[slot * sizeof(
1039 struct b43legacy_txhdr_fw3)]);
1040 err = b43legacy_generate_txhdr(ring->dev, header,
1041 skb->data, skb->len, info,
1042 generate_cookie(ring, slot));
1043 if (unlikely(err)) {
1044 ring->current_slot = old_top_slot;
1045 ring->used_slots = old_used_slots;
1046 return err;
1047 }
1048
1049 meta_hdr->dmaaddr = map_descbuffer(ring, (unsigned char *)header,
1050 sizeof(struct b43legacy_txhdr_fw3), 1);
1051 if (b43legacy_dma_mapping_error(ring, meta_hdr->dmaaddr,
1052 sizeof(struct b43legacy_txhdr_fw3), 1)) {
1053 ring->current_slot = old_top_slot;
1054 ring->used_slots = old_used_slots;
1055 return -EIO;
1056 }
1057 op32_fill_descriptor(ring, desc, meta_hdr->dmaaddr,
1058 sizeof(struct b43legacy_txhdr_fw3), 1, 0, 0);
1059
1060 /* Get a slot for the payload. */
1061 slot = request_slot(ring);
1062 desc = op32_idx2desc(ring, slot, &meta);
1063 memset(meta, 0, sizeof(*meta));
1064
1065 meta->skb = skb;
1066 meta->is_last_fragment = true;
1067
1068 meta->dmaaddr = map_descbuffer(ring, skb->data, skb->len, 1);
1069 /* create a bounce buffer in zone_dma on mapping failure. */
1070 if (b43legacy_dma_mapping_error(ring, meta->dmaaddr, skb->len, 1)) {
1071 bounce_skb = alloc_skb(skb->len, GFP_ATOMIC | GFP_DMA);
1072 if (!bounce_skb) {
1073 ring->current_slot = old_top_slot;
1074 ring->used_slots = old_used_slots;
1075 err = -ENOMEM;
1076 goto out_unmap_hdr;
1077 }
1078
1079 memcpy(skb_put(bounce_skb, skb->len), skb->data, skb->len);
1080 memcpy(bounce_skb->cb, skb->cb, sizeof(skb->cb));
1081 bounce_skb->dev = skb->dev;
1082 skb_set_queue_mapping(bounce_skb, skb_get_queue_mapping(skb));
1083 info = IEEE80211_SKB_CB(bounce_skb);
1084
1085 dev_kfree_skb_any(skb);
1086 skb = bounce_skb;
1087 *in_skb = bounce_skb;
1088 meta->skb = skb;
1089 meta->dmaaddr = map_descbuffer(ring, skb->data, skb->len, 1);
1090 if (b43legacy_dma_mapping_error(ring, meta->dmaaddr, skb->len, 1)) {
1091 ring->current_slot = old_top_slot;
1092 ring->used_slots = old_used_slots;
1093 err = -EIO;
1094 goto out_free_bounce;
1095 }
1096 }
1097
1098 op32_fill_descriptor(ring, desc, meta->dmaaddr,
1099 skb->len, 0, 1, 1);
1100
1101 wmb(); /* previous stuff MUST be done */
1102 /* Now transfer the whole frame. */
1103 op32_poke_tx(ring, next_slot(ring, slot));
1104 return 0;
1105
1106 out_free_bounce:
1107 dev_kfree_skb_any(skb);
1108 out_unmap_hdr:
1109 unmap_descbuffer(ring, meta_hdr->dmaaddr,
1110 sizeof(struct b43legacy_txhdr_fw3), 1);
1111 return err;
1112 }
1113
1114 static inline
1115 int should_inject_overflow(struct b43legacy_dmaring *ring)
1116 {
1117 #ifdef CONFIG_B43LEGACY_DEBUG
1118 if (unlikely(b43legacy_debug(ring->dev,
1119 B43legacy_DBG_DMAOVERFLOW))) {
1120 /* Check if we should inject another ringbuffer overflow
1121 * to test handling of this situation in the stack. */
1122 unsigned long next_overflow;
1123
1124 next_overflow = ring->last_injected_overflow + HZ;
1125 if (time_after(jiffies, next_overflow)) {
1126 ring->last_injected_overflow = jiffies;
1127 b43legacydbg(ring->dev->wl,
1128 "Injecting TX ring overflow on "
1129 "DMA controller %d\n", ring->index);
1130 return 1;
1131 }
1132 }
1133 #endif /* CONFIG_B43LEGACY_DEBUG */
1134 return 0;
1135 }
1136
1137 int b43legacy_dma_tx(struct b43legacy_wldev *dev,
1138 struct sk_buff *skb)
1139 {
1140 struct b43legacy_dmaring *ring;
1141 int err = 0;
1142
1143 ring = priority_to_txring(dev, skb_get_queue_mapping(skb));
1144 B43legacy_WARN_ON(!ring->tx);
1145
1146 if (unlikely(ring->stopped)) {
1147 /* We get here only because of a bug in mac80211.
1148 * Because of a race, one packet may be queued after
1149 * the queue is stopped, thus we got called when we shouldn't.
1150 * For now, just refuse the transmit. */
1151 if (b43legacy_debug(dev, B43legacy_DBG_DMAVERBOSE))
1152 b43legacyerr(dev->wl, "Packet after queue stopped\n");
1153 return -ENOSPC;
1154 }
1155
1156 if (unlikely(WARN_ON(free_slots(ring) < SLOTS_PER_PACKET))) {
1157 /* If we get here, we have a real error with the queue
1158 * full, but queues not stopped. */
1159 b43legacyerr(dev->wl, "DMA queue overflow\n");
1160 return -ENOSPC;
1161 }
1162
1163 /* dma_tx_fragment might reallocate the skb, so invalidate pointers pointing
1164 * into the skb data or cb now. */
1165 err = dma_tx_fragment(ring, &skb);
1166 if (unlikely(err == -ENOKEY)) {
1167 /* Drop this packet, as we don't have the encryption key
1168 * anymore and must not transmit it unencrypted. */
1169 dev_kfree_skb_any(skb);
1170 return 0;
1171 }
1172 if (unlikely(err)) {
1173 b43legacyerr(dev->wl, "DMA tx mapping failure\n");
1174 return err;
1175 }
1176 if ((free_slots(ring) < SLOTS_PER_PACKET) ||
1177 should_inject_overflow(ring)) {
1178 /* This TX ring is full. */
1179 unsigned int skb_mapping = skb_get_queue_mapping(skb);
1180 ieee80211_stop_queue(dev->wl->hw, skb_mapping);
1181 dev->wl->tx_queue_stopped[skb_mapping] = 1;
1182 ring->stopped = true;
1183 if (b43legacy_debug(dev, B43legacy_DBG_DMAVERBOSE))
1184 b43legacydbg(dev->wl, "Stopped TX ring %d\n",
1185 ring->index);
1186 }
1187 return err;
1188 }
1189
1190 void b43legacy_dma_handle_txstatus(struct b43legacy_wldev *dev,
1191 const struct b43legacy_txstatus *status)
1192 {
1193 struct b43legacy_dmaring *ring;
1194 struct b43legacy_dmadesc_meta *meta;
1195 int retry_limit;
1196 int slot;
1197 int firstused;
1198
1199 ring = parse_cookie(dev, status->cookie, &slot);
1200 if (unlikely(!ring))
1201 return;
1202 B43legacy_WARN_ON(!ring->tx);
1203
1204 /* Sanity check: TX packets are processed in-order on one ring.
1205 * Check if the slot deduced from the cookie really is the first
1206 * used slot. */
1207 firstused = ring->current_slot - ring->used_slots + 1;
1208 if (firstused < 0)
1209 firstused = ring->nr_slots + firstused;
1210 if (unlikely(slot != firstused)) {
1211 /* This possibly is a firmware bug and will result in
1212 * malfunction, memory leaks and/or stall of DMA functionality.
1213 */
1214 b43legacydbg(dev->wl, "Out of order TX status report on DMA "
1215 "ring %d. Expected %d, but got %d\n",
1216 ring->index, firstused, slot);
1217 return;
1218 }
1219
1220 while (1) {
1221 B43legacy_WARN_ON(!(slot >= 0 && slot < ring->nr_slots));
1222 op32_idx2desc(ring, slot, &meta);
1223
1224 if (meta->skb)
1225 unmap_descbuffer(ring, meta->dmaaddr,
1226 meta->skb->len, 1);
1227 else
1228 unmap_descbuffer(ring, meta->dmaaddr,
1229 sizeof(struct b43legacy_txhdr_fw3),
1230 1);
1231
1232 if (meta->is_last_fragment) {
1233 struct ieee80211_tx_info *info;
1234 BUG_ON(!meta->skb);
1235 info = IEEE80211_SKB_CB(meta->skb);
1236
1237 /* preserve the confiured retry limit before clearing the status
1238 * The xmit function has overwritten the rc's value with the actual
1239 * retry limit done by the hardware */
1240 retry_limit = info->status.rates[0].count;
1241 ieee80211_tx_info_clear_status(info);
1242
1243 if (status->acked)
1244 info->flags |= IEEE80211_TX_STAT_ACK;
1245
1246 if (status->rts_count > dev->wl->hw->conf.short_frame_max_tx_count) {
1247 /*
1248 * If the short retries (RTS, not data frame) have exceeded
1249 * the limit, the hw will not have tried the selected rate,
1250 * but will have used the fallback rate instead.
1251 * Don't let the rate control count attempts for the selected
1252 * rate in this case, otherwise the statistics will be off.
1253 */
1254 info->status.rates[0].count = 0;
1255 info->status.rates[1].count = status->frame_count;
1256 } else {
1257 if (status->frame_count > retry_limit) {
1258 info->status.rates[0].count = retry_limit;
1259 info->status.rates[1].count = status->frame_count -
1260 retry_limit;
1261
1262 } else {
1263 info->status.rates[0].count = status->frame_count;
1264 info->status.rates[1].idx = -1;
1265 }
1266 }
1267
1268 /* Call back to inform the ieee80211 subsystem about the
1269 * status of the transmission.
1270 * Some fields of txstat are already filled in dma_tx().
1271 */
1272 ieee80211_tx_status_irqsafe(dev->wl->hw, meta->skb);
1273 /* skb is freed by ieee80211_tx_status_irqsafe() */
1274 meta->skb = NULL;
1275 } else {
1276 /* No need to call free_descriptor_buffer here, as
1277 * this is only the txhdr, which is not allocated.
1278 */
1279 B43legacy_WARN_ON(meta->skb != NULL);
1280 }
1281
1282 /* Everything unmapped and free'd. So it's not used anymore. */
1283 ring->used_slots--;
1284
1285 if (meta->is_last_fragment)
1286 break;
1287 slot = next_slot(ring, slot);
1288 }
1289 dev->stats.last_tx = jiffies;
1290 if (ring->stopped) {
1291 B43legacy_WARN_ON(free_slots(ring) < SLOTS_PER_PACKET);
1292 ring->stopped = false;
1293 }
1294
1295 if (dev->wl->tx_queue_stopped[ring->queue_prio]) {
1296 dev->wl->tx_queue_stopped[ring->queue_prio] = 0;
1297 } else {
1298 /* If the driver queue is running wake the corresponding
1299 * mac80211 queue. */
1300 ieee80211_wake_queue(dev->wl->hw, ring->queue_prio);
1301 if (b43legacy_debug(dev, B43legacy_DBG_DMAVERBOSE))
1302 b43legacydbg(dev->wl, "Woke up TX ring %d\n",
1303 ring->index);
1304 }
1305 /* Add work to the queue. */
1306 ieee80211_queue_work(dev->wl->hw, &dev->wl->tx_work);
1307 }
1308
1309 static void dma_rx(struct b43legacy_dmaring *ring,
1310 int *slot)
1311 {
1312 struct b43legacy_dmadesc32 *desc;
1313 struct b43legacy_dmadesc_meta *meta;
1314 struct b43legacy_rxhdr_fw3 *rxhdr;
1315 struct sk_buff *skb;
1316 u16 len;
1317 int err;
1318 dma_addr_t dmaaddr;
1319
1320 desc = op32_idx2desc(ring, *slot, &meta);
1321
1322 sync_descbuffer_for_cpu(ring, meta->dmaaddr, ring->rx_buffersize);
1323 skb = meta->skb;
1324
1325 if (ring->index == 3) {
1326 /* We received an xmit status. */
1327 struct b43legacy_hwtxstatus *hw =
1328 (struct b43legacy_hwtxstatus *)skb->data;
1329 int i = 0;
1330
1331 while (hw->cookie == 0) {
1332 if (i > 100)
1333 break;
1334 i++;
1335 udelay(2);
1336 barrier();
1337 }
1338 b43legacy_handle_hwtxstatus(ring->dev, hw);
1339 /* recycle the descriptor buffer. */
1340 sync_descbuffer_for_device(ring, meta->dmaaddr,
1341 ring->rx_buffersize);
1342
1343 return;
1344 }
1345 rxhdr = (struct b43legacy_rxhdr_fw3 *)skb->data;
1346 len = le16_to_cpu(rxhdr->frame_len);
1347 if (len == 0) {
1348 int i = 0;
1349
1350 do {
1351 udelay(2);
1352 barrier();
1353 len = le16_to_cpu(rxhdr->frame_len);
1354 } while (len == 0 && i++ < 5);
1355 if (unlikely(len == 0)) {
1356 /* recycle the descriptor buffer. */
1357 sync_descbuffer_for_device(ring, meta->dmaaddr,
1358 ring->rx_buffersize);
1359 goto drop;
1360 }
1361 }
1362 if (unlikely(len > ring->rx_buffersize)) {
1363 /* The data did not fit into one descriptor buffer
1364 * and is split over multiple buffers.
1365 * This should never happen, as we try to allocate buffers
1366 * big enough. So simply ignore this packet.
1367 */
1368 int cnt = 0;
1369 s32 tmp = len;
1370
1371 while (1) {
1372 desc = op32_idx2desc(ring, *slot, &meta);
1373 /* recycle the descriptor buffer. */
1374 sync_descbuffer_for_device(ring, meta->dmaaddr,
1375 ring->rx_buffersize);
1376 *slot = next_slot(ring, *slot);
1377 cnt++;
1378 tmp -= ring->rx_buffersize;
1379 if (tmp <= 0)
1380 break;
1381 }
1382 b43legacyerr(ring->dev->wl, "DMA RX buffer too small "
1383 "(len: %u, buffer: %u, nr-dropped: %d)\n",
1384 len, ring->rx_buffersize, cnt);
1385 goto drop;
1386 }
1387
1388 dmaaddr = meta->dmaaddr;
1389 err = setup_rx_descbuffer(ring, desc, meta, GFP_ATOMIC);
1390 if (unlikely(err)) {
1391 b43legacydbg(ring->dev->wl, "DMA RX: setup_rx_descbuffer()"
1392 " failed\n");
1393 sync_descbuffer_for_device(ring, dmaaddr,
1394 ring->rx_buffersize);
1395 goto drop;
1396 }
1397
1398 unmap_descbuffer(ring, dmaaddr, ring->rx_buffersize, 0);
1399 skb_put(skb, len + ring->frameoffset);
1400 skb_pull(skb, ring->frameoffset);
1401
1402 b43legacy_rx(ring->dev, skb, rxhdr);
1403 drop:
1404 return;
1405 }
1406
1407 void b43legacy_dma_rx(struct b43legacy_dmaring *ring)
1408 {
1409 int slot;
1410 int current_slot;
1411 int used_slots = 0;
1412
1413 B43legacy_WARN_ON(ring->tx);
1414 current_slot = op32_get_current_rxslot(ring);
1415 B43legacy_WARN_ON(!(current_slot >= 0 && current_slot <
1416 ring->nr_slots));
1417
1418 slot = ring->current_slot;
1419 for (; slot != current_slot; slot = next_slot(ring, slot)) {
1420 dma_rx(ring, &slot);
1421 update_max_used_slots(ring, ++used_slots);
1422 }
1423 op32_set_current_rxslot(ring, slot);
1424 ring->current_slot = slot;
1425 }
1426
1427 static void b43legacy_dma_tx_suspend_ring(struct b43legacy_dmaring *ring)
1428 {
1429 B43legacy_WARN_ON(!ring->tx);
1430 op32_tx_suspend(ring);
1431 }
1432
1433 static void b43legacy_dma_tx_resume_ring(struct b43legacy_dmaring *ring)
1434 {
1435 B43legacy_WARN_ON(!ring->tx);
1436 op32_tx_resume(ring);
1437 }
1438
1439 void b43legacy_dma_tx_suspend(struct b43legacy_wldev *dev)
1440 {
1441 b43legacy_power_saving_ctl_bits(dev, -1, 1);
1442 b43legacy_dma_tx_suspend_ring(dev->dma.tx_ring0);
1443 b43legacy_dma_tx_suspend_ring(dev->dma.tx_ring1);
1444 b43legacy_dma_tx_suspend_ring(dev->dma.tx_ring2);
1445 b43legacy_dma_tx_suspend_ring(dev->dma.tx_ring3);
1446 b43legacy_dma_tx_suspend_ring(dev->dma.tx_ring4);
1447 b43legacy_dma_tx_suspend_ring(dev->dma.tx_ring5);
1448 }
1449
1450 void b43legacy_dma_tx_resume(struct b43legacy_wldev *dev)
1451 {
1452 b43legacy_dma_tx_resume_ring(dev->dma.tx_ring5);
1453 b43legacy_dma_tx_resume_ring(dev->dma.tx_ring4);
1454 b43legacy_dma_tx_resume_ring(dev->dma.tx_ring3);
1455 b43legacy_dma_tx_resume_ring(dev->dma.tx_ring2);
1456 b43legacy_dma_tx_resume_ring(dev->dma.tx_ring1);
1457 b43legacy_dma_tx_resume_ring(dev->dma.tx_ring0);
1458 b43legacy_power_saving_ctl_bits(dev, -1, -1);
1459 }
Linux kernel - Deliverables
This page took 0.06056 seconds and 6 git commands to generate.