4 #include <linux/hw_random.h>
5 #include <linux/version.h>
6 #include <linux/kernel.h>
7 #include <linux/spinlock.h>
8 #include <linux/interrupt.h>
9 #include <linux/stringify.h>
10 #include <linux/pci.h>
11 #include <net/ieee80211.h>
12 #include <net/ieee80211softmac.h>
13 #include <asm/atomic.h>
17 #include "bcm43xx_debugfs.h"
18 #include "bcm43xx_leds.h"
21 #define PFX KBUILD_MODNAME ": "
23 #define BCM43xx_SWITCH_CORE_MAX_RETRIES 50
24 #define BCM43xx_IRQWAIT_MAX_RETRIES 50
26 #define BCM43xx_IO_SIZE 8192
28 /* Active Core PCI Configuration Register. */
29 #define BCM43xx_PCICFG_ACTIVE_CORE 0x80
30 /* SPROM control register. */
31 #define BCM43xx_PCICFG_SPROMCTL 0x88
32 /* Interrupt Control PCI Configuration Register. (Only on PCI cores with rev >= 6) */
33 #define BCM43xx_PCICFG_ICR 0x94
36 #define BCM43xx_MMIO_DMA0_REASON 0x20
37 #define BCM43xx_MMIO_DMA0_IRQ_MASK 0x24
38 #define BCM43xx_MMIO_DMA1_REASON 0x28
39 #define BCM43xx_MMIO_DMA1_IRQ_MASK 0x2C
40 #define BCM43xx_MMIO_DMA2_REASON 0x30
41 #define BCM43xx_MMIO_DMA2_IRQ_MASK 0x34
42 #define BCM43xx_MMIO_DMA3_REASON 0x38
43 #define BCM43xx_MMIO_DMA3_IRQ_MASK 0x3C
44 #define BCM43xx_MMIO_DMA4_REASON 0x40
45 #define BCM43xx_MMIO_DMA4_IRQ_MASK 0x44
46 #define BCM43xx_MMIO_DMA5_REASON 0x48
47 #define BCM43xx_MMIO_DMA5_IRQ_MASK 0x4C
48 #define BCM43xx_MMIO_STATUS_BITFIELD 0x120
49 #define BCM43xx_MMIO_STATUS2_BITFIELD 0x124
50 #define BCM43xx_MMIO_GEN_IRQ_REASON 0x128
51 #define BCM43xx_MMIO_GEN_IRQ_MASK 0x12C
52 #define BCM43xx_MMIO_RAM_CONTROL 0x130
53 #define BCM43xx_MMIO_RAM_DATA 0x134
54 #define BCM43xx_MMIO_PS_STATUS 0x140
55 #define BCM43xx_MMIO_RADIO_HWENABLED_HI 0x158
56 #define BCM43xx_MMIO_SHM_CONTROL 0x160
57 #define BCM43xx_MMIO_SHM_DATA 0x164
58 #define BCM43xx_MMIO_SHM_DATA_UNALIGNED 0x166
59 #define BCM43xx_MMIO_XMITSTAT_0 0x170
60 #define BCM43xx_MMIO_XMITSTAT_1 0x174
61 #define BCM43xx_MMIO_REV3PLUS_TSF_LOW 0x180 /* core rev >= 3 only */
62 #define BCM43xx_MMIO_REV3PLUS_TSF_HIGH 0x184 /* core rev >= 3 only */
65 #define BCM43xx_MMIO_DMA32_BASE0 0x200
66 #define BCM43xx_MMIO_DMA32_BASE1 0x220
67 #define BCM43xx_MMIO_DMA32_BASE2 0x240
68 #define BCM43xx_MMIO_DMA32_BASE3 0x260
69 #define BCM43xx_MMIO_DMA32_BASE4 0x280
70 #define BCM43xx_MMIO_DMA32_BASE5 0x2A0
72 #define BCM43xx_MMIO_DMA64_BASE0 0x200
73 #define BCM43xx_MMIO_DMA64_BASE1 0x240
74 #define BCM43xx_MMIO_DMA64_BASE2 0x280
75 #define BCM43xx_MMIO_DMA64_BASE3 0x2C0
76 #define BCM43xx_MMIO_DMA64_BASE4 0x300
77 #define BCM43xx_MMIO_DMA64_BASE5 0x340
79 #define BCM43xx_MMIO_PIO1_BASE 0x300
80 #define BCM43xx_MMIO_PIO2_BASE 0x310
81 #define BCM43xx_MMIO_PIO3_BASE 0x320
82 #define BCM43xx_MMIO_PIO4_BASE 0x330
84 #define BCM43xx_MMIO_PHY_VER 0x3E0
85 #define BCM43xx_MMIO_PHY_RADIO 0x3E2
86 #define BCM43xx_MMIO_ANTENNA 0x3E8
87 #define BCM43xx_MMIO_CHANNEL 0x3F0
88 #define BCM43xx_MMIO_CHANNEL_EXT 0x3F4
89 #define BCM43xx_MMIO_RADIO_CONTROL 0x3F6
90 #define BCM43xx_MMIO_RADIO_DATA_HIGH 0x3F8
91 #define BCM43xx_MMIO_RADIO_DATA_LOW 0x3FA
92 #define BCM43xx_MMIO_PHY_CONTROL 0x3FC
93 #define BCM43xx_MMIO_PHY_DATA 0x3FE
94 #define BCM43xx_MMIO_MACFILTER_CONTROL 0x420
95 #define BCM43xx_MMIO_MACFILTER_DATA 0x422
96 #define BCM43xx_MMIO_RADIO_HWENABLED_LO 0x49A
97 #define BCM43xx_MMIO_GPIO_CONTROL 0x49C
98 #define BCM43xx_MMIO_GPIO_MASK 0x49E
99 #define BCM43xx_MMIO_TSF_0 0x632 /* core rev < 3 only */
100 #define BCM43xx_MMIO_TSF_1 0x634 /* core rev < 3 only */
101 #define BCM43xx_MMIO_TSF_2 0x636 /* core rev < 3 only */
102 #define BCM43xx_MMIO_TSF_3 0x638 /* core rev < 3 only */
103 #define BCM43xx_MMIO_RNG 0x65A
104 #define BCM43xx_MMIO_POWERUP_DELAY 0x6A8
107 #define BCM43xx_SPROM_BASE 0x1000
108 #define BCM43xx_SPROM_BOARDFLAGS2 0x1c
109 #define BCM43xx_SPROM_IL0MACADDR 0x24
110 #define BCM43xx_SPROM_ET0MACADDR 0x27
111 #define BCM43xx_SPROM_ET1MACADDR 0x2a
112 #define BCM43xx_SPROM_ETHPHY 0x2d
113 #define BCM43xx_SPROM_BOARDREV 0x2e
114 #define BCM43xx_SPROM_PA0B0 0x2f
115 #define BCM43xx_SPROM_PA0B1 0x30
116 #define BCM43xx_SPROM_PA0B2 0x31
117 #define BCM43xx_SPROM_WL0GPIO0 0x32
118 #define BCM43xx_SPROM_WL0GPIO2 0x33
119 #define BCM43xx_SPROM_MAXPWR 0x34
120 #define BCM43xx_SPROM_PA1B0 0x35
121 #define BCM43xx_SPROM_PA1B1 0x36
122 #define BCM43xx_SPROM_PA1B2 0x37
123 #define BCM43xx_SPROM_IDL_TSSI_TGT 0x38
124 #define BCM43xx_SPROM_BOARDFLAGS 0x39
125 #define BCM43xx_SPROM_ANTENNA_GAIN 0x3a
126 #define BCM43xx_SPROM_VERSION 0x3f
128 /* BCM43xx_SPROM_BOARDFLAGS values */
129 #define BCM43xx_BFL_BTCOEXIST 0x0001 /* implements Bluetooth coexistance */
130 #define BCM43xx_BFL_PACTRL 0x0002 /* GPIO 9 controlling the PA */
131 #define BCM43xx_BFL_AIRLINEMODE 0x0004 /* implements GPIO 13 radio disable indication */
132 #define BCM43xx_BFL_RSSI 0x0008 /* software calculates nrssi slope. */
133 #define BCM43xx_BFL_ENETSPI 0x0010 /* has ephy roboswitch spi */
134 #define BCM43xx_BFL_XTAL_NOSLOW 0x0020 /* no slow clock available */
135 #define BCM43xx_BFL_CCKHIPWR 0x0040 /* can do high power CCK transmission */
136 #define BCM43xx_BFL_ENETADM 0x0080 /* has ADMtek switch */
137 #define BCM43xx_BFL_ENETVLAN 0x0100 /* can do vlan */
138 #define BCM43xx_BFL_AFTERBURNER 0x0200 /* supports Afterburner mode */
139 #define BCM43xx_BFL_NOPCI 0x0400 /* leaves PCI floating */
140 #define BCM43xx_BFL_FEM 0x0800 /* supports the Front End Module */
141 #define BCM43xx_BFL_EXTLNA 0x1000 /* has an external LNA */
142 #define BCM43xx_BFL_HGPA 0x2000 /* had high gain PA */
143 #define BCM43xx_BFL_BTCMOD 0x4000 /* BFL_BTCOEXIST is given in alternate GPIOs */
144 #define BCM43xx_BFL_ALTIQ 0x8000 /* alternate I/Q settings */
146 /* GPIO register offset, in both ChipCommon and PCI core. */
147 #define BCM43xx_GPIO_CONTROL 0x6c
150 #define BCM43xx_SHM_SHARED 0x0001
151 #define BCM43xx_SHM_WIRELESS 0x0002
152 #define BCM43xx_SHM_PCM 0x0003
153 #define BCM43xx_SHM_HWMAC 0x0004
154 #define BCM43xx_SHM_UCODE 0x0300
156 /* MacFilter offsets. */
157 #define BCM43xx_MACFILTER_SELF 0x0000
158 #define BCM43xx_MACFILTER_ASSOC 0x0003
160 /* Chipcommon registers. */
161 #define BCM43xx_CHIPCOMMON_CAPABILITIES 0x04
162 #define BCM43xx_CHIPCOMMON_PLLONDELAY 0xB0
163 #define BCM43xx_CHIPCOMMON_FREFSELDELAY 0xB4
164 #define BCM43xx_CHIPCOMMON_SLOWCLKCTL 0xB8
165 #define BCM43xx_CHIPCOMMON_SYSCLKCTL 0xC0
167 /* PCI core specific registers. */
168 #define BCM43xx_PCICORE_BCAST_ADDR 0x50
169 #define BCM43xx_PCICORE_BCAST_DATA 0x54
170 #define BCM43xx_PCICORE_SBTOPCI2 0x108
172 /* SBTOPCI2 values. */
173 #define BCM43xx_SBTOPCI2_PREFETCH 0x4
174 #define BCM43xx_SBTOPCI2_BURST 0x8
176 /* Chipcommon capabilities. */
177 #define BCM43xx_CAPABILITIES_PCTL 0x00040000
178 #define BCM43xx_CAPABILITIES_PLLMASK 0x00030000
179 #define BCM43xx_CAPABILITIES_PLLSHIFT 16
180 #define BCM43xx_CAPABILITIES_FLASHMASK 0x00000700
181 #define BCM43xx_CAPABILITIES_FLASHSHIFT 8
182 #define BCM43xx_CAPABILITIES_EXTBUSPRESENT 0x00000040
183 #define BCM43xx_CAPABILITIES_UARTGPIO 0x00000020
184 #define BCM43xx_CAPABILITIES_UARTCLOCKMASK 0x00000018
185 #define BCM43xx_CAPABILITIES_UARTCLOCKSHIFT 3
186 #define BCM43xx_CAPABILITIES_MIPSBIGENDIAN 0x00000004
187 #define BCM43xx_CAPABILITIES_NRUARTSMASK 0x00000003
190 #define BCM43xx_PCTL_IN 0xB0
191 #define BCM43xx_PCTL_OUT 0xB4
192 #define BCM43xx_PCTL_OUTENABLE 0xB8
193 #define BCM43xx_PCTL_XTAL_POWERUP 0x40
194 #define BCM43xx_PCTL_PLL_POWERDOWN 0x80
196 /* PowerControl Clock Modes */
197 #define BCM43xx_PCTL_CLK_FAST 0x00
198 #define BCM43xx_PCTL_CLK_SLOW 0x01
199 #define BCM43xx_PCTL_CLK_DYNAMIC 0x02
201 #define BCM43xx_PCTL_FORCE_SLOW 0x0800
202 #define BCM43xx_PCTL_FORCE_PLL 0x1000
203 #define BCM43xx_PCTL_DYN_XTAL 0x2000
206 #define BCM43xx_COREID_CHIPCOMMON 0x800
207 #define BCM43xx_COREID_ILINE20 0x801
208 #define BCM43xx_COREID_SDRAM 0x803
209 #define BCM43xx_COREID_PCI 0x804
210 #define BCM43xx_COREID_MIPS 0x805
211 #define BCM43xx_COREID_ETHERNET 0x806
212 #define BCM43xx_COREID_V90 0x807
213 #define BCM43xx_COREID_USB11_HOSTDEV 0x80a
214 #define BCM43xx_COREID_IPSEC 0x80b
215 #define BCM43xx_COREID_PCMCIA 0x80d
216 #define BCM43xx_COREID_EXT_IF 0x80f
217 #define BCM43xx_COREID_80211 0x812
218 #define BCM43xx_COREID_MIPS_3302 0x816
219 #define BCM43xx_COREID_USB11_HOST 0x817
220 #define BCM43xx_COREID_USB11_DEV 0x818
221 #define BCM43xx_COREID_USB20_HOST 0x819
222 #define BCM43xx_COREID_USB20_DEV 0x81a
223 #define BCM43xx_COREID_SDIO_HOST 0x81b
225 /* Core Information Registers */
226 #define BCM43xx_CIR_BASE 0xf00
227 #define BCM43xx_CIR_SBTPSFLAG (BCM43xx_CIR_BASE + 0x18)
228 #define BCM43xx_CIR_SBIMSTATE (BCM43xx_CIR_BASE + 0x90)
229 #define BCM43xx_CIR_SBINTVEC (BCM43xx_CIR_BASE + 0x94)
230 #define BCM43xx_CIR_SBTMSTATELOW (BCM43xx_CIR_BASE + 0x98)
231 #define BCM43xx_CIR_SBTMSTATEHIGH (BCM43xx_CIR_BASE + 0x9c)
232 #define BCM43xx_CIR_SBIMCONFIGLOW (BCM43xx_CIR_BASE + 0xa8)
233 #define BCM43xx_CIR_SB_ID_HI (BCM43xx_CIR_BASE + 0xfc)
235 /* Mask to get the Backplane Flag Number from SBTPSFLAG. */
236 #define BCM43xx_BACKPLANE_FLAG_NR_MASK 0x3f
238 /* SBIMCONFIGLOW values/masks. */
239 #define BCM43xx_SBIMCONFIGLOW_SERVICE_TOUT_MASK 0x00000007
240 #define BCM43xx_SBIMCONFIGLOW_SERVICE_TOUT_SHIFT 0
241 #define BCM43xx_SBIMCONFIGLOW_REQUEST_TOUT_MASK 0x00000070
242 #define BCM43xx_SBIMCONFIGLOW_REQUEST_TOUT_SHIFT 4
243 #define BCM43xx_SBIMCONFIGLOW_CONNID_MASK 0x00ff0000
244 #define BCM43xx_SBIMCONFIGLOW_CONNID_SHIFT 16
246 /* sbtmstatelow state flags */
247 #define BCM43xx_SBTMSTATELOW_RESET 0x01
248 #define BCM43xx_SBTMSTATELOW_REJECT 0x02
249 #define BCM43xx_SBTMSTATELOW_CLOCK 0x10000
250 #define BCM43xx_SBTMSTATELOW_FORCE_GATE_CLOCK 0x20000
252 /* sbtmstatehigh state flags */
253 #define BCM43xx_SBTMSTATEHIGH_SERROR 0x00000001
254 #define BCM43xx_SBTMSTATEHIGH_BUSY 0x00000004
255 #define BCM43xx_SBTMSTATEHIGH_TIMEOUT 0x00000020
256 #define BCM43xx_SBTMSTATEHIGH_COREFLAGS 0x1FFF0000
257 #define BCM43xx_SBTMSTATEHIGH_DMA64BIT 0x10000000
258 #define BCM43xx_SBTMSTATEHIGH_GATEDCLK 0x20000000
259 #define BCM43xx_SBTMSTATEHIGH_BISTFAILED 0x40000000
260 #define BCM43xx_SBTMSTATEHIGH_BISTCOMPLETE 0x80000000
262 /* sbimstate flags */
263 #define BCM43xx_SBIMSTATE_IB_ERROR 0x20000
264 #define BCM43xx_SBIMSTATE_TIMEOUT 0x40000
267 #define BCM43xx_PHYTYPE_A 0x00
268 #define BCM43xx_PHYTYPE_B 0x01
269 #define BCM43xx_PHYTYPE_G 0x02
272 #define BCM43xx_PHY_ILT_A_CTRL 0x0072
273 #define BCM43xx_PHY_ILT_A_DATA1 0x0073
274 #define BCM43xx_PHY_ILT_A_DATA2 0x0074
275 #define BCM43xx_PHY_G_LO_CONTROL 0x0810
276 #define BCM43xx_PHY_ILT_G_CTRL 0x0472
277 #define BCM43xx_PHY_ILT_G_DATA1 0x0473
278 #define BCM43xx_PHY_ILT_G_DATA2 0x0474
279 #define BCM43xx_PHY_A_PCTL 0x007B
280 #define BCM43xx_PHY_G_PCTL 0x0029
281 #define BCM43xx_PHY_A_CRS 0x0029
282 #define BCM43xx_PHY_RADIO_BITFIELD 0x0401
283 #define BCM43xx_PHY_G_CRS 0x0429
284 #define BCM43xx_PHY_NRSSILT_CTRL 0x0803
285 #define BCM43xx_PHY_NRSSILT_DATA 0x0804
288 #define BCM43xx_RADIOCTL_ID 0x01
291 #define BCM43xx_SBF_MAC_ENABLED 0x00000001
292 #define BCM43xx_SBF_2 0x00000002 /*FIXME: fix name*/
293 #define BCM43xx_SBF_CORE_READY 0x00000004
294 #define BCM43xx_SBF_400 0x00000400 /*FIXME: fix name*/
295 #define BCM43xx_SBF_4000 0x00004000 /*FIXME: fix name*/
296 #define BCM43xx_SBF_8000 0x00008000 /*FIXME: fix name*/
297 #define BCM43xx_SBF_XFER_REG_BYTESWAP 0x00010000
298 #define BCM43xx_SBF_MODE_NOTADHOC 0x00020000
299 #define BCM43xx_SBF_MODE_AP 0x00040000
300 #define BCM43xx_SBF_RADIOREG_LOCK 0x00080000
301 #define BCM43xx_SBF_MODE_MONITOR 0x00400000
302 #define BCM43xx_SBF_MODE_PROMISC 0x01000000
303 #define BCM43xx_SBF_PS1 0x02000000
304 #define BCM43xx_SBF_PS2 0x04000000
305 #define BCM43xx_SBF_NO_SSID_BCAST 0x08000000
306 #define BCM43xx_SBF_TIME_UPDATE 0x10000000
307 #define BCM43xx_SBF_80000000 0x80000000 /*FIXME: fix name*/
310 #define BCM43xx_UCODE_REVISION 0x0000
311 #define BCM43xx_UCODE_PATCHLEVEL 0x0002
312 #define BCM43xx_UCODE_DATE 0x0004
313 #define BCM43xx_UCODE_TIME 0x0006
315 /* MicrocodeFlagsBitfield (addr + lo-word values?)*/
316 #define BCM43xx_UCODEFLAGS_OFFSET 0x005E
318 #define BCM43xx_UCODEFLAG_AUTODIV 0x0001
319 #define BCM43xx_UCODEFLAG_UNKBGPHY 0x0002
320 #define BCM43xx_UCODEFLAG_UNKBPHY 0x0004
321 #define BCM43xx_UCODEFLAG_UNKGPHY 0x0020
322 #define BCM43xx_UCODEFLAG_UNKPACTRL 0x0040
323 #define BCM43xx_UCODEFLAG_JAPAN 0x0080
325 /* Generic-Interrupt reasons. */
326 #define BCM43xx_IRQ_READY (1 << 0)
327 #define BCM43xx_IRQ_BEACON (1 << 1)
328 #define BCM43xx_IRQ_PS (1 << 2)
329 #define BCM43xx_IRQ_REG124 (1 << 5)
330 #define BCM43xx_IRQ_PMQ (1 << 6)
331 #define BCM43xx_IRQ_PIO_WORKAROUND (1 << 8)
332 #define BCM43xx_IRQ_XMIT_ERROR (1 << 11)
333 #define BCM43xx_IRQ_RX (1 << 15)
334 #define BCM43xx_IRQ_SCAN (1 << 16)
335 #define BCM43xx_IRQ_NOISE (1 << 18)
336 #define BCM43xx_IRQ_XMIT_STATUS (1 << 29)
338 #define BCM43xx_IRQ_ALL 0xffffffff
339 #define BCM43xx_IRQ_INITIAL (BCM43xx_IRQ_PS | \
340 BCM43xx_IRQ_REG124 | \
342 BCM43xx_IRQ_XMIT_ERROR | \
345 BCM43xx_IRQ_NOISE | \
346 BCM43xx_IRQ_XMIT_STATUS)
349 /* Initial default iw_mode */
350 #define BCM43xx_INITIAL_IWMODE IW_MODE_INFRA
353 #define BCM43xx_BUSTYPE_PCI 0
354 /* Bus type Silicone Backplane Bus. */
355 #define BCM43xx_BUSTYPE_SB 1
356 /* Bus type PCMCIA. */
357 #define BCM43xx_BUSTYPE_PCMCIA 2
359 /* Threshold values. */
360 #define BCM43xx_MIN_RTS_THRESHOLD 1U
361 #define BCM43xx_MAX_RTS_THRESHOLD 2304U
362 #define BCM43xx_DEFAULT_RTS_THRESHOLD BCM43xx_MAX_RTS_THRESHOLD
364 #define BCM43xx_DEFAULT_SHORT_RETRY_LIMIT 7
365 #define BCM43xx_DEFAULT_LONG_RETRY_LIMIT 4
367 /* Max size of a security key */
368 #define BCM43xx_SEC_KEYSIZE 16
369 /* Security algorithms. */
371 BCM43xx_SEC_ALGO_NONE
= 0, /* unencrypted, as of TX header. */
372 BCM43xx_SEC_ALGO_WEP
,
373 BCM43xx_SEC_ALGO_UNKNOWN
,
374 BCM43xx_SEC_ALGO_AES
,
375 BCM43xx_SEC_ALGO_WEP104
,
376 BCM43xx_SEC_ALGO_TKIP
,
382 #ifdef CONFIG_BCM43XX_DEBUG
383 #define assert(expr) \
385 if (unlikely(!(expr))) { \
386 printk(KERN_ERR PFX "ASSERTION FAILED (%s) at: %s:%d:%s()\n", \
387 #expr, __FILE__, __LINE__, __FUNCTION__); \
391 #define assert(expr) do { /* nothing */ } while (0)
394 /* rate limited printk(). */
398 #define printkl(f, x...) do { if (printk_ratelimit()) printk(f ,##x); } while (0)
399 /* rate limited printk() for debugging */
403 #ifdef CONFIG_BCM43XX_DEBUG
404 # define dprintkl printkl
406 # define dprintkl(f, x...) do { /* nothing */ } while (0)
409 /* Helper macro for if branches.
410 * An if branch marked with this macro is only taken in DEBUG mode.
412 * if (DEBUG_ONLY(foo == bar)) {
415 * In DEBUG mode, the branch will be taken if (foo == bar).
416 * In non-DEBUG mode, the branch will never be taken.
421 #ifdef CONFIG_BCM43XX_DEBUG
422 # define DEBUG_ONLY(x) (x)
424 # define DEBUG_ONLY(x) 0
427 /* debugging printk() */
431 #ifdef CONFIG_BCM43XX_DEBUG
432 # define dprintk(f, x...) do { printk(f ,##x); } while (0)
434 # define dprintk(f, x...) do { /* nothing */ } while (0)
440 struct bcm43xx_dmaring
;
441 struct bcm43xx_pioqueue
;
443 struct bcm43xx_initval
{
447 } __attribute__((__packed__
));
449 /* Values for bcm430x_sprominfo.locale */
451 BCM43xx_LOCALE_WORLD
= 0,
452 BCM43xx_LOCALE_THAILAND
,
453 BCM43xx_LOCALE_ISRAEL
,
454 BCM43xx_LOCALE_JORDAN
,
455 BCM43xx_LOCALE_CHINA
,
456 BCM43xx_LOCALE_JAPAN
,
457 BCM43xx_LOCALE_USA_CANADA_ANZ
,
458 BCM43xx_LOCALE_EUROPE
,
459 BCM43xx_LOCALE_USA_LOW
,
460 BCM43xx_LOCALE_JAPAN_HIGH
,
465 #define BCM43xx_SPROM_SIZE 64 /* in 16-bit words. */
466 struct bcm43xx_sprominfo
{
491 u8 idle_tssi_tgt_aphy
;
492 u8 idle_tssi_tgt_bgphy
;
494 u16 antennagain_aphy
;
495 u16 antennagain_bgphy
;
498 /* Value pair to measure the LocalOscillator. */
499 struct bcm43xx_lopair
{
504 #define BCM43xx_LO_COUNT (14*4)
506 struct bcm43xx_phyinfo
{
511 u16 antenna_diversity
;
517 is_locked
:1, /* used in bcm43xx_phy_{un}lock() */
518 dyn_tssi_tbl
:1; /* used in bcm43xx_phy_init_tssi2dbm_table() */
519 /* LO Measurement Data.
520 * Use bcm43xx_get_lopair() to get a value.
522 struct bcm43xx_lopair
*_lo_pairs
;
524 /* TSSI to dBm table in use */
526 /* idle TSSI value */
529 /* Values from bcm43xx_calc_loopback_gain() */
530 u16 loopback_gain
[2];
532 /* PHY lock for core.rev < 3
533 * This lock is only used by bcm43xx_phy_{un}lock()
538 const struct firmware
*ucode
;
539 const struct firmware
*pcm
;
540 const struct firmware
*initvals0
;
541 const struct firmware
*initvals1
;
545 struct bcm43xx_radioinfo
{
550 /* Desired TX power in dBm Q5.2 */
552 /* TX Power control values. */
567 /* Current Interference Mitigation mode */
569 /* Stack of saved values from the Interference Mitigation code.
570 * Each value in the stack is layed out as follows:
572 * bit 12-15: register ID
574 * register ID is: 0x1 PHY, 0x2 Radio, 0x3 ILT
576 #define BCM43xx_INTERFSTACK_SIZE 26
577 u32 interfstack
[BCM43xx_INTERFSTACK_SIZE
];
579 /* Saved values from the NRSSI Slope calculation */
582 /* In memory nrssi lookup table. */
585 /* current channel */
594 /* ACI (adjacent channel interference) flags. */
596 aci_wlan_automatic
:1,
600 /* Data structures for DMA transmission, per 80211 core. */
602 struct bcm43xx_dmaring
*tx_ring0
;
603 struct bcm43xx_dmaring
*tx_ring1
;
604 struct bcm43xx_dmaring
*tx_ring2
;
605 struct bcm43xx_dmaring
*tx_ring3
;
606 struct bcm43xx_dmaring
*tx_ring4
;
607 struct bcm43xx_dmaring
*tx_ring5
;
609 struct bcm43xx_dmaring
*rx_ring0
;
610 struct bcm43xx_dmaring
*rx_ring3
; /* only available on core.rev < 5 */
613 /* Data structures for PIO transmission, per 80211 core. */
615 struct bcm43xx_pioqueue
*queue0
;
616 struct bcm43xx_pioqueue
*queue1
;
617 struct bcm43xx_pioqueue
*queue2
;
618 struct bcm43xx_pioqueue
*queue3
;
621 #define BCM43xx_MAX_80211_CORES 2
623 #ifdef CONFIG_BCM947XX
624 #define core_offset(bcm) (bcm)->current_core_offset
626 #define core_offset(bcm) 0
629 /* Generic information about a core. */
630 struct bcm43xx_coreinfo
{
634 /** core_rev revision number */
636 /** Index number for _switch_core() */
638 /** core_id ID number */
640 /** Core-specific data. */
644 /* Additional information for each 80211 core. */
645 struct bcm43xx_coreinfo_80211
{
647 struct bcm43xx_phyinfo phy
;
649 struct bcm43xx_radioinfo radio
;
652 struct bcm43xx_dma dma
;
654 struct bcm43xx_pio pio
;
658 /* Context information for a noise calculation (Link Quality). */
659 struct bcm43xx_noise_calculation
{
660 struct bcm43xx_coreinfo
*core_at_start
;
662 u8 calculation_running
:1;
667 struct bcm43xx_stats
{
670 struct iw_statistics wstats
;
671 /* Store the last TX/RX times here for updating the leds. */
672 unsigned long last_tx
;
673 unsigned long last_rx
;
681 /* Driver initialization status. */
683 BCM43xx_STAT_UNINIT
, /* Uninitialized. */
684 BCM43xx_STAT_INITIALIZING
, /* init_board() in progress. */
685 BCM43xx_STAT_INITIALIZED
, /* Fully operational. */
686 BCM43xx_STAT_SHUTTINGDOWN
, /* free_board() in progress. */
687 BCM43xx_STAT_RESTARTING
, /* controller_restart() called. */
689 #define bcm43xx_status(bcm) atomic_read(&(bcm)->init_status)
690 #define bcm43xx_set_status(bcm, stat) do { \
691 atomic_set(&(bcm)->init_status, (stat)); \
695 /* *** THEORY OF LOCKING ***
697 * We have two different locks in the bcm43xx driver.
698 * => bcm->mutex: General sleeping mutex. Protects struct bcm43xx_private
699 * and the device registers. This mutex does _not_ protect
700 * against concurrency from the IRQ handler.
701 * => bcm->irq_lock: IRQ spinlock. Protects against IRQ handler concurrency.
703 * Please note that, if you only take the irq_lock, you are not protected
704 * against concurrency from the periodic work handlers.
705 * Most times you want to take _both_ locks.
708 struct bcm43xx_private
{
709 struct ieee80211_device
*ieee
;
710 struct ieee80211softmac_device
*softmac
;
712 struct net_device
*net_dev
;
713 struct pci_dev
*pci_dev
;
716 void __iomem
*mmio_addr
;
721 /* Driver initialization status BCM43xx_STAT_*** */
722 atomic_t init_status
;
724 u16 was_initialized
:1, /* for PCI suspend/resume. */
725 __using_pio
:1, /* Internal, use bcm43xx_using_pio(). */
726 bad_frames_preempt
:1, /* Use "Bad Frames Preemption" (default off) */
727 reg124_set_0x4
:1, /* Some variable to keep track of IRQ stuff. */
728 short_preamble
:1, /* TRUE, if short preamble is enabled. */
729 firmware_norelease
:1; /* Do not release the firmware. Used on suspend. */
731 struct bcm43xx_stats stats
;
733 /* Bus type we are connected to.
734 * This is currently always BCM43xx_BUSTYPE_PCI
746 struct bcm43xx_sprominfo sprom
;
747 #define BCM43xx_NR_LEDS 4
748 struct bcm43xx_led leds
[BCM43xx_NR_LEDS
];
749 spinlock_t leds_lock
;
751 /* The currently active core. */
752 struct bcm43xx_coreinfo
*current_core
;
753 #ifdef CONFIG_BCM947XX
754 /** current core memory offset */
755 u32 current_core_offset
;
757 struct bcm43xx_coreinfo
*active_80211_core
;
758 /* coreinfo structs for all possible cores follow.
759 * Note that a core might not exist.
760 * So check the coreinfo flags before using it.
762 struct bcm43xx_coreinfo core_chipcommon
;
763 struct bcm43xx_coreinfo core_pci
;
764 struct bcm43xx_coreinfo core_80211
[ BCM43xx_MAX_80211_CORES
];
765 /* Additional information, specific to the 80211 cores. */
766 struct bcm43xx_coreinfo_80211 core_80211_ext
[ BCM43xx_MAX_80211_CORES
];
767 /* Number of available 80211 cores. */
768 int nr_80211_available
;
770 u32 chipcommon_capabilities
;
772 /* Reason code of the last interrupt. */
775 /* saved irq enable/disable state bitfield. */
777 /* Link Quality calculation context. */
778 struct bcm43xx_noise_calculation noisecalc
;
779 /* if > 0 MAC is suspended. if == 0 MAC is enabled. */
782 /* Threshold values. */
783 //TODO: The RTS thr has to be _used_. Currently, it is only set via WX.
786 /* Interrupt Service Routine tasklet (bottom-half) */
787 struct tasklet_struct isr_tasklet
;
790 struct work_struct periodic_work
;
791 unsigned int periodic_state
;
793 struct work_struct restart_work
;
795 /* Informational stuff. */
796 char nick
[IW_ESSID_MAX_SIZE
+ 1];
798 /* encryption/decryption */
800 struct bcm43xx_key key
[54];
803 /* Random Number Generator. */
805 char rng_name
[20 + 1];
807 /* Debugging stuff follows. */
808 #ifdef CONFIG_BCM43XX_DEBUG
809 struct bcm43xx_dfsentry
*dfsentry
;
815 struct bcm43xx_private
* bcm43xx_priv(struct net_device
*dev
)
817 return ieee80211softmac_priv(dev
);
823 struct bcm43xx_private
* dev_to_bcm(struct device
*dev
)
825 struct net_device
*net_dev
;
826 struct bcm43xx_private
*bcm
;
828 net_dev
= dev_get_drvdata(dev
);
829 bcm
= bcm43xx_priv(net_dev
);
835 /* Helper function, which returns a boolean.
836 * TRUE, if PIO is used; FALSE, if DMA is used.
838 #if defined(CONFIG_BCM43XX_DMA) && defined(CONFIG_BCM43XX_PIO)
840 int bcm43xx_using_pio(struct bcm43xx_private
*bcm
)
842 return bcm
->__using_pio
;
844 #elif defined(CONFIG_BCM43XX_DMA)
846 int bcm43xx_using_pio(struct bcm43xx_private
*bcm
)
850 #elif defined(CONFIG_BCM43XX_PIO)
852 int bcm43xx_using_pio(struct bcm43xx_private
*bcm
)
857 # error "Using neither DMA nor PIO? Confused..."
860 /* Helper functions to access data structures private to the 80211 cores.
861 * Note that we _must_ have an 80211 core mapped when calling
862 * any of these functions.
865 struct bcm43xx_coreinfo_80211
*
866 bcm43xx_current_80211_priv(struct bcm43xx_private
*bcm
)
868 assert(bcm
->current_core
->id
== BCM43xx_COREID_80211
);
869 return bcm
->current_core
->priv
;
872 struct bcm43xx_pio
* bcm43xx_current_pio(struct bcm43xx_private
*bcm
)
874 assert(bcm43xx_using_pio(bcm
));
875 return &(bcm43xx_current_80211_priv(bcm
)->pio
);
878 struct bcm43xx_dma
* bcm43xx_current_dma(struct bcm43xx_private
*bcm
)
880 assert(!bcm43xx_using_pio(bcm
));
881 return &(bcm43xx_current_80211_priv(bcm
)->dma
);
884 struct bcm43xx_phyinfo
* bcm43xx_current_phy(struct bcm43xx_private
*bcm
)
886 return &(bcm43xx_current_80211_priv(bcm
)->phy
);
889 struct bcm43xx_radioinfo
* bcm43xx_current_radio(struct bcm43xx_private
*bcm
)
891 return &(bcm43xx_current_80211_priv(bcm
)->radio
);
896 struct bcm43xx_lopair
* bcm43xx_get_lopair(struct bcm43xx_phyinfo
*phy
,
897 u16 radio_attenuation
,
898 u16 baseband_attenuation
)
900 return phy
->_lo_pairs
+ (radio_attenuation
+ 14 * (baseband_attenuation
/ 2));
905 u16
bcm43xx_read16(struct bcm43xx_private
*bcm
, u16 offset
)
907 return ioread16(bcm
->mmio_addr
+ core_offset(bcm
) + offset
);
911 void bcm43xx_write16(struct bcm43xx_private
*bcm
, u16 offset
, u16 value
)
913 iowrite16(value
, bcm
->mmio_addr
+ core_offset(bcm
) + offset
);
917 u32
bcm43xx_read32(struct bcm43xx_private
*bcm
, u16 offset
)
919 return ioread32(bcm
->mmio_addr
+ core_offset(bcm
) + offset
);
923 void bcm43xx_write32(struct bcm43xx_private
*bcm
, u16 offset
, u32 value
)
925 iowrite32(value
, bcm
->mmio_addr
+ core_offset(bcm
) + offset
);
929 int bcm43xx_pci_read_config16(struct bcm43xx_private
*bcm
, int offset
, u16
*value
)
931 return pci_read_config_word(bcm
->pci_dev
, offset
, value
);
935 int bcm43xx_pci_read_config32(struct bcm43xx_private
*bcm
, int offset
, u32
*value
)
937 return pci_read_config_dword(bcm
->pci_dev
, offset
, value
);
941 int bcm43xx_pci_write_config16(struct bcm43xx_private
*bcm
, int offset
, u16 value
)
943 return pci_write_config_word(bcm
->pci_dev
, offset
, value
);
947 int bcm43xx_pci_write_config32(struct bcm43xx_private
*bcm
, int offset
, u32 value
)
949 return pci_write_config_dword(bcm
->pci_dev
, offset
, value
);
952 /** Limit a value between two limits */
956 #define limit_value(value, min, max) \
958 typeof(value) __value = (value); \
959 typeof(value) __min = (min); \
960 typeof(value) __max = (max); \
961 if (__value < __min) \
963 else if (__value > __max) \
968 /** Helpers to print MAC addresses. */
969 #define BCM43xx_MACFMT "%02x:%02x:%02x:%02x:%02x:%02x"
970 #define BCM43xx_MACARG(x) ((u8*)(x))[0], ((u8*)(x))[1], \
971 ((u8*)(x))[2], ((u8*)(x))[3], \
972 ((u8*)(x))[4], ((u8*)(x))[5]
974 #endif /* BCM43xx_H_ */