drivers/net/wireless/bcm43xx/bcm43xx.h

   1 #ifndef BCM43xx_H_
   2 #define BCM43xx_H_
   3
   4 #include <linux/hw_random.h>
   5 #include <linux/version.h>
   6 #include <linux/kernel.h>
   7 #include <linux/spinlock.h>
   8 #include <linux/interrupt.h>
   9 #include <linux/stringify.h>
  10 #include <linux/pci.h>
  11 #include <net/ieee80211.h>
  12 #include <net/ieee80211softmac.h>
  13 #include <asm/atomic.h>
  14 #include <asm/io.h>
  15
  16
  17 #include "bcm43xx_debugfs.h"
  18 #include "bcm43xx_leds.h"
  19
  20
  21 #define PFX                             KBUILD_MODNAME ": "
  22
  23 #define BCM43xx_SWITCH_CORE_MAX_RETRIES 50
  24 #define BCM43xx_IRQWAIT_MAX_RETRIES     50
  25
  26 #define BCM43xx_IO_SIZE                 8192
  27
  28 /* Active Core PCI Configuration Register. */
  29 #define BCM43xx_PCICFG_ACTIVE_CORE      0x80
  30 /* SPROM control register. */
  31 #define BCM43xx_PCICFG_SPROMCTL         0x88
  32 /* Interrupt Control PCI Configuration Register. (Only on PCI cores with rev >= 6) */
  33 #define BCM43xx_PCICFG_ICR              0x94
  34
  35 /* MMIO offsets */
  36 #define BCM43xx_MMIO_DMA1_REASON        0x20
  37 #define BCM43xx_MMIO_DMA1_IRQ_MASK      0x24
  38 #define BCM43xx_MMIO_DMA2_REASON        0x28
  39 #define BCM43xx_MMIO_DMA2_IRQ_MASK      0x2C
  40 #define BCM43xx_MMIO_DMA3_REASON        0x30
  41 #define BCM43xx_MMIO_DMA3_IRQ_MASK      0x34
  42 #define BCM43xx_MMIO_DMA4_REASON        0x38
  43 #define BCM43xx_MMIO_DMA4_IRQ_MASK      0x3C
  44 #define BCM43xx_MMIO_STATUS_BITFIELD    0x120
  45 #define BCM43xx_MMIO_STATUS2_BITFIELD   0x124
  46 #define BCM43xx_MMIO_GEN_IRQ_REASON     0x128
  47 #define BCM43xx_MMIO_GEN_IRQ_MASK       0x12C
  48 #define BCM43xx_MMIO_RAM_CONTROL        0x130
  49 #define BCM43xx_MMIO_RAM_DATA           0x134
  50 #define BCM43xx_MMIO_PS_STATUS          0x140
  51 #define BCM43xx_MMIO_RADIO_HWENABLED_HI 0x158
  52 #define BCM43xx_MMIO_SHM_CONTROL        0x160
  53 #define BCM43xx_MMIO_SHM_DATA           0x164
  54 #define BCM43xx_MMIO_SHM_DATA_UNALIGNED 0x166
  55 #define BCM43xx_MMIO_XMITSTAT_0         0x170
  56 #define BCM43xx_MMIO_XMITSTAT_1         0x174
  57 #define BCM43xx_MMIO_REV3PLUS_TSF_LOW   0x180 /* core rev >= 3 only */
  58 #define BCM43xx_MMIO_REV3PLUS_TSF_HIGH  0x184 /* core rev >= 3 only */
  59 #define BCM43xx_MMIO_DMA1_BASE          0x200
  60 #define BCM43xx_MMIO_DMA2_BASE          0x220
  61 #define BCM43xx_MMIO_DMA3_BASE          0x240
  62 #define BCM43xx_MMIO_DMA4_BASE          0x260
  63 #define BCM43xx_MMIO_PIO1_BASE          0x300
  64 #define BCM43xx_MMIO_PIO2_BASE          0x310
  65 #define BCM43xx_MMIO_PIO3_BASE          0x320
  66 #define BCM43xx_MMIO_PIO4_BASE          0x330
  67 #define BCM43xx_MMIO_PHY_VER            0x3E0
  68 #define BCM43xx_MMIO_PHY_RADIO          0x3E2
  69 #define BCM43xx_MMIO_ANTENNA            0x3E8
  70 #define BCM43xx_MMIO_CHANNEL            0x3F0
  71 #define BCM43xx_MMIO_CHANNEL_EXT        0x3F4
  72 #define BCM43xx_MMIO_RADIO_CONTROL      0x3F6
  73 #define BCM43xx_MMIO_RADIO_DATA_HIGH    0x3F8
  74 #define BCM43xx_MMIO_RADIO_DATA_LOW     0x3FA
  75 #define BCM43xx_MMIO_PHY_CONTROL        0x3FC
  76 #define BCM43xx_MMIO_PHY_DATA           0x3FE
  77 #define BCM43xx_MMIO_MACFILTER_CONTROL  0x420
  78 #define BCM43xx_MMIO_MACFILTER_DATA     0x422
  79 #define BCM43xx_MMIO_RADIO_HWENABLED_LO 0x49A
  80 #define BCM43xx_MMIO_GPIO_CONTROL       0x49C
  81 #define BCM43xx_MMIO_GPIO_MASK          0x49E
  82 #define BCM43xx_MMIO_TSF_0              0x632 /* core rev < 3 only */
  83 #define BCM43xx_MMIO_TSF_1              0x634 /* core rev < 3 only */
  84 #define BCM43xx_MMIO_TSF_2              0x636 /* core rev < 3 only */
  85 #define BCM43xx_MMIO_TSF_3              0x638 /* core rev < 3 only */
  86 #define BCM43xx_MMIO_RNG                0x65A
  87 #define BCM43xx_MMIO_POWERUP_DELAY      0x6A8
  88
  89 /* SPROM offsets. */
  90 #define BCM43xx_SPROM_BASE              0x1000
  91 #define BCM43xx_SPROM_BOARDFLAGS2       0x1c
  92 #define BCM43xx_SPROM_IL0MACADDR        0x24
  93 #define BCM43xx_SPROM_ET0MACADDR        0x27
  94 #define BCM43xx_SPROM_ET1MACADDR        0x2a
  95 #define BCM43xx_SPROM_ETHPHY            0x2d
  96 #define BCM43xx_SPROM_BOARDREV          0x2e
  97 #define BCM43xx_SPROM_PA0B0             0x2f
  98 #define BCM43xx_SPROM_PA0B1             0x30
  99 #define BCM43xx_SPROM_PA0B2             0x31
 100 #define BCM43xx_SPROM_WL0GPIO0          0x32
 101 #define BCM43xx_SPROM_WL0GPIO2          0x33
 102 #define BCM43xx_SPROM_MAXPWR            0x34
 103 #define BCM43xx_SPROM_PA1B0             0x35
 104 #define BCM43xx_SPROM_PA1B1             0x36
 105 #define BCM43xx_SPROM_PA1B2             0x37
 106 #define BCM43xx_SPROM_IDL_TSSI_TGT      0x38
 107 #define BCM43xx_SPROM_BOARDFLAGS        0x39
 108 #define BCM43xx_SPROM_ANTENNA_GAIN      0x3a
 109 #define BCM43xx_SPROM_VERSION           0x3f
 110
 111 /* BCM43xx_SPROM_BOARDFLAGS values */
 112 #define BCM43xx_BFL_BTCOEXIST           0x0001 /* implements Bluetooth coexistance */
 113 #define BCM43xx_BFL_PACTRL              0x0002 /* GPIO 9 controlling the PA */
 114 #define BCM43xx_BFL_AIRLINEMODE         0x0004 /* implements GPIO 13 radio disable indication */
 115 #define BCM43xx_BFL_RSSI                0x0008 /* software calculates nrssi slope. */
 116 #define BCM43xx_BFL_ENETSPI             0x0010 /* has ephy roboswitch spi */
 117 #define BCM43xx_BFL_XTAL_NOSLOW         0x0020 /* no slow clock available */
 118 #define BCM43xx_BFL_CCKHIPWR            0x0040 /* can do high power CCK transmission */
 119 #define BCM43xx_BFL_ENETADM             0x0080 /* has ADMtek switch */
 120 #define BCM43xx_BFL_ENETVLAN            0x0100 /* can do vlan */
 121 #define BCM43xx_BFL_AFTERBURNER         0x0200 /* supports Afterburner mode */
 122 #define BCM43xx_BFL_NOPCI               0x0400 /* leaves PCI floating */
 123 #define BCM43xx_BFL_FEM                 0x0800 /* supports the Front End Module */
 124 #define BCM43xx_BFL_EXTLNA              0x1000 /* has an external LNA */
 125 #define BCM43xx_BFL_HGPA                0x2000 /* had high gain PA */
 126 #define BCM43xx_BFL_BTCMOD              0x4000 /* BFL_BTCOEXIST is given in alternate GPIOs */
 127 #define BCM43xx_BFL_ALTIQ               0x8000 /* alternate I/Q settings */
 128
 129 /* GPIO register offset, in both ChipCommon and PCI core. */
 130 #define BCM43xx_GPIO_CONTROL            0x6c
 131
 132 /* SHM Routing */
 133 #define BCM43xx_SHM_SHARED              0x0001
 134 #define BCM43xx_SHM_WIRELESS            0x0002
 135 #define BCM43xx_SHM_PCM                 0x0003
 136 #define BCM43xx_SHM_HWMAC               0x0004
 137 #define BCM43xx_SHM_UCODE               0x0300
 138
 139 /* MacFilter offsets. */
 140 #define BCM43xx_MACFILTER_SELF          0x0000
 141 #define BCM43xx_MACFILTER_ASSOC         0x0003
 142
 143 /* Chipcommon registers. */
 144 #define BCM43xx_CHIPCOMMON_CAPABILITIES         0x04
 145 #define BCM43xx_CHIPCOMMON_PLLONDELAY           0xB0
 146 #define BCM43xx_CHIPCOMMON_FREFSELDELAY         0xB4
 147 #define BCM43xx_CHIPCOMMON_SLOWCLKCTL           0xB8
 148 #define BCM43xx_CHIPCOMMON_SYSCLKCTL            0xC0
 149
 150 /* PCI core specific registers. */
 151 #define BCM43xx_PCICORE_BCAST_ADDR      0x50
 152 #define BCM43xx_PCICORE_BCAST_DATA      0x54
 153 #define BCM43xx_PCICORE_SBTOPCI2        0x108
 154
 155 /* SBTOPCI2 values. */
 156 #define BCM43xx_SBTOPCI2_PREFETCH       0x4
 157 #define BCM43xx_SBTOPCI2_BURST          0x8
 158
 159 /* Chipcommon capabilities. */
 160 #define BCM43xx_CAPABILITIES_PCTL               0x00040000
 161 #define BCM43xx_CAPABILITIES_PLLMASK            0x00030000
 162 #define BCM43xx_CAPABILITIES_PLLSHIFT           16
 163 #define BCM43xx_CAPABILITIES_FLASHMASK          0x00000700
 164 #define BCM43xx_CAPABILITIES_FLASHSHIFT         8
 165 #define BCM43xx_CAPABILITIES_EXTBUSPRESENT      0x00000040
 166 #define BCM43xx_CAPABILITIES_UARTGPIO           0x00000020
 167 #define BCM43xx_CAPABILITIES_UARTCLOCKMASK      0x00000018
 168 #define BCM43xx_CAPABILITIES_UARTCLOCKSHIFT     3
 169 #define BCM43xx_CAPABILITIES_MIPSBIGENDIAN      0x00000004
 170 #define BCM43xx_CAPABILITIES_NRUARTSMASK        0x00000003
 171
 172 /* PowerControl */
 173 #define BCM43xx_PCTL_IN                 0xB0
 174 #define BCM43xx_PCTL_OUT                0xB4
 175 #define BCM43xx_PCTL_OUTENABLE          0xB8
 176 #define BCM43xx_PCTL_XTAL_POWERUP       0x40
 177 #define BCM43xx_PCTL_PLL_POWERDOWN      0x80
 178
 179 /* PowerControl Clock Modes */
 180 #define BCM43xx_PCTL_CLK_FAST           0x00
 181 #define BCM43xx_PCTL_CLK_SLOW           0x01
 182 #define BCM43xx_PCTL_CLK_DYNAMIC        0x02
 183
 184 #define BCM43xx_PCTL_FORCE_SLOW         0x0800
 185 #define BCM43xx_PCTL_FORCE_PLL          0x1000
 186 #define BCM43xx_PCTL_DYN_XTAL           0x2000
 187
 188 /* COREIDs */
 189 #define BCM43xx_COREID_CHIPCOMMON       0x800
 190 #define BCM43xx_COREID_ILINE20          0x801
 191 #define BCM43xx_COREID_SDRAM            0x803
 192 #define BCM43xx_COREID_PCI              0x804
 193 #define BCM43xx_COREID_MIPS             0x805
 194 #define BCM43xx_COREID_ETHERNET         0x806
 195 #define BCM43xx_COREID_V90              0x807
 196 #define BCM43xx_COREID_USB11_HOSTDEV    0x80a
 197 #define BCM43xx_COREID_IPSEC            0x80b
 198 #define BCM43xx_COREID_PCMCIA           0x80d
 199 #define BCM43xx_COREID_EXT_IF           0x80f
 200 #define BCM43xx_COREID_80211            0x812
 201 #define BCM43xx_COREID_MIPS_3302        0x816
 202 #define BCM43xx_COREID_USB11_HOST       0x817
 203 #define BCM43xx_COREID_USB11_DEV        0x818
 204 #define BCM43xx_COREID_USB20_HOST       0x819
 205 #define BCM43xx_COREID_USB20_DEV        0x81a
 206 #define BCM43xx_COREID_SDIO_HOST        0x81b
 207
 208 /* Core Information Registers */
 209 #define BCM43xx_CIR_BASE                0xf00
 210 #define BCM43xx_CIR_SBTPSFLAG           (BCM43xx_CIR_BASE + 0x18)
 211 #define BCM43xx_CIR_SBIMSTATE           (BCM43xx_CIR_BASE + 0x90)
 212 #define BCM43xx_CIR_SBINTVEC            (BCM43xx_CIR_BASE + 0x94)
 213 #define BCM43xx_CIR_SBTMSTATELOW        (BCM43xx_CIR_BASE + 0x98)
 214 #define BCM43xx_CIR_SBTMSTATEHIGH       (BCM43xx_CIR_BASE + 0x9c)
 215 #define BCM43xx_CIR_SBIMCONFIGLOW       (BCM43xx_CIR_BASE + 0xa8)
 216 #define BCM43xx_CIR_SB_ID_HI            (BCM43xx_CIR_BASE + 0xfc)
 217
 218 /* Mask to get the Backplane Flag Number from SBTPSFLAG. */
 219 #define BCM43xx_BACKPLANE_FLAG_NR_MASK  0x3f
 220
 221 /* SBIMCONFIGLOW values/masks. */
 222 #define BCM43xx_SBIMCONFIGLOW_SERVICE_TOUT_MASK         0x00000007
 223 #define BCM43xx_SBIMCONFIGLOW_SERVICE_TOUT_SHIFT        0
 224 #define BCM43xx_SBIMCONFIGLOW_REQUEST_TOUT_MASK         0x00000070
 225 #define BCM43xx_SBIMCONFIGLOW_REQUEST_TOUT_SHIFT        4
 226 #define BCM43xx_SBIMCONFIGLOW_CONNID_MASK               0x00ff0000
 227 #define BCM43xx_SBIMCONFIGLOW_CONNID_SHIFT              16
 228
 229 /* sbtmstatelow state flags */
 230 #define BCM43xx_SBTMSTATELOW_RESET              0x01
 231 #define BCM43xx_SBTMSTATELOW_REJECT             0x02
 232 #define BCM43xx_SBTMSTATELOW_CLOCK              0x10000
 233 #define BCM43xx_SBTMSTATELOW_FORCE_GATE_CLOCK   0x20000
 234
 235 /* sbtmstatehigh state flags */
 236 #define BCM43xx_SBTMSTATEHIGH_SERROR            0x1
 237 #define BCM43xx_SBTMSTATEHIGH_BUSY              0x4
 238
 239 /* sbimstate flags */
 240 #define BCM43xx_SBIMSTATE_IB_ERROR              0x20000
 241 #define BCM43xx_SBIMSTATE_TIMEOUT               0x40000
 242
 243 /* PHYVersioning */
 244 #define BCM43xx_PHYTYPE_A               0x00
 245 #define BCM43xx_PHYTYPE_B               0x01
 246 #define BCM43xx_PHYTYPE_G               0x02
 247
 248 /* PHYRegisters */
 249 #define BCM43xx_PHY_ILT_A_CTRL          0x0072
 250 #define BCM43xx_PHY_ILT_A_DATA1         0x0073
 251 #define BCM43xx_PHY_ILT_A_DATA2         0x0074
 252 #define BCM43xx_PHY_G_LO_CONTROL        0x0810
 253 #define BCM43xx_PHY_ILT_G_CTRL          0x0472
 254 #define BCM43xx_PHY_ILT_G_DATA1         0x0473
 255 #define BCM43xx_PHY_ILT_G_DATA2         0x0474
 256 #define BCM43xx_PHY_A_PCTL              0x007B
 257 #define BCM43xx_PHY_G_PCTL              0x0029
 258 #define BCM43xx_PHY_A_CRS               0x0029
 259 #define BCM43xx_PHY_RADIO_BITFIELD      0x0401
 260 #define BCM43xx_PHY_G_CRS               0x0429
 261 #define BCM43xx_PHY_NRSSILT_CTRL        0x0803
 262 #define BCM43xx_PHY_NRSSILT_DATA        0x0804
 263
 264 /* RadioRegisters */
 265 #define BCM43xx_RADIOCTL_ID             0x01
 266
 267 /* StatusBitField */
 268 #define BCM43xx_SBF_MAC_ENABLED         0x00000001
 269 #define BCM43xx_SBF_2                   0x00000002 /*FIXME: fix name*/
 270 #define BCM43xx_SBF_CORE_READY          0x00000004
 271 #define BCM43xx_SBF_400                 0x00000400 /*FIXME: fix name*/
 272 #define BCM43xx_SBF_4000                0x00004000 /*FIXME: fix name*/
 273 #define BCM43xx_SBF_8000                0x00008000 /*FIXME: fix name*/
 274 #define BCM43xx_SBF_XFER_REG_BYTESWAP   0x00010000
 275 #define BCM43xx_SBF_MODE_NOTADHOC       0x00020000
 276 #define BCM43xx_SBF_MODE_AP             0x00040000
 277 #define BCM43xx_SBF_RADIOREG_LOCK       0x00080000
 278 #define BCM43xx_SBF_MODE_MONITOR        0x00400000
 279 #define BCM43xx_SBF_MODE_PROMISC        0x01000000
 280 #define BCM43xx_SBF_PS1                 0x02000000
 281 #define BCM43xx_SBF_PS2                 0x04000000
 282 #define BCM43xx_SBF_NO_SSID_BCAST       0x08000000
 283 #define BCM43xx_SBF_TIME_UPDATE         0x10000000
 284 #define BCM43xx_SBF_80000000            0x80000000 /*FIXME: fix name*/
 285
 286 /* MicrocodeFlagsBitfield (addr + lo-word values?)*/
 287 #define BCM43xx_UCODEFLAGS_OFFSET       0x005E
 288
 289 #define BCM43xx_UCODEFLAG_AUTODIV       0x0001
 290 #define BCM43xx_UCODEFLAG_UNKBGPHY      0x0002
 291 #define BCM43xx_UCODEFLAG_UNKBPHY       0x0004
 292 #define BCM43xx_UCODEFLAG_UNKGPHY       0x0020
 293 #define BCM43xx_UCODEFLAG_UNKPACTRL     0x0040
 294 #define BCM43xx_UCODEFLAG_JAPAN         0x0080
 295
 296 /* Generic-Interrupt reasons. */
 297 #define BCM43xx_IRQ_READY               (1 << 0)
 298 #define BCM43xx_IRQ_BEACON              (1 << 1)
 299 #define BCM43xx_IRQ_PS                  (1 << 2)
 300 #define BCM43xx_IRQ_REG124              (1 << 5)
 301 #define BCM43xx_IRQ_PMQ                 (1 << 6)
 302 #define BCM43xx_IRQ_PIO_WORKAROUND      (1 << 8)
 303 #define BCM43xx_IRQ_XMIT_ERROR          (1 << 11)
 304 #define BCM43xx_IRQ_RX                  (1 << 15)
 305 #define BCM43xx_IRQ_SCAN                (1 << 16)
 306 #define BCM43xx_IRQ_NOISE               (1 << 18)
 307 #define BCM43xx_IRQ_XMIT_STATUS         (1 << 29)
 308
 309 #define BCM43xx_IRQ_ALL                 0xffffffff
 310 #define BCM43xx_IRQ_INITIAL             (BCM43xx_IRQ_PS |               \
 311                                          BCM43xx_IRQ_REG124 |           \
 312                                          BCM43xx_IRQ_PMQ |              \
 313                                          BCM43xx_IRQ_XMIT_ERROR |       \
 314                                          BCM43xx_IRQ_RX |               \
 315                                          BCM43xx_IRQ_SCAN |             \
 316                                          BCM43xx_IRQ_NOISE |            \
 317                                          BCM43xx_IRQ_XMIT_STATUS)
 318
 319
 320 /* Initial default iw_mode */
 321 #define BCM43xx_INITIAL_IWMODE                  IW_MODE_INFRA
 322
 323 /* Bus type PCI. */
 324 #define BCM43xx_BUSTYPE_PCI     0
 325 /* Bus type Silicone Backplane Bus. */
 326 #define BCM43xx_BUSTYPE_SB      1
 327 /* Bus type PCMCIA. */
 328 #define BCM43xx_BUSTYPE_PCMCIA  2
 329
 330 /* Threshold values. */
 331 #define BCM43xx_MIN_RTS_THRESHOLD               1U
 332 #define BCM43xx_MAX_RTS_THRESHOLD               2304U
 333 #define BCM43xx_DEFAULT_RTS_THRESHOLD           BCM43xx_MAX_RTS_THRESHOLD
 334
 335 #define BCM43xx_DEFAULT_SHORT_RETRY_LIMIT       7
 336 #define BCM43xx_DEFAULT_LONG_RETRY_LIMIT        4
 337
 338 /* Max size of a security key */
 339 #define BCM43xx_SEC_KEYSIZE                     16
 340 /* Security algorithms. */
 341 enum {
 342         BCM43xx_SEC_ALGO_NONE = 0, /* unencrypted, as of TX header. */
 343         BCM43xx_SEC_ALGO_WEP,
 344         BCM43xx_SEC_ALGO_UNKNOWN,
 345         BCM43xx_SEC_ALGO_AES,
 346         BCM43xx_SEC_ALGO_WEP104,
 347         BCM43xx_SEC_ALGO_TKIP,
 348 };
 349
 350 #ifdef assert
 351 # undef assert
 352 #endif
 353 #ifdef CONFIG_BCM43XX_DEBUG
 354 #define assert(expr) \
 355         do {                                                                    \
 356                 if (unlikely(!(expr))) {                                        \
 357                 printk(KERN_ERR PFX "ASSERTION FAILED (%s) at: %s:%d:%s()\n",   \
 358                         #expr, __FILE__, __LINE__, __FUNCTION__);               \
 359                 }                                                               \
 360         } while (0)
 361 #else
 362 #define assert(expr)    do { /* nothing */ } while (0)
 363 #endif
 364
 365 /* rate limited printk(). */
 366 #ifdef printkl
 367 # undef printkl
 368 #endif
 369 #define printkl(f, x...)  do { if (printk_ratelimit()) printk(f ,##x); } while (0)
 370 /* rate limited printk() for debugging */
 371 #ifdef dprintkl
 372 # undef dprintkl
 373 #endif
 374 #ifdef CONFIG_BCM43XX_DEBUG
 375 # define dprintkl               printkl
 376 #else
 377 # define dprintkl(f, x...)      do { /* nothing */ } while (0)
 378 #endif
 379
 380 /* Helper macro for if branches.
 381  * An if branch marked with this macro is only taken in DEBUG mode.
 382  * Example:
 383  *      if (DEBUG_ONLY(foo == bar)) {
 384  *              do something
 385  *      }
 386  *      In DEBUG mode, the branch will be taken if (foo == bar).
 387  *      In non-DEBUG mode, the branch will never be taken.
 388  */
 389 #ifdef DEBUG_ONLY
 390 # undef DEBUG_ONLY
 391 #endif
 392 #ifdef CONFIG_BCM43XX_DEBUG
 393 # define DEBUG_ONLY(x)  (x)
 394 #else
 395 # define DEBUG_ONLY(x)  0
 396 #endif
 397
 398 /* debugging printk() */
 399 #ifdef dprintk
 400 # undef dprintk
 401 #endif
 402 #ifdef CONFIG_BCM43XX_DEBUG
 403 # define dprintk(f, x...)  do { printk(f ,##x); } while (0)
 404 #else
 405 # define dprintk(f, x...)  do { /* nothing */ } while (0)
 406 #endif
 407
 408
 409 struct net_device;
 410 struct pci_dev;
 411 struct bcm43xx_dmaring;
 412 struct bcm43xx_pioqueue;
 413
 414 struct bcm43xx_initval {
 415         u16 offset;
 416         u16 size;
 417         u32 value;
 418 } __attribute__((__packed__));
 419
 420 /* Values for bcm430x_sprominfo.locale */
 421 enum {
 422         BCM43xx_LOCALE_WORLD = 0,
 423         BCM43xx_LOCALE_THAILAND,
 424         BCM43xx_LOCALE_ISRAEL,
 425         BCM43xx_LOCALE_JORDAN,
 426         BCM43xx_LOCALE_CHINA,
 427         BCM43xx_LOCALE_JAPAN,
 428         BCM43xx_LOCALE_USA_CANADA_ANZ,
 429         BCM43xx_LOCALE_EUROPE,
 430         BCM43xx_LOCALE_USA_LOW,
 431         BCM43xx_LOCALE_JAPAN_HIGH,
 432         BCM43xx_LOCALE_ALL,
 433         BCM43xx_LOCALE_NONE,
 434 };
 435
 436 #define BCM43xx_SPROM_SIZE      64 /* in 16-bit words. */
 437 struct bcm43xx_sprominfo {
 438         u16 boardflags2;
 439         u8 il0macaddr[6];
 440         u8 et0macaddr[6];
 441         u8 et1macaddr[6];
 442         u8 et0phyaddr:5;
 443         u8 et1phyaddr:5;
 444         u8 et0mdcport:1;
 445         u8 et1mdcport:1;
 446         u8 boardrev;
 447         u8 locale:4;
 448         u8 antennas_aphy:2;
 449         u8 antennas_bgphy:2;
 450         u16 pa0b0;
 451         u16 pa0b1;
 452         u16 pa0b2;
 453         u8 wl0gpio0;
 454         u8 wl0gpio1;
 455         u8 wl0gpio2;
 456         u8 wl0gpio3;
 457         u8 maxpower_aphy;
 458         u8 maxpower_bgphy;
 459         u16 pa1b0;
 460         u16 pa1b1;
 461         u16 pa1b2;
 462         u8 idle_tssi_tgt_aphy;
 463         u8 idle_tssi_tgt_bgphy;
 464         u16 boardflags;
 465         u16 antennagain_aphy;
 466         u16 antennagain_bgphy;
 467 };
 468
 469 /* Value pair to measure the LocalOscillator. */
 470 struct bcm43xx_lopair {
 471         s8 low;
 472         s8 high;
 473         u8 used:1;
 474 };
 475 #define BCM43xx_LO_COUNT        (14*4)
 476
 477 struct bcm43xx_phyinfo {
 478         /* Hardware Data */
 479         u8 version;
 480         u8 type;
 481         u8 rev;
 482         u16 antenna_diversity;
 483         u16 savedpctlreg;
 484         u16 minlowsig[2];
 485         u16 minlowsigpos[2];
 486         u8 connected:1,
 487            calibrated:1,
 488            is_locked:1, /* used in bcm43xx_phy_{un}lock() */
 489            dyn_tssi_tbl:1; /* used in bcm43xx_phy_init_tssi2dbm_table() */
 490         /* LO Measurement Data.
 491          * Use bcm43xx_get_lopair() to get a value.
 492          */
 493         struct bcm43xx_lopair *_lo_pairs;
 494
 495         /* TSSI to dBm table in use */
 496         const s8 *tssi2dbm;
 497         /* idle TSSI value */
 498         s8 idle_tssi;
 499
 500         /* Values from bcm43xx_calc_loopback_gain() */
 501         u16 loopback_gain[2];
 502
 503         /* PHY lock for core.rev < 3
 504          * This lock is only used by bcm43xx_phy_{un}lock()
 505          */
 506         spinlock_t lock;
 507 };
 508
 509
 510 struct bcm43xx_radioinfo {
 511         u16 manufact;
 512         u16 version;
 513         u8 revision;
 514
 515         /* Desired TX power in dBm Q5.2 */
 516         u16 txpower_desired;
 517         /* TX Power control values. */
 518         union {
 519                 /* B/G PHY */
 520                 struct {
 521                         u16 baseband_atten;
 522                         u16 radio_atten;
 523                         u16 txctl1;
 524                         u16 txctl2;
 525                 };
 526                 /* A PHY */
 527                 struct {
 528                         u16 txpwr_offset;
 529                 };
 530         };
 531
 532         /* Current Interference Mitigation mode */
 533         int interfmode;
 534         /* Stack of saved values from the Interference Mitigation code.
 535          * Each value in the stack is layed out as follows:
 536          * bit 0-11:  offset
 537          * bit 12-15: register ID
 538          * bit 16-32: value
 539          * register ID is: 0x1 PHY, 0x2 Radio, 0x3 ILT
 540          */
 541 #define BCM43xx_INTERFSTACK_SIZE        26
 542         u32 interfstack[BCM43xx_INTERFSTACK_SIZE];
 543
 544         /* Saved values from the NRSSI Slope calculation */
 545         s16 nrssi[2];
 546         s32 nrssislope;
 547         /* In memory nrssi lookup table. */
 548         s8 nrssi_lt[64];
 549
 550         /* current channel */
 551         u8 channel;
 552         u8 initial_channel;
 553
 554         u16 lofcal;
 555
 556         u16 initval;
 557
 558         u8 enabled:1;
 559         /* ACI (adjacent channel interference) flags. */
 560         u8 aci_enable:1,
 561            aci_wlan_automatic:1,
 562            aci_hw_rssi:1;
 563 };
 564
 565 /* Data structures for DMA transmission, per 80211 core. */
 566 struct bcm43xx_dma {
 567         struct bcm43xx_dmaring *tx_ring0;
 568         struct bcm43xx_dmaring *tx_ring1;
 569         struct bcm43xx_dmaring *tx_ring2;
 570         struct bcm43xx_dmaring *tx_ring3;
 571         struct bcm43xx_dmaring *rx_ring0;
 572         struct bcm43xx_dmaring *rx_ring1; /* only available on core.rev < 5 */
 573 };
 574
 575 /* Data structures for PIO transmission, per 80211 core. */
 576 struct bcm43xx_pio {
 577         struct bcm43xx_pioqueue *queue0;
 578         struct bcm43xx_pioqueue *queue1;
 579         struct bcm43xx_pioqueue *queue2;
 580         struct bcm43xx_pioqueue *queue3;
 581 };
 582
 583 #define BCM43xx_MAX_80211_CORES         2
 584
 585 #ifdef CONFIG_BCM947XX
 586 #define core_offset(bcm) (bcm)->current_core_offset
 587 #else
 588 #define core_offset(bcm) 0
 589 #endif
 590
 591 /* Generic information about a core. */
 592 struct bcm43xx_coreinfo {
 593         u8 available:1,
 594            enabled:1,
 595            initialized:1;
 596         /** core_id ID number */
 597         u16 id;
 598         /** core_rev revision number */
 599         u8 rev;
 600         /** Index number for _switch_core() */
 601         u8 index;
 602 };
 603
 604 /* Additional information for each 80211 core. */
 605 struct bcm43xx_coreinfo_80211 {
 606         /* PHY device. */
 607         struct bcm43xx_phyinfo phy;
 608         /* Radio device. */
 609         struct bcm43xx_radioinfo radio;
 610         union {
 611                 /* DMA context. */
 612                 struct bcm43xx_dma dma;
 613                 /* PIO context. */
 614                 struct bcm43xx_pio pio;
 615         };
 616 };
 617
 618 /* Context information for a noise calculation (Link Quality). */
 619 struct bcm43xx_noise_calculation {
 620         struct bcm43xx_coreinfo *core_at_start;
 621         u8 channel_at_start;
 622         u8 calculation_running:1;
 623         u8 nr_samples;
 624         s8 samples[8][4];
 625 };
 626
 627 struct bcm43xx_stats {
 628         u8 link_quality;
 629         u8 noise;
 630         struct iw_statistics wstats;
 631         /* Store the last TX/RX times here for updating the leds. */
 632         unsigned long last_tx;
 633         unsigned long last_rx;
 634 };
 635
 636 struct bcm43xx_key {
 637         u8 enabled:1;
 638         u8 algorithm;
 639 };
 640
 641 /* Driver initialization status. */
 642 enum {
 643         BCM43xx_STAT_UNINIT,            /* Uninitialized. */
 644         BCM43xx_STAT_INITIALIZING,      /* init_board() in progress. */
 645         BCM43xx_STAT_INITIALIZED,       /* Fully operational. */
 646         BCM43xx_STAT_SHUTTINGDOWN,      /* free_board() in progress. */
 647         BCM43xx_STAT_RESTARTING,        /* controller_restart() called. */
 648 };
 649 #define bcm43xx_status(bcm)             atomic_read(&(bcm)->init_status)
 650 #define bcm43xx_set_status(bcm, stat)   atomic_set(&(bcm)->init_status, (stat))
 651
 652 /*    *** THEORY OF LOCKING ***
 653  *
 654  * We have two different locks in the bcm43xx driver.
 655  * => bcm->mutex:    General sleeping mutex. Protects struct bcm43xx_private
 656  *                   and the device registers. This mutex does _not_ protect
 657  *                   against concurrency from the IRQ handler.
 658  * => bcm->irq_lock: IRQ spinlock. Protects against IRQ handler concurrency.
 659  *
 660  * Please note that, if you only take the irq_lock, you are not protected
 661  * against concurrency from the periodic work handlers.
 662  * Most times you want to take _both_ locks.
 663  */
 664
 665 struct bcm43xx_private {
 666         struct ieee80211_device *ieee;
 667         struct ieee80211softmac_device *softmac;
 668
 669         struct net_device *net_dev;
 670         struct pci_dev *pci_dev;
 671         unsigned int irq;
 672
 673         void __iomem *mmio_addr;
 674
 675         spinlock_t irq_lock;
 676         struct mutex mutex;
 677
 678         /* Driver initialization status BCM43xx_STAT_*** */
 679         atomic_t init_status;
 680
 681         u16 was_initialized:1,          /* for PCI suspend/resume. */
 682             __using_pio:1,              /* Internal, use bcm43xx_using_pio(). */
 683             bad_frames_preempt:1,       /* Use "Bad Frames Preemption" (default off) */
 684             reg124_set_0x4:1,           /* Some variable to keep track of IRQ stuff. */
 685             short_preamble:1,           /* TRUE, if short preamble is enabled. */
 686             firmware_norelease:1;       /* Do not release the firmware. Used on suspend. */
 687
 688         struct bcm43xx_stats stats;
 689
 690         /* Bus type we are connected to.
 691          * This is currently always BCM43xx_BUSTYPE_PCI
 692          */
 693         u8 bustype;
 694
 695         u16 board_vendor;
 696         u16 board_type;
 697         u16 board_revision;
 698
 699         u16 chip_id;
 700         u8 chip_rev;
 701         u8 chip_package;
 702
 703         struct bcm43xx_sprominfo sprom;
 704 #define BCM43xx_NR_LEDS         4
 705         struct bcm43xx_led leds[BCM43xx_NR_LEDS];
 706         spinlock_t leds_lock;
 707
 708         /* The currently active core. */
 709         struct bcm43xx_coreinfo *current_core;
 710 #ifdef CONFIG_BCM947XX
 711         /** current core memory offset */
 712         u32 current_core_offset;
 713 #endif
 714         struct bcm43xx_coreinfo *active_80211_core;
 715         /* coreinfo structs for all possible cores follow.
 716          * Note that a core might not exist.
 717          * So check the coreinfo flags before using it.
 718          */
 719         struct bcm43xx_coreinfo core_chipcommon;
 720         struct bcm43xx_coreinfo core_pci;
 721         struct bcm43xx_coreinfo core_80211[ BCM43xx_MAX_80211_CORES ];
 722         /* Additional information, specific to the 80211 cores. */
 723         struct bcm43xx_coreinfo_80211 core_80211_ext[ BCM43xx_MAX_80211_CORES ];
 724         /* Index of the current 80211 core. If current_core is not
 725          * an 80211 core, this is -1.
 726          */
 727         int current_80211_core_idx;
 728         /* Number of available 80211 cores. */
 729         int nr_80211_available;
 730
 731         u32 chipcommon_capabilities;
 732
 733         /* Reason code of the last interrupt. */
 734         u32 irq_reason;
 735         u32 dma_reason[4];
 736         /* saved irq enable/disable state bitfield. */
 737         u32 irq_savedstate;
 738         /* Link Quality calculation context. */
 739         struct bcm43xx_noise_calculation noisecalc;
 740
 741         /* Threshold values. */
 742         //TODO: The RTS thr has to be _used_. Currently, it is only set via WX.
 743         u32 rts_threshold;
 744
 745         /* Interrupt Service Routine tasklet (bottom-half) */
 746         struct tasklet_struct isr_tasklet;
 747
 748         /* Periodic tasks */
 749         struct work_struct periodic_work;
 750         unsigned int periodic_state;
 751
 752         struct work_struct restart_work;
 753
 754         /* Informational stuff. */
 755         char nick[IW_ESSID_MAX_SIZE + 1];
 756
 757         /* encryption/decryption */
 758         u16 security_offset;
 759         struct bcm43xx_key key[54];
 760         u8 default_key_idx;
 761
 762         /* Firmware. */
 763         const struct firmware *ucode;
 764         const struct firmware *pcm;
 765         const struct firmware *initvals0;
 766         const struct firmware *initvals1;
 767
 768         /* Random Number Generator. */
 769         struct hwrng rng;
 770         char rng_name[20 + 1];
 771
 772         /* Debugging stuff follows. */
 773 #ifdef CONFIG_BCM43XX_DEBUG
 774         struct bcm43xx_dfsentry *dfsentry;
 775 #endif
 776 };
 777
 778
 779 static inline
 780 struct bcm43xx_private * bcm43xx_priv(struct net_device *dev)
 781 {
 782         return ieee80211softmac_priv(dev);
 783 }
 784
 785 struct device;
 786
 787 static inline
 788 struct bcm43xx_private * dev_to_bcm(struct device *dev)
 789 {
 790         struct net_device *net_dev;
 791         struct bcm43xx_private *bcm;
 792
 793         net_dev = dev_get_drvdata(dev);
 794         bcm = bcm43xx_priv(net_dev);
 795
 796         return bcm;
 797 }
 798
 799
 800 /* Helper function, which returns a boolean.
 801  * TRUE, if PIO is used; FALSE, if DMA is used.
 802  */
 803 #if defined(CONFIG_BCM43XX_DMA) && defined(CONFIG_BCM43XX_PIO)
 804 static inline
 805 int bcm43xx_using_pio(struct bcm43xx_private *bcm)
 806 {
 807         return bcm->__using_pio;
 808 }
 809 #elif defined(CONFIG_BCM43XX_DMA)
 810 static inline
 811 int bcm43xx_using_pio(struct bcm43xx_private *bcm)
 812 {
 813         return 0;
 814 }
 815 #elif defined(CONFIG_BCM43XX_PIO)
 816 static inline
 817 int bcm43xx_using_pio(struct bcm43xx_private *bcm)
 818 {
 819         return 1;
 820 }
 821 #else
 822 # error "Using neither DMA nor PIO? Confused..."
 823 #endif
 824
 825 /* Helper functions to access data structures private to the 80211 cores.
 826  * Note that we _must_ have an 80211 core mapped when calling
 827  * any of these functions.
 828  */
 829 static inline
 830 struct bcm43xx_pio * bcm43xx_current_pio(struct bcm43xx_private *bcm)
 831 {
 832         assert(bcm43xx_using_pio(bcm));
 833         assert(bcm->current_80211_core_idx >= 0);
 834         assert(bcm->current_80211_core_idx < BCM43xx_MAX_80211_CORES);
 835         return &(bcm->core_80211_ext[bcm->current_80211_core_idx].pio);
 836 }
 837 static inline
 838 struct bcm43xx_dma * bcm43xx_current_dma(struct bcm43xx_private *bcm)
 839 {
 840         assert(!bcm43xx_using_pio(bcm));
 841         assert(bcm->current_80211_core_idx >= 0);
 842         assert(bcm->current_80211_core_idx < BCM43xx_MAX_80211_CORES);
 843         return &(bcm->core_80211_ext[bcm->current_80211_core_idx].dma);
 844 }
 845 static inline
 846 struct bcm43xx_phyinfo * bcm43xx_current_phy(struct bcm43xx_private *bcm)
 847 {
 848         assert(bcm->current_80211_core_idx >= 0);
 849         assert(bcm->current_80211_core_idx < BCM43xx_MAX_80211_CORES);
 850         return &(bcm->core_80211_ext[bcm->current_80211_core_idx].phy);
 851 }
 852 static inline
 853 struct bcm43xx_radioinfo * bcm43xx_current_radio(struct bcm43xx_private *bcm)
 854 {
 855         assert(bcm->current_80211_core_idx >= 0);
 856         assert(bcm->current_80211_core_idx < BCM43xx_MAX_80211_CORES);
 857         return &(bcm->core_80211_ext[bcm->current_80211_core_idx].radio);
 858 }
 859
 860
 861 static inline
 862 struct bcm43xx_lopair * bcm43xx_get_lopair(struct bcm43xx_phyinfo *phy,
 863                                            u16 radio_attenuation,
 864                                            u16 baseband_attenuation)
 865 {
 866         return phy->_lo_pairs + (radio_attenuation + 14 * (baseband_attenuation / 2));
 867 }
 868
 869
 870 static inline
 871 u16 bcm43xx_read16(struct bcm43xx_private *bcm, u16 offset)
 872 {
 873         return ioread16(bcm->mmio_addr + core_offset(bcm) + offset);
 874 }
 875
 876 static inline
 877 void bcm43xx_write16(struct bcm43xx_private *bcm, u16 offset, u16 value)
 878 {
 879         iowrite16(value, bcm->mmio_addr + core_offset(bcm) + offset);
 880 }
 881
 882 static inline
 883 u32 bcm43xx_read32(struct bcm43xx_private *bcm, u16 offset)
 884 {
 885         return ioread32(bcm->mmio_addr + core_offset(bcm) + offset);
 886 }
 887
 888 static inline
 889 void bcm43xx_write32(struct bcm43xx_private *bcm, u16 offset, u32 value)
 890 {
 891         iowrite32(value, bcm->mmio_addr + core_offset(bcm) + offset);
 892 }
 893
 894 static inline
 895 int bcm43xx_pci_read_config16(struct bcm43xx_private *bcm, int offset, u16 *value)
 896 {
 897         return pci_read_config_word(bcm->pci_dev, offset, value);
 898 }
 899
 900 static inline
 901 int bcm43xx_pci_read_config32(struct bcm43xx_private *bcm, int offset, u32 *value)
 902 {
 903         return pci_read_config_dword(bcm->pci_dev, offset, value);
 904 }
 905
 906 static inline
 907 int bcm43xx_pci_write_config16(struct bcm43xx_private *bcm, int offset, u16 value)
 908 {
 909         return pci_write_config_word(bcm->pci_dev, offset, value);
 910 }
 911
 912 static inline
 913 int bcm43xx_pci_write_config32(struct bcm43xx_private *bcm, int offset, u32 value)
 914 {
 915         return pci_write_config_dword(bcm->pci_dev, offset, value);
 916 }
 917
 918 /** Limit a value between two limits */
 919 #ifdef limit_value
 920 # undef limit_value
 921 #endif
 922 #define limit_value(value, min, max)  \
 923         ({                                              \
 924                 typeof(value) __value = (value);        \
 925                 typeof(value) __min = (min);            \
 926                 typeof(value) __max = (max);            \
 927                 if (__value < __min)                    \
 928                         __value = __min;                \
 929                 else if (__value > __max)               \
 930                         __value = __max;                \
 931                 __value;                                \
 932         })
 933
 934 /** Helpers to print MAC addresses. */
 935 #define BCM43xx_MACFMT          "%02x:%02x:%02x:%02x:%02x:%02x"
 936 #define BCM43xx_MACARG(x)       ((u8*)(x))[0], ((u8*)(x))[1], \
 937                                 ((u8*)(x))[2], ((u8*)(x))[3], \
 938                                 ((u8*)(x))[4], ((u8*)(x))[5]
 939
 940 #endif /* BCM43xx_H_ */