4 #include <linux/hw_random.h>
5 #include <linux/version.h>
6 #include <linux/kernel.h>
7 #include <linux/spinlock.h>
8 #include <linux/interrupt.h>
9 #include <linux/stringify.h>
10 #include <linux/pci.h>
11 #include <net/ieee80211.h>
12 #include <net/ieee80211softmac.h>
13 #include <asm/atomic.h>
17 #include "bcm43xx_debugfs.h"
18 #include "bcm43xx_leds.h"
21 #define PFX KBUILD_MODNAME ": "
23 #define BCM43xx_SWITCH_CORE_MAX_RETRIES 50
24 #define BCM43xx_IRQWAIT_MAX_RETRIES 50
26 #define BCM43xx_IO_SIZE 8192
28 /* Active Core PCI Configuration Register. */
29 #define BCM43xx_PCICFG_ACTIVE_CORE 0x80
30 /* SPROM control register. */
31 #define BCM43xx_PCICFG_SPROMCTL 0x88
32 /* Interrupt Control PCI Configuration Register. (Only on PCI cores with rev >= 6) */
33 #define BCM43xx_PCICFG_ICR 0x94
36 #define BCM43xx_MMIO_DMA1_REASON 0x20
37 #define BCM43xx_MMIO_DMA1_IRQ_MASK 0x24
38 #define BCM43xx_MMIO_DMA2_REASON 0x28
39 #define BCM43xx_MMIO_DMA2_IRQ_MASK 0x2C
40 #define BCM43xx_MMIO_DMA3_REASON 0x30
41 #define BCM43xx_MMIO_DMA3_IRQ_MASK 0x34
42 #define BCM43xx_MMIO_DMA4_REASON 0x38
43 #define BCM43xx_MMIO_DMA4_IRQ_MASK 0x3C
44 #define BCM43xx_MMIO_STATUS_BITFIELD 0x120
45 #define BCM43xx_MMIO_STATUS2_BITFIELD 0x124
46 #define BCM43xx_MMIO_GEN_IRQ_REASON 0x128
47 #define BCM43xx_MMIO_GEN_IRQ_MASK 0x12C
48 #define BCM43xx_MMIO_RAM_CONTROL 0x130
49 #define BCM43xx_MMIO_RAM_DATA 0x134
50 #define BCM43xx_MMIO_PS_STATUS 0x140
51 #define BCM43xx_MMIO_RADIO_HWENABLED_HI 0x158
52 #define BCM43xx_MMIO_SHM_CONTROL 0x160
53 #define BCM43xx_MMIO_SHM_DATA 0x164
54 #define BCM43xx_MMIO_SHM_DATA_UNALIGNED 0x166
55 #define BCM43xx_MMIO_XMITSTAT_0 0x170
56 #define BCM43xx_MMIO_XMITSTAT_1 0x174
57 #define BCM43xx_MMIO_REV3PLUS_TSF_LOW 0x180 /* core rev >= 3 only */
58 #define BCM43xx_MMIO_REV3PLUS_TSF_HIGH 0x184 /* core rev >= 3 only */
59 #define BCM43xx_MMIO_DMA1_BASE 0x200
60 #define BCM43xx_MMIO_DMA2_BASE 0x220
61 #define BCM43xx_MMIO_DMA3_BASE 0x240
62 #define BCM43xx_MMIO_DMA4_BASE 0x260
63 #define BCM43xx_MMIO_PIO1_BASE 0x300
64 #define BCM43xx_MMIO_PIO2_BASE 0x310
65 #define BCM43xx_MMIO_PIO3_BASE 0x320
66 #define BCM43xx_MMIO_PIO4_BASE 0x330
67 #define BCM43xx_MMIO_PHY_VER 0x3E0
68 #define BCM43xx_MMIO_PHY_RADIO 0x3E2
69 #define BCM43xx_MMIO_ANTENNA 0x3E8
70 #define BCM43xx_MMIO_CHANNEL 0x3F0
71 #define BCM43xx_MMIO_CHANNEL_EXT 0x3F4
72 #define BCM43xx_MMIO_RADIO_CONTROL 0x3F6
73 #define BCM43xx_MMIO_RADIO_DATA_HIGH 0x3F8
74 #define BCM43xx_MMIO_RADIO_DATA_LOW 0x3FA
75 #define BCM43xx_MMIO_PHY_CONTROL 0x3FC
76 #define BCM43xx_MMIO_PHY_DATA 0x3FE
77 #define BCM43xx_MMIO_MACFILTER_CONTROL 0x420
78 #define BCM43xx_MMIO_MACFILTER_DATA 0x422
79 #define BCM43xx_MMIO_RADIO_HWENABLED_LO 0x49A
80 #define BCM43xx_MMIO_GPIO_CONTROL 0x49C
81 #define BCM43xx_MMIO_GPIO_MASK 0x49E
82 #define BCM43xx_MMIO_TSF_0 0x632 /* core rev < 3 only */
83 #define BCM43xx_MMIO_TSF_1 0x634 /* core rev < 3 only */
84 #define BCM43xx_MMIO_TSF_2 0x636 /* core rev < 3 only */
85 #define BCM43xx_MMIO_TSF_3 0x638 /* core rev < 3 only */
86 #define BCM43xx_MMIO_RNG 0x65A
87 #define BCM43xx_MMIO_POWERUP_DELAY 0x6A8
90 #define BCM43xx_SPROM_BASE 0x1000
91 #define BCM43xx_SPROM_BOARDFLAGS2 0x1c
92 #define BCM43xx_SPROM_IL0MACADDR 0x24
93 #define BCM43xx_SPROM_ET0MACADDR 0x27
94 #define BCM43xx_SPROM_ET1MACADDR 0x2a
95 #define BCM43xx_SPROM_ETHPHY 0x2d
96 #define BCM43xx_SPROM_BOARDREV 0x2e
97 #define BCM43xx_SPROM_PA0B0 0x2f
98 #define BCM43xx_SPROM_PA0B1 0x30
99 #define BCM43xx_SPROM_PA0B2 0x31
100 #define BCM43xx_SPROM_WL0GPIO0 0x32
101 #define BCM43xx_SPROM_WL0GPIO2 0x33
102 #define BCM43xx_SPROM_MAXPWR 0x34
103 #define BCM43xx_SPROM_PA1B0 0x35
104 #define BCM43xx_SPROM_PA1B1 0x36
105 #define BCM43xx_SPROM_PA1B2 0x37
106 #define BCM43xx_SPROM_IDL_TSSI_TGT 0x38
107 #define BCM43xx_SPROM_BOARDFLAGS 0x39
108 #define BCM43xx_SPROM_ANTENNA_GAIN 0x3a
109 #define BCM43xx_SPROM_VERSION 0x3f
111 /* BCM43xx_SPROM_BOARDFLAGS values */
112 #define BCM43xx_BFL_BTCOEXIST 0x0001 /* implements Bluetooth coexistance */
113 #define BCM43xx_BFL_PACTRL 0x0002 /* GPIO 9 controlling the PA */
114 #define BCM43xx_BFL_AIRLINEMODE 0x0004 /* implements GPIO 13 radio disable indication */
115 #define BCM43xx_BFL_RSSI 0x0008 /* software calculates nrssi slope. */
116 #define BCM43xx_BFL_ENETSPI 0x0010 /* has ephy roboswitch spi */
117 #define BCM43xx_BFL_XTAL_NOSLOW 0x0020 /* no slow clock available */
118 #define BCM43xx_BFL_CCKHIPWR 0x0040 /* can do high power CCK transmission */
119 #define BCM43xx_BFL_ENETADM 0x0080 /* has ADMtek switch */
120 #define BCM43xx_BFL_ENETVLAN 0x0100 /* can do vlan */
121 #define BCM43xx_BFL_AFTERBURNER 0x0200 /* supports Afterburner mode */
122 #define BCM43xx_BFL_NOPCI 0x0400 /* leaves PCI floating */
123 #define BCM43xx_BFL_FEM 0x0800 /* supports the Front End Module */
124 #define BCM43xx_BFL_EXTLNA 0x1000 /* has an external LNA */
125 #define BCM43xx_BFL_HGPA 0x2000 /* had high gain PA */
126 #define BCM43xx_BFL_BTCMOD 0x4000 /* BFL_BTCOEXIST is given in alternate GPIOs */
127 #define BCM43xx_BFL_ALTIQ 0x8000 /* alternate I/Q settings */
129 /* GPIO register offset, in both ChipCommon and PCI core. */
130 #define BCM43xx_GPIO_CONTROL 0x6c
133 #define BCM43xx_SHM_SHARED 0x0001
134 #define BCM43xx_SHM_WIRELESS 0x0002
135 #define BCM43xx_SHM_PCM 0x0003
136 #define BCM43xx_SHM_HWMAC 0x0004
137 #define BCM43xx_SHM_UCODE 0x0300
139 /* MacFilter offsets. */
140 #define BCM43xx_MACFILTER_SELF 0x0000
141 #define BCM43xx_MACFILTER_ASSOC 0x0003
143 /* Chipcommon registers. */
144 #define BCM43xx_CHIPCOMMON_CAPABILITIES 0x04
145 #define BCM43xx_CHIPCOMMON_PLLONDELAY 0xB0
146 #define BCM43xx_CHIPCOMMON_FREFSELDELAY 0xB4
147 #define BCM43xx_CHIPCOMMON_SLOWCLKCTL 0xB8
148 #define BCM43xx_CHIPCOMMON_SYSCLKCTL 0xC0
150 /* PCI core specific registers. */
151 #define BCM43xx_PCICORE_BCAST_ADDR 0x50
152 #define BCM43xx_PCICORE_BCAST_DATA 0x54
153 #define BCM43xx_PCICORE_SBTOPCI2 0x108
155 /* SBTOPCI2 values. */
156 #define BCM43xx_SBTOPCI2_PREFETCH 0x4
157 #define BCM43xx_SBTOPCI2_BURST 0x8
159 /* Chipcommon capabilities. */
160 #define BCM43xx_CAPABILITIES_PCTL 0x00040000
161 #define BCM43xx_CAPABILITIES_PLLMASK 0x00030000
162 #define BCM43xx_CAPABILITIES_PLLSHIFT 16
163 #define BCM43xx_CAPABILITIES_FLASHMASK 0x00000700
164 #define BCM43xx_CAPABILITIES_FLASHSHIFT 8
165 #define BCM43xx_CAPABILITIES_EXTBUSPRESENT 0x00000040
166 #define BCM43xx_CAPABILITIES_UARTGPIO 0x00000020
167 #define BCM43xx_CAPABILITIES_UARTCLOCKMASK 0x00000018
168 #define BCM43xx_CAPABILITIES_UARTCLOCKSHIFT 3
169 #define BCM43xx_CAPABILITIES_MIPSBIGENDIAN 0x00000004
170 #define BCM43xx_CAPABILITIES_NRUARTSMASK 0x00000003
173 #define BCM43xx_PCTL_IN 0xB0
174 #define BCM43xx_PCTL_OUT 0xB4
175 #define BCM43xx_PCTL_OUTENABLE 0xB8
176 #define BCM43xx_PCTL_XTAL_POWERUP 0x40
177 #define BCM43xx_PCTL_PLL_POWERDOWN 0x80
179 /* PowerControl Clock Modes */
180 #define BCM43xx_PCTL_CLK_FAST 0x00
181 #define BCM43xx_PCTL_CLK_SLOW 0x01
182 #define BCM43xx_PCTL_CLK_DYNAMIC 0x02
184 #define BCM43xx_PCTL_FORCE_SLOW 0x0800
185 #define BCM43xx_PCTL_FORCE_PLL 0x1000
186 #define BCM43xx_PCTL_DYN_XTAL 0x2000
189 #define BCM43xx_COREID_CHIPCOMMON 0x800
190 #define BCM43xx_COREID_ILINE20 0x801
191 #define BCM43xx_COREID_SDRAM 0x803
192 #define BCM43xx_COREID_PCI 0x804
193 #define BCM43xx_COREID_MIPS 0x805
194 #define BCM43xx_COREID_ETHERNET 0x806
195 #define BCM43xx_COREID_V90 0x807
196 #define BCM43xx_COREID_USB11_HOSTDEV 0x80a
197 #define BCM43xx_COREID_IPSEC 0x80b
198 #define BCM43xx_COREID_PCMCIA 0x80d
199 #define BCM43xx_COREID_EXT_IF 0x80f
200 #define BCM43xx_COREID_80211 0x812
201 #define BCM43xx_COREID_MIPS_3302 0x816
202 #define BCM43xx_COREID_USB11_HOST 0x817
203 #define BCM43xx_COREID_USB11_DEV 0x818
204 #define BCM43xx_COREID_USB20_HOST 0x819
205 #define BCM43xx_COREID_USB20_DEV 0x81a
206 #define BCM43xx_COREID_SDIO_HOST 0x81b
208 /* Core Information Registers */
209 #define BCM43xx_CIR_BASE 0xf00
210 #define BCM43xx_CIR_SBTPSFLAG (BCM43xx_CIR_BASE + 0x18)
211 #define BCM43xx_CIR_SBIMSTATE (BCM43xx_CIR_BASE + 0x90)
212 #define BCM43xx_CIR_SBINTVEC (BCM43xx_CIR_BASE + 0x94)
213 #define BCM43xx_CIR_SBTMSTATELOW (BCM43xx_CIR_BASE + 0x98)
214 #define BCM43xx_CIR_SBTMSTATEHIGH (BCM43xx_CIR_BASE + 0x9c)
215 #define BCM43xx_CIR_SBIMCONFIGLOW (BCM43xx_CIR_BASE + 0xa8)
216 #define BCM43xx_CIR_SB_ID_HI (BCM43xx_CIR_BASE + 0xfc)
218 /* Mask to get the Backplane Flag Number from SBTPSFLAG. */
219 #define BCM43xx_BACKPLANE_FLAG_NR_MASK 0x3f
221 /* SBIMCONFIGLOW values/masks. */
222 #define BCM43xx_SBIMCONFIGLOW_SERVICE_TOUT_MASK 0x00000007
223 #define BCM43xx_SBIMCONFIGLOW_SERVICE_TOUT_SHIFT 0
224 #define BCM43xx_SBIMCONFIGLOW_REQUEST_TOUT_MASK 0x00000070
225 #define BCM43xx_SBIMCONFIGLOW_REQUEST_TOUT_SHIFT 4
226 #define BCM43xx_SBIMCONFIGLOW_CONNID_MASK 0x00ff0000
227 #define BCM43xx_SBIMCONFIGLOW_CONNID_SHIFT 16
229 /* sbtmstatelow state flags */
230 #define BCM43xx_SBTMSTATELOW_RESET 0x01
231 #define BCM43xx_SBTMSTATELOW_REJECT 0x02
232 #define BCM43xx_SBTMSTATELOW_CLOCK 0x10000
233 #define BCM43xx_SBTMSTATELOW_FORCE_GATE_CLOCK 0x20000
235 /* sbtmstatehigh state flags */
236 #define BCM43xx_SBTMSTATEHIGH_SERROR 0x1
237 #define BCM43xx_SBTMSTATEHIGH_BUSY 0x4
239 /* sbimstate flags */
240 #define BCM43xx_SBIMSTATE_IB_ERROR 0x20000
241 #define BCM43xx_SBIMSTATE_TIMEOUT 0x40000
244 #define BCM43xx_PHYTYPE_A 0x00
245 #define BCM43xx_PHYTYPE_B 0x01
246 #define BCM43xx_PHYTYPE_G 0x02
249 #define BCM43xx_PHY_ILT_A_CTRL 0x0072
250 #define BCM43xx_PHY_ILT_A_DATA1 0x0073
251 #define BCM43xx_PHY_ILT_A_DATA2 0x0074
252 #define BCM43xx_PHY_G_LO_CONTROL 0x0810
253 #define BCM43xx_PHY_ILT_G_CTRL 0x0472
254 #define BCM43xx_PHY_ILT_G_DATA1 0x0473
255 #define BCM43xx_PHY_ILT_G_DATA2 0x0474
256 #define BCM43xx_PHY_A_PCTL 0x007B
257 #define BCM43xx_PHY_G_PCTL 0x0029
258 #define BCM43xx_PHY_A_CRS 0x0029
259 #define BCM43xx_PHY_RADIO_BITFIELD 0x0401
260 #define BCM43xx_PHY_G_CRS 0x0429
261 #define BCM43xx_PHY_NRSSILT_CTRL 0x0803
262 #define BCM43xx_PHY_NRSSILT_DATA 0x0804
265 #define BCM43xx_RADIOCTL_ID 0x01
268 #define BCM43xx_SBF_MAC_ENABLED 0x00000001
269 #define BCM43xx_SBF_2 0x00000002 /*FIXME: fix name*/
270 #define BCM43xx_SBF_CORE_READY 0x00000004
271 #define BCM43xx_SBF_400 0x00000400 /*FIXME: fix name*/
272 #define BCM43xx_SBF_4000 0x00004000 /*FIXME: fix name*/
273 #define BCM43xx_SBF_8000 0x00008000 /*FIXME: fix name*/
274 #define BCM43xx_SBF_XFER_REG_BYTESWAP 0x00010000
275 #define BCM43xx_SBF_MODE_NOTADHOC 0x00020000
276 #define BCM43xx_SBF_MODE_AP 0x00040000
277 #define BCM43xx_SBF_RADIOREG_LOCK 0x00080000
278 #define BCM43xx_SBF_MODE_MONITOR 0x00400000
279 #define BCM43xx_SBF_MODE_PROMISC 0x01000000
280 #define BCM43xx_SBF_PS1 0x02000000
281 #define BCM43xx_SBF_PS2 0x04000000
282 #define BCM43xx_SBF_NO_SSID_BCAST 0x08000000
283 #define BCM43xx_SBF_TIME_UPDATE 0x10000000
284 #define BCM43xx_SBF_80000000 0x80000000 /*FIXME: fix name*/
286 /* MicrocodeFlagsBitfield (addr + lo-word values?)*/
287 #define BCM43xx_UCODEFLAGS_OFFSET 0x005E
289 #define BCM43xx_UCODEFLAG_AUTODIV 0x0001
290 #define BCM43xx_UCODEFLAG_UNKBGPHY 0x0002
291 #define BCM43xx_UCODEFLAG_UNKBPHY 0x0004
292 #define BCM43xx_UCODEFLAG_UNKGPHY 0x0020
293 #define BCM43xx_UCODEFLAG_UNKPACTRL 0x0040
294 #define BCM43xx_UCODEFLAG_JAPAN 0x0080
296 /* Generic-Interrupt reasons. */
297 #define BCM43xx_IRQ_READY (1 << 0)
298 #define BCM43xx_IRQ_BEACON (1 << 1)
299 #define BCM43xx_IRQ_PS (1 << 2)
300 #define BCM43xx_IRQ_REG124 (1 << 5)
301 #define BCM43xx_IRQ_PMQ (1 << 6)
302 #define BCM43xx_IRQ_PIO_WORKAROUND (1 << 8)
303 #define BCM43xx_IRQ_XMIT_ERROR (1 << 11)
304 #define BCM43xx_IRQ_RX (1 << 15)
305 #define BCM43xx_IRQ_SCAN (1 << 16)
306 #define BCM43xx_IRQ_NOISE (1 << 18)
307 #define BCM43xx_IRQ_XMIT_STATUS (1 << 29)
309 #define BCM43xx_IRQ_ALL 0xffffffff
310 #define BCM43xx_IRQ_INITIAL (BCM43xx_IRQ_PS | \
311 BCM43xx_IRQ_REG124 | \
313 BCM43xx_IRQ_XMIT_ERROR | \
316 BCM43xx_IRQ_NOISE | \
317 BCM43xx_IRQ_XMIT_STATUS)
320 /* Initial default iw_mode */
321 #define BCM43xx_INITIAL_IWMODE IW_MODE_INFRA
324 #define BCM43xx_BUSTYPE_PCI 0
325 /* Bus type Silicone Backplane Bus. */
326 #define BCM43xx_BUSTYPE_SB 1
327 /* Bus type PCMCIA. */
328 #define BCM43xx_BUSTYPE_PCMCIA 2
330 /* Threshold values. */
331 #define BCM43xx_MIN_RTS_THRESHOLD 1U
332 #define BCM43xx_MAX_RTS_THRESHOLD 2304U
333 #define BCM43xx_DEFAULT_RTS_THRESHOLD BCM43xx_MAX_RTS_THRESHOLD
335 #define BCM43xx_DEFAULT_SHORT_RETRY_LIMIT 7
336 #define BCM43xx_DEFAULT_LONG_RETRY_LIMIT 4
338 /* Max size of a security key */
339 #define BCM43xx_SEC_KEYSIZE 16
340 /* Security algorithms. */
342 BCM43xx_SEC_ALGO_NONE
= 0, /* unencrypted, as of TX header. */
343 BCM43xx_SEC_ALGO_WEP
,
344 BCM43xx_SEC_ALGO_UNKNOWN
,
345 BCM43xx_SEC_ALGO_AES
,
346 BCM43xx_SEC_ALGO_WEP104
,
347 BCM43xx_SEC_ALGO_TKIP
,
353 #ifdef CONFIG_BCM43XX_DEBUG
354 #define assert(expr) \
356 if (unlikely(!(expr))) { \
357 printk(KERN_ERR PFX "ASSERTION FAILED (%s) at: %s:%d:%s()\n", \
358 #expr, __FILE__, __LINE__, __FUNCTION__); \
362 #define assert(expr) do { /* nothing */ } while (0)
365 /* rate limited printk(). */
369 #define printkl(f, x...) do { if (printk_ratelimit()) printk(f ,##x); } while (0)
370 /* rate limited printk() for debugging */
374 #ifdef CONFIG_BCM43XX_DEBUG
375 # define dprintkl printkl
377 # define dprintkl(f, x...) do { /* nothing */ } while (0)
380 /* Helper macro for if branches.
381 * An if branch marked with this macro is only taken in DEBUG mode.
383 * if (DEBUG_ONLY(foo == bar)) {
386 * In DEBUG mode, the branch will be taken if (foo == bar).
387 * In non-DEBUG mode, the branch will never be taken.
392 #ifdef CONFIG_BCM43XX_DEBUG
393 # define DEBUG_ONLY(x) (x)
395 # define DEBUG_ONLY(x) 0
398 /* debugging printk() */
402 #ifdef CONFIG_BCM43XX_DEBUG
403 # define dprintk(f, x...) do { printk(f ,##x); } while (0)
405 # define dprintk(f, x...) do { /* nothing */ } while (0)
411 struct bcm43xx_dmaring
;
412 struct bcm43xx_pioqueue
;
414 struct bcm43xx_initval
{
418 } __attribute__((__packed__
));
420 /* Values for bcm430x_sprominfo.locale */
422 BCM43xx_LOCALE_WORLD
= 0,
423 BCM43xx_LOCALE_THAILAND
,
424 BCM43xx_LOCALE_ISRAEL
,
425 BCM43xx_LOCALE_JORDAN
,
426 BCM43xx_LOCALE_CHINA
,
427 BCM43xx_LOCALE_JAPAN
,
428 BCM43xx_LOCALE_USA_CANADA_ANZ
,
429 BCM43xx_LOCALE_EUROPE
,
430 BCM43xx_LOCALE_USA_LOW
,
431 BCM43xx_LOCALE_JAPAN_HIGH
,
436 #define BCM43xx_SPROM_SIZE 64 /* in 16-bit words. */
437 struct bcm43xx_sprominfo
{
462 u8 idle_tssi_tgt_aphy
;
463 u8 idle_tssi_tgt_bgphy
;
465 u16 antennagain_aphy
;
466 u16 antennagain_bgphy
;
469 /* Value pair to measure the LocalOscillator. */
470 struct bcm43xx_lopair
{
475 #define BCM43xx_LO_COUNT (14*4)
477 struct bcm43xx_phyinfo
{
482 u16 antenna_diversity
;
488 is_locked
:1, /* used in bcm43xx_phy_{un}lock() */
489 dyn_tssi_tbl
:1; /* used in bcm43xx_phy_init_tssi2dbm_table() */
490 /* LO Measurement Data.
491 * Use bcm43xx_get_lopair() to get a value.
493 struct bcm43xx_lopair
*_lo_pairs
;
495 /* TSSI to dBm table in use */
497 /* idle TSSI value */
500 /* Values from bcm43xx_calc_loopback_gain() */
501 u16 loopback_gain
[2];
503 /* PHY lock for core.rev < 3
504 * This lock is only used by bcm43xx_phy_{un}lock()
510 struct bcm43xx_radioinfo
{
515 /* Desired TX power in dBm Q5.2 */
517 /* TX Power control values. */
532 /* Current Interference Mitigation mode */
534 /* Stack of saved values from the Interference Mitigation code.
535 * Each value in the stack is layed out as follows:
537 * bit 12-15: register ID
539 * register ID is: 0x1 PHY, 0x2 Radio, 0x3 ILT
541 #define BCM43xx_INTERFSTACK_SIZE 26
542 u32 interfstack
[BCM43xx_INTERFSTACK_SIZE
];
544 /* Saved values from the NRSSI Slope calculation */
547 /* In memory nrssi lookup table. */
550 /* current channel */
559 /* ACI (adjacent channel interference) flags. */
561 aci_wlan_automatic
:1,
565 /* Data structures for DMA transmission, per 80211 core. */
567 struct bcm43xx_dmaring
*tx_ring0
;
568 struct bcm43xx_dmaring
*tx_ring1
;
569 struct bcm43xx_dmaring
*tx_ring2
;
570 struct bcm43xx_dmaring
*tx_ring3
;
571 struct bcm43xx_dmaring
*rx_ring0
;
572 struct bcm43xx_dmaring
*rx_ring1
; /* only available on core.rev < 5 */
575 /* Data structures for PIO transmission, per 80211 core. */
577 struct bcm43xx_pioqueue
*queue0
;
578 struct bcm43xx_pioqueue
*queue1
;
579 struct bcm43xx_pioqueue
*queue2
;
580 struct bcm43xx_pioqueue
*queue3
;
583 #define BCM43xx_MAX_80211_CORES 2
585 #ifdef CONFIG_BCM947XX
586 #define core_offset(bcm) (bcm)->current_core_offset
588 #define core_offset(bcm) 0
591 /* Generic information about a core. */
592 struct bcm43xx_coreinfo
{
596 /** core_id ID number */
598 /** core_rev revision number */
600 /** Index number for _switch_core() */
604 /* Additional information for each 80211 core. */
605 struct bcm43xx_coreinfo_80211
{
607 struct bcm43xx_phyinfo phy
;
609 struct bcm43xx_radioinfo radio
;
612 struct bcm43xx_dma dma
;
614 struct bcm43xx_pio pio
;
618 /* Context information for a noise calculation (Link Quality). */
619 struct bcm43xx_noise_calculation
{
620 struct bcm43xx_coreinfo
*core_at_start
;
622 u8 calculation_running
:1;
627 struct bcm43xx_stats
{
630 struct iw_statistics wstats
;
631 /* Store the last TX/RX times here for updating the leds. */
632 unsigned long last_tx
;
633 unsigned long last_rx
;
641 /* Driver initialization status. */
643 BCM43xx_STAT_UNINIT
, /* Uninitialized. */
644 BCM43xx_STAT_INITIALIZING
, /* init_board() in progress. */
645 BCM43xx_STAT_INITIALIZED
, /* Fully operational. */
646 BCM43xx_STAT_SHUTTINGDOWN
, /* free_board() in progress. */
647 BCM43xx_STAT_RESTARTING
, /* controller_restart() called. */
649 #define bcm43xx_status(bcm) atomic_read(&(bcm)->init_status)
650 #define bcm43xx_set_status(bcm, stat) atomic_set(&(bcm)->init_status, (stat))
652 struct bcm43xx_private
{
653 struct ieee80211_device
*ieee
;
654 struct ieee80211softmac_device
*softmac
;
656 struct net_device
*net_dev
;
657 struct pci_dev
*pci_dev
;
660 void __iomem
*mmio_addr
;
662 /* Locking, see "theory of locking" text below. */
666 /* Driver initialization status BCM43xx_STAT_*** */
667 atomic_t init_status
;
669 u16 was_initialized
:1, /* for PCI suspend/resume. */
670 __using_pio
:1, /* Internal, use bcm43xx_using_pio(). */
671 bad_frames_preempt
:1, /* Use "Bad Frames Preemption" (default off) */
672 reg124_set_0x4
:1, /* Some variable to keep track of IRQ stuff. */
673 short_preamble
:1, /* TRUE, if short preamble is enabled. */
674 firmware_norelease
:1; /* Do not release the firmware. Used on suspend. */
676 struct bcm43xx_stats stats
;
678 /* Bus type we are connected to.
679 * This is currently always BCM43xx_BUSTYPE_PCI
691 struct bcm43xx_sprominfo sprom
;
692 #define BCM43xx_NR_LEDS 4
693 struct bcm43xx_led leds
[BCM43xx_NR_LEDS
];
695 /* The currently active core. */
696 struct bcm43xx_coreinfo
*current_core
;
697 #ifdef CONFIG_BCM947XX
698 /** current core memory offset */
699 u32 current_core_offset
;
701 struct bcm43xx_coreinfo
*active_80211_core
;
702 /* coreinfo structs for all possible cores follow.
703 * Note that a core might not exist.
704 * So check the coreinfo flags before using it.
706 struct bcm43xx_coreinfo core_chipcommon
;
707 struct bcm43xx_coreinfo core_pci
;
708 struct bcm43xx_coreinfo core_80211
[ BCM43xx_MAX_80211_CORES
];
709 /* Additional information, specific to the 80211 cores. */
710 struct bcm43xx_coreinfo_80211 core_80211_ext
[ BCM43xx_MAX_80211_CORES
];
711 /* Index of the current 80211 core. If current_core is not
712 * an 80211 core, this is -1.
714 int current_80211_core_idx
;
715 /* Number of available 80211 cores. */
716 int nr_80211_available
;
718 u32 chipcommon_capabilities
;
720 /* Reason code of the last interrupt. */
723 /* saved irq enable/disable state bitfield. */
725 /* Link Quality calculation context. */
726 struct bcm43xx_noise_calculation noisecalc
;
728 /* Threshold values. */
729 //TODO: The RTS thr has to be _used_. Currently, it is only set via WX.
732 /* Interrupt Service Routine tasklet (bottom-half) */
733 struct tasklet_struct isr_tasklet
;
736 struct work_struct periodic_work
;
737 unsigned int periodic_state
;
739 struct work_struct restart_work
;
741 /* Informational stuff. */
742 char nick
[IW_ESSID_MAX_SIZE
+ 1];
744 /* encryption/decryption */
746 struct bcm43xx_key key
[54];
750 const struct firmware
*ucode
;
751 const struct firmware
*pcm
;
752 const struct firmware
*initvals0
;
753 const struct firmware
*initvals1
;
755 /* Random Number Generator. */
757 char rng_name
[20 + 1];
759 /* Debugging stuff follows. */
760 #ifdef CONFIG_BCM43XX_DEBUG
761 struct bcm43xx_dfsentry
*dfsentry
;
766 /* *** THEORY OF LOCKING ***
768 * We have two different locks in the bcm43xx driver.
769 * => bcm->mutex: General sleeping mutex. Protects struct bcm43xx_private
770 * and the device registers.
771 * => bcm->irq_lock: IRQ spinlock. Protects against IRQ handler concurrency.
773 * We have three types of helper function pairs to utilize these locks.
774 * (Always use the helper functions.)
775 * 1) bcm43xx_{un}lock_noirq():
776 * Takes bcm->mutex. Does _not_ protect against IRQ concurrency,
777 * so it is almost always unsafe, if device IRQs are enabled.
778 * So only use this, if device IRQs are masked.
780 * You can sleep within the critical section.
781 * 2) bcm43xx_{un}lock_irqonly():
782 * Takes bcm->irq_lock. Does _not_ protect against
783 * bcm43xx_lock_noirq() critical sections.
784 * Does only protect against the IRQ handler path and other
785 * irqonly() critical sections.
786 * Locking does not sleep.
787 * You must not sleep within the critical section.
788 * 3) bcm43xx_{un}lock_irqsafe():
789 * This is the cummulative lock and takes both, mutex and irq_lock.
790 * Protects against noirq() and irqonly() critical sections (and
791 * the IRQ handler path).
793 * You must not sleep within the critical section.
797 #define bcm43xx_lock_noirq(bcm) mutex_lock(&(bcm)->mutex)
798 #define bcm43xx_unlock_noirq(bcm) mutex_unlock(&(bcm)->mutex)
800 #define bcm43xx_lock_irqonly(bcm, flags) \
801 spin_lock_irqsave(&(bcm)->irq_lock, flags)
802 #define bcm43xx_unlock_irqonly(bcm, flags) \
803 spin_unlock_irqrestore(&(bcm)->irq_lock, flags)
805 #define bcm43xx_lock_irqsafe(bcm, flags) do { \
806 bcm43xx_lock_noirq(bcm); \
807 bcm43xx_lock_irqonly(bcm, flags); \
809 #define bcm43xx_unlock_irqsafe(bcm, flags) do { \
810 bcm43xx_unlock_irqonly(bcm, flags); \
811 bcm43xx_unlock_noirq(bcm); \
816 struct bcm43xx_private
* bcm43xx_priv(struct net_device
*dev
)
818 return ieee80211softmac_priv(dev
);
824 struct bcm43xx_private
* dev_to_bcm(struct device
*dev
)
826 struct net_device
*net_dev
;
827 struct bcm43xx_private
*bcm
;
829 net_dev
= dev_get_drvdata(dev
);
830 bcm
= bcm43xx_priv(net_dev
);
836 /* Helper function, which returns a boolean.
837 * TRUE, if PIO is used; FALSE, if DMA is used.
839 #if defined(CONFIG_BCM43XX_DMA) && defined(CONFIG_BCM43XX_PIO)
841 int bcm43xx_using_pio(struct bcm43xx_private
*bcm
)
843 return bcm
->__using_pio
;
845 #elif defined(CONFIG_BCM43XX_DMA)
847 int bcm43xx_using_pio(struct bcm43xx_private
*bcm
)
851 #elif defined(CONFIG_BCM43XX_PIO)
853 int bcm43xx_using_pio(struct bcm43xx_private
*bcm
)
858 # error "Using neither DMA nor PIO? Confused..."
861 /* Helper functions to access data structures private to the 80211 cores.
862 * Note that we _must_ have an 80211 core mapped when calling
863 * any of these functions.
866 struct bcm43xx_pio
* bcm43xx_current_pio(struct bcm43xx_private
*bcm
)
868 assert(bcm43xx_using_pio(bcm
));
869 assert(bcm
->current_80211_core_idx
>= 0);
870 assert(bcm
->current_80211_core_idx
< BCM43xx_MAX_80211_CORES
);
871 return &(bcm
->core_80211_ext
[bcm
->current_80211_core_idx
].pio
);
874 struct bcm43xx_dma
* bcm43xx_current_dma(struct bcm43xx_private
*bcm
)
876 assert(!bcm43xx_using_pio(bcm
));
877 assert(bcm
->current_80211_core_idx
>= 0);
878 assert(bcm
->current_80211_core_idx
< BCM43xx_MAX_80211_CORES
);
879 return &(bcm
->core_80211_ext
[bcm
->current_80211_core_idx
].dma
);
882 struct bcm43xx_phyinfo
* bcm43xx_current_phy(struct bcm43xx_private
*bcm
)
884 assert(bcm
->current_80211_core_idx
>= 0);
885 assert(bcm
->current_80211_core_idx
< BCM43xx_MAX_80211_CORES
);
886 return &(bcm
->core_80211_ext
[bcm
->current_80211_core_idx
].phy
);
889 struct bcm43xx_radioinfo
* bcm43xx_current_radio(struct bcm43xx_private
*bcm
)
891 assert(bcm
->current_80211_core_idx
>= 0);
892 assert(bcm
->current_80211_core_idx
< BCM43xx_MAX_80211_CORES
);
893 return &(bcm
->core_80211_ext
[bcm
->current_80211_core_idx
].radio
);
898 struct bcm43xx_lopair
* bcm43xx_get_lopair(struct bcm43xx_phyinfo
*phy
,
899 u16 radio_attenuation
,
900 u16 baseband_attenuation
)
902 return phy
->_lo_pairs
+ (radio_attenuation
+ 14 * (baseband_attenuation
/ 2));
907 u16
bcm43xx_read16(struct bcm43xx_private
*bcm
, u16 offset
)
909 return ioread16(bcm
->mmio_addr
+ core_offset(bcm
) + offset
);
913 void bcm43xx_write16(struct bcm43xx_private
*bcm
, u16 offset
, u16 value
)
915 iowrite16(value
, bcm
->mmio_addr
+ core_offset(bcm
) + offset
);
919 u32
bcm43xx_read32(struct bcm43xx_private
*bcm
, u16 offset
)
921 return ioread32(bcm
->mmio_addr
+ core_offset(bcm
) + offset
);
925 void bcm43xx_write32(struct bcm43xx_private
*bcm
, u16 offset
, u32 value
)
927 iowrite32(value
, bcm
->mmio_addr
+ core_offset(bcm
) + offset
);
931 int bcm43xx_pci_read_config16(struct bcm43xx_private
*bcm
, int offset
, u16
*value
)
933 return pci_read_config_word(bcm
->pci_dev
, offset
, value
);
937 int bcm43xx_pci_read_config32(struct bcm43xx_private
*bcm
, int offset
, u32
*value
)
939 return pci_read_config_dword(bcm
->pci_dev
, offset
, value
);
943 int bcm43xx_pci_write_config16(struct bcm43xx_private
*bcm
, int offset
, u16 value
)
945 return pci_write_config_word(bcm
->pci_dev
, offset
, value
);
949 int bcm43xx_pci_write_config32(struct bcm43xx_private
*bcm
, int offset
, u32 value
)
951 return pci_write_config_dword(bcm
->pci_dev
, offset
, value
);
954 /** Limit a value between two limits */
958 #define limit_value(value, min, max) \
960 typeof(value) __value = (value); \
961 typeof(value) __min = (min); \
962 typeof(value) __max = (max); \
963 if (__value < __min) \
965 else if (__value > __max) \
970 /** Helpers to print MAC addresses. */
971 #define BCM43xx_MACFMT "%02x:%02x:%02x:%02x:%02x:%02x"
972 #define BCM43xx_MACARG(x) ((u8*)(x))[0], ((u8*)(x))[1], \
973 ((u8*)(x))[2], ((u8*)(x))[3], \
974 ((u8*)(x))[4], ((u8*)(x))[5]
976 #endif /* BCM43xx_H_ */