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brcmfmac: remove brcmf_find_bssidx() function
[deliverable/linux.git] / drivers / net / wireless / brcm80211 / brcmfmac / dhd_sdio.c
1 /*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
18
19 #include <linux/types.h>
20 #include <linux/kernel.h>
21 #include <linux/kthread.h>
22 #include <linux/printk.h>
23 #include <linux/pci_ids.h>
24 #include <linux/netdevice.h>
25 #include <linux/interrupt.h>
26 #include <linux/sched.h>
27 #include <linux/mmc/sdio.h>
28 #include <linux/mmc/sdio_func.h>
29 #include <linux/mmc/card.h>
30 #include <linux/semaphore.h>
31 #include <linux/firmware.h>
32 #include <linux/module.h>
33 #include <linux/bcma/bcma.h>
34 #include <linux/debugfs.h>
35 #include <linux/vmalloc.h>
36 #include <asm/unaligned.h>
37 #include <defs.h>
38 #include <brcmu_wifi.h>
39 #include <brcmu_utils.h>
40 #include <brcm_hw_ids.h>
41 #include <soc.h>
42 #include "sdio_host.h"
43 #include "sdio_chip.h"
44
45 #define DCMD_RESP_TIMEOUT 2000 /* In milli second */
46
47 #ifdef DEBUG
48
49 #define BRCMF_TRAP_INFO_SIZE 80
50
51 #define CBUF_LEN (128)
52
53 /* Device console log buffer state */
54 #define CONSOLE_BUFFER_MAX 2024
55
56 struct rte_log_le {
57 __le32 buf; /* Can't be pointer on (64-bit) hosts */
58 __le32 buf_size;
59 __le32 idx;
60 char *_buf_compat; /* Redundant pointer for backward compat. */
61 };
62
63 struct rte_console {
64 /* Virtual UART
65 * When there is no UART (e.g. Quickturn),
66 * the host should write a complete
67 * input line directly into cbuf and then write
68 * the length into vcons_in.
69 * This may also be used when there is a real UART
70 * (at risk of conflicting with
71 * the real UART). vcons_out is currently unused.
72 */
73 uint vcons_in;
74 uint vcons_out;
75
76 /* Output (logging) buffer
77 * Console output is written to a ring buffer log_buf at index log_idx.
78 * The host may read the output when it sees log_idx advance.
79 * Output will be lost if the output wraps around faster than the host
80 * polls.
81 */
82 struct rte_log_le log_le;
83
84 /* Console input line buffer
85 * Characters are read one at a time into cbuf
86 * until <CR> is received, then
87 * the buffer is processed as a command line.
88 * Also used for virtual UART.
89 */
90 uint cbuf_idx;
91 char cbuf[CBUF_LEN];
92 };
93
94 #endif /* DEBUG */
95 #include <chipcommon.h>
96
97 #include "dhd_bus.h"
98 #include "dhd_dbg.h"
99
100 #define TXQLEN 2048 /* bulk tx queue length */
101 #define TXHI (TXQLEN - 256) /* turn on flow control above TXHI */
102 #define TXLOW (TXHI - 256) /* turn off flow control below TXLOW */
103 #define PRIOMASK 7
104
105 #define TXRETRIES 2 /* # of retries for tx frames */
106
107 #define BRCMF_RXBOUND 50 /* Default for max rx frames in
108 one scheduling */
109
110 #define BRCMF_TXBOUND 20 /* Default for max tx frames in
111 one scheduling */
112
113 #define BRCMF_TXMINMAX 1 /* Max tx frames if rx still pending */
114
115 #define MEMBLOCK 2048 /* Block size used for downloading
116 of dongle image */
117 #define MAX_DATA_BUF (32 * 1024) /* Must be large enough to hold
118 biggest possible glom */
119
120 #define BRCMF_FIRSTREAD (1 << 6)
121
122
123 /* SBSDIO_DEVICE_CTL */
124
125 /* 1: device will assert busy signal when receiving CMD53 */
126 #define SBSDIO_DEVCTL_SETBUSY 0x01
127 /* 1: assertion of sdio interrupt is synchronous to the sdio clock */
128 #define SBSDIO_DEVCTL_SPI_INTR_SYNC 0x02
129 /* 1: mask all interrupts to host except the chipActive (rev 8) */
130 #define SBSDIO_DEVCTL_CA_INT_ONLY 0x04
131 /* 1: isolate internal sdio signals, put external pads in tri-state; requires
132 * sdio bus power cycle to clear (rev 9) */
133 #define SBSDIO_DEVCTL_PADS_ISO 0x08
134 /* Force SD->SB reset mapping (rev 11) */
135 #define SBSDIO_DEVCTL_SB_RST_CTL 0x30
136 /* Determined by CoreControl bit */
137 #define SBSDIO_DEVCTL_RST_CORECTL 0x00
138 /* Force backplane reset */
139 #define SBSDIO_DEVCTL_RST_BPRESET 0x10
140 /* Force no backplane reset */
141 #define SBSDIO_DEVCTL_RST_NOBPRESET 0x20
142
143 /* direct(mapped) cis space */
144
145 /* MAPPED common CIS address */
146 #define SBSDIO_CIS_BASE_COMMON 0x1000
147 /* maximum bytes in one CIS */
148 #define SBSDIO_CIS_SIZE_LIMIT 0x200
149 /* cis offset addr is < 17 bits */
150 #define SBSDIO_CIS_OFT_ADDR_MASK 0x1FFFF
151
152 /* manfid tuple length, include tuple, link bytes */
153 #define SBSDIO_CIS_MANFID_TUPLE_LEN 6
154
155 /* intstatus */
156 #define I_SMB_SW0 (1 << 0) /* To SB Mail S/W interrupt 0 */
157 #define I_SMB_SW1 (1 << 1) /* To SB Mail S/W interrupt 1 */
158 #define I_SMB_SW2 (1 << 2) /* To SB Mail S/W interrupt 2 */
159 #define I_SMB_SW3 (1 << 3) /* To SB Mail S/W interrupt 3 */
160 #define I_SMB_SW_MASK 0x0000000f /* To SB Mail S/W interrupts mask */
161 #define I_SMB_SW_SHIFT 0 /* To SB Mail S/W interrupts shift */
162 #define I_HMB_SW0 (1 << 4) /* To Host Mail S/W interrupt 0 */
163 #define I_HMB_SW1 (1 << 5) /* To Host Mail S/W interrupt 1 */
164 #define I_HMB_SW2 (1 << 6) /* To Host Mail S/W interrupt 2 */
165 #define I_HMB_SW3 (1 << 7) /* To Host Mail S/W interrupt 3 */
166 #define I_HMB_SW_MASK 0x000000f0 /* To Host Mail S/W interrupts mask */
167 #define I_HMB_SW_SHIFT 4 /* To Host Mail S/W interrupts shift */
168 #define I_WR_OOSYNC (1 << 8) /* Write Frame Out Of Sync */
169 #define I_RD_OOSYNC (1 << 9) /* Read Frame Out Of Sync */
170 #define I_PC (1 << 10) /* descriptor error */
171 #define I_PD (1 << 11) /* data error */
172 #define I_DE (1 << 12) /* Descriptor protocol Error */
173 #define I_RU (1 << 13) /* Receive descriptor Underflow */
174 #define I_RO (1 << 14) /* Receive fifo Overflow */
175 #define I_XU (1 << 15) /* Transmit fifo Underflow */
176 #define I_RI (1 << 16) /* Receive Interrupt */
177 #define I_BUSPWR (1 << 17) /* SDIO Bus Power Change (rev 9) */
178 #define I_XMTDATA_AVAIL (1 << 23) /* bits in fifo */
179 #define I_XI (1 << 24) /* Transmit Interrupt */
180 #define I_RF_TERM (1 << 25) /* Read Frame Terminate */
181 #define I_WF_TERM (1 << 26) /* Write Frame Terminate */
182 #define I_PCMCIA_XU (1 << 27) /* PCMCIA Transmit FIFO Underflow */
183 #define I_SBINT (1 << 28) /* sbintstatus Interrupt */
184 #define I_CHIPACTIVE (1 << 29) /* chip from doze to active state */
185 #define I_SRESET (1 << 30) /* CCCR RES interrupt */
186 #define I_IOE2 (1U << 31) /* CCCR IOE2 Bit Changed */
187 #define I_ERRORS (I_PC | I_PD | I_DE | I_RU | I_RO | I_XU)
188 #define I_DMA (I_RI | I_XI | I_ERRORS)
189
190 /* corecontrol */
191 #define CC_CISRDY (1 << 0) /* CIS Ready */
192 #define CC_BPRESEN (1 << 1) /* CCCR RES signal */
193 #define CC_F2RDY (1 << 2) /* set CCCR IOR2 bit */
194 #define CC_CLRPADSISO (1 << 3) /* clear SDIO pads isolation */
195 #define CC_XMTDATAAVAIL_MODE (1 << 4)
196 #define CC_XMTDATAAVAIL_CTRL (1 << 5)
197
198 /* SDA_FRAMECTRL */
199 #define SFC_RF_TERM (1 << 0) /* Read Frame Terminate */
200 #define SFC_WF_TERM (1 << 1) /* Write Frame Terminate */
201 #define SFC_CRC4WOOS (1 << 2) /* CRC error for write out of sync */
202 #define SFC_ABORTALL (1 << 3) /* Abort all in-progress frames */
203
204 /* HW frame tag */
205 #define SDPCM_FRAMETAG_LEN 4 /* 2 bytes len, 2 bytes check val */
206
207 /* Total length of frame header for dongle protocol */
208 #define SDPCM_HDRLEN (SDPCM_FRAMETAG_LEN + SDPCM_SWHEADER_LEN)
209 #define SDPCM_RESERVE (SDPCM_HDRLEN + BRCMF_SDALIGN)
210
211 /*
212 * Software allocation of To SB Mailbox resources
213 */
214
215 /* tosbmailbox bits corresponding to intstatus bits */
216 #define SMB_NAK (1 << 0) /* Frame NAK */
217 #define SMB_INT_ACK (1 << 1) /* Host Interrupt ACK */
218 #define SMB_USE_OOB (1 << 2) /* Use OOB Wakeup */
219 #define SMB_DEV_INT (1 << 3) /* Miscellaneous Interrupt */
220
221 /* tosbmailboxdata */
222 #define SMB_DATA_VERSION_SHIFT 16 /* host protocol version */
223
224 /*
225 * Software allocation of To Host Mailbox resources
226 */
227
228 /* intstatus bits */
229 #define I_HMB_FC_STATE I_HMB_SW0 /* Flow Control State */
230 #define I_HMB_FC_CHANGE I_HMB_SW1 /* Flow Control State Changed */
231 #define I_HMB_FRAME_IND I_HMB_SW2 /* Frame Indication */
232 #define I_HMB_HOST_INT I_HMB_SW3 /* Miscellaneous Interrupt */
233
234 /* tohostmailboxdata */
235 #define HMB_DATA_NAKHANDLED 1 /* retransmit NAK'd frame */
236 #define HMB_DATA_DEVREADY 2 /* talk to host after enable */
237 #define HMB_DATA_FC 4 /* per prio flowcontrol update flag */
238 #define HMB_DATA_FWREADY 8 /* fw ready for protocol activity */
239
240 #define HMB_DATA_FCDATA_MASK 0xff000000
241 #define HMB_DATA_FCDATA_SHIFT 24
242
243 #define HMB_DATA_VERSION_MASK 0x00ff0000
244 #define HMB_DATA_VERSION_SHIFT 16
245
246 /*
247 * Software-defined protocol header
248 */
249
250 /* Current protocol version */
251 #define SDPCM_PROT_VERSION 4
252
253 /* SW frame header */
254 #define SDPCM_PACKET_SEQUENCE(p) (((u8 *)p)[0] & 0xff)
255
256 #define SDPCM_CHANNEL_MASK 0x00000f00
257 #define SDPCM_CHANNEL_SHIFT 8
258 #define SDPCM_PACKET_CHANNEL(p) (((u8 *)p)[1] & 0x0f)
259
260 #define SDPCM_NEXTLEN_OFFSET 2
261
262 /* Data Offset from SOF (HW Tag, SW Tag, Pad) */
263 #define SDPCM_DOFFSET_OFFSET 3 /* Data Offset */
264 #define SDPCM_DOFFSET_VALUE(p) (((u8 *)p)[SDPCM_DOFFSET_OFFSET] & 0xff)
265 #define SDPCM_DOFFSET_MASK 0xff000000
266 #define SDPCM_DOFFSET_SHIFT 24
267 #define SDPCM_FCMASK_OFFSET 4 /* Flow control */
268 #define SDPCM_FCMASK_VALUE(p) (((u8 *)p)[SDPCM_FCMASK_OFFSET] & 0xff)
269 #define SDPCM_WINDOW_OFFSET 5 /* Credit based fc */
270 #define SDPCM_WINDOW_VALUE(p) (((u8 *)p)[SDPCM_WINDOW_OFFSET] & 0xff)
271
272 #define SDPCM_SWHEADER_LEN 8 /* SW header is 64 bits */
273
274 /* logical channel numbers */
275 #define SDPCM_CONTROL_CHANNEL 0 /* Control channel Id */
276 #define SDPCM_EVENT_CHANNEL 1 /* Asyc Event Indication Channel Id */
277 #define SDPCM_DATA_CHANNEL 2 /* Data Xmit/Recv Channel Id */
278 #define SDPCM_GLOM_CHANNEL 3 /* For coalesced packets */
279 #define SDPCM_TEST_CHANNEL 15 /* Reserved for test/debug packets */
280
281 #define SDPCM_SEQUENCE_WRAP 256 /* wrap-around val for 8bit frame seq */
282
283 #define SDPCM_GLOMDESC(p) (((u8 *)p)[1] & 0x80)
284
285 /*
286 * Shared structure between dongle and the host.
287 * The structure contains pointers to trap or assert information.
288 */
289 #define SDPCM_SHARED_VERSION 0x0003
290 #define SDPCM_SHARED_VERSION_MASK 0x00FF
291 #define SDPCM_SHARED_ASSERT_BUILT 0x0100
292 #define SDPCM_SHARED_ASSERT 0x0200
293 #define SDPCM_SHARED_TRAP 0x0400
294
295 /* Space for header read, limit for data packets */
296 #define MAX_HDR_READ (1 << 6)
297 #define MAX_RX_DATASZ 2048
298
299 /* Maximum milliseconds to wait for F2 to come up */
300 #define BRCMF_WAIT_F2RDY 3000
301
302 /* Bump up limit on waiting for HT to account for first startup;
303 * if the image is doing a CRC calculation before programming the PMU
304 * for HT availability, it could take a couple hundred ms more, so
305 * max out at a 1 second (1000000us).
306 */
307 #undef PMU_MAX_TRANSITION_DLY
308 #define PMU_MAX_TRANSITION_DLY 1000000
309
310 /* Value for ChipClockCSR during initial setup */
311 #define BRCMF_INIT_CLKCTL1 (SBSDIO_FORCE_HW_CLKREQ_OFF | \
312 SBSDIO_ALP_AVAIL_REQ)
313
314 /* Flags for SDH calls */
315 #define F2SYNC (SDIO_REQ_4BYTE | SDIO_REQ_FIXED)
316
317 #define BRCMF_SDIO_FW_NAME "brcm/brcmfmac-sdio.bin"
318 #define BRCMF_SDIO_NV_NAME "brcm/brcmfmac-sdio.txt"
319 MODULE_FIRMWARE(BRCMF_SDIO_FW_NAME);
320 MODULE_FIRMWARE(BRCMF_SDIO_NV_NAME);
321
322 #define BRCMF_IDLE_IMMEDIATE (-1) /* Enter idle immediately */
323 #define BRCMF_IDLE_ACTIVE 0 /* Do not request any SD clock change
324 * when idle
325 */
326 #define BRCMF_IDLE_INTERVAL 1
327
328 /*
329 * Conversion of 802.1D priority to precedence level
330 */
331 static uint prio2prec(u32 prio)
332 {
333 return (prio == PRIO_8021D_NONE || prio == PRIO_8021D_BE) ?
334 (prio^2) : prio;
335 }
336
337 /* core registers */
338 struct sdpcmd_regs {
339 u32 corecontrol; /* 0x00, rev8 */
340 u32 corestatus; /* rev8 */
341 u32 PAD[1];
342 u32 biststatus; /* rev8 */
343
344 /* PCMCIA access */
345 u16 pcmciamesportaladdr; /* 0x010, rev8 */
346 u16 PAD[1];
347 u16 pcmciamesportalmask; /* rev8 */
348 u16 PAD[1];
349 u16 pcmciawrframebc; /* rev8 */
350 u16 PAD[1];
351 u16 pcmciaunderflowtimer; /* rev8 */
352 u16 PAD[1];
353
354 /* interrupt */
355 u32 intstatus; /* 0x020, rev8 */
356 u32 hostintmask; /* rev8 */
357 u32 intmask; /* rev8 */
358 u32 sbintstatus; /* rev8 */
359 u32 sbintmask; /* rev8 */
360 u32 funcintmask; /* rev4 */
361 u32 PAD[2];
362 u32 tosbmailbox; /* 0x040, rev8 */
363 u32 tohostmailbox; /* rev8 */
364 u32 tosbmailboxdata; /* rev8 */
365 u32 tohostmailboxdata; /* rev8 */
366
367 /* synchronized access to registers in SDIO clock domain */
368 u32 sdioaccess; /* 0x050, rev8 */
369 u32 PAD[3];
370
371 /* PCMCIA frame control */
372 u8 pcmciaframectrl; /* 0x060, rev8 */
373 u8 PAD[3];
374 u8 pcmciawatermark; /* rev8 */
375 u8 PAD[155];
376
377 /* interrupt batching control */
378 u32 intrcvlazy; /* 0x100, rev8 */
379 u32 PAD[3];
380
381 /* counters */
382 u32 cmd52rd; /* 0x110, rev8 */
383 u32 cmd52wr; /* rev8 */
384 u32 cmd53rd; /* rev8 */
385 u32 cmd53wr; /* rev8 */
386 u32 abort; /* rev8 */
387 u32 datacrcerror; /* rev8 */
388 u32 rdoutofsync; /* rev8 */
389 u32 wroutofsync; /* rev8 */
390 u32 writebusy; /* rev8 */
391 u32 readwait; /* rev8 */
392 u32 readterm; /* rev8 */
393 u32 writeterm; /* rev8 */
394 u32 PAD[40];
395 u32 clockctlstatus; /* rev8 */
396 u32 PAD[7];
397
398 u32 PAD[128]; /* DMA engines */
399
400 /* SDIO/PCMCIA CIS region */
401 char cis[512]; /* 0x400-0x5ff, rev6 */
402
403 /* PCMCIA function control registers */
404 char pcmciafcr[256]; /* 0x600-6ff, rev6 */
405 u16 PAD[55];
406
407 /* PCMCIA backplane access */
408 u16 backplanecsr; /* 0x76E, rev6 */
409 u16 backplaneaddr0; /* rev6 */
410 u16 backplaneaddr1; /* rev6 */
411 u16 backplaneaddr2; /* rev6 */
412 u16 backplaneaddr3; /* rev6 */
413 u16 backplanedata0; /* rev6 */
414 u16 backplanedata1; /* rev6 */
415 u16 backplanedata2; /* rev6 */
416 u16 backplanedata3; /* rev6 */
417 u16 PAD[31];
418
419 /* sprom "size" & "blank" info */
420 u16 spromstatus; /* 0x7BE, rev2 */
421 u32 PAD[464];
422
423 u16 PAD[0x80];
424 };
425
426 #ifdef DEBUG
427 /* Device console log buffer state */
428 struct brcmf_console {
429 uint count; /* Poll interval msec counter */
430 uint log_addr; /* Log struct address (fixed) */
431 struct rte_log_le log_le; /* Log struct (host copy) */
432 uint bufsize; /* Size of log buffer */
433 u8 *buf; /* Log buffer (host copy) */
434 uint last; /* Last buffer read index */
435 };
436
437 struct brcmf_trap_info {
438 __le32 type;
439 __le32 epc;
440 __le32 cpsr;
441 __le32 spsr;
442 __le32 r0; /* a1 */
443 __le32 r1; /* a2 */
444 __le32 r2; /* a3 */
445 __le32 r3; /* a4 */
446 __le32 r4; /* v1 */
447 __le32 r5; /* v2 */
448 __le32 r6; /* v3 */
449 __le32 r7; /* v4 */
450 __le32 r8; /* v5 */
451 __le32 r9; /* sb/v6 */
452 __le32 r10; /* sl/v7 */
453 __le32 r11; /* fp/v8 */
454 __le32 r12; /* ip */
455 __le32 r13; /* sp */
456 __le32 r14; /* lr */
457 __le32 pc; /* r15 */
458 };
459 #endif /* DEBUG */
460
461 struct sdpcm_shared {
462 u32 flags;
463 u32 trap_addr;
464 u32 assert_exp_addr;
465 u32 assert_file_addr;
466 u32 assert_line;
467 u32 console_addr; /* Address of struct rte_console */
468 u32 msgtrace_addr;
469 u8 tag[32];
470 u32 brpt_addr;
471 };
472
473 struct sdpcm_shared_le {
474 __le32 flags;
475 __le32 trap_addr;
476 __le32 assert_exp_addr;
477 __le32 assert_file_addr;
478 __le32 assert_line;
479 __le32 console_addr; /* Address of struct rte_console */
480 __le32 msgtrace_addr;
481 u8 tag[32];
482 __le32 brpt_addr;
483 };
484
485 /* SDIO read frame info */
486 struct brcmf_sdio_read {
487 u8 seq_num;
488 u8 channel;
489 u16 len;
490 u16 len_left;
491 u16 len_nxtfrm;
492 u8 dat_offset;
493 };
494
495 /* misc chip info needed by some of the routines */
496 /* Private data for SDIO bus interaction */
497 struct brcmf_sdio {
498 struct brcmf_sdio_dev *sdiodev; /* sdio device handler */
499 struct chip_info *ci; /* Chip info struct */
500 char *vars; /* Variables (from CIS and/or other) */
501 uint varsz; /* Size of variables buffer */
502
503 u32 ramsize; /* Size of RAM in SOCRAM (bytes) */
504
505 u32 hostintmask; /* Copy of Host Interrupt Mask */
506 atomic_t intstatus; /* Intstatus bits (events) pending */
507 atomic_t fcstate; /* State of dongle flow-control */
508
509 uint blocksize; /* Block size of SDIO transfers */
510 uint roundup; /* Max roundup limit */
511
512 struct pktq txq; /* Queue length used for flow-control */
513 u8 flowcontrol; /* per prio flow control bitmask */
514 u8 tx_seq; /* Transmit sequence number (next) */
515 u8 tx_max; /* Maximum transmit sequence allowed */
516
517 u8 hdrbuf[MAX_HDR_READ + BRCMF_SDALIGN];
518 u8 *rxhdr; /* Header of current rx frame (in hdrbuf) */
519 u8 rx_seq; /* Receive sequence number (expected) */
520 struct brcmf_sdio_read cur_read;
521 /* info of current read frame */
522 bool rxskip; /* Skip receive (awaiting NAK ACK) */
523 bool rxpending; /* Data frame pending in dongle */
524
525 uint rxbound; /* Rx frames to read before resched */
526 uint txbound; /* Tx frames to send before resched */
527 uint txminmax;
528
529 struct sk_buff *glomd; /* Packet containing glomming descriptor */
530 struct sk_buff_head glom; /* Packet list for glommed superframe */
531 uint glomerr; /* Glom packet read errors */
532
533 u8 *rxbuf; /* Buffer for receiving control packets */
534 uint rxblen; /* Allocated length of rxbuf */
535 u8 *rxctl; /* Aligned pointer into rxbuf */
536 u8 *databuf; /* Buffer for receiving big glom packet */
537 u8 *dataptr; /* Aligned pointer into databuf */
538 uint rxlen; /* Length of valid data in buffer */
539
540 u8 sdpcm_ver; /* Bus protocol reported by dongle */
541
542 bool intr; /* Use interrupts */
543 bool poll; /* Use polling */
544 atomic_t ipend; /* Device interrupt is pending */
545 uint spurious; /* Count of spurious interrupts */
546 uint pollrate; /* Ticks between device polls */
547 uint polltick; /* Tick counter */
548
549 #ifdef DEBUG
550 uint console_interval;
551 struct brcmf_console console; /* Console output polling support */
552 uint console_addr; /* Console address from shared struct */
553 #endif /* DEBUG */
554
555 uint clkstate; /* State of sd and backplane clock(s) */
556 bool activity; /* Activity flag for clock down */
557 s32 idletime; /* Control for activity timeout */
558 s32 idlecount; /* Activity timeout counter */
559 s32 idleclock; /* How to set bus driver when idle */
560 s32 sd_rxchain;
561 bool use_rxchain; /* If brcmf should use PKT chains */
562 bool rxflow_mode; /* Rx flow control mode */
563 bool rxflow; /* Is rx flow control on */
564 bool alp_only; /* Don't use HT clock (ALP only) */
565
566 u8 *ctrl_frame_buf;
567 u32 ctrl_frame_len;
568 bool ctrl_frame_stat;
569
570 spinlock_t txqlock;
571 wait_queue_head_t ctrl_wait;
572 wait_queue_head_t dcmd_resp_wait;
573
574 struct timer_list timer;
575 struct completion watchdog_wait;
576 struct task_struct *watchdog_tsk;
577 bool wd_timer_valid;
578 uint save_ms;
579
580 struct workqueue_struct *brcmf_wq;
581 struct work_struct datawork;
582 struct list_head dpc_tsklst;
583 spinlock_t dpc_tl_lock;
584
585 struct semaphore sdsem;
586
587 const struct firmware *firmware;
588 u32 fw_ptr;
589
590 bool txoff; /* Transmit flow-controlled */
591 struct brcmf_sdio_count sdcnt;
592 };
593
594 /* clkstate */
595 #define CLK_NONE 0
596 #define CLK_SDONLY 1
597 #define CLK_PENDING 2 /* Not used yet */
598 #define CLK_AVAIL 3
599
600 #ifdef DEBUG
601 static int qcount[NUMPRIO];
602 static int tx_packets[NUMPRIO];
603 #endif /* DEBUG */
604
605 #define SDIO_DRIVE_STRENGTH 6 /* in milliamps */
606
607 #define RETRYCHAN(chan) ((chan) == SDPCM_EVENT_CHANNEL)
608
609 /* Retry count for register access failures */
610 static const uint retry_limit = 2;
611
612 /* Limit on rounding up frames */
613 static const uint max_roundup = 512;
614
615 #define ALIGNMENT 4
616
617 enum brcmf_sdio_frmtype {
618 BRCMF_SDIO_FT_NORMAL,
619 BRCMF_SDIO_FT_SUPER,
620 BRCMF_SDIO_FT_SUB,
621 };
622
623 static void pkt_align(struct sk_buff *p, int len, int align)
624 {
625 uint datalign;
626 datalign = (unsigned long)(p->data);
627 datalign = roundup(datalign, (align)) - datalign;
628 if (datalign)
629 skb_pull(p, datalign);
630 __skb_trim(p, len);
631 }
632
633 /* To check if there's window offered */
634 static bool data_ok(struct brcmf_sdio *bus)
635 {
636 return (u8)(bus->tx_max - bus->tx_seq) != 0 &&
637 ((u8)(bus->tx_max - bus->tx_seq) & 0x80) == 0;
638 }
639
640 /*
641 * Reads a register in the SDIO hardware block. This block occupies a series of
642 * adresses on the 32 bit backplane bus.
643 */
644 static int
645 r_sdreg32(struct brcmf_sdio *bus, u32 *regvar, u32 offset)
646 {
647 u8 idx = brcmf_sdio_chip_getinfidx(bus->ci, BCMA_CORE_SDIO_DEV);
648 int ret;
649
650 *regvar = brcmf_sdio_regrl(bus->sdiodev,
651 bus->ci->c_inf[idx].base + offset, &ret);
652
653 return ret;
654 }
655
656 static int
657 w_sdreg32(struct brcmf_sdio *bus, u32 regval, u32 reg_offset)
658 {
659 u8 idx = brcmf_sdio_chip_getinfidx(bus->ci, BCMA_CORE_SDIO_DEV);
660 int ret;
661
662 brcmf_sdio_regwl(bus->sdiodev,
663 bus->ci->c_inf[idx].base + reg_offset,
664 regval, &ret);
665
666 return ret;
667 }
668
669 #define PKT_AVAILABLE() (intstatus & I_HMB_FRAME_IND)
670
671 #define HOSTINTMASK (I_HMB_SW_MASK | I_CHIPACTIVE)
672
673 /* Turn backplane clock on or off */
674 static int brcmf_sdbrcm_htclk(struct brcmf_sdio *bus, bool on, bool pendok)
675 {
676 int err;
677 u8 clkctl, clkreq, devctl;
678 unsigned long timeout;
679
680 brcmf_dbg(TRACE, "Enter\n");
681
682 clkctl = 0;
683
684 if (on) {
685 /* Request HT Avail */
686 clkreq =
687 bus->alp_only ? SBSDIO_ALP_AVAIL_REQ : SBSDIO_HT_AVAIL_REQ;
688
689 brcmf_sdio_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
690 clkreq, &err);
691 if (err) {
692 brcmf_dbg(ERROR, "HT Avail request error: %d\n", err);
693 return -EBADE;
694 }
695
696 /* Check current status */
697 clkctl = brcmf_sdio_regrb(bus->sdiodev,
698 SBSDIO_FUNC1_CHIPCLKCSR, &err);
699 if (err) {
700 brcmf_dbg(ERROR, "HT Avail read error: %d\n", err);
701 return -EBADE;
702 }
703
704 /* Go to pending and await interrupt if appropriate */
705 if (!SBSDIO_CLKAV(clkctl, bus->alp_only) && pendok) {
706 /* Allow only clock-available interrupt */
707 devctl = brcmf_sdio_regrb(bus->sdiodev,
708 SBSDIO_DEVICE_CTL, &err);
709 if (err) {
710 brcmf_dbg(ERROR, "Devctl error setting CA: %d\n",
711 err);
712 return -EBADE;
713 }
714
715 devctl |= SBSDIO_DEVCTL_CA_INT_ONLY;
716 brcmf_sdio_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL,
717 devctl, &err);
718 brcmf_dbg(INFO, "CLKCTL: set PENDING\n");
719 bus->clkstate = CLK_PENDING;
720
721 return 0;
722 } else if (bus->clkstate == CLK_PENDING) {
723 /* Cancel CA-only interrupt filter */
724 devctl = brcmf_sdio_regrb(bus->sdiodev,
725 SBSDIO_DEVICE_CTL, &err);
726 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
727 brcmf_sdio_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL,
728 devctl, &err);
729 }
730
731 /* Otherwise, wait here (polling) for HT Avail */
732 timeout = jiffies +
733 msecs_to_jiffies(PMU_MAX_TRANSITION_DLY/1000);
734 while (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
735 clkctl = brcmf_sdio_regrb(bus->sdiodev,
736 SBSDIO_FUNC1_CHIPCLKCSR,
737 &err);
738 if (time_after(jiffies, timeout))
739 break;
740 else
741 usleep_range(5000, 10000);
742 }
743 if (err) {
744 brcmf_dbg(ERROR, "HT Avail request error: %d\n", err);
745 return -EBADE;
746 }
747 if (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
748 brcmf_dbg(ERROR, "HT Avail timeout (%d): clkctl 0x%02x\n",
749 PMU_MAX_TRANSITION_DLY, clkctl);
750 return -EBADE;
751 }
752
753 /* Mark clock available */
754 bus->clkstate = CLK_AVAIL;
755 brcmf_dbg(INFO, "CLKCTL: turned ON\n");
756
757 #if defined(DEBUG)
758 if (!bus->alp_only) {
759 if (SBSDIO_ALPONLY(clkctl))
760 brcmf_dbg(ERROR, "HT Clock should be on\n");
761 }
762 #endif /* defined (DEBUG) */
763
764 bus->activity = true;
765 } else {
766 clkreq = 0;
767
768 if (bus->clkstate == CLK_PENDING) {
769 /* Cancel CA-only interrupt filter */
770 devctl = brcmf_sdio_regrb(bus->sdiodev,
771 SBSDIO_DEVICE_CTL, &err);
772 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
773 brcmf_sdio_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL,
774 devctl, &err);
775 }
776
777 bus->clkstate = CLK_SDONLY;
778 brcmf_sdio_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
779 clkreq, &err);
780 brcmf_dbg(INFO, "CLKCTL: turned OFF\n");
781 if (err) {
782 brcmf_dbg(ERROR, "Failed access turning clock off: %d\n",
783 err);
784 return -EBADE;
785 }
786 }
787 return 0;
788 }
789
790 /* Change idle/active SD state */
791 static int brcmf_sdbrcm_sdclk(struct brcmf_sdio *bus, bool on)
792 {
793 brcmf_dbg(TRACE, "Enter\n");
794
795 if (on)
796 bus->clkstate = CLK_SDONLY;
797 else
798 bus->clkstate = CLK_NONE;
799
800 return 0;
801 }
802
803 /* Transition SD and backplane clock readiness */
804 static int brcmf_sdbrcm_clkctl(struct brcmf_sdio *bus, uint target, bool pendok)
805 {
806 #ifdef DEBUG
807 uint oldstate = bus->clkstate;
808 #endif /* DEBUG */
809
810 brcmf_dbg(TRACE, "Enter\n");
811
812 /* Early exit if we're already there */
813 if (bus->clkstate == target) {
814 if (target == CLK_AVAIL) {
815 brcmf_sdbrcm_wd_timer(bus, BRCMF_WD_POLL_MS);
816 bus->activity = true;
817 }
818 return 0;
819 }
820
821 switch (target) {
822 case CLK_AVAIL:
823 /* Make sure SD clock is available */
824 if (bus->clkstate == CLK_NONE)
825 brcmf_sdbrcm_sdclk(bus, true);
826 /* Now request HT Avail on the backplane */
827 brcmf_sdbrcm_htclk(bus, true, pendok);
828 brcmf_sdbrcm_wd_timer(bus, BRCMF_WD_POLL_MS);
829 bus->activity = true;
830 break;
831
832 case CLK_SDONLY:
833 /* Remove HT request, or bring up SD clock */
834 if (bus->clkstate == CLK_NONE)
835 brcmf_sdbrcm_sdclk(bus, true);
836 else if (bus->clkstate == CLK_AVAIL)
837 brcmf_sdbrcm_htclk(bus, false, false);
838 else
839 brcmf_dbg(ERROR, "request for %d -> %d\n",
840 bus->clkstate, target);
841 brcmf_sdbrcm_wd_timer(bus, BRCMF_WD_POLL_MS);
842 break;
843
844 case CLK_NONE:
845 /* Make sure to remove HT request */
846 if (bus->clkstate == CLK_AVAIL)
847 brcmf_sdbrcm_htclk(bus, false, false);
848 /* Now remove the SD clock */
849 brcmf_sdbrcm_sdclk(bus, false);
850 brcmf_sdbrcm_wd_timer(bus, 0);
851 break;
852 }
853 #ifdef DEBUG
854 brcmf_dbg(INFO, "%d -> %d\n", oldstate, bus->clkstate);
855 #endif /* DEBUG */
856
857 return 0;
858 }
859
860 static u32 brcmf_sdbrcm_hostmail(struct brcmf_sdio *bus)
861 {
862 u32 intstatus = 0;
863 u32 hmb_data;
864 u8 fcbits;
865 int ret;
866
867 brcmf_dbg(TRACE, "Enter\n");
868
869 /* Read mailbox data and ack that we did so */
870 ret = r_sdreg32(bus, &hmb_data,
871 offsetof(struct sdpcmd_regs, tohostmailboxdata));
872
873 if (ret == 0)
874 w_sdreg32(bus, SMB_INT_ACK,
875 offsetof(struct sdpcmd_regs, tosbmailbox));
876 bus->sdcnt.f1regdata += 2;
877
878 /* Dongle recomposed rx frames, accept them again */
879 if (hmb_data & HMB_DATA_NAKHANDLED) {
880 brcmf_dbg(INFO, "Dongle reports NAK handled, expect rtx of %d\n",
881 bus->rx_seq);
882 if (!bus->rxskip)
883 brcmf_dbg(ERROR, "unexpected NAKHANDLED!\n");
884
885 bus->rxskip = false;
886 intstatus |= I_HMB_FRAME_IND;
887 }
888
889 /*
890 * DEVREADY does not occur with gSPI.
891 */
892 if (hmb_data & (HMB_DATA_DEVREADY | HMB_DATA_FWREADY)) {
893 bus->sdpcm_ver =
894 (hmb_data & HMB_DATA_VERSION_MASK) >>
895 HMB_DATA_VERSION_SHIFT;
896 if (bus->sdpcm_ver != SDPCM_PROT_VERSION)
897 brcmf_dbg(ERROR, "Version mismatch, dongle reports %d, "
898 "expecting %d\n",
899 bus->sdpcm_ver, SDPCM_PROT_VERSION);
900 else
901 brcmf_dbg(INFO, "Dongle ready, protocol version %d\n",
902 bus->sdpcm_ver);
903 }
904
905 /*
906 * Flow Control has been moved into the RX headers and this out of band
907 * method isn't used any more.
908 * remaining backward compatible with older dongles.
909 */
910 if (hmb_data & HMB_DATA_FC) {
911 fcbits = (hmb_data & HMB_DATA_FCDATA_MASK) >>
912 HMB_DATA_FCDATA_SHIFT;
913
914 if (fcbits & ~bus->flowcontrol)
915 bus->sdcnt.fc_xoff++;
916
917 if (bus->flowcontrol & ~fcbits)
918 bus->sdcnt.fc_xon++;
919
920 bus->sdcnt.fc_rcvd++;
921 bus->flowcontrol = fcbits;
922 }
923
924 /* Shouldn't be any others */
925 if (hmb_data & ~(HMB_DATA_DEVREADY |
926 HMB_DATA_NAKHANDLED |
927 HMB_DATA_FC |
928 HMB_DATA_FWREADY |
929 HMB_DATA_FCDATA_MASK | HMB_DATA_VERSION_MASK))
930 brcmf_dbg(ERROR, "Unknown mailbox data content: 0x%02x\n",
931 hmb_data);
932
933 return intstatus;
934 }
935
936 static void brcmf_sdbrcm_rxfail(struct brcmf_sdio *bus, bool abort, bool rtx)
937 {
938 uint retries = 0;
939 u16 lastrbc;
940 u8 hi, lo;
941 int err;
942
943 brcmf_dbg(ERROR, "%sterminate frame%s\n",
944 abort ? "abort command, " : "",
945 rtx ? ", send NAK" : "");
946
947 if (abort)
948 brcmf_sdcard_abort(bus->sdiodev, SDIO_FUNC_2);
949
950 brcmf_sdio_regwb(bus->sdiodev, SBSDIO_FUNC1_FRAMECTRL,
951 SFC_RF_TERM, &err);
952 bus->sdcnt.f1regdata++;
953
954 /* Wait until the packet has been flushed (device/FIFO stable) */
955 for (lastrbc = retries = 0xffff; retries > 0; retries--) {
956 hi = brcmf_sdio_regrb(bus->sdiodev,
957 SBSDIO_FUNC1_RFRAMEBCHI, &err);
958 lo = brcmf_sdio_regrb(bus->sdiodev,
959 SBSDIO_FUNC1_RFRAMEBCLO, &err);
960 bus->sdcnt.f1regdata += 2;
961
962 if ((hi == 0) && (lo == 0))
963 break;
964
965 if ((hi > (lastrbc >> 8)) && (lo > (lastrbc & 0x00ff))) {
966 brcmf_dbg(ERROR, "count growing: last 0x%04x now 0x%04x\n",
967 lastrbc, (hi << 8) + lo);
968 }
969 lastrbc = (hi << 8) + lo;
970 }
971
972 if (!retries)
973 brcmf_dbg(ERROR, "count never zeroed: last 0x%04x\n", lastrbc);
974 else
975 brcmf_dbg(INFO, "flush took %d iterations\n", 0xffff - retries);
976
977 if (rtx) {
978 bus->sdcnt.rxrtx++;
979 err = w_sdreg32(bus, SMB_NAK,
980 offsetof(struct sdpcmd_regs, tosbmailbox));
981
982 bus->sdcnt.f1regdata++;
983 if (err == 0)
984 bus->rxskip = true;
985 }
986
987 /* Clear partial in any case */
988 bus->cur_read.len = 0;
989
990 /* If we can't reach the device, signal failure */
991 if (err)
992 bus->sdiodev->bus_if->state = BRCMF_BUS_DOWN;
993 }
994
995 /* copy a buffer into a pkt buffer chain */
996 static uint brcmf_sdbrcm_glom_from_buf(struct brcmf_sdio *bus, uint len)
997 {
998 uint n, ret = 0;
999 struct sk_buff *p;
1000 u8 *buf;
1001
1002 buf = bus->dataptr;
1003
1004 /* copy the data */
1005 skb_queue_walk(&bus->glom, p) {
1006 n = min_t(uint, p->len, len);
1007 memcpy(p->data, buf, n);
1008 buf += n;
1009 len -= n;
1010 ret += n;
1011 if (!len)
1012 break;
1013 }
1014
1015 return ret;
1016 }
1017
1018 /* return total length of buffer chain */
1019 static uint brcmf_sdbrcm_glom_len(struct brcmf_sdio *bus)
1020 {
1021 struct sk_buff *p;
1022 uint total;
1023
1024 total = 0;
1025 skb_queue_walk(&bus->glom, p)
1026 total += p->len;
1027 return total;
1028 }
1029
1030 static void brcmf_sdbrcm_free_glom(struct brcmf_sdio *bus)
1031 {
1032 struct sk_buff *cur, *next;
1033
1034 skb_queue_walk_safe(&bus->glom, cur, next) {
1035 skb_unlink(cur, &bus->glom);
1036 brcmu_pkt_buf_free_skb(cur);
1037 }
1038 }
1039
1040 static bool brcmf_sdio_hdparser(struct brcmf_sdio *bus, u8 *header,
1041 struct brcmf_sdio_read *rd,
1042 enum brcmf_sdio_frmtype type)
1043 {
1044 u16 len, checksum;
1045 u8 rx_seq, fc, tx_seq_max;
1046
1047 /*
1048 * 4 bytes hardware header (frame tag)
1049 * Byte 0~1: Frame length
1050 * Byte 2~3: Checksum, bit-wise inverse of frame length
1051 */
1052 len = get_unaligned_le16(header);
1053 checksum = get_unaligned_le16(header + sizeof(u16));
1054 /* All zero means no more to read */
1055 if (!(len | checksum)) {
1056 bus->rxpending = false;
1057 return false;
1058 }
1059 if ((u16)(~(len ^ checksum))) {
1060 brcmf_dbg(ERROR, "HW header checksum error\n");
1061 bus->sdcnt.rx_badhdr++;
1062 brcmf_sdbrcm_rxfail(bus, false, false);
1063 return false;
1064 }
1065 if (len < SDPCM_HDRLEN) {
1066 brcmf_dbg(ERROR, "HW header length error\n");
1067 return false;
1068 }
1069 if (type == BRCMF_SDIO_FT_SUPER &&
1070 (roundup(len, bus->blocksize) != rd->len)) {
1071 brcmf_dbg(ERROR, "HW superframe header length error\n");
1072 return false;
1073 }
1074 if (type == BRCMF_SDIO_FT_SUB && len > rd->len) {
1075 brcmf_dbg(ERROR, "HW subframe header length error\n");
1076 return false;
1077 }
1078 rd->len = len;
1079
1080 /*
1081 * 8 bytes hardware header
1082 * Byte 0: Rx sequence number
1083 * Byte 1: 4 MSB Channel number, 4 LSB arbitrary flag
1084 * Byte 2: Length of next data frame
1085 * Byte 3: Data offset
1086 * Byte 4: Flow control bits
1087 * Byte 5: Maximum Sequence number allow for Tx
1088 * Byte 6~7: Reserved
1089 */
1090 if (type == BRCMF_SDIO_FT_SUPER &&
1091 SDPCM_GLOMDESC(&header[SDPCM_FRAMETAG_LEN])) {
1092 brcmf_dbg(ERROR, "Glom descriptor found in superframe head\n");
1093 rd->len = 0;
1094 return false;
1095 }
1096 rx_seq = SDPCM_PACKET_SEQUENCE(&header[SDPCM_FRAMETAG_LEN]);
1097 rd->channel = SDPCM_PACKET_CHANNEL(&header[SDPCM_FRAMETAG_LEN]);
1098 if (len > MAX_RX_DATASZ && rd->channel != SDPCM_CONTROL_CHANNEL &&
1099 type != BRCMF_SDIO_FT_SUPER) {
1100 brcmf_dbg(ERROR, "HW header length too long\n");
1101 bus->sdiodev->bus_if->dstats.rx_errors++;
1102 bus->sdcnt.rx_toolong++;
1103 brcmf_sdbrcm_rxfail(bus, false, false);
1104 rd->len = 0;
1105 return false;
1106 }
1107 if (type == BRCMF_SDIO_FT_SUPER && rd->channel != SDPCM_GLOM_CHANNEL) {
1108 brcmf_dbg(ERROR, "Wrong channel for superframe\n");
1109 rd->len = 0;
1110 return false;
1111 }
1112 if (type == BRCMF_SDIO_FT_SUB && rd->channel != SDPCM_DATA_CHANNEL &&
1113 rd->channel != SDPCM_EVENT_CHANNEL) {
1114 brcmf_dbg(ERROR, "Wrong channel for subframe\n");
1115 rd->len = 0;
1116 return false;
1117 }
1118 rd->dat_offset = SDPCM_DOFFSET_VALUE(&header[SDPCM_FRAMETAG_LEN]);
1119 if (rd->dat_offset < SDPCM_HDRLEN || rd->dat_offset > rd->len) {
1120 brcmf_dbg(ERROR, "seq %d: bad data offset\n", rx_seq);
1121 bus->sdcnt.rx_badhdr++;
1122 brcmf_sdbrcm_rxfail(bus, false, false);
1123 rd->len = 0;
1124 return false;
1125 }
1126 if (rd->seq_num != rx_seq) {
1127 brcmf_dbg(ERROR, "seq %d: sequence number error, expect %d\n",
1128 rx_seq, rd->seq_num);
1129 bus->sdcnt.rx_badseq++;
1130 rd->seq_num = rx_seq;
1131 }
1132 /* no need to check the reset for subframe */
1133 if (type == BRCMF_SDIO_FT_SUB)
1134 return true;
1135 rd->len_nxtfrm = header[SDPCM_FRAMETAG_LEN + SDPCM_NEXTLEN_OFFSET];
1136 if (rd->len_nxtfrm << 4 > MAX_RX_DATASZ) {
1137 /* only warm for NON glom packet */
1138 if (rd->channel != SDPCM_GLOM_CHANNEL)
1139 brcmf_dbg(ERROR, "seq %d: next length error\n", rx_seq);
1140 rd->len_nxtfrm = 0;
1141 }
1142 fc = SDPCM_FCMASK_VALUE(&header[SDPCM_FRAMETAG_LEN]);
1143 if (bus->flowcontrol != fc) {
1144 if (~bus->flowcontrol & fc)
1145 bus->sdcnt.fc_xoff++;
1146 if (bus->flowcontrol & ~fc)
1147 bus->sdcnt.fc_xon++;
1148 bus->sdcnt.fc_rcvd++;
1149 bus->flowcontrol = fc;
1150 }
1151 tx_seq_max = SDPCM_WINDOW_VALUE(&header[SDPCM_FRAMETAG_LEN]);
1152 if ((u8)(tx_seq_max - bus->tx_seq) > 0x40) {
1153 brcmf_dbg(ERROR, "seq %d: max tx seq number error\n", rx_seq);
1154 tx_seq_max = bus->tx_seq + 2;
1155 }
1156 bus->tx_max = tx_seq_max;
1157
1158 return true;
1159 }
1160
1161 static u8 brcmf_sdbrcm_rxglom(struct brcmf_sdio *bus, u8 rxseq)
1162 {
1163 u16 dlen, totlen;
1164 u8 *dptr, num = 0;
1165
1166 u16 sublen;
1167 struct sk_buff *pfirst, *pnext;
1168
1169 int errcode;
1170 u8 doff, sfdoff;
1171
1172 int ifidx = 0;
1173 bool usechain = bus->use_rxchain;
1174
1175 struct brcmf_sdio_read rd_new;
1176
1177 /* If packets, issue read(s) and send up packet chain */
1178 /* Return sequence numbers consumed? */
1179
1180 brcmf_dbg(TRACE, "start: glomd %p glom %p\n",
1181 bus->glomd, skb_peek(&bus->glom));
1182
1183 /* If there's a descriptor, generate the packet chain */
1184 if (bus->glomd) {
1185 pfirst = pnext = NULL;
1186 dlen = (u16) (bus->glomd->len);
1187 dptr = bus->glomd->data;
1188 if (!dlen || (dlen & 1)) {
1189 brcmf_dbg(ERROR, "bad glomd len(%d), ignore descriptor\n",
1190 dlen);
1191 dlen = 0;
1192 }
1193
1194 for (totlen = num = 0; dlen; num++) {
1195 /* Get (and move past) next length */
1196 sublen = get_unaligned_le16(dptr);
1197 dlen -= sizeof(u16);
1198 dptr += sizeof(u16);
1199 if ((sublen < SDPCM_HDRLEN) ||
1200 ((num == 0) && (sublen < (2 * SDPCM_HDRLEN)))) {
1201 brcmf_dbg(ERROR, "descriptor len %d bad: %d\n",
1202 num, sublen);
1203 pnext = NULL;
1204 break;
1205 }
1206 if (sublen % BRCMF_SDALIGN) {
1207 brcmf_dbg(ERROR, "sublen %d not multiple of %d\n",
1208 sublen, BRCMF_SDALIGN);
1209 usechain = false;
1210 }
1211 totlen += sublen;
1212
1213 /* For last frame, adjust read len so total
1214 is a block multiple */
1215 if (!dlen) {
1216 sublen +=
1217 (roundup(totlen, bus->blocksize) - totlen);
1218 totlen = roundup(totlen, bus->blocksize);
1219 }
1220
1221 /* Allocate/chain packet for next subframe */
1222 pnext = brcmu_pkt_buf_get_skb(sublen + BRCMF_SDALIGN);
1223 if (pnext == NULL) {
1224 brcmf_dbg(ERROR, "bcm_pkt_buf_get_skb failed, num %d len %d\n",
1225 num, sublen);
1226 break;
1227 }
1228 skb_queue_tail(&bus->glom, pnext);
1229
1230 /* Adhere to start alignment requirements */
1231 pkt_align(pnext, sublen, BRCMF_SDALIGN);
1232 }
1233
1234 /* If all allocations succeeded, save packet chain
1235 in bus structure */
1236 if (pnext) {
1237 brcmf_dbg(GLOM, "allocated %d-byte packet chain for %d subframes\n",
1238 totlen, num);
1239 if (BRCMF_GLOM_ON() && bus->cur_read.len &&
1240 totlen != bus->cur_read.len) {
1241 brcmf_dbg(GLOM, "glomdesc mismatch: nextlen %d glomdesc %d rxseq %d\n",
1242 bus->cur_read.len, totlen, rxseq);
1243 }
1244 pfirst = pnext = NULL;
1245 } else {
1246 brcmf_sdbrcm_free_glom(bus);
1247 num = 0;
1248 }
1249
1250 /* Done with descriptor packet */
1251 brcmu_pkt_buf_free_skb(bus->glomd);
1252 bus->glomd = NULL;
1253 bus->cur_read.len = 0;
1254 }
1255
1256 /* Ok -- either we just generated a packet chain,
1257 or had one from before */
1258 if (!skb_queue_empty(&bus->glom)) {
1259 if (BRCMF_GLOM_ON()) {
1260 brcmf_dbg(GLOM, "try superframe read, packet chain:\n");
1261 skb_queue_walk(&bus->glom, pnext) {
1262 brcmf_dbg(GLOM, " %p: %p len 0x%04x (%d)\n",
1263 pnext, (u8 *) (pnext->data),
1264 pnext->len, pnext->len);
1265 }
1266 }
1267
1268 pfirst = skb_peek(&bus->glom);
1269 dlen = (u16) brcmf_sdbrcm_glom_len(bus);
1270
1271 /* Do an SDIO read for the superframe. Configurable iovar to
1272 * read directly into the chained packet, or allocate a large
1273 * packet and and copy into the chain.
1274 */
1275 if (usechain) {
1276 errcode = brcmf_sdcard_recv_chain(bus->sdiodev,
1277 bus->sdiodev->sbwad,
1278 SDIO_FUNC_2, F2SYNC, &bus->glom);
1279 } else if (bus->dataptr) {
1280 errcode = brcmf_sdcard_recv_buf(bus->sdiodev,
1281 bus->sdiodev->sbwad,
1282 SDIO_FUNC_2, F2SYNC,
1283 bus->dataptr, dlen);
1284 sublen = (u16) brcmf_sdbrcm_glom_from_buf(bus, dlen);
1285 if (sublen != dlen) {
1286 brcmf_dbg(ERROR, "FAILED TO COPY, dlen %d sublen %d\n",
1287 dlen, sublen);
1288 errcode = -1;
1289 }
1290 pnext = NULL;
1291 } else {
1292 brcmf_dbg(ERROR, "COULDN'T ALLOC %d-BYTE GLOM, FORCE FAILURE\n",
1293 dlen);
1294 errcode = -1;
1295 }
1296 bus->sdcnt.f2rxdata++;
1297
1298 /* On failure, kill the superframe, allow a couple retries */
1299 if (errcode < 0) {
1300 brcmf_dbg(ERROR, "glom read of %d bytes failed: %d\n",
1301 dlen, errcode);
1302 bus->sdiodev->bus_if->dstats.rx_errors++;
1303
1304 if (bus->glomerr++ < 3) {
1305 brcmf_sdbrcm_rxfail(bus, true, true);
1306 } else {
1307 bus->glomerr = 0;
1308 brcmf_sdbrcm_rxfail(bus, true, false);
1309 bus->sdcnt.rxglomfail++;
1310 brcmf_sdbrcm_free_glom(bus);
1311 }
1312 return 0;
1313 }
1314
1315 brcmf_dbg_hex_dump(BRCMF_GLOM_ON(),
1316 pfirst->data, min_t(int, pfirst->len, 48),
1317 "SUPERFRAME:\n");
1318
1319 rd_new.seq_num = rxseq;
1320 rd_new.len = dlen;
1321 errcode = -!brcmf_sdio_hdparser(bus, pfirst->data, &rd_new,
1322 BRCMF_SDIO_FT_SUPER);
1323 bus->cur_read.len = rd_new.len_nxtfrm << 4;
1324
1325 /* Remove superframe header, remember offset */
1326 skb_pull(pfirst, rd_new.dat_offset);
1327 sfdoff = rd_new.dat_offset;
1328 num = 0;
1329
1330 /* Validate all the subframe headers */
1331 skb_queue_walk(&bus->glom, pnext) {
1332 /* leave when invalid subframe is found */
1333 if (errcode)
1334 break;
1335
1336 rd_new.len = pnext->len;
1337 rd_new.seq_num = rxseq++;
1338 errcode = -!brcmf_sdio_hdparser(bus, pnext->data,
1339 &rd_new,
1340 BRCMF_SDIO_FT_SUB);
1341 brcmf_dbg_hex_dump(BRCMF_GLOM_ON(),
1342 pnext->data, 32, "subframe:\n");
1343
1344 num++;
1345 }
1346
1347 if (errcode) {
1348 /* Terminate frame on error, request
1349 a couple retries */
1350 if (bus->glomerr++ < 3) {
1351 /* Restore superframe header space */
1352 skb_push(pfirst, sfdoff);
1353 brcmf_sdbrcm_rxfail(bus, true, true);
1354 } else {
1355 bus->glomerr = 0;
1356 brcmf_sdbrcm_rxfail(bus, true, false);
1357 bus->sdcnt.rxglomfail++;
1358 brcmf_sdbrcm_free_glom(bus);
1359 }
1360 bus->cur_read.len = 0;
1361 return 0;
1362 }
1363
1364 /* Basic SD framing looks ok - process each packet (header) */
1365
1366 skb_queue_walk_safe(&bus->glom, pfirst, pnext) {
1367 dptr = (u8 *) (pfirst->data);
1368 sublen = get_unaligned_le16(dptr);
1369 doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
1370
1371 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_DATA_ON(),
1372 dptr, pfirst->len,
1373 "Rx Subframe Data:\n");
1374
1375 __skb_trim(pfirst, sublen);
1376 skb_pull(pfirst, doff);
1377
1378 if (pfirst->len == 0) {
1379 skb_unlink(pfirst, &bus->glom);
1380 brcmu_pkt_buf_free_skb(pfirst);
1381 continue;
1382 } else if (brcmf_proto_hdrpull(bus->sdiodev->dev,
1383 &ifidx, pfirst) != 0) {
1384 brcmf_dbg(ERROR, "rx protocol error\n");
1385 bus->sdiodev->bus_if->dstats.rx_errors++;
1386 skb_unlink(pfirst, &bus->glom);
1387 brcmu_pkt_buf_free_skb(pfirst);
1388 continue;
1389 }
1390
1391 brcmf_dbg_hex_dump(BRCMF_GLOM_ON(),
1392 pfirst->data,
1393 min_t(int, pfirst->len, 32),
1394 "subframe %d to stack, %p (%p/%d) nxt/lnk %p/%p\n",
1395 bus->glom.qlen, pfirst, pfirst->data,
1396 pfirst->len, pfirst->next,
1397 pfirst->prev);
1398 }
1399 /* sent any remaining packets up */
1400 if (bus->glom.qlen) {
1401 up(&bus->sdsem);
1402 brcmf_rx_frame(bus->sdiodev->dev, ifidx, &bus->glom);
1403 down(&bus->sdsem);
1404 }
1405
1406 bus->sdcnt.rxglomframes++;
1407 bus->sdcnt.rxglompkts += bus->glom.qlen;
1408 }
1409 return num;
1410 }
1411
1412 static int brcmf_sdbrcm_dcmd_resp_wait(struct brcmf_sdio *bus, uint *condition,
1413 bool *pending)
1414 {
1415 DECLARE_WAITQUEUE(wait, current);
1416 int timeout = msecs_to_jiffies(DCMD_RESP_TIMEOUT);
1417
1418 /* Wait until control frame is available */
1419 add_wait_queue(&bus->dcmd_resp_wait, &wait);
1420 set_current_state(TASK_INTERRUPTIBLE);
1421
1422 while (!(*condition) && (!signal_pending(current) && timeout))
1423 timeout = schedule_timeout(timeout);
1424
1425 if (signal_pending(current))
1426 *pending = true;
1427
1428 set_current_state(TASK_RUNNING);
1429 remove_wait_queue(&bus->dcmd_resp_wait, &wait);
1430
1431 return timeout;
1432 }
1433
1434 static int brcmf_sdbrcm_dcmd_resp_wake(struct brcmf_sdio *bus)
1435 {
1436 if (waitqueue_active(&bus->dcmd_resp_wait))
1437 wake_up_interruptible(&bus->dcmd_resp_wait);
1438
1439 return 0;
1440 }
1441 static void
1442 brcmf_sdbrcm_read_control(struct brcmf_sdio *bus, u8 *hdr, uint len, uint doff)
1443 {
1444 uint rdlen, pad;
1445
1446 int sdret;
1447
1448 brcmf_dbg(TRACE, "Enter\n");
1449
1450 /* Set rxctl for frame (w/optional alignment) */
1451 bus->rxctl = bus->rxbuf;
1452 bus->rxctl += BRCMF_FIRSTREAD;
1453 pad = ((unsigned long)bus->rxctl % BRCMF_SDALIGN);
1454 if (pad)
1455 bus->rxctl += (BRCMF_SDALIGN - pad);
1456 bus->rxctl -= BRCMF_FIRSTREAD;
1457
1458 /* Copy the already-read portion over */
1459 memcpy(bus->rxctl, hdr, BRCMF_FIRSTREAD);
1460 if (len <= BRCMF_FIRSTREAD)
1461 goto gotpkt;
1462
1463 /* Raise rdlen to next SDIO block to avoid tail command */
1464 rdlen = len - BRCMF_FIRSTREAD;
1465 if (bus->roundup && bus->blocksize && (rdlen > bus->blocksize)) {
1466 pad = bus->blocksize - (rdlen % bus->blocksize);
1467 if ((pad <= bus->roundup) && (pad < bus->blocksize) &&
1468 ((len + pad) < bus->sdiodev->bus_if->maxctl))
1469 rdlen += pad;
1470 } else if (rdlen % BRCMF_SDALIGN) {
1471 rdlen += BRCMF_SDALIGN - (rdlen % BRCMF_SDALIGN);
1472 }
1473
1474 /* Satisfy length-alignment requirements */
1475 if (rdlen & (ALIGNMENT - 1))
1476 rdlen = roundup(rdlen, ALIGNMENT);
1477
1478 /* Drop if the read is too big or it exceeds our maximum */
1479 if ((rdlen + BRCMF_FIRSTREAD) > bus->sdiodev->bus_if->maxctl) {
1480 brcmf_dbg(ERROR, "%d-byte control read exceeds %d-byte buffer\n",
1481 rdlen, bus->sdiodev->bus_if->maxctl);
1482 bus->sdiodev->bus_if->dstats.rx_errors++;
1483 brcmf_sdbrcm_rxfail(bus, false, false);
1484 goto done;
1485 }
1486
1487 if ((len - doff) > bus->sdiodev->bus_if->maxctl) {
1488 brcmf_dbg(ERROR, "%d-byte ctl frame (%d-byte ctl data) exceeds %d-byte limit\n",
1489 len, len - doff, bus->sdiodev->bus_if->maxctl);
1490 bus->sdiodev->bus_if->dstats.rx_errors++;
1491 bus->sdcnt.rx_toolong++;
1492 brcmf_sdbrcm_rxfail(bus, false, false);
1493 goto done;
1494 }
1495
1496 /* Read remainder of frame body into the rxctl buffer */
1497 sdret = brcmf_sdcard_recv_buf(bus->sdiodev,
1498 bus->sdiodev->sbwad,
1499 SDIO_FUNC_2,
1500 F2SYNC, (bus->rxctl + BRCMF_FIRSTREAD), rdlen);
1501 bus->sdcnt.f2rxdata++;
1502
1503 /* Control frame failures need retransmission */
1504 if (sdret < 0) {
1505 brcmf_dbg(ERROR, "read %d control bytes failed: %d\n",
1506 rdlen, sdret);
1507 bus->sdcnt.rxc_errors++;
1508 brcmf_sdbrcm_rxfail(bus, true, true);
1509 goto done;
1510 }
1511
1512 gotpkt:
1513
1514 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_CTL_ON(),
1515 bus->rxctl, len, "RxCtrl:\n");
1516
1517 /* Point to valid data and indicate its length */
1518 bus->rxctl += doff;
1519 bus->rxlen = len - doff;
1520
1521 done:
1522 /* Awake any waiters */
1523 brcmf_sdbrcm_dcmd_resp_wake(bus);
1524 }
1525
1526 /* Pad read to blocksize for efficiency */
1527 static void brcmf_pad(struct brcmf_sdio *bus, u16 *pad, u16 *rdlen)
1528 {
1529 if (bus->roundup && bus->blocksize && *rdlen > bus->blocksize) {
1530 *pad = bus->blocksize - (*rdlen % bus->blocksize);
1531 if (*pad <= bus->roundup && *pad < bus->blocksize &&
1532 *rdlen + *pad + BRCMF_FIRSTREAD < MAX_RX_DATASZ)
1533 *rdlen += *pad;
1534 } else if (*rdlen % BRCMF_SDALIGN) {
1535 *rdlen += BRCMF_SDALIGN - (*rdlen % BRCMF_SDALIGN);
1536 }
1537 }
1538
1539 static uint brcmf_sdio_readframes(struct brcmf_sdio *bus, uint maxframes)
1540 {
1541 struct sk_buff *pkt; /* Packet for event or data frames */
1542 u16 pad; /* Number of pad bytes to read */
1543 uint rxleft = 0; /* Remaining number of frames allowed */
1544 int sdret; /* Return code from calls */
1545 int ifidx = 0;
1546 uint rxcount = 0; /* Total frames read */
1547 struct brcmf_sdio_read *rd = &bus->cur_read, rd_new;
1548 u8 head_read = 0;
1549
1550 brcmf_dbg(TRACE, "Enter\n");
1551
1552 /* Not finished unless we encounter no more frames indication */
1553 bus->rxpending = true;
1554
1555 for (rd->seq_num = bus->rx_seq, rxleft = maxframes;
1556 !bus->rxskip && rxleft &&
1557 bus->sdiodev->bus_if->state != BRCMF_BUS_DOWN;
1558 rd->seq_num++, rxleft--) {
1559
1560 /* Handle glomming separately */
1561 if (bus->glomd || !skb_queue_empty(&bus->glom)) {
1562 u8 cnt;
1563 brcmf_dbg(GLOM, "calling rxglom: glomd %p, glom %p\n",
1564 bus->glomd, skb_peek(&bus->glom));
1565 cnt = brcmf_sdbrcm_rxglom(bus, rd->seq_num);
1566 brcmf_dbg(GLOM, "rxglom returned %d\n", cnt);
1567 rd->seq_num += cnt - 1;
1568 rxleft = (rxleft > cnt) ? (rxleft - cnt) : 1;
1569 continue;
1570 }
1571
1572 rd->len_left = rd->len;
1573 /* read header first for unknow frame length */
1574 if (!rd->len) {
1575 sdret = brcmf_sdcard_recv_buf(bus->sdiodev,
1576 bus->sdiodev->sbwad,
1577 SDIO_FUNC_2, F2SYNC,
1578 bus->rxhdr,
1579 BRCMF_FIRSTREAD);
1580 bus->sdcnt.f2rxhdrs++;
1581 if (sdret < 0) {
1582 brcmf_dbg(ERROR, "RXHEADER FAILED: %d\n",
1583 sdret);
1584 bus->sdcnt.rx_hdrfail++;
1585 brcmf_sdbrcm_rxfail(bus, true, true);
1586 continue;
1587 }
1588
1589 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() || BRCMF_HDRS_ON(),
1590 bus->rxhdr, SDPCM_HDRLEN,
1591 "RxHdr:\n");
1592
1593 if (!brcmf_sdio_hdparser(bus, bus->rxhdr, rd,
1594 BRCMF_SDIO_FT_NORMAL)) {
1595 if (!bus->rxpending)
1596 break;
1597 else
1598 continue;
1599 }
1600
1601 if (rd->channel == SDPCM_CONTROL_CHANNEL) {
1602 brcmf_sdbrcm_read_control(bus, bus->rxhdr,
1603 rd->len,
1604 rd->dat_offset);
1605 /* prepare the descriptor for the next read */
1606 rd->len = rd->len_nxtfrm << 4;
1607 rd->len_nxtfrm = 0;
1608 /* treat all packet as event if we don't know */
1609 rd->channel = SDPCM_EVENT_CHANNEL;
1610 continue;
1611 }
1612 rd->len_left = rd->len > BRCMF_FIRSTREAD ?
1613 rd->len - BRCMF_FIRSTREAD : 0;
1614 head_read = BRCMF_FIRSTREAD;
1615 }
1616
1617 brcmf_pad(bus, &pad, &rd->len_left);
1618
1619 pkt = brcmu_pkt_buf_get_skb(rd->len_left + head_read +
1620 BRCMF_SDALIGN);
1621 if (!pkt) {
1622 /* Give up on data, request rtx of events */
1623 brcmf_dbg(ERROR, "brcmu_pkt_buf_get_skb failed\n");
1624 bus->sdiodev->bus_if->dstats.rx_dropped++;
1625 brcmf_sdbrcm_rxfail(bus, false,
1626 RETRYCHAN(rd->channel));
1627 continue;
1628 }
1629 skb_pull(pkt, head_read);
1630 pkt_align(pkt, rd->len_left, BRCMF_SDALIGN);
1631
1632 sdret = brcmf_sdcard_recv_pkt(bus->sdiodev, bus->sdiodev->sbwad,
1633 SDIO_FUNC_2, F2SYNC, pkt);
1634 bus->sdcnt.f2rxdata++;
1635
1636 if (sdret < 0) {
1637 brcmf_dbg(ERROR, "read %d bytes from channel %d failed: %d\n",
1638 rd->len, rd->channel, sdret);
1639 brcmu_pkt_buf_free_skb(pkt);
1640 bus->sdiodev->bus_if->dstats.rx_errors++;
1641 brcmf_sdbrcm_rxfail(bus, true,
1642 RETRYCHAN(rd->channel));
1643 continue;
1644 }
1645
1646 if (head_read) {
1647 skb_push(pkt, head_read);
1648 memcpy(pkt->data, bus->rxhdr, head_read);
1649 head_read = 0;
1650 } else {
1651 memcpy(bus->rxhdr, pkt->data, SDPCM_HDRLEN);
1652 rd_new.seq_num = rd->seq_num;
1653 if (!brcmf_sdio_hdparser(bus, bus->rxhdr, &rd_new,
1654 BRCMF_SDIO_FT_NORMAL)) {
1655 rd->len = 0;
1656 brcmu_pkt_buf_free_skb(pkt);
1657 }
1658 bus->sdcnt.rx_readahead_cnt++;
1659 if (rd->len != roundup(rd_new.len, 16)) {
1660 brcmf_dbg(ERROR, "frame length mismatch:read %d, should be %d\n",
1661 rd->len,
1662 roundup(rd_new.len, 16) >> 4);
1663 rd->len = 0;
1664 brcmf_sdbrcm_rxfail(bus, true, true);
1665 brcmu_pkt_buf_free_skb(pkt);
1666 continue;
1667 }
1668 rd->len_nxtfrm = rd_new.len_nxtfrm;
1669 rd->channel = rd_new.channel;
1670 rd->dat_offset = rd_new.dat_offset;
1671
1672 brcmf_dbg_hex_dump(!(BRCMF_BYTES_ON() &&
1673 BRCMF_DATA_ON()) &&
1674 BRCMF_HDRS_ON(),
1675 bus->rxhdr, SDPCM_HDRLEN,
1676 "RxHdr:\n");
1677
1678 if (rd_new.channel == SDPCM_CONTROL_CHANNEL) {
1679 brcmf_dbg(ERROR, "readahead on control packet %d?\n",
1680 rd_new.seq_num);
1681 /* Force retry w/normal header read */
1682 rd->len = 0;
1683 brcmf_sdbrcm_rxfail(bus, false, true);
1684 brcmu_pkt_buf_free_skb(pkt);
1685 continue;
1686 }
1687 }
1688
1689 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_DATA_ON(),
1690 pkt->data, rd->len, "Rx Data:\n");
1691
1692 /* Save superframe descriptor and allocate packet frame */
1693 if (rd->channel == SDPCM_GLOM_CHANNEL) {
1694 if (SDPCM_GLOMDESC(&bus->rxhdr[SDPCM_FRAMETAG_LEN])) {
1695 brcmf_dbg(GLOM, "glom descriptor, %d bytes:\n",
1696 rd->len);
1697 brcmf_dbg_hex_dump(BRCMF_GLOM_ON(),
1698 pkt->data, rd->len,
1699 "Glom Data:\n");
1700 __skb_trim(pkt, rd->len);
1701 skb_pull(pkt, SDPCM_HDRLEN);
1702 bus->glomd = pkt;
1703 } else {
1704 brcmf_dbg(ERROR, "%s: glom superframe w/o "
1705 "descriptor!\n", __func__);
1706 brcmf_sdbrcm_rxfail(bus, false, false);
1707 }
1708 /* prepare the descriptor for the next read */
1709 rd->len = rd->len_nxtfrm << 4;
1710 rd->len_nxtfrm = 0;
1711 /* treat all packet as event if we don't know */
1712 rd->channel = SDPCM_EVENT_CHANNEL;
1713 continue;
1714 }
1715
1716 /* Fill in packet len and prio, deliver upward */
1717 __skb_trim(pkt, rd->len);
1718 skb_pull(pkt, rd->dat_offset);
1719
1720 /* prepare the descriptor for the next read */
1721 rd->len = rd->len_nxtfrm << 4;
1722 rd->len_nxtfrm = 0;
1723 /* treat all packet as event if we don't know */
1724 rd->channel = SDPCM_EVENT_CHANNEL;
1725
1726 if (pkt->len == 0) {
1727 brcmu_pkt_buf_free_skb(pkt);
1728 continue;
1729 } else if (brcmf_proto_hdrpull(bus->sdiodev->dev, &ifidx,
1730 pkt) != 0) {
1731 brcmf_dbg(ERROR, "rx protocol error\n");
1732 brcmu_pkt_buf_free_skb(pkt);
1733 bus->sdiodev->bus_if->dstats.rx_errors++;
1734 continue;
1735 }
1736
1737 /* Unlock during rx call */
1738 up(&bus->sdsem);
1739 brcmf_rx_packet(bus->sdiodev->dev, ifidx, pkt);
1740 down(&bus->sdsem);
1741 }
1742
1743 rxcount = maxframes - rxleft;
1744 /* Message if we hit the limit */
1745 if (!rxleft)
1746 brcmf_dbg(DATA, "hit rx limit of %d frames\n", maxframes);
1747 else
1748 brcmf_dbg(DATA, "processed %d frames\n", rxcount);
1749 /* Back off rxseq if awaiting rtx, update rx_seq */
1750 if (bus->rxskip)
1751 rd->seq_num--;
1752 bus->rx_seq = rd->seq_num;
1753
1754 return rxcount;
1755 }
1756
1757 static void
1758 brcmf_sdbrcm_wait_for_event(struct brcmf_sdio *bus, bool *lockvar)
1759 {
1760 up(&bus->sdsem);
1761 wait_event_interruptible_timeout(bus->ctrl_wait, !*lockvar, HZ * 2);
1762 down(&bus->sdsem);
1763 return;
1764 }
1765
1766 static void
1767 brcmf_sdbrcm_wait_event_wakeup(struct brcmf_sdio *bus)
1768 {
1769 if (waitqueue_active(&bus->ctrl_wait))
1770 wake_up_interruptible(&bus->ctrl_wait);
1771 return;
1772 }
1773
1774 /* Writes a HW/SW header into the packet and sends it. */
1775 /* Assumes: (a) header space already there, (b) caller holds lock */
1776 static int brcmf_sdbrcm_txpkt(struct brcmf_sdio *bus, struct sk_buff *pkt,
1777 uint chan, bool free_pkt)
1778 {
1779 int ret;
1780 u8 *frame;
1781 u16 len, pad = 0;
1782 u32 swheader;
1783 struct sk_buff *new;
1784 int i;
1785
1786 brcmf_dbg(TRACE, "Enter\n");
1787
1788 frame = (u8 *) (pkt->data);
1789
1790 /* Add alignment padding, allocate new packet if needed */
1791 pad = ((unsigned long)frame % BRCMF_SDALIGN);
1792 if (pad) {
1793 if (skb_headroom(pkt) < pad) {
1794 brcmf_dbg(INFO, "insufficient headroom %d for %d pad\n",
1795 skb_headroom(pkt), pad);
1796 bus->sdiodev->bus_if->tx_realloc++;
1797 new = brcmu_pkt_buf_get_skb(pkt->len + BRCMF_SDALIGN);
1798 if (!new) {
1799 brcmf_dbg(ERROR, "couldn't allocate new %d-byte packet\n",
1800 pkt->len + BRCMF_SDALIGN);
1801 ret = -ENOMEM;
1802 goto done;
1803 }
1804
1805 pkt_align(new, pkt->len, BRCMF_SDALIGN);
1806 memcpy(new->data, pkt->data, pkt->len);
1807 if (free_pkt)
1808 brcmu_pkt_buf_free_skb(pkt);
1809 /* free the pkt if canned one is not used */
1810 free_pkt = true;
1811 pkt = new;
1812 frame = (u8 *) (pkt->data);
1813 /* precondition: (frame % BRCMF_SDALIGN) == 0) */
1814 pad = 0;
1815 } else {
1816 skb_push(pkt, pad);
1817 frame = (u8 *) (pkt->data);
1818 /* precondition: pad + SDPCM_HDRLEN <= pkt->len */
1819 memset(frame, 0, pad + SDPCM_HDRLEN);
1820 }
1821 }
1822 /* precondition: pad < BRCMF_SDALIGN */
1823
1824 /* Hardware tag: 2 byte len followed by 2 byte ~len check (all LE) */
1825 len = (u16) (pkt->len);
1826 *(__le16 *) frame = cpu_to_le16(len);
1827 *(((__le16 *) frame) + 1) = cpu_to_le16(~len);
1828
1829 /* Software tag: channel, sequence number, data offset */
1830 swheader =
1831 ((chan << SDPCM_CHANNEL_SHIFT) & SDPCM_CHANNEL_MASK) | bus->tx_seq |
1832 (((pad +
1833 SDPCM_HDRLEN) << SDPCM_DOFFSET_SHIFT) & SDPCM_DOFFSET_MASK);
1834
1835 put_unaligned_le32(swheader, frame + SDPCM_FRAMETAG_LEN);
1836 put_unaligned_le32(0, frame + SDPCM_FRAMETAG_LEN + sizeof(swheader));
1837
1838 #ifdef DEBUG
1839 tx_packets[pkt->priority]++;
1840 #endif
1841
1842 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() &&
1843 ((BRCMF_CTL_ON() && chan == SDPCM_CONTROL_CHANNEL) ||
1844 (BRCMF_DATA_ON() && chan != SDPCM_CONTROL_CHANNEL)),
1845 frame, len, "Tx Frame:\n");
1846 brcmf_dbg_hex_dump(!(BRCMF_BYTES_ON() &&
1847 ((BRCMF_CTL_ON() &&
1848 chan == SDPCM_CONTROL_CHANNEL) ||
1849 (BRCMF_DATA_ON() &&
1850 chan != SDPCM_CONTROL_CHANNEL))) &&
1851 BRCMF_HDRS_ON(),
1852 frame, min_t(u16, len, 16), "TxHdr:\n");
1853
1854 /* Raise len to next SDIO block to eliminate tail command */
1855 if (bus->roundup && bus->blocksize && (len > bus->blocksize)) {
1856 u16 pad = bus->blocksize - (len % bus->blocksize);
1857 if ((pad <= bus->roundup) && (pad < bus->blocksize))
1858 len += pad;
1859 } else if (len % BRCMF_SDALIGN) {
1860 len += BRCMF_SDALIGN - (len % BRCMF_SDALIGN);
1861 }
1862
1863 /* Some controllers have trouble with odd bytes -- round to even */
1864 if (len & (ALIGNMENT - 1))
1865 len = roundup(len, ALIGNMENT);
1866
1867 ret = brcmf_sdcard_send_pkt(bus->sdiodev, bus->sdiodev->sbwad,
1868 SDIO_FUNC_2, F2SYNC, pkt);
1869 bus->sdcnt.f2txdata++;
1870
1871 if (ret < 0) {
1872 /* On failure, abort the command and terminate the frame */
1873 brcmf_dbg(INFO, "sdio error %d, abort command and terminate frame\n",
1874 ret);
1875 bus->sdcnt.tx_sderrs++;
1876
1877 brcmf_sdcard_abort(bus->sdiodev, SDIO_FUNC_2);
1878 brcmf_sdio_regwb(bus->sdiodev, SBSDIO_FUNC1_FRAMECTRL,
1879 SFC_WF_TERM, NULL);
1880 bus->sdcnt.f1regdata++;
1881
1882 for (i = 0; i < 3; i++) {
1883 u8 hi, lo;
1884 hi = brcmf_sdio_regrb(bus->sdiodev,
1885 SBSDIO_FUNC1_WFRAMEBCHI, NULL);
1886 lo = brcmf_sdio_regrb(bus->sdiodev,
1887 SBSDIO_FUNC1_WFRAMEBCLO, NULL);
1888 bus->sdcnt.f1regdata += 2;
1889 if ((hi == 0) && (lo == 0))
1890 break;
1891 }
1892
1893 }
1894 if (ret == 0)
1895 bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
1896
1897 done:
1898 /* restore pkt buffer pointer before calling tx complete routine */
1899 skb_pull(pkt, SDPCM_HDRLEN + pad);
1900 up(&bus->sdsem);
1901 brcmf_txcomplete(bus->sdiodev->dev, pkt, ret != 0);
1902 down(&bus->sdsem);
1903
1904 if (free_pkt)
1905 brcmu_pkt_buf_free_skb(pkt);
1906
1907 return ret;
1908 }
1909
1910 static uint brcmf_sdbrcm_sendfromq(struct brcmf_sdio *bus, uint maxframes)
1911 {
1912 struct sk_buff *pkt;
1913 u32 intstatus = 0;
1914 int ret = 0, prec_out;
1915 uint cnt = 0;
1916 uint datalen;
1917 u8 tx_prec_map;
1918
1919 brcmf_dbg(TRACE, "Enter\n");
1920
1921 tx_prec_map = ~bus->flowcontrol;
1922
1923 /* Send frames until the limit or some other event */
1924 for (cnt = 0; (cnt < maxframes) && data_ok(bus); cnt++) {
1925 spin_lock_bh(&bus->txqlock);
1926 pkt = brcmu_pktq_mdeq(&bus->txq, tx_prec_map, &prec_out);
1927 if (pkt == NULL) {
1928 spin_unlock_bh(&bus->txqlock);
1929 break;
1930 }
1931 spin_unlock_bh(&bus->txqlock);
1932 datalen = pkt->len - SDPCM_HDRLEN;
1933
1934 ret = brcmf_sdbrcm_txpkt(bus, pkt, SDPCM_DATA_CHANNEL, true);
1935 if (ret)
1936 bus->sdiodev->bus_if->dstats.tx_errors++;
1937 else
1938 bus->sdiodev->bus_if->dstats.tx_bytes += datalen;
1939
1940 /* In poll mode, need to check for other events */
1941 if (!bus->intr && cnt) {
1942 /* Check device status, signal pending interrupt */
1943 ret = r_sdreg32(bus, &intstatus,
1944 offsetof(struct sdpcmd_regs,
1945 intstatus));
1946 bus->sdcnt.f2txdata++;
1947 if (ret != 0)
1948 break;
1949 if (intstatus & bus->hostintmask)
1950 atomic_set(&bus->ipend, 1);
1951 }
1952 }
1953
1954 /* Deflow-control stack if needed */
1955 if (bus->sdiodev->bus_if->drvr_up &&
1956 (bus->sdiodev->bus_if->state == BRCMF_BUS_DATA) &&
1957 bus->txoff && (pktq_len(&bus->txq) < TXLOW)) {
1958 bus->txoff = false;
1959 brcmf_txflowblock(bus->sdiodev->dev, false);
1960 }
1961
1962 return cnt;
1963 }
1964
1965 static void brcmf_sdbrcm_bus_stop(struct device *dev)
1966 {
1967 u32 local_hostintmask;
1968 u8 saveclk;
1969 int err;
1970 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
1971 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
1972 struct brcmf_sdio *bus = sdiodev->bus;
1973
1974 brcmf_dbg(TRACE, "Enter\n");
1975
1976 if (bus->watchdog_tsk) {
1977 send_sig(SIGTERM, bus->watchdog_tsk, 1);
1978 kthread_stop(bus->watchdog_tsk);
1979 bus->watchdog_tsk = NULL;
1980 }
1981
1982 down(&bus->sdsem);
1983
1984 /* Enable clock for device interrupts */
1985 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
1986
1987 /* Disable and clear interrupts at the chip level also */
1988 w_sdreg32(bus, 0, offsetof(struct sdpcmd_regs, hostintmask));
1989 local_hostintmask = bus->hostintmask;
1990 bus->hostintmask = 0;
1991
1992 /* Change our idea of bus state */
1993 bus->sdiodev->bus_if->state = BRCMF_BUS_DOWN;
1994
1995 /* Force clocks on backplane to be sure F2 interrupt propagates */
1996 saveclk = brcmf_sdio_regrb(bus->sdiodev,
1997 SBSDIO_FUNC1_CHIPCLKCSR, &err);
1998 if (!err) {
1999 brcmf_sdio_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
2000 (saveclk | SBSDIO_FORCE_HT), &err);
2001 }
2002 if (err)
2003 brcmf_dbg(ERROR, "Failed to force clock for F2: err %d\n", err);
2004
2005 /* Turn off the bus (F2), free any pending packets */
2006 brcmf_dbg(INTR, "disable SDIO interrupts\n");
2007 brcmf_sdio_regwb(bus->sdiodev, SDIO_CCCR_IOEx, SDIO_FUNC_ENABLE_1,
2008 NULL);
2009
2010 /* Clear any pending interrupts now that F2 is disabled */
2011 w_sdreg32(bus, local_hostintmask,
2012 offsetof(struct sdpcmd_regs, intstatus));
2013
2014 /* Turn off the backplane clock (only) */
2015 brcmf_sdbrcm_clkctl(bus, CLK_SDONLY, false);
2016
2017 /* Clear the data packet queues */
2018 brcmu_pktq_flush(&bus->txq, true, NULL, NULL);
2019
2020 /* Clear any held glomming stuff */
2021 if (bus->glomd)
2022 brcmu_pkt_buf_free_skb(bus->glomd);
2023 brcmf_sdbrcm_free_glom(bus);
2024
2025 /* Clear rx control and wake any waiters */
2026 bus->rxlen = 0;
2027 brcmf_sdbrcm_dcmd_resp_wake(bus);
2028
2029 /* Reset some F2 state stuff */
2030 bus->rxskip = false;
2031 bus->tx_seq = bus->rx_seq = 0;
2032
2033 up(&bus->sdsem);
2034 }
2035
2036 #ifdef CONFIG_BRCMFMAC_SDIO_OOB
2037 static inline void brcmf_sdbrcm_clrintr(struct brcmf_sdio *bus)
2038 {
2039 unsigned long flags;
2040
2041 spin_lock_irqsave(&bus->sdiodev->irq_en_lock, flags);
2042 if (!bus->sdiodev->irq_en && !atomic_read(&bus->ipend)) {
2043 enable_irq(bus->sdiodev->irq);
2044 bus->sdiodev->irq_en = true;
2045 }
2046 spin_unlock_irqrestore(&bus->sdiodev->irq_en_lock, flags);
2047 }
2048 #else
2049 static inline void brcmf_sdbrcm_clrintr(struct brcmf_sdio *bus)
2050 {
2051 }
2052 #endif /* CONFIG_BRCMFMAC_SDIO_OOB */
2053
2054 static inline void brcmf_sdbrcm_adddpctsk(struct brcmf_sdio *bus)
2055 {
2056 struct list_head *new_hd;
2057 unsigned long flags;
2058
2059 if (in_interrupt())
2060 new_hd = kzalloc(sizeof(struct list_head), GFP_ATOMIC);
2061 else
2062 new_hd = kzalloc(sizeof(struct list_head), GFP_KERNEL);
2063 if (new_hd == NULL)
2064 return;
2065
2066 spin_lock_irqsave(&bus->dpc_tl_lock, flags);
2067 list_add_tail(new_hd, &bus->dpc_tsklst);
2068 spin_unlock_irqrestore(&bus->dpc_tl_lock, flags);
2069 }
2070
2071 static int brcmf_sdio_intr_rstatus(struct brcmf_sdio *bus)
2072 {
2073 u8 idx;
2074 u32 addr;
2075 unsigned long val;
2076 int n, ret;
2077
2078 idx = brcmf_sdio_chip_getinfidx(bus->ci, BCMA_CORE_SDIO_DEV);
2079 addr = bus->ci->c_inf[idx].base +
2080 offsetof(struct sdpcmd_regs, intstatus);
2081
2082 ret = brcmf_sdio_regrw_helper(bus->sdiodev, addr, &val, false);
2083 bus->sdcnt.f1regdata++;
2084 if (ret != 0)
2085 val = 0;
2086
2087 val &= bus->hostintmask;
2088 atomic_set(&bus->fcstate, !!(val & I_HMB_FC_STATE));
2089
2090 /* Clear interrupts */
2091 if (val) {
2092 ret = brcmf_sdio_regrw_helper(bus->sdiodev, addr, &val, true);
2093 bus->sdcnt.f1regdata++;
2094 }
2095
2096 if (ret) {
2097 atomic_set(&bus->intstatus, 0);
2098 } else if (val) {
2099 for_each_set_bit(n, &val, 32)
2100 set_bit(n, (unsigned long *)&bus->intstatus.counter);
2101 }
2102
2103 return ret;
2104 }
2105
2106 static void brcmf_sdbrcm_dpc(struct brcmf_sdio *bus)
2107 {
2108 u32 newstatus = 0;
2109 unsigned long intstatus;
2110 uint rxlimit = bus->rxbound; /* Rx frames to read before resched */
2111 uint txlimit = bus->txbound; /* Tx frames to send before resched */
2112 uint framecnt = 0; /* Temporary counter of tx/rx frames */
2113 int err = 0, n;
2114
2115 brcmf_dbg(TRACE, "Enter\n");
2116
2117 down(&bus->sdsem);
2118
2119 /* If waiting for HTAVAIL, check status */
2120 if (bus->clkstate == CLK_PENDING) {
2121 u8 clkctl, devctl = 0;
2122
2123 #ifdef DEBUG
2124 /* Check for inconsistent device control */
2125 devctl = brcmf_sdio_regrb(bus->sdiodev,
2126 SBSDIO_DEVICE_CTL, &err);
2127 if (err) {
2128 brcmf_dbg(ERROR, "error reading DEVCTL: %d\n", err);
2129 bus->sdiodev->bus_if->state = BRCMF_BUS_DOWN;
2130 }
2131 #endif /* DEBUG */
2132
2133 /* Read CSR, if clock on switch to AVAIL, else ignore */
2134 clkctl = brcmf_sdio_regrb(bus->sdiodev,
2135 SBSDIO_FUNC1_CHIPCLKCSR, &err);
2136 if (err) {
2137 brcmf_dbg(ERROR, "error reading CSR: %d\n",
2138 err);
2139 bus->sdiodev->bus_if->state = BRCMF_BUS_DOWN;
2140 }
2141
2142 brcmf_dbg(INFO, "DPC: PENDING, devctl 0x%02x clkctl 0x%02x\n",
2143 devctl, clkctl);
2144
2145 if (SBSDIO_HTAV(clkctl)) {
2146 devctl = brcmf_sdio_regrb(bus->sdiodev,
2147 SBSDIO_DEVICE_CTL, &err);
2148 if (err) {
2149 brcmf_dbg(ERROR, "error reading DEVCTL: %d\n",
2150 err);
2151 bus->sdiodev->bus_if->state = BRCMF_BUS_DOWN;
2152 }
2153 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
2154 brcmf_sdio_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL,
2155 devctl, &err);
2156 if (err) {
2157 brcmf_dbg(ERROR, "error writing DEVCTL: %d\n",
2158 err);
2159 bus->sdiodev->bus_if->state = BRCMF_BUS_DOWN;
2160 }
2161 bus->clkstate = CLK_AVAIL;
2162 }
2163 }
2164
2165 /* Make sure backplane clock is on */
2166 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, true);
2167
2168 /* Pending interrupt indicates new device status */
2169 if (atomic_read(&bus->ipend) > 0) {
2170 atomic_set(&bus->ipend, 0);
2171 sdio_claim_host(bus->sdiodev->func[1]);
2172 err = brcmf_sdio_intr_rstatus(bus);
2173 sdio_release_host(bus->sdiodev->func[1]);
2174 }
2175
2176 /* Start with leftover status bits */
2177 intstatus = atomic_xchg(&bus->intstatus, 0);
2178
2179 /* Handle flow-control change: read new state in case our ack
2180 * crossed another change interrupt. If change still set, assume
2181 * FC ON for safety, let next loop through do the debounce.
2182 */
2183 if (intstatus & I_HMB_FC_CHANGE) {
2184 intstatus &= ~I_HMB_FC_CHANGE;
2185 err = w_sdreg32(bus, I_HMB_FC_CHANGE,
2186 offsetof(struct sdpcmd_regs, intstatus));
2187
2188 err = r_sdreg32(bus, &newstatus,
2189 offsetof(struct sdpcmd_regs, intstatus));
2190 bus->sdcnt.f1regdata += 2;
2191 atomic_set(&bus->fcstate,
2192 !!(newstatus & (I_HMB_FC_STATE | I_HMB_FC_CHANGE)));
2193 intstatus |= (newstatus & bus->hostintmask);
2194 }
2195
2196 /* Handle host mailbox indication */
2197 if (intstatus & I_HMB_HOST_INT) {
2198 intstatus &= ~I_HMB_HOST_INT;
2199 intstatus |= brcmf_sdbrcm_hostmail(bus);
2200 }
2201
2202 /* Generally don't ask for these, can get CRC errors... */
2203 if (intstatus & I_WR_OOSYNC) {
2204 brcmf_dbg(ERROR, "Dongle reports WR_OOSYNC\n");
2205 intstatus &= ~I_WR_OOSYNC;
2206 }
2207
2208 if (intstatus & I_RD_OOSYNC) {
2209 brcmf_dbg(ERROR, "Dongle reports RD_OOSYNC\n");
2210 intstatus &= ~I_RD_OOSYNC;
2211 }
2212
2213 if (intstatus & I_SBINT) {
2214 brcmf_dbg(ERROR, "Dongle reports SBINT\n");
2215 intstatus &= ~I_SBINT;
2216 }
2217
2218 /* Would be active due to wake-wlan in gSPI */
2219 if (intstatus & I_CHIPACTIVE) {
2220 brcmf_dbg(INFO, "Dongle reports CHIPACTIVE\n");
2221 intstatus &= ~I_CHIPACTIVE;
2222 }
2223
2224 /* Ignore frame indications if rxskip is set */
2225 if (bus->rxskip)
2226 intstatus &= ~I_HMB_FRAME_IND;
2227
2228 /* On frame indication, read available frames */
2229 if (PKT_AVAILABLE() && bus->clkstate == CLK_AVAIL) {
2230 framecnt = brcmf_sdio_readframes(bus, rxlimit);
2231 if (!bus->rxpending)
2232 intstatus &= ~I_HMB_FRAME_IND;
2233 rxlimit -= min(framecnt, rxlimit);
2234 }
2235
2236 /* Keep still-pending events for next scheduling */
2237 if (intstatus) {
2238 for_each_set_bit(n, &intstatus, 32)
2239 set_bit(n, (unsigned long *)&bus->intstatus.counter);
2240 }
2241
2242 brcmf_sdbrcm_clrintr(bus);
2243
2244 if (data_ok(bus) && bus->ctrl_frame_stat &&
2245 (bus->clkstate == CLK_AVAIL)) {
2246 int i;
2247
2248 err = brcmf_sdcard_send_buf(bus->sdiodev, bus->sdiodev->sbwad,
2249 SDIO_FUNC_2, F2SYNC, bus->ctrl_frame_buf,
2250 (u32) bus->ctrl_frame_len);
2251
2252 if (err < 0) {
2253 /* On failure, abort the command and
2254 terminate the frame */
2255 brcmf_dbg(INFO, "sdio error %d, abort command and terminate frame\n",
2256 err);
2257 bus->sdcnt.tx_sderrs++;
2258
2259 brcmf_sdcard_abort(bus->sdiodev, SDIO_FUNC_2);
2260
2261 brcmf_sdio_regwb(bus->sdiodev, SBSDIO_FUNC1_FRAMECTRL,
2262 SFC_WF_TERM, &err);
2263 bus->sdcnt.f1regdata++;
2264
2265 for (i = 0; i < 3; i++) {
2266 u8 hi, lo;
2267 hi = brcmf_sdio_regrb(bus->sdiodev,
2268 SBSDIO_FUNC1_WFRAMEBCHI,
2269 &err);
2270 lo = brcmf_sdio_regrb(bus->sdiodev,
2271 SBSDIO_FUNC1_WFRAMEBCLO,
2272 &err);
2273 bus->sdcnt.f1regdata += 2;
2274 if ((hi == 0) && (lo == 0))
2275 break;
2276 }
2277
2278 } else {
2279 bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
2280 }
2281 bus->ctrl_frame_stat = false;
2282 brcmf_sdbrcm_wait_event_wakeup(bus);
2283 }
2284 /* Send queued frames (limit 1 if rx may still be pending) */
2285 else if ((bus->clkstate == CLK_AVAIL) && !atomic_read(&bus->fcstate) &&
2286 brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol) && txlimit
2287 && data_ok(bus)) {
2288 framecnt = bus->rxpending ? min(txlimit, bus->txminmax) :
2289 txlimit;
2290 framecnt = brcmf_sdbrcm_sendfromq(bus, framecnt);
2291 txlimit -= framecnt;
2292 }
2293
2294 if ((bus->sdiodev->bus_if->state == BRCMF_BUS_DOWN) || (err != 0)) {
2295 brcmf_dbg(ERROR, "failed backplane access over SDIO, halting operation\n");
2296 bus->sdiodev->bus_if->state = BRCMF_BUS_DOWN;
2297 atomic_set(&bus->intstatus, 0);
2298 } else if (atomic_read(&bus->intstatus) ||
2299 atomic_read(&bus->ipend) > 0 ||
2300 (!atomic_read(&bus->fcstate) &&
2301 brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol) &&
2302 data_ok(bus)) || PKT_AVAILABLE()) {
2303 brcmf_sdbrcm_adddpctsk(bus);
2304 }
2305
2306 /* If we're done for now, turn off clock request. */
2307 if ((bus->clkstate != CLK_PENDING)
2308 && bus->idletime == BRCMF_IDLE_IMMEDIATE) {
2309 bus->activity = false;
2310 brcmf_sdbrcm_clkctl(bus, CLK_NONE, false);
2311 }
2312
2313 up(&bus->sdsem);
2314 }
2315
2316 static int brcmf_sdbrcm_bus_txdata(struct device *dev, struct sk_buff *pkt)
2317 {
2318 int ret = -EBADE;
2319 uint datalen, prec;
2320 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
2321 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
2322 struct brcmf_sdio *bus = sdiodev->bus;
2323 unsigned long flags;
2324
2325 brcmf_dbg(TRACE, "Enter\n");
2326
2327 datalen = pkt->len;
2328
2329 /* Add space for the header */
2330 skb_push(pkt, SDPCM_HDRLEN);
2331 /* precondition: IS_ALIGNED((unsigned long)(pkt->data), 2) */
2332
2333 prec = prio2prec((pkt->priority & PRIOMASK));
2334
2335 /* Check for existing queue, current flow-control,
2336 pending event, or pending clock */
2337 brcmf_dbg(TRACE, "deferring pktq len %d\n", pktq_len(&bus->txq));
2338 bus->sdcnt.fcqueued++;
2339
2340 /* Priority based enq */
2341 spin_lock_bh(&bus->txqlock);
2342 if (!brcmf_c_prec_enq(bus->sdiodev->dev, &bus->txq, pkt, prec)) {
2343 skb_pull(pkt, SDPCM_HDRLEN);
2344 brcmf_txcomplete(bus->sdiodev->dev, pkt, false);
2345 brcmu_pkt_buf_free_skb(pkt);
2346 brcmf_dbg(ERROR, "out of bus->txq !!!\n");
2347 ret = -ENOSR;
2348 } else {
2349 ret = 0;
2350 }
2351 spin_unlock_bh(&bus->txqlock);
2352
2353 if (pktq_len(&bus->txq) >= TXHI) {
2354 bus->txoff = true;
2355 brcmf_txflowblock(bus->sdiodev->dev, true);
2356 }
2357
2358 #ifdef DEBUG
2359 if (pktq_plen(&bus->txq, prec) > qcount[prec])
2360 qcount[prec] = pktq_plen(&bus->txq, prec);
2361 #endif
2362
2363 spin_lock_irqsave(&bus->dpc_tl_lock, flags);
2364 if (list_empty(&bus->dpc_tsklst)) {
2365 spin_unlock_irqrestore(&bus->dpc_tl_lock, flags);
2366
2367 brcmf_sdbrcm_adddpctsk(bus);
2368 queue_work(bus->brcmf_wq, &bus->datawork);
2369 } else {
2370 spin_unlock_irqrestore(&bus->dpc_tl_lock, flags);
2371 }
2372
2373 return ret;
2374 }
2375
2376 static int
2377 brcmf_sdbrcm_membytes(struct brcmf_sdio *bus, bool write, u32 address, u8 *data,
2378 uint size)
2379 {
2380 int bcmerror = 0;
2381 u32 sdaddr;
2382 uint dsize;
2383
2384 /* Determine initial transfer parameters */
2385 sdaddr = address & SBSDIO_SB_OFT_ADDR_MASK;
2386 if ((sdaddr + size) & SBSDIO_SBWINDOW_MASK)
2387 dsize = (SBSDIO_SB_OFT_ADDR_LIMIT - sdaddr);
2388 else
2389 dsize = size;
2390
2391 sdio_claim_host(bus->sdiodev->func[1]);
2392
2393 /* Set the backplane window to include the start address */
2394 bcmerror = brcmf_sdcard_set_sbaddr_window(bus->sdiodev, address);
2395 if (bcmerror) {
2396 brcmf_dbg(ERROR, "window change failed\n");
2397 goto xfer_done;
2398 }
2399
2400 /* Do the transfer(s) */
2401 while (size) {
2402 brcmf_dbg(INFO, "%s %d bytes at offset 0x%08x in window 0x%08x\n",
2403 write ? "write" : "read", dsize,
2404 sdaddr, address & SBSDIO_SBWINDOW_MASK);
2405 bcmerror = brcmf_sdcard_rwdata(bus->sdiodev, write,
2406 sdaddr, data, dsize);
2407 if (bcmerror) {
2408 brcmf_dbg(ERROR, "membytes transfer failed\n");
2409 break;
2410 }
2411
2412 /* Adjust for next transfer (if any) */
2413 size -= dsize;
2414 if (size) {
2415 data += dsize;
2416 address += dsize;
2417 bcmerror = brcmf_sdcard_set_sbaddr_window(bus->sdiodev,
2418 address);
2419 if (bcmerror) {
2420 brcmf_dbg(ERROR, "window change failed\n");
2421 break;
2422 }
2423 sdaddr = 0;
2424 dsize = min_t(uint, SBSDIO_SB_OFT_ADDR_LIMIT, size);
2425 }
2426 }
2427
2428 xfer_done:
2429 /* Return the window to backplane enumeration space for core access */
2430 if (brcmf_sdcard_set_sbaddr_window(bus->sdiodev, bus->sdiodev->sbwad))
2431 brcmf_dbg(ERROR, "FAILED to set window back to 0x%x\n",
2432 bus->sdiodev->sbwad);
2433
2434 sdio_release_host(bus->sdiodev->func[1]);
2435
2436 return bcmerror;
2437 }
2438
2439 #ifdef DEBUG
2440 #define CONSOLE_LINE_MAX 192
2441
2442 static int brcmf_sdbrcm_readconsole(struct brcmf_sdio *bus)
2443 {
2444 struct brcmf_console *c = &bus->console;
2445 u8 line[CONSOLE_LINE_MAX], ch;
2446 u32 n, idx, addr;
2447 int rv;
2448
2449 /* Don't do anything until FWREADY updates console address */
2450 if (bus->console_addr == 0)
2451 return 0;
2452
2453 /* Read console log struct */
2454 addr = bus->console_addr + offsetof(struct rte_console, log_le);
2455 rv = brcmf_sdbrcm_membytes(bus, false, addr, (u8 *)&c->log_le,
2456 sizeof(c->log_le));
2457 if (rv < 0)
2458 return rv;
2459
2460 /* Allocate console buffer (one time only) */
2461 if (c->buf == NULL) {
2462 c->bufsize = le32_to_cpu(c->log_le.buf_size);
2463 c->buf = kmalloc(c->bufsize, GFP_ATOMIC);
2464 if (c->buf == NULL)
2465 return -ENOMEM;
2466 }
2467
2468 idx = le32_to_cpu(c->log_le.idx);
2469
2470 /* Protect against corrupt value */
2471 if (idx > c->bufsize)
2472 return -EBADE;
2473
2474 /* Skip reading the console buffer if the index pointer
2475 has not moved */
2476 if (idx == c->last)
2477 return 0;
2478
2479 /* Read the console buffer */
2480 addr = le32_to_cpu(c->log_le.buf);
2481 rv = brcmf_sdbrcm_membytes(bus, false, addr, c->buf, c->bufsize);
2482 if (rv < 0)
2483 return rv;
2484
2485 while (c->last != idx) {
2486 for (n = 0; n < CONSOLE_LINE_MAX - 2; n++) {
2487 if (c->last == idx) {
2488 /* This would output a partial line.
2489 * Instead, back up
2490 * the buffer pointer and output this
2491 * line next time around.
2492 */
2493 if (c->last >= n)
2494 c->last -= n;
2495 else
2496 c->last = c->bufsize - n;
2497 goto break2;
2498 }
2499 ch = c->buf[c->last];
2500 c->last = (c->last + 1) % c->bufsize;
2501 if (ch == '\n')
2502 break;
2503 line[n] = ch;
2504 }
2505
2506 if (n > 0) {
2507 if (line[n - 1] == '\r')
2508 n--;
2509 line[n] = 0;
2510 pr_debug("CONSOLE: %s\n", line);
2511 }
2512 }
2513 break2:
2514
2515 return 0;
2516 }
2517 #endif /* DEBUG */
2518
2519 static int brcmf_tx_frame(struct brcmf_sdio *bus, u8 *frame, u16 len)
2520 {
2521 int i;
2522 int ret;
2523
2524 bus->ctrl_frame_stat = false;
2525 ret = brcmf_sdcard_send_buf(bus->sdiodev, bus->sdiodev->sbwad,
2526 SDIO_FUNC_2, F2SYNC, frame, len);
2527
2528 if (ret < 0) {
2529 /* On failure, abort the command and terminate the frame */
2530 brcmf_dbg(INFO, "sdio error %d, abort command and terminate frame\n",
2531 ret);
2532 bus->sdcnt.tx_sderrs++;
2533
2534 brcmf_sdcard_abort(bus->sdiodev, SDIO_FUNC_2);
2535
2536 brcmf_sdio_regwb(bus->sdiodev, SBSDIO_FUNC1_FRAMECTRL,
2537 SFC_WF_TERM, NULL);
2538 bus->sdcnt.f1regdata++;
2539
2540 for (i = 0; i < 3; i++) {
2541 u8 hi, lo;
2542 hi = brcmf_sdio_regrb(bus->sdiodev,
2543 SBSDIO_FUNC1_WFRAMEBCHI, NULL);
2544 lo = brcmf_sdio_regrb(bus->sdiodev,
2545 SBSDIO_FUNC1_WFRAMEBCLO, NULL);
2546 bus->sdcnt.f1regdata += 2;
2547 if (hi == 0 && lo == 0)
2548 break;
2549 }
2550 return ret;
2551 }
2552
2553 bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
2554
2555 return ret;
2556 }
2557
2558 static int
2559 brcmf_sdbrcm_bus_txctl(struct device *dev, unsigned char *msg, uint msglen)
2560 {
2561 u8 *frame;
2562 u16 len;
2563 u32 swheader;
2564 uint retries = 0;
2565 u8 doff = 0;
2566 int ret = -1;
2567 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
2568 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
2569 struct brcmf_sdio *bus = sdiodev->bus;
2570 unsigned long flags;
2571
2572 brcmf_dbg(TRACE, "Enter\n");
2573
2574 /* Back the pointer to make a room for bus header */
2575 frame = msg - SDPCM_HDRLEN;
2576 len = (msglen += SDPCM_HDRLEN);
2577
2578 /* Add alignment padding (optional for ctl frames) */
2579 doff = ((unsigned long)frame % BRCMF_SDALIGN);
2580 if (doff) {
2581 frame -= doff;
2582 len += doff;
2583 msglen += doff;
2584 memset(frame, 0, doff + SDPCM_HDRLEN);
2585 }
2586 /* precondition: doff < BRCMF_SDALIGN */
2587 doff += SDPCM_HDRLEN;
2588
2589 /* Round send length to next SDIO block */
2590 if (bus->roundup && bus->blocksize && (len > bus->blocksize)) {
2591 u16 pad = bus->blocksize - (len % bus->blocksize);
2592 if ((pad <= bus->roundup) && (pad < bus->blocksize))
2593 len += pad;
2594 } else if (len % BRCMF_SDALIGN) {
2595 len += BRCMF_SDALIGN - (len % BRCMF_SDALIGN);
2596 }
2597
2598 /* Satisfy length-alignment requirements */
2599 if (len & (ALIGNMENT - 1))
2600 len = roundup(len, ALIGNMENT);
2601
2602 /* precondition: IS_ALIGNED((unsigned long)frame, 2) */
2603
2604 /* Need to lock here to protect txseq and SDIO tx calls */
2605 down(&bus->sdsem);
2606
2607 /* Make sure backplane clock is on */
2608 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
2609
2610 /* Hardware tag: 2 byte len followed by 2 byte ~len check (all LE) */
2611 *(__le16 *) frame = cpu_to_le16((u16) msglen);
2612 *(((__le16 *) frame) + 1) = cpu_to_le16(~msglen);
2613
2614 /* Software tag: channel, sequence number, data offset */
2615 swheader =
2616 ((SDPCM_CONTROL_CHANNEL << SDPCM_CHANNEL_SHIFT) &
2617 SDPCM_CHANNEL_MASK)
2618 | bus->tx_seq | ((doff << SDPCM_DOFFSET_SHIFT) &
2619 SDPCM_DOFFSET_MASK);
2620 put_unaligned_le32(swheader, frame + SDPCM_FRAMETAG_LEN);
2621 put_unaligned_le32(0, frame + SDPCM_FRAMETAG_LEN + sizeof(swheader));
2622
2623 if (!data_ok(bus)) {
2624 brcmf_dbg(INFO, "No bus credit bus->tx_max %d, bus->tx_seq %d\n",
2625 bus->tx_max, bus->tx_seq);
2626 bus->ctrl_frame_stat = true;
2627 /* Send from dpc */
2628 bus->ctrl_frame_buf = frame;
2629 bus->ctrl_frame_len = len;
2630
2631 brcmf_sdbrcm_wait_for_event(bus, &bus->ctrl_frame_stat);
2632
2633 if (!bus->ctrl_frame_stat) {
2634 brcmf_dbg(INFO, "ctrl_frame_stat == false\n");
2635 ret = 0;
2636 } else {
2637 brcmf_dbg(INFO, "ctrl_frame_stat == true\n");
2638 ret = -1;
2639 }
2640 }
2641
2642 if (ret == -1) {
2643 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_CTL_ON(),
2644 frame, len, "Tx Frame:\n");
2645 brcmf_dbg_hex_dump(!(BRCMF_BYTES_ON() && BRCMF_CTL_ON()) &&
2646 BRCMF_HDRS_ON(),
2647 frame, min_t(u16, len, 16), "TxHdr:\n");
2648
2649 do {
2650 ret = brcmf_tx_frame(bus, frame, len);
2651 } while (ret < 0 && retries++ < TXRETRIES);
2652 }
2653
2654 spin_lock_irqsave(&bus->dpc_tl_lock, flags);
2655 if ((bus->idletime == BRCMF_IDLE_IMMEDIATE) &&
2656 list_empty(&bus->dpc_tsklst)) {
2657 spin_unlock_irqrestore(&bus->dpc_tl_lock, flags);
2658
2659 bus->activity = false;
2660 brcmf_sdbrcm_clkctl(bus, CLK_NONE, true);
2661 } else {
2662 spin_unlock_irqrestore(&bus->dpc_tl_lock, flags);
2663 }
2664
2665 up(&bus->sdsem);
2666
2667 if (ret)
2668 bus->sdcnt.tx_ctlerrs++;
2669 else
2670 bus->sdcnt.tx_ctlpkts++;
2671
2672 return ret ? -EIO : 0;
2673 }
2674
2675 #ifdef DEBUG
2676 static inline bool brcmf_sdio_valid_shared_address(u32 addr)
2677 {
2678 return !(addr == 0 || ((~addr >> 16) & 0xffff) == (addr & 0xffff));
2679 }
2680
2681 static int brcmf_sdio_readshared(struct brcmf_sdio *bus,
2682 struct sdpcm_shared *sh)
2683 {
2684 u32 addr;
2685 int rv;
2686 u32 shaddr = 0;
2687 struct sdpcm_shared_le sh_le;
2688 __le32 addr_le;
2689
2690 shaddr = bus->ramsize - 4;
2691
2692 /*
2693 * Read last word in socram to determine
2694 * address of sdpcm_shared structure
2695 */
2696 rv = brcmf_sdbrcm_membytes(bus, false, shaddr,
2697 (u8 *)&addr_le, 4);
2698 if (rv < 0)
2699 return rv;
2700
2701 addr = le32_to_cpu(addr_le);
2702
2703 brcmf_dbg(INFO, "sdpcm_shared address 0x%08X\n", addr);
2704
2705 /*
2706 * Check if addr is valid.
2707 * NVRAM length at the end of memory should have been overwritten.
2708 */
2709 if (!brcmf_sdio_valid_shared_address(addr)) {
2710 brcmf_dbg(ERROR, "invalid sdpcm_shared address 0x%08X\n",
2711 addr);
2712 return -EINVAL;
2713 }
2714
2715 /* Read hndrte_shared structure */
2716 rv = brcmf_sdbrcm_membytes(bus, false, addr, (u8 *)&sh_le,
2717 sizeof(struct sdpcm_shared_le));
2718 if (rv < 0)
2719 return rv;
2720
2721 /* Endianness */
2722 sh->flags = le32_to_cpu(sh_le.flags);
2723 sh->trap_addr = le32_to_cpu(sh_le.trap_addr);
2724 sh->assert_exp_addr = le32_to_cpu(sh_le.assert_exp_addr);
2725 sh->assert_file_addr = le32_to_cpu(sh_le.assert_file_addr);
2726 sh->assert_line = le32_to_cpu(sh_le.assert_line);
2727 sh->console_addr = le32_to_cpu(sh_le.console_addr);
2728 sh->msgtrace_addr = le32_to_cpu(sh_le.msgtrace_addr);
2729
2730 if ((sh->flags & SDPCM_SHARED_VERSION_MASK) != SDPCM_SHARED_VERSION) {
2731 brcmf_dbg(ERROR,
2732 "sdpcm_shared version mismatch: dhd %d dongle %d\n",
2733 SDPCM_SHARED_VERSION,
2734 sh->flags & SDPCM_SHARED_VERSION_MASK);
2735 return -EPROTO;
2736 }
2737
2738 return 0;
2739 }
2740
2741 static int brcmf_sdio_dump_console(struct brcmf_sdio *bus,
2742 struct sdpcm_shared *sh, char __user *data,
2743 size_t count)
2744 {
2745 u32 addr, console_ptr, console_size, console_index;
2746 char *conbuf = NULL;
2747 __le32 sh_val;
2748 int rv;
2749 loff_t pos = 0;
2750 int nbytes = 0;
2751
2752 /* obtain console information from device memory */
2753 addr = sh->console_addr + offsetof(struct rte_console, log_le);
2754 rv = brcmf_sdbrcm_membytes(bus, false, addr,
2755 (u8 *)&sh_val, sizeof(u32));
2756 if (rv < 0)
2757 return rv;
2758 console_ptr = le32_to_cpu(sh_val);
2759
2760 addr = sh->console_addr + offsetof(struct rte_console, log_le.buf_size);
2761 rv = brcmf_sdbrcm_membytes(bus, false, addr,
2762 (u8 *)&sh_val, sizeof(u32));
2763 if (rv < 0)
2764 return rv;
2765 console_size = le32_to_cpu(sh_val);
2766
2767 addr = sh->console_addr + offsetof(struct rte_console, log_le.idx);
2768 rv = brcmf_sdbrcm_membytes(bus, false, addr,
2769 (u8 *)&sh_val, sizeof(u32));
2770 if (rv < 0)
2771 return rv;
2772 console_index = le32_to_cpu(sh_val);
2773
2774 /* allocate buffer for console data */
2775 if (console_size <= CONSOLE_BUFFER_MAX)
2776 conbuf = vzalloc(console_size+1);
2777
2778 if (!conbuf)
2779 return -ENOMEM;
2780
2781 /* obtain the console data from device */
2782 conbuf[console_size] = '\0';
2783 rv = brcmf_sdbrcm_membytes(bus, false, console_ptr, (u8 *)conbuf,
2784 console_size);
2785 if (rv < 0)
2786 goto done;
2787
2788 rv = simple_read_from_buffer(data, count, &pos,
2789 conbuf + console_index,
2790 console_size - console_index);
2791 if (rv < 0)
2792 goto done;
2793
2794 nbytes = rv;
2795 if (console_index > 0) {
2796 pos = 0;
2797 rv = simple_read_from_buffer(data+nbytes, count, &pos,
2798 conbuf, console_index - 1);
2799 if (rv < 0)
2800 goto done;
2801 rv += nbytes;
2802 }
2803 done:
2804 vfree(conbuf);
2805 return rv;
2806 }
2807
2808 static int brcmf_sdio_trap_info(struct brcmf_sdio *bus, struct sdpcm_shared *sh,
2809 char __user *data, size_t count)
2810 {
2811 int error, res;
2812 char buf[350];
2813 struct brcmf_trap_info tr;
2814 int nbytes;
2815 loff_t pos = 0;
2816
2817 if ((sh->flags & SDPCM_SHARED_TRAP) == 0)
2818 return 0;
2819
2820 error = brcmf_sdbrcm_membytes(bus, false, sh->trap_addr, (u8 *)&tr,
2821 sizeof(struct brcmf_trap_info));
2822 if (error < 0)
2823 return error;
2824
2825 nbytes = brcmf_sdio_dump_console(bus, sh, data, count);
2826 if (nbytes < 0)
2827 return nbytes;
2828
2829 res = scnprintf(buf, sizeof(buf),
2830 "dongle trap info: type 0x%x @ epc 0x%08x\n"
2831 " cpsr 0x%08x spsr 0x%08x sp 0x%08x\n"
2832 " lr 0x%08x pc 0x%08x offset 0x%x\n"
2833 " r0 0x%08x r1 0x%08x r2 0x%08x r3 0x%08x\n"
2834 " r4 0x%08x r5 0x%08x r6 0x%08x r7 0x%08x\n",
2835 le32_to_cpu(tr.type), le32_to_cpu(tr.epc),
2836 le32_to_cpu(tr.cpsr), le32_to_cpu(tr.spsr),
2837 le32_to_cpu(tr.r13), le32_to_cpu(tr.r14),
2838 le32_to_cpu(tr.pc), sh->trap_addr,
2839 le32_to_cpu(tr.r0), le32_to_cpu(tr.r1),
2840 le32_to_cpu(tr.r2), le32_to_cpu(tr.r3),
2841 le32_to_cpu(tr.r4), le32_to_cpu(tr.r5),
2842 le32_to_cpu(tr.r6), le32_to_cpu(tr.r7));
2843
2844 error = simple_read_from_buffer(data+nbytes, count, &pos, buf, res);
2845 if (error < 0)
2846 return error;
2847
2848 nbytes += error;
2849 return nbytes;
2850 }
2851
2852 static int brcmf_sdio_assert_info(struct brcmf_sdio *bus,
2853 struct sdpcm_shared *sh, char __user *data,
2854 size_t count)
2855 {
2856 int error = 0;
2857 char buf[200];
2858 char file[80] = "?";
2859 char expr[80] = "<???>";
2860 int res;
2861 loff_t pos = 0;
2862
2863 if ((sh->flags & SDPCM_SHARED_ASSERT_BUILT) == 0) {
2864 brcmf_dbg(INFO, "firmware not built with -assert\n");
2865 return 0;
2866 } else if ((sh->flags & SDPCM_SHARED_ASSERT) == 0) {
2867 brcmf_dbg(INFO, "no assert in dongle\n");
2868 return 0;
2869 }
2870
2871 if (sh->assert_file_addr != 0) {
2872 error = brcmf_sdbrcm_membytes(bus, false, sh->assert_file_addr,
2873 (u8 *)file, 80);
2874 if (error < 0)
2875 return error;
2876 }
2877 if (sh->assert_exp_addr != 0) {
2878 error = brcmf_sdbrcm_membytes(bus, false, sh->assert_exp_addr,
2879 (u8 *)expr, 80);
2880 if (error < 0)
2881 return error;
2882 }
2883
2884 res = scnprintf(buf, sizeof(buf),
2885 "dongle assert: %s:%d: assert(%s)\n",
2886 file, sh->assert_line, expr);
2887 return simple_read_from_buffer(data, count, &pos, buf, res);
2888 }
2889
2890 static int brcmf_sdbrcm_checkdied(struct brcmf_sdio *bus)
2891 {
2892 int error;
2893 struct sdpcm_shared sh;
2894
2895 down(&bus->sdsem);
2896 error = brcmf_sdio_readshared(bus, &sh);
2897 up(&bus->sdsem);
2898
2899 if (error < 0)
2900 return error;
2901
2902 if ((sh.flags & SDPCM_SHARED_ASSERT_BUILT) == 0)
2903 brcmf_dbg(INFO, "firmware not built with -assert\n");
2904 else if (sh.flags & SDPCM_SHARED_ASSERT)
2905 brcmf_dbg(ERROR, "assertion in dongle\n");
2906
2907 if (sh.flags & SDPCM_SHARED_TRAP)
2908 brcmf_dbg(ERROR, "firmware trap in dongle\n");
2909
2910 return 0;
2911 }
2912
2913 static int brcmf_sdbrcm_died_dump(struct brcmf_sdio *bus, char __user *data,
2914 size_t count, loff_t *ppos)
2915 {
2916 int error = 0;
2917 struct sdpcm_shared sh;
2918 int nbytes = 0;
2919 loff_t pos = *ppos;
2920
2921 if (pos != 0)
2922 return 0;
2923
2924 down(&bus->sdsem);
2925 error = brcmf_sdio_readshared(bus, &sh);
2926 if (error < 0)
2927 goto done;
2928
2929 error = brcmf_sdio_assert_info(bus, &sh, data, count);
2930 if (error < 0)
2931 goto done;
2932
2933 nbytes = error;
2934 error = brcmf_sdio_trap_info(bus, &sh, data, count);
2935 if (error < 0)
2936 goto done;
2937
2938 error += nbytes;
2939 *ppos += error;
2940 done:
2941 up(&bus->sdsem);
2942 return error;
2943 }
2944
2945 static ssize_t brcmf_sdio_forensic_read(struct file *f, char __user *data,
2946 size_t count, loff_t *ppos)
2947 {
2948 struct brcmf_sdio *bus = f->private_data;
2949 int res;
2950
2951 res = brcmf_sdbrcm_died_dump(bus, data, count, ppos);
2952 if (res > 0)
2953 *ppos += res;
2954 return (ssize_t)res;
2955 }
2956
2957 static const struct file_operations brcmf_sdio_forensic_ops = {
2958 .owner = THIS_MODULE,
2959 .open = simple_open,
2960 .read = brcmf_sdio_forensic_read
2961 };
2962
2963 static void brcmf_sdio_debugfs_create(struct brcmf_sdio *bus)
2964 {
2965 struct brcmf_pub *drvr = bus->sdiodev->bus_if->drvr;
2966 struct dentry *dentry = brcmf_debugfs_get_devdir(drvr);
2967
2968 if (IS_ERR_OR_NULL(dentry))
2969 return;
2970
2971 debugfs_create_file("forensics", S_IRUGO, dentry, bus,
2972 &brcmf_sdio_forensic_ops);
2973 brcmf_debugfs_create_sdio_count(drvr, &bus->sdcnt);
2974 }
2975 #else
2976 static int brcmf_sdbrcm_checkdied(struct brcmf_sdio *bus)
2977 {
2978 return 0;
2979 }
2980
2981 static void brcmf_sdio_debugfs_create(struct brcmf_sdio *bus)
2982 {
2983 }
2984 #endif /* DEBUG */
2985
2986 static int
2987 brcmf_sdbrcm_bus_rxctl(struct device *dev, unsigned char *msg, uint msglen)
2988 {
2989 int timeleft;
2990 uint rxlen = 0;
2991 bool pending;
2992 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
2993 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
2994 struct brcmf_sdio *bus = sdiodev->bus;
2995
2996 brcmf_dbg(TRACE, "Enter\n");
2997
2998 /* Wait until control frame is available */
2999 timeleft = brcmf_sdbrcm_dcmd_resp_wait(bus, &bus->rxlen, &pending);
3000
3001 down(&bus->sdsem);
3002 rxlen = bus->rxlen;
3003 memcpy(msg, bus->rxctl, min(msglen, rxlen));
3004 bus->rxlen = 0;
3005 up(&bus->sdsem);
3006
3007 if (rxlen) {
3008 brcmf_dbg(CTL, "resumed on rxctl frame, got %d expected %d\n",
3009 rxlen, msglen);
3010 } else if (timeleft == 0) {
3011 brcmf_dbg(ERROR, "resumed on timeout\n");
3012 brcmf_sdbrcm_checkdied(bus);
3013 } else if (pending) {
3014 brcmf_dbg(CTL, "cancelled\n");
3015 return -ERESTARTSYS;
3016 } else {
3017 brcmf_dbg(CTL, "resumed for unknown reason?\n");
3018 brcmf_sdbrcm_checkdied(bus);
3019 }
3020
3021 if (rxlen)
3022 bus->sdcnt.rx_ctlpkts++;
3023 else
3024 bus->sdcnt.rx_ctlerrs++;
3025
3026 return rxlen ? (int)rxlen : -ETIMEDOUT;
3027 }
3028
3029 static int brcmf_sdbrcm_write_vars(struct brcmf_sdio *bus)
3030 {
3031 int bcmerror = 0;
3032 u32 varaddr;
3033 u32 varsizew;
3034 __le32 varsizew_le;
3035 #ifdef DEBUG
3036 char *nvram_ularray;
3037 #endif /* DEBUG */
3038
3039 /* Even if there are no vars are to be written, we still
3040 need to set the ramsize. */
3041 varaddr = (bus->ramsize - 4) - bus->varsz;
3042
3043 if (bus->vars) {
3044 /* Write the vars list */
3045 bcmerror = brcmf_sdbrcm_membytes(bus, true, varaddr,
3046 bus->vars, bus->varsz);
3047 #ifdef DEBUG
3048 /* Verify NVRAM bytes */
3049 brcmf_dbg(INFO, "Compare NVRAM dl & ul; varsize=%d\n",
3050 bus->varsz);
3051 nvram_ularray = kmalloc(bus->varsz, GFP_ATOMIC);
3052 if (!nvram_ularray)
3053 return -ENOMEM;
3054
3055 /* Upload image to verify downloaded contents. */
3056 memset(nvram_ularray, 0xaa, bus->varsz);
3057
3058 /* Read the vars list to temp buffer for comparison */
3059 bcmerror = brcmf_sdbrcm_membytes(bus, false, varaddr,
3060 nvram_ularray, bus->varsz);
3061 if (bcmerror) {
3062 brcmf_dbg(ERROR, "error %d on reading %d nvram bytes at 0x%08x\n",
3063 bcmerror, bus->varsz, varaddr);
3064 }
3065 /* Compare the org NVRAM with the one read from RAM */
3066 if (memcmp(bus->vars, nvram_ularray, bus->varsz))
3067 brcmf_dbg(ERROR, "Downloaded NVRAM image is corrupted\n");
3068 else
3069 brcmf_dbg(ERROR, "Download/Upload/Compare of NVRAM ok\n");
3070
3071 kfree(nvram_ularray);
3072 #endif /* DEBUG */
3073 }
3074
3075 /* adjust to the user specified RAM */
3076 brcmf_dbg(INFO, "Physical memory size: %d\n", bus->ramsize);
3077 brcmf_dbg(INFO, "Vars are at %d, orig varsize is %d\n",
3078 varaddr, bus->varsz);
3079
3080 /*
3081 * Determine the length token:
3082 * Varsize, converted to words, in lower 16-bits, checksum
3083 * in upper 16-bits.
3084 */
3085 if (bcmerror) {
3086 varsizew = 0;
3087 varsizew_le = cpu_to_le32(0);
3088 } else {
3089 varsizew = bus->varsz / 4;
3090 varsizew = (~varsizew << 16) | (varsizew & 0x0000FFFF);
3091 varsizew_le = cpu_to_le32(varsizew);
3092 }
3093
3094 brcmf_dbg(INFO, "New varsize is %d, length token=0x%08x\n",
3095 bus->varsz, varsizew);
3096
3097 /* Write the length token to the last word */
3098 bcmerror = brcmf_sdbrcm_membytes(bus, true, (bus->ramsize - 4),
3099 (u8 *)&varsizew_le, 4);
3100
3101 return bcmerror;
3102 }
3103
3104 static int brcmf_sdbrcm_download_state(struct brcmf_sdio *bus, bool enter)
3105 {
3106 int bcmerror = 0;
3107 struct chip_info *ci = bus->ci;
3108
3109 /* To enter download state, disable ARM and reset SOCRAM.
3110 * To exit download state, simply reset ARM (default is RAM boot).
3111 */
3112 if (enter) {
3113 bus->alp_only = true;
3114
3115 ci->coredisable(bus->sdiodev, ci, BCMA_CORE_ARM_CM3);
3116
3117 ci->resetcore(bus->sdiodev, ci, BCMA_CORE_INTERNAL_MEM);
3118
3119 /* Clear the top bit of memory */
3120 if (bus->ramsize) {
3121 u32 zeros = 0;
3122 brcmf_sdbrcm_membytes(bus, true, bus->ramsize - 4,
3123 (u8 *)&zeros, 4);
3124 }
3125 } else {
3126 if (!ci->iscoreup(bus->sdiodev, ci, BCMA_CORE_INTERNAL_MEM)) {
3127 brcmf_dbg(ERROR, "SOCRAM core is down after reset?\n");
3128 bcmerror = -EBADE;
3129 goto fail;
3130 }
3131
3132 bcmerror = brcmf_sdbrcm_write_vars(bus);
3133 if (bcmerror) {
3134 brcmf_dbg(ERROR, "no vars written to RAM\n");
3135 bcmerror = 0;
3136 }
3137
3138 w_sdreg32(bus, 0xFFFFFFFF,
3139 offsetof(struct sdpcmd_regs, intstatus));
3140
3141 ci->resetcore(bus->sdiodev, ci, BCMA_CORE_ARM_CM3);
3142
3143 /* Allow HT Clock now that the ARM is running. */
3144 bus->alp_only = false;
3145
3146 bus->sdiodev->bus_if->state = BRCMF_BUS_LOAD;
3147 }
3148 fail:
3149 return bcmerror;
3150 }
3151
3152 static int brcmf_sdbrcm_get_image(char *buf, int len, struct brcmf_sdio *bus)
3153 {
3154 if (bus->firmware->size < bus->fw_ptr + len)
3155 len = bus->firmware->size - bus->fw_ptr;
3156
3157 memcpy(buf, &bus->firmware->data[bus->fw_ptr], len);
3158 bus->fw_ptr += len;
3159 return len;
3160 }
3161
3162 static int brcmf_sdbrcm_download_code_file(struct brcmf_sdio *bus)
3163 {
3164 int offset = 0;
3165 uint len;
3166 u8 *memblock = NULL, *memptr;
3167 int ret;
3168
3169 brcmf_dbg(INFO, "Enter\n");
3170
3171 ret = request_firmware(&bus->firmware, BRCMF_SDIO_FW_NAME,
3172 &bus->sdiodev->func[2]->dev);
3173 if (ret) {
3174 brcmf_dbg(ERROR, "Fail to request firmware %d\n", ret);
3175 return ret;
3176 }
3177 bus->fw_ptr = 0;
3178
3179 memptr = memblock = kmalloc(MEMBLOCK + BRCMF_SDALIGN, GFP_ATOMIC);
3180 if (memblock == NULL) {
3181 ret = -ENOMEM;
3182 goto err;
3183 }
3184 if ((u32)(unsigned long)memblock % BRCMF_SDALIGN)
3185 memptr += (BRCMF_SDALIGN -
3186 ((u32)(unsigned long)memblock % BRCMF_SDALIGN));
3187
3188 /* Download image */
3189 while ((len =
3190 brcmf_sdbrcm_get_image((char *)memptr, MEMBLOCK, bus))) {
3191 ret = brcmf_sdbrcm_membytes(bus, true, offset, memptr, len);
3192 if (ret) {
3193 brcmf_dbg(ERROR, "error %d on writing %d membytes at 0x%08x\n",
3194 ret, MEMBLOCK, offset);
3195 goto err;
3196 }
3197
3198 offset += MEMBLOCK;
3199 }
3200
3201 err:
3202 kfree(memblock);
3203
3204 release_firmware(bus->firmware);
3205 bus->fw_ptr = 0;
3206
3207 return ret;
3208 }
3209
3210 /*
3211 * ProcessVars:Takes a buffer of "<var>=<value>\n" lines read from a file
3212 * and ending in a NUL.
3213 * Removes carriage returns, empty lines, comment lines, and converts
3214 * newlines to NULs.
3215 * Shortens buffer as needed and pads with NULs. End of buffer is marked
3216 * by two NULs.
3217 */
3218
3219 static int brcmf_process_nvram_vars(struct brcmf_sdio *bus)
3220 {
3221 char *varbuf;
3222 char *dp;
3223 bool findNewline;
3224 int column;
3225 int ret = 0;
3226 uint buf_len, n, len;
3227
3228 len = bus->firmware->size;
3229 varbuf = vmalloc(len);
3230 if (!varbuf)
3231 return -ENOMEM;
3232
3233 memcpy(varbuf, bus->firmware->data, len);
3234 dp = varbuf;
3235
3236 findNewline = false;
3237 column = 0;
3238
3239 for (n = 0; n < len; n++) {
3240 if (varbuf[n] == 0)
3241 break;
3242 if (varbuf[n] == '\r')
3243 continue;
3244 if (findNewline && varbuf[n] != '\n')
3245 continue;
3246 findNewline = false;
3247 if (varbuf[n] == '#') {
3248 findNewline = true;
3249 continue;
3250 }
3251 if (varbuf[n] == '\n') {
3252 if (column == 0)
3253 continue;
3254 *dp++ = 0;
3255 column = 0;
3256 continue;
3257 }
3258 *dp++ = varbuf[n];
3259 column++;
3260 }
3261 buf_len = dp - varbuf;
3262 while (dp < varbuf + n)
3263 *dp++ = 0;
3264
3265 kfree(bus->vars);
3266 /* roundup needed for download to device */
3267 bus->varsz = roundup(buf_len + 1, 4);
3268 bus->vars = kmalloc(bus->varsz, GFP_KERNEL);
3269 if (bus->vars == NULL) {
3270 bus->varsz = 0;
3271 ret = -ENOMEM;
3272 goto err;
3273 }
3274
3275 /* copy the processed variables and add null termination */
3276 memcpy(bus->vars, varbuf, buf_len);
3277 bus->vars[buf_len] = 0;
3278 err:
3279 vfree(varbuf);
3280 return ret;
3281 }
3282
3283 static int brcmf_sdbrcm_download_nvram(struct brcmf_sdio *bus)
3284 {
3285 int ret;
3286
3287 if (bus->sdiodev->bus_if->drvr_up)
3288 return -EISCONN;
3289
3290 ret = request_firmware(&bus->firmware, BRCMF_SDIO_NV_NAME,
3291 &bus->sdiodev->func[2]->dev);
3292 if (ret) {
3293 brcmf_dbg(ERROR, "Fail to request nvram %d\n", ret);
3294 return ret;
3295 }
3296
3297 ret = brcmf_process_nvram_vars(bus);
3298
3299 release_firmware(bus->firmware);
3300
3301 return ret;
3302 }
3303
3304 static int _brcmf_sdbrcm_download_firmware(struct brcmf_sdio *bus)
3305 {
3306 int bcmerror = -1;
3307
3308 /* Keep arm in reset */
3309 if (brcmf_sdbrcm_download_state(bus, true)) {
3310 brcmf_dbg(ERROR, "error placing ARM core in reset\n");
3311 goto err;
3312 }
3313
3314 /* External image takes precedence if specified */
3315 if (brcmf_sdbrcm_download_code_file(bus)) {
3316 brcmf_dbg(ERROR, "dongle image file download failed\n");
3317 goto err;
3318 }
3319
3320 /* External nvram takes precedence if specified */
3321 if (brcmf_sdbrcm_download_nvram(bus))
3322 brcmf_dbg(ERROR, "dongle nvram file download failed\n");
3323
3324 /* Take arm out of reset */
3325 if (brcmf_sdbrcm_download_state(bus, false)) {
3326 brcmf_dbg(ERROR, "error getting out of ARM core reset\n");
3327 goto err;
3328 }
3329
3330 bcmerror = 0;
3331
3332 err:
3333 return bcmerror;
3334 }
3335
3336 static bool
3337 brcmf_sdbrcm_download_firmware(struct brcmf_sdio *bus)
3338 {
3339 bool ret;
3340
3341 /* Download the firmware */
3342 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
3343
3344 ret = _brcmf_sdbrcm_download_firmware(bus) == 0;
3345
3346 brcmf_sdbrcm_clkctl(bus, CLK_SDONLY, false);
3347
3348 return ret;
3349 }
3350
3351 static int brcmf_sdbrcm_bus_init(struct device *dev)
3352 {
3353 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
3354 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
3355 struct brcmf_sdio *bus = sdiodev->bus;
3356 unsigned long timeout;
3357 u8 ready, enable;
3358 int err, ret = 0;
3359 u8 saveclk;
3360
3361 brcmf_dbg(TRACE, "Enter\n");
3362
3363 /* try to download image and nvram to the dongle */
3364 if (bus_if->state == BRCMF_BUS_DOWN) {
3365 if (!(brcmf_sdbrcm_download_firmware(bus)))
3366 return -1;
3367 }
3368
3369 if (!bus->sdiodev->bus_if->drvr)
3370 return 0;
3371
3372 /* Start the watchdog timer */
3373 bus->sdcnt.tickcnt = 0;
3374 brcmf_sdbrcm_wd_timer(bus, BRCMF_WD_POLL_MS);
3375
3376 down(&bus->sdsem);
3377
3378 /* Make sure backplane clock is on, needed to generate F2 interrupt */
3379 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
3380 if (bus->clkstate != CLK_AVAIL)
3381 goto exit;
3382
3383 /* Force clocks on backplane to be sure F2 interrupt propagates */
3384 saveclk = brcmf_sdio_regrb(bus->sdiodev,
3385 SBSDIO_FUNC1_CHIPCLKCSR, &err);
3386 if (!err) {
3387 brcmf_sdio_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
3388 (saveclk | SBSDIO_FORCE_HT), &err);
3389 }
3390 if (err) {
3391 brcmf_dbg(ERROR, "Failed to force clock for F2: err %d\n", err);
3392 goto exit;
3393 }
3394
3395 /* Enable function 2 (frame transfers) */
3396 w_sdreg32(bus, SDPCM_PROT_VERSION << SMB_DATA_VERSION_SHIFT,
3397 offsetof(struct sdpcmd_regs, tosbmailboxdata));
3398 enable = (SDIO_FUNC_ENABLE_1 | SDIO_FUNC_ENABLE_2);
3399
3400 brcmf_sdio_regwb(bus->sdiodev, SDIO_CCCR_IOEx, enable, NULL);
3401
3402 timeout = jiffies + msecs_to_jiffies(BRCMF_WAIT_F2RDY);
3403 ready = 0;
3404 while (enable != ready) {
3405 ready = brcmf_sdio_regrb(bus->sdiodev,
3406 SDIO_CCCR_IORx, NULL);
3407 if (time_after(jiffies, timeout))
3408 break;
3409 else if (time_after(jiffies, timeout - BRCMF_WAIT_F2RDY + 50))
3410 /* prevent busy waiting if it takes too long */
3411 msleep_interruptible(20);
3412 }
3413
3414 brcmf_dbg(INFO, "enable 0x%02x, ready 0x%02x\n", enable, ready);
3415
3416 /* If F2 successfully enabled, set core and enable interrupts */
3417 if (ready == enable) {
3418 /* Set up the interrupt mask and enable interrupts */
3419 bus->hostintmask = HOSTINTMASK;
3420 w_sdreg32(bus, bus->hostintmask,
3421 offsetof(struct sdpcmd_regs, hostintmask));
3422
3423 brcmf_sdio_regwb(bus->sdiodev, SBSDIO_WATERMARK, 8, &err);
3424 } else {
3425 /* Disable F2 again */
3426 enable = SDIO_FUNC_ENABLE_1;
3427 brcmf_sdio_regwb(bus->sdiodev, SDIO_CCCR_IOEx, enable, NULL);
3428 ret = -ENODEV;
3429 }
3430
3431 /* Restore previous clock setting */
3432 brcmf_sdio_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, saveclk, &err);
3433
3434 if (ret == 0) {
3435 ret = brcmf_sdio_intr_register(bus->sdiodev);
3436 if (ret != 0)
3437 brcmf_dbg(ERROR, "intr register failed:%d\n", ret);
3438 }
3439
3440 /* If we didn't come up, turn off backplane clock */
3441 if (bus_if->state != BRCMF_BUS_DATA)
3442 brcmf_sdbrcm_clkctl(bus, CLK_NONE, false);
3443
3444 exit:
3445 up(&bus->sdsem);
3446
3447 return ret;
3448 }
3449
3450 void brcmf_sdbrcm_isr(void *arg)
3451 {
3452 struct brcmf_sdio *bus = (struct brcmf_sdio *) arg;
3453
3454 brcmf_dbg(TRACE, "Enter\n");
3455
3456 if (!bus) {
3457 brcmf_dbg(ERROR, "bus is null pointer, exiting\n");
3458 return;
3459 }
3460
3461 if (bus->sdiodev->bus_if->state == BRCMF_BUS_DOWN) {
3462 brcmf_dbg(ERROR, "bus is down. we have nothing to do\n");
3463 return;
3464 }
3465 /* Count the interrupt call */
3466 bus->sdcnt.intrcount++;
3467 if (in_interrupt())
3468 atomic_set(&bus->ipend, 1);
3469 else
3470 if (brcmf_sdio_intr_rstatus(bus)) {
3471 brcmf_dbg(ERROR, "failed backplane access\n");
3472 bus->sdiodev->bus_if->state = BRCMF_BUS_DOWN;
3473 }
3474
3475 /* Disable additional interrupts (is this needed now)? */
3476 if (!bus->intr)
3477 brcmf_dbg(ERROR, "isr w/o interrupt configured!\n");
3478
3479 brcmf_sdbrcm_adddpctsk(bus);
3480 queue_work(bus->brcmf_wq, &bus->datawork);
3481 }
3482
3483 static bool brcmf_sdbrcm_bus_watchdog(struct brcmf_sdio *bus)
3484 {
3485 #ifdef DEBUG
3486 struct brcmf_bus *bus_if = dev_get_drvdata(bus->sdiodev->dev);
3487 #endif /* DEBUG */
3488 unsigned long flags;
3489
3490 brcmf_dbg(TIMER, "Enter\n");
3491
3492 down(&bus->sdsem);
3493
3494 /* Poll period: check device if appropriate. */
3495 if (bus->poll && (++bus->polltick >= bus->pollrate)) {
3496 u32 intstatus = 0;
3497
3498 /* Reset poll tick */
3499 bus->polltick = 0;
3500
3501 /* Check device if no interrupts */
3502 if (!bus->intr ||
3503 (bus->sdcnt.intrcount == bus->sdcnt.lastintrs)) {
3504
3505 spin_lock_irqsave(&bus->dpc_tl_lock, flags);
3506 if (list_empty(&bus->dpc_tsklst)) {
3507 u8 devpend;
3508 spin_unlock_irqrestore(&bus->dpc_tl_lock,
3509 flags);
3510 devpend = brcmf_sdio_regrb(bus->sdiodev,
3511 SDIO_CCCR_INTx,
3512 NULL);
3513 intstatus =
3514 devpend & (INTR_STATUS_FUNC1 |
3515 INTR_STATUS_FUNC2);
3516 } else {
3517 spin_unlock_irqrestore(&bus->dpc_tl_lock,
3518 flags);
3519 }
3520
3521 /* If there is something, make like the ISR and
3522 schedule the DPC */
3523 if (intstatus) {
3524 bus->sdcnt.pollcnt++;
3525 atomic_set(&bus->ipend, 1);
3526
3527 brcmf_sdbrcm_adddpctsk(bus);
3528 queue_work(bus->brcmf_wq, &bus->datawork);
3529 }
3530 }
3531
3532 /* Update interrupt tracking */
3533 bus->sdcnt.lastintrs = bus->sdcnt.intrcount;
3534 }
3535 #ifdef DEBUG
3536 /* Poll for console output periodically */
3537 if (bus_if->state == BRCMF_BUS_DATA &&
3538 bus->console_interval != 0) {
3539 bus->console.count += BRCMF_WD_POLL_MS;
3540 if (bus->console.count >= bus->console_interval) {
3541 bus->console.count -= bus->console_interval;
3542 /* Make sure backplane clock is on */
3543 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
3544 if (brcmf_sdbrcm_readconsole(bus) < 0)
3545 /* stop on error */
3546 bus->console_interval = 0;
3547 }
3548 }
3549 #endif /* DEBUG */
3550
3551 /* On idle timeout clear activity flag and/or turn off clock */
3552 if ((bus->idletime > 0) && (bus->clkstate == CLK_AVAIL)) {
3553 if (++bus->idlecount >= bus->idletime) {
3554 bus->idlecount = 0;
3555 if (bus->activity) {
3556 bus->activity = false;
3557 brcmf_sdbrcm_wd_timer(bus, BRCMF_WD_POLL_MS);
3558 } else {
3559 brcmf_sdbrcm_clkctl(bus, CLK_NONE, false);
3560 }
3561 }
3562 }
3563
3564 up(&bus->sdsem);
3565
3566 return (atomic_read(&bus->ipend) > 0);
3567 }
3568
3569 static bool brcmf_sdbrcm_chipmatch(u16 chipid)
3570 {
3571 if (chipid == BCM43241_CHIP_ID)
3572 return true;
3573 if (chipid == BCM4329_CHIP_ID)
3574 return true;
3575 if (chipid == BCM4330_CHIP_ID)
3576 return true;
3577 if (chipid == BCM4334_CHIP_ID)
3578 return true;
3579 return false;
3580 }
3581
3582 static void brcmf_sdio_dataworker(struct work_struct *work)
3583 {
3584 struct brcmf_sdio *bus = container_of(work, struct brcmf_sdio,
3585 datawork);
3586 struct list_head *cur_hd, *tmp_hd;
3587 unsigned long flags;
3588
3589 spin_lock_irqsave(&bus->dpc_tl_lock, flags);
3590 list_for_each_safe(cur_hd, tmp_hd, &bus->dpc_tsklst) {
3591 spin_unlock_irqrestore(&bus->dpc_tl_lock, flags);
3592
3593 brcmf_sdbrcm_dpc(bus);
3594
3595 spin_lock_irqsave(&bus->dpc_tl_lock, flags);
3596 list_del(cur_hd);
3597 kfree(cur_hd);
3598 }
3599 spin_unlock_irqrestore(&bus->dpc_tl_lock, flags);
3600 }
3601
3602 static void brcmf_sdbrcm_release_malloc(struct brcmf_sdio *bus)
3603 {
3604 brcmf_dbg(TRACE, "Enter\n");
3605
3606 kfree(bus->rxbuf);
3607 bus->rxctl = bus->rxbuf = NULL;
3608 bus->rxlen = 0;
3609
3610 kfree(bus->databuf);
3611 bus->databuf = NULL;
3612 }
3613
3614 static bool brcmf_sdbrcm_probe_malloc(struct brcmf_sdio *bus)
3615 {
3616 brcmf_dbg(TRACE, "Enter\n");
3617
3618 if (bus->sdiodev->bus_if->maxctl) {
3619 bus->rxblen =
3620 roundup((bus->sdiodev->bus_if->maxctl + SDPCM_HDRLEN),
3621 ALIGNMENT) + BRCMF_SDALIGN;
3622 bus->rxbuf = kmalloc(bus->rxblen, GFP_ATOMIC);
3623 if (!(bus->rxbuf))
3624 goto fail;
3625 }
3626
3627 /* Allocate buffer to receive glomed packet */
3628 bus->databuf = kmalloc(MAX_DATA_BUF, GFP_ATOMIC);
3629 if (!(bus->databuf)) {
3630 /* release rxbuf which was already located as above */
3631 if (!bus->rxblen)
3632 kfree(bus->rxbuf);
3633 goto fail;
3634 }
3635
3636 /* Align the buffer */
3637 if ((unsigned long)bus->databuf % BRCMF_SDALIGN)
3638 bus->dataptr = bus->databuf + (BRCMF_SDALIGN -
3639 ((unsigned long)bus->databuf % BRCMF_SDALIGN));
3640 else
3641 bus->dataptr = bus->databuf;
3642
3643 return true;
3644
3645 fail:
3646 return false;
3647 }
3648
3649 static bool
3650 brcmf_sdbrcm_probe_attach(struct brcmf_sdio *bus, u32 regsva)
3651 {
3652 u8 clkctl = 0;
3653 int err = 0;
3654 int reg_addr;
3655 u32 reg_val;
3656 u8 idx;
3657
3658 bus->alp_only = true;
3659
3660 pr_debug("F1 signature read @0x18000000=0x%4x\n",
3661 brcmf_sdio_regrl(bus->sdiodev, SI_ENUM_BASE, NULL));
3662
3663 /*
3664 * Force PLL off until brcmf_sdio_chip_attach()
3665 * programs PLL control regs
3666 */
3667
3668 brcmf_sdio_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
3669 BRCMF_INIT_CLKCTL1, &err);
3670 if (!err)
3671 clkctl = brcmf_sdio_regrb(bus->sdiodev,
3672 SBSDIO_FUNC1_CHIPCLKCSR, &err);
3673
3674 if (err || ((clkctl & ~SBSDIO_AVBITS) != BRCMF_INIT_CLKCTL1)) {
3675 brcmf_dbg(ERROR, "ChipClkCSR access: err %d wrote 0x%02x read 0x%02x\n",
3676 err, BRCMF_INIT_CLKCTL1, clkctl);
3677 goto fail;
3678 }
3679
3680 if (brcmf_sdio_chip_attach(bus->sdiodev, &bus->ci, regsva)) {
3681 brcmf_dbg(ERROR, "brcmf_sdio_chip_attach failed!\n");
3682 goto fail;
3683 }
3684
3685 if (!brcmf_sdbrcm_chipmatch((u16) bus->ci->chip)) {
3686 brcmf_dbg(ERROR, "unsupported chip: 0x%04x\n", bus->ci->chip);
3687 goto fail;
3688 }
3689
3690 brcmf_sdio_chip_drivestrengthinit(bus->sdiodev, bus->ci,
3691 SDIO_DRIVE_STRENGTH);
3692
3693 /* Get info on the SOCRAM cores... */
3694 bus->ramsize = bus->ci->ramsize;
3695 if (!(bus->ramsize)) {
3696 brcmf_dbg(ERROR, "failed to find SOCRAM memory!\n");
3697 goto fail;
3698 }
3699
3700 /* Set core control so an SDIO reset does a backplane reset */
3701 idx = brcmf_sdio_chip_getinfidx(bus->ci, BCMA_CORE_SDIO_DEV);
3702 reg_addr = bus->ci->c_inf[idx].base +
3703 offsetof(struct sdpcmd_regs, corecontrol);
3704 reg_val = brcmf_sdio_regrl(bus->sdiodev, reg_addr, NULL);
3705 brcmf_sdio_regwl(bus->sdiodev, reg_addr, reg_val | CC_BPRESEN, NULL);
3706
3707 brcmu_pktq_init(&bus->txq, (PRIOMASK + 1), TXQLEN);
3708
3709 /* Locate an appropriately-aligned portion of hdrbuf */
3710 bus->rxhdr = (u8 *) roundup((unsigned long)&bus->hdrbuf[0],
3711 BRCMF_SDALIGN);
3712
3713 /* Set the poll and/or interrupt flags */
3714 bus->intr = true;
3715 bus->poll = false;
3716 if (bus->poll)
3717 bus->pollrate = 1;
3718
3719 return true;
3720
3721 fail:
3722 return false;
3723 }
3724
3725 static bool brcmf_sdbrcm_probe_init(struct brcmf_sdio *bus)
3726 {
3727 brcmf_dbg(TRACE, "Enter\n");
3728
3729 /* Disable F2 to clear any intermediate frame state on the dongle */
3730 brcmf_sdio_regwb(bus->sdiodev, SDIO_CCCR_IOEx,
3731 SDIO_FUNC_ENABLE_1, NULL);
3732
3733 bus->sdiodev->bus_if->state = BRCMF_BUS_DOWN;
3734 bus->rxflow = false;
3735
3736 /* Done with backplane-dependent accesses, can drop clock... */
3737 brcmf_sdio_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL);
3738
3739 /* ...and initialize clock/power states */
3740 bus->clkstate = CLK_SDONLY;
3741 bus->idletime = BRCMF_IDLE_INTERVAL;
3742 bus->idleclock = BRCMF_IDLE_ACTIVE;
3743
3744 /* Query the F2 block size, set roundup accordingly */
3745 bus->blocksize = bus->sdiodev->func[2]->cur_blksize;
3746 bus->roundup = min(max_roundup, bus->blocksize);
3747
3748 /* bus module does not support packet chaining */
3749 bus->use_rxchain = false;
3750 bus->sd_rxchain = false;
3751
3752 return true;
3753 }
3754
3755 static int
3756 brcmf_sdbrcm_watchdog_thread(void *data)
3757 {
3758 struct brcmf_sdio *bus = (struct brcmf_sdio *)data;
3759
3760 allow_signal(SIGTERM);
3761 /* Run until signal received */
3762 while (1) {
3763 if (kthread_should_stop())
3764 break;
3765 if (!wait_for_completion_interruptible(&bus->watchdog_wait)) {
3766 brcmf_sdbrcm_bus_watchdog(bus);
3767 /* Count the tick for reference */
3768 bus->sdcnt.tickcnt++;
3769 } else
3770 break;
3771 }
3772 return 0;
3773 }
3774
3775 static void
3776 brcmf_sdbrcm_watchdog(unsigned long data)
3777 {
3778 struct brcmf_sdio *bus = (struct brcmf_sdio *)data;
3779
3780 if (bus->watchdog_tsk) {
3781 complete(&bus->watchdog_wait);
3782 /* Reschedule the watchdog */
3783 if (bus->wd_timer_valid)
3784 mod_timer(&bus->timer,
3785 jiffies + BRCMF_WD_POLL_MS * HZ / 1000);
3786 }
3787 }
3788
3789 static void brcmf_sdbrcm_release_dongle(struct brcmf_sdio *bus)
3790 {
3791 brcmf_dbg(TRACE, "Enter\n");
3792
3793 if (bus->ci) {
3794 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
3795 brcmf_sdbrcm_clkctl(bus, CLK_NONE, false);
3796 brcmf_sdio_chip_detach(&bus->ci);
3797 if (bus->vars && bus->varsz)
3798 kfree(bus->vars);
3799 bus->vars = NULL;
3800 }
3801
3802 brcmf_dbg(TRACE, "Disconnected\n");
3803 }
3804
3805 /* Detach and free everything */
3806 static void brcmf_sdbrcm_release(struct brcmf_sdio *bus)
3807 {
3808 brcmf_dbg(TRACE, "Enter\n");
3809
3810 if (bus) {
3811 /* De-register interrupt handler */
3812 brcmf_sdio_intr_unregister(bus->sdiodev);
3813
3814 cancel_work_sync(&bus->datawork);
3815 destroy_workqueue(bus->brcmf_wq);
3816
3817 if (bus->sdiodev->bus_if->drvr) {
3818 brcmf_detach(bus->sdiodev->dev);
3819 brcmf_sdbrcm_release_dongle(bus);
3820 }
3821
3822 brcmf_sdbrcm_release_malloc(bus);
3823
3824 kfree(bus);
3825 }
3826
3827 brcmf_dbg(TRACE, "Disconnected\n");
3828 }
3829
3830 void *brcmf_sdbrcm_probe(u32 regsva, struct brcmf_sdio_dev *sdiodev)
3831 {
3832 int ret;
3833 struct brcmf_sdio *bus;
3834 struct brcmf_bus_dcmd *dlst;
3835 u32 dngl_txglom;
3836 u32 dngl_txglomalign;
3837 u8 idx;
3838
3839 brcmf_dbg(TRACE, "Enter\n");
3840
3841 /* We make an assumption about address window mappings:
3842 * regsva == SI_ENUM_BASE*/
3843
3844 /* Allocate private bus interface state */
3845 bus = kzalloc(sizeof(struct brcmf_sdio), GFP_ATOMIC);
3846 if (!bus)
3847 goto fail;
3848
3849 bus->sdiodev = sdiodev;
3850 sdiodev->bus = bus;
3851 skb_queue_head_init(&bus->glom);
3852 bus->txbound = BRCMF_TXBOUND;
3853 bus->rxbound = BRCMF_RXBOUND;
3854 bus->txminmax = BRCMF_TXMINMAX;
3855 bus->tx_seq = SDPCM_SEQUENCE_WRAP - 1;
3856
3857 /* attempt to attach to the dongle */
3858 if (!(brcmf_sdbrcm_probe_attach(bus, regsva))) {
3859 brcmf_dbg(ERROR, "brcmf_sdbrcm_probe_attach failed\n");
3860 goto fail;
3861 }
3862
3863 spin_lock_init(&bus->txqlock);
3864 init_waitqueue_head(&bus->ctrl_wait);
3865 init_waitqueue_head(&bus->dcmd_resp_wait);
3866
3867 bus->brcmf_wq = create_singlethread_workqueue("brcmf_wq");
3868 if (bus->brcmf_wq == NULL) {
3869 brcmf_dbg(ERROR, "insufficient memory to create txworkqueue\n");
3870 goto fail;
3871 }
3872 INIT_WORK(&bus->datawork, brcmf_sdio_dataworker);
3873
3874 /* Set up the watchdog timer */
3875 init_timer(&bus->timer);
3876 bus->timer.data = (unsigned long)bus;
3877 bus->timer.function = brcmf_sdbrcm_watchdog;
3878
3879 /* Initialize thread based operation and lock */
3880 sema_init(&bus->sdsem, 1);
3881
3882 /* Initialize watchdog thread */
3883 init_completion(&bus->watchdog_wait);
3884 bus->watchdog_tsk = kthread_run(brcmf_sdbrcm_watchdog_thread,
3885 bus, "brcmf_watchdog");
3886 if (IS_ERR(bus->watchdog_tsk)) {
3887 pr_warn("brcmf_watchdog thread failed to start\n");
3888 bus->watchdog_tsk = NULL;
3889 }
3890 /* Initialize DPC thread */
3891 INIT_LIST_HEAD(&bus->dpc_tsklst);
3892 spin_lock_init(&bus->dpc_tl_lock);
3893
3894 /* Assign bus interface call back */
3895 bus->sdiodev->bus_if->brcmf_bus_stop = brcmf_sdbrcm_bus_stop;
3896 bus->sdiodev->bus_if->brcmf_bus_init = brcmf_sdbrcm_bus_init;
3897 bus->sdiodev->bus_if->brcmf_bus_txdata = brcmf_sdbrcm_bus_txdata;
3898 bus->sdiodev->bus_if->brcmf_bus_txctl = brcmf_sdbrcm_bus_txctl;
3899 bus->sdiodev->bus_if->brcmf_bus_rxctl = brcmf_sdbrcm_bus_rxctl;
3900 /* Attach to the brcmf/OS/network interface */
3901 ret = brcmf_attach(SDPCM_RESERVE, bus->sdiodev->dev);
3902 if (ret != 0) {
3903 brcmf_dbg(ERROR, "brcmf_attach failed\n");
3904 goto fail;
3905 }
3906
3907 /* Allocate buffers */
3908 if (!(brcmf_sdbrcm_probe_malloc(bus))) {
3909 brcmf_dbg(ERROR, "brcmf_sdbrcm_probe_malloc failed\n");
3910 goto fail;
3911 }
3912
3913 if (!(brcmf_sdbrcm_probe_init(bus))) {
3914 brcmf_dbg(ERROR, "brcmf_sdbrcm_probe_init failed\n");
3915 goto fail;
3916 }
3917
3918 brcmf_sdio_debugfs_create(bus);
3919 brcmf_dbg(INFO, "completed!!\n");
3920
3921 /* sdio bus core specific dcmd */
3922 idx = brcmf_sdio_chip_getinfidx(bus->ci, BCMA_CORE_SDIO_DEV);
3923 dlst = kzalloc(sizeof(struct brcmf_bus_dcmd), GFP_KERNEL);
3924 if (dlst) {
3925 if (bus->ci->c_inf[idx].rev < 12) {
3926 /* for sdio core rev < 12, disable txgloming */
3927 dngl_txglom = 0;
3928 dlst->name = "bus:txglom";
3929 dlst->param = (char *)&dngl_txglom;
3930 dlst->param_len = sizeof(u32);
3931 } else {
3932 /* otherwise, set txglomalign */
3933 dngl_txglomalign = bus->sdiodev->bus_if->align;
3934 dlst->name = "bus:txglomalign";
3935 dlst->param = (char *)&dngl_txglomalign;
3936 dlst->param_len = sizeof(u32);
3937 }
3938 list_add(&dlst->list, &bus->sdiodev->bus_if->dcmd_list);
3939 }
3940
3941 /* if firmware path present try to download and bring up bus */
3942 ret = brcmf_bus_start(bus->sdiodev->dev);
3943 if (ret != 0) {
3944 if (ret == -ENOLINK) {
3945 brcmf_dbg(ERROR, "dongle is not responding\n");
3946 goto fail;
3947 }
3948 }
3949
3950 return bus;
3951
3952 fail:
3953 brcmf_sdbrcm_release(bus);
3954 return NULL;
3955 }
3956
3957 void brcmf_sdbrcm_disconnect(void *ptr)
3958 {
3959 struct brcmf_sdio *bus = (struct brcmf_sdio *)ptr;
3960
3961 brcmf_dbg(TRACE, "Enter\n");
3962
3963 if (bus)
3964 brcmf_sdbrcm_release(bus);
3965
3966 brcmf_dbg(TRACE, "Disconnected\n");
3967 }
3968
3969 void
3970 brcmf_sdbrcm_wd_timer(struct brcmf_sdio *bus, uint wdtick)
3971 {
3972 /* Totally stop the timer */
3973 if (!wdtick && bus->wd_timer_valid) {
3974 del_timer_sync(&bus->timer);
3975 bus->wd_timer_valid = false;
3976 bus->save_ms = wdtick;
3977 return;
3978 }
3979
3980 /* don't start the wd until fw is loaded */
3981 if (bus->sdiodev->bus_if->state == BRCMF_BUS_DOWN)
3982 return;
3983
3984 if (wdtick) {
3985 if (bus->save_ms != BRCMF_WD_POLL_MS) {
3986 if (bus->wd_timer_valid)
3987 /* Stop timer and restart at new value */
3988 del_timer_sync(&bus->timer);
3989
3990 /* Create timer again when watchdog period is
3991 dynamically changed or in the first instance
3992 */
3993 bus->timer.expires =
3994 jiffies + BRCMF_WD_POLL_MS * HZ / 1000;
3995 add_timer(&bus->timer);
3996
3997 } else {
3998 /* Re arm the timer, at last watchdog period */
3999 mod_timer(&bus->timer,
4000 jiffies + BRCMF_WD_POLL_MS * HZ / 1000);
4001 }
4002
4003 bus->wd_timer_valid = true;
4004 bus->save_ms = wdtick;
4005 }
4006 }
Linux kernel - Deliverables
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