2 * Copyright (c) 2010 Broadcom Corporation
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/types.h>
18 #include <linux/kernel.h>
19 #include <linux/kthread.h>
20 #include <linux/printk.h>
21 #include <linux/pci_ids.h>
22 #include <linux/netdevice.h>
23 #include <linux/interrupt.h>
24 #include <linux/sched.h>
25 #include <linux/mmc/sdio.h>
26 #include <linux/mmc/sdio_func.h>
27 #include <linux/mmc/card.h>
28 #include <linux/semaphore.h>
29 #include <linux/firmware.h>
30 #include <linux/module.h>
31 #include <asm/unaligned.h>
33 #include <brcmu_wifi.h>
34 #include <brcmu_utils.h>
35 #include <brcm_hw_ids.h>
37 #include "sdio_host.h"
38 #include "sdio_chip.h"
40 #define DCMD_RESP_TIMEOUT 2000 /* In milli second */
44 #define BRCMF_TRAP_INFO_SIZE 80
46 #define CBUF_LEN (128)
49 __le32 buf
; /* Can't be pointer on (64-bit) hosts */
52 char *_buf_compat
; /* Redundant pointer for backward compat. */
57 * When there is no UART (e.g. Quickturn),
58 * the host should write a complete
59 * input line directly into cbuf and then write
60 * the length into vcons_in.
61 * This may also be used when there is a real UART
62 * (at risk of conflicting with
63 * the real UART). vcons_out is currently unused.
68 /* Output (logging) buffer
69 * Console output is written to a ring buffer log_buf at index log_idx.
70 * The host may read the output when it sees log_idx advance.
71 * Output will be lost if the output wraps around faster than the host
74 struct rte_log_le log_le
;
76 /* Console input line buffer
77 * Characters are read one at a time into cbuf
78 * until <CR> is received, then
79 * the buffer is processed as a command line.
80 * Also used for virtual UART.
87 #include <chipcommon.h>
91 #include "dhd_proto.h"
95 #define TXQLEN 2048 /* bulk tx queue length */
96 #define TXHI (TXQLEN - 256) /* turn on flow control above TXHI */
97 #define TXLOW (TXHI - 256) /* turn off flow control below TXLOW */
100 #define TXRETRIES 2 /* # of retries for tx frames */
102 #define BRCMF_RXBOUND 50 /* Default for max rx frames in
105 #define BRCMF_TXBOUND 20 /* Default for max tx frames in
108 #define BRCMF_TXMINMAX 1 /* Max tx frames if rx still pending */
110 #define MEMBLOCK 2048 /* Block size used for downloading
112 #define MAX_DATA_BUF (32 * 1024) /* Must be large enough to hold
113 biggest possible glom */
115 #define BRCMF_FIRSTREAD (1 << 6)
118 /* SBSDIO_DEVICE_CTL */
120 /* 1: device will assert busy signal when receiving CMD53 */
121 #define SBSDIO_DEVCTL_SETBUSY 0x01
122 /* 1: assertion of sdio interrupt is synchronous to the sdio clock */
123 #define SBSDIO_DEVCTL_SPI_INTR_SYNC 0x02
124 /* 1: mask all interrupts to host except the chipActive (rev 8) */
125 #define SBSDIO_DEVCTL_CA_INT_ONLY 0x04
126 /* 1: isolate internal sdio signals, put external pads in tri-state; requires
127 * sdio bus power cycle to clear (rev 9) */
128 #define SBSDIO_DEVCTL_PADS_ISO 0x08
129 /* Force SD->SB reset mapping (rev 11) */
130 #define SBSDIO_DEVCTL_SB_RST_CTL 0x30
131 /* Determined by CoreControl bit */
132 #define SBSDIO_DEVCTL_RST_CORECTL 0x00
133 /* Force backplane reset */
134 #define SBSDIO_DEVCTL_RST_BPRESET 0x10
135 /* Force no backplane reset */
136 #define SBSDIO_DEVCTL_RST_NOBPRESET 0x20
138 /* direct(mapped) cis space */
140 /* MAPPED common CIS address */
141 #define SBSDIO_CIS_BASE_COMMON 0x1000
142 /* maximum bytes in one CIS */
143 #define SBSDIO_CIS_SIZE_LIMIT 0x200
144 /* cis offset addr is < 17 bits */
145 #define SBSDIO_CIS_OFT_ADDR_MASK 0x1FFFF
147 /* manfid tuple length, include tuple, link bytes */
148 #define SBSDIO_CIS_MANFID_TUPLE_LEN 6
151 #define I_SMB_SW0 (1 << 0) /* To SB Mail S/W interrupt 0 */
152 #define I_SMB_SW1 (1 << 1) /* To SB Mail S/W interrupt 1 */
153 #define I_SMB_SW2 (1 << 2) /* To SB Mail S/W interrupt 2 */
154 #define I_SMB_SW3 (1 << 3) /* To SB Mail S/W interrupt 3 */
155 #define I_SMB_SW_MASK 0x0000000f /* To SB Mail S/W interrupts mask */
156 #define I_SMB_SW_SHIFT 0 /* To SB Mail S/W interrupts shift */
157 #define I_HMB_SW0 (1 << 4) /* To Host Mail S/W interrupt 0 */
158 #define I_HMB_SW1 (1 << 5) /* To Host Mail S/W interrupt 1 */
159 #define I_HMB_SW2 (1 << 6) /* To Host Mail S/W interrupt 2 */
160 #define I_HMB_SW3 (1 << 7) /* To Host Mail S/W interrupt 3 */
161 #define I_HMB_SW_MASK 0x000000f0 /* To Host Mail S/W interrupts mask */
162 #define I_HMB_SW_SHIFT 4 /* To Host Mail S/W interrupts shift */
163 #define I_WR_OOSYNC (1 << 8) /* Write Frame Out Of Sync */
164 #define I_RD_OOSYNC (1 << 9) /* Read Frame Out Of Sync */
165 #define I_PC (1 << 10) /* descriptor error */
166 #define I_PD (1 << 11) /* data error */
167 #define I_DE (1 << 12) /* Descriptor protocol Error */
168 #define I_RU (1 << 13) /* Receive descriptor Underflow */
169 #define I_RO (1 << 14) /* Receive fifo Overflow */
170 #define I_XU (1 << 15) /* Transmit fifo Underflow */
171 #define I_RI (1 << 16) /* Receive Interrupt */
172 #define I_BUSPWR (1 << 17) /* SDIO Bus Power Change (rev 9) */
173 #define I_XMTDATA_AVAIL (1 << 23) /* bits in fifo */
174 #define I_XI (1 << 24) /* Transmit Interrupt */
175 #define I_RF_TERM (1 << 25) /* Read Frame Terminate */
176 #define I_WF_TERM (1 << 26) /* Write Frame Terminate */
177 #define I_PCMCIA_XU (1 << 27) /* PCMCIA Transmit FIFO Underflow */
178 #define I_SBINT (1 << 28) /* sbintstatus Interrupt */
179 #define I_CHIPACTIVE (1 << 29) /* chip from doze to active state */
180 #define I_SRESET (1 << 30) /* CCCR RES interrupt */
181 #define I_IOE2 (1U << 31) /* CCCR IOE2 Bit Changed */
182 #define I_ERRORS (I_PC | I_PD | I_DE | I_RU | I_RO | I_XU)
183 #define I_DMA (I_RI | I_XI | I_ERRORS)
186 #define CC_CISRDY (1 << 0) /* CIS Ready */
187 #define CC_BPRESEN (1 << 1) /* CCCR RES signal */
188 #define CC_F2RDY (1 << 2) /* set CCCR IOR2 bit */
189 #define CC_CLRPADSISO (1 << 3) /* clear SDIO pads isolation */
190 #define CC_XMTDATAAVAIL_MODE (1 << 4)
191 #define CC_XMTDATAAVAIL_CTRL (1 << 5)
194 #define SFC_RF_TERM (1 << 0) /* Read Frame Terminate */
195 #define SFC_WF_TERM (1 << 1) /* Write Frame Terminate */
196 #define SFC_CRC4WOOS (1 << 2) /* CRC error for write out of sync */
197 #define SFC_ABORTALL (1 << 3) /* Abort all in-progress frames */
200 #define SDPCM_FRAMETAG_LEN 4 /* 2 bytes len, 2 bytes check val */
202 /* Total length of frame header for dongle protocol */
203 #define SDPCM_HDRLEN (SDPCM_FRAMETAG_LEN + SDPCM_SWHEADER_LEN)
204 #define SDPCM_RESERVE (SDPCM_HDRLEN + BRCMF_SDALIGN)
207 * Software allocation of To SB Mailbox resources
210 /* tosbmailbox bits corresponding to intstatus bits */
211 #define SMB_NAK (1 << 0) /* Frame NAK */
212 #define SMB_INT_ACK (1 << 1) /* Host Interrupt ACK */
213 #define SMB_USE_OOB (1 << 2) /* Use OOB Wakeup */
214 #define SMB_DEV_INT (1 << 3) /* Miscellaneous Interrupt */
216 /* tosbmailboxdata */
217 #define SMB_DATA_VERSION_SHIFT 16 /* host protocol version */
220 * Software allocation of To Host Mailbox resources
224 #define I_HMB_FC_STATE I_HMB_SW0 /* Flow Control State */
225 #define I_HMB_FC_CHANGE I_HMB_SW1 /* Flow Control State Changed */
226 #define I_HMB_FRAME_IND I_HMB_SW2 /* Frame Indication */
227 #define I_HMB_HOST_INT I_HMB_SW3 /* Miscellaneous Interrupt */
229 /* tohostmailboxdata */
230 #define HMB_DATA_NAKHANDLED 1 /* retransmit NAK'd frame */
231 #define HMB_DATA_DEVREADY 2 /* talk to host after enable */
232 #define HMB_DATA_FC 4 /* per prio flowcontrol update flag */
233 #define HMB_DATA_FWREADY 8 /* fw ready for protocol activity */
235 #define HMB_DATA_FCDATA_MASK 0xff000000
236 #define HMB_DATA_FCDATA_SHIFT 24
238 #define HMB_DATA_VERSION_MASK 0x00ff0000
239 #define HMB_DATA_VERSION_SHIFT 16
242 * Software-defined protocol header
245 /* Current protocol version */
246 #define SDPCM_PROT_VERSION 4
248 /* SW frame header */
249 #define SDPCM_PACKET_SEQUENCE(p) (((u8 *)p)[0] & 0xff)
251 #define SDPCM_CHANNEL_MASK 0x00000f00
252 #define SDPCM_CHANNEL_SHIFT 8
253 #define SDPCM_PACKET_CHANNEL(p) (((u8 *)p)[1] & 0x0f)
255 #define SDPCM_NEXTLEN_OFFSET 2
257 /* Data Offset from SOF (HW Tag, SW Tag, Pad) */
258 #define SDPCM_DOFFSET_OFFSET 3 /* Data Offset */
259 #define SDPCM_DOFFSET_VALUE(p) (((u8 *)p)[SDPCM_DOFFSET_OFFSET] & 0xff)
260 #define SDPCM_DOFFSET_MASK 0xff000000
261 #define SDPCM_DOFFSET_SHIFT 24
262 #define SDPCM_FCMASK_OFFSET 4 /* Flow control */
263 #define SDPCM_FCMASK_VALUE(p) (((u8 *)p)[SDPCM_FCMASK_OFFSET] & 0xff)
264 #define SDPCM_WINDOW_OFFSET 5 /* Credit based fc */
265 #define SDPCM_WINDOW_VALUE(p) (((u8 *)p)[SDPCM_WINDOW_OFFSET] & 0xff)
267 #define SDPCM_SWHEADER_LEN 8 /* SW header is 64 bits */
269 /* logical channel numbers */
270 #define SDPCM_CONTROL_CHANNEL 0 /* Control channel Id */
271 #define SDPCM_EVENT_CHANNEL 1 /* Asyc Event Indication Channel Id */
272 #define SDPCM_DATA_CHANNEL 2 /* Data Xmit/Recv Channel Id */
273 #define SDPCM_GLOM_CHANNEL 3 /* For coalesced packets */
274 #define SDPCM_TEST_CHANNEL 15 /* Reserved for test/debug packets */
276 #define SDPCM_SEQUENCE_WRAP 256 /* wrap-around val for 8bit frame seq */
278 #define SDPCM_GLOMDESC(p) (((u8 *)p)[1] & 0x80)
281 * Shared structure between dongle and the host.
282 * The structure contains pointers to trap or assert information.
284 #define SDPCM_SHARED_VERSION 0x0002
285 #define SDPCM_SHARED_VERSION_MASK 0x00FF
286 #define SDPCM_SHARED_ASSERT_BUILT 0x0100
287 #define SDPCM_SHARED_ASSERT 0x0200
288 #define SDPCM_SHARED_TRAP 0x0400
290 /* Space for header read, limit for data packets */
291 #define MAX_HDR_READ (1 << 6)
292 #define MAX_RX_DATASZ 2048
294 /* Maximum milliseconds to wait for F2 to come up */
295 #define BRCMF_WAIT_F2RDY 3000
297 /* Bump up limit on waiting for HT to account for first startup;
298 * if the image is doing a CRC calculation before programming the PMU
299 * for HT availability, it could take a couple hundred ms more, so
300 * max out at a 1 second (1000000us).
302 #undef PMU_MAX_TRANSITION_DLY
303 #define PMU_MAX_TRANSITION_DLY 1000000
305 /* Value for ChipClockCSR during initial setup */
306 #define BRCMF_INIT_CLKCTL1 (SBSDIO_FORCE_HW_CLKREQ_OFF | \
307 SBSDIO_ALP_AVAIL_REQ)
309 /* Flags for SDH calls */
310 #define F2SYNC (SDIO_REQ_4BYTE | SDIO_REQ_FIXED)
313 * Conversion of 802.1D priority to precedence level
315 static uint
prio2prec(u32 prio
)
317 return (prio
== PRIO_8021D_NONE
|| prio
== PRIO_8021D_BE
) ?
323 u32 corecontrol
; /* 0x00, rev8 */
324 u32 corestatus
; /* rev8 */
326 u32 biststatus
; /* rev8 */
329 u16 pcmciamesportaladdr
; /* 0x010, rev8 */
331 u16 pcmciamesportalmask
; /* rev8 */
333 u16 pcmciawrframebc
; /* rev8 */
335 u16 pcmciaunderflowtimer
; /* rev8 */
339 u32 intstatus
; /* 0x020, rev8 */
340 u32 hostintmask
; /* rev8 */
341 u32 intmask
; /* rev8 */
342 u32 sbintstatus
; /* rev8 */
343 u32 sbintmask
; /* rev8 */
344 u32 funcintmask
; /* rev4 */
346 u32 tosbmailbox
; /* 0x040, rev8 */
347 u32 tohostmailbox
; /* rev8 */
348 u32 tosbmailboxdata
; /* rev8 */
349 u32 tohostmailboxdata
; /* rev8 */
351 /* synchronized access to registers in SDIO clock domain */
352 u32 sdioaccess
; /* 0x050, rev8 */
355 /* PCMCIA frame control */
356 u8 pcmciaframectrl
; /* 0x060, rev8 */
358 u8 pcmciawatermark
; /* rev8 */
361 /* interrupt batching control */
362 u32 intrcvlazy
; /* 0x100, rev8 */
366 u32 cmd52rd
; /* 0x110, rev8 */
367 u32 cmd52wr
; /* rev8 */
368 u32 cmd53rd
; /* rev8 */
369 u32 cmd53wr
; /* rev8 */
370 u32 abort
; /* rev8 */
371 u32 datacrcerror
; /* rev8 */
372 u32 rdoutofsync
; /* rev8 */
373 u32 wroutofsync
; /* rev8 */
374 u32 writebusy
; /* rev8 */
375 u32 readwait
; /* rev8 */
376 u32 readterm
; /* rev8 */
377 u32 writeterm
; /* rev8 */
379 u32 clockctlstatus
; /* rev8 */
382 u32 PAD
[128]; /* DMA engines */
384 /* SDIO/PCMCIA CIS region */
385 char cis
[512]; /* 0x400-0x5ff, rev6 */
387 /* PCMCIA function control registers */
388 char pcmciafcr
[256]; /* 0x600-6ff, rev6 */
391 /* PCMCIA backplane access */
392 u16 backplanecsr
; /* 0x76E, rev6 */
393 u16 backplaneaddr0
; /* rev6 */
394 u16 backplaneaddr1
; /* rev6 */
395 u16 backplaneaddr2
; /* rev6 */
396 u16 backplaneaddr3
; /* rev6 */
397 u16 backplanedata0
; /* rev6 */
398 u16 backplanedata1
; /* rev6 */
399 u16 backplanedata2
; /* rev6 */
400 u16 backplanedata3
; /* rev6 */
403 /* sprom "size" & "blank" info */
404 u16 spromstatus
; /* 0x7BE, rev2 */
411 /* Device console log buffer state */
412 struct brcmf_console
{
413 uint count
; /* Poll interval msec counter */
414 uint log_addr
; /* Log struct address (fixed) */
415 struct rte_log_le log_le
; /* Log struct (host copy) */
416 uint bufsize
; /* Size of log buffer */
417 u8
*buf
; /* Log buffer (host copy) */
418 uint last
; /* Last buffer read index */
422 struct sdpcm_shared
{
426 u32 assert_file_addr
;
428 u32 console_addr
; /* Address of struct rte_console */
433 struct sdpcm_shared_le
{
436 __le32 assert_exp_addr
;
437 __le32 assert_file_addr
;
439 __le32 console_addr
; /* Address of struct rte_console */
440 __le32 msgtrace_addr
;
445 /* misc chip info needed by some of the routines */
446 /* Private data for SDIO bus interaction */
448 struct brcmf_pub
*drvr
;
450 struct brcmf_sdio_dev
*sdiodev
; /* sdio device handler */
451 struct chip_info
*ci
; /* Chip info struct */
452 char *vars
; /* Variables (from CIS and/or other) */
453 uint varsz
; /* Size of variables buffer */
455 u32 ramsize
; /* Size of RAM in SOCRAM (bytes) */
457 u32 hostintmask
; /* Copy of Host Interrupt Mask */
458 u32 intstatus
; /* Intstatus bits (events) pending */
459 bool dpc_sched
; /* Indicates DPC schedule (intrpt rcvd) */
460 bool fcstate
; /* State of dongle flow-control */
462 uint blocksize
; /* Block size of SDIO transfers */
463 uint roundup
; /* Max roundup limit */
465 struct pktq txq
; /* Queue length used for flow-control */
466 u8 flowcontrol
; /* per prio flow control bitmask */
467 u8 tx_seq
; /* Transmit sequence number (next) */
468 u8 tx_max
; /* Maximum transmit sequence allowed */
470 u8 hdrbuf
[MAX_HDR_READ
+ BRCMF_SDALIGN
];
471 u8
*rxhdr
; /* Header of current rx frame (in hdrbuf) */
472 u16 nextlen
; /* Next Read Len from last header */
473 u8 rx_seq
; /* Receive sequence number (expected) */
474 bool rxskip
; /* Skip receive (awaiting NAK ACK) */
476 uint rxbound
; /* Rx frames to read before resched */
477 uint txbound
; /* Tx frames to send before resched */
480 struct sk_buff
*glomd
; /* Packet containing glomming descriptor */
481 struct sk_buff_head glom
; /* Packet list for glommed superframe */
482 uint glomerr
; /* Glom packet read errors */
484 u8
*rxbuf
; /* Buffer for receiving control packets */
485 uint rxblen
; /* Allocated length of rxbuf */
486 u8
*rxctl
; /* Aligned pointer into rxbuf */
487 u8
*databuf
; /* Buffer for receiving big glom packet */
488 u8
*dataptr
; /* Aligned pointer into databuf */
489 uint rxlen
; /* Length of valid data in buffer */
491 u8 sdpcm_ver
; /* Bus protocol reported by dongle */
493 bool intr
; /* Use interrupts */
494 bool poll
; /* Use polling */
495 bool ipend
; /* Device interrupt is pending */
496 uint intrcount
; /* Count of device interrupt callbacks */
497 uint lastintrs
; /* Count as of last watchdog timer */
498 uint spurious
; /* Count of spurious interrupts */
499 uint pollrate
; /* Ticks between device polls */
500 uint polltick
; /* Tick counter */
501 uint pollcnt
; /* Count of active polls */
504 uint console_interval
;
505 struct brcmf_console console
; /* Console output polling support */
506 uint console_addr
; /* Console address from shared struct */
509 uint regfails
; /* Count of R_REG failures */
511 uint clkstate
; /* State of sd and backplane clock(s) */
512 bool activity
; /* Activity flag for clock down */
513 s32 idletime
; /* Control for activity timeout */
514 s32 idlecount
; /* Activity timeout counter */
515 s32 idleclock
; /* How to set bus driver when idle */
517 bool use_rxchain
; /* If brcmf should use PKT chains */
518 bool sleeping
; /* Is SDIO bus sleeping? */
519 bool rxflow_mode
; /* Rx flow control mode */
520 bool rxflow
; /* Is rx flow control on */
521 bool alp_only
; /* Don't use HT clock (ALP only) */
522 /* Field to decide if rx of control frames happen in rxbuf or lb-pool */
525 /* Some additional counters */
526 uint tx_sderrs
; /* Count of tx attempts with sd errors */
527 uint fcqueued
; /* Tx packets that got queued */
528 uint rxrtx
; /* Count of rtx requests (NAK to dongle) */
529 uint rx_toolong
; /* Receive frames too long to receive */
530 uint rxc_errors
; /* SDIO errors when reading control frames */
531 uint rx_hdrfail
; /* SDIO errors on header reads */
532 uint rx_badhdr
; /* Bad received headers (roosync?) */
533 uint rx_badseq
; /* Mismatched rx sequence number */
534 uint fc_rcvd
; /* Number of flow-control events received */
535 uint fc_xoff
; /* Number which turned on flow-control */
536 uint fc_xon
; /* Number which turned off flow-control */
537 uint rxglomfail
; /* Failed deglom attempts */
538 uint rxglomframes
; /* Number of glom frames (superframes) */
539 uint rxglompkts
; /* Number of packets from glom frames */
540 uint f2rxhdrs
; /* Number of header reads */
541 uint f2rxdata
; /* Number of frame data reads */
542 uint f2txdata
; /* Number of f2 frame writes */
543 uint f1regdata
; /* Number of f1 register accesses */
547 bool ctrl_frame_stat
;
550 wait_queue_head_t ctrl_wait
;
551 wait_queue_head_t dcmd_resp_wait
;
553 struct timer_list timer
;
554 struct completion watchdog_wait
;
555 struct task_struct
*watchdog_tsk
;
559 struct task_struct
*dpc_tsk
;
560 struct completion dpc_wait
;
562 struct semaphore sdsem
;
565 const struct firmware
*firmware
;
573 #define CLK_PENDING 2 /* Not used yet */
577 static int qcount
[NUMPRIO
];
578 static int tx_packets
[NUMPRIO
];
581 #define SDIO_DRIVE_STRENGTH 6 /* in milliamps */
583 #define RETRYCHAN(chan) ((chan) == SDPCM_EVENT_CHANNEL)
585 /* Retry count for register access failures */
586 static const uint retry_limit
= 2;
588 /* Limit on rounding up frames */
589 static const uint max_roundup
= 512;
593 static void pkt_align(struct sk_buff
*p
, int len
, int align
)
596 datalign
= (unsigned long)(p
->data
);
597 datalign
= roundup(datalign
, (align
)) - datalign
;
599 skb_pull(p
, datalign
);
603 /* To check if there's window offered */
604 static bool data_ok(struct brcmf_bus
*bus
)
606 return (u8
)(bus
->tx_max
- bus
->tx_seq
) != 0 &&
607 ((u8
)(bus
->tx_max
- bus
->tx_seq
) & 0x80) == 0;
611 * Reads a register in the SDIO hardware block. This block occupies a series of
612 * adresses on the 32 bit backplane bus.
615 r_sdreg32(struct brcmf_bus
*bus
, u32
*regvar
, u32 reg_offset
, u32
*retryvar
)
619 *regvar
= brcmf_sdcard_reg_read(bus
->sdiodev
,
620 bus
->ci
->buscorebase
+ reg_offset
, sizeof(u32
));
621 } while (brcmf_sdcard_regfail(bus
->sdiodev
) &&
622 (++(*retryvar
) <= retry_limit
));
624 bus
->regfails
+= (*retryvar
-1);
625 if (*retryvar
> retry_limit
) {
626 brcmf_dbg(ERROR
, "FAILED READ %Xh\n", reg_offset
);
633 w_sdreg32(struct brcmf_bus
*bus
, u32 regval
, u32 reg_offset
, u32
*retryvar
)
637 brcmf_sdcard_reg_write(bus
->sdiodev
,
638 bus
->ci
->buscorebase
+ reg_offset
,
639 sizeof(u32
), regval
);
640 } while (brcmf_sdcard_regfail(bus
->sdiodev
) &&
641 (++(*retryvar
) <= retry_limit
));
643 bus
->regfails
+= (*retryvar
-1);
644 if (*retryvar
> retry_limit
)
645 brcmf_dbg(ERROR
, "FAILED REGISTER WRITE %Xh\n",
650 #define PKT_AVAILABLE() (intstatus & I_HMB_FRAME_IND)
652 #define HOSTINTMASK (I_HMB_SW_MASK | I_CHIPACTIVE)
654 /* Packet free applicable unconditionally for sdio and sdspi.
655 * Conditional if bufpool was present for gspi bus.
657 static void brcmf_sdbrcm_pktfree2(struct brcmf_bus
*bus
, struct sk_buff
*pkt
)
660 brcmu_pkt_buf_free_skb(pkt
);
663 /* Turn backplane clock on or off */
664 static int brcmf_sdbrcm_htclk(struct brcmf_bus
*bus
, bool on
, bool pendok
)
667 u8 clkctl
, clkreq
, devctl
;
668 unsigned long timeout
;
670 brcmf_dbg(TRACE
, "Enter\n");
675 /* Request HT Avail */
677 bus
->alp_only
? SBSDIO_ALP_AVAIL_REQ
: SBSDIO_HT_AVAIL_REQ
;
679 brcmf_sdcard_cfg_write(bus
->sdiodev
, SDIO_FUNC_1
,
680 SBSDIO_FUNC1_CHIPCLKCSR
, clkreq
, &err
);
682 brcmf_dbg(ERROR
, "HT Avail request error: %d\n", err
);
686 if (pendok
&& ((bus
->ci
->buscoretype
== PCMCIA_CORE_ID
)
687 && (bus
->ci
->buscorerev
== 9))) {
689 r_sdreg32(bus
, &dummy
,
690 offsetof(struct sdpcmd_regs
, clockctlstatus
),
694 /* Check current status */
695 clkctl
= brcmf_sdcard_cfg_read(bus
->sdiodev
, SDIO_FUNC_1
,
696 SBSDIO_FUNC1_CHIPCLKCSR
, &err
);
698 brcmf_dbg(ERROR
, "HT Avail read error: %d\n", err
);
702 /* Go to pending and await interrupt if appropriate */
703 if (!SBSDIO_CLKAV(clkctl
, bus
->alp_only
) && pendok
) {
704 /* Allow only clock-available interrupt */
705 devctl
= brcmf_sdcard_cfg_read(bus
->sdiodev
,
707 SBSDIO_DEVICE_CTL
, &err
);
709 brcmf_dbg(ERROR
, "Devctl error setting CA: %d\n",
714 devctl
|= SBSDIO_DEVCTL_CA_INT_ONLY
;
715 brcmf_sdcard_cfg_write(bus
->sdiodev
, SDIO_FUNC_1
,
716 SBSDIO_DEVICE_CTL
, devctl
, &err
);
717 brcmf_dbg(INFO
, "CLKCTL: set PENDING\n");
718 bus
->clkstate
= CLK_PENDING
;
721 } else if (bus
->clkstate
== CLK_PENDING
) {
722 /* Cancel CA-only interrupt filter */
724 brcmf_sdcard_cfg_read(bus
->sdiodev
, SDIO_FUNC_1
,
725 SBSDIO_DEVICE_CTL
, &err
);
726 devctl
&= ~SBSDIO_DEVCTL_CA_INT_ONLY
;
727 brcmf_sdcard_cfg_write(bus
->sdiodev
, SDIO_FUNC_1
,
728 SBSDIO_DEVICE_CTL
, devctl
, &err
);
731 /* Otherwise, wait here (polling) for HT Avail */
733 msecs_to_jiffies(PMU_MAX_TRANSITION_DLY
/1000);
734 while (!SBSDIO_CLKAV(clkctl
, bus
->alp_only
)) {
735 clkctl
= brcmf_sdcard_cfg_read(bus
->sdiodev
,
737 SBSDIO_FUNC1_CHIPCLKCSR
,
739 if (time_after(jiffies
, timeout
))
742 usleep_range(5000, 10000);
745 brcmf_dbg(ERROR
, "HT Avail request error: %d\n", err
);
748 if (!SBSDIO_CLKAV(clkctl
, bus
->alp_only
)) {
749 brcmf_dbg(ERROR
, "HT Avail timeout (%d): clkctl 0x%02x\n",
750 PMU_MAX_TRANSITION_DLY
, clkctl
);
754 /* Mark clock available */
755 bus
->clkstate
= CLK_AVAIL
;
756 brcmf_dbg(INFO
, "CLKCTL: turned ON\n");
759 if (bus
->alp_only
!= true) {
760 if (SBSDIO_ALPONLY(clkctl
))
761 brcmf_dbg(ERROR
, "HT Clock should be on\n");
763 #endif /* defined (BCMDBG) */
765 bus
->activity
= true;
769 if (bus
->clkstate
== CLK_PENDING
) {
770 /* Cancel CA-only interrupt filter */
771 devctl
= brcmf_sdcard_cfg_read(bus
->sdiodev
,
773 SBSDIO_DEVICE_CTL
, &err
);
774 devctl
&= ~SBSDIO_DEVCTL_CA_INT_ONLY
;
775 brcmf_sdcard_cfg_write(bus
->sdiodev
, SDIO_FUNC_1
,
776 SBSDIO_DEVICE_CTL
, devctl
, &err
);
779 bus
->clkstate
= CLK_SDONLY
;
780 brcmf_sdcard_cfg_write(bus
->sdiodev
, SDIO_FUNC_1
,
781 SBSDIO_FUNC1_CHIPCLKCSR
, clkreq
, &err
);
782 brcmf_dbg(INFO
, "CLKCTL: turned OFF\n");
784 brcmf_dbg(ERROR
, "Failed access turning clock off: %d\n",
792 /* Change idle/active SD state */
793 static int brcmf_sdbrcm_sdclk(struct brcmf_bus
*bus
, bool on
)
795 brcmf_dbg(TRACE
, "Enter\n");
798 bus
->clkstate
= CLK_SDONLY
;
800 bus
->clkstate
= CLK_NONE
;
805 /* Transition SD and backplane clock readiness */
806 static int brcmf_sdbrcm_clkctl(struct brcmf_bus
*bus
, uint target
, bool pendok
)
809 uint oldstate
= bus
->clkstate
;
812 brcmf_dbg(TRACE
, "Enter\n");
814 /* Early exit if we're already there */
815 if (bus
->clkstate
== target
) {
816 if (target
== CLK_AVAIL
) {
817 brcmf_sdbrcm_wd_timer(bus
, BRCMF_WD_POLL_MS
);
818 bus
->activity
= true;
825 /* Make sure SD clock is available */
826 if (bus
->clkstate
== CLK_NONE
)
827 brcmf_sdbrcm_sdclk(bus
, true);
828 /* Now request HT Avail on the backplane */
829 brcmf_sdbrcm_htclk(bus
, true, pendok
);
830 brcmf_sdbrcm_wd_timer(bus
, BRCMF_WD_POLL_MS
);
831 bus
->activity
= true;
835 /* Remove HT request, or bring up SD clock */
836 if (bus
->clkstate
== CLK_NONE
)
837 brcmf_sdbrcm_sdclk(bus
, true);
838 else if (bus
->clkstate
== CLK_AVAIL
)
839 brcmf_sdbrcm_htclk(bus
, false, false);
841 brcmf_dbg(ERROR
, "request for %d -> %d\n",
842 bus
->clkstate
, target
);
843 brcmf_sdbrcm_wd_timer(bus
, BRCMF_WD_POLL_MS
);
847 /* Make sure to remove HT request */
848 if (bus
->clkstate
== CLK_AVAIL
)
849 brcmf_sdbrcm_htclk(bus
, false, false);
850 /* Now remove the SD clock */
851 brcmf_sdbrcm_sdclk(bus
, false);
852 brcmf_sdbrcm_wd_timer(bus
, 0);
856 brcmf_dbg(INFO
, "%d -> %d\n", oldstate
, bus
->clkstate
);
862 static int brcmf_sdbrcm_bussleep(struct brcmf_bus
*bus
, bool sleep
)
866 brcmf_dbg(INFO
, "request %s (currently %s)\n",
867 sleep
? "SLEEP" : "WAKE",
868 bus
->sleeping
? "SLEEP" : "WAKE");
870 /* Done if we're already in the requested state */
871 if (sleep
== bus
->sleeping
)
874 /* Going to sleep: set the alarm and turn off the lights... */
876 /* Don't sleep if something is pending */
877 if (bus
->dpc_sched
|| bus
->rxskip
|| pktq_len(&bus
->txq
))
880 /* Make sure the controller has the bus up */
881 brcmf_sdbrcm_clkctl(bus
, CLK_AVAIL
, false);
883 /* Tell device to start using OOB wakeup */
884 w_sdreg32(bus
, SMB_USE_OOB
,
885 offsetof(struct sdpcmd_regs
, tosbmailbox
), &retries
);
886 if (retries
> retry_limit
)
887 brcmf_dbg(ERROR
, "CANNOT SIGNAL CHIP, WILL NOT WAKE UP!!\n");
889 /* Turn off our contribution to the HT clock request */
890 brcmf_sdbrcm_clkctl(bus
, CLK_SDONLY
, false);
892 brcmf_sdcard_cfg_write(bus
->sdiodev
, SDIO_FUNC_1
,
893 SBSDIO_FUNC1_CHIPCLKCSR
,
894 SBSDIO_FORCE_HW_CLKREQ_OFF
, NULL
);
896 /* Isolate the bus */
897 brcmf_sdcard_cfg_write(bus
->sdiodev
, SDIO_FUNC_1
,
899 SBSDIO_DEVCTL_PADS_ISO
, NULL
);
902 bus
->sleeping
= true;
905 /* Waking up: bus power up is ok, set local state */
907 brcmf_sdcard_cfg_write(bus
->sdiodev
, SDIO_FUNC_1
,
908 SBSDIO_FUNC1_CHIPCLKCSR
, 0, NULL
);
910 /* Force pad isolation off if possible
911 (in case power never toggled) */
912 if ((bus
->ci
->buscoretype
== PCMCIA_CORE_ID
)
913 && (bus
->ci
->buscorerev
>= 10))
914 brcmf_sdcard_cfg_write(bus
->sdiodev
, SDIO_FUNC_1
,
915 SBSDIO_DEVICE_CTL
, 0, NULL
);
917 /* Make sure the controller has the bus up */
918 brcmf_sdbrcm_clkctl(bus
, CLK_AVAIL
, false);
920 /* Send misc interrupt to indicate OOB not needed */
921 w_sdreg32(bus
, 0, offsetof(struct sdpcmd_regs
, tosbmailboxdata
),
923 if (retries
<= retry_limit
)
924 w_sdreg32(bus
, SMB_DEV_INT
,
925 offsetof(struct sdpcmd_regs
, tosbmailbox
),
928 if (retries
> retry_limit
)
929 brcmf_dbg(ERROR
, "CANNOT SIGNAL CHIP TO CLEAR OOB!!\n");
931 /* Make sure we have SD bus access */
932 brcmf_sdbrcm_clkctl(bus
, CLK_SDONLY
, false);
935 bus
->sleeping
= false;
941 static void bus_wake(struct brcmf_bus
*bus
)
944 brcmf_sdbrcm_bussleep(bus
, false);
947 static u32
brcmf_sdbrcm_hostmail(struct brcmf_bus
*bus
)
954 brcmf_dbg(TRACE
, "Enter\n");
956 /* Read mailbox data and ack that we did so */
957 r_sdreg32(bus
, &hmb_data
,
958 offsetof(struct sdpcmd_regs
, tohostmailboxdata
), &retries
);
960 if (retries
<= retry_limit
)
961 w_sdreg32(bus
, SMB_INT_ACK
,
962 offsetof(struct sdpcmd_regs
, tosbmailbox
), &retries
);
965 /* Dongle recomposed rx frames, accept them again */
966 if (hmb_data
& HMB_DATA_NAKHANDLED
) {
967 brcmf_dbg(INFO
, "Dongle reports NAK handled, expect rtx of %d\n",
970 brcmf_dbg(ERROR
, "unexpected NAKHANDLED!\n");
973 intstatus
|= I_HMB_FRAME_IND
;
977 * DEVREADY does not occur with gSPI.
979 if (hmb_data
& (HMB_DATA_DEVREADY
| HMB_DATA_FWREADY
)) {
981 (hmb_data
& HMB_DATA_VERSION_MASK
) >>
982 HMB_DATA_VERSION_SHIFT
;
983 if (bus
->sdpcm_ver
!= SDPCM_PROT_VERSION
)
984 brcmf_dbg(ERROR
, "Version mismatch, dongle reports %d, "
986 bus
->sdpcm_ver
, SDPCM_PROT_VERSION
);
988 brcmf_dbg(INFO
, "Dongle ready, protocol version %d\n",
993 * Flow Control has been moved into the RX headers and this out of band
994 * method isn't used any more.
995 * remaining backward compatible with older dongles.
997 if (hmb_data
& HMB_DATA_FC
) {
998 fcbits
= (hmb_data
& HMB_DATA_FCDATA_MASK
) >>
999 HMB_DATA_FCDATA_SHIFT
;
1001 if (fcbits
& ~bus
->flowcontrol
)
1004 if (bus
->flowcontrol
& ~fcbits
)
1008 bus
->flowcontrol
= fcbits
;
1011 /* Shouldn't be any others */
1012 if (hmb_data
& ~(HMB_DATA_DEVREADY
|
1013 HMB_DATA_NAKHANDLED
|
1016 HMB_DATA_FCDATA_MASK
| HMB_DATA_VERSION_MASK
))
1017 brcmf_dbg(ERROR
, "Unknown mailbox data content: 0x%02x\n",
1023 static void brcmf_sdbrcm_rxfail(struct brcmf_bus
*bus
, bool abort
, bool rtx
)
1030 brcmf_dbg(ERROR
, "%sterminate frame%s\n",
1031 abort
? "abort command, " : "",
1032 rtx
? ", send NAK" : "");
1035 brcmf_sdcard_abort(bus
->sdiodev
, SDIO_FUNC_2
);
1037 brcmf_sdcard_cfg_write(bus
->sdiodev
, SDIO_FUNC_1
,
1038 SBSDIO_FUNC1_FRAMECTRL
,
1042 /* Wait until the packet has been flushed (device/FIFO stable) */
1043 for (lastrbc
= retries
= 0xffff; retries
> 0; retries
--) {
1044 hi
= brcmf_sdcard_cfg_read(bus
->sdiodev
, SDIO_FUNC_1
,
1045 SBSDIO_FUNC1_RFRAMEBCHI
, NULL
);
1046 lo
= brcmf_sdcard_cfg_read(bus
->sdiodev
, SDIO_FUNC_1
,
1047 SBSDIO_FUNC1_RFRAMEBCLO
, NULL
);
1048 bus
->f1regdata
+= 2;
1050 if ((hi
== 0) && (lo
== 0))
1053 if ((hi
> (lastrbc
>> 8)) && (lo
> (lastrbc
& 0x00ff))) {
1054 brcmf_dbg(ERROR
, "count growing: last 0x%04x now 0x%04x\n",
1055 lastrbc
, (hi
<< 8) + lo
);
1057 lastrbc
= (hi
<< 8) + lo
;
1061 brcmf_dbg(ERROR
, "count never zeroed: last 0x%04x\n", lastrbc
);
1063 brcmf_dbg(INFO
, "flush took %d iterations\n", 0xffff - retries
);
1067 w_sdreg32(bus
, SMB_NAK
,
1068 offsetof(struct sdpcmd_regs
, tosbmailbox
), &retries
);
1071 if (retries
<= retry_limit
)
1075 /* Clear partial in any case */
1078 /* If we can't reach the device, signal failure */
1079 if (err
|| brcmf_sdcard_regfail(bus
->sdiodev
))
1080 bus
->drvr
->busstate
= BRCMF_BUS_DOWN
;
1083 /* copy a buffer into a pkt buffer chain */
1084 static uint
brcmf_sdbrcm_glom_from_buf(struct brcmf_bus
*bus
, uint len
)
1093 skb_queue_walk(&bus
->glom
, p
) {
1094 n
= min_t(uint
, p
->len
, len
);
1095 memcpy(p
->data
, buf
, n
);
1106 static u8
brcmf_sdbrcm_rxglom(struct brcmf_bus
*bus
, u8 rxseq
)
1112 struct sk_buff
*pfirst
, *plast
, *pnext
, *save_pfirst
;
1115 u8 chan
, seq
, doff
, sfdoff
;
1119 bool usechain
= bus
->use_rxchain
;
1121 /* If packets, issue read(s) and send up packet chain */
1122 /* Return sequence numbers consumed? */
1124 brcmf_dbg(TRACE
, "start: glomd %p glom %p\n",
1125 bus
->glomd
, skb_peek(&bus
->glom
));
1127 /* If there's a descriptor, generate the packet chain */
1129 pfirst
= plast
= pnext
= NULL
;
1130 dlen
= (u16
) (bus
->glomd
->len
);
1131 dptr
= bus
->glomd
->data
;
1132 if (!dlen
|| (dlen
& 1)) {
1133 brcmf_dbg(ERROR
, "bad glomd len(%d), ignore descriptor\n",
1138 for (totlen
= num
= 0; dlen
; num
++) {
1139 /* Get (and move past) next length */
1140 sublen
= get_unaligned_le16(dptr
);
1141 dlen
-= sizeof(u16
);
1142 dptr
+= sizeof(u16
);
1143 if ((sublen
< SDPCM_HDRLEN
) ||
1144 ((num
== 0) && (sublen
< (2 * SDPCM_HDRLEN
)))) {
1145 brcmf_dbg(ERROR
, "descriptor len %d bad: %d\n",
1150 if (sublen
% BRCMF_SDALIGN
) {
1151 brcmf_dbg(ERROR
, "sublen %d not multiple of %d\n",
1152 sublen
, BRCMF_SDALIGN
);
1157 /* For last frame, adjust read len so total
1158 is a block multiple */
1161 (roundup(totlen
, bus
->blocksize
) - totlen
);
1162 totlen
= roundup(totlen
, bus
->blocksize
);
1165 /* Allocate/chain packet for next subframe */
1166 pnext
= brcmu_pkt_buf_get_skb(sublen
+ BRCMF_SDALIGN
);
1167 if (pnext
== NULL
) {
1168 brcmf_dbg(ERROR
, "bcm_pkt_buf_get_skb failed, num %d len %d\n",
1172 skb_queue_tail(&bus
->glom
, pnext
);
1174 /* Adhere to start alignment requirements */
1175 pkt_align(pnext
, sublen
, BRCMF_SDALIGN
);
1178 /* If all allocations succeeded, save packet chain
1181 brcmf_dbg(GLOM
, "allocated %d-byte packet chain for %d subframes\n",
1183 if (BRCMF_GLOM_ON() && bus
->nextlen
&&
1184 totlen
!= bus
->nextlen
) {
1185 brcmf_dbg(GLOM
, "glomdesc mismatch: nextlen %d glomdesc %d rxseq %d\n",
1186 bus
->nextlen
, totlen
, rxseq
);
1188 pfirst
= pnext
= NULL
;
1190 if (!skb_queue_empty(&bus
->glom
))
1191 skb_queue_walk_safe(&bus
->glom
, pfirst
, pnext
) {
1192 skb_unlink(pfirst
, &bus
->glom
);
1193 brcmu_pkt_buf_free_skb(pfirst
);
1198 /* Done with descriptor packet */
1199 brcmu_pkt_buf_free_skb(bus
->glomd
);
1204 /* Ok -- either we just generated a packet chain,
1205 or had one from before */
1206 if (!skb_queue_empty(&bus
->glom
)) {
1207 if (BRCMF_GLOM_ON()) {
1208 brcmf_dbg(GLOM
, "try superframe read, packet chain:\n");
1209 skb_queue_walk(&bus
->glom
, pnext
) {
1210 brcmf_dbg(GLOM
, " %p: %p len 0x%04x (%d)\n",
1211 pnext
, (u8
*) (pnext
->data
),
1212 pnext
->len
, pnext
->len
);
1216 pfirst
= skb_peek(&bus
->glom
);
1217 dlen
= (u16
) brcmu_pkttotlen(pfirst
);
1219 /* Do an SDIO read for the superframe. Configurable iovar to
1220 * read directly into the chained packet, or allocate a large
1221 * packet and and copy into the chain.
1224 errcode
= brcmf_sdcard_recv_buf(bus
->sdiodev
,
1225 bus
->sdiodev
->sbwad
,
1227 F2SYNC
, (u8
*) pfirst
->data
, dlen
,
1229 } else if (bus
->dataptr
) {
1230 errcode
= brcmf_sdcard_recv_buf(bus
->sdiodev
,
1231 bus
->sdiodev
->sbwad
,
1233 F2SYNC
, bus
->dataptr
, dlen
,
1235 sublen
= (u16
) brcmf_sdbrcm_glom_from_buf(bus
, dlen
);
1236 if (sublen
!= dlen
) {
1237 brcmf_dbg(ERROR
, "FAILED TO COPY, dlen %d sublen %d\n",
1243 brcmf_dbg(ERROR
, "COULDN'T ALLOC %d-BYTE GLOM, FORCE FAILURE\n",
1249 /* On failure, kill the superframe, allow a couple retries */
1251 brcmf_dbg(ERROR
, "glom read of %d bytes failed: %d\n",
1253 bus
->drvr
->rx_errors
++;
1255 if (bus
->glomerr
++ < 3) {
1256 brcmf_sdbrcm_rxfail(bus
, true, true);
1259 brcmf_sdbrcm_rxfail(bus
, true, false);
1261 skb_queue_walk_safe(&bus
->glom
, pfirst
, pnext
) {
1262 skb_unlink(pfirst
, &bus
->glom
);
1263 brcmu_pkt_buf_free_skb(pfirst
);
1269 if (BRCMF_GLOM_ON()) {
1270 printk(KERN_DEBUG
"SUPERFRAME:\n");
1271 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET
,
1272 pfirst
->data
, min_t(int, pfirst
->len
, 48));
1276 /* Validate the superframe header */
1277 dptr
= (u8
*) (pfirst
->data
);
1278 sublen
= get_unaligned_le16(dptr
);
1279 check
= get_unaligned_le16(dptr
+ sizeof(u16
));
1281 chan
= SDPCM_PACKET_CHANNEL(&dptr
[SDPCM_FRAMETAG_LEN
]);
1282 seq
= SDPCM_PACKET_SEQUENCE(&dptr
[SDPCM_FRAMETAG_LEN
]);
1283 bus
->nextlen
= dptr
[SDPCM_FRAMETAG_LEN
+ SDPCM_NEXTLEN_OFFSET
];
1284 if ((bus
->nextlen
<< 4) > MAX_RX_DATASZ
) {
1285 brcmf_dbg(INFO
, "nextlen too large (%d) seq %d\n",
1289 doff
= SDPCM_DOFFSET_VALUE(&dptr
[SDPCM_FRAMETAG_LEN
]);
1290 txmax
= SDPCM_WINDOW_VALUE(&dptr
[SDPCM_FRAMETAG_LEN
]);
1293 if ((u16
)~(sublen
^ check
)) {
1294 brcmf_dbg(ERROR
, "(superframe): HW hdr error: len/check 0x%04x/0x%04x\n",
1297 } else if (roundup(sublen
, bus
->blocksize
) != dlen
) {
1298 brcmf_dbg(ERROR
, "(superframe): len 0x%04x, rounded 0x%04x, expect 0x%04x\n",
1299 sublen
, roundup(sublen
, bus
->blocksize
),
1302 } else if (SDPCM_PACKET_CHANNEL(&dptr
[SDPCM_FRAMETAG_LEN
]) !=
1303 SDPCM_GLOM_CHANNEL
) {
1304 brcmf_dbg(ERROR
, "(superframe): bad channel %d\n",
1305 SDPCM_PACKET_CHANNEL(
1306 &dptr
[SDPCM_FRAMETAG_LEN
]));
1308 } else if (SDPCM_GLOMDESC(&dptr
[SDPCM_FRAMETAG_LEN
])) {
1309 brcmf_dbg(ERROR
, "(superframe): got 2nd descriptor?\n");
1311 } else if ((doff
< SDPCM_HDRLEN
) ||
1312 (doff
> (pfirst
->len
- SDPCM_HDRLEN
))) {
1313 brcmf_dbg(ERROR
, "(superframe): Bad data offset %d: HW %d pkt %d min %d\n",
1314 doff
, sublen
, pfirst
->len
, SDPCM_HDRLEN
);
1318 /* Check sequence number of superframe SW header */
1320 brcmf_dbg(INFO
, "(superframe) rx_seq %d, expected %d\n",
1326 /* Check window for sanity */
1327 if ((u8
) (txmax
- bus
->tx_seq
) > 0x40) {
1328 brcmf_dbg(ERROR
, "unlikely tx max %d with tx_seq %d\n",
1329 txmax
, bus
->tx_seq
);
1330 txmax
= bus
->tx_seq
+ 2;
1332 bus
->tx_max
= txmax
;
1334 /* Remove superframe header, remember offset */
1335 skb_pull(pfirst
, doff
);
1338 /* Validate all the subframe headers */
1339 for (num
= 0, pnext
= pfirst
; pnext
&& !errcode
;
1340 num
++, pnext
= pnext
->next
) {
1341 dptr
= (u8
*) (pnext
->data
);
1342 dlen
= (u16
) (pnext
->len
);
1343 sublen
= get_unaligned_le16(dptr
);
1344 check
= get_unaligned_le16(dptr
+ sizeof(u16
));
1345 chan
= SDPCM_PACKET_CHANNEL(&dptr
[SDPCM_FRAMETAG_LEN
]);
1346 doff
= SDPCM_DOFFSET_VALUE(&dptr
[SDPCM_FRAMETAG_LEN
]);
1348 if (BRCMF_GLOM_ON()) {
1349 printk(KERN_DEBUG
"subframe:\n");
1350 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET
,
1355 if ((u16
)~(sublen
^ check
)) {
1356 brcmf_dbg(ERROR
, "(subframe %d): HW hdr error: len/check 0x%04x/0x%04x\n",
1357 num
, sublen
, check
);
1359 } else if ((sublen
> dlen
) || (sublen
< SDPCM_HDRLEN
)) {
1360 brcmf_dbg(ERROR
, "(subframe %d): length mismatch: len 0x%04x, expect 0x%04x\n",
1363 } else if ((chan
!= SDPCM_DATA_CHANNEL
) &&
1364 (chan
!= SDPCM_EVENT_CHANNEL
)) {
1365 brcmf_dbg(ERROR
, "(subframe %d): bad channel %d\n",
1368 } else if ((doff
< SDPCM_HDRLEN
) || (doff
> sublen
)) {
1369 brcmf_dbg(ERROR
, "(subframe %d): Bad data offset %d: HW %d min %d\n",
1370 num
, doff
, sublen
, SDPCM_HDRLEN
);
1376 /* Terminate frame on error, request
1378 if (bus
->glomerr
++ < 3) {
1379 /* Restore superframe header space */
1380 skb_push(pfirst
, sfdoff
);
1381 brcmf_sdbrcm_rxfail(bus
, true, true);
1384 brcmf_sdbrcm_rxfail(bus
, true, false);
1386 skb_queue_walk_safe(&bus
->glom
, pfirst
, pnext
) {
1387 skb_unlink(pfirst
, &bus
->glom
);
1388 brcmu_pkt_buf_free_skb(pfirst
);
1395 /* Basic SD framing looks ok - process each packet (header) */
1396 save_pfirst
= pfirst
;
1399 for (num
= 0; pfirst
; rxseq
++, pfirst
= pnext
) {
1400 pnext
= pfirst
->next
;
1401 pfirst
->next
= NULL
;
1403 dptr
= (u8
*) (pfirst
->data
);
1404 sublen
= get_unaligned_le16(dptr
);
1405 chan
= SDPCM_PACKET_CHANNEL(&dptr
[SDPCM_FRAMETAG_LEN
]);
1406 seq
= SDPCM_PACKET_SEQUENCE(&dptr
[SDPCM_FRAMETAG_LEN
]);
1407 doff
= SDPCM_DOFFSET_VALUE(&dptr
[SDPCM_FRAMETAG_LEN
]);
1409 brcmf_dbg(GLOM
, "Get subframe %d, %p(%p/%d), sublen %d chan %d seq %d\n",
1410 num
, pfirst
, pfirst
->data
,
1411 pfirst
->len
, sublen
, chan
, seq
);
1413 /* precondition: chan == SDPCM_DATA_CHANNEL ||
1414 chan == SDPCM_EVENT_CHANNEL */
1417 brcmf_dbg(GLOM
, "rx_seq %d, expected %d\n",
1423 if (BRCMF_BYTES_ON() && BRCMF_DATA_ON()) {
1424 printk(KERN_DEBUG
"Rx Subframe Data:\n");
1425 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET
,
1430 __skb_trim(pfirst
, sublen
);
1431 skb_pull(pfirst
, doff
);
1433 if (pfirst
->len
== 0) {
1434 brcmu_pkt_buf_free_skb(pfirst
);
1436 plast
->next
= pnext
;
1438 save_pfirst
= pnext
;
1441 } else if (brcmf_proto_hdrpull(bus
->drvr
, &ifidx
,
1443 brcmf_dbg(ERROR
, "rx protocol error\n");
1444 bus
->drvr
->rx_errors
++;
1445 brcmu_pkt_buf_free_skb(pfirst
);
1447 plast
->next
= pnext
;
1449 save_pfirst
= pnext
;
1454 /* this packet will go up, link back into
1455 chain and count it */
1456 pfirst
->next
= pnext
;
1461 if (BRCMF_GLOM_ON()) {
1462 brcmf_dbg(GLOM
, "subframe %d to stack, %p (%p/%d) nxt/lnk %p/%p\n",
1463 num
, pfirst
, pfirst
->data
,
1464 pfirst
->len
, pfirst
->next
,
1466 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET
,
1468 min_t(int, pfirst
->len
, 32));
1474 brcmf_rx_frame(bus
->drvr
, ifidx
, save_pfirst
, num
);
1478 bus
->rxglomframes
++;
1479 bus
->rxglompkts
+= num
;
1484 static int brcmf_sdbrcm_dcmd_resp_wait(struct brcmf_bus
*bus
, uint
*condition
,
1487 DECLARE_WAITQUEUE(wait
, current
);
1488 int timeout
= msecs_to_jiffies(DCMD_RESP_TIMEOUT
);
1490 /* Wait until control frame is available */
1491 add_wait_queue(&bus
->dcmd_resp_wait
, &wait
);
1492 set_current_state(TASK_INTERRUPTIBLE
);
1494 while (!(*condition
) && (!signal_pending(current
) && timeout
))
1495 timeout
= schedule_timeout(timeout
);
1497 if (signal_pending(current
))
1500 set_current_state(TASK_RUNNING
);
1501 remove_wait_queue(&bus
->dcmd_resp_wait
, &wait
);
1506 static int brcmf_sdbrcm_dcmd_resp_wake(struct brcmf_bus
*bus
)
1508 if (waitqueue_active(&bus
->dcmd_resp_wait
))
1509 wake_up_interruptible(&bus
->dcmd_resp_wait
);
1514 brcmf_sdbrcm_read_control(struct brcmf_bus
*bus
, u8
*hdr
, uint len
, uint doff
)
1520 brcmf_dbg(TRACE
, "Enter\n");
1522 /* Set rxctl for frame (w/optional alignment) */
1523 bus
->rxctl
= bus
->rxbuf
;
1524 bus
->rxctl
+= BRCMF_FIRSTREAD
;
1525 pad
= ((unsigned long)bus
->rxctl
% BRCMF_SDALIGN
);
1527 bus
->rxctl
+= (BRCMF_SDALIGN
- pad
);
1528 bus
->rxctl
-= BRCMF_FIRSTREAD
;
1530 /* Copy the already-read portion over */
1531 memcpy(bus
->rxctl
, hdr
, BRCMF_FIRSTREAD
);
1532 if (len
<= BRCMF_FIRSTREAD
)
1535 /* Raise rdlen to next SDIO block to avoid tail command */
1536 rdlen
= len
- BRCMF_FIRSTREAD
;
1537 if (bus
->roundup
&& bus
->blocksize
&& (rdlen
> bus
->blocksize
)) {
1538 pad
= bus
->blocksize
- (rdlen
% bus
->blocksize
);
1539 if ((pad
<= bus
->roundup
) && (pad
< bus
->blocksize
) &&
1540 ((len
+ pad
) < bus
->drvr
->maxctl
))
1542 } else if (rdlen
% BRCMF_SDALIGN
) {
1543 rdlen
+= BRCMF_SDALIGN
- (rdlen
% BRCMF_SDALIGN
);
1546 /* Satisfy length-alignment requirements */
1547 if (rdlen
& (ALIGNMENT
- 1))
1548 rdlen
= roundup(rdlen
, ALIGNMENT
);
1550 /* Drop if the read is too big or it exceeds our maximum */
1551 if ((rdlen
+ BRCMF_FIRSTREAD
) > bus
->drvr
->maxctl
) {
1552 brcmf_dbg(ERROR
, "%d-byte control read exceeds %d-byte buffer\n",
1553 rdlen
, bus
->drvr
->maxctl
);
1554 bus
->drvr
->rx_errors
++;
1555 brcmf_sdbrcm_rxfail(bus
, false, false);
1559 if ((len
- doff
) > bus
->drvr
->maxctl
) {
1560 brcmf_dbg(ERROR
, "%d-byte ctl frame (%d-byte ctl data) exceeds %d-byte limit\n",
1561 len
, len
- doff
, bus
->drvr
->maxctl
);
1562 bus
->drvr
->rx_errors
++;
1564 brcmf_sdbrcm_rxfail(bus
, false, false);
1568 /* Read remainder of frame body into the rxctl buffer */
1569 sdret
= brcmf_sdcard_recv_buf(bus
->sdiodev
,
1570 bus
->sdiodev
->sbwad
,
1572 F2SYNC
, (bus
->rxctl
+ BRCMF_FIRSTREAD
), rdlen
,
1576 /* Control frame failures need retransmission */
1578 brcmf_dbg(ERROR
, "read %d control bytes failed: %d\n",
1581 brcmf_sdbrcm_rxfail(bus
, true, true);
1588 if (BRCMF_BYTES_ON() && BRCMF_CTL_ON()) {
1589 printk(KERN_DEBUG
"RxCtrl:\n");
1590 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET
, bus
->rxctl
, len
);
1594 /* Point to valid data and indicate its length */
1596 bus
->rxlen
= len
- doff
;
1599 /* Awake any waiters */
1600 brcmf_sdbrcm_dcmd_resp_wake(bus
);
1603 /* Pad read to blocksize for efficiency */
1604 static void brcmf_pad(struct brcmf_bus
*bus
, u16
*pad
, u16
*rdlen
)
1606 if (bus
->roundup
&& bus
->blocksize
&& *rdlen
> bus
->blocksize
) {
1607 *pad
= bus
->blocksize
- (*rdlen
% bus
->blocksize
);
1608 if (*pad
<= bus
->roundup
&& *pad
< bus
->blocksize
&&
1609 *rdlen
+ *pad
+ BRCMF_FIRSTREAD
< MAX_RX_DATASZ
)
1611 } else if (*rdlen
% BRCMF_SDALIGN
) {
1612 *rdlen
+= BRCMF_SDALIGN
- (*rdlen
% BRCMF_SDALIGN
);
1617 brcmf_alloc_pkt_and_read(struct brcmf_bus
*bus
, u16 rdlen
,
1618 struct sk_buff
**pkt
, u8
**rxbuf
)
1620 int sdret
; /* Return code from calls */
1622 *pkt
= brcmu_pkt_buf_get_skb(rdlen
+ BRCMF_SDALIGN
);
1626 pkt_align(*pkt
, rdlen
, BRCMF_SDALIGN
);
1627 *rxbuf
= (u8
*) ((*pkt
)->data
);
1628 /* Read the entire frame */
1629 sdret
= brcmf_sdcard_recv_buf(bus
->sdiodev
, bus
->sdiodev
->sbwad
,
1630 SDIO_FUNC_2
, F2SYNC
,
1631 *rxbuf
, rdlen
, *pkt
);
1635 brcmf_dbg(ERROR
, "(nextlen): read %d bytes failed: %d\n",
1637 brcmu_pkt_buf_free_skb(*pkt
);
1638 bus
->drvr
->rx_errors
++;
1639 /* Force retry w/normal header read.
1640 * Don't attempt NAK for
1643 brcmf_sdbrcm_rxfail(bus
, true, true);
1648 /* Checks the header */
1650 brcmf_check_rxbuf(struct brcmf_bus
*bus
, struct sk_buff
*pkt
, u8
*rxbuf
,
1651 u8 rxseq
, u16 nextlen
, u16
*len
)
1654 bool len_consistent
; /* Result of comparing readahead len and
1657 memcpy(bus
->rxhdr
, rxbuf
, SDPCM_HDRLEN
);
1659 /* Extract hardware header fields */
1660 *len
= get_unaligned_le16(bus
->rxhdr
);
1661 check
= get_unaligned_le16(bus
->rxhdr
+ sizeof(u16
));
1663 /* All zeros means readahead info was bad */
1664 if (!(*len
| check
)) {
1665 brcmf_dbg(INFO
, "(nextlen): read zeros in HW header???\n");
1669 /* Validate check bytes */
1670 if ((u16
)~(*len
^ check
)) {
1671 brcmf_dbg(ERROR
, "(nextlen): HW hdr error: nextlen/len/check 0x%04x/0x%04x/0x%04x\n",
1672 nextlen
, *len
, check
);
1674 brcmf_sdbrcm_rxfail(bus
, false, false);
1678 /* Validate frame length */
1679 if (*len
< SDPCM_HDRLEN
) {
1680 brcmf_dbg(ERROR
, "(nextlen): HW hdr length invalid: %d\n",
1685 /* Check for consistency with readahead info */
1686 len_consistent
= (nextlen
!= (roundup(*len
, 16) >> 4));
1687 if (len_consistent
) {
1688 /* Mismatch, force retry w/normal
1689 header (may be >4K) */
1690 brcmf_dbg(ERROR
, "(nextlen): mismatch, nextlen %d len %d rnd %d; expected rxseq %d\n",
1691 nextlen
, *len
, roundup(*len
, 16),
1693 brcmf_sdbrcm_rxfail(bus
, true, true);
1700 brcmf_sdbrcm_pktfree2(bus
, pkt
);
1704 /* Return true if there may be more frames to read */
1706 brcmf_sdbrcm_readframes(struct brcmf_bus
*bus
, uint maxframes
, bool *finished
)
1708 u16 len
, check
; /* Extracted hardware header fields */
1709 u8 chan
, seq
, doff
; /* Extracted software header fields */
1710 u8 fcbits
; /* Extracted fcbits from software header */
1712 struct sk_buff
*pkt
; /* Packet for event or data frames */
1713 u16 pad
; /* Number of pad bytes to read */
1714 u16 rdlen
; /* Total number of bytes to read */
1715 u8 rxseq
; /* Next sequence number to expect */
1716 uint rxleft
= 0; /* Remaining number of frames allowed */
1717 int sdret
; /* Return code from calls */
1718 u8 txmax
; /* Maximum tx sequence offered */
1721 uint rxcount
= 0; /* Total frames read */
1723 brcmf_dbg(TRACE
, "Enter\n");
1725 /* Not finished unless we encounter no more frames indication */
1728 for (rxseq
= bus
->rx_seq
, rxleft
= maxframes
;
1729 !bus
->rxskip
&& rxleft
&& bus
->drvr
->busstate
!= BRCMF_BUS_DOWN
;
1730 rxseq
++, rxleft
--) {
1732 /* Handle glomming separately */
1733 if (bus
->glomd
|| !skb_queue_empty(&bus
->glom
)) {
1735 brcmf_dbg(GLOM
, "calling rxglom: glomd %p, glom %p\n",
1736 bus
->glomd
, skb_peek(&bus
->glom
));
1737 cnt
= brcmf_sdbrcm_rxglom(bus
, rxseq
);
1738 brcmf_dbg(GLOM
, "rxglom returned %d\n", cnt
);
1740 rxleft
= (rxleft
> cnt
) ? (rxleft
- cnt
) : 1;
1744 /* Try doing single read if we can */
1746 u16 nextlen
= bus
->nextlen
;
1749 rdlen
= len
= nextlen
<< 4;
1750 brcmf_pad(bus
, &pad
, &rdlen
);
1753 * After the frame is received we have to
1754 * distinguish whether it is data
1755 * or non-data frame.
1757 brcmf_alloc_pkt_and_read(bus
, rdlen
, &pkt
, &rxbuf
);
1759 /* Give up on data, request rtx of events */
1760 brcmf_dbg(ERROR
, "(nextlen): brcmf_alloc_pkt_and_read failed: len %d rdlen %d expected rxseq %d\n",
1765 if (brcmf_check_rxbuf(bus
, pkt
, rxbuf
, rxseq
, nextlen
,
1769 /* Extract software header fields */
1770 chan
= SDPCM_PACKET_CHANNEL(
1771 &bus
->rxhdr
[SDPCM_FRAMETAG_LEN
]);
1772 seq
= SDPCM_PACKET_SEQUENCE(
1773 &bus
->rxhdr
[SDPCM_FRAMETAG_LEN
]);
1774 doff
= SDPCM_DOFFSET_VALUE(
1775 &bus
->rxhdr
[SDPCM_FRAMETAG_LEN
]);
1776 txmax
= SDPCM_WINDOW_VALUE(
1777 &bus
->rxhdr
[SDPCM_FRAMETAG_LEN
]);
1780 bus
->rxhdr
[SDPCM_FRAMETAG_LEN
+
1781 SDPCM_NEXTLEN_OFFSET
];
1782 if ((bus
->nextlen
<< 4) > MAX_RX_DATASZ
) {
1783 brcmf_dbg(INFO
, "(nextlen): got frame w/nextlen too large (%d), seq %d\n",
1788 bus
->drvr
->rx_readahead_cnt
++;
1790 /* Handle Flow Control */
1791 fcbits
= SDPCM_FCMASK_VALUE(
1792 &bus
->rxhdr
[SDPCM_FRAMETAG_LEN
]);
1794 if (bus
->flowcontrol
!= fcbits
) {
1795 if (~bus
->flowcontrol
& fcbits
)
1798 if (bus
->flowcontrol
& ~fcbits
)
1802 bus
->flowcontrol
= fcbits
;
1805 /* Check and update sequence number */
1807 brcmf_dbg(INFO
, "(nextlen): rx_seq %d, expected %d\n",
1813 /* Check window for sanity */
1814 if ((u8
) (txmax
- bus
->tx_seq
) > 0x40) {
1815 brcmf_dbg(ERROR
, "got unlikely tx max %d with tx_seq %d\n",
1816 txmax
, bus
->tx_seq
);
1817 txmax
= bus
->tx_seq
+ 2;
1819 bus
->tx_max
= txmax
;
1822 if (BRCMF_BYTES_ON() && BRCMF_DATA_ON()) {
1823 printk(KERN_DEBUG
"Rx Data:\n");
1824 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET
,
1826 } else if (BRCMF_HDRS_ON()) {
1827 printk(KERN_DEBUG
"RxHdr:\n");
1828 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET
,
1829 bus
->rxhdr
, SDPCM_HDRLEN
);
1833 if (chan
== SDPCM_CONTROL_CHANNEL
) {
1834 brcmf_dbg(ERROR
, "(nextlen): readahead on control packet %d?\n",
1836 /* Force retry w/normal header read */
1838 brcmf_sdbrcm_rxfail(bus
, false, true);
1839 brcmf_sdbrcm_pktfree2(bus
, pkt
);
1843 /* Validate data offset */
1844 if ((doff
< SDPCM_HDRLEN
) || (doff
> len
)) {
1845 brcmf_dbg(ERROR
, "(nextlen): bad data offset %d: HW len %d min %d\n",
1846 doff
, len
, SDPCM_HDRLEN
);
1847 brcmf_sdbrcm_rxfail(bus
, false, false);
1848 brcmf_sdbrcm_pktfree2(bus
, pkt
);
1852 /* All done with this one -- now deliver the packet */
1856 /* Read frame header (hardware and software) */
1857 sdret
= brcmf_sdcard_recv_buf(bus
->sdiodev
, bus
->sdiodev
->sbwad
,
1858 SDIO_FUNC_2
, F2SYNC
, bus
->rxhdr
,
1859 BRCMF_FIRSTREAD
, NULL
);
1863 brcmf_dbg(ERROR
, "RXHEADER FAILED: %d\n", sdret
);
1865 brcmf_sdbrcm_rxfail(bus
, true, true);
1869 if (BRCMF_BYTES_ON() || BRCMF_HDRS_ON()) {
1870 printk(KERN_DEBUG
"RxHdr:\n");
1871 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET
,
1872 bus
->rxhdr
, SDPCM_HDRLEN
);
1876 /* Extract hardware header fields */
1877 len
= get_unaligned_le16(bus
->rxhdr
);
1878 check
= get_unaligned_le16(bus
->rxhdr
+ sizeof(u16
));
1880 /* All zeros means no more frames */
1881 if (!(len
| check
)) {
1886 /* Validate check bytes */
1887 if ((u16
) ~(len
^ check
)) {
1888 brcmf_dbg(ERROR
, "HW hdr err: len/check 0x%04x/0x%04x\n",
1891 brcmf_sdbrcm_rxfail(bus
, false, false);
1895 /* Validate frame length */
1896 if (len
< SDPCM_HDRLEN
) {
1897 brcmf_dbg(ERROR
, "HW hdr length invalid: %d\n", len
);
1901 /* Extract software header fields */
1902 chan
= SDPCM_PACKET_CHANNEL(&bus
->rxhdr
[SDPCM_FRAMETAG_LEN
]);
1903 seq
= SDPCM_PACKET_SEQUENCE(&bus
->rxhdr
[SDPCM_FRAMETAG_LEN
]);
1904 doff
= SDPCM_DOFFSET_VALUE(&bus
->rxhdr
[SDPCM_FRAMETAG_LEN
]);
1905 txmax
= SDPCM_WINDOW_VALUE(&bus
->rxhdr
[SDPCM_FRAMETAG_LEN
]);
1907 /* Validate data offset */
1908 if ((doff
< SDPCM_HDRLEN
) || (doff
> len
)) {
1909 brcmf_dbg(ERROR
, "Bad data offset %d: HW len %d, min %d seq %d\n",
1910 doff
, len
, SDPCM_HDRLEN
, seq
);
1912 brcmf_sdbrcm_rxfail(bus
, false, false);
1916 /* Save the readahead length if there is one */
1918 bus
->rxhdr
[SDPCM_FRAMETAG_LEN
+ SDPCM_NEXTLEN_OFFSET
];
1919 if ((bus
->nextlen
<< 4) > MAX_RX_DATASZ
) {
1920 brcmf_dbg(INFO
, "(nextlen): got frame w/nextlen too large (%d), seq %d\n",
1925 /* Handle Flow Control */
1926 fcbits
= SDPCM_FCMASK_VALUE(&bus
->rxhdr
[SDPCM_FRAMETAG_LEN
]);
1928 if (bus
->flowcontrol
!= fcbits
) {
1929 if (~bus
->flowcontrol
& fcbits
)
1932 if (bus
->flowcontrol
& ~fcbits
)
1936 bus
->flowcontrol
= fcbits
;
1939 /* Check and update sequence number */
1941 brcmf_dbg(INFO
, "rx_seq %d, expected %d\n", seq
, rxseq
);
1946 /* Check window for sanity */
1947 if ((u8
) (txmax
- bus
->tx_seq
) > 0x40) {
1948 brcmf_dbg(ERROR
, "unlikely tx max %d with tx_seq %d\n",
1949 txmax
, bus
->tx_seq
);
1950 txmax
= bus
->tx_seq
+ 2;
1952 bus
->tx_max
= txmax
;
1954 /* Call a separate function for control frames */
1955 if (chan
== SDPCM_CONTROL_CHANNEL
) {
1956 brcmf_sdbrcm_read_control(bus
, bus
->rxhdr
, len
, doff
);
1960 /* precondition: chan is either SDPCM_DATA_CHANNEL,
1961 SDPCM_EVENT_CHANNEL, SDPCM_TEST_CHANNEL or
1962 SDPCM_GLOM_CHANNEL */
1964 /* Length to read */
1965 rdlen
= (len
> BRCMF_FIRSTREAD
) ? (len
- BRCMF_FIRSTREAD
) : 0;
1967 /* May pad read to blocksize for efficiency */
1968 if (bus
->roundup
&& bus
->blocksize
&&
1969 (rdlen
> bus
->blocksize
)) {
1970 pad
= bus
->blocksize
- (rdlen
% bus
->blocksize
);
1971 if ((pad
<= bus
->roundup
) && (pad
< bus
->blocksize
) &&
1972 ((rdlen
+ pad
+ BRCMF_FIRSTREAD
) < MAX_RX_DATASZ
))
1974 } else if (rdlen
% BRCMF_SDALIGN
) {
1975 rdlen
+= BRCMF_SDALIGN
- (rdlen
% BRCMF_SDALIGN
);
1978 /* Satisfy length-alignment requirements */
1979 if (rdlen
& (ALIGNMENT
- 1))
1980 rdlen
= roundup(rdlen
, ALIGNMENT
);
1982 if ((rdlen
+ BRCMF_FIRSTREAD
) > MAX_RX_DATASZ
) {
1983 /* Too long -- skip this frame */
1984 brcmf_dbg(ERROR
, "too long: len %d rdlen %d\n",
1986 bus
->drvr
->rx_errors
++;
1988 brcmf_sdbrcm_rxfail(bus
, false, false);
1992 pkt
= brcmu_pkt_buf_get_skb(rdlen
+
1993 BRCMF_FIRSTREAD
+ BRCMF_SDALIGN
);
1995 /* Give up on data, request rtx of events */
1996 brcmf_dbg(ERROR
, "brcmu_pkt_buf_get_skb failed: rdlen %d chan %d\n",
1998 bus
->drvr
->rx_dropped
++;
1999 brcmf_sdbrcm_rxfail(bus
, false, RETRYCHAN(chan
));
2003 /* Leave room for what we already read, and align remainder */
2004 skb_pull(pkt
, BRCMF_FIRSTREAD
);
2005 pkt_align(pkt
, rdlen
, BRCMF_SDALIGN
);
2007 /* Read the remaining frame data */
2008 sdret
= brcmf_sdcard_recv_buf(bus
->sdiodev
, bus
->sdiodev
->sbwad
,
2009 SDIO_FUNC_2
, F2SYNC
, ((u8
*) (pkt
->data
)),
2014 brcmf_dbg(ERROR
, "read %d %s bytes failed: %d\n", rdlen
,
2015 ((chan
== SDPCM_EVENT_CHANNEL
) ? "event"
2016 : ((chan
== SDPCM_DATA_CHANNEL
) ? "data"
2018 brcmu_pkt_buf_free_skb(pkt
);
2019 bus
->drvr
->rx_errors
++;
2020 brcmf_sdbrcm_rxfail(bus
, true, RETRYCHAN(chan
));
2024 /* Copy the already-read portion */
2025 skb_push(pkt
, BRCMF_FIRSTREAD
);
2026 memcpy(pkt
->data
, bus
->rxhdr
, BRCMF_FIRSTREAD
);
2029 if (BRCMF_BYTES_ON() && BRCMF_DATA_ON()) {
2030 printk(KERN_DEBUG
"Rx Data:\n");
2031 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET
,
2037 /* Save superframe descriptor and allocate packet frame */
2038 if (chan
== SDPCM_GLOM_CHANNEL
) {
2039 if (SDPCM_GLOMDESC(&bus
->rxhdr
[SDPCM_FRAMETAG_LEN
])) {
2040 brcmf_dbg(GLOM
, "glom descriptor, %d bytes:\n",
2043 if (BRCMF_GLOM_ON()) {
2044 printk(KERN_DEBUG
"Glom Data:\n");
2045 print_hex_dump_bytes("",
2050 __skb_trim(pkt
, len
);
2051 skb_pull(pkt
, SDPCM_HDRLEN
);
2054 brcmf_dbg(ERROR
, "%s: glom superframe w/o "
2055 "descriptor!\n", __func__
);
2056 brcmf_sdbrcm_rxfail(bus
, false, false);
2061 /* Fill in packet len and prio, deliver upward */
2062 __skb_trim(pkt
, len
);
2063 skb_pull(pkt
, doff
);
2065 if (pkt
->len
== 0) {
2066 brcmu_pkt_buf_free_skb(pkt
);
2068 } else if (brcmf_proto_hdrpull(bus
->drvr
, &ifidx
, pkt
) != 0) {
2069 brcmf_dbg(ERROR
, "rx protocol error\n");
2070 brcmu_pkt_buf_free_skb(pkt
);
2071 bus
->drvr
->rx_errors
++;
2075 /* Unlock during rx call */
2077 brcmf_rx_frame(bus
->drvr
, ifidx
, pkt
, 1);
2080 rxcount
= maxframes
- rxleft
;
2082 /* Message if we hit the limit */
2084 brcmf_dbg(DATA
, "hit rx limit of %d frames\n",
2088 brcmf_dbg(DATA
, "processed %d frames\n", rxcount
);
2089 /* Back off rxseq if awaiting rtx, update rx_seq */
2092 bus
->rx_seq
= rxseq
;
2098 brcmf_sdbrcm_send_buf(struct brcmf_bus
*bus
, u32 addr
, uint fn
, uint flags
,
2099 u8
*buf
, uint nbytes
, struct sk_buff
*pkt
)
2101 return brcmf_sdcard_send_buf
2102 (bus
->sdiodev
, addr
, fn
, flags
, buf
, nbytes
, pkt
);
2106 brcmf_sdbrcm_wait_for_event(struct brcmf_bus
*bus
, bool *lockvar
)
2109 wait_event_interruptible_timeout(bus
->ctrl_wait
,
2110 (*lockvar
== false), HZ
* 2);
2116 brcmf_sdbrcm_wait_event_wakeup(struct brcmf_bus
*bus
)
2118 if (waitqueue_active(&bus
->ctrl_wait
))
2119 wake_up_interruptible(&bus
->ctrl_wait
);
2123 /* Writes a HW/SW header into the packet and sends it. */
2124 /* Assumes: (a) header space already there, (b) caller holds lock */
2125 static int brcmf_sdbrcm_txpkt(struct brcmf_bus
*bus
, struct sk_buff
*pkt
,
2126 uint chan
, bool free_pkt
)
2132 struct sk_buff
*new;
2135 brcmf_dbg(TRACE
, "Enter\n");
2137 frame
= (u8
*) (pkt
->data
);
2139 /* Add alignment padding, allocate new packet if needed */
2140 pad
= ((unsigned long)frame
% BRCMF_SDALIGN
);
2142 if (skb_headroom(pkt
) < pad
) {
2143 brcmf_dbg(INFO
, "insufficient headroom %d for %d pad\n",
2144 skb_headroom(pkt
), pad
);
2145 bus
->drvr
->tx_realloc
++;
2146 new = brcmu_pkt_buf_get_skb(pkt
->len
+ BRCMF_SDALIGN
);
2148 brcmf_dbg(ERROR
, "couldn't allocate new %d-byte packet\n",
2149 pkt
->len
+ BRCMF_SDALIGN
);
2154 pkt_align(new, pkt
->len
, BRCMF_SDALIGN
);
2155 memcpy(new->data
, pkt
->data
, pkt
->len
);
2157 brcmu_pkt_buf_free_skb(pkt
);
2158 /* free the pkt if canned one is not used */
2161 frame
= (u8
*) (pkt
->data
);
2162 /* precondition: (frame % BRCMF_SDALIGN) == 0) */
2166 frame
= (u8
*) (pkt
->data
);
2167 /* precondition: pad + SDPCM_HDRLEN <= pkt->len */
2168 memset(frame
, 0, pad
+ SDPCM_HDRLEN
);
2171 /* precondition: pad < BRCMF_SDALIGN */
2173 /* Hardware tag: 2 byte len followed by 2 byte ~len check (all LE) */
2174 len
= (u16
) (pkt
->len
);
2175 *(__le16
*) frame
= cpu_to_le16(len
);
2176 *(((__le16
*) frame
) + 1) = cpu_to_le16(~len
);
2178 /* Software tag: channel, sequence number, data offset */
2180 ((chan
<< SDPCM_CHANNEL_SHIFT
) & SDPCM_CHANNEL_MASK
) | bus
->tx_seq
|
2182 SDPCM_HDRLEN
) << SDPCM_DOFFSET_SHIFT
) & SDPCM_DOFFSET_MASK
);
2184 put_unaligned_le32(swheader
, frame
+ SDPCM_FRAMETAG_LEN
);
2185 put_unaligned_le32(0, frame
+ SDPCM_FRAMETAG_LEN
+ sizeof(swheader
));
2188 tx_packets
[pkt
->priority
]++;
2189 if (BRCMF_BYTES_ON() &&
2190 (((BRCMF_CTL_ON() && (chan
== SDPCM_CONTROL_CHANNEL
)) ||
2191 (BRCMF_DATA_ON() && (chan
!= SDPCM_CONTROL_CHANNEL
))))) {
2192 printk(KERN_DEBUG
"Tx Frame:\n");
2193 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET
, frame
, len
);
2194 } else if (BRCMF_HDRS_ON()) {
2195 printk(KERN_DEBUG
"TxHdr:\n");
2196 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET
,
2197 frame
, min_t(u16
, len
, 16));
2201 /* Raise len to next SDIO block to eliminate tail command */
2202 if (bus
->roundup
&& bus
->blocksize
&& (len
> bus
->blocksize
)) {
2203 u16 pad
= bus
->blocksize
- (len
% bus
->blocksize
);
2204 if ((pad
<= bus
->roundup
) && (pad
< bus
->blocksize
))
2206 } else if (len
% BRCMF_SDALIGN
) {
2207 len
+= BRCMF_SDALIGN
- (len
% BRCMF_SDALIGN
);
2210 /* Some controllers have trouble with odd bytes -- round to even */
2211 if (len
& (ALIGNMENT
- 1))
2212 len
= roundup(len
, ALIGNMENT
);
2214 ret
= brcmf_sdbrcm_send_buf(bus
, bus
->sdiodev
->sbwad
,
2215 SDIO_FUNC_2
, F2SYNC
, frame
,
2220 /* On failure, abort the command and terminate the frame */
2221 brcmf_dbg(INFO
, "sdio error %d, abort command and terminate frame\n",
2225 brcmf_sdcard_abort(bus
->sdiodev
, SDIO_FUNC_2
);
2226 brcmf_sdcard_cfg_write(bus
->sdiodev
, SDIO_FUNC_1
,
2227 SBSDIO_FUNC1_FRAMECTRL
, SFC_WF_TERM
,
2231 for (i
= 0; i
< 3; i
++) {
2233 hi
= brcmf_sdcard_cfg_read(bus
->sdiodev
,
2235 SBSDIO_FUNC1_WFRAMEBCHI
,
2237 lo
= brcmf_sdcard_cfg_read(bus
->sdiodev
,
2239 SBSDIO_FUNC1_WFRAMEBCLO
,
2241 bus
->f1regdata
+= 2;
2242 if ((hi
== 0) && (lo
== 0))
2248 bus
->tx_seq
= (bus
->tx_seq
+ 1) % SDPCM_SEQUENCE_WRAP
;
2251 /* restore pkt buffer pointer before calling tx complete routine */
2252 skb_pull(pkt
, SDPCM_HDRLEN
+ pad
);
2254 brcmf_txcomplete(bus
->drvr
, pkt
, ret
!= 0);
2258 brcmu_pkt_buf_free_skb(pkt
);
2263 static uint
brcmf_sdbrcm_sendfromq(struct brcmf_bus
*bus
, uint maxframes
)
2265 struct sk_buff
*pkt
;
2268 int ret
= 0, prec_out
;
2273 struct brcmf_pub
*drvr
= bus
->drvr
;
2275 brcmf_dbg(TRACE
, "Enter\n");
2277 tx_prec_map
= ~bus
->flowcontrol
;
2279 /* Send frames until the limit or some other event */
2280 for (cnt
= 0; (cnt
< maxframes
) && data_ok(bus
); cnt
++) {
2281 spin_lock_bh(&bus
->txqlock
);
2282 pkt
= brcmu_pktq_mdeq(&bus
->txq
, tx_prec_map
, &prec_out
);
2284 spin_unlock_bh(&bus
->txqlock
);
2287 spin_unlock_bh(&bus
->txqlock
);
2288 datalen
= pkt
->len
- SDPCM_HDRLEN
;
2290 ret
= brcmf_sdbrcm_txpkt(bus
, pkt
, SDPCM_DATA_CHANNEL
, true);
2292 bus
->drvr
->tx_errors
++;
2294 bus
->drvr
->dstats
.tx_bytes
+= datalen
;
2296 /* In poll mode, need to check for other events */
2297 if (!bus
->intr
&& cnt
) {
2298 /* Check device status, signal pending interrupt */
2299 r_sdreg32(bus
, &intstatus
,
2300 offsetof(struct sdpcmd_regs
, intstatus
),
2303 if (brcmf_sdcard_regfail(bus
->sdiodev
))
2305 if (intstatus
& bus
->hostintmask
)
2310 /* Deflow-control stack if needed */
2311 if (drvr
->up
&& (drvr
->busstate
== BRCMF_BUS_DATA
) &&
2312 drvr
->txoff
&& (pktq_len(&bus
->txq
) < TXLOW
))
2313 brcmf_txflowcontrol(drvr
, 0, OFF
);
2318 static bool brcmf_sdbrcm_dpc(struct brcmf_bus
*bus
)
2320 u32 intstatus
, newstatus
= 0;
2322 uint rxlimit
= bus
->rxbound
; /* Rx frames to read before resched */
2323 uint txlimit
= bus
->txbound
; /* Tx frames to send before resched */
2324 uint framecnt
= 0; /* Temporary counter of tx/rx frames */
2325 bool rxdone
= true; /* Flag for no more read data */
2326 bool resched
= false; /* Flag indicating resched wanted */
2328 brcmf_dbg(TRACE
, "Enter\n");
2330 /* Start with leftover status bits */
2331 intstatus
= bus
->intstatus
;
2335 /* If waiting for HTAVAIL, check status */
2336 if (bus
->clkstate
== CLK_PENDING
) {
2338 u8 clkctl
, devctl
= 0;
2341 /* Check for inconsistent device control */
2342 devctl
= brcmf_sdcard_cfg_read(bus
->sdiodev
, SDIO_FUNC_1
,
2343 SBSDIO_DEVICE_CTL
, &err
);
2345 brcmf_dbg(ERROR
, "error reading DEVCTL: %d\n", err
);
2346 bus
->drvr
->busstate
= BRCMF_BUS_DOWN
;
2350 /* Read CSR, if clock on switch to AVAIL, else ignore */
2351 clkctl
= brcmf_sdcard_cfg_read(bus
->sdiodev
, SDIO_FUNC_1
,
2352 SBSDIO_FUNC1_CHIPCLKCSR
, &err
);
2354 brcmf_dbg(ERROR
, "error reading CSR: %d\n",
2356 bus
->drvr
->busstate
= BRCMF_BUS_DOWN
;
2359 brcmf_dbg(INFO
, "DPC: PENDING, devctl 0x%02x clkctl 0x%02x\n",
2362 if (SBSDIO_HTAV(clkctl
)) {
2363 devctl
= brcmf_sdcard_cfg_read(bus
->sdiodev
,
2365 SBSDIO_DEVICE_CTL
, &err
);
2367 brcmf_dbg(ERROR
, "error reading DEVCTL: %d\n",
2369 bus
->drvr
->busstate
= BRCMF_BUS_DOWN
;
2371 devctl
&= ~SBSDIO_DEVCTL_CA_INT_ONLY
;
2372 brcmf_sdcard_cfg_write(bus
->sdiodev
, SDIO_FUNC_1
,
2373 SBSDIO_DEVICE_CTL
, devctl
, &err
);
2375 brcmf_dbg(ERROR
, "error writing DEVCTL: %d\n",
2377 bus
->drvr
->busstate
= BRCMF_BUS_DOWN
;
2379 bus
->clkstate
= CLK_AVAIL
;
2387 /* Make sure backplane clock is on */
2388 brcmf_sdbrcm_clkctl(bus
, CLK_AVAIL
, true);
2389 if (bus
->clkstate
== CLK_PENDING
)
2392 /* Pending interrupt indicates new device status */
2395 r_sdreg32(bus
, &newstatus
,
2396 offsetof(struct sdpcmd_regs
, intstatus
), &retries
);
2398 if (brcmf_sdcard_regfail(bus
->sdiodev
))
2400 newstatus
&= bus
->hostintmask
;
2401 bus
->fcstate
= !!(newstatus
& I_HMB_FC_STATE
);
2403 w_sdreg32(bus
, newstatus
,
2404 offsetof(struct sdpcmd_regs
, intstatus
),
2410 /* Merge new bits with previous */
2411 intstatus
|= newstatus
;
2414 /* Handle flow-control change: read new state in case our ack
2415 * crossed another change interrupt. If change still set, assume
2416 * FC ON for safety, let next loop through do the debounce.
2418 if (intstatus
& I_HMB_FC_CHANGE
) {
2419 intstatus
&= ~I_HMB_FC_CHANGE
;
2420 w_sdreg32(bus
, I_HMB_FC_CHANGE
,
2421 offsetof(struct sdpcmd_regs
, intstatus
), &retries
);
2423 r_sdreg32(bus
, &newstatus
,
2424 offsetof(struct sdpcmd_regs
, intstatus
), &retries
);
2425 bus
->f1regdata
+= 2;
2427 !!(newstatus
& (I_HMB_FC_STATE
| I_HMB_FC_CHANGE
));
2428 intstatus
|= (newstatus
& bus
->hostintmask
);
2431 /* Handle host mailbox indication */
2432 if (intstatus
& I_HMB_HOST_INT
) {
2433 intstatus
&= ~I_HMB_HOST_INT
;
2434 intstatus
|= brcmf_sdbrcm_hostmail(bus
);
2437 /* Generally don't ask for these, can get CRC errors... */
2438 if (intstatus
& I_WR_OOSYNC
) {
2439 brcmf_dbg(ERROR
, "Dongle reports WR_OOSYNC\n");
2440 intstatus
&= ~I_WR_OOSYNC
;
2443 if (intstatus
& I_RD_OOSYNC
) {
2444 brcmf_dbg(ERROR
, "Dongle reports RD_OOSYNC\n");
2445 intstatus
&= ~I_RD_OOSYNC
;
2448 if (intstatus
& I_SBINT
) {
2449 brcmf_dbg(ERROR
, "Dongle reports SBINT\n");
2450 intstatus
&= ~I_SBINT
;
2453 /* Would be active due to wake-wlan in gSPI */
2454 if (intstatus
& I_CHIPACTIVE
) {
2455 brcmf_dbg(INFO
, "Dongle reports CHIPACTIVE\n");
2456 intstatus
&= ~I_CHIPACTIVE
;
2459 /* Ignore frame indications if rxskip is set */
2461 intstatus
&= ~I_HMB_FRAME_IND
;
2463 /* On frame indication, read available frames */
2464 if (PKT_AVAILABLE()) {
2465 framecnt
= brcmf_sdbrcm_readframes(bus
, rxlimit
, &rxdone
);
2466 if (rxdone
|| bus
->rxskip
)
2467 intstatus
&= ~I_HMB_FRAME_IND
;
2468 rxlimit
-= min(framecnt
, rxlimit
);
2471 /* Keep still-pending events for next scheduling */
2472 bus
->intstatus
= intstatus
;
2475 if (data_ok(bus
) && bus
->ctrl_frame_stat
&&
2476 (bus
->clkstate
== CLK_AVAIL
)) {
2479 ret
= brcmf_sdbrcm_send_buf(bus
, bus
->sdiodev
->sbwad
,
2480 SDIO_FUNC_2
, F2SYNC
, (u8
*) bus
->ctrl_frame_buf
,
2481 (u32
) bus
->ctrl_frame_len
, NULL
);
2484 /* On failure, abort the command and
2485 terminate the frame */
2486 brcmf_dbg(INFO
, "sdio error %d, abort command and terminate frame\n",
2490 brcmf_sdcard_abort(bus
->sdiodev
, SDIO_FUNC_2
);
2492 brcmf_sdcard_cfg_write(bus
->sdiodev
, SDIO_FUNC_1
,
2493 SBSDIO_FUNC1_FRAMECTRL
, SFC_WF_TERM
,
2497 for (i
= 0; i
< 3; i
++) {
2499 hi
= brcmf_sdcard_cfg_read(bus
->sdiodev
,
2501 SBSDIO_FUNC1_WFRAMEBCHI
,
2503 lo
= brcmf_sdcard_cfg_read(bus
->sdiodev
,
2505 SBSDIO_FUNC1_WFRAMEBCLO
,
2507 bus
->f1regdata
+= 2;
2508 if ((hi
== 0) && (lo
== 0))
2514 bus
->tx_seq
= (bus
->tx_seq
+ 1) % SDPCM_SEQUENCE_WRAP
;
2516 brcmf_dbg(INFO
, "Return_dpc value is : %d\n", ret
);
2517 bus
->ctrl_frame_stat
= false;
2518 brcmf_sdbrcm_wait_event_wakeup(bus
);
2520 /* Send queued frames (limit 1 if rx may still be pending) */
2521 else if ((bus
->clkstate
== CLK_AVAIL
) && !bus
->fcstate
&&
2522 brcmu_pktq_mlen(&bus
->txq
, ~bus
->flowcontrol
) && txlimit
2524 framecnt
= rxdone
? txlimit
: min(txlimit
, bus
->txminmax
);
2525 framecnt
= brcmf_sdbrcm_sendfromq(bus
, framecnt
);
2526 txlimit
-= framecnt
;
2529 /* Resched if events or tx frames are pending,
2530 else await next interrupt */
2531 /* On failed register access, all bets are off:
2532 no resched or interrupts */
2533 if ((bus
->drvr
->busstate
== BRCMF_BUS_DOWN
) ||
2534 brcmf_sdcard_regfail(bus
->sdiodev
)) {
2535 brcmf_dbg(ERROR
, "failed backplane access over SDIO, halting operation %d\n",
2536 brcmf_sdcard_regfail(bus
->sdiodev
));
2537 bus
->drvr
->busstate
= BRCMF_BUS_DOWN
;
2539 } else if (bus
->clkstate
== CLK_PENDING
) {
2540 brcmf_dbg(INFO
, "rescheduled due to CLK_PENDING awaiting I_CHIPACTIVE interrupt\n");
2542 } else if (bus
->intstatus
|| bus
->ipend
||
2543 (!bus
->fcstate
&& brcmu_pktq_mlen(&bus
->txq
, ~bus
->flowcontrol
)
2544 && data_ok(bus
)) || PKT_AVAILABLE()) {
2548 bus
->dpc_sched
= resched
;
2550 /* If we're done for now, turn off clock request. */
2551 if ((bus
->clkstate
!= CLK_PENDING
)
2552 && bus
->idletime
== BRCMF_IDLE_IMMEDIATE
) {
2553 bus
->activity
= false;
2554 brcmf_sdbrcm_clkctl(bus
, CLK_NONE
, false);
2562 static int brcmf_sdbrcm_dpc_thread(void *data
)
2564 struct brcmf_bus
*bus
= (struct brcmf_bus
*) data
;
2566 allow_signal(SIGTERM
);
2567 /* Run until signal received */
2569 if (kthread_should_stop())
2571 if (!wait_for_completion_interruptible(&bus
->dpc_wait
)) {
2572 /* Call bus dpc unless it indicated down
2573 (then clean stop) */
2574 if (bus
->drvr
->busstate
!= BRCMF_BUS_DOWN
) {
2575 if (brcmf_sdbrcm_dpc(bus
))
2576 complete(&bus
->dpc_wait
);
2578 /* after stopping the bus, exit thread */
2579 brcmf_sdbrcm_bus_stop(bus
);
2580 bus
->dpc_tsk
= NULL
;
2589 int brcmf_sdbrcm_bus_txdata(struct brcmf_bus
*bus
, struct sk_buff
*pkt
)
2594 brcmf_dbg(TRACE
, "Enter\n");
2598 /* Add space for the header */
2599 skb_push(pkt
, SDPCM_HDRLEN
);
2600 /* precondition: IS_ALIGNED((unsigned long)(pkt->data), 2) */
2602 prec
= prio2prec((pkt
->priority
& PRIOMASK
));
2604 /* Check for existing queue, current flow-control,
2605 pending event, or pending clock */
2606 brcmf_dbg(TRACE
, "deferring pktq len %d\n", pktq_len(&bus
->txq
));
2609 /* Priority based enq */
2610 spin_lock_bh(&bus
->txqlock
);
2611 if (brcmf_c_prec_enq(bus
->drvr
, &bus
->txq
, pkt
, prec
) == false) {
2612 skb_pull(pkt
, SDPCM_HDRLEN
);
2613 brcmf_txcomplete(bus
->drvr
, pkt
, false);
2614 brcmu_pkt_buf_free_skb(pkt
);
2615 brcmf_dbg(ERROR
, "out of bus->txq !!!\n");
2620 spin_unlock_bh(&bus
->txqlock
);
2622 if (pktq_len(&bus
->txq
) >= TXHI
)
2623 brcmf_txflowcontrol(bus
->drvr
, 0, ON
);
2626 if (pktq_plen(&bus
->txq
, prec
) > qcount
[prec
])
2627 qcount
[prec
] = pktq_plen(&bus
->txq
, prec
);
2629 /* Schedule DPC if needed to send queued packet(s) */
2630 if (!bus
->dpc_sched
) {
2631 bus
->dpc_sched
= true;
2633 complete(&bus
->dpc_wait
);
2640 brcmf_sdbrcm_membytes(struct brcmf_bus
*bus
, bool write
, u32 address
, u8
*data
,
2647 /* Determine initial transfer parameters */
2648 sdaddr
= address
& SBSDIO_SB_OFT_ADDR_MASK
;
2649 if ((sdaddr
+ size
) & SBSDIO_SBWINDOW_MASK
)
2650 dsize
= (SBSDIO_SB_OFT_ADDR_LIMIT
- sdaddr
);
2654 /* Set the backplane window to include the start address */
2655 bcmerror
= brcmf_sdcard_set_sbaddr_window(bus
->sdiodev
, address
);
2657 brcmf_dbg(ERROR
, "window change failed\n");
2661 /* Do the transfer(s) */
2663 brcmf_dbg(INFO
, "%s %d bytes at offset 0x%08x in window 0x%08x\n",
2664 write
? "write" : "read", dsize
,
2665 sdaddr
, address
& SBSDIO_SBWINDOW_MASK
);
2666 bcmerror
= brcmf_sdcard_rwdata(bus
->sdiodev
, write
,
2667 sdaddr
, data
, dsize
);
2669 brcmf_dbg(ERROR
, "membytes transfer failed\n");
2673 /* Adjust for next transfer (if any) */
2678 bcmerror
= brcmf_sdcard_set_sbaddr_window(bus
->sdiodev
,
2681 brcmf_dbg(ERROR
, "window change failed\n");
2685 dsize
= min_t(uint
, SBSDIO_SB_OFT_ADDR_LIMIT
, size
);
2690 /* Return the window to backplane enumeration space for core access */
2691 if (brcmf_sdcard_set_sbaddr_window(bus
->sdiodev
, bus
->sdiodev
->sbwad
))
2692 brcmf_dbg(ERROR
, "FAILED to set window back to 0x%x\n",
2693 bus
->sdiodev
->sbwad
);
2699 #define CONSOLE_LINE_MAX 192
2701 static int brcmf_sdbrcm_readconsole(struct brcmf_bus
*bus
)
2703 struct brcmf_console
*c
= &bus
->console
;
2704 u8 line
[CONSOLE_LINE_MAX
], ch
;
2708 /* Don't do anything until FWREADY updates console address */
2709 if (bus
->console_addr
== 0)
2712 /* Read console log struct */
2713 addr
= bus
->console_addr
+ offsetof(struct rte_console
, log_le
);
2714 rv
= brcmf_sdbrcm_membytes(bus
, false, addr
, (u8
*)&c
->log_le
,
2719 /* Allocate console buffer (one time only) */
2720 if (c
->buf
== NULL
) {
2721 c
->bufsize
= le32_to_cpu(c
->log_le
.buf_size
);
2722 c
->buf
= kmalloc(c
->bufsize
, GFP_ATOMIC
);
2727 idx
= le32_to_cpu(c
->log_le
.idx
);
2729 /* Protect against corrupt value */
2730 if (idx
> c
->bufsize
)
2733 /* Skip reading the console buffer if the index pointer
2738 /* Read the console buffer */
2739 addr
= le32_to_cpu(c
->log_le
.buf
);
2740 rv
= brcmf_sdbrcm_membytes(bus
, false, addr
, c
->buf
, c
->bufsize
);
2744 while (c
->last
!= idx
) {
2745 for (n
= 0; n
< CONSOLE_LINE_MAX
- 2; n
++) {
2746 if (c
->last
== idx
) {
2747 /* This would output a partial line.
2749 * the buffer pointer and output this
2750 * line next time around.
2755 c
->last
= c
->bufsize
- n
;
2758 ch
= c
->buf
[c
->last
];
2759 c
->last
= (c
->last
+ 1) % c
->bufsize
;
2766 if (line
[n
- 1] == '\r')
2769 printk(KERN_DEBUG
"CONSOLE: %s\n", line
);
2778 static int brcmf_tx_frame(struct brcmf_bus
*bus
, u8
*frame
, u16 len
)
2783 bus
->ctrl_frame_stat
= false;
2784 ret
= brcmf_sdbrcm_send_buf(bus
, bus
->sdiodev
->sbwad
,
2785 SDIO_FUNC_2
, F2SYNC
, frame
, len
, NULL
);
2788 /* On failure, abort the command and terminate the frame */
2789 brcmf_dbg(INFO
, "sdio error %d, abort command and terminate frame\n",
2793 brcmf_sdcard_abort(bus
->sdiodev
, SDIO_FUNC_2
);
2795 brcmf_sdcard_cfg_write(bus
->sdiodev
, SDIO_FUNC_1
,
2796 SBSDIO_FUNC1_FRAMECTRL
,
2800 for (i
= 0; i
< 3; i
++) {
2802 hi
= brcmf_sdcard_cfg_read(bus
->sdiodev
, SDIO_FUNC_1
,
2803 SBSDIO_FUNC1_WFRAMEBCHI
,
2805 lo
= brcmf_sdcard_cfg_read(bus
->sdiodev
, SDIO_FUNC_1
,
2806 SBSDIO_FUNC1_WFRAMEBCLO
,
2808 bus
->f1regdata
+= 2;
2809 if (hi
== 0 && lo
== 0)
2815 bus
->tx_seq
= (bus
->tx_seq
+ 1) % SDPCM_SEQUENCE_WRAP
;
2821 brcmf_sdbrcm_bus_txctl(struct brcmf_bus
*bus
, unsigned char *msg
, uint msglen
)
2830 brcmf_dbg(TRACE
, "Enter\n");
2832 /* Back the pointer to make a room for bus header */
2833 frame
= msg
- SDPCM_HDRLEN
;
2834 len
= (msglen
+= SDPCM_HDRLEN
);
2836 /* Add alignment padding (optional for ctl frames) */
2837 doff
= ((unsigned long)frame
% BRCMF_SDALIGN
);
2842 memset(frame
, 0, doff
+ SDPCM_HDRLEN
);
2844 /* precondition: doff < BRCMF_SDALIGN */
2845 doff
+= SDPCM_HDRLEN
;
2847 /* Round send length to next SDIO block */
2848 if (bus
->roundup
&& bus
->blocksize
&& (len
> bus
->blocksize
)) {
2849 u16 pad
= bus
->blocksize
- (len
% bus
->blocksize
);
2850 if ((pad
<= bus
->roundup
) && (pad
< bus
->blocksize
))
2852 } else if (len
% BRCMF_SDALIGN
) {
2853 len
+= BRCMF_SDALIGN
- (len
% BRCMF_SDALIGN
);
2856 /* Satisfy length-alignment requirements */
2857 if (len
& (ALIGNMENT
- 1))
2858 len
= roundup(len
, ALIGNMENT
);
2860 /* precondition: IS_ALIGNED((unsigned long)frame, 2) */
2862 /* Need to lock here to protect txseq and SDIO tx calls */
2867 /* Make sure backplane clock is on */
2868 brcmf_sdbrcm_clkctl(bus
, CLK_AVAIL
, false);
2870 /* Hardware tag: 2 byte len followed by 2 byte ~len check (all LE) */
2871 *(__le16
*) frame
= cpu_to_le16((u16
) msglen
);
2872 *(((__le16
*) frame
) + 1) = cpu_to_le16(~msglen
);
2874 /* Software tag: channel, sequence number, data offset */
2876 ((SDPCM_CONTROL_CHANNEL
<< SDPCM_CHANNEL_SHIFT
) &
2878 | bus
->tx_seq
| ((doff
<< SDPCM_DOFFSET_SHIFT
) &
2879 SDPCM_DOFFSET_MASK
);
2880 put_unaligned_le32(swheader
, frame
+ SDPCM_FRAMETAG_LEN
);
2881 put_unaligned_le32(0, frame
+ SDPCM_FRAMETAG_LEN
+ sizeof(swheader
));
2883 if (!data_ok(bus
)) {
2884 brcmf_dbg(INFO
, "No bus credit bus->tx_max %d, bus->tx_seq %d\n",
2885 bus
->tx_max
, bus
->tx_seq
);
2886 bus
->ctrl_frame_stat
= true;
2888 bus
->ctrl_frame_buf
= frame
;
2889 bus
->ctrl_frame_len
= len
;
2891 brcmf_sdbrcm_wait_for_event(bus
, &bus
->ctrl_frame_stat
);
2893 if (bus
->ctrl_frame_stat
== false) {
2894 brcmf_dbg(INFO
, "ctrl_frame_stat == false\n");
2897 brcmf_dbg(INFO
, "ctrl_frame_stat == true\n");
2904 if (BRCMF_BYTES_ON() && BRCMF_CTL_ON()) {
2905 printk(KERN_DEBUG
"Tx Frame:\n");
2906 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET
,
2908 } else if (BRCMF_HDRS_ON()) {
2909 printk(KERN_DEBUG
"TxHdr:\n");
2910 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET
,
2911 frame
, min_t(u16
, len
, 16));
2916 ret
= brcmf_tx_frame(bus
, frame
, len
);
2917 } while (ret
< 0 && retries
++ < TXRETRIES
);
2920 if ((bus
->idletime
== BRCMF_IDLE_IMMEDIATE
) && !bus
->dpc_sched
) {
2921 bus
->activity
= false;
2922 brcmf_sdbrcm_clkctl(bus
, CLK_NONE
, true);
2928 bus
->drvr
->tx_ctlerrs
++;
2930 bus
->drvr
->tx_ctlpkts
++;
2932 return ret
? -EIO
: 0;
2936 brcmf_sdbrcm_bus_rxctl(struct brcmf_bus
*bus
, unsigned char *msg
, uint msglen
)
2942 brcmf_dbg(TRACE
, "Enter\n");
2944 /* Wait until control frame is available */
2945 timeleft
= brcmf_sdbrcm_dcmd_resp_wait(bus
, &bus
->rxlen
, &pending
);
2949 memcpy(msg
, bus
->rxctl
, min(msglen
, rxlen
));
2954 brcmf_dbg(CTL
, "resumed on rxctl frame, got %d expected %d\n",
2956 } else if (timeleft
== 0) {
2957 brcmf_dbg(ERROR
, "resumed on timeout\n");
2958 } else if (pending
== true) {
2959 brcmf_dbg(CTL
, "cancelled\n");
2960 return -ERESTARTSYS
;
2962 brcmf_dbg(CTL
, "resumed for unknown reason?\n");
2966 bus
->drvr
->rx_ctlpkts
++;
2968 bus
->drvr
->rx_ctlerrs
++;
2970 return rxlen
? (int)rxlen
: -ETIMEDOUT
;
2973 static int brcmf_sdbrcm_downloadvars(struct brcmf_bus
*bus
, void *arg
, int len
)
2977 brcmf_dbg(TRACE
, "Enter\n");
2979 /* Basic sanity checks */
2980 if (bus
->drvr
->up
) {
2981 bcmerror
= -EISCONN
;
2985 bcmerror
= -EOVERFLOW
;
2989 /* Free the old ones and replace with passed variables */
2992 bus
->vars
= kmalloc(len
, GFP_ATOMIC
);
2993 bus
->varsz
= bus
->vars
? len
: 0;
2994 if (bus
->vars
== NULL
) {
2999 /* Copy the passed variables, which should include the
3000 terminating double-null */
3001 memcpy(bus
->vars
, arg
, bus
->varsz
);
3006 static int brcmf_sdbrcm_write_vars(struct brcmf_bus
*bus
)
3015 char *nvram_ularray
;
3018 /* Even if there are no vars are to be written, we still
3019 need to set the ramsize. */
3020 varsize
= bus
->varsz
? roundup(bus
->varsz
, 4) : 0;
3021 varaddr
= (bus
->ramsize
- 4) - varsize
;
3024 vbuffer
= kzalloc(varsize
, GFP_ATOMIC
);
3028 memcpy(vbuffer
, bus
->vars
, bus
->varsz
);
3030 /* Write the vars list */
3032 brcmf_sdbrcm_membytes(bus
, true, varaddr
, vbuffer
, varsize
);
3034 /* Verify NVRAM bytes */
3035 brcmf_dbg(INFO
, "Compare NVRAM dl & ul; varsize=%d\n", varsize
);
3036 nvram_ularray
= kmalloc(varsize
, GFP_ATOMIC
);
3040 /* Upload image to verify downloaded contents. */
3041 memset(nvram_ularray
, 0xaa, varsize
);
3043 /* Read the vars list to temp buffer for comparison */
3045 brcmf_sdbrcm_membytes(bus
, false, varaddr
, nvram_ularray
,
3048 brcmf_dbg(ERROR
, "error %d on reading %d nvram bytes at 0x%08x\n",
3049 bcmerror
, varsize
, varaddr
);
3051 /* Compare the org NVRAM with the one read from RAM */
3052 if (memcmp(vbuffer
, nvram_ularray
, varsize
))
3053 brcmf_dbg(ERROR
, "Downloaded NVRAM image is corrupted\n");
3055 brcmf_dbg(ERROR
, "Download/Upload/Compare of NVRAM ok\n");
3057 kfree(nvram_ularray
);
3063 /* adjust to the user specified RAM */
3064 brcmf_dbg(INFO
, "Physical memory size: %d\n", bus
->ramsize
);
3065 brcmf_dbg(INFO
, "Vars are at %d, orig varsize is %d\n",
3067 varsize
= ((bus
->ramsize
- 4) - varaddr
);
3070 * Determine the length token:
3071 * Varsize, converted to words, in lower 16-bits, checksum
3076 varsizew_le
= cpu_to_le32(0);
3078 varsizew
= varsize
/ 4;
3079 varsizew
= (~varsizew
<< 16) | (varsizew
& 0x0000FFFF);
3080 varsizew_le
= cpu_to_le32(varsizew
);
3083 brcmf_dbg(INFO
, "New varsize is %d, length token=0x%08x\n",
3086 /* Write the length token to the last word */
3087 bcmerror
= brcmf_sdbrcm_membytes(bus
, true, (bus
->ramsize
- 4),
3088 (u8
*)&varsizew_le
, 4);
3094 brcmf_sdbrcm_chip_resetcore(struct brcmf_sdio_dev
*sdiodev
, u32 corebase
)
3099 * Must do the disable sequence first to work for
3100 * arbitrary current core state.
3102 brcmf_sdio_chip_coredisable(sdiodev
, corebase
);
3105 * Now do the initialization sequence.
3106 * set reset while enabling the clock and
3107 * forcing them on throughout the core
3109 brcmf_sdcard_reg_write(sdiodev
, CORE_SB(corebase
, sbtmstatelow
), 4,
3110 ((SICF_FGC
| SICF_CLOCK_EN
) << SBTML_SICF_SHIFT
) |
3114 regdata
= brcmf_sdcard_reg_read(sdiodev
,
3115 CORE_SB(corebase
, sbtmstatehigh
), 4);
3116 if (regdata
& SBTMH_SERR
)
3117 brcmf_sdcard_reg_write(sdiodev
,
3118 CORE_SB(corebase
, sbtmstatehigh
), 4, 0);
3120 regdata
= brcmf_sdcard_reg_read(sdiodev
,
3121 CORE_SB(corebase
, sbimstate
), 4);
3122 if (regdata
& (SBIM_IBE
| SBIM_TO
))
3123 brcmf_sdcard_reg_write(sdiodev
, CORE_SB(corebase
, sbimstate
), 4,
3124 regdata
& ~(SBIM_IBE
| SBIM_TO
));
3126 /* clear reset and allow it to propagate throughout the core */
3127 brcmf_sdcard_reg_write(sdiodev
, CORE_SB(corebase
, sbtmstatelow
), 4,
3128 (SICF_FGC
<< SBTML_SICF_SHIFT
) |
3129 (SICF_CLOCK_EN
<< SBTML_SICF_SHIFT
));
3132 /* leave clock enabled */
3133 brcmf_sdcard_reg_write(sdiodev
, CORE_SB(corebase
, sbtmstatelow
), 4,
3134 (SICF_CLOCK_EN
<< SBTML_SICF_SHIFT
));
3138 static int brcmf_sdbrcm_download_state(struct brcmf_bus
*bus
, bool enter
)
3144 /* To enter download state, disable ARM and reset SOCRAM.
3145 * To exit download state, simply reset ARM (default is RAM boot).
3148 bus
->alp_only
= true;
3150 brcmf_sdio_chip_coredisable(bus
->sdiodev
,
3151 bus
->ci
->armcorebase
);
3153 brcmf_sdbrcm_chip_resetcore(bus
->sdiodev
, bus
->ci
->ramcorebase
);
3155 /* Clear the top bit of memory */
3158 brcmf_sdbrcm_membytes(bus
, true, bus
->ramsize
- 4,
3162 regdata
= brcmf_sdcard_reg_read(bus
->sdiodev
,
3163 CORE_SB(bus
->ci
->ramcorebase
, sbtmstatelow
), 4);
3164 regdata
&= (SBTML_RESET
| SBTML_REJ_MASK
|
3165 (SICF_CLOCK_EN
<< SBTML_SICF_SHIFT
));
3166 if ((SICF_CLOCK_EN
<< SBTML_SICF_SHIFT
) != regdata
) {
3167 brcmf_dbg(ERROR
, "SOCRAM core is down after reset?\n");
3172 bcmerror
= brcmf_sdbrcm_write_vars(bus
);
3174 brcmf_dbg(ERROR
, "no vars written to RAM\n");
3178 w_sdreg32(bus
, 0xFFFFFFFF,
3179 offsetof(struct sdpcmd_regs
, intstatus
), &retries
);
3181 brcmf_sdbrcm_chip_resetcore(bus
->sdiodev
, bus
->ci
->armcorebase
);
3183 /* Allow HT Clock now that the ARM is running. */
3184 bus
->alp_only
= false;
3186 bus
->drvr
->busstate
= BRCMF_BUS_LOAD
;
3192 static int brcmf_sdbrcm_get_image(char *buf
, int len
, struct brcmf_bus
*bus
)
3194 if (bus
->firmware
->size
< bus
->fw_ptr
+ len
)
3195 len
= bus
->firmware
->size
- bus
->fw_ptr
;
3197 memcpy(buf
, &bus
->firmware
->data
[bus
->fw_ptr
], len
);
3202 MODULE_FIRMWARE(BCM4329_FW_NAME
);
3203 MODULE_FIRMWARE(BCM4329_NV_NAME
);
3205 static int brcmf_sdbrcm_download_code_file(struct brcmf_bus
*bus
)
3209 u8
*memblock
= NULL
, *memptr
;
3212 brcmf_dbg(INFO
, "Enter\n");
3214 bus
->fw_name
= BCM4329_FW_NAME
;
3215 ret
= request_firmware(&bus
->firmware
, bus
->fw_name
,
3216 &bus
->sdiodev
->func
[2]->dev
);
3218 brcmf_dbg(ERROR
, "Fail to request firmware %d\n", ret
);
3223 memptr
= memblock
= kmalloc(MEMBLOCK
+ BRCMF_SDALIGN
, GFP_ATOMIC
);
3224 if (memblock
== NULL
) {
3228 if ((u32
)(unsigned long)memblock
% BRCMF_SDALIGN
)
3229 memptr
+= (BRCMF_SDALIGN
-
3230 ((u32
)(unsigned long)memblock
% BRCMF_SDALIGN
));
3232 /* Download image */
3234 brcmf_sdbrcm_get_image((char *)memptr
, MEMBLOCK
, bus
))) {
3235 ret
= brcmf_sdbrcm_membytes(bus
, true, offset
, memptr
, len
);
3237 brcmf_dbg(ERROR
, "error %d on writing %d membytes at 0x%08x\n",
3238 ret
, MEMBLOCK
, offset
);
3248 release_firmware(bus
->firmware
);
3255 * ProcessVars:Takes a buffer of "<var>=<value>\n" lines read from a file
3256 * and ending in a NUL.
3257 * Removes carriage returns, empty lines, comment lines, and converts
3259 * Shortens buffer as needed and pads with NULs. End of buffer is marked
3263 static uint
brcmf_process_nvram_vars(char *varbuf
, uint len
)
3272 findNewline
= false;
3275 for (n
= 0; n
< len
; n
++) {
3278 if (varbuf
[n
] == '\r')
3280 if (findNewline
&& varbuf
[n
] != '\n')
3282 findNewline
= false;
3283 if (varbuf
[n
] == '#') {
3287 if (varbuf
[n
] == '\n') {
3297 buf_len
= dp
- varbuf
;
3299 while (dp
< varbuf
+ n
)
3305 static int brcmf_sdbrcm_download_nvram(struct brcmf_bus
*bus
)
3308 char *memblock
= NULL
;
3312 bus
->nv_name
= BCM4329_NV_NAME
;
3313 ret
= request_firmware(&bus
->firmware
, bus
->nv_name
,
3314 &bus
->sdiodev
->func
[2]->dev
);
3316 brcmf_dbg(ERROR
, "Fail to request nvram %d\n", ret
);
3321 memblock
= kmalloc(MEMBLOCK
, GFP_ATOMIC
);
3322 if (memblock
== NULL
) {
3327 len
= brcmf_sdbrcm_get_image(memblock
, MEMBLOCK
, bus
);
3329 if (len
> 0 && len
< MEMBLOCK
) {
3330 bufp
= (char *)memblock
;
3332 len
= brcmf_process_nvram_vars(bufp
, len
);
3336 ret
= brcmf_sdbrcm_downloadvars(bus
, memblock
, len
+ 1);
3338 brcmf_dbg(ERROR
, "error downloading vars: %d\n", ret
);
3340 brcmf_dbg(ERROR
, "error reading nvram file: %d\n", len
);
3347 release_firmware(bus
->firmware
);
3353 static int _brcmf_sdbrcm_download_firmware(struct brcmf_bus
*bus
)
3357 /* Keep arm in reset */
3358 if (brcmf_sdbrcm_download_state(bus
, true)) {
3359 brcmf_dbg(ERROR
, "error placing ARM core in reset\n");
3363 /* External image takes precedence if specified */
3364 if (brcmf_sdbrcm_download_code_file(bus
)) {
3365 brcmf_dbg(ERROR
, "dongle image file download failed\n");
3369 /* External nvram takes precedence if specified */
3370 if (brcmf_sdbrcm_download_nvram(bus
))
3371 brcmf_dbg(ERROR
, "dongle nvram file download failed\n");
3373 /* Take arm out of reset */
3374 if (brcmf_sdbrcm_download_state(bus
, false)) {
3375 brcmf_dbg(ERROR
, "error getting out of ARM core reset\n");
3386 brcmf_sdbrcm_download_firmware(struct brcmf_bus
*bus
)
3390 /* Download the firmware */
3391 brcmf_sdbrcm_clkctl(bus
, CLK_AVAIL
, false);
3393 ret
= _brcmf_sdbrcm_download_firmware(bus
) == 0;
3395 brcmf_sdbrcm_clkctl(bus
, CLK_SDONLY
, false);
3400 void brcmf_sdbrcm_bus_stop(struct brcmf_bus
*bus
)
3402 u32 local_hostintmask
;
3406 struct sk_buff
*cur
;
3407 struct sk_buff
*next
;
3409 brcmf_dbg(TRACE
, "Enter\n");
3411 if (bus
->watchdog_tsk
) {
3412 send_sig(SIGTERM
, bus
->watchdog_tsk
, 1);
3413 kthread_stop(bus
->watchdog_tsk
);
3414 bus
->watchdog_tsk
= NULL
;
3417 if (bus
->dpc_tsk
&& bus
->dpc_tsk
!= current
) {
3418 send_sig(SIGTERM
, bus
->dpc_tsk
, 1);
3419 kthread_stop(bus
->dpc_tsk
);
3420 bus
->dpc_tsk
= NULL
;
3427 /* Enable clock for device interrupts */
3428 brcmf_sdbrcm_clkctl(bus
, CLK_AVAIL
, false);
3430 /* Disable and clear interrupts at the chip level also */
3431 w_sdreg32(bus
, 0, offsetof(struct sdpcmd_regs
, hostintmask
), &retries
);
3432 local_hostintmask
= bus
->hostintmask
;
3433 bus
->hostintmask
= 0;
3435 /* Change our idea of bus state */
3436 bus
->drvr
->busstate
= BRCMF_BUS_DOWN
;
3438 /* Force clocks on backplane to be sure F2 interrupt propagates */
3439 saveclk
= brcmf_sdcard_cfg_read(bus
->sdiodev
, SDIO_FUNC_1
,
3440 SBSDIO_FUNC1_CHIPCLKCSR
, &err
);
3442 brcmf_sdcard_cfg_write(bus
->sdiodev
, SDIO_FUNC_1
,
3443 SBSDIO_FUNC1_CHIPCLKCSR
,
3444 (saveclk
| SBSDIO_FORCE_HT
), &err
);
3447 brcmf_dbg(ERROR
, "Failed to force clock for F2: err %d\n", err
);
3449 /* Turn off the bus (F2), free any pending packets */
3450 brcmf_dbg(INTR
, "disable SDIO interrupts\n");
3451 brcmf_sdcard_cfg_write(bus
->sdiodev
, SDIO_FUNC_0
, SDIO_CCCR_IOEx
,
3452 SDIO_FUNC_ENABLE_1
, NULL
);
3454 /* Clear any pending interrupts now that F2 is disabled */
3455 w_sdreg32(bus
, local_hostintmask
,
3456 offsetof(struct sdpcmd_regs
, intstatus
), &retries
);
3458 /* Turn off the backplane clock (only) */
3459 brcmf_sdbrcm_clkctl(bus
, CLK_SDONLY
, false);
3461 /* Clear the data packet queues */
3462 brcmu_pktq_flush(&bus
->txq
, true, NULL
, NULL
);
3464 /* Clear any held glomming stuff */
3466 brcmu_pkt_buf_free_skb(bus
->glomd
);
3467 if (!skb_queue_empty(&bus
->glom
))
3468 skb_queue_walk_safe(&bus
->glom
, cur
, next
) {
3469 skb_unlink(cur
, &bus
->glom
);
3470 brcmu_pkt_buf_free_skb(cur
);
3473 /* Clear rx control and wake any waiters */
3475 brcmf_sdbrcm_dcmd_resp_wake(bus
);
3477 /* Reset some F2 state stuff */
3478 bus
->rxskip
= false;
3479 bus
->tx_seq
= bus
->rx_seq
= 0;
3484 int brcmf_sdbrcm_bus_init(struct brcmf_pub
*drvr
)
3486 struct brcmf_bus
*bus
= drvr
->bus
;
3487 unsigned long timeout
;
3493 brcmf_dbg(TRACE
, "Enter\n");
3495 /* try to download image and nvram to the dongle */
3496 if (drvr
->busstate
== BRCMF_BUS_DOWN
) {
3497 if (!(brcmf_sdbrcm_download_firmware(bus
)))
3504 /* Start the watchdog timer */
3505 bus
->drvr
->tickcnt
= 0;
3506 brcmf_sdbrcm_wd_timer(bus
, BRCMF_WD_POLL_MS
);
3510 /* Make sure backplane clock is on, needed to generate F2 interrupt */
3511 brcmf_sdbrcm_clkctl(bus
, CLK_AVAIL
, false);
3512 if (bus
->clkstate
!= CLK_AVAIL
)
3515 /* Force clocks on backplane to be sure F2 interrupt propagates */
3517 brcmf_sdcard_cfg_read(bus
->sdiodev
, SDIO_FUNC_1
,
3518 SBSDIO_FUNC1_CHIPCLKCSR
, &err
);
3520 brcmf_sdcard_cfg_write(bus
->sdiodev
, SDIO_FUNC_1
,
3521 SBSDIO_FUNC1_CHIPCLKCSR
,
3522 (saveclk
| SBSDIO_FORCE_HT
), &err
);
3525 brcmf_dbg(ERROR
, "Failed to force clock for F2: err %d\n", err
);
3529 /* Enable function 2 (frame transfers) */
3530 w_sdreg32(bus
, SDPCM_PROT_VERSION
<< SMB_DATA_VERSION_SHIFT
,
3531 offsetof(struct sdpcmd_regs
, tosbmailboxdata
), &retries
);
3532 enable
= (SDIO_FUNC_ENABLE_1
| SDIO_FUNC_ENABLE_2
);
3534 brcmf_sdcard_cfg_write(bus
->sdiodev
, SDIO_FUNC_0
, SDIO_CCCR_IOEx
,
3537 timeout
= jiffies
+ msecs_to_jiffies(BRCMF_WAIT_F2RDY
);
3539 while (enable
!= ready
) {
3540 ready
= brcmf_sdcard_cfg_read(bus
->sdiodev
, SDIO_FUNC_0
,
3541 SDIO_CCCR_IORx
, NULL
);
3542 if (time_after(jiffies
, timeout
))
3544 else if (time_after(jiffies
, timeout
- BRCMF_WAIT_F2RDY
+ 50))
3545 /* prevent busy waiting if it takes too long */
3546 msleep_interruptible(20);
3549 brcmf_dbg(INFO
, "enable 0x%02x, ready 0x%02x\n", enable
, ready
);
3551 /* If F2 successfully enabled, set core and enable interrupts */
3552 if (ready
== enable
) {
3553 /* Set up the interrupt mask and enable interrupts */
3554 bus
->hostintmask
= HOSTINTMASK
;
3555 w_sdreg32(bus
, bus
->hostintmask
,
3556 offsetof(struct sdpcmd_regs
, hostintmask
), &retries
);
3558 brcmf_sdcard_cfg_write(bus
->sdiodev
, SDIO_FUNC_1
,
3559 SBSDIO_WATERMARK
, 8, &err
);
3561 /* Set bus state according to enable result */
3562 drvr
->busstate
= BRCMF_BUS_DATA
;
3566 /* Disable F2 again */
3567 enable
= SDIO_FUNC_ENABLE_1
;
3568 brcmf_sdcard_cfg_write(bus
->sdiodev
, SDIO_FUNC_0
,
3569 SDIO_CCCR_IOEx
, enable
, NULL
);
3572 /* Restore previous clock setting */
3573 brcmf_sdcard_cfg_write(bus
->sdiodev
, SDIO_FUNC_1
,
3574 SBSDIO_FUNC1_CHIPCLKCSR
, saveclk
, &err
);
3576 /* If we didn't come up, turn off backplane clock */
3577 if (drvr
->busstate
!= BRCMF_BUS_DATA
)
3578 brcmf_sdbrcm_clkctl(bus
, CLK_NONE
, false);
3586 void brcmf_sdbrcm_isr(void *arg
)
3588 struct brcmf_bus
*bus
= (struct brcmf_bus
*) arg
;
3590 brcmf_dbg(TRACE
, "Enter\n");
3593 brcmf_dbg(ERROR
, "bus is null pointer, exiting\n");
3597 if (bus
->drvr
->busstate
== BRCMF_BUS_DOWN
) {
3598 brcmf_dbg(ERROR
, "bus is down. we have nothing to do\n");
3601 /* Count the interrupt call */
3605 /* Shouldn't get this interrupt if we're sleeping? */
3606 if (bus
->sleeping
) {
3607 brcmf_dbg(ERROR
, "INTERRUPT WHILE SLEEPING??\n");
3611 /* Disable additional interrupts (is this needed now)? */
3613 brcmf_dbg(ERROR
, "isr w/o interrupt configured!\n");
3615 bus
->dpc_sched
= true;
3617 complete(&bus
->dpc_wait
);
3620 static bool brcmf_sdbrcm_bus_watchdog(struct brcmf_pub
*drvr
)
3622 struct brcmf_bus
*bus
;
3624 brcmf_dbg(TIMER
, "Enter\n");
3628 /* Ignore the timer if simulating bus down */
3634 /* Poll period: check device if appropriate. */
3635 if (bus
->poll
&& (++bus
->polltick
>= bus
->pollrate
)) {
3638 /* Reset poll tick */
3641 /* Check device if no interrupts */
3642 if (!bus
->intr
|| (bus
->intrcount
== bus
->lastintrs
)) {
3644 if (!bus
->dpc_sched
) {
3646 devpend
= brcmf_sdcard_cfg_read(bus
->sdiodev
,
3647 SDIO_FUNC_0
, SDIO_CCCR_INTx
,
3650 devpend
& (INTR_STATUS_FUNC1
|
3654 /* If there is something, make like the ISR and
3660 bus
->dpc_sched
= true;
3662 complete(&bus
->dpc_wait
);
3666 /* Update interrupt tracking */
3667 bus
->lastintrs
= bus
->intrcount
;
3670 /* Poll for console output periodically */
3671 if (drvr
->busstate
== BRCMF_BUS_DATA
&& bus
->console_interval
!= 0) {
3672 bus
->console
.count
+= BRCMF_WD_POLL_MS
;
3673 if (bus
->console
.count
>= bus
->console_interval
) {
3674 bus
->console
.count
-= bus
->console_interval
;
3675 /* Make sure backplane clock is on */
3676 brcmf_sdbrcm_clkctl(bus
, CLK_AVAIL
, false);
3677 if (brcmf_sdbrcm_readconsole(bus
) < 0)
3679 bus
->console_interval
= 0;
3684 /* On idle timeout clear activity flag and/or turn off clock */
3685 if ((bus
->idletime
> 0) && (bus
->clkstate
== CLK_AVAIL
)) {
3686 if (++bus
->idlecount
>= bus
->idletime
) {
3688 if (bus
->activity
) {
3689 bus
->activity
= false;
3690 brcmf_sdbrcm_wd_timer(bus
, BRCMF_WD_POLL_MS
);
3692 brcmf_sdbrcm_clkctl(bus
, CLK_NONE
, false);
3702 static bool brcmf_sdbrcm_chipmatch(u16 chipid
)
3704 if (chipid
== BCM4329_CHIP_ID
)
3709 static void brcmf_sdbrcm_release_malloc(struct brcmf_bus
*bus
)
3711 brcmf_dbg(TRACE
, "Enter\n");
3714 bus
->rxctl
= bus
->rxbuf
= NULL
;
3717 kfree(bus
->databuf
);
3718 bus
->databuf
= NULL
;
3721 static bool brcmf_sdbrcm_probe_malloc(struct brcmf_bus
*bus
)
3723 brcmf_dbg(TRACE
, "Enter\n");
3725 if (bus
->drvr
->maxctl
) {
3727 roundup((bus
->drvr
->maxctl
+ SDPCM_HDRLEN
),
3728 ALIGNMENT
) + BRCMF_SDALIGN
;
3729 bus
->rxbuf
= kmalloc(bus
->rxblen
, GFP_ATOMIC
);
3734 /* Allocate buffer to receive glomed packet */
3735 bus
->databuf
= kmalloc(MAX_DATA_BUF
, GFP_ATOMIC
);
3736 if (!(bus
->databuf
)) {
3737 /* release rxbuf which was already located as above */
3743 /* Align the buffer */
3744 if ((unsigned long)bus
->databuf
% BRCMF_SDALIGN
)
3745 bus
->dataptr
= bus
->databuf
+ (BRCMF_SDALIGN
-
3746 ((unsigned long)bus
->databuf
% BRCMF_SDALIGN
));
3748 bus
->dataptr
= bus
->databuf
;
3756 /* SDIO Pad drive strength to select value mappings */
3757 struct sdiod_drive_str
{
3758 u8 strength
; /* Pad Drive Strength in mA */
3759 u8 sel
; /* Chip-specific select value */
3762 /* SDIO Drive Strength to sel value table for PMU Rev 1 */
3763 static const struct sdiod_drive_str sdiod_drive_strength_tab1
[] = {
3771 /* SDIO Drive Strength to sel value table for PMU Rev 2, 3 */
3772 static const struct sdiod_drive_str sdiod_drive_strength_tab2
[] = {
3783 /* SDIO Drive Strength to sel value table for PMU Rev 8 (1.8V) */
3784 static const struct sdiod_drive_str sdiod_drive_strength_tab3
[] = {
3796 #define SDIOD_DRVSTR_KEY(chip, pmu) (((chip) << 16) | (pmu))
3798 static char *brcmf_chipname(uint chipid
, char *buf
, uint len
)
3802 fmt
= ((chipid
> 0xa000) || (chipid
< 0x4000)) ? "%d" : "%x";
3803 snprintf(buf
, len
, fmt
, chipid
);
3807 static void brcmf_sdbrcm_sdiod_drive_strength_init(struct brcmf_bus
*bus
,
3808 u32 drivestrength
) {
3809 struct sdiod_drive_str
*str_tab
= NULL
;
3814 if (!(bus
->ci
->cccaps
& CC_CAP_PMU
))
3817 switch (SDIOD_DRVSTR_KEY(bus
->ci
->chip
, bus
->ci
->pmurev
)) {
3818 case SDIOD_DRVSTR_KEY(BCM4325_CHIP_ID
, 1):
3819 str_tab
= (struct sdiod_drive_str
*)&sdiod_drive_strength_tab1
;
3820 str_mask
= 0x30000000;
3823 case SDIOD_DRVSTR_KEY(BCM4325_CHIP_ID
, 2):
3824 case SDIOD_DRVSTR_KEY(BCM4325_CHIP_ID
, 3):
3825 str_tab
= (struct sdiod_drive_str
*)&sdiod_drive_strength_tab2
;
3826 str_mask
= 0x00003800;
3829 case SDIOD_DRVSTR_KEY(BCM4336_CHIP_ID
, 8):
3830 str_tab
= (struct sdiod_drive_str
*)&sdiod_drive_strength_tab3
;
3831 str_mask
= 0x00003800;
3835 brcmf_dbg(ERROR
, "No SDIO Drive strength init done for chip %s rev %d pmurev %d\n",
3836 brcmf_chipname(bus
->ci
->chip
, chn
, 8),
3837 bus
->ci
->chiprev
, bus
->ci
->pmurev
);
3841 if (str_tab
!= NULL
) {
3842 u32 drivestrength_sel
= 0;
3846 for (i
= 0; str_tab
[i
].strength
!= 0; i
++) {
3847 if (drivestrength
>= str_tab
[i
].strength
) {
3848 drivestrength_sel
= str_tab
[i
].sel
;
3853 brcmf_sdcard_reg_write(bus
->sdiodev
,
3854 CORE_CC_REG(bus
->ci
->cccorebase
, chipcontrol_addr
),
3856 cc_data_temp
= brcmf_sdcard_reg_read(bus
->sdiodev
,
3857 CORE_CC_REG(bus
->ci
->cccorebase
, chipcontrol_addr
), 4);
3858 cc_data_temp
&= ~str_mask
;
3859 drivestrength_sel
<<= str_shift
;
3860 cc_data_temp
|= drivestrength_sel
;
3861 brcmf_sdcard_reg_write(bus
->sdiodev
,
3862 CORE_CC_REG(bus
->ci
->cccorebase
, chipcontrol_addr
),
3865 brcmf_dbg(INFO
, "SDIO: %dmA drive strength selected, set to 0x%08x\n",
3866 drivestrength
, cc_data_temp
);
3871 brcmf_sdbrcm_probe_attach(struct brcmf_bus
*bus
, u32 regsva
)
3878 bus
->alp_only
= true;
3880 /* Return the window to backplane enumeration space for core access */
3881 if (brcmf_sdcard_set_sbaddr_window(bus
->sdiodev
, SI_ENUM_BASE
))
3882 brcmf_dbg(ERROR
, "FAILED to return to SI_ENUM_BASE\n");
3885 printk(KERN_DEBUG
"F1 signature read @0x18000000=0x%4x\n",
3886 brcmf_sdcard_reg_read(bus
->sdiodev
, SI_ENUM_BASE
, 4));
3891 * Force PLL off until brcmf_sdio_chip_attach()
3892 * programs PLL control regs
3895 brcmf_sdcard_cfg_write(bus
->sdiodev
, SDIO_FUNC_1
,
3896 SBSDIO_FUNC1_CHIPCLKCSR
,
3897 BRCMF_INIT_CLKCTL1
, &err
);
3900 brcmf_sdcard_cfg_read(bus
->sdiodev
, SDIO_FUNC_1
,
3901 SBSDIO_FUNC1_CHIPCLKCSR
, &err
);
3903 if (err
|| ((clkctl
& ~SBSDIO_AVBITS
) != BRCMF_INIT_CLKCTL1
)) {
3904 brcmf_dbg(ERROR
, "ChipClkCSR access: err %d wrote 0x%02x read 0x%02x\n",
3905 err
, BRCMF_INIT_CLKCTL1
, clkctl
);
3909 if (brcmf_sdio_chip_attach(bus
->sdiodev
, &bus
->ci
, regsva
)) {
3910 brcmf_dbg(ERROR
, "brcmf_sdio_chip_attach failed!\n");
3914 if (!brcmf_sdbrcm_chipmatch((u16
) bus
->ci
->chip
)) {
3915 brcmf_dbg(ERROR
, "unsupported chip: 0x%04x\n", bus
->ci
->chip
);
3919 brcmf_sdbrcm_sdiod_drive_strength_init(bus
, SDIO_DRIVE_STRENGTH
);
3921 /* Get info on the ARM and SOCRAM cores... */
3922 brcmf_sdcard_reg_read(bus
->sdiodev
,
3923 CORE_SB(bus
->ci
->armcorebase
, sbidhigh
), 4);
3924 bus
->ramsize
= bus
->ci
->ramsize
;
3925 if (!(bus
->ramsize
)) {
3926 brcmf_dbg(ERROR
, "failed to find SOCRAM memory!\n");
3930 /* Set core control so an SDIO reset does a backplane reset */
3931 reg_addr
= bus
->ci
->buscorebase
+
3932 offsetof(struct sdpcmd_regs
, corecontrol
);
3933 reg_val
= brcmf_sdcard_reg_read(bus
->sdiodev
, reg_addr
, sizeof(u32
));
3934 brcmf_sdcard_reg_write(bus
->sdiodev
, reg_addr
, sizeof(u32
),
3935 reg_val
| CC_BPRESEN
);
3937 brcmu_pktq_init(&bus
->txq
, (PRIOMASK
+ 1), TXQLEN
);
3939 /* Locate an appropriately-aligned portion of hdrbuf */
3940 bus
->rxhdr
= (u8
*) roundup((unsigned long)&bus
->hdrbuf
[0],
3943 /* Set the poll and/or interrupt flags */
3955 static bool brcmf_sdbrcm_probe_init(struct brcmf_bus
*bus
)
3957 brcmf_dbg(TRACE
, "Enter\n");
3959 /* Disable F2 to clear any intermediate frame state on the dongle */
3960 brcmf_sdcard_cfg_write(bus
->sdiodev
, SDIO_FUNC_0
, SDIO_CCCR_IOEx
,
3961 SDIO_FUNC_ENABLE_1
, NULL
);
3963 bus
->drvr
->busstate
= BRCMF_BUS_DOWN
;
3964 bus
->sleeping
= false;
3965 bus
->rxflow
= false;
3967 /* Done with backplane-dependent accesses, can drop clock... */
3968 brcmf_sdcard_cfg_write(bus
->sdiodev
, SDIO_FUNC_1
,
3969 SBSDIO_FUNC1_CHIPCLKCSR
, 0, NULL
);
3971 /* ...and initialize clock/power states */
3972 bus
->clkstate
= CLK_SDONLY
;
3973 bus
->idletime
= BRCMF_IDLE_INTERVAL
;
3974 bus
->idleclock
= BRCMF_IDLE_ACTIVE
;
3976 /* Query the F2 block size, set roundup accordingly */
3977 bus
->blocksize
= bus
->sdiodev
->func
[2]->cur_blksize
;
3978 bus
->roundup
= min(max_roundup
, bus
->blocksize
);
3980 /* bus module does not support packet chaining */
3981 bus
->use_rxchain
= false;
3982 bus
->sd_rxchain
= false;
3988 brcmf_sdbrcm_watchdog_thread(void *data
)
3990 struct brcmf_bus
*bus
= (struct brcmf_bus
*)data
;
3992 allow_signal(SIGTERM
);
3993 /* Run until signal received */
3995 if (kthread_should_stop())
3997 if (!wait_for_completion_interruptible(&bus
->watchdog_wait
)) {
3998 brcmf_sdbrcm_bus_watchdog(bus
->drvr
);
3999 /* Count the tick for reference */
4000 bus
->drvr
->tickcnt
++;
4008 brcmf_sdbrcm_watchdog(unsigned long data
)
4010 struct brcmf_bus
*bus
= (struct brcmf_bus
*)data
;
4012 if (bus
->watchdog_tsk
) {
4013 complete(&bus
->watchdog_wait
);
4014 /* Reschedule the watchdog */
4015 if (bus
->wd_timer_valid
)
4016 mod_timer(&bus
->timer
,
4017 jiffies
+ BRCMF_WD_POLL_MS
* HZ
/ 1000);
4022 brcmf_sdbrcm_chip_detach(struct brcmf_bus
*bus
)
4024 brcmf_dbg(TRACE
, "Enter\n");
4030 static void brcmf_sdbrcm_release_dongle(struct brcmf_bus
*bus
)
4032 brcmf_dbg(TRACE
, "Enter\n");
4035 brcmf_sdbrcm_clkctl(bus
, CLK_AVAIL
, false);
4036 brcmf_sdbrcm_clkctl(bus
, CLK_NONE
, false);
4037 brcmf_sdbrcm_chip_detach(bus
);
4038 if (bus
->vars
&& bus
->varsz
)
4043 brcmf_dbg(TRACE
, "Disconnected\n");
4046 /* Detach and free everything */
4047 static void brcmf_sdbrcm_release(struct brcmf_bus
*bus
)
4049 brcmf_dbg(TRACE
, "Enter\n");
4052 /* De-register interrupt handler */
4053 brcmf_sdcard_intr_dereg(bus
->sdiodev
);
4056 brcmf_detach(bus
->drvr
);
4057 brcmf_sdbrcm_release_dongle(bus
);
4061 brcmf_sdbrcm_release_malloc(bus
);
4066 brcmf_dbg(TRACE
, "Disconnected\n");
4069 void *brcmf_sdbrcm_probe(u16 bus_no
, u16 slot
, u16 func
, uint bustype
,
4070 u32 regsva
, struct brcmf_sdio_dev
*sdiodev
)
4073 struct brcmf_bus
*bus
;
4075 /* Init global variables at run-time, not as part of the declaration.
4076 * This is required to support init/de-init of the driver.
4078 * of globals as part of the declaration results in non-deterministic
4079 * behavior since the value of the globals may be different on the
4080 * first time that the driver is initialized vs subsequent
4085 brcmf_dbg(TRACE
, "Enter\n");
4087 /* We make an assumption about address window mappings:
4088 * regsva == SI_ENUM_BASE*/
4090 /* Allocate private bus interface state */
4091 bus
= kzalloc(sizeof(struct brcmf_bus
), GFP_ATOMIC
);
4095 bus
->sdiodev
= sdiodev
;
4097 skb_queue_head_init(&bus
->glom
);
4098 bus
->txbound
= BRCMF_TXBOUND
;
4099 bus
->rxbound
= BRCMF_RXBOUND
;
4100 bus
->txminmax
= BRCMF_TXMINMAX
;
4101 bus
->tx_seq
= SDPCM_SEQUENCE_WRAP
- 1;
4102 bus
->usebufpool
= false; /* Use bufpool if allocated,
4103 else use locally malloced rxbuf */
4105 /* attempt to attach to the dongle */
4106 if (!(brcmf_sdbrcm_probe_attach(bus
, regsva
))) {
4107 brcmf_dbg(ERROR
, "brcmf_sdbrcm_probe_attach failed\n");
4111 spin_lock_init(&bus
->txqlock
);
4112 init_waitqueue_head(&bus
->ctrl_wait
);
4113 init_waitqueue_head(&bus
->dcmd_resp_wait
);
4115 /* Set up the watchdog timer */
4116 init_timer(&bus
->timer
);
4117 bus
->timer
.data
= (unsigned long)bus
;
4118 bus
->timer
.function
= brcmf_sdbrcm_watchdog
;
4120 /* Initialize thread based operation and lock */
4121 sema_init(&bus
->sdsem
, 1);
4123 /* Initialize watchdog thread */
4124 init_completion(&bus
->watchdog_wait
);
4125 bus
->watchdog_tsk
= kthread_run(brcmf_sdbrcm_watchdog_thread
,
4126 bus
, "brcmf_watchdog");
4127 if (IS_ERR(bus
->watchdog_tsk
)) {
4129 "brcmf_watchdog thread failed to start\n");
4130 bus
->watchdog_tsk
= NULL
;
4132 /* Initialize DPC thread */
4133 init_completion(&bus
->dpc_wait
);
4134 bus
->dpc_tsk
= kthread_run(brcmf_sdbrcm_dpc_thread
,
4136 if (IS_ERR(bus
->dpc_tsk
)) {
4138 "brcmf_dpc thread failed to start\n");
4139 bus
->dpc_tsk
= NULL
;
4142 /* Attach to the brcmf/OS/network interface */
4143 bus
->drvr
= brcmf_attach(bus
, SDPCM_RESERVE
);
4145 brcmf_dbg(ERROR
, "brcmf_attach failed\n");
4149 /* Allocate buffers */
4150 if (!(brcmf_sdbrcm_probe_malloc(bus
))) {
4151 brcmf_dbg(ERROR
, "brcmf_sdbrcm_probe_malloc failed\n");
4155 if (!(brcmf_sdbrcm_probe_init(bus
))) {
4156 brcmf_dbg(ERROR
, "brcmf_sdbrcm_probe_init failed\n");
4160 /* Register interrupt callback, but mask it (not operational yet). */
4161 brcmf_dbg(INTR
, "disable SDIO interrupts (not interested yet)\n");
4162 ret
= brcmf_sdcard_intr_reg(bus
->sdiodev
);
4164 brcmf_dbg(ERROR
, "FAILED: sdcard_intr_reg returned %d\n", ret
);
4167 brcmf_dbg(INTR
, "registered SDIO interrupt function ok\n");
4169 brcmf_dbg(INFO
, "completed!!\n");
4171 /* if firmware path present try to download and bring up bus */
4172 ret
= brcmf_bus_start(bus
->drvr
);
4174 if (ret
== -ENOLINK
) {
4175 brcmf_dbg(ERROR
, "dongle is not responding\n");
4180 /* add interface and open for business */
4181 if (brcmf_add_if((struct brcmf_info
*)bus
->drvr
, 0, "wlan%d", NULL
)) {
4182 brcmf_dbg(ERROR
, "Add primary net device interface failed!!\n");
4189 brcmf_sdbrcm_release(bus
);
4193 void brcmf_sdbrcm_disconnect(void *ptr
)
4195 struct brcmf_bus
*bus
= (struct brcmf_bus
*)ptr
;
4197 brcmf_dbg(TRACE
, "Enter\n");
4200 brcmf_sdbrcm_release(bus
);
4202 brcmf_dbg(TRACE
, "Disconnected\n");
4205 struct device
*brcmf_bus_get_device(struct brcmf_bus
*bus
)
4207 return &bus
->sdiodev
->func
[2]->dev
;
4211 brcmf_sdbrcm_wd_timer(struct brcmf_bus
*bus
, uint wdtick
)
4213 /* Totally stop the timer */
4214 if (!wdtick
&& bus
->wd_timer_valid
== true) {
4215 del_timer_sync(&bus
->timer
);
4216 bus
->wd_timer_valid
= false;
4217 bus
->save_ms
= wdtick
;
4221 /* don't start the wd until fw is loaded */
4222 if (bus
->drvr
->busstate
== BRCMF_BUS_DOWN
)
4226 if (bus
->save_ms
!= BRCMF_WD_POLL_MS
) {
4227 if (bus
->wd_timer_valid
== true)
4228 /* Stop timer and restart at new value */
4229 del_timer_sync(&bus
->timer
);
4231 /* Create timer again when watchdog period is
4232 dynamically changed or in the first instance
4234 bus
->timer
.expires
=
4235 jiffies
+ BRCMF_WD_POLL_MS
* HZ
/ 1000;
4236 add_timer(&bus
->timer
);
4239 /* Re arm the timer, at last watchdog period */
4240 mod_timer(&bus
->timer
,
4241 jiffies
+ BRCMF_WD_POLL_MS
* HZ
/ 1000);
4244 bus
->wd_timer_valid
= true;
4245 bus
->save_ms
= wdtick
;