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brcm80211: fmac: separate receiving skb chain from other receive path
[deliverable/linux.git] / drivers / net / wireless / brcm80211 / brcmfmac / dhd_sdio.c
1 /*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/types.h>
18 #include <linux/kernel.h>
19 #include <linux/kthread.h>
20 #include <linux/printk.h>
21 #include <linux/pci_ids.h>
22 #include <linux/netdevice.h>
23 #include <linux/interrupt.h>
24 #include <linux/sched.h>
25 #include <linux/mmc/sdio.h>
26 #include <linux/mmc/sdio_func.h>
27 #include <linux/mmc/card.h>
28 #include <linux/semaphore.h>
29 #include <linux/firmware.h>
30 #include <linux/module.h>
31 #include <linux/bcma/bcma.h>
32 #include <asm/unaligned.h>
33 #include <defs.h>
34 #include <brcmu_wifi.h>
35 #include <brcmu_utils.h>
36 #include <brcm_hw_ids.h>
37 #include <soc.h>
38 #include "sdio_host.h"
39 #include "sdio_chip.h"
40
41 #define DCMD_RESP_TIMEOUT 2000 /* In milli second */
42
43 #ifdef BCMDBG
44
45 #define BRCMF_TRAP_INFO_SIZE 80
46
47 #define CBUF_LEN (128)
48
49 struct rte_log_le {
50 __le32 buf; /* Can't be pointer on (64-bit) hosts */
51 __le32 buf_size;
52 __le32 idx;
53 char *_buf_compat; /* Redundant pointer for backward compat. */
54 };
55
56 struct rte_console {
57 /* Virtual UART
58 * When there is no UART (e.g. Quickturn),
59 * the host should write a complete
60 * input line directly into cbuf and then write
61 * the length into vcons_in.
62 * This may also be used when there is a real UART
63 * (at risk of conflicting with
64 * the real UART). vcons_out is currently unused.
65 */
66 uint vcons_in;
67 uint vcons_out;
68
69 /* Output (logging) buffer
70 * Console output is written to a ring buffer log_buf at index log_idx.
71 * The host may read the output when it sees log_idx advance.
72 * Output will be lost if the output wraps around faster than the host
73 * polls.
74 */
75 struct rte_log_le log_le;
76
77 /* Console input line buffer
78 * Characters are read one at a time into cbuf
79 * until <CR> is received, then
80 * the buffer is processed as a command line.
81 * Also used for virtual UART.
82 */
83 uint cbuf_idx;
84 char cbuf[CBUF_LEN];
85 };
86
87 #endif /* BCMDBG */
88 #include <chipcommon.h>
89
90 #include "dhd.h"
91 #include "dhd_bus.h"
92 #include "dhd_proto.h"
93 #include "dhd_dbg.h"
94 #include <bcmchip.h>
95
96 #define TXQLEN 2048 /* bulk tx queue length */
97 #define TXHI (TXQLEN - 256) /* turn on flow control above TXHI */
98 #define TXLOW (TXHI - 256) /* turn off flow control below TXLOW */
99 #define PRIOMASK 7
100
101 #define TXRETRIES 2 /* # of retries for tx frames */
102
103 #define BRCMF_RXBOUND 50 /* Default for max rx frames in
104 one scheduling */
105
106 #define BRCMF_TXBOUND 20 /* Default for max tx frames in
107 one scheduling */
108
109 #define BRCMF_TXMINMAX 1 /* Max tx frames if rx still pending */
110
111 #define MEMBLOCK 2048 /* Block size used for downloading
112 of dongle image */
113 #define MAX_DATA_BUF (32 * 1024) /* Must be large enough to hold
114 biggest possible glom */
115
116 #define BRCMF_FIRSTREAD (1 << 6)
117
118
119 /* SBSDIO_DEVICE_CTL */
120
121 /* 1: device will assert busy signal when receiving CMD53 */
122 #define SBSDIO_DEVCTL_SETBUSY 0x01
123 /* 1: assertion of sdio interrupt is synchronous to the sdio clock */
124 #define SBSDIO_DEVCTL_SPI_INTR_SYNC 0x02
125 /* 1: mask all interrupts to host except the chipActive (rev 8) */
126 #define SBSDIO_DEVCTL_CA_INT_ONLY 0x04
127 /* 1: isolate internal sdio signals, put external pads in tri-state; requires
128 * sdio bus power cycle to clear (rev 9) */
129 #define SBSDIO_DEVCTL_PADS_ISO 0x08
130 /* Force SD->SB reset mapping (rev 11) */
131 #define SBSDIO_DEVCTL_SB_RST_CTL 0x30
132 /* Determined by CoreControl bit */
133 #define SBSDIO_DEVCTL_RST_CORECTL 0x00
134 /* Force backplane reset */
135 #define SBSDIO_DEVCTL_RST_BPRESET 0x10
136 /* Force no backplane reset */
137 #define SBSDIO_DEVCTL_RST_NOBPRESET 0x20
138
139 /* direct(mapped) cis space */
140
141 /* MAPPED common CIS address */
142 #define SBSDIO_CIS_BASE_COMMON 0x1000
143 /* maximum bytes in one CIS */
144 #define SBSDIO_CIS_SIZE_LIMIT 0x200
145 /* cis offset addr is < 17 bits */
146 #define SBSDIO_CIS_OFT_ADDR_MASK 0x1FFFF
147
148 /* manfid tuple length, include tuple, link bytes */
149 #define SBSDIO_CIS_MANFID_TUPLE_LEN 6
150
151 /* intstatus */
152 #define I_SMB_SW0 (1 << 0) /* To SB Mail S/W interrupt 0 */
153 #define I_SMB_SW1 (1 << 1) /* To SB Mail S/W interrupt 1 */
154 #define I_SMB_SW2 (1 << 2) /* To SB Mail S/W interrupt 2 */
155 #define I_SMB_SW3 (1 << 3) /* To SB Mail S/W interrupt 3 */
156 #define I_SMB_SW_MASK 0x0000000f /* To SB Mail S/W interrupts mask */
157 #define I_SMB_SW_SHIFT 0 /* To SB Mail S/W interrupts shift */
158 #define I_HMB_SW0 (1 << 4) /* To Host Mail S/W interrupt 0 */
159 #define I_HMB_SW1 (1 << 5) /* To Host Mail S/W interrupt 1 */
160 #define I_HMB_SW2 (1 << 6) /* To Host Mail S/W interrupt 2 */
161 #define I_HMB_SW3 (1 << 7) /* To Host Mail S/W interrupt 3 */
162 #define I_HMB_SW_MASK 0x000000f0 /* To Host Mail S/W interrupts mask */
163 #define I_HMB_SW_SHIFT 4 /* To Host Mail S/W interrupts shift */
164 #define I_WR_OOSYNC (1 << 8) /* Write Frame Out Of Sync */
165 #define I_RD_OOSYNC (1 << 9) /* Read Frame Out Of Sync */
166 #define I_PC (1 << 10) /* descriptor error */
167 #define I_PD (1 << 11) /* data error */
168 #define I_DE (1 << 12) /* Descriptor protocol Error */
169 #define I_RU (1 << 13) /* Receive descriptor Underflow */
170 #define I_RO (1 << 14) /* Receive fifo Overflow */
171 #define I_XU (1 << 15) /* Transmit fifo Underflow */
172 #define I_RI (1 << 16) /* Receive Interrupt */
173 #define I_BUSPWR (1 << 17) /* SDIO Bus Power Change (rev 9) */
174 #define I_XMTDATA_AVAIL (1 << 23) /* bits in fifo */
175 #define I_XI (1 << 24) /* Transmit Interrupt */
176 #define I_RF_TERM (1 << 25) /* Read Frame Terminate */
177 #define I_WF_TERM (1 << 26) /* Write Frame Terminate */
178 #define I_PCMCIA_XU (1 << 27) /* PCMCIA Transmit FIFO Underflow */
179 #define I_SBINT (1 << 28) /* sbintstatus Interrupt */
180 #define I_CHIPACTIVE (1 << 29) /* chip from doze to active state */
181 #define I_SRESET (1 << 30) /* CCCR RES interrupt */
182 #define I_IOE2 (1U << 31) /* CCCR IOE2 Bit Changed */
183 #define I_ERRORS (I_PC | I_PD | I_DE | I_RU | I_RO | I_XU)
184 #define I_DMA (I_RI | I_XI | I_ERRORS)
185
186 /* corecontrol */
187 #define CC_CISRDY (1 << 0) /* CIS Ready */
188 #define CC_BPRESEN (1 << 1) /* CCCR RES signal */
189 #define CC_F2RDY (1 << 2) /* set CCCR IOR2 bit */
190 #define CC_CLRPADSISO (1 << 3) /* clear SDIO pads isolation */
191 #define CC_XMTDATAAVAIL_MODE (1 << 4)
192 #define CC_XMTDATAAVAIL_CTRL (1 << 5)
193
194 /* SDA_FRAMECTRL */
195 #define SFC_RF_TERM (1 << 0) /* Read Frame Terminate */
196 #define SFC_WF_TERM (1 << 1) /* Write Frame Terminate */
197 #define SFC_CRC4WOOS (1 << 2) /* CRC error for write out of sync */
198 #define SFC_ABORTALL (1 << 3) /* Abort all in-progress frames */
199
200 /* HW frame tag */
201 #define SDPCM_FRAMETAG_LEN 4 /* 2 bytes len, 2 bytes check val */
202
203 /* Total length of frame header for dongle protocol */
204 #define SDPCM_HDRLEN (SDPCM_FRAMETAG_LEN + SDPCM_SWHEADER_LEN)
205 #define SDPCM_RESERVE (SDPCM_HDRLEN + BRCMF_SDALIGN)
206
207 /*
208 * Software allocation of To SB Mailbox resources
209 */
210
211 /* tosbmailbox bits corresponding to intstatus bits */
212 #define SMB_NAK (1 << 0) /* Frame NAK */
213 #define SMB_INT_ACK (1 << 1) /* Host Interrupt ACK */
214 #define SMB_USE_OOB (1 << 2) /* Use OOB Wakeup */
215 #define SMB_DEV_INT (1 << 3) /* Miscellaneous Interrupt */
216
217 /* tosbmailboxdata */
218 #define SMB_DATA_VERSION_SHIFT 16 /* host protocol version */
219
220 /*
221 * Software allocation of To Host Mailbox resources
222 */
223
224 /* intstatus bits */
225 #define I_HMB_FC_STATE I_HMB_SW0 /* Flow Control State */
226 #define I_HMB_FC_CHANGE I_HMB_SW1 /* Flow Control State Changed */
227 #define I_HMB_FRAME_IND I_HMB_SW2 /* Frame Indication */
228 #define I_HMB_HOST_INT I_HMB_SW3 /* Miscellaneous Interrupt */
229
230 /* tohostmailboxdata */
231 #define HMB_DATA_NAKHANDLED 1 /* retransmit NAK'd frame */
232 #define HMB_DATA_DEVREADY 2 /* talk to host after enable */
233 #define HMB_DATA_FC 4 /* per prio flowcontrol update flag */
234 #define HMB_DATA_FWREADY 8 /* fw ready for protocol activity */
235
236 #define HMB_DATA_FCDATA_MASK 0xff000000
237 #define HMB_DATA_FCDATA_SHIFT 24
238
239 #define HMB_DATA_VERSION_MASK 0x00ff0000
240 #define HMB_DATA_VERSION_SHIFT 16
241
242 /*
243 * Software-defined protocol header
244 */
245
246 /* Current protocol version */
247 #define SDPCM_PROT_VERSION 4
248
249 /* SW frame header */
250 #define SDPCM_PACKET_SEQUENCE(p) (((u8 *)p)[0] & 0xff)
251
252 #define SDPCM_CHANNEL_MASK 0x00000f00
253 #define SDPCM_CHANNEL_SHIFT 8
254 #define SDPCM_PACKET_CHANNEL(p) (((u8 *)p)[1] & 0x0f)
255
256 #define SDPCM_NEXTLEN_OFFSET 2
257
258 /* Data Offset from SOF (HW Tag, SW Tag, Pad) */
259 #define SDPCM_DOFFSET_OFFSET 3 /* Data Offset */
260 #define SDPCM_DOFFSET_VALUE(p) (((u8 *)p)[SDPCM_DOFFSET_OFFSET] & 0xff)
261 #define SDPCM_DOFFSET_MASK 0xff000000
262 #define SDPCM_DOFFSET_SHIFT 24
263 #define SDPCM_FCMASK_OFFSET 4 /* Flow control */
264 #define SDPCM_FCMASK_VALUE(p) (((u8 *)p)[SDPCM_FCMASK_OFFSET] & 0xff)
265 #define SDPCM_WINDOW_OFFSET 5 /* Credit based fc */
266 #define SDPCM_WINDOW_VALUE(p) (((u8 *)p)[SDPCM_WINDOW_OFFSET] & 0xff)
267
268 #define SDPCM_SWHEADER_LEN 8 /* SW header is 64 bits */
269
270 /* logical channel numbers */
271 #define SDPCM_CONTROL_CHANNEL 0 /* Control channel Id */
272 #define SDPCM_EVENT_CHANNEL 1 /* Asyc Event Indication Channel Id */
273 #define SDPCM_DATA_CHANNEL 2 /* Data Xmit/Recv Channel Id */
274 #define SDPCM_GLOM_CHANNEL 3 /* For coalesced packets */
275 #define SDPCM_TEST_CHANNEL 15 /* Reserved for test/debug packets */
276
277 #define SDPCM_SEQUENCE_WRAP 256 /* wrap-around val for 8bit frame seq */
278
279 #define SDPCM_GLOMDESC(p) (((u8 *)p)[1] & 0x80)
280
281 /*
282 * Shared structure between dongle and the host.
283 * The structure contains pointers to trap or assert information.
284 */
285 #define SDPCM_SHARED_VERSION 0x0002
286 #define SDPCM_SHARED_VERSION_MASK 0x00FF
287 #define SDPCM_SHARED_ASSERT_BUILT 0x0100
288 #define SDPCM_SHARED_ASSERT 0x0200
289 #define SDPCM_SHARED_TRAP 0x0400
290
291 /* Space for header read, limit for data packets */
292 #define MAX_HDR_READ (1 << 6)
293 #define MAX_RX_DATASZ 2048
294
295 /* Maximum milliseconds to wait for F2 to come up */
296 #define BRCMF_WAIT_F2RDY 3000
297
298 /* Bump up limit on waiting for HT to account for first startup;
299 * if the image is doing a CRC calculation before programming the PMU
300 * for HT availability, it could take a couple hundred ms more, so
301 * max out at a 1 second (1000000us).
302 */
303 #undef PMU_MAX_TRANSITION_DLY
304 #define PMU_MAX_TRANSITION_DLY 1000000
305
306 /* Value for ChipClockCSR during initial setup */
307 #define BRCMF_INIT_CLKCTL1 (SBSDIO_FORCE_HW_CLKREQ_OFF | \
308 SBSDIO_ALP_AVAIL_REQ)
309
310 /* Flags for SDH calls */
311 #define F2SYNC (SDIO_REQ_4BYTE | SDIO_REQ_FIXED)
312
313 /*
314 * Conversion of 802.1D priority to precedence level
315 */
316 static uint prio2prec(u32 prio)
317 {
318 return (prio == PRIO_8021D_NONE || prio == PRIO_8021D_BE) ?
319 (prio^2) : prio;
320 }
321
322 /* core registers */
323 struct sdpcmd_regs {
324 u32 corecontrol; /* 0x00, rev8 */
325 u32 corestatus; /* rev8 */
326 u32 PAD[1];
327 u32 biststatus; /* rev8 */
328
329 /* PCMCIA access */
330 u16 pcmciamesportaladdr; /* 0x010, rev8 */
331 u16 PAD[1];
332 u16 pcmciamesportalmask; /* rev8 */
333 u16 PAD[1];
334 u16 pcmciawrframebc; /* rev8 */
335 u16 PAD[1];
336 u16 pcmciaunderflowtimer; /* rev8 */
337 u16 PAD[1];
338
339 /* interrupt */
340 u32 intstatus; /* 0x020, rev8 */
341 u32 hostintmask; /* rev8 */
342 u32 intmask; /* rev8 */
343 u32 sbintstatus; /* rev8 */
344 u32 sbintmask; /* rev8 */
345 u32 funcintmask; /* rev4 */
346 u32 PAD[2];
347 u32 tosbmailbox; /* 0x040, rev8 */
348 u32 tohostmailbox; /* rev8 */
349 u32 tosbmailboxdata; /* rev8 */
350 u32 tohostmailboxdata; /* rev8 */
351
352 /* synchronized access to registers in SDIO clock domain */
353 u32 sdioaccess; /* 0x050, rev8 */
354 u32 PAD[3];
355
356 /* PCMCIA frame control */
357 u8 pcmciaframectrl; /* 0x060, rev8 */
358 u8 PAD[3];
359 u8 pcmciawatermark; /* rev8 */
360 u8 PAD[155];
361
362 /* interrupt batching control */
363 u32 intrcvlazy; /* 0x100, rev8 */
364 u32 PAD[3];
365
366 /* counters */
367 u32 cmd52rd; /* 0x110, rev8 */
368 u32 cmd52wr; /* rev8 */
369 u32 cmd53rd; /* rev8 */
370 u32 cmd53wr; /* rev8 */
371 u32 abort; /* rev8 */
372 u32 datacrcerror; /* rev8 */
373 u32 rdoutofsync; /* rev8 */
374 u32 wroutofsync; /* rev8 */
375 u32 writebusy; /* rev8 */
376 u32 readwait; /* rev8 */
377 u32 readterm; /* rev8 */
378 u32 writeterm; /* rev8 */
379 u32 PAD[40];
380 u32 clockctlstatus; /* rev8 */
381 u32 PAD[7];
382
383 u32 PAD[128]; /* DMA engines */
384
385 /* SDIO/PCMCIA CIS region */
386 char cis[512]; /* 0x400-0x5ff, rev6 */
387
388 /* PCMCIA function control registers */
389 char pcmciafcr[256]; /* 0x600-6ff, rev6 */
390 u16 PAD[55];
391
392 /* PCMCIA backplane access */
393 u16 backplanecsr; /* 0x76E, rev6 */
394 u16 backplaneaddr0; /* rev6 */
395 u16 backplaneaddr1; /* rev6 */
396 u16 backplaneaddr2; /* rev6 */
397 u16 backplaneaddr3; /* rev6 */
398 u16 backplanedata0; /* rev6 */
399 u16 backplanedata1; /* rev6 */
400 u16 backplanedata2; /* rev6 */
401 u16 backplanedata3; /* rev6 */
402 u16 PAD[31];
403
404 /* sprom "size" & "blank" info */
405 u16 spromstatus; /* 0x7BE, rev2 */
406 u32 PAD[464];
407
408 u16 PAD[0x80];
409 };
410
411 #ifdef BCMDBG
412 /* Device console log buffer state */
413 struct brcmf_console {
414 uint count; /* Poll interval msec counter */
415 uint log_addr; /* Log struct address (fixed) */
416 struct rte_log_le log_le; /* Log struct (host copy) */
417 uint bufsize; /* Size of log buffer */
418 u8 *buf; /* Log buffer (host copy) */
419 uint last; /* Last buffer read index */
420 };
421 #endif /* BCMDBG */
422
423 struct sdpcm_shared {
424 u32 flags;
425 u32 trap_addr;
426 u32 assert_exp_addr;
427 u32 assert_file_addr;
428 u32 assert_line;
429 u32 console_addr; /* Address of struct rte_console */
430 u32 msgtrace_addr;
431 u8 tag[32];
432 };
433
434 struct sdpcm_shared_le {
435 __le32 flags;
436 __le32 trap_addr;
437 __le32 assert_exp_addr;
438 __le32 assert_file_addr;
439 __le32 assert_line;
440 __le32 console_addr; /* Address of struct rte_console */
441 __le32 msgtrace_addr;
442 u8 tag[32];
443 };
444
445
446 /* misc chip info needed by some of the routines */
447 /* Private data for SDIO bus interaction */
448 struct brcmf_bus {
449 struct brcmf_pub *drvr;
450
451 struct brcmf_sdio_dev *sdiodev; /* sdio device handler */
452 struct chip_info *ci; /* Chip info struct */
453 char *vars; /* Variables (from CIS and/or other) */
454 uint varsz; /* Size of variables buffer */
455
456 u32 ramsize; /* Size of RAM in SOCRAM (bytes) */
457
458 u32 hostintmask; /* Copy of Host Interrupt Mask */
459 u32 intstatus; /* Intstatus bits (events) pending */
460 bool dpc_sched; /* Indicates DPC schedule (intrpt rcvd) */
461 bool fcstate; /* State of dongle flow-control */
462
463 uint blocksize; /* Block size of SDIO transfers */
464 uint roundup; /* Max roundup limit */
465
466 struct pktq txq; /* Queue length used for flow-control */
467 u8 flowcontrol; /* per prio flow control bitmask */
468 u8 tx_seq; /* Transmit sequence number (next) */
469 u8 tx_max; /* Maximum transmit sequence allowed */
470
471 u8 hdrbuf[MAX_HDR_READ + BRCMF_SDALIGN];
472 u8 *rxhdr; /* Header of current rx frame (in hdrbuf) */
473 u16 nextlen; /* Next Read Len from last header */
474 u8 rx_seq; /* Receive sequence number (expected) */
475 bool rxskip; /* Skip receive (awaiting NAK ACK) */
476
477 uint rxbound; /* Rx frames to read before resched */
478 uint txbound; /* Tx frames to send before resched */
479 uint txminmax;
480
481 struct sk_buff *glomd; /* Packet containing glomming descriptor */
482 struct sk_buff_head glom; /* Packet list for glommed superframe */
483 uint glomerr; /* Glom packet read errors */
484
485 u8 *rxbuf; /* Buffer for receiving control packets */
486 uint rxblen; /* Allocated length of rxbuf */
487 u8 *rxctl; /* Aligned pointer into rxbuf */
488 u8 *databuf; /* Buffer for receiving big glom packet */
489 u8 *dataptr; /* Aligned pointer into databuf */
490 uint rxlen; /* Length of valid data in buffer */
491
492 u8 sdpcm_ver; /* Bus protocol reported by dongle */
493
494 bool intr; /* Use interrupts */
495 bool poll; /* Use polling */
496 bool ipend; /* Device interrupt is pending */
497 uint intrcount; /* Count of device interrupt callbacks */
498 uint lastintrs; /* Count as of last watchdog timer */
499 uint spurious; /* Count of spurious interrupts */
500 uint pollrate; /* Ticks between device polls */
501 uint polltick; /* Tick counter */
502 uint pollcnt; /* Count of active polls */
503
504 #ifdef BCMDBG
505 uint console_interval;
506 struct brcmf_console console; /* Console output polling support */
507 uint console_addr; /* Console address from shared struct */
508 #endif /* BCMDBG */
509
510 uint regfails; /* Count of R_REG failures */
511
512 uint clkstate; /* State of sd and backplane clock(s) */
513 bool activity; /* Activity flag for clock down */
514 s32 idletime; /* Control for activity timeout */
515 s32 idlecount; /* Activity timeout counter */
516 s32 idleclock; /* How to set bus driver when idle */
517 s32 sd_rxchain;
518 bool use_rxchain; /* If brcmf should use PKT chains */
519 bool sleeping; /* Is SDIO bus sleeping? */
520 bool rxflow_mode; /* Rx flow control mode */
521 bool rxflow; /* Is rx flow control on */
522 bool alp_only; /* Don't use HT clock (ALP only) */
523 /* Field to decide if rx of control frames happen in rxbuf or lb-pool */
524 bool usebufpool;
525
526 /* Some additional counters */
527 uint tx_sderrs; /* Count of tx attempts with sd errors */
528 uint fcqueued; /* Tx packets that got queued */
529 uint rxrtx; /* Count of rtx requests (NAK to dongle) */
530 uint rx_toolong; /* Receive frames too long to receive */
531 uint rxc_errors; /* SDIO errors when reading control frames */
532 uint rx_hdrfail; /* SDIO errors on header reads */
533 uint rx_badhdr; /* Bad received headers (roosync?) */
534 uint rx_badseq; /* Mismatched rx sequence number */
535 uint fc_rcvd; /* Number of flow-control events received */
536 uint fc_xoff; /* Number which turned on flow-control */
537 uint fc_xon; /* Number which turned off flow-control */
538 uint rxglomfail; /* Failed deglom attempts */
539 uint rxglomframes; /* Number of glom frames (superframes) */
540 uint rxglompkts; /* Number of packets from glom frames */
541 uint f2rxhdrs; /* Number of header reads */
542 uint f2rxdata; /* Number of frame data reads */
543 uint f2txdata; /* Number of f2 frame writes */
544 uint f1regdata; /* Number of f1 register accesses */
545
546 u8 *ctrl_frame_buf;
547 u32 ctrl_frame_len;
548 bool ctrl_frame_stat;
549
550 spinlock_t txqlock;
551 wait_queue_head_t ctrl_wait;
552 wait_queue_head_t dcmd_resp_wait;
553
554 struct timer_list timer;
555 struct completion watchdog_wait;
556 struct task_struct *watchdog_tsk;
557 bool wd_timer_valid;
558 uint save_ms;
559
560 struct task_struct *dpc_tsk;
561 struct completion dpc_wait;
562
563 struct semaphore sdsem;
564
565 const char *fw_name;
566 const struct firmware *firmware;
567 const char *nv_name;
568 u32 fw_ptr;
569 };
570
571 /* clkstate */
572 #define CLK_NONE 0
573 #define CLK_SDONLY 1
574 #define CLK_PENDING 2 /* Not used yet */
575 #define CLK_AVAIL 3
576
577 #ifdef BCMDBG
578 static int qcount[NUMPRIO];
579 static int tx_packets[NUMPRIO];
580 #endif /* BCMDBG */
581
582 #define SDIO_DRIVE_STRENGTH 6 /* in milliamps */
583
584 #define RETRYCHAN(chan) ((chan) == SDPCM_EVENT_CHANNEL)
585
586 /* Retry count for register access failures */
587 static const uint retry_limit = 2;
588
589 /* Limit on rounding up frames */
590 static const uint max_roundup = 512;
591
592 #define ALIGNMENT 4
593
594 static void pkt_align(struct sk_buff *p, int len, int align)
595 {
596 uint datalign;
597 datalign = (unsigned long)(p->data);
598 datalign = roundup(datalign, (align)) - datalign;
599 if (datalign)
600 skb_pull(p, datalign);
601 __skb_trim(p, len);
602 }
603
604 /* To check if there's window offered */
605 static bool data_ok(struct brcmf_bus *bus)
606 {
607 return (u8)(bus->tx_max - bus->tx_seq) != 0 &&
608 ((u8)(bus->tx_max - bus->tx_seq) & 0x80) == 0;
609 }
610
611 /*
612 * Reads a register in the SDIO hardware block. This block occupies a series of
613 * adresses on the 32 bit backplane bus.
614 */
615 static void
616 r_sdreg32(struct brcmf_bus *bus, u32 *regvar, u32 reg_offset, u32 *retryvar)
617 {
618 u8 idx = brcmf_sdio_chip_getinfidx(bus->ci, BCMA_CORE_SDIO_DEV);
619 *retryvar = 0;
620 do {
621 *regvar = brcmf_sdcard_reg_read(bus->sdiodev,
622 bus->ci->c_inf[idx].base + reg_offset,
623 sizeof(u32));
624 } while (brcmf_sdcard_regfail(bus->sdiodev) &&
625 (++(*retryvar) <= retry_limit));
626 if (*retryvar) {
627 bus->regfails += (*retryvar-1);
628 if (*retryvar > retry_limit) {
629 brcmf_dbg(ERROR, "FAILED READ %Xh\n", reg_offset);
630 *regvar = 0;
631 }
632 }
633 }
634
635 static void
636 w_sdreg32(struct brcmf_bus *bus, u32 regval, u32 reg_offset, u32 *retryvar)
637 {
638 u8 idx = brcmf_sdio_chip_getinfidx(bus->ci, BCMA_CORE_SDIO_DEV);
639 *retryvar = 0;
640 do {
641 brcmf_sdcard_reg_write(bus->sdiodev,
642 bus->ci->c_inf[idx].base + reg_offset,
643 sizeof(u32), regval);
644 } while (brcmf_sdcard_regfail(bus->sdiodev) &&
645 (++(*retryvar) <= retry_limit));
646 if (*retryvar) {
647 bus->regfails += (*retryvar-1);
648 if (*retryvar > retry_limit)
649 brcmf_dbg(ERROR, "FAILED REGISTER WRITE %Xh\n",
650 reg_offset);
651 }
652 }
653
654 #define PKT_AVAILABLE() (intstatus & I_HMB_FRAME_IND)
655
656 #define HOSTINTMASK (I_HMB_SW_MASK | I_CHIPACTIVE)
657
658 /* Packet free applicable unconditionally for sdio and sdspi.
659 * Conditional if bufpool was present for gspi bus.
660 */
661 static void brcmf_sdbrcm_pktfree2(struct brcmf_bus *bus, struct sk_buff *pkt)
662 {
663 if (bus->usebufpool)
664 brcmu_pkt_buf_free_skb(pkt);
665 }
666
667 /* Turn backplane clock on or off */
668 static int brcmf_sdbrcm_htclk(struct brcmf_bus *bus, bool on, bool pendok)
669 {
670 int err;
671 u8 clkctl, clkreq, devctl;
672 unsigned long timeout;
673
674 brcmf_dbg(TRACE, "Enter\n");
675
676 clkctl = 0;
677
678 if (on) {
679 /* Request HT Avail */
680 clkreq =
681 bus->alp_only ? SBSDIO_ALP_AVAIL_REQ : SBSDIO_HT_AVAIL_REQ;
682
683 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
684 SBSDIO_FUNC1_CHIPCLKCSR, clkreq, &err);
685 if (err) {
686 brcmf_dbg(ERROR, "HT Avail request error: %d\n", err);
687 return -EBADE;
688 }
689
690 /* Check current status */
691 clkctl = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
692 SBSDIO_FUNC1_CHIPCLKCSR, &err);
693 if (err) {
694 brcmf_dbg(ERROR, "HT Avail read error: %d\n", err);
695 return -EBADE;
696 }
697
698 /* Go to pending and await interrupt if appropriate */
699 if (!SBSDIO_CLKAV(clkctl, bus->alp_only) && pendok) {
700 /* Allow only clock-available interrupt */
701 devctl = brcmf_sdcard_cfg_read(bus->sdiodev,
702 SDIO_FUNC_1,
703 SBSDIO_DEVICE_CTL, &err);
704 if (err) {
705 brcmf_dbg(ERROR, "Devctl error setting CA: %d\n",
706 err);
707 return -EBADE;
708 }
709
710 devctl |= SBSDIO_DEVCTL_CA_INT_ONLY;
711 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
712 SBSDIO_DEVICE_CTL, devctl, &err);
713 brcmf_dbg(INFO, "CLKCTL: set PENDING\n");
714 bus->clkstate = CLK_PENDING;
715
716 return 0;
717 } else if (bus->clkstate == CLK_PENDING) {
718 /* Cancel CA-only interrupt filter */
719 devctl =
720 brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
721 SBSDIO_DEVICE_CTL, &err);
722 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
723 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
724 SBSDIO_DEVICE_CTL, devctl, &err);
725 }
726
727 /* Otherwise, wait here (polling) for HT Avail */
728 timeout = jiffies +
729 msecs_to_jiffies(PMU_MAX_TRANSITION_DLY/1000);
730 while (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
731 clkctl = brcmf_sdcard_cfg_read(bus->sdiodev,
732 SDIO_FUNC_1,
733 SBSDIO_FUNC1_CHIPCLKCSR,
734 &err);
735 if (time_after(jiffies, timeout))
736 break;
737 else
738 usleep_range(5000, 10000);
739 }
740 if (err) {
741 brcmf_dbg(ERROR, "HT Avail request error: %d\n", err);
742 return -EBADE;
743 }
744 if (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
745 brcmf_dbg(ERROR, "HT Avail timeout (%d): clkctl 0x%02x\n",
746 PMU_MAX_TRANSITION_DLY, clkctl);
747 return -EBADE;
748 }
749
750 /* Mark clock available */
751 bus->clkstate = CLK_AVAIL;
752 brcmf_dbg(INFO, "CLKCTL: turned ON\n");
753
754 #if defined(BCMDBG)
755 if (bus->alp_only != true) {
756 if (SBSDIO_ALPONLY(clkctl))
757 brcmf_dbg(ERROR, "HT Clock should be on\n");
758 }
759 #endif /* defined (BCMDBG) */
760
761 bus->activity = true;
762 } else {
763 clkreq = 0;
764
765 if (bus->clkstate == CLK_PENDING) {
766 /* Cancel CA-only interrupt filter */
767 devctl = brcmf_sdcard_cfg_read(bus->sdiodev,
768 SDIO_FUNC_1,
769 SBSDIO_DEVICE_CTL, &err);
770 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
771 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
772 SBSDIO_DEVICE_CTL, devctl, &err);
773 }
774
775 bus->clkstate = CLK_SDONLY;
776 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
777 SBSDIO_FUNC1_CHIPCLKCSR, clkreq, &err);
778 brcmf_dbg(INFO, "CLKCTL: turned OFF\n");
779 if (err) {
780 brcmf_dbg(ERROR, "Failed access turning clock off: %d\n",
781 err);
782 return -EBADE;
783 }
784 }
785 return 0;
786 }
787
788 /* Change idle/active SD state */
789 static int brcmf_sdbrcm_sdclk(struct brcmf_bus *bus, bool on)
790 {
791 brcmf_dbg(TRACE, "Enter\n");
792
793 if (on)
794 bus->clkstate = CLK_SDONLY;
795 else
796 bus->clkstate = CLK_NONE;
797
798 return 0;
799 }
800
801 /* Transition SD and backplane clock readiness */
802 static int brcmf_sdbrcm_clkctl(struct brcmf_bus *bus, uint target, bool pendok)
803 {
804 #ifdef BCMDBG
805 uint oldstate = bus->clkstate;
806 #endif /* BCMDBG */
807
808 brcmf_dbg(TRACE, "Enter\n");
809
810 /* Early exit if we're already there */
811 if (bus->clkstate == target) {
812 if (target == CLK_AVAIL) {
813 brcmf_sdbrcm_wd_timer(bus, BRCMF_WD_POLL_MS);
814 bus->activity = true;
815 }
816 return 0;
817 }
818
819 switch (target) {
820 case CLK_AVAIL:
821 /* Make sure SD clock is available */
822 if (bus->clkstate == CLK_NONE)
823 brcmf_sdbrcm_sdclk(bus, true);
824 /* Now request HT Avail on the backplane */
825 brcmf_sdbrcm_htclk(bus, true, pendok);
826 brcmf_sdbrcm_wd_timer(bus, BRCMF_WD_POLL_MS);
827 bus->activity = true;
828 break;
829
830 case CLK_SDONLY:
831 /* Remove HT request, or bring up SD clock */
832 if (bus->clkstate == CLK_NONE)
833 brcmf_sdbrcm_sdclk(bus, true);
834 else if (bus->clkstate == CLK_AVAIL)
835 brcmf_sdbrcm_htclk(bus, false, false);
836 else
837 brcmf_dbg(ERROR, "request for %d -> %d\n",
838 bus->clkstate, target);
839 brcmf_sdbrcm_wd_timer(bus, BRCMF_WD_POLL_MS);
840 break;
841
842 case CLK_NONE:
843 /* Make sure to remove HT request */
844 if (bus->clkstate == CLK_AVAIL)
845 brcmf_sdbrcm_htclk(bus, false, false);
846 /* Now remove the SD clock */
847 brcmf_sdbrcm_sdclk(bus, false);
848 brcmf_sdbrcm_wd_timer(bus, 0);
849 break;
850 }
851 #ifdef BCMDBG
852 brcmf_dbg(INFO, "%d -> %d\n", oldstate, bus->clkstate);
853 #endif /* BCMDBG */
854
855 return 0;
856 }
857
858 static int brcmf_sdbrcm_bussleep(struct brcmf_bus *bus, bool sleep)
859 {
860 uint retries = 0;
861
862 brcmf_dbg(INFO, "request %s (currently %s)\n",
863 sleep ? "SLEEP" : "WAKE",
864 bus->sleeping ? "SLEEP" : "WAKE");
865
866 /* Done if we're already in the requested state */
867 if (sleep == bus->sleeping)
868 return 0;
869
870 /* Going to sleep: set the alarm and turn off the lights... */
871 if (sleep) {
872 /* Don't sleep if something is pending */
873 if (bus->dpc_sched || bus->rxskip || pktq_len(&bus->txq))
874 return -EBUSY;
875
876 /* Make sure the controller has the bus up */
877 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
878
879 /* Tell device to start using OOB wakeup */
880 w_sdreg32(bus, SMB_USE_OOB,
881 offsetof(struct sdpcmd_regs, tosbmailbox), &retries);
882 if (retries > retry_limit)
883 brcmf_dbg(ERROR, "CANNOT SIGNAL CHIP, WILL NOT WAKE UP!!\n");
884
885 /* Turn off our contribution to the HT clock request */
886 brcmf_sdbrcm_clkctl(bus, CLK_SDONLY, false);
887
888 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
889 SBSDIO_FUNC1_CHIPCLKCSR,
890 SBSDIO_FORCE_HW_CLKREQ_OFF, NULL);
891
892 /* Isolate the bus */
893 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
894 SBSDIO_DEVICE_CTL,
895 SBSDIO_DEVCTL_PADS_ISO, NULL);
896
897 /* Change state */
898 bus->sleeping = true;
899
900 } else {
901 /* Waking up: bus power up is ok, set local state */
902
903 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
904 SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL);
905
906 /* Make sure the controller has the bus up */
907 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
908
909 /* Send misc interrupt to indicate OOB not needed */
910 w_sdreg32(bus, 0, offsetof(struct sdpcmd_regs, tosbmailboxdata),
911 &retries);
912 if (retries <= retry_limit)
913 w_sdreg32(bus, SMB_DEV_INT,
914 offsetof(struct sdpcmd_regs, tosbmailbox),
915 &retries);
916
917 if (retries > retry_limit)
918 brcmf_dbg(ERROR, "CANNOT SIGNAL CHIP TO CLEAR OOB!!\n");
919
920 /* Make sure we have SD bus access */
921 brcmf_sdbrcm_clkctl(bus, CLK_SDONLY, false);
922
923 /* Change state */
924 bus->sleeping = false;
925 }
926
927 return 0;
928 }
929
930 static void bus_wake(struct brcmf_bus *bus)
931 {
932 if (bus->sleeping)
933 brcmf_sdbrcm_bussleep(bus, false);
934 }
935
936 static u32 brcmf_sdbrcm_hostmail(struct brcmf_bus *bus)
937 {
938 u32 intstatus = 0;
939 u32 hmb_data;
940 u8 fcbits;
941 uint retries = 0;
942
943 brcmf_dbg(TRACE, "Enter\n");
944
945 /* Read mailbox data and ack that we did so */
946 r_sdreg32(bus, &hmb_data,
947 offsetof(struct sdpcmd_regs, tohostmailboxdata), &retries);
948
949 if (retries <= retry_limit)
950 w_sdreg32(bus, SMB_INT_ACK,
951 offsetof(struct sdpcmd_regs, tosbmailbox), &retries);
952 bus->f1regdata += 2;
953
954 /* Dongle recomposed rx frames, accept them again */
955 if (hmb_data & HMB_DATA_NAKHANDLED) {
956 brcmf_dbg(INFO, "Dongle reports NAK handled, expect rtx of %d\n",
957 bus->rx_seq);
958 if (!bus->rxskip)
959 brcmf_dbg(ERROR, "unexpected NAKHANDLED!\n");
960
961 bus->rxskip = false;
962 intstatus |= I_HMB_FRAME_IND;
963 }
964
965 /*
966 * DEVREADY does not occur with gSPI.
967 */
968 if (hmb_data & (HMB_DATA_DEVREADY | HMB_DATA_FWREADY)) {
969 bus->sdpcm_ver =
970 (hmb_data & HMB_DATA_VERSION_MASK) >>
971 HMB_DATA_VERSION_SHIFT;
972 if (bus->sdpcm_ver != SDPCM_PROT_VERSION)
973 brcmf_dbg(ERROR, "Version mismatch, dongle reports %d, "
974 "expecting %d\n",
975 bus->sdpcm_ver, SDPCM_PROT_VERSION);
976 else
977 brcmf_dbg(INFO, "Dongle ready, protocol version %d\n",
978 bus->sdpcm_ver);
979 }
980
981 /*
982 * Flow Control has been moved into the RX headers and this out of band
983 * method isn't used any more.
984 * remaining backward compatible with older dongles.
985 */
986 if (hmb_data & HMB_DATA_FC) {
987 fcbits = (hmb_data & HMB_DATA_FCDATA_MASK) >>
988 HMB_DATA_FCDATA_SHIFT;
989
990 if (fcbits & ~bus->flowcontrol)
991 bus->fc_xoff++;
992
993 if (bus->flowcontrol & ~fcbits)
994 bus->fc_xon++;
995
996 bus->fc_rcvd++;
997 bus->flowcontrol = fcbits;
998 }
999
1000 /* Shouldn't be any others */
1001 if (hmb_data & ~(HMB_DATA_DEVREADY |
1002 HMB_DATA_NAKHANDLED |
1003 HMB_DATA_FC |
1004 HMB_DATA_FWREADY |
1005 HMB_DATA_FCDATA_MASK | HMB_DATA_VERSION_MASK))
1006 brcmf_dbg(ERROR, "Unknown mailbox data content: 0x%02x\n",
1007 hmb_data);
1008
1009 return intstatus;
1010 }
1011
1012 static void brcmf_sdbrcm_rxfail(struct brcmf_bus *bus, bool abort, bool rtx)
1013 {
1014 uint retries = 0;
1015 u16 lastrbc;
1016 u8 hi, lo;
1017 int err;
1018
1019 brcmf_dbg(ERROR, "%sterminate frame%s\n",
1020 abort ? "abort command, " : "",
1021 rtx ? ", send NAK" : "");
1022
1023 if (abort)
1024 brcmf_sdcard_abort(bus->sdiodev, SDIO_FUNC_2);
1025
1026 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
1027 SBSDIO_FUNC1_FRAMECTRL,
1028 SFC_RF_TERM, &err);
1029 bus->f1regdata++;
1030
1031 /* Wait until the packet has been flushed (device/FIFO stable) */
1032 for (lastrbc = retries = 0xffff; retries > 0; retries--) {
1033 hi = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
1034 SBSDIO_FUNC1_RFRAMEBCHI, NULL);
1035 lo = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
1036 SBSDIO_FUNC1_RFRAMEBCLO, NULL);
1037 bus->f1regdata += 2;
1038
1039 if ((hi == 0) && (lo == 0))
1040 break;
1041
1042 if ((hi > (lastrbc >> 8)) && (lo > (lastrbc & 0x00ff))) {
1043 brcmf_dbg(ERROR, "count growing: last 0x%04x now 0x%04x\n",
1044 lastrbc, (hi << 8) + lo);
1045 }
1046 lastrbc = (hi << 8) + lo;
1047 }
1048
1049 if (!retries)
1050 brcmf_dbg(ERROR, "count never zeroed: last 0x%04x\n", lastrbc);
1051 else
1052 brcmf_dbg(INFO, "flush took %d iterations\n", 0xffff - retries);
1053
1054 if (rtx) {
1055 bus->rxrtx++;
1056 w_sdreg32(bus, SMB_NAK,
1057 offsetof(struct sdpcmd_regs, tosbmailbox), &retries);
1058
1059 bus->f1regdata++;
1060 if (retries <= retry_limit)
1061 bus->rxskip = true;
1062 }
1063
1064 /* Clear partial in any case */
1065 bus->nextlen = 0;
1066
1067 /* If we can't reach the device, signal failure */
1068 if (err || brcmf_sdcard_regfail(bus->sdiodev))
1069 bus->drvr->busstate = BRCMF_BUS_DOWN;
1070 }
1071
1072 /* copy a buffer into a pkt buffer chain */
1073 static uint brcmf_sdbrcm_glom_from_buf(struct brcmf_bus *bus, uint len)
1074 {
1075 uint n, ret = 0;
1076 struct sk_buff *p;
1077 u8 *buf;
1078
1079 buf = bus->dataptr;
1080
1081 /* copy the data */
1082 skb_queue_walk(&bus->glom, p) {
1083 n = min_t(uint, p->len, len);
1084 memcpy(p->data, buf, n);
1085 buf += n;
1086 len -= n;
1087 ret += n;
1088 if (!len)
1089 break;
1090 }
1091
1092 return ret;
1093 }
1094
1095 /* return total length of buffer chain */
1096 static uint brcmf_sdbrcm_glom_len(struct brcmf_bus *bus)
1097 {
1098 struct sk_buff *p;
1099 uint total;
1100
1101 total = 0;
1102 skb_queue_walk(&bus->glom, p)
1103 total += p->len;
1104 return total;
1105 }
1106
1107 static void brcmf_sdbrcm_free_glom(struct brcmf_bus *bus)
1108 {
1109 struct sk_buff *cur, *next;
1110
1111 skb_queue_walk_safe(&bus->glom, cur, next) {
1112 skb_unlink(cur, &bus->glom);
1113 brcmu_pkt_buf_free_skb(cur);
1114 }
1115 }
1116
1117 static u8 brcmf_sdbrcm_rxglom(struct brcmf_bus *bus, u8 rxseq)
1118 {
1119 u16 dlen, totlen;
1120 u8 *dptr, num = 0;
1121
1122 u16 sublen, check;
1123 struct sk_buff *pfirst, *pnext;
1124
1125 int errcode;
1126 u8 chan, seq, doff, sfdoff;
1127 u8 txmax;
1128
1129 int ifidx = 0;
1130 bool usechain = bus->use_rxchain;
1131
1132 /* If packets, issue read(s) and send up packet chain */
1133 /* Return sequence numbers consumed? */
1134
1135 brcmf_dbg(TRACE, "start: glomd %p glom %p\n",
1136 bus->glomd, skb_peek(&bus->glom));
1137
1138 /* If there's a descriptor, generate the packet chain */
1139 if (bus->glomd) {
1140 pfirst = pnext = NULL;
1141 dlen = (u16) (bus->glomd->len);
1142 dptr = bus->glomd->data;
1143 if (!dlen || (dlen & 1)) {
1144 brcmf_dbg(ERROR, "bad glomd len(%d), ignore descriptor\n",
1145 dlen);
1146 dlen = 0;
1147 }
1148
1149 for (totlen = num = 0; dlen; num++) {
1150 /* Get (and move past) next length */
1151 sublen = get_unaligned_le16(dptr);
1152 dlen -= sizeof(u16);
1153 dptr += sizeof(u16);
1154 if ((sublen < SDPCM_HDRLEN) ||
1155 ((num == 0) && (sublen < (2 * SDPCM_HDRLEN)))) {
1156 brcmf_dbg(ERROR, "descriptor len %d bad: %d\n",
1157 num, sublen);
1158 pnext = NULL;
1159 break;
1160 }
1161 if (sublen % BRCMF_SDALIGN) {
1162 brcmf_dbg(ERROR, "sublen %d not multiple of %d\n",
1163 sublen, BRCMF_SDALIGN);
1164 usechain = false;
1165 }
1166 totlen += sublen;
1167
1168 /* For last frame, adjust read len so total
1169 is a block multiple */
1170 if (!dlen) {
1171 sublen +=
1172 (roundup(totlen, bus->blocksize) - totlen);
1173 totlen = roundup(totlen, bus->blocksize);
1174 }
1175
1176 /* Allocate/chain packet for next subframe */
1177 pnext = brcmu_pkt_buf_get_skb(sublen + BRCMF_SDALIGN);
1178 if (pnext == NULL) {
1179 brcmf_dbg(ERROR, "bcm_pkt_buf_get_skb failed, num %d len %d\n",
1180 num, sublen);
1181 break;
1182 }
1183 skb_queue_tail(&bus->glom, pnext);
1184
1185 /* Adhere to start alignment requirements */
1186 pkt_align(pnext, sublen, BRCMF_SDALIGN);
1187 }
1188
1189 /* If all allocations succeeded, save packet chain
1190 in bus structure */
1191 if (pnext) {
1192 brcmf_dbg(GLOM, "allocated %d-byte packet chain for %d subframes\n",
1193 totlen, num);
1194 if (BRCMF_GLOM_ON() && bus->nextlen &&
1195 totlen != bus->nextlen) {
1196 brcmf_dbg(GLOM, "glomdesc mismatch: nextlen %d glomdesc %d rxseq %d\n",
1197 bus->nextlen, totlen, rxseq);
1198 }
1199 pfirst = pnext = NULL;
1200 } else {
1201 brcmf_sdbrcm_free_glom(bus);
1202 num = 0;
1203 }
1204
1205 /* Done with descriptor packet */
1206 brcmu_pkt_buf_free_skb(bus->glomd);
1207 bus->glomd = NULL;
1208 bus->nextlen = 0;
1209 }
1210
1211 /* Ok -- either we just generated a packet chain,
1212 or had one from before */
1213 if (!skb_queue_empty(&bus->glom)) {
1214 if (BRCMF_GLOM_ON()) {
1215 brcmf_dbg(GLOM, "try superframe read, packet chain:\n");
1216 skb_queue_walk(&bus->glom, pnext) {
1217 brcmf_dbg(GLOM, " %p: %p len 0x%04x (%d)\n",
1218 pnext, (u8 *) (pnext->data),
1219 pnext->len, pnext->len);
1220 }
1221 }
1222
1223 pfirst = skb_peek(&bus->glom);
1224 dlen = (u16) brcmf_sdbrcm_glom_len(bus);
1225
1226 /* Do an SDIO read for the superframe. Configurable iovar to
1227 * read directly into the chained packet, or allocate a large
1228 * packet and and copy into the chain.
1229 */
1230 if (usechain) {
1231 errcode = brcmf_sdcard_recv_chain(bus->sdiodev,
1232 bus->sdiodev->sbwad,
1233 SDIO_FUNC_2, F2SYNC, &bus->glom);
1234 } else if (bus->dataptr) {
1235 errcode = brcmf_sdcard_recv_buf(bus->sdiodev,
1236 bus->sdiodev->sbwad,
1237 SDIO_FUNC_2, F2SYNC,
1238 bus->dataptr, dlen);
1239 sublen = (u16) brcmf_sdbrcm_glom_from_buf(bus, dlen);
1240 if (sublen != dlen) {
1241 brcmf_dbg(ERROR, "FAILED TO COPY, dlen %d sublen %d\n",
1242 dlen, sublen);
1243 errcode = -1;
1244 }
1245 pnext = NULL;
1246 } else {
1247 brcmf_dbg(ERROR, "COULDN'T ALLOC %d-BYTE GLOM, FORCE FAILURE\n",
1248 dlen);
1249 errcode = -1;
1250 }
1251 bus->f2rxdata++;
1252
1253 /* On failure, kill the superframe, allow a couple retries */
1254 if (errcode < 0) {
1255 brcmf_dbg(ERROR, "glom read of %d bytes failed: %d\n",
1256 dlen, errcode);
1257 bus->drvr->rx_errors++;
1258
1259 if (bus->glomerr++ < 3) {
1260 brcmf_sdbrcm_rxfail(bus, true, true);
1261 } else {
1262 bus->glomerr = 0;
1263 brcmf_sdbrcm_rxfail(bus, true, false);
1264 bus->rxglomfail++;
1265 brcmf_sdbrcm_free_glom(bus);
1266 }
1267 return 0;
1268 }
1269 #ifdef BCMDBG
1270 if (BRCMF_GLOM_ON()) {
1271 printk(KERN_DEBUG "SUPERFRAME:\n");
1272 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
1273 pfirst->data, min_t(int, pfirst->len, 48));
1274 }
1275 #endif
1276
1277 /* Validate the superframe header */
1278 dptr = (u8 *) (pfirst->data);
1279 sublen = get_unaligned_le16(dptr);
1280 check = get_unaligned_le16(dptr + sizeof(u16));
1281
1282 chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
1283 seq = SDPCM_PACKET_SEQUENCE(&dptr[SDPCM_FRAMETAG_LEN]);
1284 bus->nextlen = dptr[SDPCM_FRAMETAG_LEN + SDPCM_NEXTLEN_OFFSET];
1285 if ((bus->nextlen << 4) > MAX_RX_DATASZ) {
1286 brcmf_dbg(INFO, "nextlen too large (%d) seq %d\n",
1287 bus->nextlen, seq);
1288 bus->nextlen = 0;
1289 }
1290 doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
1291 txmax = SDPCM_WINDOW_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
1292
1293 errcode = 0;
1294 if ((u16)~(sublen ^ check)) {
1295 brcmf_dbg(ERROR, "(superframe): HW hdr error: len/check 0x%04x/0x%04x\n",
1296 sublen, check);
1297 errcode = -1;
1298 } else if (roundup(sublen, bus->blocksize) != dlen) {
1299 brcmf_dbg(ERROR, "(superframe): len 0x%04x, rounded 0x%04x, expect 0x%04x\n",
1300 sublen, roundup(sublen, bus->blocksize),
1301 dlen);
1302 errcode = -1;
1303 } else if (SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]) !=
1304 SDPCM_GLOM_CHANNEL) {
1305 brcmf_dbg(ERROR, "(superframe): bad channel %d\n",
1306 SDPCM_PACKET_CHANNEL(
1307 &dptr[SDPCM_FRAMETAG_LEN]));
1308 errcode = -1;
1309 } else if (SDPCM_GLOMDESC(&dptr[SDPCM_FRAMETAG_LEN])) {
1310 brcmf_dbg(ERROR, "(superframe): got 2nd descriptor?\n");
1311 errcode = -1;
1312 } else if ((doff < SDPCM_HDRLEN) ||
1313 (doff > (pfirst->len - SDPCM_HDRLEN))) {
1314 brcmf_dbg(ERROR, "(superframe): Bad data offset %d: HW %d pkt %d min %d\n",
1315 doff, sublen, pfirst->len, SDPCM_HDRLEN);
1316 errcode = -1;
1317 }
1318
1319 /* Check sequence number of superframe SW header */
1320 if (rxseq != seq) {
1321 brcmf_dbg(INFO, "(superframe) rx_seq %d, expected %d\n",
1322 seq, rxseq);
1323 bus->rx_badseq++;
1324 rxseq = seq;
1325 }
1326
1327 /* Check window for sanity */
1328 if ((u8) (txmax - bus->tx_seq) > 0x40) {
1329 brcmf_dbg(ERROR, "unlikely tx max %d with tx_seq %d\n",
1330 txmax, bus->tx_seq);
1331 txmax = bus->tx_seq + 2;
1332 }
1333 bus->tx_max = txmax;
1334
1335 /* Remove superframe header, remember offset */
1336 skb_pull(pfirst, doff);
1337 sfdoff = doff;
1338 num = 0;
1339
1340 /* Validate all the subframe headers */
1341 skb_queue_walk(&bus->glom, pnext) {
1342 /* leave when invalid subframe is found */
1343 if (errcode)
1344 break;
1345
1346 dptr = (u8 *) (pnext->data);
1347 dlen = (u16) (pnext->len);
1348 sublen = get_unaligned_le16(dptr);
1349 check = get_unaligned_le16(dptr + sizeof(u16));
1350 chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
1351 doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
1352 #ifdef BCMDBG
1353 if (BRCMF_GLOM_ON()) {
1354 printk(KERN_DEBUG "subframe:\n");
1355 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
1356 dptr, 32);
1357 }
1358 #endif
1359
1360 if ((u16)~(sublen ^ check)) {
1361 brcmf_dbg(ERROR, "(subframe %d): HW hdr error: len/check 0x%04x/0x%04x\n",
1362 num, sublen, check);
1363 errcode = -1;
1364 } else if ((sublen > dlen) || (sublen < SDPCM_HDRLEN)) {
1365 brcmf_dbg(ERROR, "(subframe %d): length mismatch: len 0x%04x, expect 0x%04x\n",
1366 num, sublen, dlen);
1367 errcode = -1;
1368 } else if ((chan != SDPCM_DATA_CHANNEL) &&
1369 (chan != SDPCM_EVENT_CHANNEL)) {
1370 brcmf_dbg(ERROR, "(subframe %d): bad channel %d\n",
1371 num, chan);
1372 errcode = -1;
1373 } else if ((doff < SDPCM_HDRLEN) || (doff > sublen)) {
1374 brcmf_dbg(ERROR, "(subframe %d): Bad data offset %d: HW %d min %d\n",
1375 num, doff, sublen, SDPCM_HDRLEN);
1376 errcode = -1;
1377 }
1378 /* increase the subframe count */
1379 num++;
1380 }
1381
1382 if (errcode) {
1383 /* Terminate frame on error, request
1384 a couple retries */
1385 if (bus->glomerr++ < 3) {
1386 /* Restore superframe header space */
1387 skb_push(pfirst, sfdoff);
1388 brcmf_sdbrcm_rxfail(bus, true, true);
1389 } else {
1390 bus->glomerr = 0;
1391 brcmf_sdbrcm_rxfail(bus, true, false);
1392 bus->rxglomfail++;
1393 brcmf_sdbrcm_free_glom(bus);
1394 }
1395 bus->nextlen = 0;
1396 return 0;
1397 }
1398
1399 /* Basic SD framing looks ok - process each packet (header) */
1400
1401 skb_queue_walk_safe(&bus->glom, pfirst, pnext) {
1402 dptr = (u8 *) (pfirst->data);
1403 sublen = get_unaligned_le16(dptr);
1404 chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
1405 seq = SDPCM_PACKET_SEQUENCE(&dptr[SDPCM_FRAMETAG_LEN]);
1406 doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
1407
1408 brcmf_dbg(GLOM, "Get subframe %d, %p(%p/%d), sublen %d chan %d seq %d\n",
1409 num, pfirst, pfirst->data,
1410 pfirst->len, sublen, chan, seq);
1411
1412 /* precondition: chan == SDPCM_DATA_CHANNEL ||
1413 chan == SDPCM_EVENT_CHANNEL */
1414
1415 if (rxseq != seq) {
1416 brcmf_dbg(GLOM, "rx_seq %d, expected %d\n",
1417 seq, rxseq);
1418 bus->rx_badseq++;
1419 rxseq = seq;
1420 }
1421 rxseq++;
1422
1423 #ifdef BCMDBG
1424 if (BRCMF_BYTES_ON() && BRCMF_DATA_ON()) {
1425 printk(KERN_DEBUG "Rx Subframe Data:\n");
1426 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
1427 dptr, dlen);
1428 }
1429 #endif
1430
1431 __skb_trim(pfirst, sublen);
1432 skb_pull(pfirst, doff);
1433
1434 if (pfirst->len == 0) {
1435 skb_unlink(pfirst, &bus->glom);
1436 brcmu_pkt_buf_free_skb(pfirst);
1437 continue;
1438 } else if (brcmf_proto_hdrpull(bus->drvr, &ifidx,
1439 pfirst) != 0) {
1440 brcmf_dbg(ERROR, "rx protocol error\n");
1441 bus->drvr->rx_errors++;
1442 skb_unlink(pfirst, &bus->glom);
1443 brcmu_pkt_buf_free_skb(pfirst);
1444 continue;
1445 }
1446
1447 #ifdef BCMDBG
1448 if (BRCMF_GLOM_ON()) {
1449 brcmf_dbg(GLOM, "subframe %d to stack, %p (%p/%d) nxt/lnk %p/%p\n",
1450 bus->glom.qlen, pfirst, pfirst->data,
1451 pfirst->len, pfirst->next,
1452 pfirst->prev);
1453 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
1454 pfirst->data,
1455 min_t(int, pfirst->len, 32));
1456 }
1457 #endif /* BCMDBG */
1458 }
1459 /* sent any remaining packets up */
1460 if (bus->glom.qlen) {
1461 up(&bus->sdsem);
1462 brcmf_rx_frame(bus->drvr, ifidx, &bus->glom);
1463 down(&bus->sdsem);
1464 }
1465
1466 bus->rxglomframes++;
1467 bus->rxglompkts += bus->glom.qlen;
1468 }
1469 return num;
1470 }
1471
1472 static int brcmf_sdbrcm_dcmd_resp_wait(struct brcmf_bus *bus, uint *condition,
1473 bool *pending)
1474 {
1475 DECLARE_WAITQUEUE(wait, current);
1476 int timeout = msecs_to_jiffies(DCMD_RESP_TIMEOUT);
1477
1478 /* Wait until control frame is available */
1479 add_wait_queue(&bus->dcmd_resp_wait, &wait);
1480 set_current_state(TASK_INTERRUPTIBLE);
1481
1482 while (!(*condition) && (!signal_pending(current) && timeout))
1483 timeout = schedule_timeout(timeout);
1484
1485 if (signal_pending(current))
1486 *pending = true;
1487
1488 set_current_state(TASK_RUNNING);
1489 remove_wait_queue(&bus->dcmd_resp_wait, &wait);
1490
1491 return timeout;
1492 }
1493
1494 static int brcmf_sdbrcm_dcmd_resp_wake(struct brcmf_bus *bus)
1495 {
1496 if (waitqueue_active(&bus->dcmd_resp_wait))
1497 wake_up_interruptible(&bus->dcmd_resp_wait);
1498
1499 return 0;
1500 }
1501 static void
1502 brcmf_sdbrcm_read_control(struct brcmf_bus *bus, u8 *hdr, uint len, uint doff)
1503 {
1504 uint rdlen, pad;
1505
1506 int sdret;
1507
1508 brcmf_dbg(TRACE, "Enter\n");
1509
1510 /* Set rxctl for frame (w/optional alignment) */
1511 bus->rxctl = bus->rxbuf;
1512 bus->rxctl += BRCMF_FIRSTREAD;
1513 pad = ((unsigned long)bus->rxctl % BRCMF_SDALIGN);
1514 if (pad)
1515 bus->rxctl += (BRCMF_SDALIGN - pad);
1516 bus->rxctl -= BRCMF_FIRSTREAD;
1517
1518 /* Copy the already-read portion over */
1519 memcpy(bus->rxctl, hdr, BRCMF_FIRSTREAD);
1520 if (len <= BRCMF_FIRSTREAD)
1521 goto gotpkt;
1522
1523 /* Raise rdlen to next SDIO block to avoid tail command */
1524 rdlen = len - BRCMF_FIRSTREAD;
1525 if (bus->roundup && bus->blocksize && (rdlen > bus->blocksize)) {
1526 pad = bus->blocksize - (rdlen % bus->blocksize);
1527 if ((pad <= bus->roundup) && (pad < bus->blocksize) &&
1528 ((len + pad) < bus->drvr->maxctl))
1529 rdlen += pad;
1530 } else if (rdlen % BRCMF_SDALIGN) {
1531 rdlen += BRCMF_SDALIGN - (rdlen % BRCMF_SDALIGN);
1532 }
1533
1534 /* Satisfy length-alignment requirements */
1535 if (rdlen & (ALIGNMENT - 1))
1536 rdlen = roundup(rdlen, ALIGNMENT);
1537
1538 /* Drop if the read is too big or it exceeds our maximum */
1539 if ((rdlen + BRCMF_FIRSTREAD) > bus->drvr->maxctl) {
1540 brcmf_dbg(ERROR, "%d-byte control read exceeds %d-byte buffer\n",
1541 rdlen, bus->drvr->maxctl);
1542 bus->drvr->rx_errors++;
1543 brcmf_sdbrcm_rxfail(bus, false, false);
1544 goto done;
1545 }
1546
1547 if ((len - doff) > bus->drvr->maxctl) {
1548 brcmf_dbg(ERROR, "%d-byte ctl frame (%d-byte ctl data) exceeds %d-byte limit\n",
1549 len, len - doff, bus->drvr->maxctl);
1550 bus->drvr->rx_errors++;
1551 bus->rx_toolong++;
1552 brcmf_sdbrcm_rxfail(bus, false, false);
1553 goto done;
1554 }
1555
1556 /* Read remainder of frame body into the rxctl buffer */
1557 sdret = brcmf_sdcard_recv_buf(bus->sdiodev,
1558 bus->sdiodev->sbwad,
1559 SDIO_FUNC_2,
1560 F2SYNC, (bus->rxctl + BRCMF_FIRSTREAD), rdlen);
1561 bus->f2rxdata++;
1562
1563 /* Control frame failures need retransmission */
1564 if (sdret < 0) {
1565 brcmf_dbg(ERROR, "read %d control bytes failed: %d\n",
1566 rdlen, sdret);
1567 bus->rxc_errors++;
1568 brcmf_sdbrcm_rxfail(bus, true, true);
1569 goto done;
1570 }
1571
1572 gotpkt:
1573
1574 #ifdef BCMDBG
1575 if (BRCMF_BYTES_ON() && BRCMF_CTL_ON()) {
1576 printk(KERN_DEBUG "RxCtrl:\n");
1577 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, bus->rxctl, len);
1578 }
1579 #endif
1580
1581 /* Point to valid data and indicate its length */
1582 bus->rxctl += doff;
1583 bus->rxlen = len - doff;
1584
1585 done:
1586 /* Awake any waiters */
1587 brcmf_sdbrcm_dcmd_resp_wake(bus);
1588 }
1589
1590 /* Pad read to blocksize for efficiency */
1591 static void brcmf_pad(struct brcmf_bus *bus, u16 *pad, u16 *rdlen)
1592 {
1593 if (bus->roundup && bus->blocksize && *rdlen > bus->blocksize) {
1594 *pad = bus->blocksize - (*rdlen % bus->blocksize);
1595 if (*pad <= bus->roundup && *pad < bus->blocksize &&
1596 *rdlen + *pad + BRCMF_FIRSTREAD < MAX_RX_DATASZ)
1597 *rdlen += *pad;
1598 } else if (*rdlen % BRCMF_SDALIGN) {
1599 *rdlen += BRCMF_SDALIGN - (*rdlen % BRCMF_SDALIGN);
1600 }
1601 }
1602
1603 static void
1604 brcmf_alloc_pkt_and_read(struct brcmf_bus *bus, u16 rdlen,
1605 struct sk_buff **pkt, u8 **rxbuf)
1606 {
1607 int sdret; /* Return code from calls */
1608
1609 *pkt = brcmu_pkt_buf_get_skb(rdlen + BRCMF_SDALIGN);
1610 if (*pkt == NULL)
1611 return;
1612
1613 pkt_align(*pkt, rdlen, BRCMF_SDALIGN);
1614 *rxbuf = (u8 *) ((*pkt)->data);
1615 /* Read the entire frame */
1616 sdret = brcmf_sdcard_recv_pkt(bus->sdiodev, bus->sdiodev->sbwad,
1617 SDIO_FUNC_2, F2SYNC, *pkt);
1618 bus->f2rxdata++;
1619
1620 if (sdret < 0) {
1621 brcmf_dbg(ERROR, "(nextlen): read %d bytes failed: %d\n",
1622 rdlen, sdret);
1623 brcmu_pkt_buf_free_skb(*pkt);
1624 bus->drvr->rx_errors++;
1625 /* Force retry w/normal header read.
1626 * Don't attempt NAK for
1627 * gSPI
1628 */
1629 brcmf_sdbrcm_rxfail(bus, true, true);
1630 *pkt = NULL;
1631 }
1632 }
1633
1634 /* Checks the header */
1635 static int
1636 brcmf_check_rxbuf(struct brcmf_bus *bus, struct sk_buff *pkt, u8 *rxbuf,
1637 u8 rxseq, u16 nextlen, u16 *len)
1638 {
1639 u16 check;
1640 bool len_consistent; /* Result of comparing readahead len and
1641 len from hw-hdr */
1642
1643 memcpy(bus->rxhdr, rxbuf, SDPCM_HDRLEN);
1644
1645 /* Extract hardware header fields */
1646 *len = get_unaligned_le16(bus->rxhdr);
1647 check = get_unaligned_le16(bus->rxhdr + sizeof(u16));
1648
1649 /* All zeros means readahead info was bad */
1650 if (!(*len | check)) {
1651 brcmf_dbg(INFO, "(nextlen): read zeros in HW header???\n");
1652 goto fail;
1653 }
1654
1655 /* Validate check bytes */
1656 if ((u16)~(*len ^ check)) {
1657 brcmf_dbg(ERROR, "(nextlen): HW hdr error: nextlen/len/check 0x%04x/0x%04x/0x%04x\n",
1658 nextlen, *len, check);
1659 bus->rx_badhdr++;
1660 brcmf_sdbrcm_rxfail(bus, false, false);
1661 goto fail;
1662 }
1663
1664 /* Validate frame length */
1665 if (*len < SDPCM_HDRLEN) {
1666 brcmf_dbg(ERROR, "(nextlen): HW hdr length invalid: %d\n",
1667 *len);
1668 goto fail;
1669 }
1670
1671 /* Check for consistency with readahead info */
1672 len_consistent = (nextlen != (roundup(*len, 16) >> 4));
1673 if (len_consistent) {
1674 /* Mismatch, force retry w/normal
1675 header (may be >4K) */
1676 brcmf_dbg(ERROR, "(nextlen): mismatch, nextlen %d len %d rnd %d; expected rxseq %d\n",
1677 nextlen, *len, roundup(*len, 16),
1678 rxseq);
1679 brcmf_sdbrcm_rxfail(bus, true, true);
1680 goto fail;
1681 }
1682
1683 return 0;
1684
1685 fail:
1686 brcmf_sdbrcm_pktfree2(bus, pkt);
1687 return -EINVAL;
1688 }
1689
1690 /* Return true if there may be more frames to read */
1691 static uint
1692 brcmf_sdbrcm_readframes(struct brcmf_bus *bus, uint maxframes, bool *finished)
1693 {
1694 u16 len, check; /* Extracted hardware header fields */
1695 u8 chan, seq, doff; /* Extracted software header fields */
1696 u8 fcbits; /* Extracted fcbits from software header */
1697
1698 struct sk_buff *pkt; /* Packet for event or data frames */
1699 u16 pad; /* Number of pad bytes to read */
1700 u16 rdlen; /* Total number of bytes to read */
1701 u8 rxseq; /* Next sequence number to expect */
1702 uint rxleft = 0; /* Remaining number of frames allowed */
1703 int sdret; /* Return code from calls */
1704 u8 txmax; /* Maximum tx sequence offered */
1705 u8 *rxbuf;
1706 int ifidx = 0;
1707 uint rxcount = 0; /* Total frames read */
1708
1709 brcmf_dbg(TRACE, "Enter\n");
1710
1711 /* Not finished unless we encounter no more frames indication */
1712 *finished = false;
1713
1714 for (rxseq = bus->rx_seq, rxleft = maxframes;
1715 !bus->rxskip && rxleft && bus->drvr->busstate != BRCMF_BUS_DOWN;
1716 rxseq++, rxleft--) {
1717
1718 /* Handle glomming separately */
1719 if (bus->glomd || !skb_queue_empty(&bus->glom)) {
1720 u8 cnt;
1721 brcmf_dbg(GLOM, "calling rxglom: glomd %p, glom %p\n",
1722 bus->glomd, skb_peek(&bus->glom));
1723 cnt = brcmf_sdbrcm_rxglom(bus, rxseq);
1724 brcmf_dbg(GLOM, "rxglom returned %d\n", cnt);
1725 rxseq += cnt - 1;
1726 rxleft = (rxleft > cnt) ? (rxleft - cnt) : 1;
1727 continue;
1728 }
1729
1730 /* Try doing single read if we can */
1731 if (bus->nextlen) {
1732 u16 nextlen = bus->nextlen;
1733 bus->nextlen = 0;
1734
1735 rdlen = len = nextlen << 4;
1736 brcmf_pad(bus, &pad, &rdlen);
1737
1738 /*
1739 * After the frame is received we have to
1740 * distinguish whether it is data
1741 * or non-data frame.
1742 */
1743 brcmf_alloc_pkt_and_read(bus, rdlen, &pkt, &rxbuf);
1744 if (pkt == NULL) {
1745 /* Give up on data, request rtx of events */
1746 brcmf_dbg(ERROR, "(nextlen): brcmf_alloc_pkt_and_read failed: len %d rdlen %d expected rxseq %d\n",
1747 len, rdlen, rxseq);
1748 continue;
1749 }
1750
1751 if (brcmf_check_rxbuf(bus, pkt, rxbuf, rxseq, nextlen,
1752 &len) < 0)
1753 continue;
1754
1755 /* Extract software header fields */
1756 chan = SDPCM_PACKET_CHANNEL(
1757 &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
1758 seq = SDPCM_PACKET_SEQUENCE(
1759 &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
1760 doff = SDPCM_DOFFSET_VALUE(
1761 &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
1762 txmax = SDPCM_WINDOW_VALUE(
1763 &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
1764
1765 bus->nextlen =
1766 bus->rxhdr[SDPCM_FRAMETAG_LEN +
1767 SDPCM_NEXTLEN_OFFSET];
1768 if ((bus->nextlen << 4) > MAX_RX_DATASZ) {
1769 brcmf_dbg(INFO, "(nextlen): got frame w/nextlen too large (%d), seq %d\n",
1770 bus->nextlen, seq);
1771 bus->nextlen = 0;
1772 }
1773
1774 bus->drvr->rx_readahead_cnt++;
1775
1776 /* Handle Flow Control */
1777 fcbits = SDPCM_FCMASK_VALUE(
1778 &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
1779
1780 if (bus->flowcontrol != fcbits) {
1781 if (~bus->flowcontrol & fcbits)
1782 bus->fc_xoff++;
1783
1784 if (bus->flowcontrol & ~fcbits)
1785 bus->fc_xon++;
1786
1787 bus->fc_rcvd++;
1788 bus->flowcontrol = fcbits;
1789 }
1790
1791 /* Check and update sequence number */
1792 if (rxseq != seq) {
1793 brcmf_dbg(INFO, "(nextlen): rx_seq %d, expected %d\n",
1794 seq, rxseq);
1795 bus->rx_badseq++;
1796 rxseq = seq;
1797 }
1798
1799 /* Check window for sanity */
1800 if ((u8) (txmax - bus->tx_seq) > 0x40) {
1801 brcmf_dbg(ERROR, "got unlikely tx max %d with tx_seq %d\n",
1802 txmax, bus->tx_seq);
1803 txmax = bus->tx_seq + 2;
1804 }
1805 bus->tx_max = txmax;
1806
1807 #ifdef BCMDBG
1808 if (BRCMF_BYTES_ON() && BRCMF_DATA_ON()) {
1809 printk(KERN_DEBUG "Rx Data:\n");
1810 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
1811 rxbuf, len);
1812 } else if (BRCMF_HDRS_ON()) {
1813 printk(KERN_DEBUG "RxHdr:\n");
1814 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
1815 bus->rxhdr, SDPCM_HDRLEN);
1816 }
1817 #endif
1818
1819 if (chan == SDPCM_CONTROL_CHANNEL) {
1820 brcmf_dbg(ERROR, "(nextlen): readahead on control packet %d?\n",
1821 seq);
1822 /* Force retry w/normal header read */
1823 bus->nextlen = 0;
1824 brcmf_sdbrcm_rxfail(bus, false, true);
1825 brcmf_sdbrcm_pktfree2(bus, pkt);
1826 continue;
1827 }
1828
1829 /* Validate data offset */
1830 if ((doff < SDPCM_HDRLEN) || (doff > len)) {
1831 brcmf_dbg(ERROR, "(nextlen): bad data offset %d: HW len %d min %d\n",
1832 doff, len, SDPCM_HDRLEN);
1833 brcmf_sdbrcm_rxfail(bus, false, false);
1834 brcmf_sdbrcm_pktfree2(bus, pkt);
1835 continue;
1836 }
1837
1838 /* All done with this one -- now deliver the packet */
1839 goto deliver;
1840 }
1841
1842 /* Read frame header (hardware and software) */
1843 sdret = brcmf_sdcard_recv_buf(bus->sdiodev, bus->sdiodev->sbwad,
1844 SDIO_FUNC_2, F2SYNC, bus->rxhdr,
1845 BRCMF_FIRSTREAD);
1846 bus->f2rxhdrs++;
1847
1848 if (sdret < 0) {
1849 brcmf_dbg(ERROR, "RXHEADER FAILED: %d\n", sdret);
1850 bus->rx_hdrfail++;
1851 brcmf_sdbrcm_rxfail(bus, true, true);
1852 continue;
1853 }
1854 #ifdef BCMDBG
1855 if (BRCMF_BYTES_ON() || BRCMF_HDRS_ON()) {
1856 printk(KERN_DEBUG "RxHdr:\n");
1857 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
1858 bus->rxhdr, SDPCM_HDRLEN);
1859 }
1860 #endif
1861
1862 /* Extract hardware header fields */
1863 len = get_unaligned_le16(bus->rxhdr);
1864 check = get_unaligned_le16(bus->rxhdr + sizeof(u16));
1865
1866 /* All zeros means no more frames */
1867 if (!(len | check)) {
1868 *finished = true;
1869 break;
1870 }
1871
1872 /* Validate check bytes */
1873 if ((u16) ~(len ^ check)) {
1874 brcmf_dbg(ERROR, "HW hdr err: len/check 0x%04x/0x%04x\n",
1875 len, check);
1876 bus->rx_badhdr++;
1877 brcmf_sdbrcm_rxfail(bus, false, false);
1878 continue;
1879 }
1880
1881 /* Validate frame length */
1882 if (len < SDPCM_HDRLEN) {
1883 brcmf_dbg(ERROR, "HW hdr length invalid: %d\n", len);
1884 continue;
1885 }
1886
1887 /* Extract software header fields */
1888 chan = SDPCM_PACKET_CHANNEL(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
1889 seq = SDPCM_PACKET_SEQUENCE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
1890 doff = SDPCM_DOFFSET_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
1891 txmax = SDPCM_WINDOW_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
1892
1893 /* Validate data offset */
1894 if ((doff < SDPCM_HDRLEN) || (doff > len)) {
1895 brcmf_dbg(ERROR, "Bad data offset %d: HW len %d, min %d seq %d\n",
1896 doff, len, SDPCM_HDRLEN, seq);
1897 bus->rx_badhdr++;
1898 brcmf_sdbrcm_rxfail(bus, false, false);
1899 continue;
1900 }
1901
1902 /* Save the readahead length if there is one */
1903 bus->nextlen =
1904 bus->rxhdr[SDPCM_FRAMETAG_LEN + SDPCM_NEXTLEN_OFFSET];
1905 if ((bus->nextlen << 4) > MAX_RX_DATASZ) {
1906 brcmf_dbg(INFO, "(nextlen): got frame w/nextlen too large (%d), seq %d\n",
1907 bus->nextlen, seq);
1908 bus->nextlen = 0;
1909 }
1910
1911 /* Handle Flow Control */
1912 fcbits = SDPCM_FCMASK_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
1913
1914 if (bus->flowcontrol != fcbits) {
1915 if (~bus->flowcontrol & fcbits)
1916 bus->fc_xoff++;
1917
1918 if (bus->flowcontrol & ~fcbits)
1919 bus->fc_xon++;
1920
1921 bus->fc_rcvd++;
1922 bus->flowcontrol = fcbits;
1923 }
1924
1925 /* Check and update sequence number */
1926 if (rxseq != seq) {
1927 brcmf_dbg(INFO, "rx_seq %d, expected %d\n", seq, rxseq);
1928 bus->rx_badseq++;
1929 rxseq = seq;
1930 }
1931
1932 /* Check window for sanity */
1933 if ((u8) (txmax - bus->tx_seq) > 0x40) {
1934 brcmf_dbg(ERROR, "unlikely tx max %d with tx_seq %d\n",
1935 txmax, bus->tx_seq);
1936 txmax = bus->tx_seq + 2;
1937 }
1938 bus->tx_max = txmax;
1939
1940 /* Call a separate function for control frames */
1941 if (chan == SDPCM_CONTROL_CHANNEL) {
1942 brcmf_sdbrcm_read_control(bus, bus->rxhdr, len, doff);
1943 continue;
1944 }
1945
1946 /* precondition: chan is either SDPCM_DATA_CHANNEL,
1947 SDPCM_EVENT_CHANNEL, SDPCM_TEST_CHANNEL or
1948 SDPCM_GLOM_CHANNEL */
1949
1950 /* Length to read */
1951 rdlen = (len > BRCMF_FIRSTREAD) ? (len - BRCMF_FIRSTREAD) : 0;
1952
1953 /* May pad read to blocksize for efficiency */
1954 if (bus->roundup && bus->blocksize &&
1955 (rdlen > bus->blocksize)) {
1956 pad = bus->blocksize - (rdlen % bus->blocksize);
1957 if ((pad <= bus->roundup) && (pad < bus->blocksize) &&
1958 ((rdlen + pad + BRCMF_FIRSTREAD) < MAX_RX_DATASZ))
1959 rdlen += pad;
1960 } else if (rdlen % BRCMF_SDALIGN) {
1961 rdlen += BRCMF_SDALIGN - (rdlen % BRCMF_SDALIGN);
1962 }
1963
1964 /* Satisfy length-alignment requirements */
1965 if (rdlen & (ALIGNMENT - 1))
1966 rdlen = roundup(rdlen, ALIGNMENT);
1967
1968 if ((rdlen + BRCMF_FIRSTREAD) > MAX_RX_DATASZ) {
1969 /* Too long -- skip this frame */
1970 brcmf_dbg(ERROR, "too long: len %d rdlen %d\n",
1971 len, rdlen);
1972 bus->drvr->rx_errors++;
1973 bus->rx_toolong++;
1974 brcmf_sdbrcm_rxfail(bus, false, false);
1975 continue;
1976 }
1977
1978 pkt = brcmu_pkt_buf_get_skb(rdlen +
1979 BRCMF_FIRSTREAD + BRCMF_SDALIGN);
1980 if (!pkt) {
1981 /* Give up on data, request rtx of events */
1982 brcmf_dbg(ERROR, "brcmu_pkt_buf_get_skb failed: rdlen %d chan %d\n",
1983 rdlen, chan);
1984 bus->drvr->rx_dropped++;
1985 brcmf_sdbrcm_rxfail(bus, false, RETRYCHAN(chan));
1986 continue;
1987 }
1988
1989 /* Leave room for what we already read, and align remainder */
1990 skb_pull(pkt, BRCMF_FIRSTREAD);
1991 pkt_align(pkt, rdlen, BRCMF_SDALIGN);
1992
1993 /* Read the remaining frame data */
1994 sdret = brcmf_sdcard_recv_pkt(bus->sdiodev, bus->sdiodev->sbwad,
1995 SDIO_FUNC_2, F2SYNC, pkt);
1996 bus->f2rxdata++;
1997
1998 if (sdret < 0) {
1999 brcmf_dbg(ERROR, "read %d %s bytes failed: %d\n", rdlen,
2000 ((chan == SDPCM_EVENT_CHANNEL) ? "event"
2001 : ((chan == SDPCM_DATA_CHANNEL) ? "data"
2002 : "test")), sdret);
2003 brcmu_pkt_buf_free_skb(pkt);
2004 bus->drvr->rx_errors++;
2005 brcmf_sdbrcm_rxfail(bus, true, RETRYCHAN(chan));
2006 continue;
2007 }
2008
2009 /* Copy the already-read portion */
2010 skb_push(pkt, BRCMF_FIRSTREAD);
2011 memcpy(pkt->data, bus->rxhdr, BRCMF_FIRSTREAD);
2012
2013 #ifdef BCMDBG
2014 if (BRCMF_BYTES_ON() && BRCMF_DATA_ON()) {
2015 printk(KERN_DEBUG "Rx Data:\n");
2016 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
2017 pkt->data, len);
2018 }
2019 #endif
2020
2021 deliver:
2022 /* Save superframe descriptor and allocate packet frame */
2023 if (chan == SDPCM_GLOM_CHANNEL) {
2024 if (SDPCM_GLOMDESC(&bus->rxhdr[SDPCM_FRAMETAG_LEN])) {
2025 brcmf_dbg(GLOM, "glom descriptor, %d bytes:\n",
2026 len);
2027 #ifdef BCMDBG
2028 if (BRCMF_GLOM_ON()) {
2029 printk(KERN_DEBUG "Glom Data:\n");
2030 print_hex_dump_bytes("",
2031 DUMP_PREFIX_OFFSET,
2032 pkt->data, len);
2033 }
2034 #endif
2035 __skb_trim(pkt, len);
2036 skb_pull(pkt, SDPCM_HDRLEN);
2037 bus->glomd = pkt;
2038 } else {
2039 brcmf_dbg(ERROR, "%s: glom superframe w/o "
2040 "descriptor!\n", __func__);
2041 brcmf_sdbrcm_rxfail(bus, false, false);
2042 }
2043 continue;
2044 }
2045
2046 /* Fill in packet len and prio, deliver upward */
2047 __skb_trim(pkt, len);
2048 skb_pull(pkt, doff);
2049
2050 if (pkt->len == 0) {
2051 brcmu_pkt_buf_free_skb(pkt);
2052 continue;
2053 } else if (brcmf_proto_hdrpull(bus->drvr, &ifidx, pkt) != 0) {
2054 brcmf_dbg(ERROR, "rx protocol error\n");
2055 brcmu_pkt_buf_free_skb(pkt);
2056 bus->drvr->rx_errors++;
2057 continue;
2058 }
2059
2060 /* Unlock during rx call */
2061 up(&bus->sdsem);
2062 brcmf_rx_packet(bus->drvr, ifidx, pkt);
2063 down(&bus->sdsem);
2064 }
2065 rxcount = maxframes - rxleft;
2066 #ifdef BCMDBG
2067 /* Message if we hit the limit */
2068 if (!rxleft)
2069 brcmf_dbg(DATA, "hit rx limit of %d frames\n",
2070 maxframes);
2071 else
2072 #endif /* BCMDBG */
2073 brcmf_dbg(DATA, "processed %d frames\n", rxcount);
2074 /* Back off rxseq if awaiting rtx, update rx_seq */
2075 if (bus->rxskip)
2076 rxseq--;
2077 bus->rx_seq = rxseq;
2078
2079 return rxcount;
2080 }
2081
2082 static void
2083 brcmf_sdbrcm_wait_for_event(struct brcmf_bus *bus, bool *lockvar)
2084 {
2085 up(&bus->sdsem);
2086 wait_event_interruptible_timeout(bus->ctrl_wait,
2087 (*lockvar == false), HZ * 2);
2088 down(&bus->sdsem);
2089 return;
2090 }
2091
2092 static void
2093 brcmf_sdbrcm_wait_event_wakeup(struct brcmf_bus *bus)
2094 {
2095 if (waitqueue_active(&bus->ctrl_wait))
2096 wake_up_interruptible(&bus->ctrl_wait);
2097 return;
2098 }
2099
2100 /* Writes a HW/SW header into the packet and sends it. */
2101 /* Assumes: (a) header space already there, (b) caller holds lock */
2102 static int brcmf_sdbrcm_txpkt(struct brcmf_bus *bus, struct sk_buff *pkt,
2103 uint chan, bool free_pkt)
2104 {
2105 int ret;
2106 u8 *frame;
2107 u16 len, pad = 0;
2108 u32 swheader;
2109 struct sk_buff *new;
2110 int i;
2111
2112 brcmf_dbg(TRACE, "Enter\n");
2113
2114 frame = (u8 *) (pkt->data);
2115
2116 /* Add alignment padding, allocate new packet if needed */
2117 pad = ((unsigned long)frame % BRCMF_SDALIGN);
2118 if (pad) {
2119 if (skb_headroom(pkt) < pad) {
2120 brcmf_dbg(INFO, "insufficient headroom %d for %d pad\n",
2121 skb_headroom(pkt), pad);
2122 bus->drvr->tx_realloc++;
2123 new = brcmu_pkt_buf_get_skb(pkt->len + BRCMF_SDALIGN);
2124 if (!new) {
2125 brcmf_dbg(ERROR, "couldn't allocate new %d-byte packet\n",
2126 pkt->len + BRCMF_SDALIGN);
2127 ret = -ENOMEM;
2128 goto done;
2129 }
2130
2131 pkt_align(new, pkt->len, BRCMF_SDALIGN);
2132 memcpy(new->data, pkt->data, pkt->len);
2133 if (free_pkt)
2134 brcmu_pkt_buf_free_skb(pkt);
2135 /* free the pkt if canned one is not used */
2136 free_pkt = true;
2137 pkt = new;
2138 frame = (u8 *) (pkt->data);
2139 /* precondition: (frame % BRCMF_SDALIGN) == 0) */
2140 pad = 0;
2141 } else {
2142 skb_push(pkt, pad);
2143 frame = (u8 *) (pkt->data);
2144 /* precondition: pad + SDPCM_HDRLEN <= pkt->len */
2145 memset(frame, 0, pad + SDPCM_HDRLEN);
2146 }
2147 }
2148 /* precondition: pad < BRCMF_SDALIGN */
2149
2150 /* Hardware tag: 2 byte len followed by 2 byte ~len check (all LE) */
2151 len = (u16) (pkt->len);
2152 *(__le16 *) frame = cpu_to_le16(len);
2153 *(((__le16 *) frame) + 1) = cpu_to_le16(~len);
2154
2155 /* Software tag: channel, sequence number, data offset */
2156 swheader =
2157 ((chan << SDPCM_CHANNEL_SHIFT) & SDPCM_CHANNEL_MASK) | bus->tx_seq |
2158 (((pad +
2159 SDPCM_HDRLEN) << SDPCM_DOFFSET_SHIFT) & SDPCM_DOFFSET_MASK);
2160
2161 put_unaligned_le32(swheader, frame + SDPCM_FRAMETAG_LEN);
2162 put_unaligned_le32(0, frame + SDPCM_FRAMETAG_LEN + sizeof(swheader));
2163
2164 #ifdef BCMDBG
2165 tx_packets[pkt->priority]++;
2166 if (BRCMF_BYTES_ON() &&
2167 (((BRCMF_CTL_ON() && (chan == SDPCM_CONTROL_CHANNEL)) ||
2168 (BRCMF_DATA_ON() && (chan != SDPCM_CONTROL_CHANNEL))))) {
2169 printk(KERN_DEBUG "Tx Frame:\n");
2170 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, frame, len);
2171 } else if (BRCMF_HDRS_ON()) {
2172 printk(KERN_DEBUG "TxHdr:\n");
2173 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
2174 frame, min_t(u16, len, 16));
2175 }
2176 #endif
2177
2178 /* Raise len to next SDIO block to eliminate tail command */
2179 if (bus->roundup && bus->blocksize && (len > bus->blocksize)) {
2180 u16 pad = bus->blocksize - (len % bus->blocksize);
2181 if ((pad <= bus->roundup) && (pad < bus->blocksize))
2182 len += pad;
2183 } else if (len % BRCMF_SDALIGN) {
2184 len += BRCMF_SDALIGN - (len % BRCMF_SDALIGN);
2185 }
2186
2187 /* Some controllers have trouble with odd bytes -- round to even */
2188 if (len & (ALIGNMENT - 1))
2189 len = roundup(len, ALIGNMENT);
2190
2191 ret = brcmf_sdcard_send_pkt(bus->sdiodev, bus->sdiodev->sbwad,
2192 SDIO_FUNC_2, F2SYNC, pkt);
2193 bus->f2txdata++;
2194
2195 if (ret < 0) {
2196 /* On failure, abort the command and terminate the frame */
2197 brcmf_dbg(INFO, "sdio error %d, abort command and terminate frame\n",
2198 ret);
2199 bus->tx_sderrs++;
2200
2201 brcmf_sdcard_abort(bus->sdiodev, SDIO_FUNC_2);
2202 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
2203 SBSDIO_FUNC1_FRAMECTRL, SFC_WF_TERM,
2204 NULL);
2205 bus->f1regdata++;
2206
2207 for (i = 0; i < 3; i++) {
2208 u8 hi, lo;
2209 hi = brcmf_sdcard_cfg_read(bus->sdiodev,
2210 SDIO_FUNC_1,
2211 SBSDIO_FUNC1_WFRAMEBCHI,
2212 NULL);
2213 lo = brcmf_sdcard_cfg_read(bus->sdiodev,
2214 SDIO_FUNC_1,
2215 SBSDIO_FUNC1_WFRAMEBCLO,
2216 NULL);
2217 bus->f1regdata += 2;
2218 if ((hi == 0) && (lo == 0))
2219 break;
2220 }
2221
2222 }
2223 if (ret == 0)
2224 bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
2225
2226 done:
2227 /* restore pkt buffer pointer before calling tx complete routine */
2228 skb_pull(pkt, SDPCM_HDRLEN + pad);
2229 up(&bus->sdsem);
2230 brcmf_txcomplete(bus->drvr, pkt, ret != 0);
2231 down(&bus->sdsem);
2232
2233 if (free_pkt)
2234 brcmu_pkt_buf_free_skb(pkt);
2235
2236 return ret;
2237 }
2238
2239 static uint brcmf_sdbrcm_sendfromq(struct brcmf_bus *bus, uint maxframes)
2240 {
2241 struct sk_buff *pkt;
2242 u32 intstatus = 0;
2243 uint retries = 0;
2244 int ret = 0, prec_out;
2245 uint cnt = 0;
2246 uint datalen;
2247 u8 tx_prec_map;
2248
2249 struct brcmf_pub *drvr = bus->drvr;
2250
2251 brcmf_dbg(TRACE, "Enter\n");
2252
2253 tx_prec_map = ~bus->flowcontrol;
2254
2255 /* Send frames until the limit or some other event */
2256 for (cnt = 0; (cnt < maxframes) && data_ok(bus); cnt++) {
2257 spin_lock_bh(&bus->txqlock);
2258 pkt = brcmu_pktq_mdeq(&bus->txq, tx_prec_map, &prec_out);
2259 if (pkt == NULL) {
2260 spin_unlock_bh(&bus->txqlock);
2261 break;
2262 }
2263 spin_unlock_bh(&bus->txqlock);
2264 datalen = pkt->len - SDPCM_HDRLEN;
2265
2266 ret = brcmf_sdbrcm_txpkt(bus, pkt, SDPCM_DATA_CHANNEL, true);
2267 if (ret)
2268 bus->drvr->tx_errors++;
2269 else
2270 bus->drvr->dstats.tx_bytes += datalen;
2271
2272 /* In poll mode, need to check for other events */
2273 if (!bus->intr && cnt) {
2274 /* Check device status, signal pending interrupt */
2275 r_sdreg32(bus, &intstatus,
2276 offsetof(struct sdpcmd_regs, intstatus),
2277 &retries);
2278 bus->f2txdata++;
2279 if (brcmf_sdcard_regfail(bus->sdiodev))
2280 break;
2281 if (intstatus & bus->hostintmask)
2282 bus->ipend = true;
2283 }
2284 }
2285
2286 /* Deflow-control stack if needed */
2287 if (drvr->up && (drvr->busstate == BRCMF_BUS_DATA) &&
2288 drvr->txoff && (pktq_len(&bus->txq) < TXLOW))
2289 brcmf_txflowcontrol(drvr, 0, OFF);
2290
2291 return cnt;
2292 }
2293
2294 static bool brcmf_sdbrcm_dpc(struct brcmf_bus *bus)
2295 {
2296 u32 intstatus, newstatus = 0;
2297 uint retries = 0;
2298 uint rxlimit = bus->rxbound; /* Rx frames to read before resched */
2299 uint txlimit = bus->txbound; /* Tx frames to send before resched */
2300 uint framecnt = 0; /* Temporary counter of tx/rx frames */
2301 bool rxdone = true; /* Flag for no more read data */
2302 bool resched = false; /* Flag indicating resched wanted */
2303
2304 brcmf_dbg(TRACE, "Enter\n");
2305
2306 /* Start with leftover status bits */
2307 intstatus = bus->intstatus;
2308
2309 down(&bus->sdsem);
2310
2311 /* If waiting for HTAVAIL, check status */
2312 if (bus->clkstate == CLK_PENDING) {
2313 int err;
2314 u8 clkctl, devctl = 0;
2315
2316 #ifdef BCMDBG
2317 /* Check for inconsistent device control */
2318 devctl = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
2319 SBSDIO_DEVICE_CTL, &err);
2320 if (err) {
2321 brcmf_dbg(ERROR, "error reading DEVCTL: %d\n", err);
2322 bus->drvr->busstate = BRCMF_BUS_DOWN;
2323 }
2324 #endif /* BCMDBG */
2325
2326 /* Read CSR, if clock on switch to AVAIL, else ignore */
2327 clkctl = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
2328 SBSDIO_FUNC1_CHIPCLKCSR, &err);
2329 if (err) {
2330 brcmf_dbg(ERROR, "error reading CSR: %d\n",
2331 err);
2332 bus->drvr->busstate = BRCMF_BUS_DOWN;
2333 }
2334
2335 brcmf_dbg(INFO, "DPC: PENDING, devctl 0x%02x clkctl 0x%02x\n",
2336 devctl, clkctl);
2337
2338 if (SBSDIO_HTAV(clkctl)) {
2339 devctl = brcmf_sdcard_cfg_read(bus->sdiodev,
2340 SDIO_FUNC_1,
2341 SBSDIO_DEVICE_CTL, &err);
2342 if (err) {
2343 brcmf_dbg(ERROR, "error reading DEVCTL: %d\n",
2344 err);
2345 bus->drvr->busstate = BRCMF_BUS_DOWN;
2346 }
2347 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
2348 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
2349 SBSDIO_DEVICE_CTL, devctl, &err);
2350 if (err) {
2351 brcmf_dbg(ERROR, "error writing DEVCTL: %d\n",
2352 err);
2353 bus->drvr->busstate = BRCMF_BUS_DOWN;
2354 }
2355 bus->clkstate = CLK_AVAIL;
2356 } else {
2357 goto clkwait;
2358 }
2359 }
2360
2361 bus_wake(bus);
2362
2363 /* Make sure backplane clock is on */
2364 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, true);
2365 if (bus->clkstate == CLK_PENDING)
2366 goto clkwait;
2367
2368 /* Pending interrupt indicates new device status */
2369 if (bus->ipend) {
2370 bus->ipend = false;
2371 r_sdreg32(bus, &newstatus,
2372 offsetof(struct sdpcmd_regs, intstatus), &retries);
2373 bus->f1regdata++;
2374 if (brcmf_sdcard_regfail(bus->sdiodev))
2375 newstatus = 0;
2376 newstatus &= bus->hostintmask;
2377 bus->fcstate = !!(newstatus & I_HMB_FC_STATE);
2378 if (newstatus) {
2379 w_sdreg32(bus, newstatus,
2380 offsetof(struct sdpcmd_regs, intstatus),
2381 &retries);
2382 bus->f1regdata++;
2383 }
2384 }
2385
2386 /* Merge new bits with previous */
2387 intstatus |= newstatus;
2388 bus->intstatus = 0;
2389
2390 /* Handle flow-control change: read new state in case our ack
2391 * crossed another change interrupt. If change still set, assume
2392 * FC ON for safety, let next loop through do the debounce.
2393 */
2394 if (intstatus & I_HMB_FC_CHANGE) {
2395 intstatus &= ~I_HMB_FC_CHANGE;
2396 w_sdreg32(bus, I_HMB_FC_CHANGE,
2397 offsetof(struct sdpcmd_regs, intstatus), &retries);
2398
2399 r_sdreg32(bus, &newstatus,
2400 offsetof(struct sdpcmd_regs, intstatus), &retries);
2401 bus->f1regdata += 2;
2402 bus->fcstate =
2403 !!(newstatus & (I_HMB_FC_STATE | I_HMB_FC_CHANGE));
2404 intstatus |= (newstatus & bus->hostintmask);
2405 }
2406
2407 /* Handle host mailbox indication */
2408 if (intstatus & I_HMB_HOST_INT) {
2409 intstatus &= ~I_HMB_HOST_INT;
2410 intstatus |= brcmf_sdbrcm_hostmail(bus);
2411 }
2412
2413 /* Generally don't ask for these, can get CRC errors... */
2414 if (intstatus & I_WR_OOSYNC) {
2415 brcmf_dbg(ERROR, "Dongle reports WR_OOSYNC\n");
2416 intstatus &= ~I_WR_OOSYNC;
2417 }
2418
2419 if (intstatus & I_RD_OOSYNC) {
2420 brcmf_dbg(ERROR, "Dongle reports RD_OOSYNC\n");
2421 intstatus &= ~I_RD_OOSYNC;
2422 }
2423
2424 if (intstatus & I_SBINT) {
2425 brcmf_dbg(ERROR, "Dongle reports SBINT\n");
2426 intstatus &= ~I_SBINT;
2427 }
2428
2429 /* Would be active due to wake-wlan in gSPI */
2430 if (intstatus & I_CHIPACTIVE) {
2431 brcmf_dbg(INFO, "Dongle reports CHIPACTIVE\n");
2432 intstatus &= ~I_CHIPACTIVE;
2433 }
2434
2435 /* Ignore frame indications if rxskip is set */
2436 if (bus->rxskip)
2437 intstatus &= ~I_HMB_FRAME_IND;
2438
2439 /* On frame indication, read available frames */
2440 if (PKT_AVAILABLE()) {
2441 framecnt = brcmf_sdbrcm_readframes(bus, rxlimit, &rxdone);
2442 if (rxdone || bus->rxskip)
2443 intstatus &= ~I_HMB_FRAME_IND;
2444 rxlimit -= min(framecnt, rxlimit);
2445 }
2446
2447 /* Keep still-pending events for next scheduling */
2448 bus->intstatus = intstatus;
2449
2450 clkwait:
2451 if (data_ok(bus) && bus->ctrl_frame_stat &&
2452 (bus->clkstate == CLK_AVAIL)) {
2453 int ret, i;
2454
2455 ret = brcmf_sdcard_send_buf(bus->sdiodev, bus->sdiodev->sbwad,
2456 SDIO_FUNC_2, F2SYNC, (u8 *) bus->ctrl_frame_buf,
2457 (u32) bus->ctrl_frame_len);
2458
2459 if (ret < 0) {
2460 /* On failure, abort the command and
2461 terminate the frame */
2462 brcmf_dbg(INFO, "sdio error %d, abort command and terminate frame\n",
2463 ret);
2464 bus->tx_sderrs++;
2465
2466 brcmf_sdcard_abort(bus->sdiodev, SDIO_FUNC_2);
2467
2468 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
2469 SBSDIO_FUNC1_FRAMECTRL, SFC_WF_TERM,
2470 NULL);
2471 bus->f1regdata++;
2472
2473 for (i = 0; i < 3; i++) {
2474 u8 hi, lo;
2475 hi = brcmf_sdcard_cfg_read(bus->sdiodev,
2476 SDIO_FUNC_1,
2477 SBSDIO_FUNC1_WFRAMEBCHI,
2478 NULL);
2479 lo = brcmf_sdcard_cfg_read(bus->sdiodev,
2480 SDIO_FUNC_1,
2481 SBSDIO_FUNC1_WFRAMEBCLO,
2482 NULL);
2483 bus->f1regdata += 2;
2484 if ((hi == 0) && (lo == 0))
2485 break;
2486 }
2487
2488 }
2489 if (ret == 0)
2490 bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
2491
2492 brcmf_dbg(INFO, "Return_dpc value is : %d\n", ret);
2493 bus->ctrl_frame_stat = false;
2494 brcmf_sdbrcm_wait_event_wakeup(bus);
2495 }
2496 /* Send queued frames (limit 1 if rx may still be pending) */
2497 else if ((bus->clkstate == CLK_AVAIL) && !bus->fcstate &&
2498 brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol) && txlimit
2499 && data_ok(bus)) {
2500 framecnt = rxdone ? txlimit : min(txlimit, bus->txminmax);
2501 framecnt = brcmf_sdbrcm_sendfromq(bus, framecnt);
2502 txlimit -= framecnt;
2503 }
2504
2505 /* Resched if events or tx frames are pending,
2506 else await next interrupt */
2507 /* On failed register access, all bets are off:
2508 no resched or interrupts */
2509 if ((bus->drvr->busstate == BRCMF_BUS_DOWN) ||
2510 brcmf_sdcard_regfail(bus->sdiodev)) {
2511 brcmf_dbg(ERROR, "failed backplane access over SDIO, halting operation %d\n",
2512 brcmf_sdcard_regfail(bus->sdiodev));
2513 bus->drvr->busstate = BRCMF_BUS_DOWN;
2514 bus->intstatus = 0;
2515 } else if (bus->clkstate == CLK_PENDING) {
2516 brcmf_dbg(INFO, "rescheduled due to CLK_PENDING awaiting I_CHIPACTIVE interrupt\n");
2517 resched = true;
2518 } else if (bus->intstatus || bus->ipend ||
2519 (!bus->fcstate && brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol)
2520 && data_ok(bus)) || PKT_AVAILABLE()) {
2521 resched = true;
2522 }
2523
2524 bus->dpc_sched = resched;
2525
2526 /* If we're done for now, turn off clock request. */
2527 if ((bus->clkstate != CLK_PENDING)
2528 && bus->idletime == BRCMF_IDLE_IMMEDIATE) {
2529 bus->activity = false;
2530 brcmf_sdbrcm_clkctl(bus, CLK_NONE, false);
2531 }
2532
2533 up(&bus->sdsem);
2534
2535 return resched;
2536 }
2537
2538 static int brcmf_sdbrcm_dpc_thread(void *data)
2539 {
2540 struct brcmf_bus *bus = (struct brcmf_bus *) data;
2541
2542 allow_signal(SIGTERM);
2543 /* Run until signal received */
2544 while (1) {
2545 if (kthread_should_stop())
2546 break;
2547 if (!wait_for_completion_interruptible(&bus->dpc_wait)) {
2548 /* Call bus dpc unless it indicated down
2549 (then clean stop) */
2550 if (bus->drvr->busstate != BRCMF_BUS_DOWN) {
2551 if (brcmf_sdbrcm_dpc(bus))
2552 complete(&bus->dpc_wait);
2553 } else {
2554 /* after stopping the bus, exit thread */
2555 brcmf_sdbrcm_bus_stop(bus);
2556 bus->dpc_tsk = NULL;
2557 break;
2558 }
2559 } else
2560 break;
2561 }
2562 return 0;
2563 }
2564
2565 int brcmf_sdbrcm_bus_txdata(struct brcmf_bus *bus, struct sk_buff *pkt)
2566 {
2567 int ret = -EBADE;
2568 uint datalen, prec;
2569
2570 brcmf_dbg(TRACE, "Enter\n");
2571
2572 datalen = pkt->len;
2573
2574 /* Add space for the header */
2575 skb_push(pkt, SDPCM_HDRLEN);
2576 /* precondition: IS_ALIGNED((unsigned long)(pkt->data), 2) */
2577
2578 prec = prio2prec((pkt->priority & PRIOMASK));
2579
2580 /* Check for existing queue, current flow-control,
2581 pending event, or pending clock */
2582 brcmf_dbg(TRACE, "deferring pktq len %d\n", pktq_len(&bus->txq));
2583 bus->fcqueued++;
2584
2585 /* Priority based enq */
2586 spin_lock_bh(&bus->txqlock);
2587 if (brcmf_c_prec_enq(bus->drvr, &bus->txq, pkt, prec) == false) {
2588 skb_pull(pkt, SDPCM_HDRLEN);
2589 brcmf_txcomplete(bus->drvr, pkt, false);
2590 brcmu_pkt_buf_free_skb(pkt);
2591 brcmf_dbg(ERROR, "out of bus->txq !!!\n");
2592 ret = -ENOSR;
2593 } else {
2594 ret = 0;
2595 }
2596 spin_unlock_bh(&bus->txqlock);
2597
2598 if (pktq_len(&bus->txq) >= TXHI)
2599 brcmf_txflowcontrol(bus->drvr, 0, ON);
2600
2601 #ifdef BCMDBG
2602 if (pktq_plen(&bus->txq, prec) > qcount[prec])
2603 qcount[prec] = pktq_plen(&bus->txq, prec);
2604 #endif
2605 /* Schedule DPC if needed to send queued packet(s) */
2606 if (!bus->dpc_sched) {
2607 bus->dpc_sched = true;
2608 if (bus->dpc_tsk)
2609 complete(&bus->dpc_wait);
2610 }
2611
2612 return ret;
2613 }
2614
2615 static int
2616 brcmf_sdbrcm_membytes(struct brcmf_bus *bus, bool write, u32 address, u8 *data,
2617 uint size)
2618 {
2619 int bcmerror = 0;
2620 u32 sdaddr;
2621 uint dsize;
2622
2623 /* Determine initial transfer parameters */
2624 sdaddr = address & SBSDIO_SB_OFT_ADDR_MASK;
2625 if ((sdaddr + size) & SBSDIO_SBWINDOW_MASK)
2626 dsize = (SBSDIO_SB_OFT_ADDR_LIMIT - sdaddr);
2627 else
2628 dsize = size;
2629
2630 /* Set the backplane window to include the start address */
2631 bcmerror = brcmf_sdcard_set_sbaddr_window(bus->sdiodev, address);
2632 if (bcmerror) {
2633 brcmf_dbg(ERROR, "window change failed\n");
2634 goto xfer_done;
2635 }
2636
2637 /* Do the transfer(s) */
2638 while (size) {
2639 brcmf_dbg(INFO, "%s %d bytes at offset 0x%08x in window 0x%08x\n",
2640 write ? "write" : "read", dsize,
2641 sdaddr, address & SBSDIO_SBWINDOW_MASK);
2642 bcmerror = brcmf_sdcard_rwdata(bus->sdiodev, write,
2643 sdaddr, data, dsize);
2644 if (bcmerror) {
2645 brcmf_dbg(ERROR, "membytes transfer failed\n");
2646 break;
2647 }
2648
2649 /* Adjust for next transfer (if any) */
2650 size -= dsize;
2651 if (size) {
2652 data += dsize;
2653 address += dsize;
2654 bcmerror = brcmf_sdcard_set_sbaddr_window(bus->sdiodev,
2655 address);
2656 if (bcmerror) {
2657 brcmf_dbg(ERROR, "window change failed\n");
2658 break;
2659 }
2660 sdaddr = 0;
2661 dsize = min_t(uint, SBSDIO_SB_OFT_ADDR_LIMIT, size);
2662 }
2663 }
2664
2665 xfer_done:
2666 /* Return the window to backplane enumeration space for core access */
2667 if (brcmf_sdcard_set_sbaddr_window(bus->sdiodev, bus->sdiodev->sbwad))
2668 brcmf_dbg(ERROR, "FAILED to set window back to 0x%x\n",
2669 bus->sdiodev->sbwad);
2670
2671 return bcmerror;
2672 }
2673
2674 #ifdef BCMDBG
2675 #define CONSOLE_LINE_MAX 192
2676
2677 static int brcmf_sdbrcm_readconsole(struct brcmf_bus *bus)
2678 {
2679 struct brcmf_console *c = &bus->console;
2680 u8 line[CONSOLE_LINE_MAX], ch;
2681 u32 n, idx, addr;
2682 int rv;
2683
2684 /* Don't do anything until FWREADY updates console address */
2685 if (bus->console_addr == 0)
2686 return 0;
2687
2688 /* Read console log struct */
2689 addr = bus->console_addr + offsetof(struct rte_console, log_le);
2690 rv = brcmf_sdbrcm_membytes(bus, false, addr, (u8 *)&c->log_le,
2691 sizeof(c->log_le));
2692 if (rv < 0)
2693 return rv;
2694
2695 /* Allocate console buffer (one time only) */
2696 if (c->buf == NULL) {
2697 c->bufsize = le32_to_cpu(c->log_le.buf_size);
2698 c->buf = kmalloc(c->bufsize, GFP_ATOMIC);
2699 if (c->buf == NULL)
2700 return -ENOMEM;
2701 }
2702
2703 idx = le32_to_cpu(c->log_le.idx);
2704
2705 /* Protect against corrupt value */
2706 if (idx > c->bufsize)
2707 return -EBADE;
2708
2709 /* Skip reading the console buffer if the index pointer
2710 has not moved */
2711 if (idx == c->last)
2712 return 0;
2713
2714 /* Read the console buffer */
2715 addr = le32_to_cpu(c->log_le.buf);
2716 rv = brcmf_sdbrcm_membytes(bus, false, addr, c->buf, c->bufsize);
2717 if (rv < 0)
2718 return rv;
2719
2720 while (c->last != idx) {
2721 for (n = 0; n < CONSOLE_LINE_MAX - 2; n++) {
2722 if (c->last == idx) {
2723 /* This would output a partial line.
2724 * Instead, back up
2725 * the buffer pointer and output this
2726 * line next time around.
2727 */
2728 if (c->last >= n)
2729 c->last -= n;
2730 else
2731 c->last = c->bufsize - n;
2732 goto break2;
2733 }
2734 ch = c->buf[c->last];
2735 c->last = (c->last + 1) % c->bufsize;
2736 if (ch == '\n')
2737 break;
2738 line[n] = ch;
2739 }
2740
2741 if (n > 0) {
2742 if (line[n - 1] == '\r')
2743 n--;
2744 line[n] = 0;
2745 printk(KERN_DEBUG "CONSOLE: %s\n", line);
2746 }
2747 }
2748 break2:
2749
2750 return 0;
2751 }
2752 #endif /* BCMDBG */
2753
2754 static int brcmf_tx_frame(struct brcmf_bus *bus, u8 *frame, u16 len)
2755 {
2756 int i;
2757 int ret;
2758
2759 bus->ctrl_frame_stat = false;
2760 ret = brcmf_sdcard_send_buf(bus->sdiodev, bus->sdiodev->sbwad,
2761 SDIO_FUNC_2, F2SYNC, frame, len);
2762
2763 if (ret < 0) {
2764 /* On failure, abort the command and terminate the frame */
2765 brcmf_dbg(INFO, "sdio error %d, abort command and terminate frame\n",
2766 ret);
2767 bus->tx_sderrs++;
2768
2769 brcmf_sdcard_abort(bus->sdiodev, SDIO_FUNC_2);
2770
2771 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
2772 SBSDIO_FUNC1_FRAMECTRL,
2773 SFC_WF_TERM, NULL);
2774 bus->f1regdata++;
2775
2776 for (i = 0; i < 3; i++) {
2777 u8 hi, lo;
2778 hi = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
2779 SBSDIO_FUNC1_WFRAMEBCHI,
2780 NULL);
2781 lo = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
2782 SBSDIO_FUNC1_WFRAMEBCLO,
2783 NULL);
2784 bus->f1regdata += 2;
2785 if (hi == 0 && lo == 0)
2786 break;
2787 }
2788 return ret;
2789 }
2790
2791 bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
2792
2793 return ret;
2794 }
2795
2796 int
2797 brcmf_sdbrcm_bus_txctl(struct brcmf_bus *bus, unsigned char *msg, uint msglen)
2798 {
2799 u8 *frame;
2800 u16 len;
2801 u32 swheader;
2802 uint retries = 0;
2803 u8 doff = 0;
2804 int ret = -1;
2805
2806 brcmf_dbg(TRACE, "Enter\n");
2807
2808 /* Back the pointer to make a room for bus header */
2809 frame = msg - SDPCM_HDRLEN;
2810 len = (msglen += SDPCM_HDRLEN);
2811
2812 /* Add alignment padding (optional for ctl frames) */
2813 doff = ((unsigned long)frame % BRCMF_SDALIGN);
2814 if (doff) {
2815 frame -= doff;
2816 len += doff;
2817 msglen += doff;
2818 memset(frame, 0, doff + SDPCM_HDRLEN);
2819 }
2820 /* precondition: doff < BRCMF_SDALIGN */
2821 doff += SDPCM_HDRLEN;
2822
2823 /* Round send length to next SDIO block */
2824 if (bus->roundup && bus->blocksize && (len > bus->blocksize)) {
2825 u16 pad = bus->blocksize - (len % bus->blocksize);
2826 if ((pad <= bus->roundup) && (pad < bus->blocksize))
2827 len += pad;
2828 } else if (len % BRCMF_SDALIGN) {
2829 len += BRCMF_SDALIGN - (len % BRCMF_SDALIGN);
2830 }
2831
2832 /* Satisfy length-alignment requirements */
2833 if (len & (ALIGNMENT - 1))
2834 len = roundup(len, ALIGNMENT);
2835
2836 /* precondition: IS_ALIGNED((unsigned long)frame, 2) */
2837
2838 /* Need to lock here to protect txseq and SDIO tx calls */
2839 down(&bus->sdsem);
2840
2841 bus_wake(bus);
2842
2843 /* Make sure backplane clock is on */
2844 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
2845
2846 /* Hardware tag: 2 byte len followed by 2 byte ~len check (all LE) */
2847 *(__le16 *) frame = cpu_to_le16((u16) msglen);
2848 *(((__le16 *) frame) + 1) = cpu_to_le16(~msglen);
2849
2850 /* Software tag: channel, sequence number, data offset */
2851 swheader =
2852 ((SDPCM_CONTROL_CHANNEL << SDPCM_CHANNEL_SHIFT) &
2853 SDPCM_CHANNEL_MASK)
2854 | bus->tx_seq | ((doff << SDPCM_DOFFSET_SHIFT) &
2855 SDPCM_DOFFSET_MASK);
2856 put_unaligned_le32(swheader, frame + SDPCM_FRAMETAG_LEN);
2857 put_unaligned_le32(0, frame + SDPCM_FRAMETAG_LEN + sizeof(swheader));
2858
2859 if (!data_ok(bus)) {
2860 brcmf_dbg(INFO, "No bus credit bus->tx_max %d, bus->tx_seq %d\n",
2861 bus->tx_max, bus->tx_seq);
2862 bus->ctrl_frame_stat = true;
2863 /* Send from dpc */
2864 bus->ctrl_frame_buf = frame;
2865 bus->ctrl_frame_len = len;
2866
2867 brcmf_sdbrcm_wait_for_event(bus, &bus->ctrl_frame_stat);
2868
2869 if (bus->ctrl_frame_stat == false) {
2870 brcmf_dbg(INFO, "ctrl_frame_stat == false\n");
2871 ret = 0;
2872 } else {
2873 brcmf_dbg(INFO, "ctrl_frame_stat == true\n");
2874 ret = -1;
2875 }
2876 }
2877
2878 if (ret == -1) {
2879 #ifdef BCMDBG
2880 if (BRCMF_BYTES_ON() && BRCMF_CTL_ON()) {
2881 printk(KERN_DEBUG "Tx Frame:\n");
2882 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
2883 frame, len);
2884 } else if (BRCMF_HDRS_ON()) {
2885 printk(KERN_DEBUG "TxHdr:\n");
2886 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
2887 frame, min_t(u16, len, 16));
2888 }
2889 #endif
2890
2891 do {
2892 ret = brcmf_tx_frame(bus, frame, len);
2893 } while (ret < 0 && retries++ < TXRETRIES);
2894 }
2895
2896 if ((bus->idletime == BRCMF_IDLE_IMMEDIATE) && !bus->dpc_sched) {
2897 bus->activity = false;
2898 brcmf_sdbrcm_clkctl(bus, CLK_NONE, true);
2899 }
2900
2901 up(&bus->sdsem);
2902
2903 if (ret)
2904 bus->drvr->tx_ctlerrs++;
2905 else
2906 bus->drvr->tx_ctlpkts++;
2907
2908 return ret ? -EIO : 0;
2909 }
2910
2911 int
2912 brcmf_sdbrcm_bus_rxctl(struct brcmf_bus *bus, unsigned char *msg, uint msglen)
2913 {
2914 int timeleft;
2915 uint rxlen = 0;
2916 bool pending;
2917
2918 brcmf_dbg(TRACE, "Enter\n");
2919
2920 /* Wait until control frame is available */
2921 timeleft = brcmf_sdbrcm_dcmd_resp_wait(bus, &bus->rxlen, &pending);
2922
2923 down(&bus->sdsem);
2924 rxlen = bus->rxlen;
2925 memcpy(msg, bus->rxctl, min(msglen, rxlen));
2926 bus->rxlen = 0;
2927 up(&bus->sdsem);
2928
2929 if (rxlen) {
2930 brcmf_dbg(CTL, "resumed on rxctl frame, got %d expected %d\n",
2931 rxlen, msglen);
2932 } else if (timeleft == 0) {
2933 brcmf_dbg(ERROR, "resumed on timeout\n");
2934 } else if (pending == true) {
2935 brcmf_dbg(CTL, "cancelled\n");
2936 return -ERESTARTSYS;
2937 } else {
2938 brcmf_dbg(CTL, "resumed for unknown reason?\n");
2939 }
2940
2941 if (rxlen)
2942 bus->drvr->rx_ctlpkts++;
2943 else
2944 bus->drvr->rx_ctlerrs++;
2945
2946 return rxlen ? (int)rxlen : -ETIMEDOUT;
2947 }
2948
2949 static int brcmf_sdbrcm_downloadvars(struct brcmf_bus *bus, void *arg, int len)
2950 {
2951 int bcmerror = 0;
2952
2953 brcmf_dbg(TRACE, "Enter\n");
2954
2955 /* Basic sanity checks */
2956 if (bus->drvr->up) {
2957 bcmerror = -EISCONN;
2958 goto err;
2959 }
2960 if (!len) {
2961 bcmerror = -EOVERFLOW;
2962 goto err;
2963 }
2964
2965 /* Free the old ones and replace with passed variables */
2966 kfree(bus->vars);
2967
2968 bus->vars = kmalloc(len, GFP_ATOMIC);
2969 bus->varsz = bus->vars ? len : 0;
2970 if (bus->vars == NULL) {
2971 bcmerror = -ENOMEM;
2972 goto err;
2973 }
2974
2975 /* Copy the passed variables, which should include the
2976 terminating double-null */
2977 memcpy(bus->vars, arg, bus->varsz);
2978 err:
2979 return bcmerror;
2980 }
2981
2982 static int brcmf_sdbrcm_write_vars(struct brcmf_bus *bus)
2983 {
2984 int bcmerror = 0;
2985 u32 varsize;
2986 u32 varaddr;
2987 u8 *vbuffer;
2988 u32 varsizew;
2989 __le32 varsizew_le;
2990 #ifdef BCMDBG
2991 char *nvram_ularray;
2992 #endif /* BCMDBG */
2993
2994 /* Even if there are no vars are to be written, we still
2995 need to set the ramsize. */
2996 varsize = bus->varsz ? roundup(bus->varsz, 4) : 0;
2997 varaddr = (bus->ramsize - 4) - varsize;
2998
2999 if (bus->vars) {
3000 vbuffer = kzalloc(varsize, GFP_ATOMIC);
3001 if (!vbuffer)
3002 return -ENOMEM;
3003
3004 memcpy(vbuffer, bus->vars, bus->varsz);
3005
3006 /* Write the vars list */
3007 bcmerror =
3008 brcmf_sdbrcm_membytes(bus, true, varaddr, vbuffer, varsize);
3009 #ifdef BCMDBG
3010 /* Verify NVRAM bytes */
3011 brcmf_dbg(INFO, "Compare NVRAM dl & ul; varsize=%d\n", varsize);
3012 nvram_ularray = kmalloc(varsize, GFP_ATOMIC);
3013 if (!nvram_ularray)
3014 return -ENOMEM;
3015
3016 /* Upload image to verify downloaded contents. */
3017 memset(nvram_ularray, 0xaa, varsize);
3018
3019 /* Read the vars list to temp buffer for comparison */
3020 bcmerror =
3021 brcmf_sdbrcm_membytes(bus, false, varaddr, nvram_ularray,
3022 varsize);
3023 if (bcmerror) {
3024 brcmf_dbg(ERROR, "error %d on reading %d nvram bytes at 0x%08x\n",
3025 bcmerror, varsize, varaddr);
3026 }
3027 /* Compare the org NVRAM with the one read from RAM */
3028 if (memcmp(vbuffer, nvram_ularray, varsize))
3029 brcmf_dbg(ERROR, "Downloaded NVRAM image is corrupted\n");
3030 else
3031 brcmf_dbg(ERROR, "Download/Upload/Compare of NVRAM ok\n");
3032
3033 kfree(nvram_ularray);
3034 #endif /* BCMDBG */
3035
3036 kfree(vbuffer);
3037 }
3038
3039 /* adjust to the user specified RAM */
3040 brcmf_dbg(INFO, "Physical memory size: %d\n", bus->ramsize);
3041 brcmf_dbg(INFO, "Vars are at %d, orig varsize is %d\n",
3042 varaddr, varsize);
3043 varsize = ((bus->ramsize - 4) - varaddr);
3044
3045 /*
3046 * Determine the length token:
3047 * Varsize, converted to words, in lower 16-bits, checksum
3048 * in upper 16-bits.
3049 */
3050 if (bcmerror) {
3051 varsizew = 0;
3052 varsizew_le = cpu_to_le32(0);
3053 } else {
3054 varsizew = varsize / 4;
3055 varsizew = (~varsizew << 16) | (varsizew & 0x0000FFFF);
3056 varsizew_le = cpu_to_le32(varsizew);
3057 }
3058
3059 brcmf_dbg(INFO, "New varsize is %d, length token=0x%08x\n",
3060 varsize, varsizew);
3061
3062 /* Write the length token to the last word */
3063 bcmerror = brcmf_sdbrcm_membytes(bus, true, (bus->ramsize - 4),
3064 (u8 *)&varsizew_le, 4);
3065
3066 return bcmerror;
3067 }
3068
3069 static int brcmf_sdbrcm_download_state(struct brcmf_bus *bus, bool enter)
3070 {
3071 uint retries;
3072 int bcmerror = 0;
3073 struct chip_info *ci = bus->ci;
3074
3075 /* To enter download state, disable ARM and reset SOCRAM.
3076 * To exit download state, simply reset ARM (default is RAM boot).
3077 */
3078 if (enter) {
3079 bus->alp_only = true;
3080
3081 ci->coredisable(bus->sdiodev, ci, BCMA_CORE_ARM_CM3);
3082
3083 ci->resetcore(bus->sdiodev, ci, BCMA_CORE_INTERNAL_MEM);
3084
3085 /* Clear the top bit of memory */
3086 if (bus->ramsize) {
3087 u32 zeros = 0;
3088 brcmf_sdbrcm_membytes(bus, true, bus->ramsize - 4,
3089 (u8 *)&zeros, 4);
3090 }
3091 } else {
3092 if (!ci->iscoreup(bus->sdiodev, ci, BCMA_CORE_INTERNAL_MEM)) {
3093 brcmf_dbg(ERROR, "SOCRAM core is down after reset?\n");
3094 bcmerror = -EBADE;
3095 goto fail;
3096 }
3097
3098 bcmerror = brcmf_sdbrcm_write_vars(bus);
3099 if (bcmerror) {
3100 brcmf_dbg(ERROR, "no vars written to RAM\n");
3101 bcmerror = 0;
3102 }
3103
3104 w_sdreg32(bus, 0xFFFFFFFF,
3105 offsetof(struct sdpcmd_regs, intstatus), &retries);
3106
3107 ci->resetcore(bus->sdiodev, ci, BCMA_CORE_ARM_CM3);
3108
3109 /* Allow HT Clock now that the ARM is running. */
3110 bus->alp_only = false;
3111
3112 bus->drvr->busstate = BRCMF_BUS_LOAD;
3113 }
3114 fail:
3115 return bcmerror;
3116 }
3117
3118 static int brcmf_sdbrcm_get_image(char *buf, int len, struct brcmf_bus *bus)
3119 {
3120 if (bus->firmware->size < bus->fw_ptr + len)
3121 len = bus->firmware->size - bus->fw_ptr;
3122
3123 memcpy(buf, &bus->firmware->data[bus->fw_ptr], len);
3124 bus->fw_ptr += len;
3125 return len;
3126 }
3127
3128 MODULE_FIRMWARE(BCM4329_FW_NAME);
3129 MODULE_FIRMWARE(BCM4329_NV_NAME);
3130
3131 static int brcmf_sdbrcm_download_code_file(struct brcmf_bus *bus)
3132 {
3133 int offset = 0;
3134 uint len;
3135 u8 *memblock = NULL, *memptr;
3136 int ret;
3137
3138 brcmf_dbg(INFO, "Enter\n");
3139
3140 bus->fw_name = BCM4329_FW_NAME;
3141 ret = request_firmware(&bus->firmware, bus->fw_name,
3142 &bus->sdiodev->func[2]->dev);
3143 if (ret) {
3144 brcmf_dbg(ERROR, "Fail to request firmware %d\n", ret);
3145 return ret;
3146 }
3147 bus->fw_ptr = 0;
3148
3149 memptr = memblock = kmalloc(MEMBLOCK + BRCMF_SDALIGN, GFP_ATOMIC);
3150 if (memblock == NULL) {
3151 ret = -ENOMEM;
3152 goto err;
3153 }
3154 if ((u32)(unsigned long)memblock % BRCMF_SDALIGN)
3155 memptr += (BRCMF_SDALIGN -
3156 ((u32)(unsigned long)memblock % BRCMF_SDALIGN));
3157
3158 /* Download image */
3159 while ((len =
3160 brcmf_sdbrcm_get_image((char *)memptr, MEMBLOCK, bus))) {
3161 ret = brcmf_sdbrcm_membytes(bus, true, offset, memptr, len);
3162 if (ret) {
3163 brcmf_dbg(ERROR, "error %d on writing %d membytes at 0x%08x\n",
3164 ret, MEMBLOCK, offset);
3165 goto err;
3166 }
3167
3168 offset += MEMBLOCK;
3169 }
3170
3171 err:
3172 kfree(memblock);
3173
3174 release_firmware(bus->firmware);
3175 bus->fw_ptr = 0;
3176
3177 return ret;
3178 }
3179
3180 /*
3181 * ProcessVars:Takes a buffer of "<var>=<value>\n" lines read from a file
3182 * and ending in a NUL.
3183 * Removes carriage returns, empty lines, comment lines, and converts
3184 * newlines to NULs.
3185 * Shortens buffer as needed and pads with NULs. End of buffer is marked
3186 * by two NULs.
3187 */
3188
3189 static uint brcmf_process_nvram_vars(char *varbuf, uint len)
3190 {
3191 char *dp;
3192 bool findNewline;
3193 int column;
3194 uint buf_len, n;
3195
3196 dp = varbuf;
3197
3198 findNewline = false;
3199 column = 0;
3200
3201 for (n = 0; n < len; n++) {
3202 if (varbuf[n] == 0)
3203 break;
3204 if (varbuf[n] == '\r')
3205 continue;
3206 if (findNewline && varbuf[n] != '\n')
3207 continue;
3208 findNewline = false;
3209 if (varbuf[n] == '#') {
3210 findNewline = true;
3211 continue;
3212 }
3213 if (varbuf[n] == '\n') {
3214 if (column == 0)
3215 continue;
3216 *dp++ = 0;
3217 column = 0;
3218 continue;
3219 }
3220 *dp++ = varbuf[n];
3221 column++;
3222 }
3223 buf_len = dp - varbuf;
3224
3225 while (dp < varbuf + n)
3226 *dp++ = 0;
3227
3228 return buf_len;
3229 }
3230
3231 static int brcmf_sdbrcm_download_nvram(struct brcmf_bus *bus)
3232 {
3233 uint len;
3234 char *memblock = NULL;
3235 char *bufp;
3236 int ret;
3237
3238 bus->nv_name = BCM4329_NV_NAME;
3239 ret = request_firmware(&bus->firmware, bus->nv_name,
3240 &bus->sdiodev->func[2]->dev);
3241 if (ret) {
3242 brcmf_dbg(ERROR, "Fail to request nvram %d\n", ret);
3243 return ret;
3244 }
3245 bus->fw_ptr = 0;
3246
3247 memblock = kmalloc(MEMBLOCK, GFP_ATOMIC);
3248 if (memblock == NULL) {
3249 ret = -ENOMEM;
3250 goto err;
3251 }
3252
3253 len = brcmf_sdbrcm_get_image(memblock, MEMBLOCK, bus);
3254
3255 if (len > 0 && len < MEMBLOCK) {
3256 bufp = (char *)memblock;
3257 bufp[len] = 0;
3258 len = brcmf_process_nvram_vars(bufp, len);
3259 bufp += len;
3260 *bufp++ = 0;
3261 if (len)
3262 ret = brcmf_sdbrcm_downloadvars(bus, memblock, len + 1);
3263 if (ret)
3264 brcmf_dbg(ERROR, "error downloading vars: %d\n", ret);
3265 } else {
3266 brcmf_dbg(ERROR, "error reading nvram file: %d\n", len);
3267 ret = -EIO;
3268 }
3269
3270 err:
3271 kfree(memblock);
3272
3273 release_firmware(bus->firmware);
3274 bus->fw_ptr = 0;
3275
3276 return ret;
3277 }
3278
3279 static int _brcmf_sdbrcm_download_firmware(struct brcmf_bus *bus)
3280 {
3281 int bcmerror = -1;
3282
3283 /* Keep arm in reset */
3284 if (brcmf_sdbrcm_download_state(bus, true)) {
3285 brcmf_dbg(ERROR, "error placing ARM core in reset\n");
3286 goto err;
3287 }
3288
3289 /* External image takes precedence if specified */
3290 if (brcmf_sdbrcm_download_code_file(bus)) {
3291 brcmf_dbg(ERROR, "dongle image file download failed\n");
3292 goto err;
3293 }
3294
3295 /* External nvram takes precedence if specified */
3296 if (brcmf_sdbrcm_download_nvram(bus))
3297 brcmf_dbg(ERROR, "dongle nvram file download failed\n");
3298
3299 /* Take arm out of reset */
3300 if (brcmf_sdbrcm_download_state(bus, false)) {
3301 brcmf_dbg(ERROR, "error getting out of ARM core reset\n");
3302 goto err;
3303 }
3304
3305 bcmerror = 0;
3306
3307 err:
3308 return bcmerror;
3309 }
3310
3311 static bool
3312 brcmf_sdbrcm_download_firmware(struct brcmf_bus *bus)
3313 {
3314 bool ret;
3315
3316 /* Download the firmware */
3317 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
3318
3319 ret = _brcmf_sdbrcm_download_firmware(bus) == 0;
3320
3321 brcmf_sdbrcm_clkctl(bus, CLK_SDONLY, false);
3322
3323 return ret;
3324 }
3325
3326 void brcmf_sdbrcm_bus_stop(struct brcmf_bus *bus)
3327 {
3328 u32 local_hostintmask;
3329 u8 saveclk;
3330 uint retries;
3331 int err;
3332
3333 brcmf_dbg(TRACE, "Enter\n");
3334
3335 if (bus->watchdog_tsk) {
3336 send_sig(SIGTERM, bus->watchdog_tsk, 1);
3337 kthread_stop(bus->watchdog_tsk);
3338 bus->watchdog_tsk = NULL;
3339 }
3340
3341 if (bus->dpc_tsk && bus->dpc_tsk != current) {
3342 send_sig(SIGTERM, bus->dpc_tsk, 1);
3343 kthread_stop(bus->dpc_tsk);
3344 bus->dpc_tsk = NULL;
3345 }
3346
3347 down(&bus->sdsem);
3348
3349 bus_wake(bus);
3350
3351 /* Enable clock for device interrupts */
3352 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
3353
3354 /* Disable and clear interrupts at the chip level also */
3355 w_sdreg32(bus, 0, offsetof(struct sdpcmd_regs, hostintmask), &retries);
3356 local_hostintmask = bus->hostintmask;
3357 bus->hostintmask = 0;
3358
3359 /* Change our idea of bus state */
3360 bus->drvr->busstate = BRCMF_BUS_DOWN;
3361
3362 /* Force clocks on backplane to be sure F2 interrupt propagates */
3363 saveclk = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
3364 SBSDIO_FUNC1_CHIPCLKCSR, &err);
3365 if (!err) {
3366 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
3367 SBSDIO_FUNC1_CHIPCLKCSR,
3368 (saveclk | SBSDIO_FORCE_HT), &err);
3369 }
3370 if (err)
3371 brcmf_dbg(ERROR, "Failed to force clock for F2: err %d\n", err);
3372
3373 /* Turn off the bus (F2), free any pending packets */
3374 brcmf_dbg(INTR, "disable SDIO interrupts\n");
3375 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_0, SDIO_CCCR_IOEx,
3376 SDIO_FUNC_ENABLE_1, NULL);
3377
3378 /* Clear any pending interrupts now that F2 is disabled */
3379 w_sdreg32(bus, local_hostintmask,
3380 offsetof(struct sdpcmd_regs, intstatus), &retries);
3381
3382 /* Turn off the backplane clock (only) */
3383 brcmf_sdbrcm_clkctl(bus, CLK_SDONLY, false);
3384
3385 /* Clear the data packet queues */
3386 brcmu_pktq_flush(&bus->txq, true, NULL, NULL);
3387
3388 /* Clear any held glomming stuff */
3389 if (bus->glomd)
3390 brcmu_pkt_buf_free_skb(bus->glomd);
3391 brcmf_sdbrcm_free_glom(bus);
3392
3393 /* Clear rx control and wake any waiters */
3394 bus->rxlen = 0;
3395 brcmf_sdbrcm_dcmd_resp_wake(bus);
3396
3397 /* Reset some F2 state stuff */
3398 bus->rxskip = false;
3399 bus->tx_seq = bus->rx_seq = 0;
3400
3401 up(&bus->sdsem);
3402 }
3403
3404 int brcmf_sdbrcm_bus_init(struct brcmf_pub *drvr)
3405 {
3406 struct brcmf_bus *bus = drvr->bus;
3407 unsigned long timeout;
3408 uint retries = 0;
3409 u8 ready, enable;
3410 int err, ret = 0;
3411 u8 saveclk;
3412
3413 brcmf_dbg(TRACE, "Enter\n");
3414
3415 /* try to download image and nvram to the dongle */
3416 if (drvr->busstate == BRCMF_BUS_DOWN) {
3417 if (!(brcmf_sdbrcm_download_firmware(bus)))
3418 return -1;
3419 }
3420
3421 if (!bus->drvr)
3422 return 0;
3423
3424 /* Start the watchdog timer */
3425 bus->drvr->tickcnt = 0;
3426 brcmf_sdbrcm_wd_timer(bus, BRCMF_WD_POLL_MS);
3427
3428 down(&bus->sdsem);
3429
3430 /* Make sure backplane clock is on, needed to generate F2 interrupt */
3431 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
3432 if (bus->clkstate != CLK_AVAIL)
3433 goto exit;
3434
3435 /* Force clocks on backplane to be sure F2 interrupt propagates */
3436 saveclk =
3437 brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
3438 SBSDIO_FUNC1_CHIPCLKCSR, &err);
3439 if (!err) {
3440 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
3441 SBSDIO_FUNC1_CHIPCLKCSR,
3442 (saveclk | SBSDIO_FORCE_HT), &err);
3443 }
3444 if (err) {
3445 brcmf_dbg(ERROR, "Failed to force clock for F2: err %d\n", err);
3446 goto exit;
3447 }
3448
3449 /* Enable function 2 (frame transfers) */
3450 w_sdreg32(bus, SDPCM_PROT_VERSION << SMB_DATA_VERSION_SHIFT,
3451 offsetof(struct sdpcmd_regs, tosbmailboxdata), &retries);
3452 enable = (SDIO_FUNC_ENABLE_1 | SDIO_FUNC_ENABLE_2);
3453
3454 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_0, SDIO_CCCR_IOEx,
3455 enable, NULL);
3456
3457 timeout = jiffies + msecs_to_jiffies(BRCMF_WAIT_F2RDY);
3458 ready = 0;
3459 while (enable != ready) {
3460 ready = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_0,
3461 SDIO_CCCR_IORx, NULL);
3462 if (time_after(jiffies, timeout))
3463 break;
3464 else if (time_after(jiffies, timeout - BRCMF_WAIT_F2RDY + 50))
3465 /* prevent busy waiting if it takes too long */
3466 msleep_interruptible(20);
3467 }
3468
3469 brcmf_dbg(INFO, "enable 0x%02x, ready 0x%02x\n", enable, ready);
3470
3471 /* If F2 successfully enabled, set core and enable interrupts */
3472 if (ready == enable) {
3473 /* Set up the interrupt mask and enable interrupts */
3474 bus->hostintmask = HOSTINTMASK;
3475 w_sdreg32(bus, bus->hostintmask,
3476 offsetof(struct sdpcmd_regs, hostintmask), &retries);
3477
3478 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
3479 SBSDIO_WATERMARK, 8, &err);
3480
3481 /* Set bus state according to enable result */
3482 drvr->busstate = BRCMF_BUS_DATA;
3483 }
3484
3485 else {
3486 /* Disable F2 again */
3487 enable = SDIO_FUNC_ENABLE_1;
3488 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_0,
3489 SDIO_CCCR_IOEx, enable, NULL);
3490 }
3491
3492 /* Restore previous clock setting */
3493 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
3494 SBSDIO_FUNC1_CHIPCLKCSR, saveclk, &err);
3495
3496 /* If we didn't come up, turn off backplane clock */
3497 if (drvr->busstate != BRCMF_BUS_DATA)
3498 brcmf_sdbrcm_clkctl(bus, CLK_NONE, false);
3499
3500 exit:
3501 up(&bus->sdsem);
3502
3503 return ret;
3504 }
3505
3506 void brcmf_sdbrcm_isr(void *arg)
3507 {
3508 struct brcmf_bus *bus = (struct brcmf_bus *) arg;
3509
3510 brcmf_dbg(TRACE, "Enter\n");
3511
3512 if (!bus) {
3513 brcmf_dbg(ERROR, "bus is null pointer, exiting\n");
3514 return;
3515 }
3516
3517 if (bus->drvr->busstate == BRCMF_BUS_DOWN) {
3518 brcmf_dbg(ERROR, "bus is down. we have nothing to do\n");
3519 return;
3520 }
3521 /* Count the interrupt call */
3522 bus->intrcount++;
3523 bus->ipend = true;
3524
3525 /* Shouldn't get this interrupt if we're sleeping? */
3526 if (bus->sleeping) {
3527 brcmf_dbg(ERROR, "INTERRUPT WHILE SLEEPING??\n");
3528 return;
3529 }
3530
3531 /* Disable additional interrupts (is this needed now)? */
3532 if (!bus->intr)
3533 brcmf_dbg(ERROR, "isr w/o interrupt configured!\n");
3534
3535 bus->dpc_sched = true;
3536 if (bus->dpc_tsk)
3537 complete(&bus->dpc_wait);
3538 }
3539
3540 static bool brcmf_sdbrcm_bus_watchdog(struct brcmf_pub *drvr)
3541 {
3542 struct brcmf_bus *bus;
3543
3544 brcmf_dbg(TIMER, "Enter\n");
3545
3546 bus = drvr->bus;
3547
3548 /* Ignore the timer if simulating bus down */
3549 if (bus->sleeping)
3550 return false;
3551
3552 down(&bus->sdsem);
3553
3554 /* Poll period: check device if appropriate. */
3555 if (bus->poll && (++bus->polltick >= bus->pollrate)) {
3556 u32 intstatus = 0;
3557
3558 /* Reset poll tick */
3559 bus->polltick = 0;
3560
3561 /* Check device if no interrupts */
3562 if (!bus->intr || (bus->intrcount == bus->lastintrs)) {
3563
3564 if (!bus->dpc_sched) {
3565 u8 devpend;
3566 devpend = brcmf_sdcard_cfg_read(bus->sdiodev,
3567 SDIO_FUNC_0, SDIO_CCCR_INTx,
3568 NULL);
3569 intstatus =
3570 devpend & (INTR_STATUS_FUNC1 |
3571 INTR_STATUS_FUNC2);
3572 }
3573
3574 /* If there is something, make like the ISR and
3575 schedule the DPC */
3576 if (intstatus) {
3577 bus->pollcnt++;
3578 bus->ipend = true;
3579
3580 bus->dpc_sched = true;
3581 if (bus->dpc_tsk)
3582 complete(&bus->dpc_wait);
3583 }
3584 }
3585
3586 /* Update interrupt tracking */
3587 bus->lastintrs = bus->intrcount;
3588 }
3589 #ifdef BCMDBG
3590 /* Poll for console output periodically */
3591 if (drvr->busstate == BRCMF_BUS_DATA && bus->console_interval != 0) {
3592 bus->console.count += BRCMF_WD_POLL_MS;
3593 if (bus->console.count >= bus->console_interval) {
3594 bus->console.count -= bus->console_interval;
3595 /* Make sure backplane clock is on */
3596 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
3597 if (brcmf_sdbrcm_readconsole(bus) < 0)
3598 /* stop on error */
3599 bus->console_interval = 0;
3600 }
3601 }
3602 #endif /* BCMDBG */
3603
3604 /* On idle timeout clear activity flag and/or turn off clock */
3605 if ((bus->idletime > 0) && (bus->clkstate == CLK_AVAIL)) {
3606 if (++bus->idlecount >= bus->idletime) {
3607 bus->idlecount = 0;
3608 if (bus->activity) {
3609 bus->activity = false;
3610 brcmf_sdbrcm_wd_timer(bus, BRCMF_WD_POLL_MS);
3611 } else {
3612 brcmf_sdbrcm_clkctl(bus, CLK_NONE, false);
3613 }
3614 }
3615 }
3616
3617 up(&bus->sdsem);
3618
3619 return bus->ipend;
3620 }
3621
3622 static bool brcmf_sdbrcm_chipmatch(u16 chipid)
3623 {
3624 if (chipid == BCM4329_CHIP_ID)
3625 return true;
3626 return false;
3627 }
3628
3629 static void brcmf_sdbrcm_release_malloc(struct brcmf_bus *bus)
3630 {
3631 brcmf_dbg(TRACE, "Enter\n");
3632
3633 kfree(bus->rxbuf);
3634 bus->rxctl = bus->rxbuf = NULL;
3635 bus->rxlen = 0;
3636
3637 kfree(bus->databuf);
3638 bus->databuf = NULL;
3639 }
3640
3641 static bool brcmf_sdbrcm_probe_malloc(struct brcmf_bus *bus)
3642 {
3643 brcmf_dbg(TRACE, "Enter\n");
3644
3645 if (bus->drvr->maxctl) {
3646 bus->rxblen =
3647 roundup((bus->drvr->maxctl + SDPCM_HDRLEN),
3648 ALIGNMENT) + BRCMF_SDALIGN;
3649 bus->rxbuf = kmalloc(bus->rxblen, GFP_ATOMIC);
3650 if (!(bus->rxbuf))
3651 goto fail;
3652 }
3653
3654 /* Allocate buffer to receive glomed packet */
3655 bus->databuf = kmalloc(MAX_DATA_BUF, GFP_ATOMIC);
3656 if (!(bus->databuf)) {
3657 /* release rxbuf which was already located as above */
3658 if (!bus->rxblen)
3659 kfree(bus->rxbuf);
3660 goto fail;
3661 }
3662
3663 /* Align the buffer */
3664 if ((unsigned long)bus->databuf % BRCMF_SDALIGN)
3665 bus->dataptr = bus->databuf + (BRCMF_SDALIGN -
3666 ((unsigned long)bus->databuf % BRCMF_SDALIGN));
3667 else
3668 bus->dataptr = bus->databuf;
3669
3670 return true;
3671
3672 fail:
3673 return false;
3674 }
3675
3676 static bool
3677 brcmf_sdbrcm_probe_attach(struct brcmf_bus *bus, u32 regsva)
3678 {
3679 u8 clkctl = 0;
3680 int err = 0;
3681 int reg_addr;
3682 u32 reg_val;
3683 u8 idx;
3684
3685 bus->alp_only = true;
3686
3687 /* Return the window to backplane enumeration space for core access */
3688 if (brcmf_sdcard_set_sbaddr_window(bus->sdiodev, SI_ENUM_BASE))
3689 brcmf_dbg(ERROR, "FAILED to return to SI_ENUM_BASE\n");
3690
3691 #ifdef BCMDBG
3692 printk(KERN_DEBUG "F1 signature read @0x18000000=0x%4x\n",
3693 brcmf_sdcard_reg_read(bus->sdiodev, SI_ENUM_BASE, 4));
3694
3695 #endif /* BCMDBG */
3696
3697 /*
3698 * Force PLL off until brcmf_sdio_chip_attach()
3699 * programs PLL control regs
3700 */
3701
3702 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
3703 SBSDIO_FUNC1_CHIPCLKCSR,
3704 BRCMF_INIT_CLKCTL1, &err);
3705 if (!err)
3706 clkctl =
3707 brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
3708 SBSDIO_FUNC1_CHIPCLKCSR, &err);
3709
3710 if (err || ((clkctl & ~SBSDIO_AVBITS) != BRCMF_INIT_CLKCTL1)) {
3711 brcmf_dbg(ERROR, "ChipClkCSR access: err %d wrote 0x%02x read 0x%02x\n",
3712 err, BRCMF_INIT_CLKCTL1, clkctl);
3713 goto fail;
3714 }
3715
3716 if (brcmf_sdio_chip_attach(bus->sdiodev, &bus->ci, regsva)) {
3717 brcmf_dbg(ERROR, "brcmf_sdio_chip_attach failed!\n");
3718 goto fail;
3719 }
3720
3721 if (!brcmf_sdbrcm_chipmatch((u16) bus->ci->chip)) {
3722 brcmf_dbg(ERROR, "unsupported chip: 0x%04x\n", bus->ci->chip);
3723 goto fail;
3724 }
3725
3726 brcmf_sdio_chip_drivestrengthinit(bus->sdiodev, bus->ci,
3727 SDIO_DRIVE_STRENGTH);
3728
3729 /* Get info on the SOCRAM cores... */
3730 bus->ramsize = bus->ci->ramsize;
3731 if (!(bus->ramsize)) {
3732 brcmf_dbg(ERROR, "failed to find SOCRAM memory!\n");
3733 goto fail;
3734 }
3735
3736 /* Set core control so an SDIO reset does a backplane reset */
3737 idx = brcmf_sdio_chip_getinfidx(bus->ci, BCMA_CORE_SDIO_DEV);
3738 reg_addr = bus->ci->c_inf[idx].base +
3739 offsetof(struct sdpcmd_regs, corecontrol);
3740 reg_val = brcmf_sdcard_reg_read(bus->sdiodev, reg_addr, sizeof(u32));
3741 brcmf_sdcard_reg_write(bus->sdiodev, reg_addr, sizeof(u32),
3742 reg_val | CC_BPRESEN);
3743
3744 brcmu_pktq_init(&bus->txq, (PRIOMASK + 1), TXQLEN);
3745
3746 /* Locate an appropriately-aligned portion of hdrbuf */
3747 bus->rxhdr = (u8 *) roundup((unsigned long)&bus->hdrbuf[0],
3748 BRCMF_SDALIGN);
3749
3750 /* Set the poll and/or interrupt flags */
3751 bus->intr = true;
3752 bus->poll = false;
3753 if (bus->poll)
3754 bus->pollrate = 1;
3755
3756 return true;
3757
3758 fail:
3759 return false;
3760 }
3761
3762 static bool brcmf_sdbrcm_probe_init(struct brcmf_bus *bus)
3763 {
3764 brcmf_dbg(TRACE, "Enter\n");
3765
3766 /* Disable F2 to clear any intermediate frame state on the dongle */
3767 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_0, SDIO_CCCR_IOEx,
3768 SDIO_FUNC_ENABLE_1, NULL);
3769
3770 bus->drvr->busstate = BRCMF_BUS_DOWN;
3771 bus->sleeping = false;
3772 bus->rxflow = false;
3773
3774 /* Done with backplane-dependent accesses, can drop clock... */
3775 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
3776 SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL);
3777
3778 /* ...and initialize clock/power states */
3779 bus->clkstate = CLK_SDONLY;
3780 bus->idletime = BRCMF_IDLE_INTERVAL;
3781 bus->idleclock = BRCMF_IDLE_ACTIVE;
3782
3783 /* Query the F2 block size, set roundup accordingly */
3784 bus->blocksize = bus->sdiodev->func[2]->cur_blksize;
3785 bus->roundup = min(max_roundup, bus->blocksize);
3786
3787 /* bus module does not support packet chaining */
3788 bus->use_rxchain = false;
3789 bus->sd_rxchain = false;
3790
3791 return true;
3792 }
3793
3794 static int
3795 brcmf_sdbrcm_watchdog_thread(void *data)
3796 {
3797 struct brcmf_bus *bus = (struct brcmf_bus *)data;
3798
3799 allow_signal(SIGTERM);
3800 /* Run until signal received */
3801 while (1) {
3802 if (kthread_should_stop())
3803 break;
3804 if (!wait_for_completion_interruptible(&bus->watchdog_wait)) {
3805 brcmf_sdbrcm_bus_watchdog(bus->drvr);
3806 /* Count the tick for reference */
3807 bus->drvr->tickcnt++;
3808 } else
3809 break;
3810 }
3811 return 0;
3812 }
3813
3814 static void
3815 brcmf_sdbrcm_watchdog(unsigned long data)
3816 {
3817 struct brcmf_bus *bus = (struct brcmf_bus *)data;
3818
3819 if (bus->watchdog_tsk) {
3820 complete(&bus->watchdog_wait);
3821 /* Reschedule the watchdog */
3822 if (bus->wd_timer_valid)
3823 mod_timer(&bus->timer,
3824 jiffies + BRCMF_WD_POLL_MS * HZ / 1000);
3825 }
3826 }
3827
3828 static void brcmf_sdbrcm_release_dongle(struct brcmf_bus *bus)
3829 {
3830 brcmf_dbg(TRACE, "Enter\n");
3831
3832 if (bus->ci) {
3833 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
3834 brcmf_sdbrcm_clkctl(bus, CLK_NONE, false);
3835 brcmf_sdio_chip_detach(&bus->ci);
3836 if (bus->vars && bus->varsz)
3837 kfree(bus->vars);
3838 bus->vars = NULL;
3839 }
3840
3841 brcmf_dbg(TRACE, "Disconnected\n");
3842 }
3843
3844 /* Detach and free everything */
3845 static void brcmf_sdbrcm_release(struct brcmf_bus *bus)
3846 {
3847 brcmf_dbg(TRACE, "Enter\n");
3848
3849 if (bus) {
3850 /* De-register interrupt handler */
3851 brcmf_sdcard_intr_dereg(bus->sdiodev);
3852
3853 if (bus->drvr) {
3854 brcmf_detach(bus->drvr);
3855 brcmf_sdbrcm_release_dongle(bus);
3856 bus->drvr = NULL;
3857 }
3858
3859 brcmf_sdbrcm_release_malloc(bus);
3860
3861 kfree(bus);
3862 }
3863
3864 brcmf_dbg(TRACE, "Disconnected\n");
3865 }
3866
3867 void *brcmf_sdbrcm_probe(u16 bus_no, u16 slot, u16 func, uint bustype,
3868 u32 regsva, struct brcmf_sdio_dev *sdiodev)
3869 {
3870 int ret;
3871 struct brcmf_bus *bus;
3872
3873 /* Init global variables at run-time, not as part of the declaration.
3874 * This is required to support init/de-init of the driver.
3875 * Initialization
3876 * of globals as part of the declaration results in non-deterministic
3877 * behavior since the value of the globals may be different on the
3878 * first time that the driver is initialized vs subsequent
3879 * initializations.
3880 */
3881 brcmf_c_init();
3882
3883 brcmf_dbg(TRACE, "Enter\n");
3884
3885 /* We make an assumption about address window mappings:
3886 * regsva == SI_ENUM_BASE*/
3887
3888 /* Allocate private bus interface state */
3889 bus = kzalloc(sizeof(struct brcmf_bus), GFP_ATOMIC);
3890 if (!bus)
3891 goto fail;
3892
3893 bus->sdiodev = sdiodev;
3894 sdiodev->bus = bus;
3895 skb_queue_head_init(&bus->glom);
3896 bus->txbound = BRCMF_TXBOUND;
3897 bus->rxbound = BRCMF_RXBOUND;
3898 bus->txminmax = BRCMF_TXMINMAX;
3899 bus->tx_seq = SDPCM_SEQUENCE_WRAP - 1;
3900 bus->usebufpool = false; /* Use bufpool if allocated,
3901 else use locally malloced rxbuf */
3902
3903 /* attempt to attach to the dongle */
3904 if (!(brcmf_sdbrcm_probe_attach(bus, regsva))) {
3905 brcmf_dbg(ERROR, "brcmf_sdbrcm_probe_attach failed\n");
3906 goto fail;
3907 }
3908
3909 spin_lock_init(&bus->txqlock);
3910 init_waitqueue_head(&bus->ctrl_wait);
3911 init_waitqueue_head(&bus->dcmd_resp_wait);
3912
3913 /* Set up the watchdog timer */
3914 init_timer(&bus->timer);
3915 bus->timer.data = (unsigned long)bus;
3916 bus->timer.function = brcmf_sdbrcm_watchdog;
3917
3918 /* Initialize thread based operation and lock */
3919 sema_init(&bus->sdsem, 1);
3920
3921 /* Initialize watchdog thread */
3922 init_completion(&bus->watchdog_wait);
3923 bus->watchdog_tsk = kthread_run(brcmf_sdbrcm_watchdog_thread,
3924 bus, "brcmf_watchdog");
3925 if (IS_ERR(bus->watchdog_tsk)) {
3926 printk(KERN_WARNING
3927 "brcmf_watchdog thread failed to start\n");
3928 bus->watchdog_tsk = NULL;
3929 }
3930 /* Initialize DPC thread */
3931 init_completion(&bus->dpc_wait);
3932 bus->dpc_tsk = kthread_run(brcmf_sdbrcm_dpc_thread,
3933 bus, "brcmf_dpc");
3934 if (IS_ERR(bus->dpc_tsk)) {
3935 printk(KERN_WARNING
3936 "brcmf_dpc thread failed to start\n");
3937 bus->dpc_tsk = NULL;
3938 }
3939
3940 /* Attach to the brcmf/OS/network interface */
3941 bus->drvr = brcmf_attach(bus, SDPCM_RESERVE);
3942 if (!bus->drvr) {
3943 brcmf_dbg(ERROR, "brcmf_attach failed\n");
3944 goto fail;
3945 }
3946
3947 /* Allocate buffers */
3948 if (!(brcmf_sdbrcm_probe_malloc(bus))) {
3949 brcmf_dbg(ERROR, "brcmf_sdbrcm_probe_malloc failed\n");
3950 goto fail;
3951 }
3952
3953 if (!(brcmf_sdbrcm_probe_init(bus))) {
3954 brcmf_dbg(ERROR, "brcmf_sdbrcm_probe_init failed\n");
3955 goto fail;
3956 }
3957
3958 /* Register interrupt callback, but mask it (not operational yet). */
3959 brcmf_dbg(INTR, "disable SDIO interrupts (not interested yet)\n");
3960 ret = brcmf_sdcard_intr_reg(bus->sdiodev);
3961 if (ret != 0) {
3962 brcmf_dbg(ERROR, "FAILED: sdcard_intr_reg returned %d\n", ret);
3963 goto fail;
3964 }
3965 brcmf_dbg(INTR, "registered SDIO interrupt function ok\n");
3966
3967 brcmf_dbg(INFO, "completed!!\n");
3968
3969 /* if firmware path present try to download and bring up bus */
3970 ret = brcmf_bus_start(bus->drvr);
3971 if (ret != 0) {
3972 if (ret == -ENOLINK) {
3973 brcmf_dbg(ERROR, "dongle is not responding\n");
3974 goto fail;
3975 }
3976 }
3977
3978 /* add interface and open for business */
3979 if (brcmf_add_if((struct brcmf_info *)bus->drvr, 0, "wlan%d", NULL)) {
3980 brcmf_dbg(ERROR, "Add primary net device interface failed!!\n");
3981 goto fail;
3982 }
3983
3984 return bus;
3985
3986 fail:
3987 brcmf_sdbrcm_release(bus);
3988 return NULL;
3989 }
3990
3991 void brcmf_sdbrcm_disconnect(void *ptr)
3992 {
3993 struct brcmf_bus *bus = (struct brcmf_bus *)ptr;
3994
3995 brcmf_dbg(TRACE, "Enter\n");
3996
3997 if (bus)
3998 brcmf_sdbrcm_release(bus);
3999
4000 brcmf_dbg(TRACE, "Disconnected\n");
4001 }
4002
4003 struct device *brcmf_bus_get_device(struct brcmf_bus *bus)
4004 {
4005 return &bus->sdiodev->func[2]->dev;
4006 }
4007
4008 void
4009 brcmf_sdbrcm_wd_timer(struct brcmf_bus *bus, uint wdtick)
4010 {
4011 /* Totally stop the timer */
4012 if (!wdtick && bus->wd_timer_valid == true) {
4013 del_timer_sync(&bus->timer);
4014 bus->wd_timer_valid = false;
4015 bus->save_ms = wdtick;
4016 return;
4017 }
4018
4019 /* don't start the wd until fw is loaded */
4020 if (bus->drvr->busstate == BRCMF_BUS_DOWN)
4021 return;
4022
4023 if (wdtick) {
4024 if (bus->save_ms != BRCMF_WD_POLL_MS) {
4025 if (bus->wd_timer_valid == true)
4026 /* Stop timer and restart at new value */
4027 del_timer_sync(&bus->timer);
4028
4029 /* Create timer again when watchdog period is
4030 dynamically changed or in the first instance
4031 */
4032 bus->timer.expires =
4033 jiffies + BRCMF_WD_POLL_MS * HZ / 1000;
4034 add_timer(&bus->timer);
4035
4036 } else {
4037 /* Re arm the timer, at last watchdog period */
4038 mod_timer(&bus->timer,
4039 jiffies + BRCMF_WD_POLL_MS * HZ / 1000);
4040 }
4041
4042 bus->wd_timer_valid = true;
4043 bus->save_ms = wdtick;
4044 }
4045 }
Linux kernel - Deliverables
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