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brcmfmac: add host tx glomming support
[deliverable/linux.git] / drivers / net / wireless / brcm80211 / brcmfmac / dhd_sdio.c
1 /*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/types.h>
18 #include <linux/kernel.h>
19 #include <linux/kthread.h>
20 #include <linux/printk.h>
21 #include <linux/pci_ids.h>
22 #include <linux/netdevice.h>
23 #include <linux/interrupt.h>
24 #include <linux/sched.h>
25 #include <linux/mmc/sdio.h>
26 #include <linux/mmc/sdio_func.h>
27 #include <linux/mmc/card.h>
28 #include <linux/semaphore.h>
29 #include <linux/firmware.h>
30 #include <linux/module.h>
31 #include <linux/bcma/bcma.h>
32 #include <linux/debugfs.h>
33 #include <linux/vmalloc.h>
34 #include <linux/platform_data/brcmfmac-sdio.h>
35 #include <linux/moduleparam.h>
36 #include <asm/unaligned.h>
37 #include <defs.h>
38 #include <brcmu_wifi.h>
39 #include <brcmu_utils.h>
40 #include <brcm_hw_ids.h>
41 #include <soc.h>
42 #include "sdio_host.h"
43 #include "sdio_chip.h"
44
45 #define DCMD_RESP_TIMEOUT 2000 /* In milli second */
46
47 #ifdef DEBUG
48
49 #define BRCMF_TRAP_INFO_SIZE 80
50
51 #define CBUF_LEN (128)
52
53 /* Device console log buffer state */
54 #define CONSOLE_BUFFER_MAX 2024
55
56 struct rte_log_le {
57 __le32 buf; /* Can't be pointer on (64-bit) hosts */
58 __le32 buf_size;
59 __le32 idx;
60 char *_buf_compat; /* Redundant pointer for backward compat. */
61 };
62
63 struct rte_console {
64 /* Virtual UART
65 * When there is no UART (e.g. Quickturn),
66 * the host should write a complete
67 * input line directly into cbuf and then write
68 * the length into vcons_in.
69 * This may also be used when there is a real UART
70 * (at risk of conflicting with
71 * the real UART). vcons_out is currently unused.
72 */
73 uint vcons_in;
74 uint vcons_out;
75
76 /* Output (logging) buffer
77 * Console output is written to a ring buffer log_buf at index log_idx.
78 * The host may read the output when it sees log_idx advance.
79 * Output will be lost if the output wraps around faster than the host
80 * polls.
81 */
82 struct rte_log_le log_le;
83
84 /* Console input line buffer
85 * Characters are read one at a time into cbuf
86 * until <CR> is received, then
87 * the buffer is processed as a command line.
88 * Also used for virtual UART.
89 */
90 uint cbuf_idx;
91 char cbuf[CBUF_LEN];
92 };
93
94 #endif /* DEBUG */
95 #include <chipcommon.h>
96
97 #include "dhd_bus.h"
98 #include "dhd_dbg.h"
99 #include "tracepoint.h"
100
101 #define TXQLEN 2048 /* bulk tx queue length */
102 #define TXHI (TXQLEN - 256) /* turn on flow control above TXHI */
103 #define TXLOW (TXHI - 256) /* turn off flow control below TXLOW */
104 #define PRIOMASK 7
105
106 #define TXRETRIES 2 /* # of retries for tx frames */
107
108 #define BRCMF_RXBOUND 50 /* Default for max rx frames in
109 one scheduling */
110
111 #define BRCMF_TXBOUND 20 /* Default for max tx frames in
112 one scheduling */
113
114 #define BRCMF_DEFAULT_TXGLOM_SIZE 32 /* max tx frames in glom chain */
115
116 #define BRCMF_TXMINMAX 1 /* Max tx frames if rx still pending */
117
118 #define MEMBLOCK 2048 /* Block size used for downloading
119 of dongle image */
120 #define MAX_DATA_BUF (32 * 1024) /* Must be large enough to hold
121 biggest possible glom */
122
123 #define BRCMF_FIRSTREAD (1 << 6)
124
125
126 /* SBSDIO_DEVICE_CTL */
127
128 /* 1: device will assert busy signal when receiving CMD53 */
129 #define SBSDIO_DEVCTL_SETBUSY 0x01
130 /* 1: assertion of sdio interrupt is synchronous to the sdio clock */
131 #define SBSDIO_DEVCTL_SPI_INTR_SYNC 0x02
132 /* 1: mask all interrupts to host except the chipActive (rev 8) */
133 #define SBSDIO_DEVCTL_CA_INT_ONLY 0x04
134 /* 1: isolate internal sdio signals, put external pads in tri-state; requires
135 * sdio bus power cycle to clear (rev 9) */
136 #define SBSDIO_DEVCTL_PADS_ISO 0x08
137 /* Force SD->SB reset mapping (rev 11) */
138 #define SBSDIO_DEVCTL_SB_RST_CTL 0x30
139 /* Determined by CoreControl bit */
140 #define SBSDIO_DEVCTL_RST_CORECTL 0x00
141 /* Force backplane reset */
142 #define SBSDIO_DEVCTL_RST_BPRESET 0x10
143 /* Force no backplane reset */
144 #define SBSDIO_DEVCTL_RST_NOBPRESET 0x20
145
146 /* direct(mapped) cis space */
147
148 /* MAPPED common CIS address */
149 #define SBSDIO_CIS_BASE_COMMON 0x1000
150 /* maximum bytes in one CIS */
151 #define SBSDIO_CIS_SIZE_LIMIT 0x200
152 /* cis offset addr is < 17 bits */
153 #define SBSDIO_CIS_OFT_ADDR_MASK 0x1FFFF
154
155 /* manfid tuple length, include tuple, link bytes */
156 #define SBSDIO_CIS_MANFID_TUPLE_LEN 6
157
158 /* intstatus */
159 #define I_SMB_SW0 (1 << 0) /* To SB Mail S/W interrupt 0 */
160 #define I_SMB_SW1 (1 << 1) /* To SB Mail S/W interrupt 1 */
161 #define I_SMB_SW2 (1 << 2) /* To SB Mail S/W interrupt 2 */
162 #define I_SMB_SW3 (1 << 3) /* To SB Mail S/W interrupt 3 */
163 #define I_SMB_SW_MASK 0x0000000f /* To SB Mail S/W interrupts mask */
164 #define I_SMB_SW_SHIFT 0 /* To SB Mail S/W interrupts shift */
165 #define I_HMB_SW0 (1 << 4) /* To Host Mail S/W interrupt 0 */
166 #define I_HMB_SW1 (1 << 5) /* To Host Mail S/W interrupt 1 */
167 #define I_HMB_SW2 (1 << 6) /* To Host Mail S/W interrupt 2 */
168 #define I_HMB_SW3 (1 << 7) /* To Host Mail S/W interrupt 3 */
169 #define I_HMB_SW_MASK 0x000000f0 /* To Host Mail S/W interrupts mask */
170 #define I_HMB_SW_SHIFT 4 /* To Host Mail S/W interrupts shift */
171 #define I_WR_OOSYNC (1 << 8) /* Write Frame Out Of Sync */
172 #define I_RD_OOSYNC (1 << 9) /* Read Frame Out Of Sync */
173 #define I_PC (1 << 10) /* descriptor error */
174 #define I_PD (1 << 11) /* data error */
175 #define I_DE (1 << 12) /* Descriptor protocol Error */
176 #define I_RU (1 << 13) /* Receive descriptor Underflow */
177 #define I_RO (1 << 14) /* Receive fifo Overflow */
178 #define I_XU (1 << 15) /* Transmit fifo Underflow */
179 #define I_RI (1 << 16) /* Receive Interrupt */
180 #define I_BUSPWR (1 << 17) /* SDIO Bus Power Change (rev 9) */
181 #define I_XMTDATA_AVAIL (1 << 23) /* bits in fifo */
182 #define I_XI (1 << 24) /* Transmit Interrupt */
183 #define I_RF_TERM (1 << 25) /* Read Frame Terminate */
184 #define I_WF_TERM (1 << 26) /* Write Frame Terminate */
185 #define I_PCMCIA_XU (1 << 27) /* PCMCIA Transmit FIFO Underflow */
186 #define I_SBINT (1 << 28) /* sbintstatus Interrupt */
187 #define I_CHIPACTIVE (1 << 29) /* chip from doze to active state */
188 #define I_SRESET (1 << 30) /* CCCR RES interrupt */
189 #define I_IOE2 (1U << 31) /* CCCR IOE2 Bit Changed */
190 #define I_ERRORS (I_PC | I_PD | I_DE | I_RU | I_RO | I_XU)
191 #define I_DMA (I_RI | I_XI | I_ERRORS)
192
193 /* corecontrol */
194 #define CC_CISRDY (1 << 0) /* CIS Ready */
195 #define CC_BPRESEN (1 << 1) /* CCCR RES signal */
196 #define CC_F2RDY (1 << 2) /* set CCCR IOR2 bit */
197 #define CC_CLRPADSISO (1 << 3) /* clear SDIO pads isolation */
198 #define CC_XMTDATAAVAIL_MODE (1 << 4)
199 #define CC_XMTDATAAVAIL_CTRL (1 << 5)
200
201 /* SDA_FRAMECTRL */
202 #define SFC_RF_TERM (1 << 0) /* Read Frame Terminate */
203 #define SFC_WF_TERM (1 << 1) /* Write Frame Terminate */
204 #define SFC_CRC4WOOS (1 << 2) /* CRC error for write out of sync */
205 #define SFC_ABORTALL (1 << 3) /* Abort all in-progress frames */
206
207 /*
208 * Software allocation of To SB Mailbox resources
209 */
210
211 /* tosbmailbox bits corresponding to intstatus bits */
212 #define SMB_NAK (1 << 0) /* Frame NAK */
213 #define SMB_INT_ACK (1 << 1) /* Host Interrupt ACK */
214 #define SMB_USE_OOB (1 << 2) /* Use OOB Wakeup */
215 #define SMB_DEV_INT (1 << 3) /* Miscellaneous Interrupt */
216
217 /* tosbmailboxdata */
218 #define SMB_DATA_VERSION_SHIFT 16 /* host protocol version */
219
220 /*
221 * Software allocation of To Host Mailbox resources
222 */
223
224 /* intstatus bits */
225 #define I_HMB_FC_STATE I_HMB_SW0 /* Flow Control State */
226 #define I_HMB_FC_CHANGE I_HMB_SW1 /* Flow Control State Changed */
227 #define I_HMB_FRAME_IND I_HMB_SW2 /* Frame Indication */
228 #define I_HMB_HOST_INT I_HMB_SW3 /* Miscellaneous Interrupt */
229
230 /* tohostmailboxdata */
231 #define HMB_DATA_NAKHANDLED 1 /* retransmit NAK'd frame */
232 #define HMB_DATA_DEVREADY 2 /* talk to host after enable */
233 #define HMB_DATA_FC 4 /* per prio flowcontrol update flag */
234 #define HMB_DATA_FWREADY 8 /* fw ready for protocol activity */
235
236 #define HMB_DATA_FCDATA_MASK 0xff000000
237 #define HMB_DATA_FCDATA_SHIFT 24
238
239 #define HMB_DATA_VERSION_MASK 0x00ff0000
240 #define HMB_DATA_VERSION_SHIFT 16
241
242 /*
243 * Software-defined protocol header
244 */
245
246 /* Current protocol version */
247 #define SDPCM_PROT_VERSION 4
248
249 /*
250 * Shared structure between dongle and the host.
251 * The structure contains pointers to trap or assert information.
252 */
253 #define SDPCM_SHARED_VERSION 0x0003
254 #define SDPCM_SHARED_VERSION_MASK 0x00FF
255 #define SDPCM_SHARED_ASSERT_BUILT 0x0100
256 #define SDPCM_SHARED_ASSERT 0x0200
257 #define SDPCM_SHARED_TRAP 0x0400
258
259 /* Space for header read, limit for data packets */
260 #define MAX_HDR_READ (1 << 6)
261 #define MAX_RX_DATASZ 2048
262
263 /* Maximum milliseconds to wait for F2 to come up */
264 #define BRCMF_WAIT_F2RDY 3000
265
266 /* Bump up limit on waiting for HT to account for first startup;
267 * if the image is doing a CRC calculation before programming the PMU
268 * for HT availability, it could take a couple hundred ms more, so
269 * max out at a 1 second (1000000us).
270 */
271 #undef PMU_MAX_TRANSITION_DLY
272 #define PMU_MAX_TRANSITION_DLY 1000000
273
274 /* Value for ChipClockCSR during initial setup */
275 #define BRCMF_INIT_CLKCTL1 (SBSDIO_FORCE_HW_CLKREQ_OFF | \
276 SBSDIO_ALP_AVAIL_REQ)
277
278 /* Flags for SDH calls */
279 #define F2SYNC (SDIO_REQ_4BYTE | SDIO_REQ_FIXED)
280
281 #define BRCMF_IDLE_IMMEDIATE (-1) /* Enter idle immediately */
282 #define BRCMF_IDLE_ACTIVE 0 /* Do not request any SD clock change
283 * when idle
284 */
285 #define BRCMF_IDLE_INTERVAL 1
286
287 #define KSO_WAIT_US 50
288 #define MAX_KSO_ATTEMPTS (PMU_MAX_TRANSITION_DLY/KSO_WAIT_US)
289
290 /*
291 * Conversion of 802.1D priority to precedence level
292 */
293 static uint prio2prec(u32 prio)
294 {
295 return (prio == PRIO_8021D_NONE || prio == PRIO_8021D_BE) ?
296 (prio^2) : prio;
297 }
298
299 #ifdef DEBUG
300 /* Device console log buffer state */
301 struct brcmf_console {
302 uint count; /* Poll interval msec counter */
303 uint log_addr; /* Log struct address (fixed) */
304 struct rte_log_le log_le; /* Log struct (host copy) */
305 uint bufsize; /* Size of log buffer */
306 u8 *buf; /* Log buffer (host copy) */
307 uint last; /* Last buffer read index */
308 };
309
310 struct brcmf_trap_info {
311 __le32 type;
312 __le32 epc;
313 __le32 cpsr;
314 __le32 spsr;
315 __le32 r0; /* a1 */
316 __le32 r1; /* a2 */
317 __le32 r2; /* a3 */
318 __le32 r3; /* a4 */
319 __le32 r4; /* v1 */
320 __le32 r5; /* v2 */
321 __le32 r6; /* v3 */
322 __le32 r7; /* v4 */
323 __le32 r8; /* v5 */
324 __le32 r9; /* sb/v6 */
325 __le32 r10; /* sl/v7 */
326 __le32 r11; /* fp/v8 */
327 __le32 r12; /* ip */
328 __le32 r13; /* sp */
329 __le32 r14; /* lr */
330 __le32 pc; /* r15 */
331 };
332 #endif /* DEBUG */
333
334 struct sdpcm_shared {
335 u32 flags;
336 u32 trap_addr;
337 u32 assert_exp_addr;
338 u32 assert_file_addr;
339 u32 assert_line;
340 u32 console_addr; /* Address of struct rte_console */
341 u32 msgtrace_addr;
342 u8 tag[32];
343 u32 brpt_addr;
344 };
345
346 struct sdpcm_shared_le {
347 __le32 flags;
348 __le32 trap_addr;
349 __le32 assert_exp_addr;
350 __le32 assert_file_addr;
351 __le32 assert_line;
352 __le32 console_addr; /* Address of struct rte_console */
353 __le32 msgtrace_addr;
354 u8 tag[32];
355 __le32 brpt_addr;
356 };
357
358 /* dongle SDIO bus specific header info */
359 struct brcmf_sdio_hdrinfo {
360 u8 seq_num;
361 u8 channel;
362 u16 len;
363 u16 len_left;
364 u16 len_nxtfrm;
365 u8 dat_offset;
366 bool lastfrm;
367 u16 tail_pad;
368 };
369
370 /* misc chip info needed by some of the routines */
371 /* Private data for SDIO bus interaction */
372 struct brcmf_sdio {
373 struct brcmf_sdio_dev *sdiodev; /* sdio device handler */
374 struct chip_info *ci; /* Chip info struct */
375 char *vars; /* Variables (from CIS and/or other) */
376 uint varsz; /* Size of variables buffer */
377
378 u32 ramsize; /* Size of RAM in SOCRAM (bytes) */
379
380 u32 hostintmask; /* Copy of Host Interrupt Mask */
381 atomic_t intstatus; /* Intstatus bits (events) pending */
382 atomic_t fcstate; /* State of dongle flow-control */
383
384 uint blocksize; /* Block size of SDIO transfers */
385 uint roundup; /* Max roundup limit */
386
387 struct pktq txq; /* Queue length used for flow-control */
388 u8 flowcontrol; /* per prio flow control bitmask */
389 u8 tx_seq; /* Transmit sequence number (next) */
390 u8 tx_max; /* Maximum transmit sequence allowed */
391
392 u8 hdrbuf[MAX_HDR_READ + BRCMF_SDALIGN];
393 u8 *rxhdr; /* Header of current rx frame (in hdrbuf) */
394 u8 rx_seq; /* Receive sequence number (expected) */
395 struct brcmf_sdio_hdrinfo cur_read;
396 /* info of current read frame */
397 bool rxskip; /* Skip receive (awaiting NAK ACK) */
398 bool rxpending; /* Data frame pending in dongle */
399
400 uint rxbound; /* Rx frames to read before resched */
401 uint txbound; /* Tx frames to send before resched */
402 uint txminmax;
403
404 struct sk_buff *glomd; /* Packet containing glomming descriptor */
405 struct sk_buff_head glom; /* Packet list for glommed superframe */
406 uint glomerr; /* Glom packet read errors */
407
408 u8 *rxbuf; /* Buffer for receiving control packets */
409 uint rxblen; /* Allocated length of rxbuf */
410 u8 *rxctl; /* Aligned pointer into rxbuf */
411 u8 *rxctl_orig; /* pointer for freeing rxctl */
412 uint rxlen; /* Length of valid data in buffer */
413 spinlock_t rxctl_lock; /* protection lock for ctrl frame resources */
414
415 u8 sdpcm_ver; /* Bus protocol reported by dongle */
416
417 bool intr; /* Use interrupts */
418 bool poll; /* Use polling */
419 atomic_t ipend; /* Device interrupt is pending */
420 uint spurious; /* Count of spurious interrupts */
421 uint pollrate; /* Ticks between device polls */
422 uint polltick; /* Tick counter */
423
424 #ifdef DEBUG
425 uint console_interval;
426 struct brcmf_console console; /* Console output polling support */
427 uint console_addr; /* Console address from shared struct */
428 #endif /* DEBUG */
429
430 uint clkstate; /* State of sd and backplane clock(s) */
431 bool activity; /* Activity flag for clock down */
432 s32 idletime; /* Control for activity timeout */
433 s32 idlecount; /* Activity timeout counter */
434 s32 idleclock; /* How to set bus driver when idle */
435 bool rxflow_mode; /* Rx flow control mode */
436 bool rxflow; /* Is rx flow control on */
437 bool alp_only; /* Don't use HT clock (ALP only) */
438
439 u8 *ctrl_frame_buf;
440 u32 ctrl_frame_len;
441 bool ctrl_frame_stat;
442
443 spinlock_t txqlock;
444 wait_queue_head_t ctrl_wait;
445 wait_queue_head_t dcmd_resp_wait;
446
447 struct timer_list timer;
448 struct completion watchdog_wait;
449 struct task_struct *watchdog_tsk;
450 bool wd_timer_valid;
451 uint save_ms;
452
453 struct workqueue_struct *brcmf_wq;
454 struct work_struct datawork;
455 atomic_t dpc_tskcnt;
456
457 bool txoff; /* Transmit flow-controlled */
458 struct brcmf_sdio_count sdcnt;
459 bool sr_enabled; /* SaveRestore enabled */
460 bool sleeping; /* SDIO bus sleeping */
461
462 u8 tx_hdrlen; /* sdio bus header length for tx packet */
463 bool txglom; /* host tx glomming enable flag */
464 struct sk_buff *txglom_sgpad; /* scatter-gather padding buffer */
465 };
466
467 /* clkstate */
468 #define CLK_NONE 0
469 #define CLK_SDONLY 1
470 #define CLK_PENDING 2
471 #define CLK_AVAIL 3
472
473 #ifdef DEBUG
474 static int qcount[NUMPRIO];
475 #endif /* DEBUG */
476
477 #define DEFAULT_SDIO_DRIVE_STRENGTH 6 /* in milliamps */
478
479 #define RETRYCHAN(chan) ((chan) == SDPCM_EVENT_CHANNEL)
480
481 /* Retry count for register access failures */
482 static const uint retry_limit = 2;
483
484 /* Limit on rounding up frames */
485 static const uint max_roundup = 512;
486
487 #define ALIGNMENT 4
488
489 static int brcmf_sdio_txglomsz = BRCMF_DEFAULT_TXGLOM_SIZE;
490 module_param_named(txglomsz, brcmf_sdio_txglomsz, int, 0);
491 MODULE_PARM_DESC(txglomsz, "maximum tx packet chain size [SDIO]");
492
493 enum brcmf_sdio_frmtype {
494 BRCMF_SDIO_FT_NORMAL,
495 BRCMF_SDIO_FT_SUPER,
496 BRCMF_SDIO_FT_SUB,
497 };
498
499 #define BCM43143_FIRMWARE_NAME "brcm/brcmfmac43143-sdio.bin"
500 #define BCM43143_NVRAM_NAME "brcm/brcmfmac43143-sdio.txt"
501 #define BCM43241B0_FIRMWARE_NAME "brcm/brcmfmac43241b0-sdio.bin"
502 #define BCM43241B0_NVRAM_NAME "brcm/brcmfmac43241b0-sdio.txt"
503 #define BCM43241B4_FIRMWARE_NAME "brcm/brcmfmac43241b4-sdio.bin"
504 #define BCM43241B4_NVRAM_NAME "brcm/brcmfmac43241b4-sdio.txt"
505 #define BCM4329_FIRMWARE_NAME "brcm/brcmfmac4329-sdio.bin"
506 #define BCM4329_NVRAM_NAME "brcm/brcmfmac4329-sdio.txt"
507 #define BCM4330_FIRMWARE_NAME "brcm/brcmfmac4330-sdio.bin"
508 #define BCM4330_NVRAM_NAME "brcm/brcmfmac4330-sdio.txt"
509 #define BCM4334_FIRMWARE_NAME "brcm/brcmfmac4334-sdio.bin"
510 #define BCM4334_NVRAM_NAME "brcm/brcmfmac4334-sdio.txt"
511 #define BCM4335_FIRMWARE_NAME "brcm/brcmfmac4335-sdio.bin"
512 #define BCM4335_NVRAM_NAME "brcm/brcmfmac4335-sdio.txt"
513 #define BCM4339_FIRMWARE_NAME "brcm/brcmfmac4339-sdio.bin"
514 #define BCM4339_NVRAM_NAME "brcm/brcmfmac4339-sdio.txt"
515
516 MODULE_FIRMWARE(BCM43143_FIRMWARE_NAME);
517 MODULE_FIRMWARE(BCM43143_NVRAM_NAME);
518 MODULE_FIRMWARE(BCM43241B0_FIRMWARE_NAME);
519 MODULE_FIRMWARE(BCM43241B0_NVRAM_NAME);
520 MODULE_FIRMWARE(BCM43241B4_FIRMWARE_NAME);
521 MODULE_FIRMWARE(BCM43241B4_NVRAM_NAME);
522 MODULE_FIRMWARE(BCM4329_FIRMWARE_NAME);
523 MODULE_FIRMWARE(BCM4329_NVRAM_NAME);
524 MODULE_FIRMWARE(BCM4330_FIRMWARE_NAME);
525 MODULE_FIRMWARE(BCM4330_NVRAM_NAME);
526 MODULE_FIRMWARE(BCM4334_FIRMWARE_NAME);
527 MODULE_FIRMWARE(BCM4334_NVRAM_NAME);
528 MODULE_FIRMWARE(BCM4335_FIRMWARE_NAME);
529 MODULE_FIRMWARE(BCM4335_NVRAM_NAME);
530 MODULE_FIRMWARE(BCM4339_FIRMWARE_NAME);
531 MODULE_FIRMWARE(BCM4339_NVRAM_NAME);
532
533 struct brcmf_firmware_names {
534 u32 chipid;
535 u32 revmsk;
536 const char *bin;
537 const char *nv;
538 };
539
540 enum brcmf_firmware_type {
541 BRCMF_FIRMWARE_BIN,
542 BRCMF_FIRMWARE_NVRAM
543 };
544
545 #define BRCMF_FIRMWARE_NVRAM(name) \
546 name ## _FIRMWARE_NAME, name ## _NVRAM_NAME
547
548 static const struct brcmf_firmware_names brcmf_fwname_data[] = {
549 { BCM43143_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM43143) },
550 { BCM43241_CHIP_ID, 0x0000001F, BRCMF_FIRMWARE_NVRAM(BCM43241B0) },
551 { BCM43241_CHIP_ID, 0xFFFFFFE0, BRCMF_FIRMWARE_NVRAM(BCM43241B4) },
552 { BCM4329_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM4329) },
553 { BCM4330_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM4330) },
554 { BCM4334_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM4334) },
555 { BCM4335_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM4335) },
556 { BCM4339_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM4339) }
557 };
558
559
560 static const struct firmware *brcmf_sdbrcm_get_fw(struct brcmf_sdio *bus,
561 enum brcmf_firmware_type type)
562 {
563 const struct firmware *fw;
564 const char *name;
565 int err, i;
566
567 for (i = 0; i < ARRAY_SIZE(brcmf_fwname_data); i++) {
568 if (brcmf_fwname_data[i].chipid == bus->ci->chip &&
569 brcmf_fwname_data[i].revmsk & BIT(bus->ci->chiprev)) {
570 switch (type) {
571 case BRCMF_FIRMWARE_BIN:
572 name = brcmf_fwname_data[i].bin;
573 break;
574 case BRCMF_FIRMWARE_NVRAM:
575 name = brcmf_fwname_data[i].nv;
576 break;
577 default:
578 brcmf_err("invalid firmware type (%d)\n", type);
579 return NULL;
580 }
581 goto found;
582 }
583 }
584 brcmf_err("Unknown chipid %d [%d]\n",
585 bus->ci->chip, bus->ci->chiprev);
586 return NULL;
587
588 found:
589 err = request_firmware(&fw, name, &bus->sdiodev->func[2]->dev);
590 if ((err) || (!fw)) {
591 brcmf_err("fail to request firmware %s (%d)\n", name, err);
592 return NULL;
593 }
594
595 return fw;
596 }
597
598 static void pkt_align(struct sk_buff *p, int len, int align)
599 {
600 uint datalign;
601 datalign = (unsigned long)(p->data);
602 datalign = roundup(datalign, (align)) - datalign;
603 if (datalign)
604 skb_pull(p, datalign);
605 __skb_trim(p, len);
606 }
607
608 /* To check if there's window offered */
609 static bool data_ok(struct brcmf_sdio *bus)
610 {
611 return (u8)(bus->tx_max - bus->tx_seq) != 0 &&
612 ((u8)(bus->tx_max - bus->tx_seq) & 0x80) == 0;
613 }
614
615 /*
616 * Reads a register in the SDIO hardware block. This block occupies a series of
617 * adresses on the 32 bit backplane bus.
618 */
619 static int
620 r_sdreg32(struct brcmf_sdio *bus, u32 *regvar, u32 offset)
621 {
622 u8 idx = brcmf_sdio_chip_getinfidx(bus->ci, BCMA_CORE_SDIO_DEV);
623 int ret;
624
625 *regvar = brcmf_sdio_regrl(bus->sdiodev,
626 bus->ci->c_inf[idx].base + offset, &ret);
627
628 return ret;
629 }
630
631 static int
632 w_sdreg32(struct brcmf_sdio *bus, u32 regval, u32 reg_offset)
633 {
634 u8 idx = brcmf_sdio_chip_getinfidx(bus->ci, BCMA_CORE_SDIO_DEV);
635 int ret;
636
637 brcmf_sdio_regwl(bus->sdiodev,
638 bus->ci->c_inf[idx].base + reg_offset,
639 regval, &ret);
640
641 return ret;
642 }
643
644 static int
645 brcmf_sdbrcm_kso_control(struct brcmf_sdio *bus, bool on)
646 {
647 u8 wr_val = 0, rd_val, cmp_val, bmask;
648 int err = 0;
649 int try_cnt = 0;
650
651 brcmf_dbg(TRACE, "Enter\n");
652
653 wr_val = (on << SBSDIO_FUNC1_SLEEPCSR_KSO_SHIFT);
654 /* 1st KSO write goes to AOS wake up core if device is asleep */
655 brcmf_sdio_regwb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR,
656 wr_val, &err);
657 if (err) {
658 brcmf_err("SDIO_AOS KSO write error: %d\n", err);
659 return err;
660 }
661
662 if (on) {
663 /* device WAKEUP through KSO:
664 * write bit 0 & read back until
665 * both bits 0 (kso bit) & 1 (dev on status) are set
666 */
667 cmp_val = SBSDIO_FUNC1_SLEEPCSR_KSO_MASK |
668 SBSDIO_FUNC1_SLEEPCSR_DEVON_MASK;
669 bmask = cmp_val;
670 usleep_range(2000, 3000);
671 } else {
672 /* Put device to sleep, turn off KSO */
673 cmp_val = 0;
674 /* only check for bit0, bit1(dev on status) may not
675 * get cleared right away
676 */
677 bmask = SBSDIO_FUNC1_SLEEPCSR_KSO_MASK;
678 }
679
680 do {
681 /* reliable KSO bit set/clr:
682 * the sdiod sleep write access is synced to PMU 32khz clk
683 * just one write attempt may fail,
684 * read it back until it matches written value
685 */
686 rd_val = brcmf_sdio_regrb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR,
687 &err);
688 if (((rd_val & bmask) == cmp_val) && !err)
689 break;
690 brcmf_dbg(SDIO, "KSO wr/rd retry:%d (max: %d) ERR:%x\n",
691 try_cnt, MAX_KSO_ATTEMPTS, err);
692 udelay(KSO_WAIT_US);
693 brcmf_sdio_regwb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR,
694 wr_val, &err);
695 } while (try_cnt++ < MAX_KSO_ATTEMPTS);
696
697 return err;
698 }
699
700 #define PKT_AVAILABLE() (intstatus & I_HMB_FRAME_IND)
701
702 #define HOSTINTMASK (I_HMB_SW_MASK | I_CHIPACTIVE)
703
704 /* Turn backplane clock on or off */
705 static int brcmf_sdbrcm_htclk(struct brcmf_sdio *bus, bool on, bool pendok)
706 {
707 int err;
708 u8 clkctl, clkreq, devctl;
709 unsigned long timeout;
710
711 brcmf_dbg(SDIO, "Enter\n");
712
713 clkctl = 0;
714
715 if (bus->sr_enabled) {
716 bus->clkstate = (on ? CLK_AVAIL : CLK_SDONLY);
717 return 0;
718 }
719
720 if (on) {
721 /* Request HT Avail */
722 clkreq =
723 bus->alp_only ? SBSDIO_ALP_AVAIL_REQ : SBSDIO_HT_AVAIL_REQ;
724
725 brcmf_sdio_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
726 clkreq, &err);
727 if (err) {
728 brcmf_err("HT Avail request error: %d\n", err);
729 return -EBADE;
730 }
731
732 /* Check current status */
733 clkctl = brcmf_sdio_regrb(bus->sdiodev,
734 SBSDIO_FUNC1_CHIPCLKCSR, &err);
735 if (err) {
736 brcmf_err("HT Avail read error: %d\n", err);
737 return -EBADE;
738 }
739
740 /* Go to pending and await interrupt if appropriate */
741 if (!SBSDIO_CLKAV(clkctl, bus->alp_only) && pendok) {
742 /* Allow only clock-available interrupt */
743 devctl = brcmf_sdio_regrb(bus->sdiodev,
744 SBSDIO_DEVICE_CTL, &err);
745 if (err) {
746 brcmf_err("Devctl error setting CA: %d\n",
747 err);
748 return -EBADE;
749 }
750
751 devctl |= SBSDIO_DEVCTL_CA_INT_ONLY;
752 brcmf_sdio_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL,
753 devctl, &err);
754 brcmf_dbg(SDIO, "CLKCTL: set PENDING\n");
755 bus->clkstate = CLK_PENDING;
756
757 return 0;
758 } else if (bus->clkstate == CLK_PENDING) {
759 /* Cancel CA-only interrupt filter */
760 devctl = brcmf_sdio_regrb(bus->sdiodev,
761 SBSDIO_DEVICE_CTL, &err);
762 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
763 brcmf_sdio_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL,
764 devctl, &err);
765 }
766
767 /* Otherwise, wait here (polling) for HT Avail */
768 timeout = jiffies +
769 msecs_to_jiffies(PMU_MAX_TRANSITION_DLY/1000);
770 while (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
771 clkctl = brcmf_sdio_regrb(bus->sdiodev,
772 SBSDIO_FUNC1_CHIPCLKCSR,
773 &err);
774 if (time_after(jiffies, timeout))
775 break;
776 else
777 usleep_range(5000, 10000);
778 }
779 if (err) {
780 brcmf_err("HT Avail request error: %d\n", err);
781 return -EBADE;
782 }
783 if (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
784 brcmf_err("HT Avail timeout (%d): clkctl 0x%02x\n",
785 PMU_MAX_TRANSITION_DLY, clkctl);
786 return -EBADE;
787 }
788
789 /* Mark clock available */
790 bus->clkstate = CLK_AVAIL;
791 brcmf_dbg(SDIO, "CLKCTL: turned ON\n");
792
793 #if defined(DEBUG)
794 if (!bus->alp_only) {
795 if (SBSDIO_ALPONLY(clkctl))
796 brcmf_err("HT Clock should be on\n");
797 }
798 #endif /* defined (DEBUG) */
799
800 bus->activity = true;
801 } else {
802 clkreq = 0;
803
804 if (bus->clkstate == CLK_PENDING) {
805 /* Cancel CA-only interrupt filter */
806 devctl = brcmf_sdio_regrb(bus->sdiodev,
807 SBSDIO_DEVICE_CTL, &err);
808 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
809 brcmf_sdio_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL,
810 devctl, &err);
811 }
812
813 bus->clkstate = CLK_SDONLY;
814 brcmf_sdio_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
815 clkreq, &err);
816 brcmf_dbg(SDIO, "CLKCTL: turned OFF\n");
817 if (err) {
818 brcmf_err("Failed access turning clock off: %d\n",
819 err);
820 return -EBADE;
821 }
822 }
823 return 0;
824 }
825
826 /* Change idle/active SD state */
827 static int brcmf_sdbrcm_sdclk(struct brcmf_sdio *bus, bool on)
828 {
829 brcmf_dbg(SDIO, "Enter\n");
830
831 if (on)
832 bus->clkstate = CLK_SDONLY;
833 else
834 bus->clkstate = CLK_NONE;
835
836 return 0;
837 }
838
839 /* Transition SD and backplane clock readiness */
840 static int brcmf_sdbrcm_clkctl(struct brcmf_sdio *bus, uint target, bool pendok)
841 {
842 #ifdef DEBUG
843 uint oldstate = bus->clkstate;
844 #endif /* DEBUG */
845
846 brcmf_dbg(SDIO, "Enter\n");
847
848 /* Early exit if we're already there */
849 if (bus->clkstate == target) {
850 if (target == CLK_AVAIL) {
851 brcmf_sdbrcm_wd_timer(bus, BRCMF_WD_POLL_MS);
852 bus->activity = true;
853 }
854 return 0;
855 }
856
857 switch (target) {
858 case CLK_AVAIL:
859 /* Make sure SD clock is available */
860 if (bus->clkstate == CLK_NONE)
861 brcmf_sdbrcm_sdclk(bus, true);
862 /* Now request HT Avail on the backplane */
863 brcmf_sdbrcm_htclk(bus, true, pendok);
864 brcmf_sdbrcm_wd_timer(bus, BRCMF_WD_POLL_MS);
865 bus->activity = true;
866 break;
867
868 case CLK_SDONLY:
869 /* Remove HT request, or bring up SD clock */
870 if (bus->clkstate == CLK_NONE)
871 brcmf_sdbrcm_sdclk(bus, true);
872 else if (bus->clkstate == CLK_AVAIL)
873 brcmf_sdbrcm_htclk(bus, false, false);
874 else
875 brcmf_err("request for %d -> %d\n",
876 bus->clkstate, target);
877 brcmf_sdbrcm_wd_timer(bus, BRCMF_WD_POLL_MS);
878 break;
879
880 case CLK_NONE:
881 /* Make sure to remove HT request */
882 if (bus->clkstate == CLK_AVAIL)
883 brcmf_sdbrcm_htclk(bus, false, false);
884 /* Now remove the SD clock */
885 brcmf_sdbrcm_sdclk(bus, false);
886 brcmf_sdbrcm_wd_timer(bus, 0);
887 break;
888 }
889 #ifdef DEBUG
890 brcmf_dbg(SDIO, "%d -> %d\n", oldstate, bus->clkstate);
891 #endif /* DEBUG */
892
893 return 0;
894 }
895
896 static int
897 brcmf_sdbrcm_bus_sleep(struct brcmf_sdio *bus, bool sleep, bool pendok)
898 {
899 int err = 0;
900 brcmf_dbg(TRACE, "Enter\n");
901 brcmf_dbg(SDIO, "request %s currently %s\n",
902 (sleep ? "SLEEP" : "WAKE"),
903 (bus->sleeping ? "SLEEP" : "WAKE"));
904
905 /* If SR is enabled control bus state with KSO */
906 if (bus->sr_enabled) {
907 /* Done if we're already in the requested state */
908 if (sleep == bus->sleeping)
909 goto end;
910
911 /* Going to sleep */
912 if (sleep) {
913 /* Don't sleep if something is pending */
914 if (atomic_read(&bus->intstatus) ||
915 atomic_read(&bus->ipend) > 0 ||
916 (!atomic_read(&bus->fcstate) &&
917 brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol) &&
918 data_ok(bus)))
919 return -EBUSY;
920 err = brcmf_sdbrcm_kso_control(bus, false);
921 /* disable watchdog */
922 if (!err)
923 brcmf_sdbrcm_wd_timer(bus, 0);
924 } else {
925 bus->idlecount = 0;
926 err = brcmf_sdbrcm_kso_control(bus, true);
927 }
928 if (!err) {
929 /* Change state */
930 bus->sleeping = sleep;
931 brcmf_dbg(SDIO, "new state %s\n",
932 (sleep ? "SLEEP" : "WAKE"));
933 } else {
934 brcmf_err("error while changing bus sleep state %d\n",
935 err);
936 return err;
937 }
938 }
939
940 end:
941 /* control clocks */
942 if (sleep) {
943 if (!bus->sr_enabled)
944 brcmf_sdbrcm_clkctl(bus, CLK_NONE, pendok);
945 } else {
946 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, pendok);
947 }
948
949 return err;
950
951 }
952
953 static u32 brcmf_sdbrcm_hostmail(struct brcmf_sdio *bus)
954 {
955 u32 intstatus = 0;
956 u32 hmb_data;
957 u8 fcbits;
958 int ret;
959
960 brcmf_dbg(SDIO, "Enter\n");
961
962 /* Read mailbox data and ack that we did so */
963 ret = r_sdreg32(bus, &hmb_data,
964 offsetof(struct sdpcmd_regs, tohostmailboxdata));
965
966 if (ret == 0)
967 w_sdreg32(bus, SMB_INT_ACK,
968 offsetof(struct sdpcmd_regs, tosbmailbox));
969 bus->sdcnt.f1regdata += 2;
970
971 /* Dongle recomposed rx frames, accept them again */
972 if (hmb_data & HMB_DATA_NAKHANDLED) {
973 brcmf_dbg(SDIO, "Dongle reports NAK handled, expect rtx of %d\n",
974 bus->rx_seq);
975 if (!bus->rxskip)
976 brcmf_err("unexpected NAKHANDLED!\n");
977
978 bus->rxskip = false;
979 intstatus |= I_HMB_FRAME_IND;
980 }
981
982 /*
983 * DEVREADY does not occur with gSPI.
984 */
985 if (hmb_data & (HMB_DATA_DEVREADY | HMB_DATA_FWREADY)) {
986 bus->sdpcm_ver =
987 (hmb_data & HMB_DATA_VERSION_MASK) >>
988 HMB_DATA_VERSION_SHIFT;
989 if (bus->sdpcm_ver != SDPCM_PROT_VERSION)
990 brcmf_err("Version mismatch, dongle reports %d, "
991 "expecting %d\n",
992 bus->sdpcm_ver, SDPCM_PROT_VERSION);
993 else
994 brcmf_dbg(SDIO, "Dongle ready, protocol version %d\n",
995 bus->sdpcm_ver);
996 }
997
998 /*
999 * Flow Control has been moved into the RX headers and this out of band
1000 * method isn't used any more.
1001 * remaining backward compatible with older dongles.
1002 */
1003 if (hmb_data & HMB_DATA_FC) {
1004 fcbits = (hmb_data & HMB_DATA_FCDATA_MASK) >>
1005 HMB_DATA_FCDATA_SHIFT;
1006
1007 if (fcbits & ~bus->flowcontrol)
1008 bus->sdcnt.fc_xoff++;
1009
1010 if (bus->flowcontrol & ~fcbits)
1011 bus->sdcnt.fc_xon++;
1012
1013 bus->sdcnt.fc_rcvd++;
1014 bus->flowcontrol = fcbits;
1015 }
1016
1017 /* Shouldn't be any others */
1018 if (hmb_data & ~(HMB_DATA_DEVREADY |
1019 HMB_DATA_NAKHANDLED |
1020 HMB_DATA_FC |
1021 HMB_DATA_FWREADY |
1022 HMB_DATA_FCDATA_MASK | HMB_DATA_VERSION_MASK))
1023 brcmf_err("Unknown mailbox data content: 0x%02x\n",
1024 hmb_data);
1025
1026 return intstatus;
1027 }
1028
1029 static void brcmf_sdbrcm_rxfail(struct brcmf_sdio *bus, bool abort, bool rtx)
1030 {
1031 uint retries = 0;
1032 u16 lastrbc;
1033 u8 hi, lo;
1034 int err;
1035
1036 brcmf_err("%sterminate frame%s\n",
1037 abort ? "abort command, " : "",
1038 rtx ? ", send NAK" : "");
1039
1040 if (abort)
1041 brcmf_sdcard_abort(bus->sdiodev, SDIO_FUNC_2);
1042
1043 brcmf_sdio_regwb(bus->sdiodev, SBSDIO_FUNC1_FRAMECTRL,
1044 SFC_RF_TERM, &err);
1045 bus->sdcnt.f1regdata++;
1046
1047 /* Wait until the packet has been flushed (device/FIFO stable) */
1048 for (lastrbc = retries = 0xffff; retries > 0; retries--) {
1049 hi = brcmf_sdio_regrb(bus->sdiodev,
1050 SBSDIO_FUNC1_RFRAMEBCHI, &err);
1051 lo = brcmf_sdio_regrb(bus->sdiodev,
1052 SBSDIO_FUNC1_RFRAMEBCLO, &err);
1053 bus->sdcnt.f1regdata += 2;
1054
1055 if ((hi == 0) && (lo == 0))
1056 break;
1057
1058 if ((hi > (lastrbc >> 8)) && (lo > (lastrbc & 0x00ff))) {
1059 brcmf_err("count growing: last 0x%04x now 0x%04x\n",
1060 lastrbc, (hi << 8) + lo);
1061 }
1062 lastrbc = (hi << 8) + lo;
1063 }
1064
1065 if (!retries)
1066 brcmf_err("count never zeroed: last 0x%04x\n", lastrbc);
1067 else
1068 brcmf_dbg(SDIO, "flush took %d iterations\n", 0xffff - retries);
1069
1070 if (rtx) {
1071 bus->sdcnt.rxrtx++;
1072 err = w_sdreg32(bus, SMB_NAK,
1073 offsetof(struct sdpcmd_regs, tosbmailbox));
1074
1075 bus->sdcnt.f1regdata++;
1076 if (err == 0)
1077 bus->rxskip = true;
1078 }
1079
1080 /* Clear partial in any case */
1081 bus->cur_read.len = 0;
1082
1083 /* If we can't reach the device, signal failure */
1084 if (err)
1085 bus->sdiodev->bus_if->state = BRCMF_BUS_DOWN;
1086 }
1087
1088 /* return total length of buffer chain */
1089 static uint brcmf_sdbrcm_glom_len(struct brcmf_sdio *bus)
1090 {
1091 struct sk_buff *p;
1092 uint total;
1093
1094 total = 0;
1095 skb_queue_walk(&bus->glom, p)
1096 total += p->len;
1097 return total;
1098 }
1099
1100 static void brcmf_sdbrcm_free_glom(struct brcmf_sdio *bus)
1101 {
1102 struct sk_buff *cur, *next;
1103
1104 skb_queue_walk_safe(&bus->glom, cur, next) {
1105 skb_unlink(cur, &bus->glom);
1106 brcmu_pkt_buf_free_skb(cur);
1107 }
1108 }
1109
1110 /**
1111 * brcmfmac sdio bus specific header
1112 * This is the lowest layer header wrapped on the packets transmitted between
1113 * host and WiFi dongle which contains information needed for SDIO core and
1114 * firmware
1115 *
1116 * It consists of 3 parts: hardware header, hardware extension header and
1117 * software header
1118 * hardware header (frame tag) - 4 bytes
1119 * Byte 0~1: Frame length
1120 * Byte 2~3: Checksum, bit-wise inverse of frame length
1121 * hardware extension header - 8 bytes
1122 * Tx glom mode only, N/A for Rx or normal Tx
1123 * Byte 0~1: Packet length excluding hw frame tag
1124 * Byte 2: Reserved
1125 * Byte 3: Frame flags, bit 0: last frame indication
1126 * Byte 4~5: Reserved
1127 * Byte 6~7: Tail padding length
1128 * software header - 8 bytes
1129 * Byte 0: Rx/Tx sequence number
1130 * Byte 1: 4 MSB Channel number, 4 LSB arbitrary flag
1131 * Byte 2: Length of next data frame, reserved for Tx
1132 * Byte 3: Data offset
1133 * Byte 4: Flow control bits, reserved for Tx
1134 * Byte 5: Maximum Sequence number allowed by firmware for Tx, N/A for Tx packet
1135 * Byte 6~7: Reserved
1136 */
1137 #define SDPCM_HWHDR_LEN 4
1138 #define SDPCM_HWEXT_LEN 8
1139 #define SDPCM_SWHDR_LEN 8
1140 #define SDPCM_HDRLEN (SDPCM_HWHDR_LEN + SDPCM_SWHDR_LEN)
1141 /* software header */
1142 #define SDPCM_SEQ_MASK 0x000000ff
1143 #define SDPCM_SEQ_WRAP 256
1144 #define SDPCM_CHANNEL_MASK 0x00000f00
1145 #define SDPCM_CHANNEL_SHIFT 8
1146 #define SDPCM_CONTROL_CHANNEL 0 /* Control */
1147 #define SDPCM_EVENT_CHANNEL 1 /* Asyc Event Indication */
1148 #define SDPCM_DATA_CHANNEL 2 /* Data Xmit/Recv */
1149 #define SDPCM_GLOM_CHANNEL 3 /* Coalesced packets */
1150 #define SDPCM_TEST_CHANNEL 15 /* Test/debug packets */
1151 #define SDPCM_GLOMDESC(p) (((u8 *)p)[1] & 0x80)
1152 #define SDPCM_NEXTLEN_MASK 0x00ff0000
1153 #define SDPCM_NEXTLEN_SHIFT 16
1154 #define SDPCM_DOFFSET_MASK 0xff000000
1155 #define SDPCM_DOFFSET_SHIFT 24
1156 #define SDPCM_FCMASK_MASK 0x000000ff
1157 #define SDPCM_WINDOW_MASK 0x0000ff00
1158 #define SDPCM_WINDOW_SHIFT 8
1159
1160 static inline u8 brcmf_sdio_getdatoffset(u8 *swheader)
1161 {
1162 u32 hdrvalue;
1163 hdrvalue = *(u32 *)swheader;
1164 return (u8)((hdrvalue & SDPCM_DOFFSET_MASK) >> SDPCM_DOFFSET_SHIFT);
1165 }
1166
1167 static int brcmf_sdio_hdparse(struct brcmf_sdio *bus, u8 *header,
1168 struct brcmf_sdio_hdrinfo *rd,
1169 enum brcmf_sdio_frmtype type)
1170 {
1171 u16 len, checksum;
1172 u8 rx_seq, fc, tx_seq_max;
1173 u32 swheader;
1174
1175 trace_brcmf_sdpcm_hdr(SDPCM_RX, header);
1176
1177 /* hw header */
1178 len = get_unaligned_le16(header);
1179 checksum = get_unaligned_le16(header + sizeof(u16));
1180 /* All zero means no more to read */
1181 if (!(len | checksum)) {
1182 bus->rxpending = false;
1183 return -ENODATA;
1184 }
1185 if ((u16)(~(len ^ checksum))) {
1186 brcmf_err("HW header checksum error\n");
1187 bus->sdcnt.rx_badhdr++;
1188 brcmf_sdbrcm_rxfail(bus, false, false);
1189 return -EIO;
1190 }
1191 if (len < SDPCM_HDRLEN) {
1192 brcmf_err("HW header length error\n");
1193 return -EPROTO;
1194 }
1195 if (type == BRCMF_SDIO_FT_SUPER &&
1196 (roundup(len, bus->blocksize) != rd->len)) {
1197 brcmf_err("HW superframe header length error\n");
1198 return -EPROTO;
1199 }
1200 if (type == BRCMF_SDIO_FT_SUB && len > rd->len) {
1201 brcmf_err("HW subframe header length error\n");
1202 return -EPROTO;
1203 }
1204 rd->len = len;
1205
1206 /* software header */
1207 header += SDPCM_HWHDR_LEN;
1208 swheader = le32_to_cpu(*(__le32 *)header);
1209 if (type == BRCMF_SDIO_FT_SUPER && SDPCM_GLOMDESC(header)) {
1210 brcmf_err("Glom descriptor found in superframe head\n");
1211 rd->len = 0;
1212 return -EINVAL;
1213 }
1214 rx_seq = (u8)(swheader & SDPCM_SEQ_MASK);
1215 rd->channel = (swheader & SDPCM_CHANNEL_MASK) >> SDPCM_CHANNEL_SHIFT;
1216 if (len > MAX_RX_DATASZ && rd->channel != SDPCM_CONTROL_CHANNEL &&
1217 type != BRCMF_SDIO_FT_SUPER) {
1218 brcmf_err("HW header length too long\n");
1219 bus->sdcnt.rx_toolong++;
1220 brcmf_sdbrcm_rxfail(bus, false, false);
1221 rd->len = 0;
1222 return -EPROTO;
1223 }
1224 if (type == BRCMF_SDIO_FT_SUPER && rd->channel != SDPCM_GLOM_CHANNEL) {
1225 brcmf_err("Wrong channel for superframe\n");
1226 rd->len = 0;
1227 return -EINVAL;
1228 }
1229 if (type == BRCMF_SDIO_FT_SUB && rd->channel != SDPCM_DATA_CHANNEL &&
1230 rd->channel != SDPCM_EVENT_CHANNEL) {
1231 brcmf_err("Wrong channel for subframe\n");
1232 rd->len = 0;
1233 return -EINVAL;
1234 }
1235 rd->dat_offset = brcmf_sdio_getdatoffset(header);
1236 if (rd->dat_offset < SDPCM_HDRLEN || rd->dat_offset > rd->len) {
1237 brcmf_err("seq %d: bad data offset\n", rx_seq);
1238 bus->sdcnt.rx_badhdr++;
1239 brcmf_sdbrcm_rxfail(bus, false, false);
1240 rd->len = 0;
1241 return -ENXIO;
1242 }
1243 if (rd->seq_num != rx_seq) {
1244 brcmf_err("seq %d: sequence number error, expect %d\n",
1245 rx_seq, rd->seq_num);
1246 bus->sdcnt.rx_badseq++;
1247 rd->seq_num = rx_seq;
1248 }
1249 /* no need to check the reset for subframe */
1250 if (type == BRCMF_SDIO_FT_SUB)
1251 return 0;
1252 rd->len_nxtfrm = (swheader & SDPCM_NEXTLEN_MASK) >> SDPCM_NEXTLEN_SHIFT;
1253 if (rd->len_nxtfrm << 4 > MAX_RX_DATASZ) {
1254 /* only warm for NON glom packet */
1255 if (rd->channel != SDPCM_GLOM_CHANNEL)
1256 brcmf_err("seq %d: next length error\n", rx_seq);
1257 rd->len_nxtfrm = 0;
1258 }
1259 swheader = le32_to_cpu(*(__le32 *)(header + 4));
1260 fc = swheader & SDPCM_FCMASK_MASK;
1261 if (bus->flowcontrol != fc) {
1262 if (~bus->flowcontrol & fc)
1263 bus->sdcnt.fc_xoff++;
1264 if (bus->flowcontrol & ~fc)
1265 bus->sdcnt.fc_xon++;
1266 bus->sdcnt.fc_rcvd++;
1267 bus->flowcontrol = fc;
1268 }
1269 tx_seq_max = (swheader & SDPCM_WINDOW_MASK) >> SDPCM_WINDOW_SHIFT;
1270 if ((u8)(tx_seq_max - bus->tx_seq) > 0x40) {
1271 brcmf_err("seq %d: max tx seq number error\n", rx_seq);
1272 tx_seq_max = bus->tx_seq + 2;
1273 }
1274 bus->tx_max = tx_seq_max;
1275
1276 return 0;
1277 }
1278
1279 static inline void brcmf_sdio_update_hwhdr(u8 *header, u16 frm_length)
1280 {
1281 *(__le16 *)header = cpu_to_le16(frm_length);
1282 *(((__le16 *)header) + 1) = cpu_to_le16(~frm_length);
1283 }
1284
1285 static void brcmf_sdio_hdpack(struct brcmf_sdio *bus, u8 *header,
1286 struct brcmf_sdio_hdrinfo *hd_info)
1287 {
1288 u32 hdrval;
1289 u8 hdr_offset;
1290
1291 brcmf_sdio_update_hwhdr(header, hd_info->len);
1292 hdr_offset = SDPCM_HWHDR_LEN;
1293
1294 if (bus->txglom) {
1295 hdrval = (hd_info->len - hdr_offset) | (hd_info->lastfrm << 24);
1296 *((__le32 *)(header + hdr_offset)) = cpu_to_le32(hdrval);
1297 hdrval = (u16)hd_info->tail_pad << 16;
1298 *(((__le32 *)(header + hdr_offset)) + 1) = cpu_to_le32(hdrval);
1299 hdr_offset += SDPCM_HWEXT_LEN;
1300 }
1301
1302 hdrval = hd_info->seq_num;
1303 hdrval |= (hd_info->channel << SDPCM_CHANNEL_SHIFT) &
1304 SDPCM_CHANNEL_MASK;
1305 hdrval |= (hd_info->dat_offset << SDPCM_DOFFSET_SHIFT) &
1306 SDPCM_DOFFSET_MASK;
1307 *((__le32 *)(header + hdr_offset)) = cpu_to_le32(hdrval);
1308 *(((__le32 *)(header + hdr_offset)) + 1) = 0;
1309 trace_brcmf_sdpcm_hdr(SDPCM_TX + !!(bus->txglom), header);
1310 }
1311
1312 static u8 brcmf_sdbrcm_rxglom(struct brcmf_sdio *bus, u8 rxseq)
1313 {
1314 u16 dlen, totlen;
1315 u8 *dptr, num = 0;
1316 u32 align = 0;
1317 u16 sublen;
1318 struct sk_buff *pfirst, *pnext;
1319
1320 int errcode;
1321 u8 doff, sfdoff;
1322
1323 struct brcmf_sdio_hdrinfo rd_new;
1324
1325 /* If packets, issue read(s) and send up packet chain */
1326 /* Return sequence numbers consumed? */
1327
1328 brcmf_dbg(SDIO, "start: glomd %p glom %p\n",
1329 bus->glomd, skb_peek(&bus->glom));
1330
1331 if (bus->sdiodev->pdata)
1332 align = bus->sdiodev->pdata->sd_sgentry_align;
1333 if (align < 4)
1334 align = 4;
1335
1336 /* If there's a descriptor, generate the packet chain */
1337 if (bus->glomd) {
1338 pfirst = pnext = NULL;
1339 dlen = (u16) (bus->glomd->len);
1340 dptr = bus->glomd->data;
1341 if (!dlen || (dlen & 1)) {
1342 brcmf_err("bad glomd len(%d), ignore descriptor\n",
1343 dlen);
1344 dlen = 0;
1345 }
1346
1347 for (totlen = num = 0; dlen; num++) {
1348 /* Get (and move past) next length */
1349 sublen = get_unaligned_le16(dptr);
1350 dlen -= sizeof(u16);
1351 dptr += sizeof(u16);
1352 if ((sublen < SDPCM_HDRLEN) ||
1353 ((num == 0) && (sublen < (2 * SDPCM_HDRLEN)))) {
1354 brcmf_err("descriptor len %d bad: %d\n",
1355 num, sublen);
1356 pnext = NULL;
1357 break;
1358 }
1359 if (sublen % align) {
1360 brcmf_err("sublen %d not multiple of %d\n",
1361 sublen, align);
1362 }
1363 totlen += sublen;
1364
1365 /* For last frame, adjust read len so total
1366 is a block multiple */
1367 if (!dlen) {
1368 sublen +=
1369 (roundup(totlen, bus->blocksize) - totlen);
1370 totlen = roundup(totlen, bus->blocksize);
1371 }
1372
1373 /* Allocate/chain packet for next subframe */
1374 pnext = brcmu_pkt_buf_get_skb(sublen + align);
1375 if (pnext == NULL) {
1376 brcmf_err("bcm_pkt_buf_get_skb failed, num %d len %d\n",
1377 num, sublen);
1378 break;
1379 }
1380 skb_queue_tail(&bus->glom, pnext);
1381
1382 /* Adhere to start alignment requirements */
1383 pkt_align(pnext, sublen, align);
1384 }
1385
1386 /* If all allocations succeeded, save packet chain
1387 in bus structure */
1388 if (pnext) {
1389 brcmf_dbg(GLOM, "allocated %d-byte packet chain for %d subframes\n",
1390 totlen, num);
1391 if (BRCMF_GLOM_ON() && bus->cur_read.len &&
1392 totlen != bus->cur_read.len) {
1393 brcmf_dbg(GLOM, "glomdesc mismatch: nextlen %d glomdesc %d rxseq %d\n",
1394 bus->cur_read.len, totlen, rxseq);
1395 }
1396 pfirst = pnext = NULL;
1397 } else {
1398 brcmf_sdbrcm_free_glom(bus);
1399 num = 0;
1400 }
1401
1402 /* Done with descriptor packet */
1403 brcmu_pkt_buf_free_skb(bus->glomd);
1404 bus->glomd = NULL;
1405 bus->cur_read.len = 0;
1406 }
1407
1408 /* Ok -- either we just generated a packet chain,
1409 or had one from before */
1410 if (!skb_queue_empty(&bus->glom)) {
1411 if (BRCMF_GLOM_ON()) {
1412 brcmf_dbg(GLOM, "try superframe read, packet chain:\n");
1413 skb_queue_walk(&bus->glom, pnext) {
1414 brcmf_dbg(GLOM, " %p: %p len 0x%04x (%d)\n",
1415 pnext, (u8 *) (pnext->data),
1416 pnext->len, pnext->len);
1417 }
1418 }
1419
1420 pfirst = skb_peek(&bus->glom);
1421 dlen = (u16) brcmf_sdbrcm_glom_len(bus);
1422
1423 /* Do an SDIO read for the superframe. Configurable iovar to
1424 * read directly into the chained packet, or allocate a large
1425 * packet and and copy into the chain.
1426 */
1427 sdio_claim_host(bus->sdiodev->func[1]);
1428 errcode = brcmf_sdcard_recv_chain(bus->sdiodev,
1429 bus->sdiodev->sbwad,
1430 SDIO_FUNC_2, F2SYNC, &bus->glom, dlen);
1431 sdio_release_host(bus->sdiodev->func[1]);
1432 bus->sdcnt.f2rxdata++;
1433
1434 /* On failure, kill the superframe, allow a couple retries */
1435 if (errcode < 0) {
1436 brcmf_err("glom read of %d bytes failed: %d\n",
1437 dlen, errcode);
1438
1439 sdio_claim_host(bus->sdiodev->func[1]);
1440 if (bus->glomerr++ < 3) {
1441 brcmf_sdbrcm_rxfail(bus, true, true);
1442 } else {
1443 bus->glomerr = 0;
1444 brcmf_sdbrcm_rxfail(bus, true, false);
1445 bus->sdcnt.rxglomfail++;
1446 brcmf_sdbrcm_free_glom(bus);
1447 }
1448 sdio_release_host(bus->sdiodev->func[1]);
1449 return 0;
1450 }
1451
1452 brcmf_dbg_hex_dump(BRCMF_GLOM_ON(),
1453 pfirst->data, min_t(int, pfirst->len, 48),
1454 "SUPERFRAME:\n");
1455
1456 rd_new.seq_num = rxseq;
1457 rd_new.len = dlen;
1458 sdio_claim_host(bus->sdiodev->func[1]);
1459 errcode = brcmf_sdio_hdparse(bus, pfirst->data, &rd_new,
1460 BRCMF_SDIO_FT_SUPER);
1461 sdio_release_host(bus->sdiodev->func[1]);
1462 bus->cur_read.len = rd_new.len_nxtfrm << 4;
1463
1464 /* Remove superframe header, remember offset */
1465 skb_pull(pfirst, rd_new.dat_offset);
1466 sfdoff = rd_new.dat_offset;
1467 num = 0;
1468
1469 /* Validate all the subframe headers */
1470 skb_queue_walk(&bus->glom, pnext) {
1471 /* leave when invalid subframe is found */
1472 if (errcode)
1473 break;
1474
1475 rd_new.len = pnext->len;
1476 rd_new.seq_num = rxseq++;
1477 sdio_claim_host(bus->sdiodev->func[1]);
1478 errcode = brcmf_sdio_hdparse(bus, pnext->data, &rd_new,
1479 BRCMF_SDIO_FT_SUB);
1480 sdio_release_host(bus->sdiodev->func[1]);
1481 brcmf_dbg_hex_dump(BRCMF_GLOM_ON(),
1482 pnext->data, 32, "subframe:\n");
1483
1484 num++;
1485 }
1486
1487 if (errcode) {
1488 /* Terminate frame on error, request
1489 a couple retries */
1490 sdio_claim_host(bus->sdiodev->func[1]);
1491 if (bus->glomerr++ < 3) {
1492 /* Restore superframe header space */
1493 skb_push(pfirst, sfdoff);
1494 brcmf_sdbrcm_rxfail(bus, true, true);
1495 } else {
1496 bus->glomerr = 0;
1497 brcmf_sdbrcm_rxfail(bus, true, false);
1498 bus->sdcnt.rxglomfail++;
1499 brcmf_sdbrcm_free_glom(bus);
1500 }
1501 sdio_release_host(bus->sdiodev->func[1]);
1502 bus->cur_read.len = 0;
1503 return 0;
1504 }
1505
1506 /* Basic SD framing looks ok - process each packet (header) */
1507
1508 skb_queue_walk_safe(&bus->glom, pfirst, pnext) {
1509 dptr = (u8 *) (pfirst->data);
1510 sublen = get_unaligned_le16(dptr);
1511 doff = brcmf_sdio_getdatoffset(&dptr[SDPCM_HWHDR_LEN]);
1512
1513 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_DATA_ON(),
1514 dptr, pfirst->len,
1515 "Rx Subframe Data:\n");
1516
1517 __skb_trim(pfirst, sublen);
1518 skb_pull(pfirst, doff);
1519
1520 if (pfirst->len == 0) {
1521 skb_unlink(pfirst, &bus->glom);
1522 brcmu_pkt_buf_free_skb(pfirst);
1523 continue;
1524 }
1525
1526 brcmf_dbg_hex_dump(BRCMF_GLOM_ON(),
1527 pfirst->data,
1528 min_t(int, pfirst->len, 32),
1529 "subframe %d to stack, %p (%p/%d) nxt/lnk %p/%p\n",
1530 bus->glom.qlen, pfirst, pfirst->data,
1531 pfirst->len, pfirst->next,
1532 pfirst->prev);
1533 skb_unlink(pfirst, &bus->glom);
1534 brcmf_rx_frame(bus->sdiodev->dev, pfirst);
1535 bus->sdcnt.rxglompkts++;
1536 }
1537
1538 bus->sdcnt.rxglomframes++;
1539 }
1540 return num;
1541 }
1542
1543 static int brcmf_sdbrcm_dcmd_resp_wait(struct brcmf_sdio *bus, uint *condition,
1544 bool *pending)
1545 {
1546 DECLARE_WAITQUEUE(wait, current);
1547 int timeout = msecs_to_jiffies(DCMD_RESP_TIMEOUT);
1548
1549 /* Wait until control frame is available */
1550 add_wait_queue(&bus->dcmd_resp_wait, &wait);
1551 set_current_state(TASK_INTERRUPTIBLE);
1552
1553 while (!(*condition) && (!signal_pending(current) && timeout))
1554 timeout = schedule_timeout(timeout);
1555
1556 if (signal_pending(current))
1557 *pending = true;
1558
1559 set_current_state(TASK_RUNNING);
1560 remove_wait_queue(&bus->dcmd_resp_wait, &wait);
1561
1562 return timeout;
1563 }
1564
1565 static int brcmf_sdbrcm_dcmd_resp_wake(struct brcmf_sdio *bus)
1566 {
1567 if (waitqueue_active(&bus->dcmd_resp_wait))
1568 wake_up_interruptible(&bus->dcmd_resp_wait);
1569
1570 return 0;
1571 }
1572 static void
1573 brcmf_sdbrcm_read_control(struct brcmf_sdio *bus, u8 *hdr, uint len, uint doff)
1574 {
1575 uint rdlen, pad;
1576 u8 *buf = NULL, *rbuf;
1577 int sdret;
1578
1579 brcmf_dbg(TRACE, "Enter\n");
1580
1581 if (bus->rxblen)
1582 buf = vzalloc(bus->rxblen);
1583 if (!buf)
1584 goto done;
1585
1586 rbuf = bus->rxbuf;
1587 pad = ((unsigned long)rbuf % BRCMF_SDALIGN);
1588 if (pad)
1589 rbuf += (BRCMF_SDALIGN - pad);
1590
1591 /* Copy the already-read portion over */
1592 memcpy(buf, hdr, BRCMF_FIRSTREAD);
1593 if (len <= BRCMF_FIRSTREAD)
1594 goto gotpkt;
1595
1596 /* Raise rdlen to next SDIO block to avoid tail command */
1597 rdlen = len - BRCMF_FIRSTREAD;
1598 if (bus->roundup && bus->blocksize && (rdlen > bus->blocksize)) {
1599 pad = bus->blocksize - (rdlen % bus->blocksize);
1600 if ((pad <= bus->roundup) && (pad < bus->blocksize) &&
1601 ((len + pad) < bus->sdiodev->bus_if->maxctl))
1602 rdlen += pad;
1603 } else if (rdlen % BRCMF_SDALIGN) {
1604 rdlen += BRCMF_SDALIGN - (rdlen % BRCMF_SDALIGN);
1605 }
1606
1607 /* Satisfy length-alignment requirements */
1608 if (rdlen & (ALIGNMENT - 1))
1609 rdlen = roundup(rdlen, ALIGNMENT);
1610
1611 /* Drop if the read is too big or it exceeds our maximum */
1612 if ((rdlen + BRCMF_FIRSTREAD) > bus->sdiodev->bus_if->maxctl) {
1613 brcmf_err("%d-byte control read exceeds %d-byte buffer\n",
1614 rdlen, bus->sdiodev->bus_if->maxctl);
1615 brcmf_sdbrcm_rxfail(bus, false, false);
1616 goto done;
1617 }
1618
1619 if ((len - doff) > bus->sdiodev->bus_if->maxctl) {
1620 brcmf_err("%d-byte ctl frame (%d-byte ctl data) exceeds %d-byte limit\n",
1621 len, len - doff, bus->sdiodev->bus_if->maxctl);
1622 bus->sdcnt.rx_toolong++;
1623 brcmf_sdbrcm_rxfail(bus, false, false);
1624 goto done;
1625 }
1626
1627 /* Read remain of frame body */
1628 sdret = brcmf_sdcard_recv_buf(bus->sdiodev,
1629 bus->sdiodev->sbwad,
1630 SDIO_FUNC_2,
1631 F2SYNC, rbuf, rdlen);
1632 bus->sdcnt.f2rxdata++;
1633
1634 /* Control frame failures need retransmission */
1635 if (sdret < 0) {
1636 brcmf_err("read %d control bytes failed: %d\n",
1637 rdlen, sdret);
1638 bus->sdcnt.rxc_errors++;
1639 brcmf_sdbrcm_rxfail(bus, true, true);
1640 goto done;
1641 } else
1642 memcpy(buf + BRCMF_FIRSTREAD, rbuf, rdlen);
1643
1644 gotpkt:
1645
1646 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_CTL_ON(),
1647 buf, len, "RxCtrl:\n");
1648
1649 /* Point to valid data and indicate its length */
1650 spin_lock_bh(&bus->rxctl_lock);
1651 if (bus->rxctl) {
1652 brcmf_err("last control frame is being processed.\n");
1653 spin_unlock_bh(&bus->rxctl_lock);
1654 vfree(buf);
1655 goto done;
1656 }
1657 bus->rxctl = buf + doff;
1658 bus->rxctl_orig = buf;
1659 bus->rxlen = len - doff;
1660 spin_unlock_bh(&bus->rxctl_lock);
1661
1662 done:
1663 /* Awake any waiters */
1664 brcmf_sdbrcm_dcmd_resp_wake(bus);
1665 }
1666
1667 /* Pad read to blocksize for efficiency */
1668 static void brcmf_pad(struct brcmf_sdio *bus, u16 *pad, u16 *rdlen)
1669 {
1670 if (bus->roundup && bus->blocksize && *rdlen > bus->blocksize) {
1671 *pad = bus->blocksize - (*rdlen % bus->blocksize);
1672 if (*pad <= bus->roundup && *pad < bus->blocksize &&
1673 *rdlen + *pad + BRCMF_FIRSTREAD < MAX_RX_DATASZ)
1674 *rdlen += *pad;
1675 } else if (*rdlen % BRCMF_SDALIGN) {
1676 *rdlen += BRCMF_SDALIGN - (*rdlen % BRCMF_SDALIGN);
1677 }
1678 }
1679
1680 static uint brcmf_sdio_readframes(struct brcmf_sdio *bus, uint maxframes)
1681 {
1682 struct sk_buff *pkt; /* Packet for event or data frames */
1683 u16 pad; /* Number of pad bytes to read */
1684 uint rxleft = 0; /* Remaining number of frames allowed */
1685 int ret; /* Return code from calls */
1686 uint rxcount = 0; /* Total frames read */
1687 struct brcmf_sdio_hdrinfo *rd = &bus->cur_read, rd_new;
1688 u8 head_read = 0;
1689
1690 brcmf_dbg(TRACE, "Enter\n");
1691
1692 /* Not finished unless we encounter no more frames indication */
1693 bus->rxpending = true;
1694
1695 for (rd->seq_num = bus->rx_seq, rxleft = maxframes;
1696 !bus->rxskip && rxleft &&
1697 bus->sdiodev->bus_if->state != BRCMF_BUS_DOWN;
1698 rd->seq_num++, rxleft--) {
1699
1700 /* Handle glomming separately */
1701 if (bus->glomd || !skb_queue_empty(&bus->glom)) {
1702 u8 cnt;
1703 brcmf_dbg(GLOM, "calling rxglom: glomd %p, glom %p\n",
1704 bus->glomd, skb_peek(&bus->glom));
1705 cnt = brcmf_sdbrcm_rxglom(bus, rd->seq_num);
1706 brcmf_dbg(GLOM, "rxglom returned %d\n", cnt);
1707 rd->seq_num += cnt - 1;
1708 rxleft = (rxleft > cnt) ? (rxleft - cnt) : 1;
1709 continue;
1710 }
1711
1712 rd->len_left = rd->len;
1713 /* read header first for unknow frame length */
1714 sdio_claim_host(bus->sdiodev->func[1]);
1715 if (!rd->len) {
1716 ret = brcmf_sdcard_recv_buf(bus->sdiodev,
1717 bus->sdiodev->sbwad,
1718 SDIO_FUNC_2, F2SYNC,
1719 bus->rxhdr,
1720 BRCMF_FIRSTREAD);
1721 bus->sdcnt.f2rxhdrs++;
1722 if (ret < 0) {
1723 brcmf_err("RXHEADER FAILED: %d\n",
1724 ret);
1725 bus->sdcnt.rx_hdrfail++;
1726 brcmf_sdbrcm_rxfail(bus, true, true);
1727 sdio_release_host(bus->sdiodev->func[1]);
1728 continue;
1729 }
1730
1731 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() || BRCMF_HDRS_ON(),
1732 bus->rxhdr, SDPCM_HDRLEN,
1733 "RxHdr:\n");
1734
1735 if (brcmf_sdio_hdparse(bus, bus->rxhdr, rd,
1736 BRCMF_SDIO_FT_NORMAL)) {
1737 sdio_release_host(bus->sdiodev->func[1]);
1738 if (!bus->rxpending)
1739 break;
1740 else
1741 continue;
1742 }
1743
1744 if (rd->channel == SDPCM_CONTROL_CHANNEL) {
1745 brcmf_sdbrcm_read_control(bus, bus->rxhdr,
1746 rd->len,
1747 rd->dat_offset);
1748 /* prepare the descriptor for the next read */
1749 rd->len = rd->len_nxtfrm << 4;
1750 rd->len_nxtfrm = 0;
1751 /* treat all packet as event if we don't know */
1752 rd->channel = SDPCM_EVENT_CHANNEL;
1753 sdio_release_host(bus->sdiodev->func[1]);
1754 continue;
1755 }
1756 rd->len_left = rd->len > BRCMF_FIRSTREAD ?
1757 rd->len - BRCMF_FIRSTREAD : 0;
1758 head_read = BRCMF_FIRSTREAD;
1759 }
1760
1761 brcmf_pad(bus, &pad, &rd->len_left);
1762
1763 pkt = brcmu_pkt_buf_get_skb(rd->len_left + head_read +
1764 BRCMF_SDALIGN);
1765 if (!pkt) {
1766 /* Give up on data, request rtx of events */
1767 brcmf_err("brcmu_pkt_buf_get_skb failed\n");
1768 brcmf_sdbrcm_rxfail(bus, false,
1769 RETRYCHAN(rd->channel));
1770 sdio_release_host(bus->sdiodev->func[1]);
1771 continue;
1772 }
1773 skb_pull(pkt, head_read);
1774 pkt_align(pkt, rd->len_left, BRCMF_SDALIGN);
1775
1776 ret = brcmf_sdcard_recv_pkt(bus->sdiodev, bus->sdiodev->sbwad,
1777 SDIO_FUNC_2, F2SYNC, pkt);
1778 bus->sdcnt.f2rxdata++;
1779 sdio_release_host(bus->sdiodev->func[1]);
1780
1781 if (ret < 0) {
1782 brcmf_err("read %d bytes from channel %d failed: %d\n",
1783 rd->len, rd->channel, ret);
1784 brcmu_pkt_buf_free_skb(pkt);
1785 sdio_claim_host(bus->sdiodev->func[1]);
1786 brcmf_sdbrcm_rxfail(bus, true,
1787 RETRYCHAN(rd->channel));
1788 sdio_release_host(bus->sdiodev->func[1]);
1789 continue;
1790 }
1791
1792 if (head_read) {
1793 skb_push(pkt, head_read);
1794 memcpy(pkt->data, bus->rxhdr, head_read);
1795 head_read = 0;
1796 } else {
1797 memcpy(bus->rxhdr, pkt->data, SDPCM_HDRLEN);
1798 rd_new.seq_num = rd->seq_num;
1799 sdio_claim_host(bus->sdiodev->func[1]);
1800 if (brcmf_sdio_hdparse(bus, bus->rxhdr, &rd_new,
1801 BRCMF_SDIO_FT_NORMAL)) {
1802 rd->len = 0;
1803 brcmu_pkt_buf_free_skb(pkt);
1804 }
1805 bus->sdcnt.rx_readahead_cnt++;
1806 if (rd->len != roundup(rd_new.len, 16)) {
1807 brcmf_err("frame length mismatch:read %d, should be %d\n",
1808 rd->len,
1809 roundup(rd_new.len, 16) >> 4);
1810 rd->len = 0;
1811 brcmf_sdbrcm_rxfail(bus, true, true);
1812 sdio_release_host(bus->sdiodev->func[1]);
1813 brcmu_pkt_buf_free_skb(pkt);
1814 continue;
1815 }
1816 sdio_release_host(bus->sdiodev->func[1]);
1817 rd->len_nxtfrm = rd_new.len_nxtfrm;
1818 rd->channel = rd_new.channel;
1819 rd->dat_offset = rd_new.dat_offset;
1820
1821 brcmf_dbg_hex_dump(!(BRCMF_BYTES_ON() &&
1822 BRCMF_DATA_ON()) &&
1823 BRCMF_HDRS_ON(),
1824 bus->rxhdr, SDPCM_HDRLEN,
1825 "RxHdr:\n");
1826
1827 if (rd_new.channel == SDPCM_CONTROL_CHANNEL) {
1828 brcmf_err("readahead on control packet %d?\n",
1829 rd_new.seq_num);
1830 /* Force retry w/normal header read */
1831 rd->len = 0;
1832 sdio_claim_host(bus->sdiodev->func[1]);
1833 brcmf_sdbrcm_rxfail(bus, false, true);
1834 sdio_release_host(bus->sdiodev->func[1]);
1835 brcmu_pkt_buf_free_skb(pkt);
1836 continue;
1837 }
1838 }
1839
1840 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_DATA_ON(),
1841 pkt->data, rd->len, "Rx Data:\n");
1842
1843 /* Save superframe descriptor and allocate packet frame */
1844 if (rd->channel == SDPCM_GLOM_CHANNEL) {
1845 if (SDPCM_GLOMDESC(&bus->rxhdr[SDPCM_HWHDR_LEN])) {
1846 brcmf_dbg(GLOM, "glom descriptor, %d bytes:\n",
1847 rd->len);
1848 brcmf_dbg_hex_dump(BRCMF_GLOM_ON(),
1849 pkt->data, rd->len,
1850 "Glom Data:\n");
1851 __skb_trim(pkt, rd->len);
1852 skb_pull(pkt, SDPCM_HDRLEN);
1853 bus->glomd = pkt;
1854 } else {
1855 brcmf_err("%s: glom superframe w/o "
1856 "descriptor!\n", __func__);
1857 sdio_claim_host(bus->sdiodev->func[1]);
1858 brcmf_sdbrcm_rxfail(bus, false, false);
1859 sdio_release_host(bus->sdiodev->func[1]);
1860 }
1861 /* prepare the descriptor for the next read */
1862 rd->len = rd->len_nxtfrm << 4;
1863 rd->len_nxtfrm = 0;
1864 /* treat all packet as event if we don't know */
1865 rd->channel = SDPCM_EVENT_CHANNEL;
1866 continue;
1867 }
1868
1869 /* Fill in packet len and prio, deliver upward */
1870 __skb_trim(pkt, rd->len);
1871 skb_pull(pkt, rd->dat_offset);
1872
1873 /* prepare the descriptor for the next read */
1874 rd->len = rd->len_nxtfrm << 4;
1875 rd->len_nxtfrm = 0;
1876 /* treat all packet as event if we don't know */
1877 rd->channel = SDPCM_EVENT_CHANNEL;
1878
1879 if (pkt->len == 0) {
1880 brcmu_pkt_buf_free_skb(pkt);
1881 continue;
1882 }
1883
1884 brcmf_rx_frame(bus->sdiodev->dev, pkt);
1885 }
1886
1887 rxcount = maxframes - rxleft;
1888 /* Message if we hit the limit */
1889 if (!rxleft)
1890 brcmf_dbg(DATA, "hit rx limit of %d frames\n", maxframes);
1891 else
1892 brcmf_dbg(DATA, "processed %d frames\n", rxcount);
1893 /* Back off rxseq if awaiting rtx, update rx_seq */
1894 if (bus->rxskip)
1895 rd->seq_num--;
1896 bus->rx_seq = rd->seq_num;
1897
1898 return rxcount;
1899 }
1900
1901 static void
1902 brcmf_sdbrcm_wait_event_wakeup(struct brcmf_sdio *bus)
1903 {
1904 if (waitqueue_active(&bus->ctrl_wait))
1905 wake_up_interruptible(&bus->ctrl_wait);
1906 return;
1907 }
1908
1909 static int brcmf_sdio_txpkt_hdalign(struct brcmf_sdio *bus, struct sk_buff *pkt)
1910 {
1911 u16 head_align, head_pad;
1912 u8 *dat_buf;
1913
1914 /* SDIO ADMA requires at least 32 bit alignment */
1915 head_align = 4;
1916 if (bus->sdiodev->pdata && bus->sdiodev->pdata->sd_head_align > 4)
1917 head_align = bus->sdiodev->pdata->sd_head_align;
1918
1919 dat_buf = (u8 *)(pkt->data);
1920
1921 /* Check head padding */
1922 head_pad = ((unsigned long)dat_buf % head_align);
1923 if (head_pad) {
1924 if (skb_headroom(pkt) < head_pad) {
1925 bus->sdiodev->bus_if->tx_realloc++;
1926 head_pad = 0;
1927 if (skb_cow(pkt, head_pad))
1928 return -ENOMEM;
1929 }
1930 skb_push(pkt, head_pad);
1931 dat_buf = (u8 *)(pkt->data);
1932 memset(dat_buf, 0, head_pad + bus->tx_hdrlen);
1933 }
1934 return head_pad;
1935 }
1936
1937 /**
1938 * struct brcmf_skbuff_cb reserves first two bytes in sk_buff::cb for
1939 * bus layer usage.
1940 */
1941 /* flag marking a dummy skb added for DMA alignment requirement */
1942 #define ALIGN_SKB_FLAG 0x8000
1943 /* bit mask of data length chopped from the previous packet */
1944 #define ALIGN_SKB_CHOP_LEN_MASK 0x7fff
1945
1946 static int brcmf_sdio_txpkt_prep_sg(struct brcmf_sdio *bus,
1947 struct sk_buff_head *pktq,
1948 struct sk_buff *pkt, u16 total_len)
1949 {
1950 struct brcmf_sdio_dev *sdiodev;
1951 struct sk_buff *pkt_pad;
1952 u16 tail_pad, tail_chop, sg_align, chain_pad;
1953 unsigned int blksize;
1954 bool lastfrm;
1955 int ntail, ret;
1956
1957 sdiodev = bus->sdiodev;
1958 blksize = sdiodev->func[SDIO_FUNC_2]->cur_blksize;
1959 sg_align = 4;
1960 if (sdiodev->pdata && sdiodev->pdata->sd_sgentry_align > 4)
1961 sg_align = sdiodev->pdata->sd_sgentry_align;
1962 /* sg entry alignment should be a divisor of block size */
1963 WARN_ON(blksize % sg_align);
1964
1965 /* Check tail padding */
1966 lastfrm = skb_queue_is_last(pktq, pkt);
1967 tail_pad = 0;
1968 tail_chop = pkt->len % sg_align;
1969 if (tail_chop)
1970 tail_pad = sg_align - tail_chop;
1971 chain_pad = (total_len + tail_pad) % blksize;
1972 if (lastfrm && chain_pad)
1973 tail_pad += blksize - chain_pad;
1974 if (skb_tailroom(pkt) < tail_pad && pkt->len > blksize) {
1975 pkt_pad = bus->txglom_sgpad;
1976 if (pkt_pad == NULL)
1977 brcmu_pkt_buf_get_skb(tail_pad + tail_chop);
1978 if (pkt_pad == NULL)
1979 return -ENOMEM;
1980 ret = brcmf_sdio_txpkt_hdalign(bus, pkt_pad);
1981 if (unlikely(ret < 0))
1982 return ret;
1983 memcpy(pkt_pad->data,
1984 pkt->data + pkt->len - tail_chop,
1985 tail_chop);
1986 *(u32 *)(pkt_pad->cb) = ALIGN_SKB_FLAG + tail_chop;
1987 skb_trim(pkt, pkt->len - tail_chop);
1988 __skb_queue_after(pktq, pkt, pkt_pad);
1989 } else {
1990 ntail = pkt->data_len + tail_pad -
1991 (pkt->end - pkt->tail);
1992 if (skb_cloned(pkt) || ntail > 0)
1993 if (pskb_expand_head(pkt, 0, ntail, GFP_ATOMIC))
1994 return -ENOMEM;
1995 if (skb_linearize(pkt))
1996 return -ENOMEM;
1997 __skb_put(pkt, tail_pad);
1998 }
1999
2000 return tail_pad;
2001 }
2002
2003 /**
2004 * brcmf_sdio_txpkt_prep - packet preparation for transmit
2005 * @bus: brcmf_sdio structure pointer
2006 * @pktq: packet list pointer
2007 * @chan: virtual channel to transmit the packet
2008 *
2009 * Processes to be applied to the packet
2010 * - Align data buffer pointer
2011 * - Align data buffer length
2012 * - Prepare header
2013 * Return: negative value if there is error
2014 */
2015 static int
2016 brcmf_sdio_txpkt_prep(struct brcmf_sdio *bus, struct sk_buff_head *pktq,
2017 uint chan)
2018 {
2019 u16 head_pad, total_len;
2020 struct sk_buff *pkt_next;
2021 u8 txseq;
2022 int ret;
2023 struct brcmf_sdio_hdrinfo hd_info = {0};
2024
2025 txseq = bus->tx_seq;
2026 total_len = 0;
2027 skb_queue_walk(pktq, pkt_next) {
2028 /* alignment packet inserted in previous
2029 * loop cycle can be skipped as it is
2030 * already properly aligned and does not
2031 * need an sdpcm header.
2032 */
2033 if (*(u32 *)(pkt_next->cb) & ALIGN_SKB_FLAG)
2034 continue;
2035
2036 /* align packet data pointer */
2037 ret = brcmf_sdio_txpkt_hdalign(bus, pkt_next);
2038 if (ret < 0)
2039 return ret;
2040 head_pad = (u16)ret;
2041 if (head_pad)
2042 memset(pkt_next->data, 0, head_pad + bus->tx_hdrlen);
2043
2044 total_len += pkt_next->len;
2045
2046 hd_info.len = pkt_next->len;
2047 hd_info.lastfrm = skb_queue_is_last(pktq, pkt_next);
2048 if (bus->txglom && pktq->qlen > 1) {
2049 ret = brcmf_sdio_txpkt_prep_sg(bus, pktq,
2050 pkt_next, total_len);
2051 if (ret < 0)
2052 return ret;
2053 hd_info.tail_pad = (u16)ret;
2054 total_len += (u16)ret;
2055 }
2056
2057 hd_info.channel = chan;
2058 hd_info.dat_offset = head_pad + bus->tx_hdrlen;
2059 hd_info.seq_num = txseq++;
2060
2061 /* Now fill the header */
2062 brcmf_sdio_hdpack(bus, pkt_next->data, &hd_info);
2063
2064 if (BRCMF_BYTES_ON() &&
2065 ((BRCMF_CTL_ON() && chan == SDPCM_CONTROL_CHANNEL) ||
2066 (BRCMF_DATA_ON() && chan != SDPCM_CONTROL_CHANNEL)))
2067 brcmf_dbg_hex_dump(true, pkt_next, hd_info.len,
2068 "Tx Frame:\n");
2069 else if (BRCMF_HDRS_ON())
2070 brcmf_dbg_hex_dump(true, pkt_next,
2071 head_pad + bus->tx_hdrlen,
2072 "Tx Header:\n");
2073 }
2074 /* Hardware length tag of the first packet should be total
2075 * length of the chain (including padding)
2076 */
2077 if (bus->txglom)
2078 brcmf_sdio_update_hwhdr(pktq->next->data, total_len);
2079 return 0;
2080 }
2081
2082 /**
2083 * brcmf_sdio_txpkt_postp - packet post processing for transmit
2084 * @bus: brcmf_sdio structure pointer
2085 * @pktq: packet list pointer
2086 *
2087 * Processes to be applied to the packet
2088 * - Remove head padding
2089 * - Remove tail padding
2090 */
2091 static void
2092 brcmf_sdio_txpkt_postp(struct brcmf_sdio *bus, struct sk_buff_head *pktq)
2093 {
2094 u8 *hdr;
2095 u32 dat_offset;
2096 u16 tail_pad;
2097 u32 dummy_flags, chop_len;
2098 struct sk_buff *pkt_next, *tmp, *pkt_prev;
2099
2100 skb_queue_walk_safe(pktq, pkt_next, tmp) {
2101 dummy_flags = *(u32 *)(pkt_next->cb);
2102 if (dummy_flags & ALIGN_SKB_FLAG) {
2103 chop_len = dummy_flags & ALIGN_SKB_CHOP_LEN_MASK;
2104 if (chop_len) {
2105 pkt_prev = pkt_next->prev;
2106 skb_put(pkt_prev, chop_len);
2107 }
2108 __skb_unlink(pkt_next, pktq);
2109 brcmu_pkt_buf_free_skb(pkt_next);
2110 } else {
2111 hdr = pkt_next->data + bus->tx_hdrlen - SDPCM_SWHDR_LEN;
2112 dat_offset = le32_to_cpu(*(__le32 *)hdr);
2113 dat_offset = (dat_offset & SDPCM_DOFFSET_MASK) >>
2114 SDPCM_DOFFSET_SHIFT;
2115 skb_pull(pkt_next, dat_offset);
2116 if (bus->txglom) {
2117 tail_pad = le16_to_cpu(*(__le16 *)(hdr - 2));
2118 skb_trim(pkt_next, pkt_next->len - tail_pad);
2119 }
2120 }
2121 }
2122 }
2123
2124 /* Writes a HW/SW header into the packet and sends it. */
2125 /* Assumes: (a) header space already there, (b) caller holds lock */
2126 static int brcmf_sdbrcm_txpkt(struct brcmf_sdio *bus, struct sk_buff_head *pktq,
2127 uint chan)
2128 {
2129 int ret;
2130 int i;
2131 struct sk_buff *pkt_next, *tmp;
2132
2133 brcmf_dbg(TRACE, "Enter\n");
2134
2135 ret = brcmf_sdio_txpkt_prep(bus, pktq, chan);
2136 if (ret)
2137 goto done;
2138
2139 sdio_claim_host(bus->sdiodev->func[1]);
2140 ret = brcmf_sdcard_send_pkt(bus->sdiodev, bus->sdiodev->sbwad,
2141 SDIO_FUNC_2, F2SYNC, pktq);
2142 bus->sdcnt.f2txdata++;
2143
2144 if (ret < 0) {
2145 /* On failure, abort the command and terminate the frame */
2146 brcmf_dbg(INFO, "sdio error %d, abort command and terminate frame\n",
2147 ret);
2148 bus->sdcnt.tx_sderrs++;
2149
2150 brcmf_sdcard_abort(bus->sdiodev, SDIO_FUNC_2);
2151 brcmf_sdio_regwb(bus->sdiodev, SBSDIO_FUNC1_FRAMECTRL,
2152 SFC_WF_TERM, NULL);
2153 bus->sdcnt.f1regdata++;
2154
2155 for (i = 0; i < 3; i++) {
2156 u8 hi, lo;
2157 hi = brcmf_sdio_regrb(bus->sdiodev,
2158 SBSDIO_FUNC1_WFRAMEBCHI, NULL);
2159 lo = brcmf_sdio_regrb(bus->sdiodev,
2160 SBSDIO_FUNC1_WFRAMEBCLO, NULL);
2161 bus->sdcnt.f1regdata += 2;
2162 if ((hi == 0) && (lo == 0))
2163 break;
2164 }
2165 }
2166 sdio_release_host(bus->sdiodev->func[1]);
2167
2168 done:
2169 brcmf_sdio_txpkt_postp(bus, pktq);
2170 if (ret == 0)
2171 bus->tx_seq = (bus->tx_seq + pktq->qlen) % SDPCM_SEQ_WRAP;
2172 skb_queue_walk_safe(pktq, pkt_next, tmp) {
2173 __skb_unlink(pkt_next, pktq);
2174 brcmf_txcomplete(bus->sdiodev->dev, pkt_next, ret == 0);
2175 }
2176 return ret;
2177 }
2178
2179 static uint brcmf_sdbrcm_sendfromq(struct brcmf_sdio *bus, uint maxframes)
2180 {
2181 struct sk_buff *pkt;
2182 struct sk_buff_head pktq;
2183 u32 intstatus = 0;
2184 int ret = 0, prec_out, i;
2185 uint cnt = 0;
2186 u8 tx_prec_map, pkt_num;
2187
2188 brcmf_dbg(TRACE, "Enter\n");
2189
2190 tx_prec_map = ~bus->flowcontrol;
2191
2192 /* Send frames until the limit or some other event */
2193 for (cnt = 0; (cnt < maxframes) && data_ok(bus);) {
2194 pkt_num = 1;
2195 __skb_queue_head_init(&pktq);
2196 if (bus->txglom)
2197 pkt_num = min_t(u8, bus->tx_max - bus->tx_seq,
2198 brcmf_sdio_txglomsz);
2199 pkt_num = min_t(u32, pkt_num,
2200 brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol));
2201 spin_lock_bh(&bus->txqlock);
2202 for (i = 0; i < pkt_num; i++) {
2203 pkt = brcmu_pktq_mdeq(&bus->txq, tx_prec_map,
2204 &prec_out);
2205 if (pkt == NULL)
2206 break;
2207 __skb_queue_tail(&pktq, pkt);
2208 }
2209 spin_unlock_bh(&bus->txqlock);
2210 if (i == 0)
2211 break;
2212
2213 ret = brcmf_sdbrcm_txpkt(bus, &pktq, SDPCM_DATA_CHANNEL);
2214 cnt += i;
2215
2216 /* In poll mode, need to check for other events */
2217 if (!bus->intr && cnt) {
2218 /* Check device status, signal pending interrupt */
2219 sdio_claim_host(bus->sdiodev->func[1]);
2220 ret = r_sdreg32(bus, &intstatus,
2221 offsetof(struct sdpcmd_regs,
2222 intstatus));
2223 sdio_release_host(bus->sdiodev->func[1]);
2224 bus->sdcnt.f2txdata++;
2225 if (ret != 0)
2226 break;
2227 if (intstatus & bus->hostintmask)
2228 atomic_set(&bus->ipend, 1);
2229 }
2230 }
2231
2232 /* Deflow-control stack if needed */
2233 if ((bus->sdiodev->bus_if->state == BRCMF_BUS_DATA) &&
2234 bus->txoff && (pktq_len(&bus->txq) < TXLOW)) {
2235 bus->txoff = false;
2236 brcmf_txflowblock(bus->sdiodev->dev, false);
2237 }
2238
2239 return cnt;
2240 }
2241
2242 static void brcmf_sdbrcm_bus_stop(struct device *dev)
2243 {
2244 u32 local_hostintmask;
2245 u8 saveclk;
2246 int err;
2247 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
2248 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
2249 struct brcmf_sdio *bus = sdiodev->bus;
2250
2251 brcmf_dbg(TRACE, "Enter\n");
2252
2253 if (bus->watchdog_tsk) {
2254 send_sig(SIGTERM, bus->watchdog_tsk, 1);
2255 kthread_stop(bus->watchdog_tsk);
2256 bus->watchdog_tsk = NULL;
2257 }
2258
2259 sdio_claim_host(bus->sdiodev->func[1]);
2260
2261 /* Enable clock for device interrupts */
2262 brcmf_sdbrcm_bus_sleep(bus, false, false);
2263
2264 /* Disable and clear interrupts at the chip level also */
2265 w_sdreg32(bus, 0, offsetof(struct sdpcmd_regs, hostintmask));
2266 local_hostintmask = bus->hostintmask;
2267 bus->hostintmask = 0;
2268
2269 /* Change our idea of bus state */
2270 bus->sdiodev->bus_if->state = BRCMF_BUS_DOWN;
2271
2272 /* Force clocks on backplane to be sure F2 interrupt propagates */
2273 saveclk = brcmf_sdio_regrb(bus->sdiodev,
2274 SBSDIO_FUNC1_CHIPCLKCSR, &err);
2275 if (!err) {
2276 brcmf_sdio_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
2277 (saveclk | SBSDIO_FORCE_HT), &err);
2278 }
2279 if (err)
2280 brcmf_err("Failed to force clock for F2: err %d\n", err);
2281
2282 /* Turn off the bus (F2), free any pending packets */
2283 brcmf_dbg(INTR, "disable SDIO interrupts\n");
2284 brcmf_sdio_regwb(bus->sdiodev, SDIO_CCCR_IOEx, SDIO_FUNC_ENABLE_1,
2285 NULL);
2286
2287 /* Clear any pending interrupts now that F2 is disabled */
2288 w_sdreg32(bus, local_hostintmask,
2289 offsetof(struct sdpcmd_regs, intstatus));
2290
2291 /* Turn off the backplane clock (only) */
2292 brcmf_sdbrcm_clkctl(bus, CLK_SDONLY, false);
2293 sdio_release_host(bus->sdiodev->func[1]);
2294
2295 /* Clear the data packet queues */
2296 brcmu_pktq_flush(&bus->txq, true, NULL, NULL);
2297
2298 /* Clear any held glomming stuff */
2299 if (bus->glomd)
2300 brcmu_pkt_buf_free_skb(bus->glomd);
2301 brcmf_sdbrcm_free_glom(bus);
2302
2303 /* Clear rx control and wake any waiters */
2304 spin_lock_bh(&bus->rxctl_lock);
2305 bus->rxlen = 0;
2306 spin_unlock_bh(&bus->rxctl_lock);
2307 brcmf_sdbrcm_dcmd_resp_wake(bus);
2308
2309 /* Reset some F2 state stuff */
2310 bus->rxskip = false;
2311 bus->tx_seq = bus->rx_seq = 0;
2312 }
2313
2314 static inline void brcmf_sdbrcm_clrintr(struct brcmf_sdio *bus)
2315 {
2316 unsigned long flags;
2317
2318 if (bus->sdiodev->oob_irq_requested) {
2319 spin_lock_irqsave(&bus->sdiodev->irq_en_lock, flags);
2320 if (!bus->sdiodev->irq_en && !atomic_read(&bus->ipend)) {
2321 enable_irq(bus->sdiodev->pdata->oob_irq_nr);
2322 bus->sdiodev->irq_en = true;
2323 }
2324 spin_unlock_irqrestore(&bus->sdiodev->irq_en_lock, flags);
2325 }
2326 }
2327
2328 static int brcmf_sdio_intr_rstatus(struct brcmf_sdio *bus)
2329 {
2330 u8 idx;
2331 u32 addr;
2332 unsigned long val;
2333 int n, ret;
2334
2335 idx = brcmf_sdio_chip_getinfidx(bus->ci, BCMA_CORE_SDIO_DEV);
2336 addr = bus->ci->c_inf[idx].base +
2337 offsetof(struct sdpcmd_regs, intstatus);
2338
2339 ret = brcmf_sdio_regrw_helper(bus->sdiodev, addr, &val, false);
2340 bus->sdcnt.f1regdata++;
2341 if (ret != 0)
2342 val = 0;
2343
2344 val &= bus->hostintmask;
2345 atomic_set(&bus->fcstate, !!(val & I_HMB_FC_STATE));
2346
2347 /* Clear interrupts */
2348 if (val) {
2349 ret = brcmf_sdio_regrw_helper(bus->sdiodev, addr, &val, true);
2350 bus->sdcnt.f1regdata++;
2351 }
2352
2353 if (ret) {
2354 atomic_set(&bus->intstatus, 0);
2355 } else if (val) {
2356 for_each_set_bit(n, &val, 32)
2357 set_bit(n, (unsigned long *)&bus->intstatus.counter);
2358 }
2359
2360 return ret;
2361 }
2362
2363 static void brcmf_sdbrcm_dpc(struct brcmf_sdio *bus)
2364 {
2365 u32 newstatus = 0;
2366 unsigned long intstatus;
2367 uint rxlimit = bus->rxbound; /* Rx frames to read before resched */
2368 uint txlimit = bus->txbound; /* Tx frames to send before resched */
2369 uint framecnt = 0; /* Temporary counter of tx/rx frames */
2370 int err = 0, n;
2371
2372 brcmf_dbg(TRACE, "Enter\n");
2373
2374 sdio_claim_host(bus->sdiodev->func[1]);
2375
2376 /* If waiting for HTAVAIL, check status */
2377 if (!bus->sr_enabled && bus->clkstate == CLK_PENDING) {
2378 u8 clkctl, devctl = 0;
2379
2380 #ifdef DEBUG
2381 /* Check for inconsistent device control */
2382 devctl = brcmf_sdio_regrb(bus->sdiodev,
2383 SBSDIO_DEVICE_CTL, &err);
2384 if (err) {
2385 brcmf_err("error reading DEVCTL: %d\n", err);
2386 bus->sdiodev->bus_if->state = BRCMF_BUS_DOWN;
2387 }
2388 #endif /* DEBUG */
2389
2390 /* Read CSR, if clock on switch to AVAIL, else ignore */
2391 clkctl = brcmf_sdio_regrb(bus->sdiodev,
2392 SBSDIO_FUNC1_CHIPCLKCSR, &err);
2393 if (err) {
2394 brcmf_err("error reading CSR: %d\n",
2395 err);
2396 bus->sdiodev->bus_if->state = BRCMF_BUS_DOWN;
2397 }
2398
2399 brcmf_dbg(SDIO, "DPC: PENDING, devctl 0x%02x clkctl 0x%02x\n",
2400 devctl, clkctl);
2401
2402 if (SBSDIO_HTAV(clkctl)) {
2403 devctl = brcmf_sdio_regrb(bus->sdiodev,
2404 SBSDIO_DEVICE_CTL, &err);
2405 if (err) {
2406 brcmf_err("error reading DEVCTL: %d\n",
2407 err);
2408 bus->sdiodev->bus_if->state = BRCMF_BUS_DOWN;
2409 }
2410 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
2411 brcmf_sdio_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL,
2412 devctl, &err);
2413 if (err) {
2414 brcmf_err("error writing DEVCTL: %d\n",
2415 err);
2416 bus->sdiodev->bus_if->state = BRCMF_BUS_DOWN;
2417 }
2418 bus->clkstate = CLK_AVAIL;
2419 }
2420 }
2421
2422 /* Make sure backplane clock is on */
2423 brcmf_sdbrcm_bus_sleep(bus, false, true);
2424
2425 /* Pending interrupt indicates new device status */
2426 if (atomic_read(&bus->ipend) > 0) {
2427 atomic_set(&bus->ipend, 0);
2428 err = brcmf_sdio_intr_rstatus(bus);
2429 }
2430
2431 /* Start with leftover status bits */
2432 intstatus = atomic_xchg(&bus->intstatus, 0);
2433
2434 /* Handle flow-control change: read new state in case our ack
2435 * crossed another change interrupt. If change still set, assume
2436 * FC ON for safety, let next loop through do the debounce.
2437 */
2438 if (intstatus & I_HMB_FC_CHANGE) {
2439 intstatus &= ~I_HMB_FC_CHANGE;
2440 err = w_sdreg32(bus, I_HMB_FC_CHANGE,
2441 offsetof(struct sdpcmd_regs, intstatus));
2442
2443 err = r_sdreg32(bus, &newstatus,
2444 offsetof(struct sdpcmd_regs, intstatus));
2445 bus->sdcnt.f1regdata += 2;
2446 atomic_set(&bus->fcstate,
2447 !!(newstatus & (I_HMB_FC_STATE | I_HMB_FC_CHANGE)));
2448 intstatus |= (newstatus & bus->hostintmask);
2449 }
2450
2451 /* Handle host mailbox indication */
2452 if (intstatus & I_HMB_HOST_INT) {
2453 intstatus &= ~I_HMB_HOST_INT;
2454 intstatus |= brcmf_sdbrcm_hostmail(bus);
2455 }
2456
2457 sdio_release_host(bus->sdiodev->func[1]);
2458
2459 /* Generally don't ask for these, can get CRC errors... */
2460 if (intstatus & I_WR_OOSYNC) {
2461 brcmf_err("Dongle reports WR_OOSYNC\n");
2462 intstatus &= ~I_WR_OOSYNC;
2463 }
2464
2465 if (intstatus & I_RD_OOSYNC) {
2466 brcmf_err("Dongle reports RD_OOSYNC\n");
2467 intstatus &= ~I_RD_OOSYNC;
2468 }
2469
2470 if (intstatus & I_SBINT) {
2471 brcmf_err("Dongle reports SBINT\n");
2472 intstatus &= ~I_SBINT;
2473 }
2474
2475 /* Would be active due to wake-wlan in gSPI */
2476 if (intstatus & I_CHIPACTIVE) {
2477 brcmf_dbg(INFO, "Dongle reports CHIPACTIVE\n");
2478 intstatus &= ~I_CHIPACTIVE;
2479 }
2480
2481 /* Ignore frame indications if rxskip is set */
2482 if (bus->rxskip)
2483 intstatus &= ~I_HMB_FRAME_IND;
2484
2485 /* On frame indication, read available frames */
2486 if (PKT_AVAILABLE() && bus->clkstate == CLK_AVAIL) {
2487 framecnt = brcmf_sdio_readframes(bus, rxlimit);
2488 if (!bus->rxpending)
2489 intstatus &= ~I_HMB_FRAME_IND;
2490 rxlimit -= min(framecnt, rxlimit);
2491 }
2492
2493 /* Keep still-pending events for next scheduling */
2494 if (intstatus) {
2495 for_each_set_bit(n, &intstatus, 32)
2496 set_bit(n, (unsigned long *)&bus->intstatus.counter);
2497 }
2498
2499 brcmf_sdbrcm_clrintr(bus);
2500
2501 if (data_ok(bus) && bus->ctrl_frame_stat &&
2502 (bus->clkstate == CLK_AVAIL)) {
2503 int i;
2504
2505 sdio_claim_host(bus->sdiodev->func[1]);
2506 err = brcmf_sdcard_send_buf(bus->sdiodev, bus->sdiodev->sbwad,
2507 SDIO_FUNC_2, F2SYNC, bus->ctrl_frame_buf,
2508 (u32) bus->ctrl_frame_len);
2509
2510 if (err < 0) {
2511 /* On failure, abort the command and
2512 terminate the frame */
2513 brcmf_dbg(INFO, "sdio error %d, abort command and terminate frame\n",
2514 err);
2515 bus->sdcnt.tx_sderrs++;
2516
2517 brcmf_sdcard_abort(bus->sdiodev, SDIO_FUNC_2);
2518
2519 brcmf_sdio_regwb(bus->sdiodev, SBSDIO_FUNC1_FRAMECTRL,
2520 SFC_WF_TERM, &err);
2521 bus->sdcnt.f1regdata++;
2522
2523 for (i = 0; i < 3; i++) {
2524 u8 hi, lo;
2525 hi = brcmf_sdio_regrb(bus->sdiodev,
2526 SBSDIO_FUNC1_WFRAMEBCHI,
2527 &err);
2528 lo = brcmf_sdio_regrb(bus->sdiodev,
2529 SBSDIO_FUNC1_WFRAMEBCLO,
2530 &err);
2531 bus->sdcnt.f1regdata += 2;
2532 if ((hi == 0) && (lo == 0))
2533 break;
2534 }
2535
2536 } else {
2537 bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQ_WRAP;
2538 }
2539 sdio_release_host(bus->sdiodev->func[1]);
2540 bus->ctrl_frame_stat = false;
2541 brcmf_sdbrcm_wait_event_wakeup(bus);
2542 }
2543 /* Send queued frames (limit 1 if rx may still be pending) */
2544 else if ((bus->clkstate == CLK_AVAIL) && !atomic_read(&bus->fcstate) &&
2545 brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol) && txlimit
2546 && data_ok(bus)) {
2547 framecnt = bus->rxpending ? min(txlimit, bus->txminmax) :
2548 txlimit;
2549 framecnt = brcmf_sdbrcm_sendfromq(bus, framecnt);
2550 txlimit -= framecnt;
2551 }
2552
2553 if ((bus->sdiodev->bus_if->state == BRCMF_BUS_DOWN) || (err != 0)) {
2554 brcmf_err("failed backplane access over SDIO, halting operation\n");
2555 bus->sdiodev->bus_if->state = BRCMF_BUS_DOWN;
2556 atomic_set(&bus->intstatus, 0);
2557 } else if (atomic_read(&bus->intstatus) ||
2558 atomic_read(&bus->ipend) > 0 ||
2559 (!atomic_read(&bus->fcstate) &&
2560 brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol) &&
2561 data_ok(bus)) || PKT_AVAILABLE()) {
2562 atomic_inc(&bus->dpc_tskcnt);
2563 }
2564
2565 /* If we're done for now, turn off clock request. */
2566 if ((bus->clkstate != CLK_PENDING)
2567 && bus->idletime == BRCMF_IDLE_IMMEDIATE) {
2568 bus->activity = false;
2569 brcmf_dbg(SDIO, "idle state\n");
2570 sdio_claim_host(bus->sdiodev->func[1]);
2571 brcmf_sdbrcm_bus_sleep(bus, true, false);
2572 sdio_release_host(bus->sdiodev->func[1]);
2573 }
2574 }
2575
2576 static struct pktq *brcmf_sdbrcm_bus_gettxq(struct device *dev)
2577 {
2578 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
2579 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
2580 struct brcmf_sdio *bus = sdiodev->bus;
2581
2582 return &bus->txq;
2583 }
2584
2585 static int brcmf_sdbrcm_bus_txdata(struct device *dev, struct sk_buff *pkt)
2586 {
2587 int ret = -EBADE;
2588 uint datalen, prec;
2589 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
2590 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
2591 struct brcmf_sdio *bus = sdiodev->bus;
2592 ulong flags;
2593
2594 brcmf_dbg(TRACE, "Enter\n");
2595
2596 datalen = pkt->len;
2597
2598 /* Add space for the header */
2599 skb_push(pkt, bus->tx_hdrlen);
2600 /* precondition: IS_ALIGNED((unsigned long)(pkt->data), 2) */
2601
2602 prec = prio2prec((pkt->priority & PRIOMASK));
2603
2604 /* Check for existing queue, current flow-control,
2605 pending event, or pending clock */
2606 brcmf_dbg(TRACE, "deferring pktq len %d\n", pktq_len(&bus->txq));
2607 bus->sdcnt.fcqueued++;
2608
2609 /* Priority based enq */
2610 spin_lock_irqsave(&bus->txqlock, flags);
2611 if (!brcmf_c_prec_enq(bus->sdiodev->dev, &bus->txq, pkt, prec)) {
2612 skb_pull(pkt, bus->tx_hdrlen);
2613 brcmf_err("out of bus->txq !!!\n");
2614 ret = -ENOSR;
2615 } else {
2616 ret = 0;
2617 }
2618
2619 if (pktq_len(&bus->txq) >= TXHI) {
2620 bus->txoff = true;
2621 brcmf_txflowblock(bus->sdiodev->dev, true);
2622 }
2623 spin_unlock_irqrestore(&bus->txqlock, flags);
2624
2625 #ifdef DEBUG
2626 if (pktq_plen(&bus->txq, prec) > qcount[prec])
2627 qcount[prec] = pktq_plen(&bus->txq, prec);
2628 #endif
2629
2630 if (atomic_read(&bus->dpc_tskcnt) == 0) {
2631 atomic_inc(&bus->dpc_tskcnt);
2632 queue_work(bus->brcmf_wq, &bus->datawork);
2633 }
2634
2635 return ret;
2636 }
2637
2638 #ifdef DEBUG
2639 #define CONSOLE_LINE_MAX 192
2640
2641 static int brcmf_sdbrcm_readconsole(struct brcmf_sdio *bus)
2642 {
2643 struct brcmf_console *c = &bus->console;
2644 u8 line[CONSOLE_LINE_MAX], ch;
2645 u32 n, idx, addr;
2646 int rv;
2647
2648 /* Don't do anything until FWREADY updates console address */
2649 if (bus->console_addr == 0)
2650 return 0;
2651
2652 /* Read console log struct */
2653 addr = bus->console_addr + offsetof(struct rte_console, log_le);
2654 rv = brcmf_sdio_ramrw(bus->sdiodev, false, addr, (u8 *)&c->log_le,
2655 sizeof(c->log_le));
2656 if (rv < 0)
2657 return rv;
2658
2659 /* Allocate console buffer (one time only) */
2660 if (c->buf == NULL) {
2661 c->bufsize = le32_to_cpu(c->log_le.buf_size);
2662 c->buf = kmalloc(c->bufsize, GFP_ATOMIC);
2663 if (c->buf == NULL)
2664 return -ENOMEM;
2665 }
2666
2667 idx = le32_to_cpu(c->log_le.idx);
2668
2669 /* Protect against corrupt value */
2670 if (idx > c->bufsize)
2671 return -EBADE;
2672
2673 /* Skip reading the console buffer if the index pointer
2674 has not moved */
2675 if (idx == c->last)
2676 return 0;
2677
2678 /* Read the console buffer */
2679 addr = le32_to_cpu(c->log_le.buf);
2680 rv = brcmf_sdio_ramrw(bus->sdiodev, false, addr, c->buf, c->bufsize);
2681 if (rv < 0)
2682 return rv;
2683
2684 while (c->last != idx) {
2685 for (n = 0; n < CONSOLE_LINE_MAX - 2; n++) {
2686 if (c->last == idx) {
2687 /* This would output a partial line.
2688 * Instead, back up
2689 * the buffer pointer and output this
2690 * line next time around.
2691 */
2692 if (c->last >= n)
2693 c->last -= n;
2694 else
2695 c->last = c->bufsize - n;
2696 goto break2;
2697 }
2698 ch = c->buf[c->last];
2699 c->last = (c->last + 1) % c->bufsize;
2700 if (ch == '\n')
2701 break;
2702 line[n] = ch;
2703 }
2704
2705 if (n > 0) {
2706 if (line[n - 1] == '\r')
2707 n--;
2708 line[n] = 0;
2709 pr_debug("CONSOLE: %s\n", line);
2710 }
2711 }
2712 break2:
2713
2714 return 0;
2715 }
2716 #endif /* DEBUG */
2717
2718 static int brcmf_tx_frame(struct brcmf_sdio *bus, u8 *frame, u16 len)
2719 {
2720 int i;
2721 int ret;
2722
2723 bus->ctrl_frame_stat = false;
2724 ret = brcmf_sdcard_send_buf(bus->sdiodev, bus->sdiodev->sbwad,
2725 SDIO_FUNC_2, F2SYNC, frame, len);
2726
2727 if (ret < 0) {
2728 /* On failure, abort the command and terminate the frame */
2729 brcmf_dbg(INFO, "sdio error %d, abort command and terminate frame\n",
2730 ret);
2731 bus->sdcnt.tx_sderrs++;
2732
2733 brcmf_sdcard_abort(bus->sdiodev, SDIO_FUNC_2);
2734
2735 brcmf_sdio_regwb(bus->sdiodev, SBSDIO_FUNC1_FRAMECTRL,
2736 SFC_WF_TERM, NULL);
2737 bus->sdcnt.f1regdata++;
2738
2739 for (i = 0; i < 3; i++) {
2740 u8 hi, lo;
2741 hi = brcmf_sdio_regrb(bus->sdiodev,
2742 SBSDIO_FUNC1_WFRAMEBCHI, NULL);
2743 lo = brcmf_sdio_regrb(bus->sdiodev,
2744 SBSDIO_FUNC1_WFRAMEBCLO, NULL);
2745 bus->sdcnt.f1regdata += 2;
2746 if (hi == 0 && lo == 0)
2747 break;
2748 }
2749 return ret;
2750 }
2751
2752 bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQ_WRAP;
2753
2754 return ret;
2755 }
2756
2757 static int
2758 brcmf_sdbrcm_bus_txctl(struct device *dev, unsigned char *msg, uint msglen)
2759 {
2760 u8 *frame;
2761 u16 len, pad;
2762 uint retries = 0;
2763 u8 doff = 0;
2764 int ret = -1;
2765 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
2766 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
2767 struct brcmf_sdio *bus = sdiodev->bus;
2768 struct brcmf_sdio_hdrinfo hd_info = {0};
2769
2770 brcmf_dbg(TRACE, "Enter\n");
2771
2772 /* Back the pointer to make a room for bus header */
2773 frame = msg - bus->tx_hdrlen;
2774 len = (msglen += bus->tx_hdrlen);
2775
2776 /* Add alignment padding (optional for ctl frames) */
2777 doff = ((unsigned long)frame % BRCMF_SDALIGN);
2778 if (doff) {
2779 frame -= doff;
2780 len += doff;
2781 msglen += doff;
2782 memset(frame, 0, doff + bus->tx_hdrlen);
2783 }
2784 /* precondition: doff < BRCMF_SDALIGN */
2785 doff += bus->tx_hdrlen;
2786
2787 /* Round send length to next SDIO block */
2788 pad = 0;
2789 if (bus->roundup && bus->blocksize && (len > bus->blocksize)) {
2790 pad = bus->blocksize - (len % bus->blocksize);
2791 if ((pad > bus->roundup) || (pad >= bus->blocksize))
2792 pad = 0;
2793 } else if (len % BRCMF_SDALIGN) {
2794 pad = BRCMF_SDALIGN - (len % BRCMF_SDALIGN);
2795 }
2796 len += pad;
2797
2798 /* Satisfy length-alignment requirements */
2799 if (len & (ALIGNMENT - 1))
2800 len = roundup(len, ALIGNMENT);
2801
2802 /* precondition: IS_ALIGNED((unsigned long)frame, 2) */
2803
2804 /* Make sure backplane clock is on */
2805 sdio_claim_host(bus->sdiodev->func[1]);
2806 brcmf_sdbrcm_bus_sleep(bus, false, false);
2807 sdio_release_host(bus->sdiodev->func[1]);
2808
2809 hd_info.len = (u16)msglen;
2810 hd_info.channel = SDPCM_CONTROL_CHANNEL;
2811 hd_info.dat_offset = doff;
2812 hd_info.seq_num = bus->tx_seq;
2813 if (bus->txglom) {
2814 hd_info.lastfrm = true;
2815 hd_info.tail_pad = pad;
2816 }
2817 brcmf_sdio_hdpack(bus, frame, &hd_info);
2818
2819 if (bus->txglom)
2820 brcmf_sdio_update_hwhdr(frame, len);
2821
2822 if (!data_ok(bus)) {
2823 brcmf_dbg(INFO, "No bus credit bus->tx_max %d, bus->tx_seq %d\n",
2824 bus->tx_max, bus->tx_seq);
2825 bus->ctrl_frame_stat = true;
2826 /* Send from dpc */
2827 bus->ctrl_frame_buf = frame;
2828 bus->ctrl_frame_len = len;
2829
2830 wait_event_interruptible_timeout(bus->ctrl_wait,
2831 !bus->ctrl_frame_stat,
2832 msecs_to_jiffies(2000));
2833
2834 if (!bus->ctrl_frame_stat) {
2835 brcmf_dbg(SDIO, "ctrl_frame_stat == false\n");
2836 ret = 0;
2837 } else {
2838 brcmf_dbg(SDIO, "ctrl_frame_stat == true\n");
2839 ret = -1;
2840 }
2841 }
2842
2843 if (ret == -1) {
2844 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_CTL_ON(),
2845 frame, len, "Tx Frame:\n");
2846 brcmf_dbg_hex_dump(!(BRCMF_BYTES_ON() && BRCMF_CTL_ON()) &&
2847 BRCMF_HDRS_ON(),
2848 frame, min_t(u16, len, 16), "TxHdr:\n");
2849
2850 do {
2851 sdio_claim_host(bus->sdiodev->func[1]);
2852 ret = brcmf_tx_frame(bus, frame, len);
2853 sdio_release_host(bus->sdiodev->func[1]);
2854 } while (ret < 0 && retries++ < TXRETRIES);
2855 }
2856
2857 if ((bus->idletime == BRCMF_IDLE_IMMEDIATE) &&
2858 atomic_read(&bus->dpc_tskcnt) == 0) {
2859 bus->activity = false;
2860 sdio_claim_host(bus->sdiodev->func[1]);
2861 brcmf_dbg(INFO, "idle\n");
2862 brcmf_sdbrcm_clkctl(bus, CLK_NONE, true);
2863 sdio_release_host(bus->sdiodev->func[1]);
2864 }
2865
2866 if (ret)
2867 bus->sdcnt.tx_ctlerrs++;
2868 else
2869 bus->sdcnt.tx_ctlpkts++;
2870
2871 return ret ? -EIO : 0;
2872 }
2873
2874 #ifdef DEBUG
2875 static inline bool brcmf_sdio_valid_shared_address(u32 addr)
2876 {
2877 return !(addr == 0 || ((~addr >> 16) & 0xffff) == (addr & 0xffff));
2878 }
2879
2880 static int brcmf_sdio_readshared(struct brcmf_sdio *bus,
2881 struct sdpcm_shared *sh)
2882 {
2883 u32 addr;
2884 int rv;
2885 u32 shaddr = 0;
2886 struct sdpcm_shared_le sh_le;
2887 __le32 addr_le;
2888
2889 shaddr = bus->ci->rambase + bus->ramsize - 4;
2890
2891 /*
2892 * Read last word in socram to determine
2893 * address of sdpcm_shared structure
2894 */
2895 sdio_claim_host(bus->sdiodev->func[1]);
2896 brcmf_sdbrcm_bus_sleep(bus, false, false);
2897 rv = brcmf_sdio_ramrw(bus->sdiodev, false, shaddr, (u8 *)&addr_le, 4);
2898 sdio_release_host(bus->sdiodev->func[1]);
2899 if (rv < 0)
2900 return rv;
2901
2902 addr = le32_to_cpu(addr_le);
2903
2904 brcmf_dbg(SDIO, "sdpcm_shared address 0x%08X\n", addr);
2905
2906 /*
2907 * Check if addr is valid.
2908 * NVRAM length at the end of memory should have been overwritten.
2909 */
2910 if (!brcmf_sdio_valid_shared_address(addr)) {
2911 brcmf_err("invalid sdpcm_shared address 0x%08X\n",
2912 addr);
2913 return -EINVAL;
2914 }
2915
2916 /* Read hndrte_shared structure */
2917 rv = brcmf_sdio_ramrw(bus->sdiodev, false, addr, (u8 *)&sh_le,
2918 sizeof(struct sdpcm_shared_le));
2919 if (rv < 0)
2920 return rv;
2921
2922 /* Endianness */
2923 sh->flags = le32_to_cpu(sh_le.flags);
2924 sh->trap_addr = le32_to_cpu(sh_le.trap_addr);
2925 sh->assert_exp_addr = le32_to_cpu(sh_le.assert_exp_addr);
2926 sh->assert_file_addr = le32_to_cpu(sh_le.assert_file_addr);
2927 sh->assert_line = le32_to_cpu(sh_le.assert_line);
2928 sh->console_addr = le32_to_cpu(sh_le.console_addr);
2929 sh->msgtrace_addr = le32_to_cpu(sh_le.msgtrace_addr);
2930
2931 if ((sh->flags & SDPCM_SHARED_VERSION_MASK) > SDPCM_SHARED_VERSION) {
2932 brcmf_err("sdpcm shared version unsupported: dhd %d dongle %d\n",
2933 SDPCM_SHARED_VERSION,
2934 sh->flags & SDPCM_SHARED_VERSION_MASK);
2935 return -EPROTO;
2936 }
2937
2938 return 0;
2939 }
2940
2941 static int brcmf_sdio_dump_console(struct brcmf_sdio *bus,
2942 struct sdpcm_shared *sh, char __user *data,
2943 size_t count)
2944 {
2945 u32 addr, console_ptr, console_size, console_index;
2946 char *conbuf = NULL;
2947 __le32 sh_val;
2948 int rv;
2949 loff_t pos = 0;
2950 int nbytes = 0;
2951
2952 /* obtain console information from device memory */
2953 addr = sh->console_addr + offsetof(struct rte_console, log_le);
2954 rv = brcmf_sdio_ramrw(bus->sdiodev, false, addr,
2955 (u8 *)&sh_val, sizeof(u32));
2956 if (rv < 0)
2957 return rv;
2958 console_ptr = le32_to_cpu(sh_val);
2959
2960 addr = sh->console_addr + offsetof(struct rte_console, log_le.buf_size);
2961 rv = brcmf_sdio_ramrw(bus->sdiodev, false, addr,
2962 (u8 *)&sh_val, sizeof(u32));
2963 if (rv < 0)
2964 return rv;
2965 console_size = le32_to_cpu(sh_val);
2966
2967 addr = sh->console_addr + offsetof(struct rte_console, log_le.idx);
2968 rv = brcmf_sdio_ramrw(bus->sdiodev, false, addr,
2969 (u8 *)&sh_val, sizeof(u32));
2970 if (rv < 0)
2971 return rv;
2972 console_index = le32_to_cpu(sh_val);
2973
2974 /* allocate buffer for console data */
2975 if (console_size <= CONSOLE_BUFFER_MAX)
2976 conbuf = vzalloc(console_size+1);
2977
2978 if (!conbuf)
2979 return -ENOMEM;
2980
2981 /* obtain the console data from device */
2982 conbuf[console_size] = '\0';
2983 rv = brcmf_sdio_ramrw(bus->sdiodev, false, console_ptr, (u8 *)conbuf,
2984 console_size);
2985 if (rv < 0)
2986 goto done;
2987
2988 rv = simple_read_from_buffer(data, count, &pos,
2989 conbuf + console_index,
2990 console_size - console_index);
2991 if (rv < 0)
2992 goto done;
2993
2994 nbytes = rv;
2995 if (console_index > 0) {
2996 pos = 0;
2997 rv = simple_read_from_buffer(data+nbytes, count, &pos,
2998 conbuf, console_index - 1);
2999 if (rv < 0)
3000 goto done;
3001 rv += nbytes;
3002 }
3003 done:
3004 vfree(conbuf);
3005 return rv;
3006 }
3007
3008 static int brcmf_sdio_trap_info(struct brcmf_sdio *bus, struct sdpcm_shared *sh,
3009 char __user *data, size_t count)
3010 {
3011 int error, res;
3012 char buf[350];
3013 struct brcmf_trap_info tr;
3014 loff_t pos = 0;
3015
3016 if ((sh->flags & SDPCM_SHARED_TRAP) == 0) {
3017 brcmf_dbg(INFO, "no trap in firmware\n");
3018 return 0;
3019 }
3020
3021 error = brcmf_sdio_ramrw(bus->sdiodev, false, sh->trap_addr, (u8 *)&tr,
3022 sizeof(struct brcmf_trap_info));
3023 if (error < 0)
3024 return error;
3025
3026 res = scnprintf(buf, sizeof(buf),
3027 "dongle trap info: type 0x%x @ epc 0x%08x\n"
3028 " cpsr 0x%08x spsr 0x%08x sp 0x%08x\n"
3029 " lr 0x%08x pc 0x%08x offset 0x%x\n"
3030 " r0 0x%08x r1 0x%08x r2 0x%08x r3 0x%08x\n"
3031 " r4 0x%08x r5 0x%08x r6 0x%08x r7 0x%08x\n",
3032 le32_to_cpu(tr.type), le32_to_cpu(tr.epc),
3033 le32_to_cpu(tr.cpsr), le32_to_cpu(tr.spsr),
3034 le32_to_cpu(tr.r13), le32_to_cpu(tr.r14),
3035 le32_to_cpu(tr.pc), sh->trap_addr,
3036 le32_to_cpu(tr.r0), le32_to_cpu(tr.r1),
3037 le32_to_cpu(tr.r2), le32_to_cpu(tr.r3),
3038 le32_to_cpu(tr.r4), le32_to_cpu(tr.r5),
3039 le32_to_cpu(tr.r6), le32_to_cpu(tr.r7));
3040
3041 return simple_read_from_buffer(data, count, &pos, buf, res);
3042 }
3043
3044 static int brcmf_sdio_assert_info(struct brcmf_sdio *bus,
3045 struct sdpcm_shared *sh, char __user *data,
3046 size_t count)
3047 {
3048 int error = 0;
3049 char buf[200];
3050 char file[80] = "?";
3051 char expr[80] = "<???>";
3052 int res;
3053 loff_t pos = 0;
3054
3055 if ((sh->flags & SDPCM_SHARED_ASSERT_BUILT) == 0) {
3056 brcmf_dbg(INFO, "firmware not built with -assert\n");
3057 return 0;
3058 } else if ((sh->flags & SDPCM_SHARED_ASSERT) == 0) {
3059 brcmf_dbg(INFO, "no assert in dongle\n");
3060 return 0;
3061 }
3062
3063 sdio_claim_host(bus->sdiodev->func[1]);
3064 if (sh->assert_file_addr != 0) {
3065 error = brcmf_sdio_ramrw(bus->sdiodev, false,
3066 sh->assert_file_addr, (u8 *)file, 80);
3067 if (error < 0)
3068 return error;
3069 }
3070 if (sh->assert_exp_addr != 0) {
3071 error = brcmf_sdio_ramrw(bus->sdiodev, false,
3072 sh->assert_exp_addr, (u8 *)expr, 80);
3073 if (error < 0)
3074 return error;
3075 }
3076 sdio_release_host(bus->sdiodev->func[1]);
3077
3078 res = scnprintf(buf, sizeof(buf),
3079 "dongle assert: %s:%d: assert(%s)\n",
3080 file, sh->assert_line, expr);
3081 return simple_read_from_buffer(data, count, &pos, buf, res);
3082 }
3083
3084 static int brcmf_sdbrcm_checkdied(struct brcmf_sdio *bus)
3085 {
3086 int error;
3087 struct sdpcm_shared sh;
3088
3089 error = brcmf_sdio_readshared(bus, &sh);
3090
3091 if (error < 0)
3092 return error;
3093
3094 if ((sh.flags & SDPCM_SHARED_ASSERT_BUILT) == 0)
3095 brcmf_dbg(INFO, "firmware not built with -assert\n");
3096 else if (sh.flags & SDPCM_SHARED_ASSERT)
3097 brcmf_err("assertion in dongle\n");
3098
3099 if (sh.flags & SDPCM_SHARED_TRAP)
3100 brcmf_err("firmware trap in dongle\n");
3101
3102 return 0;
3103 }
3104
3105 static int brcmf_sdbrcm_died_dump(struct brcmf_sdio *bus, char __user *data,
3106 size_t count, loff_t *ppos)
3107 {
3108 int error = 0;
3109 struct sdpcm_shared sh;
3110 int nbytes = 0;
3111 loff_t pos = *ppos;
3112
3113 if (pos != 0)
3114 return 0;
3115
3116 error = brcmf_sdio_readshared(bus, &sh);
3117 if (error < 0)
3118 goto done;
3119
3120 error = brcmf_sdio_assert_info(bus, &sh, data, count);
3121 if (error < 0)
3122 goto done;
3123 nbytes = error;
3124
3125 error = brcmf_sdio_trap_info(bus, &sh, data+nbytes, count);
3126 if (error < 0)
3127 goto done;
3128 nbytes += error;
3129
3130 error = brcmf_sdio_dump_console(bus, &sh, data+nbytes, count);
3131 if (error < 0)
3132 goto done;
3133 nbytes += error;
3134
3135 error = nbytes;
3136 *ppos += nbytes;
3137 done:
3138 return error;
3139 }
3140
3141 static ssize_t brcmf_sdio_forensic_read(struct file *f, char __user *data,
3142 size_t count, loff_t *ppos)
3143 {
3144 struct brcmf_sdio *bus = f->private_data;
3145 int res;
3146
3147 res = brcmf_sdbrcm_died_dump(bus, data, count, ppos);
3148 if (res > 0)
3149 *ppos += res;
3150 return (ssize_t)res;
3151 }
3152
3153 static const struct file_operations brcmf_sdio_forensic_ops = {
3154 .owner = THIS_MODULE,
3155 .open = simple_open,
3156 .read = brcmf_sdio_forensic_read
3157 };
3158
3159 static void brcmf_sdio_debugfs_create(struct brcmf_sdio *bus)
3160 {
3161 struct brcmf_pub *drvr = bus->sdiodev->bus_if->drvr;
3162 struct dentry *dentry = brcmf_debugfs_get_devdir(drvr);
3163
3164 if (IS_ERR_OR_NULL(dentry))
3165 return;
3166
3167 debugfs_create_file("forensics", S_IRUGO, dentry, bus,
3168 &brcmf_sdio_forensic_ops);
3169 brcmf_debugfs_create_sdio_count(drvr, &bus->sdcnt);
3170 }
3171 #else
3172 static int brcmf_sdbrcm_checkdied(struct brcmf_sdio *bus)
3173 {
3174 return 0;
3175 }
3176
3177 static void brcmf_sdio_debugfs_create(struct brcmf_sdio *bus)
3178 {
3179 }
3180 #endif /* DEBUG */
3181
3182 static int
3183 brcmf_sdbrcm_bus_rxctl(struct device *dev, unsigned char *msg, uint msglen)
3184 {
3185 int timeleft;
3186 uint rxlen = 0;
3187 bool pending;
3188 u8 *buf;
3189 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
3190 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
3191 struct brcmf_sdio *bus = sdiodev->bus;
3192
3193 brcmf_dbg(TRACE, "Enter\n");
3194
3195 /* Wait until control frame is available */
3196 timeleft = brcmf_sdbrcm_dcmd_resp_wait(bus, &bus->rxlen, &pending);
3197
3198 spin_lock_bh(&bus->rxctl_lock);
3199 rxlen = bus->rxlen;
3200 memcpy(msg, bus->rxctl, min(msglen, rxlen));
3201 bus->rxctl = NULL;
3202 buf = bus->rxctl_orig;
3203 bus->rxctl_orig = NULL;
3204 bus->rxlen = 0;
3205 spin_unlock_bh(&bus->rxctl_lock);
3206 vfree(buf);
3207
3208 if (rxlen) {
3209 brcmf_dbg(CTL, "resumed on rxctl frame, got %d expected %d\n",
3210 rxlen, msglen);
3211 } else if (timeleft == 0) {
3212 brcmf_err("resumed on timeout\n");
3213 brcmf_sdbrcm_checkdied(bus);
3214 } else if (pending) {
3215 brcmf_dbg(CTL, "cancelled\n");
3216 return -ERESTARTSYS;
3217 } else {
3218 brcmf_dbg(CTL, "resumed for unknown reason?\n");
3219 brcmf_sdbrcm_checkdied(bus);
3220 }
3221
3222 if (rxlen)
3223 bus->sdcnt.rx_ctlpkts++;
3224 else
3225 bus->sdcnt.rx_ctlerrs++;
3226
3227 return rxlen ? (int)rxlen : -ETIMEDOUT;
3228 }
3229
3230 static bool brcmf_sdbrcm_download_state(struct brcmf_sdio *bus, bool enter)
3231 {
3232 struct chip_info *ci = bus->ci;
3233
3234 /* To enter download state, disable ARM and reset SOCRAM.
3235 * To exit download state, simply reset ARM (default is RAM boot).
3236 */
3237 if (enter) {
3238 bus->alp_only = true;
3239
3240 brcmf_sdio_chip_enter_download(bus->sdiodev, ci);
3241 } else {
3242 if (!brcmf_sdio_chip_exit_download(bus->sdiodev, ci, bus->vars,
3243 bus->varsz))
3244 return false;
3245
3246 /* Allow HT Clock now that the ARM is running. */
3247 bus->alp_only = false;
3248
3249 bus->sdiodev->bus_if->state = BRCMF_BUS_LOAD;
3250 }
3251
3252 return true;
3253 }
3254
3255 static int brcmf_sdbrcm_download_code_file(struct brcmf_sdio *bus)
3256 {
3257 const struct firmware *fw;
3258 int err;
3259 int offset;
3260 int address;
3261 int len;
3262
3263 fw = brcmf_sdbrcm_get_fw(bus, BRCMF_FIRMWARE_BIN);
3264 if (fw == NULL)
3265 return -ENOENT;
3266
3267 if (brcmf_sdio_chip_getinfidx(bus->ci, BCMA_CORE_ARM_CR4) !=
3268 BRCMF_MAX_CORENUM)
3269 memcpy(&bus->ci->rst_vec, fw->data, sizeof(bus->ci->rst_vec));
3270
3271 err = 0;
3272 offset = 0;
3273 address = bus->ci->rambase;
3274 while (offset < fw->size) {
3275 len = ((offset + MEMBLOCK) < fw->size) ? MEMBLOCK :
3276 fw->size - offset;
3277 err = brcmf_sdio_ramrw(bus->sdiodev, true, address,
3278 (u8 *)&fw->data[offset], len);
3279 if (err) {
3280 brcmf_err("error %d on writing %d membytes at 0x%08x\n",
3281 err, len, address);
3282 goto failure;
3283 }
3284 offset += len;
3285 address += len;
3286 }
3287
3288 failure:
3289 release_firmware(fw);
3290
3291 return err;
3292 }
3293
3294 /*
3295 * ProcessVars:Takes a buffer of "<var>=<value>\n" lines read from a file
3296 * and ending in a NUL.
3297 * Removes carriage returns, empty lines, comment lines, and converts
3298 * newlines to NULs.
3299 * Shortens buffer as needed and pads with NULs. End of buffer is marked
3300 * by two NULs.
3301 */
3302
3303 static int brcmf_process_nvram_vars(struct brcmf_sdio *bus,
3304 const struct firmware *nv)
3305 {
3306 char *varbuf;
3307 char *dp;
3308 bool findNewline;
3309 int column;
3310 int ret = 0;
3311 uint buf_len, n, len;
3312
3313 len = nv->size;
3314 varbuf = vmalloc(len);
3315 if (!varbuf)
3316 return -ENOMEM;
3317
3318 memcpy(varbuf, nv->data, len);
3319 dp = varbuf;
3320
3321 findNewline = false;
3322 column = 0;
3323
3324 for (n = 0; n < len; n++) {
3325 if (varbuf[n] == 0)
3326 break;
3327 if (varbuf[n] == '\r')
3328 continue;
3329 if (findNewline && varbuf[n] != '\n')
3330 continue;
3331 findNewline = false;
3332 if (varbuf[n] == '#') {
3333 findNewline = true;
3334 continue;
3335 }
3336 if (varbuf[n] == '\n') {
3337 if (column == 0)
3338 continue;
3339 *dp++ = 0;
3340 column = 0;
3341 continue;
3342 }
3343 *dp++ = varbuf[n];
3344 column++;
3345 }
3346 buf_len = dp - varbuf;
3347 while (dp < varbuf + n)
3348 *dp++ = 0;
3349
3350 kfree(bus->vars);
3351 /* roundup needed for download to device */
3352 bus->varsz = roundup(buf_len + 1, 4);
3353 bus->vars = kmalloc(bus->varsz, GFP_KERNEL);
3354 if (bus->vars == NULL) {
3355 bus->varsz = 0;
3356 ret = -ENOMEM;
3357 goto err;
3358 }
3359
3360 /* copy the processed variables and add null termination */
3361 memcpy(bus->vars, varbuf, buf_len);
3362 bus->vars[buf_len] = 0;
3363 err:
3364 vfree(varbuf);
3365 return ret;
3366 }
3367
3368 static int brcmf_sdbrcm_download_nvram(struct brcmf_sdio *bus)
3369 {
3370 const struct firmware *nv;
3371 int ret;
3372
3373 nv = brcmf_sdbrcm_get_fw(bus, BRCMF_FIRMWARE_NVRAM);
3374 if (nv == NULL)
3375 return -ENOENT;
3376
3377 ret = brcmf_process_nvram_vars(bus, nv);
3378
3379 release_firmware(nv);
3380
3381 return ret;
3382 }
3383
3384 static int _brcmf_sdbrcm_download_firmware(struct brcmf_sdio *bus)
3385 {
3386 int bcmerror = -1;
3387
3388 /* Keep arm in reset */
3389 if (!brcmf_sdbrcm_download_state(bus, true)) {
3390 brcmf_err("error placing ARM core in reset\n");
3391 goto err;
3392 }
3393
3394 if (brcmf_sdbrcm_download_code_file(bus)) {
3395 brcmf_err("dongle image file download failed\n");
3396 goto err;
3397 }
3398
3399 if (brcmf_sdbrcm_download_nvram(bus)) {
3400 brcmf_err("dongle nvram file download failed\n");
3401 goto err;
3402 }
3403
3404 /* Take arm out of reset */
3405 if (!brcmf_sdbrcm_download_state(bus, false)) {
3406 brcmf_err("error getting out of ARM core reset\n");
3407 goto err;
3408 }
3409
3410 bcmerror = 0;
3411
3412 err:
3413 return bcmerror;
3414 }
3415
3416 static bool brcmf_sdbrcm_sr_capable(struct brcmf_sdio *bus)
3417 {
3418 u32 addr, reg;
3419
3420 brcmf_dbg(TRACE, "Enter\n");
3421
3422 /* old chips with PMU version less than 17 don't support save restore */
3423 if (bus->ci->pmurev < 17)
3424 return false;
3425
3426 /* read PMU chipcontrol register 3*/
3427 addr = CORE_CC_REG(bus->ci->c_inf[0].base, chipcontrol_addr);
3428 brcmf_sdio_regwl(bus->sdiodev, addr, 3, NULL);
3429 addr = CORE_CC_REG(bus->ci->c_inf[0].base, chipcontrol_data);
3430 reg = brcmf_sdio_regrl(bus->sdiodev, addr, NULL);
3431
3432 return (bool)reg;
3433 }
3434
3435 static void brcmf_sdbrcm_sr_init(struct brcmf_sdio *bus)
3436 {
3437 int err = 0;
3438 u8 val;
3439
3440 brcmf_dbg(TRACE, "Enter\n");
3441
3442 val = brcmf_sdio_regrb(bus->sdiodev, SBSDIO_FUNC1_WAKEUPCTRL,
3443 &err);
3444 if (err) {
3445 brcmf_err("error reading SBSDIO_FUNC1_WAKEUPCTRL\n");
3446 return;
3447 }
3448
3449 val |= 1 << SBSDIO_FUNC1_WCTRL_HTWAIT_SHIFT;
3450 brcmf_sdio_regwb(bus->sdiodev, SBSDIO_FUNC1_WAKEUPCTRL,
3451 val, &err);
3452 if (err) {
3453 brcmf_err("error writing SBSDIO_FUNC1_WAKEUPCTRL\n");
3454 return;
3455 }
3456
3457 /* Add CMD14 Support */
3458 brcmf_sdio_regwb(bus->sdiodev, SDIO_CCCR_BRCM_CARDCAP,
3459 (SDIO_CCCR_BRCM_CARDCAP_CMD14_SUPPORT |
3460 SDIO_CCCR_BRCM_CARDCAP_CMD14_EXT),
3461 &err);
3462 if (err) {
3463 brcmf_err("error writing SDIO_CCCR_BRCM_CARDCAP\n");
3464 return;
3465 }
3466
3467 brcmf_sdio_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
3468 SBSDIO_FORCE_HT, &err);
3469 if (err) {
3470 brcmf_err("error writing SBSDIO_FUNC1_CHIPCLKCSR\n");
3471 return;
3472 }
3473
3474 /* set flag */
3475 bus->sr_enabled = true;
3476 brcmf_dbg(INFO, "SR enabled\n");
3477 }
3478
3479 /* enable KSO bit */
3480 static int brcmf_sdbrcm_kso_init(struct brcmf_sdio *bus)
3481 {
3482 u8 val;
3483 int err = 0;
3484
3485 brcmf_dbg(TRACE, "Enter\n");
3486
3487 /* KSO bit added in SDIO core rev 12 */
3488 if (bus->ci->c_inf[1].rev < 12)
3489 return 0;
3490
3491 val = brcmf_sdio_regrb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR,
3492 &err);
3493 if (err) {
3494 brcmf_err("error reading SBSDIO_FUNC1_SLEEPCSR\n");
3495 return err;
3496 }
3497
3498 if (!(val & SBSDIO_FUNC1_SLEEPCSR_KSO_MASK)) {
3499 val |= (SBSDIO_FUNC1_SLEEPCSR_KSO_EN <<
3500 SBSDIO_FUNC1_SLEEPCSR_KSO_SHIFT);
3501 brcmf_sdio_regwb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR,
3502 val, &err);
3503 if (err) {
3504 brcmf_err("error writing SBSDIO_FUNC1_SLEEPCSR\n");
3505 return err;
3506 }
3507 }
3508
3509 return 0;
3510 }
3511
3512
3513 static bool
3514 brcmf_sdbrcm_download_firmware(struct brcmf_sdio *bus)
3515 {
3516 bool ret;
3517
3518 sdio_claim_host(bus->sdiodev->func[1]);
3519
3520 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
3521
3522 ret = _brcmf_sdbrcm_download_firmware(bus) == 0;
3523
3524 brcmf_sdbrcm_clkctl(bus, CLK_SDONLY, false);
3525
3526 sdio_release_host(bus->sdiodev->func[1]);
3527
3528 return ret;
3529 }
3530
3531 static int brcmf_sdbrcm_bus_preinit(struct device *dev)
3532 {
3533 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
3534 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
3535 struct brcmf_sdio *bus = sdiodev->bus;
3536 uint pad_size;
3537 u32 value;
3538 u8 idx;
3539 int err;
3540
3541 /* the commands below use the terms tx and rx from
3542 * a device perspective, ie. bus:txglom affects the
3543 * bus transfers from device to host.
3544 */
3545 idx = brcmf_sdio_chip_getinfidx(bus->ci, BCMA_CORE_SDIO_DEV);
3546 if (bus->ci->c_inf[idx].rev < 12) {
3547 /* for sdio core rev < 12, disable txgloming */
3548 value = 0;
3549 err = brcmf_iovar_data_set(dev, "bus:txglom", &value,
3550 sizeof(u32));
3551 } else {
3552 /* otherwise, set txglomalign */
3553 value = 4;
3554 if (sdiodev->pdata)
3555 value = sdiodev->pdata->sd_sgentry_align;
3556 /* SDIO ADMA requires at least 32 bit alignment */
3557 value = max_t(u32, value, 4);
3558 err = brcmf_iovar_data_set(dev, "bus:txglomalign", &value,
3559 sizeof(u32));
3560 }
3561
3562 if (err < 0)
3563 goto done;
3564
3565 bus->tx_hdrlen = SDPCM_HWHDR_LEN + SDPCM_SWHDR_LEN;
3566 if (sdiodev->sg_support) {
3567 bus->txglom = false;
3568 value = 1;
3569 pad_size = bus->sdiodev->func[2]->cur_blksize << 1;
3570 bus->txglom_sgpad = brcmu_pkt_buf_get_skb(pad_size);
3571 if (!bus->txglom_sgpad)
3572 brcmf_err("allocating txglom padding skb failed, reduced performance\n");
3573
3574 err = brcmf_iovar_data_set(bus->sdiodev->dev, "bus:rxglom",
3575 &value, sizeof(u32));
3576 if (err < 0) {
3577 /* bus:rxglom is allowed to fail */
3578 err = 0;
3579 } else {
3580 bus->txglom = true;
3581 bus->tx_hdrlen += SDPCM_HWEXT_LEN;
3582 }
3583 }
3584 brcmf_bus_add_txhdrlen(bus->sdiodev->dev, bus->tx_hdrlen);
3585
3586 done:
3587 return err;
3588 }
3589
3590 static int brcmf_sdbrcm_bus_init(struct device *dev)
3591 {
3592 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
3593 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
3594 struct brcmf_sdio *bus = sdiodev->bus;
3595 unsigned long timeout;
3596 u8 ready, enable;
3597 int err, ret = 0;
3598 u8 saveclk;
3599
3600 brcmf_dbg(TRACE, "Enter\n");
3601
3602 /* try to download image and nvram to the dongle */
3603 if (bus_if->state == BRCMF_BUS_DOWN) {
3604 if (!(brcmf_sdbrcm_download_firmware(bus)))
3605 return -1;
3606 }
3607
3608 if (!bus->sdiodev->bus_if->drvr)
3609 return 0;
3610
3611 /* Start the watchdog timer */
3612 bus->sdcnt.tickcnt = 0;
3613 brcmf_sdbrcm_wd_timer(bus, BRCMF_WD_POLL_MS);
3614
3615 sdio_claim_host(bus->sdiodev->func[1]);
3616
3617 /* Make sure backplane clock is on, needed to generate F2 interrupt */
3618 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
3619 if (bus->clkstate != CLK_AVAIL)
3620 goto exit;
3621
3622 /* Force clocks on backplane to be sure F2 interrupt propagates */
3623 saveclk = brcmf_sdio_regrb(bus->sdiodev,
3624 SBSDIO_FUNC1_CHIPCLKCSR, &err);
3625 if (!err) {
3626 brcmf_sdio_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
3627 (saveclk | SBSDIO_FORCE_HT), &err);
3628 }
3629 if (err) {
3630 brcmf_err("Failed to force clock for F2: err %d\n", err);
3631 goto exit;
3632 }
3633
3634 /* Enable function 2 (frame transfers) */
3635 w_sdreg32(bus, SDPCM_PROT_VERSION << SMB_DATA_VERSION_SHIFT,
3636 offsetof(struct sdpcmd_regs, tosbmailboxdata));
3637 enable = (SDIO_FUNC_ENABLE_1 | SDIO_FUNC_ENABLE_2);
3638
3639 brcmf_sdio_regwb(bus->sdiodev, SDIO_CCCR_IOEx, enable, NULL);
3640
3641 timeout = jiffies + msecs_to_jiffies(BRCMF_WAIT_F2RDY);
3642 ready = 0;
3643 while (enable != ready) {
3644 ready = brcmf_sdio_regrb(bus->sdiodev,
3645 SDIO_CCCR_IORx, NULL);
3646 if (time_after(jiffies, timeout))
3647 break;
3648 else if (time_after(jiffies, timeout - BRCMF_WAIT_F2RDY + 50))
3649 /* prevent busy waiting if it takes too long */
3650 msleep_interruptible(20);
3651 }
3652
3653 brcmf_dbg(INFO, "enable 0x%02x, ready 0x%02x\n", enable, ready);
3654
3655 /* If F2 successfully enabled, set core and enable interrupts */
3656 if (ready == enable) {
3657 /* Set up the interrupt mask and enable interrupts */
3658 bus->hostintmask = HOSTINTMASK;
3659 w_sdreg32(bus, bus->hostintmask,
3660 offsetof(struct sdpcmd_regs, hostintmask));
3661
3662 brcmf_sdio_regwb(bus->sdiodev, SBSDIO_WATERMARK, 8, &err);
3663 } else {
3664 /* Disable F2 again */
3665 enable = SDIO_FUNC_ENABLE_1;
3666 brcmf_sdio_regwb(bus->sdiodev, SDIO_CCCR_IOEx, enable, NULL);
3667 ret = -ENODEV;
3668 }
3669
3670 if (brcmf_sdbrcm_sr_capable(bus)) {
3671 brcmf_sdbrcm_sr_init(bus);
3672 } else {
3673 /* Restore previous clock setting */
3674 brcmf_sdio_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
3675 saveclk, &err);
3676 }
3677
3678 if (ret == 0) {
3679 ret = brcmf_sdio_intr_register(bus->sdiodev);
3680 if (ret != 0)
3681 brcmf_err("intr register failed:%d\n", ret);
3682 }
3683
3684 /* If we didn't come up, turn off backplane clock */
3685 if (bus_if->state != BRCMF_BUS_DATA)
3686 brcmf_sdbrcm_clkctl(bus, CLK_NONE, false);
3687
3688 exit:
3689 sdio_release_host(bus->sdiodev->func[1]);
3690
3691 return ret;
3692 }
3693
3694 void brcmf_sdbrcm_isr(void *arg)
3695 {
3696 struct brcmf_sdio *bus = (struct brcmf_sdio *) arg;
3697
3698 brcmf_dbg(TRACE, "Enter\n");
3699
3700 if (!bus) {
3701 brcmf_err("bus is null pointer, exiting\n");
3702 return;
3703 }
3704
3705 if (bus->sdiodev->bus_if->state == BRCMF_BUS_DOWN) {
3706 brcmf_err("bus is down. we have nothing to do\n");
3707 return;
3708 }
3709 /* Count the interrupt call */
3710 bus->sdcnt.intrcount++;
3711 if (in_interrupt())
3712 atomic_set(&bus->ipend, 1);
3713 else
3714 if (brcmf_sdio_intr_rstatus(bus)) {
3715 brcmf_err("failed backplane access\n");
3716 bus->sdiodev->bus_if->state = BRCMF_BUS_DOWN;
3717 }
3718
3719 /* Disable additional interrupts (is this needed now)? */
3720 if (!bus->intr)
3721 brcmf_err("isr w/o interrupt configured!\n");
3722
3723 atomic_inc(&bus->dpc_tskcnt);
3724 queue_work(bus->brcmf_wq, &bus->datawork);
3725 }
3726
3727 static bool brcmf_sdbrcm_bus_watchdog(struct brcmf_sdio *bus)
3728 {
3729 #ifdef DEBUG
3730 struct brcmf_bus *bus_if = dev_get_drvdata(bus->sdiodev->dev);
3731 #endif /* DEBUG */
3732
3733 brcmf_dbg(TIMER, "Enter\n");
3734
3735 /* Poll period: check device if appropriate. */
3736 if (!bus->sr_enabled &&
3737 bus->poll && (++bus->polltick >= bus->pollrate)) {
3738 u32 intstatus = 0;
3739
3740 /* Reset poll tick */
3741 bus->polltick = 0;
3742
3743 /* Check device if no interrupts */
3744 if (!bus->intr ||
3745 (bus->sdcnt.intrcount == bus->sdcnt.lastintrs)) {
3746
3747 if (atomic_read(&bus->dpc_tskcnt) == 0) {
3748 u8 devpend;
3749
3750 sdio_claim_host(bus->sdiodev->func[1]);
3751 devpend = brcmf_sdio_regrb(bus->sdiodev,
3752 SDIO_CCCR_INTx,
3753 NULL);
3754 sdio_release_host(bus->sdiodev->func[1]);
3755 intstatus =
3756 devpend & (INTR_STATUS_FUNC1 |
3757 INTR_STATUS_FUNC2);
3758 }
3759
3760 /* If there is something, make like the ISR and
3761 schedule the DPC */
3762 if (intstatus) {
3763 bus->sdcnt.pollcnt++;
3764 atomic_set(&bus->ipend, 1);
3765
3766 atomic_inc(&bus->dpc_tskcnt);
3767 queue_work(bus->brcmf_wq, &bus->datawork);
3768 }
3769 }
3770
3771 /* Update interrupt tracking */
3772 bus->sdcnt.lastintrs = bus->sdcnt.intrcount;
3773 }
3774 #ifdef DEBUG
3775 /* Poll for console output periodically */
3776 if (bus_if && bus_if->state == BRCMF_BUS_DATA &&
3777 bus->console_interval != 0) {
3778 bus->console.count += BRCMF_WD_POLL_MS;
3779 if (bus->console.count >= bus->console_interval) {
3780 bus->console.count -= bus->console_interval;
3781 sdio_claim_host(bus->sdiodev->func[1]);
3782 /* Make sure backplane clock is on */
3783 brcmf_sdbrcm_bus_sleep(bus, false, false);
3784 if (brcmf_sdbrcm_readconsole(bus) < 0)
3785 /* stop on error */
3786 bus->console_interval = 0;
3787 sdio_release_host(bus->sdiodev->func[1]);
3788 }
3789 }
3790 #endif /* DEBUG */
3791
3792 /* On idle timeout clear activity flag and/or turn off clock */
3793 if ((bus->idletime > 0) && (bus->clkstate == CLK_AVAIL)) {
3794 if (++bus->idlecount >= bus->idletime) {
3795 bus->idlecount = 0;
3796 if (bus->activity) {
3797 bus->activity = false;
3798 brcmf_sdbrcm_wd_timer(bus, BRCMF_WD_POLL_MS);
3799 } else {
3800 brcmf_dbg(SDIO, "idle\n");
3801 sdio_claim_host(bus->sdiodev->func[1]);
3802 brcmf_sdbrcm_bus_sleep(bus, true, false);
3803 sdio_release_host(bus->sdiodev->func[1]);
3804 }
3805 }
3806 }
3807
3808 return (atomic_read(&bus->ipend) > 0);
3809 }
3810
3811 static void brcmf_sdio_dataworker(struct work_struct *work)
3812 {
3813 struct brcmf_sdio *bus = container_of(work, struct brcmf_sdio,
3814 datawork);
3815
3816 while (atomic_read(&bus->dpc_tskcnt)) {
3817 brcmf_sdbrcm_dpc(bus);
3818 atomic_dec(&bus->dpc_tskcnt);
3819 }
3820 }
3821
3822 static void brcmf_sdbrcm_release_malloc(struct brcmf_sdio *bus)
3823 {
3824 brcmf_dbg(TRACE, "Enter\n");
3825
3826 kfree(bus->rxbuf);
3827 bus->rxctl = bus->rxbuf = NULL;
3828 bus->rxlen = 0;
3829 }
3830
3831 static bool brcmf_sdbrcm_probe_malloc(struct brcmf_sdio *bus)
3832 {
3833 brcmf_dbg(TRACE, "Enter\n");
3834
3835 if (bus->sdiodev->bus_if->maxctl) {
3836 bus->rxblen =
3837 roundup((bus->sdiodev->bus_if->maxctl + SDPCM_HDRLEN),
3838 ALIGNMENT) + BRCMF_SDALIGN;
3839 bus->rxbuf = kmalloc(bus->rxblen, GFP_ATOMIC);
3840 if (!(bus->rxbuf))
3841 return false;
3842 }
3843
3844 return true;
3845 }
3846
3847 static bool
3848 brcmf_sdbrcm_probe_attach(struct brcmf_sdio *bus, u32 regsva)
3849 {
3850 u8 clkctl = 0;
3851 int err = 0;
3852 int reg_addr;
3853 u32 reg_val;
3854 u32 drivestrength;
3855
3856 bus->alp_only = true;
3857
3858 sdio_claim_host(bus->sdiodev->func[1]);
3859
3860 pr_debug("F1 signature read @0x18000000=0x%4x\n",
3861 brcmf_sdio_regrl(bus->sdiodev, SI_ENUM_BASE, NULL));
3862
3863 /*
3864 * Force PLL off until brcmf_sdio_chip_attach()
3865 * programs PLL control regs
3866 */
3867
3868 brcmf_sdio_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
3869 BRCMF_INIT_CLKCTL1, &err);
3870 if (!err)
3871 clkctl = brcmf_sdio_regrb(bus->sdiodev,
3872 SBSDIO_FUNC1_CHIPCLKCSR, &err);
3873
3874 if (err || ((clkctl & ~SBSDIO_AVBITS) != BRCMF_INIT_CLKCTL1)) {
3875 brcmf_err("ChipClkCSR access: err %d wrote 0x%02x read 0x%02x\n",
3876 err, BRCMF_INIT_CLKCTL1, clkctl);
3877 goto fail;
3878 }
3879
3880 if (brcmf_sdio_chip_attach(bus->sdiodev, &bus->ci, regsva)) {
3881 brcmf_err("brcmf_sdio_chip_attach failed!\n");
3882 goto fail;
3883 }
3884
3885 if (brcmf_sdbrcm_kso_init(bus)) {
3886 brcmf_err("error enabling KSO\n");
3887 goto fail;
3888 }
3889
3890 if ((bus->sdiodev->pdata) && (bus->sdiodev->pdata->drive_strength))
3891 drivestrength = bus->sdiodev->pdata->drive_strength;
3892 else
3893 drivestrength = DEFAULT_SDIO_DRIVE_STRENGTH;
3894 brcmf_sdio_chip_drivestrengthinit(bus->sdiodev, bus->ci, drivestrength);
3895
3896 /* Get info on the SOCRAM cores... */
3897 bus->ramsize = bus->ci->ramsize;
3898 if (!(bus->ramsize)) {
3899 brcmf_err("failed to find SOCRAM memory!\n");
3900 goto fail;
3901 }
3902
3903 /* Set card control so an SDIO card reset does a WLAN backplane reset */
3904 reg_val = brcmf_sdio_regrb(bus->sdiodev,
3905 SDIO_CCCR_BRCM_CARDCTRL, &err);
3906 if (err)
3907 goto fail;
3908
3909 reg_val |= SDIO_CCCR_BRCM_CARDCTRL_WLANRESET;
3910
3911 brcmf_sdio_regwb(bus->sdiodev,
3912 SDIO_CCCR_BRCM_CARDCTRL, reg_val, &err);
3913 if (err)
3914 goto fail;
3915
3916 /* set PMUControl so a backplane reset does PMU state reload */
3917 reg_addr = CORE_CC_REG(bus->ci->c_inf[0].base,
3918 pmucontrol);
3919 reg_val = brcmf_sdio_regrl(bus->sdiodev,
3920 reg_addr,
3921 &err);
3922 if (err)
3923 goto fail;
3924
3925 reg_val |= (BCMA_CC_PMU_CTL_RES_RELOAD << BCMA_CC_PMU_CTL_RES_SHIFT);
3926
3927 brcmf_sdio_regwl(bus->sdiodev,
3928 reg_addr,
3929 reg_val,
3930 &err);
3931 if (err)
3932 goto fail;
3933
3934
3935 sdio_release_host(bus->sdiodev->func[1]);
3936
3937 brcmu_pktq_init(&bus->txq, (PRIOMASK + 1), TXQLEN);
3938
3939 /* Locate an appropriately-aligned portion of hdrbuf */
3940 bus->rxhdr = (u8 *) roundup((unsigned long)&bus->hdrbuf[0],
3941 BRCMF_SDALIGN);
3942
3943 /* Set the poll and/or interrupt flags */
3944 bus->intr = true;
3945 bus->poll = false;
3946 if (bus->poll)
3947 bus->pollrate = 1;
3948
3949 return true;
3950
3951 fail:
3952 sdio_release_host(bus->sdiodev->func[1]);
3953 return false;
3954 }
3955
3956 static bool brcmf_sdbrcm_probe_init(struct brcmf_sdio *bus)
3957 {
3958 brcmf_dbg(TRACE, "Enter\n");
3959
3960 sdio_claim_host(bus->sdiodev->func[1]);
3961
3962 /* Disable F2 to clear any intermediate frame state on the dongle */
3963 brcmf_sdio_regwb(bus->sdiodev, SDIO_CCCR_IOEx,
3964 SDIO_FUNC_ENABLE_1, NULL);
3965
3966 bus->sdiodev->bus_if->state = BRCMF_BUS_DOWN;
3967 bus->rxflow = false;
3968
3969 /* Done with backplane-dependent accesses, can drop clock... */
3970 brcmf_sdio_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL);
3971
3972 sdio_release_host(bus->sdiodev->func[1]);
3973
3974 /* ...and initialize clock/power states */
3975 bus->clkstate = CLK_SDONLY;
3976 bus->idletime = BRCMF_IDLE_INTERVAL;
3977 bus->idleclock = BRCMF_IDLE_ACTIVE;
3978
3979 /* Query the F2 block size, set roundup accordingly */
3980 bus->blocksize = bus->sdiodev->func[2]->cur_blksize;
3981 bus->roundup = min(max_roundup, bus->blocksize);
3982
3983 /* SR state */
3984 bus->sleeping = false;
3985 bus->sr_enabled = false;
3986
3987 return true;
3988 }
3989
3990 static int
3991 brcmf_sdbrcm_watchdog_thread(void *data)
3992 {
3993 struct brcmf_sdio *bus = (struct brcmf_sdio *)data;
3994
3995 allow_signal(SIGTERM);
3996 /* Run until signal received */
3997 while (1) {
3998 if (kthread_should_stop())
3999 break;
4000 if (!wait_for_completion_interruptible(&bus->watchdog_wait)) {
4001 brcmf_sdbrcm_bus_watchdog(bus);
4002 /* Count the tick for reference */
4003 bus->sdcnt.tickcnt++;
4004 } else
4005 break;
4006 }
4007 return 0;
4008 }
4009
4010 static void
4011 brcmf_sdbrcm_watchdog(unsigned long data)
4012 {
4013 struct brcmf_sdio *bus = (struct brcmf_sdio *)data;
4014
4015 if (bus->watchdog_tsk) {
4016 complete(&bus->watchdog_wait);
4017 /* Reschedule the watchdog */
4018 if (bus->wd_timer_valid)
4019 mod_timer(&bus->timer,
4020 jiffies + BRCMF_WD_POLL_MS * HZ / 1000);
4021 }
4022 }
4023
4024 static void brcmf_sdbrcm_release_dongle(struct brcmf_sdio *bus)
4025 {
4026 brcmf_dbg(TRACE, "Enter\n");
4027
4028 if (bus->ci) {
4029 sdio_claim_host(bus->sdiodev->func[1]);
4030 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
4031 brcmf_sdbrcm_clkctl(bus, CLK_NONE, false);
4032 sdio_release_host(bus->sdiodev->func[1]);
4033 brcmf_sdio_chip_detach(&bus->ci);
4034 if (bus->vars && bus->varsz)
4035 kfree(bus->vars);
4036 bus->vars = NULL;
4037 }
4038
4039 brcmf_dbg(TRACE, "Disconnected\n");
4040 }
4041
4042 /* Detach and free everything */
4043 static void brcmf_sdbrcm_release(struct brcmf_sdio *bus)
4044 {
4045 brcmf_dbg(TRACE, "Enter\n");
4046
4047 if (bus) {
4048 /* De-register interrupt handler */
4049 brcmf_sdio_intr_unregister(bus->sdiodev);
4050
4051 cancel_work_sync(&bus->datawork);
4052 if (bus->brcmf_wq)
4053 destroy_workqueue(bus->brcmf_wq);
4054
4055 if (bus->sdiodev->bus_if->drvr) {
4056 brcmf_detach(bus->sdiodev->dev);
4057 brcmf_sdbrcm_release_dongle(bus);
4058 }
4059
4060 brcmu_pkt_buf_free_skb(bus->txglom_sgpad);
4061 brcmf_sdbrcm_release_malloc(bus);
4062
4063 kfree(bus);
4064 }
4065
4066 brcmf_dbg(TRACE, "Disconnected\n");
4067 }
4068
4069 static struct brcmf_bus_ops brcmf_sdio_bus_ops = {
4070 .stop = brcmf_sdbrcm_bus_stop,
4071 .preinit = brcmf_sdbrcm_bus_preinit,
4072 .init = brcmf_sdbrcm_bus_init,
4073 .txdata = brcmf_sdbrcm_bus_txdata,
4074 .txctl = brcmf_sdbrcm_bus_txctl,
4075 .rxctl = brcmf_sdbrcm_bus_rxctl,
4076 .gettxq = brcmf_sdbrcm_bus_gettxq,
4077 };
4078
4079 void *brcmf_sdbrcm_probe(u32 regsva, struct brcmf_sdio_dev *sdiodev)
4080 {
4081 int ret;
4082 struct brcmf_sdio *bus;
4083
4084 brcmf_dbg(TRACE, "Enter\n");
4085
4086 /* We make an assumption about address window mappings:
4087 * regsva == SI_ENUM_BASE*/
4088
4089 /* Allocate private bus interface state */
4090 bus = kzalloc(sizeof(struct brcmf_sdio), GFP_ATOMIC);
4091 if (!bus)
4092 goto fail;
4093
4094 bus->sdiodev = sdiodev;
4095 sdiodev->bus = bus;
4096 skb_queue_head_init(&bus->glom);
4097 bus->txbound = BRCMF_TXBOUND;
4098 bus->rxbound = BRCMF_RXBOUND;
4099 bus->txminmax = BRCMF_TXMINMAX;
4100 bus->tx_seq = SDPCM_SEQ_WRAP - 1;
4101
4102 INIT_WORK(&bus->datawork, brcmf_sdio_dataworker);
4103 bus->brcmf_wq = create_singlethread_workqueue("brcmf_wq");
4104 if (bus->brcmf_wq == NULL) {
4105 brcmf_err("insufficient memory to create txworkqueue\n");
4106 goto fail;
4107 }
4108
4109 /* attempt to attach to the dongle */
4110 if (!(brcmf_sdbrcm_probe_attach(bus, regsva))) {
4111 brcmf_err("brcmf_sdbrcm_probe_attach failed\n");
4112 goto fail;
4113 }
4114
4115 spin_lock_init(&bus->rxctl_lock);
4116 spin_lock_init(&bus->txqlock);
4117 init_waitqueue_head(&bus->ctrl_wait);
4118 init_waitqueue_head(&bus->dcmd_resp_wait);
4119
4120 /* Set up the watchdog timer */
4121 init_timer(&bus->timer);
4122 bus->timer.data = (unsigned long)bus;
4123 bus->timer.function = brcmf_sdbrcm_watchdog;
4124
4125 /* Initialize watchdog thread */
4126 init_completion(&bus->watchdog_wait);
4127 bus->watchdog_tsk = kthread_run(brcmf_sdbrcm_watchdog_thread,
4128 bus, "brcmf_watchdog");
4129 if (IS_ERR(bus->watchdog_tsk)) {
4130 pr_warn("brcmf_watchdog thread failed to start\n");
4131 bus->watchdog_tsk = NULL;
4132 }
4133 /* Initialize DPC thread */
4134 atomic_set(&bus->dpc_tskcnt, 0);
4135
4136 /* Assign bus interface call back */
4137 bus->sdiodev->bus_if->dev = bus->sdiodev->dev;
4138 bus->sdiodev->bus_if->ops = &brcmf_sdio_bus_ops;
4139 bus->sdiodev->bus_if->chip = bus->ci->chip;
4140 bus->sdiodev->bus_if->chiprev = bus->ci->chiprev;
4141
4142 /* default sdio bus header length for tx packet */
4143 bus->tx_hdrlen = SDPCM_HWHDR_LEN + SDPCM_SWHDR_LEN;
4144
4145 /* Attach to the common layer, reserve hdr space */
4146 ret = brcmf_attach(bus->sdiodev->dev);
4147 if (ret != 0) {
4148 brcmf_err("brcmf_attach failed\n");
4149 goto fail;
4150 }
4151
4152 /* Allocate buffers */
4153 if (!(brcmf_sdbrcm_probe_malloc(bus))) {
4154 brcmf_err("brcmf_sdbrcm_probe_malloc failed\n");
4155 goto fail;
4156 }
4157
4158 if (!(brcmf_sdbrcm_probe_init(bus))) {
4159 brcmf_err("brcmf_sdbrcm_probe_init failed\n");
4160 goto fail;
4161 }
4162
4163 brcmf_sdio_debugfs_create(bus);
4164 brcmf_dbg(INFO, "completed!!\n");
4165
4166 /* if firmware path present try to download and bring up bus */
4167 ret = brcmf_bus_start(bus->sdiodev->dev);
4168 if (ret != 0) {
4169 brcmf_err("dongle is not responding\n");
4170 goto fail;
4171 }
4172
4173 return bus;
4174
4175 fail:
4176 brcmf_sdbrcm_release(bus);
4177 return NULL;
4178 }
4179
4180 void brcmf_sdbrcm_disconnect(void *ptr)
4181 {
4182 struct brcmf_sdio *bus = (struct brcmf_sdio *)ptr;
4183
4184 brcmf_dbg(TRACE, "Enter\n");
4185
4186 if (bus)
4187 brcmf_sdbrcm_release(bus);
4188
4189 brcmf_dbg(TRACE, "Disconnected\n");
4190 }
4191
4192 void
4193 brcmf_sdbrcm_wd_timer(struct brcmf_sdio *bus, uint wdtick)
4194 {
4195 /* Totally stop the timer */
4196 if (!wdtick && bus->wd_timer_valid) {
4197 del_timer_sync(&bus->timer);
4198 bus->wd_timer_valid = false;
4199 bus->save_ms = wdtick;
4200 return;
4201 }
4202
4203 /* don't start the wd until fw is loaded */
4204 if (bus->sdiodev->bus_if->state == BRCMF_BUS_DOWN)
4205 return;
4206
4207 if (wdtick) {
4208 if (bus->save_ms != BRCMF_WD_POLL_MS) {
4209 if (bus->wd_timer_valid)
4210 /* Stop timer and restart at new value */
4211 del_timer_sync(&bus->timer);
4212
4213 /* Create timer again when watchdog period is
4214 dynamically changed or in the first instance
4215 */
4216 bus->timer.expires =
4217 jiffies + BRCMF_WD_POLL_MS * HZ / 1000;
4218 add_timer(&bus->timer);
4219
4220 } else {
4221 /* Re arm the timer, at last watchdog period */
4222 mod_timer(&bus->timer,
4223 jiffies + BRCMF_WD_POLL_MS * HZ / 1000);
4224 }
4225
4226 bus->wd_timer_valid = true;
4227 bus->save_ms = wdtick;
4228 }
4229 }
Linux kernel - Deliverables
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