projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Merge git://github.com/rustyrussell/linux
[deliverable/linux.git] / drivers / net / wireless / brcm80211 / brcmfmac / dhd_sdio.c
1 /*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/types.h>
18 #include <linux/kernel.h>
19 #include <linux/kthread.h>
20 #include <linux/printk.h>
21 #include <linux/pci_ids.h>
22 #include <linux/netdevice.h>
23 #include <linux/interrupt.h>
24 #include <linux/sched.h>
25 #include <linux/mmc/sdio.h>
26 #include <linux/mmc/sdio_func.h>
27 #include <linux/mmc/card.h>
28 #include <linux/semaphore.h>
29 #include <linux/firmware.h>
30 #include <linux/module.h>
31 #include <asm/unaligned.h>
32 #include <defs.h>
33 #include <brcmu_wifi.h>
34 #include <brcmu_utils.h>
35 #include <brcm_hw_ids.h>
36 #include <soc.h>
37 #include "sdio_host.h"
38
39 #define DCMD_RESP_TIMEOUT 2000 /* In milli second */
40
41 #ifdef BCMDBG
42
43 #define BRCMF_TRAP_INFO_SIZE 80
44
45 #define CBUF_LEN (128)
46
47 struct rte_log_le {
48 __le32 buf; /* Can't be pointer on (64-bit) hosts */
49 __le32 buf_size;
50 __le32 idx;
51 char *_buf_compat; /* Redundant pointer for backward compat. */
52 };
53
54 struct rte_console {
55 /* Virtual UART
56 * When there is no UART (e.g. Quickturn),
57 * the host should write a complete
58 * input line directly into cbuf and then write
59 * the length into vcons_in.
60 * This may also be used when there is a real UART
61 * (at risk of conflicting with
62 * the real UART). vcons_out is currently unused.
63 */
64 uint vcons_in;
65 uint vcons_out;
66
67 /* Output (logging) buffer
68 * Console output is written to a ring buffer log_buf at index log_idx.
69 * The host may read the output when it sees log_idx advance.
70 * Output will be lost if the output wraps around faster than the host
71 * polls.
72 */
73 struct rte_log_le log_le;
74
75 /* Console input line buffer
76 * Characters are read one at a time into cbuf
77 * until <CR> is received, then
78 * the buffer is processed as a command line.
79 * Also used for virtual UART.
80 */
81 uint cbuf_idx;
82 char cbuf[CBUF_LEN];
83 };
84
85 #endif /* BCMDBG */
86 #include <chipcommon.h>
87
88 #include "dhd.h"
89 #include "dhd_bus.h"
90 #include "dhd_proto.h"
91 #include "dhd_dbg.h"
92 #include <bcmchip.h>
93
94 #define TXQLEN 2048 /* bulk tx queue length */
95 #define TXHI (TXQLEN - 256) /* turn on flow control above TXHI */
96 #define TXLOW (TXHI - 256) /* turn off flow control below TXLOW */
97 #define PRIOMASK 7
98
99 #define TXRETRIES 2 /* # of retries for tx frames */
100
101 #define BRCMF_RXBOUND 50 /* Default for max rx frames in
102 one scheduling */
103
104 #define BRCMF_TXBOUND 20 /* Default for max tx frames in
105 one scheduling */
106
107 #define BRCMF_TXMINMAX 1 /* Max tx frames if rx still pending */
108
109 #define MEMBLOCK 2048 /* Block size used for downloading
110 of dongle image */
111 #define MAX_DATA_BUF (32 * 1024) /* Must be large enough to hold
112 biggest possible glom */
113
114 #define BRCMF_FIRSTREAD (1 << 6)
115
116
117 /* SBSDIO_DEVICE_CTL */
118
119 /* 1: device will assert busy signal when receiving CMD53 */
120 #define SBSDIO_DEVCTL_SETBUSY 0x01
121 /* 1: assertion of sdio interrupt is synchronous to the sdio clock */
122 #define SBSDIO_DEVCTL_SPI_INTR_SYNC 0x02
123 /* 1: mask all interrupts to host except the chipActive (rev 8) */
124 #define SBSDIO_DEVCTL_CA_INT_ONLY 0x04
125 /* 1: isolate internal sdio signals, put external pads in tri-state; requires
126 * sdio bus power cycle to clear (rev 9) */
127 #define SBSDIO_DEVCTL_PADS_ISO 0x08
128 /* Force SD->SB reset mapping (rev 11) */
129 #define SBSDIO_DEVCTL_SB_RST_CTL 0x30
130 /* Determined by CoreControl bit */
131 #define SBSDIO_DEVCTL_RST_CORECTL 0x00
132 /* Force backplane reset */
133 #define SBSDIO_DEVCTL_RST_BPRESET 0x10
134 /* Force no backplane reset */
135 #define SBSDIO_DEVCTL_RST_NOBPRESET 0x20
136
137 /* SBSDIO_FUNC1_CHIPCLKCSR */
138
139 /* Force ALP request to backplane */
140 #define SBSDIO_FORCE_ALP 0x01
141 /* Force HT request to backplane */
142 #define SBSDIO_FORCE_HT 0x02
143 /* Force ILP request to backplane */
144 #define SBSDIO_FORCE_ILP 0x04
145 /* Make ALP ready (power up xtal) */
146 #define SBSDIO_ALP_AVAIL_REQ 0x08
147 /* Make HT ready (power up PLL) */
148 #define SBSDIO_HT_AVAIL_REQ 0x10
149 /* Squelch clock requests from HW */
150 #define SBSDIO_FORCE_HW_CLKREQ_OFF 0x20
151 /* Status: ALP is ready */
152 #define SBSDIO_ALP_AVAIL 0x40
153 /* Status: HT is ready */
154 #define SBSDIO_HT_AVAIL 0x80
155
156 #define SBSDIO_AVBITS (SBSDIO_HT_AVAIL | SBSDIO_ALP_AVAIL)
157 #define SBSDIO_ALPAV(regval) ((regval) & SBSDIO_AVBITS)
158 #define SBSDIO_HTAV(regval) (((regval) & SBSDIO_AVBITS) == SBSDIO_AVBITS)
159 #define SBSDIO_ALPONLY(regval) (SBSDIO_ALPAV(regval) && !SBSDIO_HTAV(regval))
160
161 #define SBSDIO_CLKAV(regval, alponly) \
162 (SBSDIO_ALPAV(regval) && (alponly ? 1 : SBSDIO_HTAV(regval)))
163
164 /* direct(mapped) cis space */
165
166 /* MAPPED common CIS address */
167 #define SBSDIO_CIS_BASE_COMMON 0x1000
168 /* maximum bytes in one CIS */
169 #define SBSDIO_CIS_SIZE_LIMIT 0x200
170 /* cis offset addr is < 17 bits */
171 #define SBSDIO_CIS_OFT_ADDR_MASK 0x1FFFF
172
173 /* manfid tuple length, include tuple, link bytes */
174 #define SBSDIO_CIS_MANFID_TUPLE_LEN 6
175
176 /* intstatus */
177 #define I_SMB_SW0 (1 << 0) /* To SB Mail S/W interrupt 0 */
178 #define I_SMB_SW1 (1 << 1) /* To SB Mail S/W interrupt 1 */
179 #define I_SMB_SW2 (1 << 2) /* To SB Mail S/W interrupt 2 */
180 #define I_SMB_SW3 (1 << 3) /* To SB Mail S/W interrupt 3 */
181 #define I_SMB_SW_MASK 0x0000000f /* To SB Mail S/W interrupts mask */
182 #define I_SMB_SW_SHIFT 0 /* To SB Mail S/W interrupts shift */
183 #define I_HMB_SW0 (1 << 4) /* To Host Mail S/W interrupt 0 */
184 #define I_HMB_SW1 (1 << 5) /* To Host Mail S/W interrupt 1 */
185 #define I_HMB_SW2 (1 << 6) /* To Host Mail S/W interrupt 2 */
186 #define I_HMB_SW3 (1 << 7) /* To Host Mail S/W interrupt 3 */
187 #define I_HMB_SW_MASK 0x000000f0 /* To Host Mail S/W interrupts mask */
188 #define I_HMB_SW_SHIFT 4 /* To Host Mail S/W interrupts shift */
189 #define I_WR_OOSYNC (1 << 8) /* Write Frame Out Of Sync */
190 #define I_RD_OOSYNC (1 << 9) /* Read Frame Out Of Sync */
191 #define I_PC (1 << 10) /* descriptor error */
192 #define I_PD (1 << 11) /* data error */
193 #define I_DE (1 << 12) /* Descriptor protocol Error */
194 #define I_RU (1 << 13) /* Receive descriptor Underflow */
195 #define I_RO (1 << 14) /* Receive fifo Overflow */
196 #define I_XU (1 << 15) /* Transmit fifo Underflow */
197 #define I_RI (1 << 16) /* Receive Interrupt */
198 #define I_BUSPWR (1 << 17) /* SDIO Bus Power Change (rev 9) */
199 #define I_XMTDATA_AVAIL (1 << 23) /* bits in fifo */
200 #define I_XI (1 << 24) /* Transmit Interrupt */
201 #define I_RF_TERM (1 << 25) /* Read Frame Terminate */
202 #define I_WF_TERM (1 << 26) /* Write Frame Terminate */
203 #define I_PCMCIA_XU (1 << 27) /* PCMCIA Transmit FIFO Underflow */
204 #define I_SBINT (1 << 28) /* sbintstatus Interrupt */
205 #define I_CHIPACTIVE (1 << 29) /* chip from doze to active state */
206 #define I_SRESET (1 << 30) /* CCCR RES interrupt */
207 #define I_IOE2 (1U << 31) /* CCCR IOE2 Bit Changed */
208 #define I_ERRORS (I_PC | I_PD | I_DE | I_RU | I_RO | I_XU)
209 #define I_DMA (I_RI | I_XI | I_ERRORS)
210
211 /* corecontrol */
212 #define CC_CISRDY (1 << 0) /* CIS Ready */
213 #define CC_BPRESEN (1 << 1) /* CCCR RES signal */
214 #define CC_F2RDY (1 << 2) /* set CCCR IOR2 bit */
215 #define CC_CLRPADSISO (1 << 3) /* clear SDIO pads isolation */
216 #define CC_XMTDATAAVAIL_MODE (1 << 4)
217 #define CC_XMTDATAAVAIL_CTRL (1 << 5)
218
219 /* SDA_FRAMECTRL */
220 #define SFC_RF_TERM (1 << 0) /* Read Frame Terminate */
221 #define SFC_WF_TERM (1 << 1) /* Write Frame Terminate */
222 #define SFC_CRC4WOOS (1 << 2) /* CRC error for write out of sync */
223 #define SFC_ABORTALL (1 << 3) /* Abort all in-progress frames */
224
225 /* HW frame tag */
226 #define SDPCM_FRAMETAG_LEN 4 /* 2 bytes len, 2 bytes check val */
227
228 /* Total length of frame header for dongle protocol */
229 #define SDPCM_HDRLEN (SDPCM_FRAMETAG_LEN + SDPCM_SWHEADER_LEN)
230 #define SDPCM_RESERVE (SDPCM_HDRLEN + BRCMF_SDALIGN)
231
232 /*
233 * Software allocation of To SB Mailbox resources
234 */
235
236 /* tosbmailbox bits corresponding to intstatus bits */
237 #define SMB_NAK (1 << 0) /* Frame NAK */
238 #define SMB_INT_ACK (1 << 1) /* Host Interrupt ACK */
239 #define SMB_USE_OOB (1 << 2) /* Use OOB Wakeup */
240 #define SMB_DEV_INT (1 << 3) /* Miscellaneous Interrupt */
241
242 /* tosbmailboxdata */
243 #define SMB_DATA_VERSION_SHIFT 16 /* host protocol version */
244
245 /*
246 * Software allocation of To Host Mailbox resources
247 */
248
249 /* intstatus bits */
250 #define I_HMB_FC_STATE I_HMB_SW0 /* Flow Control State */
251 #define I_HMB_FC_CHANGE I_HMB_SW1 /* Flow Control State Changed */
252 #define I_HMB_FRAME_IND I_HMB_SW2 /* Frame Indication */
253 #define I_HMB_HOST_INT I_HMB_SW3 /* Miscellaneous Interrupt */
254
255 /* tohostmailboxdata */
256 #define HMB_DATA_NAKHANDLED 1 /* retransmit NAK'd frame */
257 #define HMB_DATA_DEVREADY 2 /* talk to host after enable */
258 #define HMB_DATA_FC 4 /* per prio flowcontrol update flag */
259 #define HMB_DATA_FWREADY 8 /* fw ready for protocol activity */
260
261 #define HMB_DATA_FCDATA_MASK 0xff000000
262 #define HMB_DATA_FCDATA_SHIFT 24
263
264 #define HMB_DATA_VERSION_MASK 0x00ff0000
265 #define HMB_DATA_VERSION_SHIFT 16
266
267 /*
268 * Software-defined protocol header
269 */
270
271 /* Current protocol version */
272 #define SDPCM_PROT_VERSION 4
273
274 /* SW frame header */
275 #define SDPCM_PACKET_SEQUENCE(p) (((u8 *)p)[0] & 0xff)
276
277 #define SDPCM_CHANNEL_MASK 0x00000f00
278 #define SDPCM_CHANNEL_SHIFT 8
279 #define SDPCM_PACKET_CHANNEL(p) (((u8 *)p)[1] & 0x0f)
280
281 #define SDPCM_NEXTLEN_OFFSET 2
282
283 /* Data Offset from SOF (HW Tag, SW Tag, Pad) */
284 #define SDPCM_DOFFSET_OFFSET 3 /* Data Offset */
285 #define SDPCM_DOFFSET_VALUE(p) (((u8 *)p)[SDPCM_DOFFSET_OFFSET] & 0xff)
286 #define SDPCM_DOFFSET_MASK 0xff000000
287 #define SDPCM_DOFFSET_SHIFT 24
288 #define SDPCM_FCMASK_OFFSET 4 /* Flow control */
289 #define SDPCM_FCMASK_VALUE(p) (((u8 *)p)[SDPCM_FCMASK_OFFSET] & 0xff)
290 #define SDPCM_WINDOW_OFFSET 5 /* Credit based fc */
291 #define SDPCM_WINDOW_VALUE(p) (((u8 *)p)[SDPCM_WINDOW_OFFSET] & 0xff)
292
293 #define SDPCM_SWHEADER_LEN 8 /* SW header is 64 bits */
294
295 /* logical channel numbers */
296 #define SDPCM_CONTROL_CHANNEL 0 /* Control channel Id */
297 #define SDPCM_EVENT_CHANNEL 1 /* Asyc Event Indication Channel Id */
298 #define SDPCM_DATA_CHANNEL 2 /* Data Xmit/Recv Channel Id */
299 #define SDPCM_GLOM_CHANNEL 3 /* For coalesced packets */
300 #define SDPCM_TEST_CHANNEL 15 /* Reserved for test/debug packets */
301
302 #define SDPCM_SEQUENCE_WRAP 256 /* wrap-around val for 8bit frame seq */
303
304 #define SDPCM_GLOMDESC(p) (((u8 *)p)[1] & 0x80)
305
306 /*
307 * Shared structure between dongle and the host.
308 * The structure contains pointers to trap or assert information.
309 */
310 #define SDPCM_SHARED_VERSION 0x0002
311 #define SDPCM_SHARED_VERSION_MASK 0x00FF
312 #define SDPCM_SHARED_ASSERT_BUILT 0x0100
313 #define SDPCM_SHARED_ASSERT 0x0200
314 #define SDPCM_SHARED_TRAP 0x0400
315
316 /* Space for header read, limit for data packets */
317 #define MAX_HDR_READ (1 << 6)
318 #define MAX_RX_DATASZ 2048
319
320 /* Maximum milliseconds to wait for F2 to come up */
321 #define BRCMF_WAIT_F2RDY 3000
322
323 /* Bump up limit on waiting for HT to account for first startup;
324 * if the image is doing a CRC calculation before programming the PMU
325 * for HT availability, it could take a couple hundred ms more, so
326 * max out at a 1 second (1000000us).
327 */
328 #undef PMU_MAX_TRANSITION_DLY
329 #define PMU_MAX_TRANSITION_DLY 1000000
330
331 /* Value for ChipClockCSR during initial setup */
332 #define BRCMF_INIT_CLKCTL1 (SBSDIO_FORCE_HW_CLKREQ_OFF | \
333 SBSDIO_ALP_AVAIL_REQ)
334
335 /* Flags for SDH calls */
336 #define F2SYNC (SDIO_REQ_4BYTE | SDIO_REQ_FIXED)
337
338 /* sbimstate */
339 #define SBIM_IBE 0x20000 /* inbanderror */
340 #define SBIM_TO 0x40000 /* timeout */
341 #define SBIM_BY 0x01800000 /* busy (sonics >= 2.3) */
342 #define SBIM_RJ 0x02000000 /* reject (sonics >= 2.3) */
343
344 /* sbtmstatelow */
345
346 /* reset */
347 #define SBTML_RESET 0x0001
348 /* reject field */
349 #define SBTML_REJ_MASK 0x0006
350 /* reject */
351 #define SBTML_REJ 0x0002
352 /* temporary reject, for error recovery */
353 #define SBTML_TMPREJ 0x0004
354
355 /* Shift to locate the SI control flags in sbtml */
356 #define SBTML_SICF_SHIFT 16
357
358 /* sbtmstatehigh */
359 #define SBTMH_SERR 0x0001 /* serror */
360 #define SBTMH_INT 0x0002 /* interrupt */
361 #define SBTMH_BUSY 0x0004 /* busy */
362 #define SBTMH_TO 0x0020 /* timeout (sonics >= 2.3) */
363
364 /* Shift to locate the SI status flags in sbtmh */
365 #define SBTMH_SISF_SHIFT 16
366
367 /* sbidlow */
368 #define SBIDL_INIT 0x80 /* initiator */
369
370 /* sbidhigh */
371 #define SBIDH_RC_MASK 0x000f /* revision code */
372 #define SBIDH_RCE_MASK 0x7000 /* revision code extension field */
373 #define SBIDH_RCE_SHIFT 8
374 #define SBCOREREV(sbidh) \
375 ((((sbidh) & SBIDH_RCE_MASK) >> SBIDH_RCE_SHIFT) | \
376 ((sbidh) & SBIDH_RC_MASK))
377 #define SBIDH_CC_MASK 0x8ff0 /* core code */
378 #define SBIDH_CC_SHIFT 4
379 #define SBIDH_VC_MASK 0xffff0000 /* vendor code */
380 #define SBIDH_VC_SHIFT 16
381
382 /*
383 * Conversion of 802.1D priority to precedence level
384 */
385 static uint prio2prec(u32 prio)
386 {
387 return (prio == PRIO_8021D_NONE || prio == PRIO_8021D_BE) ?
388 (prio^2) : prio;
389 }
390
391 /*
392 * Core reg address translation.
393 * Both macro's returns a 32 bits byte address on the backplane bus.
394 */
395 #define CORE_CC_REG(base, field) \
396 (base + offsetof(struct chipcregs, field))
397 #define CORE_BUS_REG(base, field) \
398 (base + offsetof(struct sdpcmd_regs, field))
399 #define CORE_SB(base, field) \
400 (base + SBCONFIGOFF + offsetof(struct sbconfig, field))
401
402 /* core registers */
403 struct sdpcmd_regs {
404 u32 corecontrol; /* 0x00, rev8 */
405 u32 corestatus; /* rev8 */
406 u32 PAD[1];
407 u32 biststatus; /* rev8 */
408
409 /* PCMCIA access */
410 u16 pcmciamesportaladdr; /* 0x010, rev8 */
411 u16 PAD[1];
412 u16 pcmciamesportalmask; /* rev8 */
413 u16 PAD[1];
414 u16 pcmciawrframebc; /* rev8 */
415 u16 PAD[1];
416 u16 pcmciaunderflowtimer; /* rev8 */
417 u16 PAD[1];
418
419 /* interrupt */
420 u32 intstatus; /* 0x020, rev8 */
421 u32 hostintmask; /* rev8 */
422 u32 intmask; /* rev8 */
423 u32 sbintstatus; /* rev8 */
424 u32 sbintmask; /* rev8 */
425 u32 funcintmask; /* rev4 */
426 u32 PAD[2];
427 u32 tosbmailbox; /* 0x040, rev8 */
428 u32 tohostmailbox; /* rev8 */
429 u32 tosbmailboxdata; /* rev8 */
430 u32 tohostmailboxdata; /* rev8 */
431
432 /* synchronized access to registers in SDIO clock domain */
433 u32 sdioaccess; /* 0x050, rev8 */
434 u32 PAD[3];
435
436 /* PCMCIA frame control */
437 u8 pcmciaframectrl; /* 0x060, rev8 */
438 u8 PAD[3];
439 u8 pcmciawatermark; /* rev8 */
440 u8 PAD[155];
441
442 /* interrupt batching control */
443 u32 intrcvlazy; /* 0x100, rev8 */
444 u32 PAD[3];
445
446 /* counters */
447 u32 cmd52rd; /* 0x110, rev8 */
448 u32 cmd52wr; /* rev8 */
449 u32 cmd53rd; /* rev8 */
450 u32 cmd53wr; /* rev8 */
451 u32 abort; /* rev8 */
452 u32 datacrcerror; /* rev8 */
453 u32 rdoutofsync; /* rev8 */
454 u32 wroutofsync; /* rev8 */
455 u32 writebusy; /* rev8 */
456 u32 readwait; /* rev8 */
457 u32 readterm; /* rev8 */
458 u32 writeterm; /* rev8 */
459 u32 PAD[40];
460 u32 clockctlstatus; /* rev8 */
461 u32 PAD[7];
462
463 u32 PAD[128]; /* DMA engines */
464
465 /* SDIO/PCMCIA CIS region */
466 char cis[512]; /* 0x400-0x5ff, rev6 */
467
468 /* PCMCIA function control registers */
469 char pcmciafcr[256]; /* 0x600-6ff, rev6 */
470 u16 PAD[55];
471
472 /* PCMCIA backplane access */
473 u16 backplanecsr; /* 0x76E, rev6 */
474 u16 backplaneaddr0; /* rev6 */
475 u16 backplaneaddr1; /* rev6 */
476 u16 backplaneaddr2; /* rev6 */
477 u16 backplaneaddr3; /* rev6 */
478 u16 backplanedata0; /* rev6 */
479 u16 backplanedata1; /* rev6 */
480 u16 backplanedata2; /* rev6 */
481 u16 backplanedata3; /* rev6 */
482 u16 PAD[31];
483
484 /* sprom "size" & "blank" info */
485 u16 spromstatus; /* 0x7BE, rev2 */
486 u32 PAD[464];
487
488 u16 PAD[0x80];
489 };
490
491 #ifdef BCMDBG
492 /* Device console log buffer state */
493 struct brcmf_console {
494 uint count; /* Poll interval msec counter */
495 uint log_addr; /* Log struct address (fixed) */
496 struct rte_log_le log_le; /* Log struct (host copy) */
497 uint bufsize; /* Size of log buffer */
498 u8 *buf; /* Log buffer (host copy) */
499 uint last; /* Last buffer read index */
500 };
501 #endif /* BCMDBG */
502
503 struct sdpcm_shared {
504 u32 flags;
505 u32 trap_addr;
506 u32 assert_exp_addr;
507 u32 assert_file_addr;
508 u32 assert_line;
509 u32 console_addr; /* Address of struct rte_console */
510 u32 msgtrace_addr;
511 u8 tag[32];
512 };
513
514 struct sdpcm_shared_le {
515 __le32 flags;
516 __le32 trap_addr;
517 __le32 assert_exp_addr;
518 __le32 assert_file_addr;
519 __le32 assert_line;
520 __le32 console_addr; /* Address of struct rte_console */
521 __le32 msgtrace_addr;
522 u8 tag[32];
523 };
524
525
526 /* misc chip info needed by some of the routines */
527 struct chip_info {
528 u32 chip;
529 u32 chiprev;
530 u32 cccorebase;
531 u32 ccrev;
532 u32 cccaps;
533 u32 buscorebase; /* 32 bits backplane bus address */
534 u32 buscorerev;
535 u32 buscoretype;
536 u32 ramcorebase;
537 u32 armcorebase;
538 u32 pmurev;
539 u32 ramsize;
540 };
541
542 /* Private data for SDIO bus interaction */
543 struct brcmf_bus {
544 struct brcmf_pub *drvr;
545
546 struct brcmf_sdio_dev *sdiodev; /* sdio device handler */
547 struct chip_info *ci; /* Chip info struct */
548 char *vars; /* Variables (from CIS and/or other) */
549 uint varsz; /* Size of variables buffer */
550
551 u32 ramsize; /* Size of RAM in SOCRAM (bytes) */
552
553 u32 hostintmask; /* Copy of Host Interrupt Mask */
554 u32 intstatus; /* Intstatus bits (events) pending */
555 bool dpc_sched; /* Indicates DPC schedule (intrpt rcvd) */
556 bool fcstate; /* State of dongle flow-control */
557
558 uint blocksize; /* Block size of SDIO transfers */
559 uint roundup; /* Max roundup limit */
560
561 struct pktq txq; /* Queue length used for flow-control */
562 u8 flowcontrol; /* per prio flow control bitmask */
563 u8 tx_seq; /* Transmit sequence number (next) */
564 u8 tx_max; /* Maximum transmit sequence allowed */
565
566 u8 hdrbuf[MAX_HDR_READ + BRCMF_SDALIGN];
567 u8 *rxhdr; /* Header of current rx frame (in hdrbuf) */
568 u16 nextlen; /* Next Read Len from last header */
569 u8 rx_seq; /* Receive sequence number (expected) */
570 bool rxskip; /* Skip receive (awaiting NAK ACK) */
571
572 uint rxbound; /* Rx frames to read before resched */
573 uint txbound; /* Tx frames to send before resched */
574 uint txminmax;
575
576 struct sk_buff *glomd; /* Packet containing glomming descriptor */
577 struct sk_buff *glom; /* Packet chain for glommed superframe */
578 uint glomerr; /* Glom packet read errors */
579
580 u8 *rxbuf; /* Buffer for receiving control packets */
581 uint rxblen; /* Allocated length of rxbuf */
582 u8 *rxctl; /* Aligned pointer into rxbuf */
583 u8 *databuf; /* Buffer for receiving big glom packet */
584 u8 *dataptr; /* Aligned pointer into databuf */
585 uint rxlen; /* Length of valid data in buffer */
586
587 u8 sdpcm_ver; /* Bus protocol reported by dongle */
588
589 bool intr; /* Use interrupts */
590 bool poll; /* Use polling */
591 bool ipend; /* Device interrupt is pending */
592 uint intrcount; /* Count of device interrupt callbacks */
593 uint lastintrs; /* Count as of last watchdog timer */
594 uint spurious; /* Count of spurious interrupts */
595 uint pollrate; /* Ticks between device polls */
596 uint polltick; /* Tick counter */
597 uint pollcnt; /* Count of active polls */
598
599 #ifdef BCMDBG
600 uint console_interval;
601 struct brcmf_console console; /* Console output polling support */
602 uint console_addr; /* Console address from shared struct */
603 #endif /* BCMDBG */
604
605 uint regfails; /* Count of R_REG failures */
606
607 uint clkstate; /* State of sd and backplane clock(s) */
608 bool activity; /* Activity flag for clock down */
609 s32 idletime; /* Control for activity timeout */
610 s32 idlecount; /* Activity timeout counter */
611 s32 idleclock; /* How to set bus driver when idle */
612 s32 sd_rxchain;
613 bool use_rxchain; /* If brcmf should use PKT chains */
614 bool sleeping; /* Is SDIO bus sleeping? */
615 bool rxflow_mode; /* Rx flow control mode */
616 bool rxflow; /* Is rx flow control on */
617 bool alp_only; /* Don't use HT clock (ALP only) */
618 /* Field to decide if rx of control frames happen in rxbuf or lb-pool */
619 bool usebufpool;
620
621 /* Some additional counters */
622 uint tx_sderrs; /* Count of tx attempts with sd errors */
623 uint fcqueued; /* Tx packets that got queued */
624 uint rxrtx; /* Count of rtx requests (NAK to dongle) */
625 uint rx_toolong; /* Receive frames too long to receive */
626 uint rxc_errors; /* SDIO errors when reading control frames */
627 uint rx_hdrfail; /* SDIO errors on header reads */
628 uint rx_badhdr; /* Bad received headers (roosync?) */
629 uint rx_badseq; /* Mismatched rx sequence number */
630 uint fc_rcvd; /* Number of flow-control events received */
631 uint fc_xoff; /* Number which turned on flow-control */
632 uint fc_xon; /* Number which turned off flow-control */
633 uint rxglomfail; /* Failed deglom attempts */
634 uint rxglomframes; /* Number of glom frames (superframes) */
635 uint rxglompkts; /* Number of packets from glom frames */
636 uint f2rxhdrs; /* Number of header reads */
637 uint f2rxdata; /* Number of frame data reads */
638 uint f2txdata; /* Number of f2 frame writes */
639 uint f1regdata; /* Number of f1 register accesses */
640
641 u8 *ctrl_frame_buf;
642 u32 ctrl_frame_len;
643 bool ctrl_frame_stat;
644
645 spinlock_t txqlock;
646 wait_queue_head_t ctrl_wait;
647 wait_queue_head_t dcmd_resp_wait;
648
649 struct timer_list timer;
650 struct completion watchdog_wait;
651 struct task_struct *watchdog_tsk;
652 bool wd_timer_valid;
653 uint save_ms;
654
655 struct task_struct *dpc_tsk;
656 struct completion dpc_wait;
657
658 struct semaphore sdsem;
659
660 const char *fw_name;
661 const struct firmware *firmware;
662 const char *nv_name;
663 u32 fw_ptr;
664 };
665
666 struct sbconfig {
667 u32 PAD[2];
668 u32 sbipsflag; /* initiator port ocp slave flag */
669 u32 PAD[3];
670 u32 sbtpsflag; /* target port ocp slave flag */
671 u32 PAD[11];
672 u32 sbtmerrloga; /* (sonics >= 2.3) */
673 u32 PAD;
674 u32 sbtmerrlog; /* (sonics >= 2.3) */
675 u32 PAD[3];
676 u32 sbadmatch3; /* address match3 */
677 u32 PAD;
678 u32 sbadmatch2; /* address match2 */
679 u32 PAD;
680 u32 sbadmatch1; /* address match1 */
681 u32 PAD[7];
682 u32 sbimstate; /* initiator agent state */
683 u32 sbintvec; /* interrupt mask */
684 u32 sbtmstatelow; /* target state */
685 u32 sbtmstatehigh; /* target state */
686 u32 sbbwa0; /* bandwidth allocation table0 */
687 u32 PAD;
688 u32 sbimconfiglow; /* initiator configuration */
689 u32 sbimconfighigh; /* initiator configuration */
690 u32 sbadmatch0; /* address match0 */
691 u32 PAD;
692 u32 sbtmconfiglow; /* target configuration */
693 u32 sbtmconfighigh; /* target configuration */
694 u32 sbbconfig; /* broadcast configuration */
695 u32 PAD;
696 u32 sbbstate; /* broadcast state */
697 u32 PAD[3];
698 u32 sbactcnfg; /* activate configuration */
699 u32 PAD[3];
700 u32 sbflagst; /* current sbflags */
701 u32 PAD[3];
702 u32 sbidlow; /* identification */
703 u32 sbidhigh; /* identification */
704 };
705
706 /* clkstate */
707 #define CLK_NONE 0
708 #define CLK_SDONLY 1
709 #define CLK_PENDING 2 /* Not used yet */
710 #define CLK_AVAIL 3
711
712 #ifdef BCMDBG
713 static int qcount[NUMPRIO];
714 static int tx_packets[NUMPRIO];
715 #endif /* BCMDBG */
716
717 #define SDIO_DRIVE_STRENGTH 6 /* in milliamps */
718
719 #define RETRYCHAN(chan) ((chan) == SDPCM_EVENT_CHANNEL)
720
721 /* Retry count for register access failures */
722 static const uint retry_limit = 2;
723
724 /* Limit on rounding up frames */
725 static const uint max_roundup = 512;
726
727 #define ALIGNMENT 4
728
729 static void pkt_align(struct sk_buff *p, int len, int align)
730 {
731 uint datalign;
732 datalign = (unsigned long)(p->data);
733 datalign = roundup(datalign, (align)) - datalign;
734 if (datalign)
735 skb_pull(p, datalign);
736 __skb_trim(p, len);
737 }
738
739 /* To check if there's window offered */
740 static bool data_ok(struct brcmf_bus *bus)
741 {
742 return (u8)(bus->tx_max - bus->tx_seq) != 0 &&
743 ((u8)(bus->tx_max - bus->tx_seq) & 0x80) == 0;
744 }
745
746 /*
747 * Reads a register in the SDIO hardware block. This block occupies a series of
748 * adresses on the 32 bit backplane bus.
749 */
750 static void
751 r_sdreg32(struct brcmf_bus *bus, u32 *regvar, u32 reg_offset, u32 *retryvar)
752 {
753 *retryvar = 0;
754 do {
755 *regvar = brcmf_sdcard_reg_read(bus->sdiodev,
756 bus->ci->buscorebase + reg_offset, sizeof(u32));
757 } while (brcmf_sdcard_regfail(bus->sdiodev) &&
758 (++(*retryvar) <= retry_limit));
759 if (*retryvar) {
760 bus->regfails += (*retryvar-1);
761 if (*retryvar > retry_limit) {
762 brcmf_dbg(ERROR, "FAILED READ %Xh\n", reg_offset);
763 *regvar = 0;
764 }
765 }
766 }
767
768 static void
769 w_sdreg32(struct brcmf_bus *bus, u32 regval, u32 reg_offset, u32 *retryvar)
770 {
771 *retryvar = 0;
772 do {
773 brcmf_sdcard_reg_write(bus->sdiodev,
774 bus->ci->buscorebase + reg_offset,
775 sizeof(u32), regval);
776 } while (brcmf_sdcard_regfail(bus->sdiodev) &&
777 (++(*retryvar) <= retry_limit));
778 if (*retryvar) {
779 bus->regfails += (*retryvar-1);
780 if (*retryvar > retry_limit)
781 brcmf_dbg(ERROR, "FAILED REGISTER WRITE %Xh\n",
782 reg_offset);
783 }
784 }
785
786 #define PKT_AVAILABLE() (intstatus & I_HMB_FRAME_IND)
787
788 #define HOSTINTMASK (I_HMB_SW_MASK | I_CHIPACTIVE)
789
790 /* Packet free applicable unconditionally for sdio and sdspi.
791 * Conditional if bufpool was present for gspi bus.
792 */
793 static void brcmf_sdbrcm_pktfree2(struct brcmf_bus *bus, struct sk_buff *pkt)
794 {
795 if (bus->usebufpool)
796 brcmu_pkt_buf_free_skb(pkt);
797 }
798
799 /* Turn backplane clock on or off */
800 static int brcmf_sdbrcm_htclk(struct brcmf_bus *bus, bool on, bool pendok)
801 {
802 int err;
803 u8 clkctl, clkreq, devctl;
804 unsigned long timeout;
805
806 brcmf_dbg(TRACE, "Enter\n");
807
808 clkctl = 0;
809
810 if (on) {
811 /* Request HT Avail */
812 clkreq =
813 bus->alp_only ? SBSDIO_ALP_AVAIL_REQ : SBSDIO_HT_AVAIL_REQ;
814
815 if ((bus->ci->chip == BCM4329_CHIP_ID)
816 && (bus->ci->chiprev == 0))
817 clkreq |= SBSDIO_FORCE_ALP;
818
819 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
820 SBSDIO_FUNC1_CHIPCLKCSR, clkreq, &err);
821 if (err) {
822 brcmf_dbg(ERROR, "HT Avail request error: %d\n", err);
823 return -EBADE;
824 }
825
826 if (pendok && ((bus->ci->buscoretype == PCMCIA_CORE_ID)
827 && (bus->ci->buscorerev == 9))) {
828 u32 dummy, retries;
829 r_sdreg32(bus, &dummy,
830 offsetof(struct sdpcmd_regs, clockctlstatus),
831 &retries);
832 }
833
834 /* Check current status */
835 clkctl = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
836 SBSDIO_FUNC1_CHIPCLKCSR, &err);
837 if (err) {
838 brcmf_dbg(ERROR, "HT Avail read error: %d\n", err);
839 return -EBADE;
840 }
841
842 /* Go to pending and await interrupt if appropriate */
843 if (!SBSDIO_CLKAV(clkctl, bus->alp_only) && pendok) {
844 /* Allow only clock-available interrupt */
845 devctl = brcmf_sdcard_cfg_read(bus->sdiodev,
846 SDIO_FUNC_1,
847 SBSDIO_DEVICE_CTL, &err);
848 if (err) {
849 brcmf_dbg(ERROR, "Devctl error setting CA: %d\n",
850 err);
851 return -EBADE;
852 }
853
854 devctl |= SBSDIO_DEVCTL_CA_INT_ONLY;
855 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
856 SBSDIO_DEVICE_CTL, devctl, &err);
857 brcmf_dbg(INFO, "CLKCTL: set PENDING\n");
858 bus->clkstate = CLK_PENDING;
859
860 return 0;
861 } else if (bus->clkstate == CLK_PENDING) {
862 /* Cancel CA-only interrupt filter */
863 devctl =
864 brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
865 SBSDIO_DEVICE_CTL, &err);
866 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
867 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
868 SBSDIO_DEVICE_CTL, devctl, &err);
869 }
870
871 /* Otherwise, wait here (polling) for HT Avail */
872 timeout = jiffies +
873 msecs_to_jiffies(PMU_MAX_TRANSITION_DLY/1000);
874 while (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
875 clkctl = brcmf_sdcard_cfg_read(bus->sdiodev,
876 SDIO_FUNC_1,
877 SBSDIO_FUNC1_CHIPCLKCSR,
878 &err);
879 if (time_after(jiffies, timeout))
880 break;
881 else
882 usleep_range(5000, 10000);
883 }
884 if (err) {
885 brcmf_dbg(ERROR, "HT Avail request error: %d\n", err);
886 return -EBADE;
887 }
888 if (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
889 brcmf_dbg(ERROR, "HT Avail timeout (%d): clkctl 0x%02x\n",
890 PMU_MAX_TRANSITION_DLY, clkctl);
891 return -EBADE;
892 }
893
894 /* Mark clock available */
895 bus->clkstate = CLK_AVAIL;
896 brcmf_dbg(INFO, "CLKCTL: turned ON\n");
897
898 #if defined(BCMDBG)
899 if (bus->alp_only != true) {
900 if (SBSDIO_ALPONLY(clkctl))
901 brcmf_dbg(ERROR, "HT Clock should be on\n");
902 }
903 #endif /* defined (BCMDBG) */
904
905 bus->activity = true;
906 } else {
907 clkreq = 0;
908
909 if (bus->clkstate == CLK_PENDING) {
910 /* Cancel CA-only interrupt filter */
911 devctl = brcmf_sdcard_cfg_read(bus->sdiodev,
912 SDIO_FUNC_1,
913 SBSDIO_DEVICE_CTL, &err);
914 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
915 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
916 SBSDIO_DEVICE_CTL, devctl, &err);
917 }
918
919 bus->clkstate = CLK_SDONLY;
920 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
921 SBSDIO_FUNC1_CHIPCLKCSR, clkreq, &err);
922 brcmf_dbg(INFO, "CLKCTL: turned OFF\n");
923 if (err) {
924 brcmf_dbg(ERROR, "Failed access turning clock off: %d\n",
925 err);
926 return -EBADE;
927 }
928 }
929 return 0;
930 }
931
932 /* Change idle/active SD state */
933 static int brcmf_sdbrcm_sdclk(struct brcmf_bus *bus, bool on)
934 {
935 brcmf_dbg(TRACE, "Enter\n");
936
937 if (on)
938 bus->clkstate = CLK_SDONLY;
939 else
940 bus->clkstate = CLK_NONE;
941
942 return 0;
943 }
944
945 /* Transition SD and backplane clock readiness */
946 static int brcmf_sdbrcm_clkctl(struct brcmf_bus *bus, uint target, bool pendok)
947 {
948 #ifdef BCMDBG
949 uint oldstate = bus->clkstate;
950 #endif /* BCMDBG */
951
952 brcmf_dbg(TRACE, "Enter\n");
953
954 /* Early exit if we're already there */
955 if (bus->clkstate == target) {
956 if (target == CLK_AVAIL) {
957 brcmf_sdbrcm_wd_timer(bus, BRCMF_WD_POLL_MS);
958 bus->activity = true;
959 }
960 return 0;
961 }
962
963 switch (target) {
964 case CLK_AVAIL:
965 /* Make sure SD clock is available */
966 if (bus->clkstate == CLK_NONE)
967 brcmf_sdbrcm_sdclk(bus, true);
968 /* Now request HT Avail on the backplane */
969 brcmf_sdbrcm_htclk(bus, true, pendok);
970 brcmf_sdbrcm_wd_timer(bus, BRCMF_WD_POLL_MS);
971 bus->activity = true;
972 break;
973
974 case CLK_SDONLY:
975 /* Remove HT request, or bring up SD clock */
976 if (bus->clkstate == CLK_NONE)
977 brcmf_sdbrcm_sdclk(bus, true);
978 else if (bus->clkstate == CLK_AVAIL)
979 brcmf_sdbrcm_htclk(bus, false, false);
980 else
981 brcmf_dbg(ERROR, "request for %d -> %d\n",
982 bus->clkstate, target);
983 brcmf_sdbrcm_wd_timer(bus, BRCMF_WD_POLL_MS);
984 break;
985
986 case CLK_NONE:
987 /* Make sure to remove HT request */
988 if (bus->clkstate == CLK_AVAIL)
989 brcmf_sdbrcm_htclk(bus, false, false);
990 /* Now remove the SD clock */
991 brcmf_sdbrcm_sdclk(bus, false);
992 brcmf_sdbrcm_wd_timer(bus, 0);
993 break;
994 }
995 #ifdef BCMDBG
996 brcmf_dbg(INFO, "%d -> %d\n", oldstate, bus->clkstate);
997 #endif /* BCMDBG */
998
999 return 0;
1000 }
1001
1002 static int brcmf_sdbrcm_bussleep(struct brcmf_bus *bus, bool sleep)
1003 {
1004 uint retries = 0;
1005
1006 brcmf_dbg(INFO, "request %s (currently %s)\n",
1007 sleep ? "SLEEP" : "WAKE",
1008 bus->sleeping ? "SLEEP" : "WAKE");
1009
1010 /* Done if we're already in the requested state */
1011 if (sleep == bus->sleeping)
1012 return 0;
1013
1014 /* Going to sleep: set the alarm and turn off the lights... */
1015 if (sleep) {
1016 /* Don't sleep if something is pending */
1017 if (bus->dpc_sched || bus->rxskip || pktq_len(&bus->txq))
1018 return -EBUSY;
1019
1020 /* Make sure the controller has the bus up */
1021 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
1022
1023 /* Tell device to start using OOB wakeup */
1024 w_sdreg32(bus, SMB_USE_OOB,
1025 offsetof(struct sdpcmd_regs, tosbmailbox), &retries);
1026 if (retries > retry_limit)
1027 brcmf_dbg(ERROR, "CANNOT SIGNAL CHIP, WILL NOT WAKE UP!!\n");
1028
1029 /* Turn off our contribution to the HT clock request */
1030 brcmf_sdbrcm_clkctl(bus, CLK_SDONLY, false);
1031
1032 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
1033 SBSDIO_FUNC1_CHIPCLKCSR,
1034 SBSDIO_FORCE_HW_CLKREQ_OFF, NULL);
1035
1036 /* Isolate the bus */
1037 if (bus->ci->chip != BCM4329_CHIP_ID) {
1038 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
1039 SBSDIO_DEVICE_CTL,
1040 SBSDIO_DEVCTL_PADS_ISO, NULL);
1041 }
1042
1043 /* Change state */
1044 bus->sleeping = true;
1045
1046 } else {
1047 /* Waking up: bus power up is ok, set local state */
1048
1049 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
1050 SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL);
1051
1052 /* Force pad isolation off if possible
1053 (in case power never toggled) */
1054 if ((bus->ci->buscoretype == PCMCIA_CORE_ID)
1055 && (bus->ci->buscorerev >= 10))
1056 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
1057 SBSDIO_DEVICE_CTL, 0, NULL);
1058
1059 /* Make sure the controller has the bus up */
1060 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
1061
1062 /* Send misc interrupt to indicate OOB not needed */
1063 w_sdreg32(bus, 0, offsetof(struct sdpcmd_regs, tosbmailboxdata),
1064 &retries);
1065 if (retries <= retry_limit)
1066 w_sdreg32(bus, SMB_DEV_INT,
1067 offsetof(struct sdpcmd_regs, tosbmailbox),
1068 &retries);
1069
1070 if (retries > retry_limit)
1071 brcmf_dbg(ERROR, "CANNOT SIGNAL CHIP TO CLEAR OOB!!\n");
1072
1073 /* Make sure we have SD bus access */
1074 brcmf_sdbrcm_clkctl(bus, CLK_SDONLY, false);
1075
1076 /* Change state */
1077 bus->sleeping = false;
1078 }
1079
1080 return 0;
1081 }
1082
1083 static void bus_wake(struct brcmf_bus *bus)
1084 {
1085 if (bus->sleeping)
1086 brcmf_sdbrcm_bussleep(bus, false);
1087 }
1088
1089 static u32 brcmf_sdbrcm_hostmail(struct brcmf_bus *bus)
1090 {
1091 u32 intstatus = 0;
1092 u32 hmb_data;
1093 u8 fcbits;
1094 uint retries = 0;
1095
1096 brcmf_dbg(TRACE, "Enter\n");
1097
1098 /* Read mailbox data and ack that we did so */
1099 r_sdreg32(bus, &hmb_data,
1100 offsetof(struct sdpcmd_regs, tohostmailboxdata), &retries);
1101
1102 if (retries <= retry_limit)
1103 w_sdreg32(bus, SMB_INT_ACK,
1104 offsetof(struct sdpcmd_regs, tosbmailbox), &retries);
1105 bus->f1regdata += 2;
1106
1107 /* Dongle recomposed rx frames, accept them again */
1108 if (hmb_data & HMB_DATA_NAKHANDLED) {
1109 brcmf_dbg(INFO, "Dongle reports NAK handled, expect rtx of %d\n",
1110 bus->rx_seq);
1111 if (!bus->rxskip)
1112 brcmf_dbg(ERROR, "unexpected NAKHANDLED!\n");
1113
1114 bus->rxskip = false;
1115 intstatus |= I_HMB_FRAME_IND;
1116 }
1117
1118 /*
1119 * DEVREADY does not occur with gSPI.
1120 */
1121 if (hmb_data & (HMB_DATA_DEVREADY | HMB_DATA_FWREADY)) {
1122 bus->sdpcm_ver =
1123 (hmb_data & HMB_DATA_VERSION_MASK) >>
1124 HMB_DATA_VERSION_SHIFT;
1125 if (bus->sdpcm_ver != SDPCM_PROT_VERSION)
1126 brcmf_dbg(ERROR, "Version mismatch, dongle reports %d, "
1127 "expecting %d\n",
1128 bus->sdpcm_ver, SDPCM_PROT_VERSION);
1129 else
1130 brcmf_dbg(INFO, "Dongle ready, protocol version %d\n",
1131 bus->sdpcm_ver);
1132 }
1133
1134 /*
1135 * Flow Control has been moved into the RX headers and this out of band
1136 * method isn't used any more.
1137 * remaining backward compatible with older dongles.
1138 */
1139 if (hmb_data & HMB_DATA_FC) {
1140 fcbits = (hmb_data & HMB_DATA_FCDATA_MASK) >>
1141 HMB_DATA_FCDATA_SHIFT;
1142
1143 if (fcbits & ~bus->flowcontrol)
1144 bus->fc_xoff++;
1145
1146 if (bus->flowcontrol & ~fcbits)
1147 bus->fc_xon++;
1148
1149 bus->fc_rcvd++;
1150 bus->flowcontrol = fcbits;
1151 }
1152
1153 /* Shouldn't be any others */
1154 if (hmb_data & ~(HMB_DATA_DEVREADY |
1155 HMB_DATA_NAKHANDLED |
1156 HMB_DATA_FC |
1157 HMB_DATA_FWREADY |
1158 HMB_DATA_FCDATA_MASK | HMB_DATA_VERSION_MASK))
1159 brcmf_dbg(ERROR, "Unknown mailbox data content: 0x%02x\n",
1160 hmb_data);
1161
1162 return intstatus;
1163 }
1164
1165 static void brcmf_sdbrcm_rxfail(struct brcmf_bus *bus, bool abort, bool rtx)
1166 {
1167 uint retries = 0;
1168 u16 lastrbc;
1169 u8 hi, lo;
1170 int err;
1171
1172 brcmf_dbg(ERROR, "%sterminate frame%s\n",
1173 abort ? "abort command, " : "",
1174 rtx ? ", send NAK" : "");
1175
1176 if (abort)
1177 brcmf_sdcard_abort(bus->sdiodev, SDIO_FUNC_2);
1178
1179 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
1180 SBSDIO_FUNC1_FRAMECTRL,
1181 SFC_RF_TERM, &err);
1182 bus->f1regdata++;
1183
1184 /* Wait until the packet has been flushed (device/FIFO stable) */
1185 for (lastrbc = retries = 0xffff; retries > 0; retries--) {
1186 hi = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
1187 SBSDIO_FUNC1_RFRAMEBCHI, NULL);
1188 lo = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
1189 SBSDIO_FUNC1_RFRAMEBCLO, NULL);
1190 bus->f1regdata += 2;
1191
1192 if ((hi == 0) && (lo == 0))
1193 break;
1194
1195 if ((hi > (lastrbc >> 8)) && (lo > (lastrbc & 0x00ff))) {
1196 brcmf_dbg(ERROR, "count growing: last 0x%04x now 0x%04x\n",
1197 lastrbc, (hi << 8) + lo);
1198 }
1199 lastrbc = (hi << 8) + lo;
1200 }
1201
1202 if (!retries)
1203 brcmf_dbg(ERROR, "count never zeroed: last 0x%04x\n", lastrbc);
1204 else
1205 brcmf_dbg(INFO, "flush took %d iterations\n", 0xffff - retries);
1206
1207 if (rtx) {
1208 bus->rxrtx++;
1209 w_sdreg32(bus, SMB_NAK,
1210 offsetof(struct sdpcmd_regs, tosbmailbox), &retries);
1211
1212 bus->f1regdata++;
1213 if (retries <= retry_limit)
1214 bus->rxskip = true;
1215 }
1216
1217 /* Clear partial in any case */
1218 bus->nextlen = 0;
1219
1220 /* If we can't reach the device, signal failure */
1221 if (err || brcmf_sdcard_regfail(bus->sdiodev))
1222 bus->drvr->busstate = BRCMF_BUS_DOWN;
1223 }
1224
1225 static u8 brcmf_sdbrcm_rxglom(struct brcmf_bus *bus, u8 rxseq)
1226 {
1227 u16 dlen, totlen;
1228 u8 *dptr, num = 0;
1229
1230 u16 sublen, check;
1231 struct sk_buff *pfirst, *plast, *pnext, *save_pfirst;
1232
1233 int errcode;
1234 u8 chan, seq, doff, sfdoff;
1235 u8 txmax;
1236
1237 int ifidx = 0;
1238 bool usechain = bus->use_rxchain;
1239
1240 /* If packets, issue read(s) and send up packet chain */
1241 /* Return sequence numbers consumed? */
1242
1243 brcmf_dbg(TRACE, "start: glomd %p glom %p\n", bus->glomd, bus->glom);
1244
1245 /* If there's a descriptor, generate the packet chain */
1246 if (bus->glomd) {
1247 pfirst = plast = pnext = NULL;
1248 dlen = (u16) (bus->glomd->len);
1249 dptr = bus->glomd->data;
1250 if (!dlen || (dlen & 1)) {
1251 brcmf_dbg(ERROR, "bad glomd len(%d), ignore descriptor\n",
1252 dlen);
1253 dlen = 0;
1254 }
1255
1256 for (totlen = num = 0; dlen; num++) {
1257 /* Get (and move past) next length */
1258 sublen = get_unaligned_le16(dptr);
1259 dlen -= sizeof(u16);
1260 dptr += sizeof(u16);
1261 if ((sublen < SDPCM_HDRLEN) ||
1262 ((num == 0) && (sublen < (2 * SDPCM_HDRLEN)))) {
1263 brcmf_dbg(ERROR, "descriptor len %d bad: %d\n",
1264 num, sublen);
1265 pnext = NULL;
1266 break;
1267 }
1268 if (sublen % BRCMF_SDALIGN) {
1269 brcmf_dbg(ERROR, "sublen %d not multiple of %d\n",
1270 sublen, BRCMF_SDALIGN);
1271 usechain = false;
1272 }
1273 totlen += sublen;
1274
1275 /* For last frame, adjust read len so total
1276 is a block multiple */
1277 if (!dlen) {
1278 sublen +=
1279 (roundup(totlen, bus->blocksize) - totlen);
1280 totlen = roundup(totlen, bus->blocksize);
1281 }
1282
1283 /* Allocate/chain packet for next subframe */
1284 pnext = brcmu_pkt_buf_get_skb(sublen + BRCMF_SDALIGN);
1285 if (pnext == NULL) {
1286 brcmf_dbg(ERROR, "bcm_pkt_buf_get_skb failed, num %d len %d\n",
1287 num, sublen);
1288 break;
1289 }
1290 if (!pfirst) {
1291 pfirst = plast = pnext;
1292 } else {
1293 plast->next = pnext;
1294 plast = pnext;
1295 }
1296
1297 /* Adhere to start alignment requirements */
1298 pkt_align(pnext, sublen, BRCMF_SDALIGN);
1299 }
1300
1301 /* If all allocations succeeded, save packet chain
1302 in bus structure */
1303 if (pnext) {
1304 brcmf_dbg(GLOM, "allocated %d-byte packet chain for %d subframes\n",
1305 totlen, num);
1306 if (BRCMF_GLOM_ON() && bus->nextlen &&
1307 totlen != bus->nextlen) {
1308 brcmf_dbg(GLOM, "glomdesc mismatch: nextlen %d glomdesc %d rxseq %d\n",
1309 bus->nextlen, totlen, rxseq);
1310 }
1311 bus->glom = pfirst;
1312 pfirst = pnext = NULL;
1313 } else {
1314 if (pfirst)
1315 brcmu_pkt_buf_free_skb(pfirst);
1316 bus->glom = NULL;
1317 num = 0;
1318 }
1319
1320 /* Done with descriptor packet */
1321 brcmu_pkt_buf_free_skb(bus->glomd);
1322 bus->glomd = NULL;
1323 bus->nextlen = 0;
1324 }
1325
1326 /* Ok -- either we just generated a packet chain,
1327 or had one from before */
1328 if (bus->glom) {
1329 if (BRCMF_GLOM_ON()) {
1330 brcmf_dbg(GLOM, "try superframe read, packet chain:\n");
1331 for (pnext = bus->glom; pnext; pnext = pnext->next) {
1332 brcmf_dbg(GLOM, " %p: %p len 0x%04x (%d)\n",
1333 pnext, (u8 *) (pnext->data),
1334 pnext->len, pnext->len);
1335 }
1336 }
1337
1338 pfirst = bus->glom;
1339 dlen = (u16) brcmu_pkttotlen(pfirst);
1340
1341 /* Do an SDIO read for the superframe. Configurable iovar to
1342 * read directly into the chained packet, or allocate a large
1343 * packet and and copy into the chain.
1344 */
1345 if (usechain) {
1346 errcode = brcmf_sdcard_recv_buf(bus->sdiodev,
1347 bus->sdiodev->sbwad,
1348 SDIO_FUNC_2,
1349 F2SYNC, (u8 *) pfirst->data, dlen,
1350 pfirst);
1351 } else if (bus->dataptr) {
1352 errcode = brcmf_sdcard_recv_buf(bus->sdiodev,
1353 bus->sdiodev->sbwad,
1354 SDIO_FUNC_2,
1355 F2SYNC, bus->dataptr, dlen,
1356 NULL);
1357 sublen = (u16) brcmu_pktfrombuf(pfirst, 0, dlen,
1358 bus->dataptr);
1359 if (sublen != dlen) {
1360 brcmf_dbg(ERROR, "FAILED TO COPY, dlen %d sublen %d\n",
1361 dlen, sublen);
1362 errcode = -1;
1363 }
1364 pnext = NULL;
1365 } else {
1366 brcmf_dbg(ERROR, "COULDN'T ALLOC %d-BYTE GLOM, FORCE FAILURE\n",
1367 dlen);
1368 errcode = -1;
1369 }
1370 bus->f2rxdata++;
1371
1372 /* On failure, kill the superframe, allow a couple retries */
1373 if (errcode < 0) {
1374 brcmf_dbg(ERROR, "glom read of %d bytes failed: %d\n",
1375 dlen, errcode);
1376 bus->drvr->rx_errors++;
1377
1378 if (bus->glomerr++ < 3) {
1379 brcmf_sdbrcm_rxfail(bus, true, true);
1380 } else {
1381 bus->glomerr = 0;
1382 brcmf_sdbrcm_rxfail(bus, true, false);
1383 brcmu_pkt_buf_free_skb(bus->glom);
1384 bus->rxglomfail++;
1385 bus->glom = NULL;
1386 }
1387 return 0;
1388 }
1389 #ifdef BCMDBG
1390 if (BRCMF_GLOM_ON()) {
1391 printk(KERN_DEBUG "SUPERFRAME:\n");
1392 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
1393 pfirst->data, min_t(int, pfirst->len, 48));
1394 }
1395 #endif
1396
1397 /* Validate the superframe header */
1398 dptr = (u8 *) (pfirst->data);
1399 sublen = get_unaligned_le16(dptr);
1400 check = get_unaligned_le16(dptr + sizeof(u16));
1401
1402 chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
1403 seq = SDPCM_PACKET_SEQUENCE(&dptr[SDPCM_FRAMETAG_LEN]);
1404 bus->nextlen = dptr[SDPCM_FRAMETAG_LEN + SDPCM_NEXTLEN_OFFSET];
1405 if ((bus->nextlen << 4) > MAX_RX_DATASZ) {
1406 brcmf_dbg(INFO, "nextlen too large (%d) seq %d\n",
1407 bus->nextlen, seq);
1408 bus->nextlen = 0;
1409 }
1410 doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
1411 txmax = SDPCM_WINDOW_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
1412
1413 errcode = 0;
1414 if ((u16)~(sublen ^ check)) {
1415 brcmf_dbg(ERROR, "(superframe): HW hdr error: len/check 0x%04x/0x%04x\n",
1416 sublen, check);
1417 errcode = -1;
1418 } else if (roundup(sublen, bus->blocksize) != dlen) {
1419 brcmf_dbg(ERROR, "(superframe): len 0x%04x, rounded 0x%04x, expect 0x%04x\n",
1420 sublen, roundup(sublen, bus->blocksize),
1421 dlen);
1422 errcode = -1;
1423 } else if (SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]) !=
1424 SDPCM_GLOM_CHANNEL) {
1425 brcmf_dbg(ERROR, "(superframe): bad channel %d\n",
1426 SDPCM_PACKET_CHANNEL(
1427 &dptr[SDPCM_FRAMETAG_LEN]));
1428 errcode = -1;
1429 } else if (SDPCM_GLOMDESC(&dptr[SDPCM_FRAMETAG_LEN])) {
1430 brcmf_dbg(ERROR, "(superframe): got 2nd descriptor?\n");
1431 errcode = -1;
1432 } else if ((doff < SDPCM_HDRLEN) ||
1433 (doff > (pfirst->len - SDPCM_HDRLEN))) {
1434 brcmf_dbg(ERROR, "(superframe): Bad data offset %d: HW %d pkt %d min %d\n",
1435 doff, sublen, pfirst->len, SDPCM_HDRLEN);
1436 errcode = -1;
1437 }
1438
1439 /* Check sequence number of superframe SW header */
1440 if (rxseq != seq) {
1441 brcmf_dbg(INFO, "(superframe) rx_seq %d, expected %d\n",
1442 seq, rxseq);
1443 bus->rx_badseq++;
1444 rxseq = seq;
1445 }
1446
1447 /* Check window for sanity */
1448 if ((u8) (txmax - bus->tx_seq) > 0x40) {
1449 brcmf_dbg(ERROR, "unlikely tx max %d with tx_seq %d\n",
1450 txmax, bus->tx_seq);
1451 txmax = bus->tx_seq + 2;
1452 }
1453 bus->tx_max = txmax;
1454
1455 /* Remove superframe header, remember offset */
1456 skb_pull(pfirst, doff);
1457 sfdoff = doff;
1458
1459 /* Validate all the subframe headers */
1460 for (num = 0, pnext = pfirst; pnext && !errcode;
1461 num++, pnext = pnext->next) {
1462 dptr = (u8 *) (pnext->data);
1463 dlen = (u16) (pnext->len);
1464 sublen = get_unaligned_le16(dptr);
1465 check = get_unaligned_le16(dptr + sizeof(u16));
1466 chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
1467 doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
1468 #ifdef BCMDBG
1469 if (BRCMF_GLOM_ON()) {
1470 printk(KERN_DEBUG "subframe:\n");
1471 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
1472 dptr, 32);
1473 }
1474 #endif
1475
1476 if ((u16)~(sublen ^ check)) {
1477 brcmf_dbg(ERROR, "(subframe %d): HW hdr error: len/check 0x%04x/0x%04x\n",
1478 num, sublen, check);
1479 errcode = -1;
1480 } else if ((sublen > dlen) || (sublen < SDPCM_HDRLEN)) {
1481 brcmf_dbg(ERROR, "(subframe %d): length mismatch: len 0x%04x, expect 0x%04x\n",
1482 num, sublen, dlen);
1483 errcode = -1;
1484 } else if ((chan != SDPCM_DATA_CHANNEL) &&
1485 (chan != SDPCM_EVENT_CHANNEL)) {
1486 brcmf_dbg(ERROR, "(subframe %d): bad channel %d\n",
1487 num, chan);
1488 errcode = -1;
1489 } else if ((doff < SDPCM_HDRLEN) || (doff > sublen)) {
1490 brcmf_dbg(ERROR, "(subframe %d): Bad data offset %d: HW %d min %d\n",
1491 num, doff, sublen, SDPCM_HDRLEN);
1492 errcode = -1;
1493 }
1494 }
1495
1496 if (errcode) {
1497 /* Terminate frame on error, request
1498 a couple retries */
1499 if (bus->glomerr++ < 3) {
1500 /* Restore superframe header space */
1501 skb_push(pfirst, sfdoff);
1502 brcmf_sdbrcm_rxfail(bus, true, true);
1503 } else {
1504 bus->glomerr = 0;
1505 brcmf_sdbrcm_rxfail(bus, true, false);
1506 brcmu_pkt_buf_free_skb(bus->glom);
1507 bus->rxglomfail++;
1508 bus->glom = NULL;
1509 }
1510 bus->nextlen = 0;
1511 return 0;
1512 }
1513
1514 /* Basic SD framing looks ok - process each packet (header) */
1515 save_pfirst = pfirst;
1516 bus->glom = NULL;
1517 plast = NULL;
1518
1519 for (num = 0; pfirst; rxseq++, pfirst = pnext) {
1520 pnext = pfirst->next;
1521 pfirst->next = NULL;
1522
1523 dptr = (u8 *) (pfirst->data);
1524 sublen = get_unaligned_le16(dptr);
1525 chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
1526 seq = SDPCM_PACKET_SEQUENCE(&dptr[SDPCM_FRAMETAG_LEN]);
1527 doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
1528
1529 brcmf_dbg(GLOM, "Get subframe %d, %p(%p/%d), sublen %d chan %d seq %d\n",
1530 num, pfirst, pfirst->data,
1531 pfirst->len, sublen, chan, seq);
1532
1533 /* precondition: chan == SDPCM_DATA_CHANNEL ||
1534 chan == SDPCM_EVENT_CHANNEL */
1535
1536 if (rxseq != seq) {
1537 brcmf_dbg(GLOM, "rx_seq %d, expected %d\n",
1538 seq, rxseq);
1539 bus->rx_badseq++;
1540 rxseq = seq;
1541 }
1542 #ifdef BCMDBG
1543 if (BRCMF_BYTES_ON() && BRCMF_DATA_ON()) {
1544 printk(KERN_DEBUG "Rx Subframe Data:\n");
1545 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
1546 dptr, dlen);
1547 }
1548 #endif
1549
1550 __skb_trim(pfirst, sublen);
1551 skb_pull(pfirst, doff);
1552
1553 if (pfirst->len == 0) {
1554 brcmu_pkt_buf_free_skb(pfirst);
1555 if (plast)
1556 plast->next = pnext;
1557 else
1558 save_pfirst = pnext;
1559
1560 continue;
1561 } else if (brcmf_proto_hdrpull(bus->drvr, &ifidx,
1562 pfirst) != 0) {
1563 brcmf_dbg(ERROR, "rx protocol error\n");
1564 bus->drvr->rx_errors++;
1565 brcmu_pkt_buf_free_skb(pfirst);
1566 if (plast)
1567 plast->next = pnext;
1568 else
1569 save_pfirst = pnext;
1570
1571 continue;
1572 }
1573
1574 /* this packet will go up, link back into
1575 chain and count it */
1576 pfirst->next = pnext;
1577 plast = pfirst;
1578 num++;
1579
1580 #ifdef BCMDBG
1581 if (BRCMF_GLOM_ON()) {
1582 brcmf_dbg(GLOM, "subframe %d to stack, %p (%p/%d) nxt/lnk %p/%p\n",
1583 num, pfirst, pfirst->data,
1584 pfirst->len, pfirst->next,
1585 pfirst->prev);
1586 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
1587 pfirst->data,
1588 min_t(int, pfirst->len, 32));
1589 }
1590 #endif /* BCMDBG */
1591 }
1592 if (num) {
1593 up(&bus->sdsem);
1594 brcmf_rx_frame(bus->drvr, ifidx, save_pfirst, num);
1595 down(&bus->sdsem);
1596 }
1597
1598 bus->rxglomframes++;
1599 bus->rxglompkts += num;
1600 }
1601 return num;
1602 }
1603
1604 static int brcmf_sdbrcm_dcmd_resp_wait(struct brcmf_bus *bus, uint *condition,
1605 bool *pending)
1606 {
1607 DECLARE_WAITQUEUE(wait, current);
1608 int timeout = msecs_to_jiffies(DCMD_RESP_TIMEOUT);
1609
1610 /* Wait until control frame is available */
1611 add_wait_queue(&bus->dcmd_resp_wait, &wait);
1612 set_current_state(TASK_INTERRUPTIBLE);
1613
1614 while (!(*condition) && (!signal_pending(current) && timeout))
1615 timeout = schedule_timeout(timeout);
1616
1617 if (signal_pending(current))
1618 *pending = true;
1619
1620 set_current_state(TASK_RUNNING);
1621 remove_wait_queue(&bus->dcmd_resp_wait, &wait);
1622
1623 return timeout;
1624 }
1625
1626 static int brcmf_sdbrcm_dcmd_resp_wake(struct brcmf_bus *bus)
1627 {
1628 if (waitqueue_active(&bus->dcmd_resp_wait))
1629 wake_up_interruptible(&bus->dcmd_resp_wait);
1630
1631 return 0;
1632 }
1633 static void
1634 brcmf_sdbrcm_read_control(struct brcmf_bus *bus, u8 *hdr, uint len, uint doff)
1635 {
1636 uint rdlen, pad;
1637
1638 int sdret;
1639
1640 brcmf_dbg(TRACE, "Enter\n");
1641
1642 /* Set rxctl for frame (w/optional alignment) */
1643 bus->rxctl = bus->rxbuf;
1644 bus->rxctl += BRCMF_FIRSTREAD;
1645 pad = ((unsigned long)bus->rxctl % BRCMF_SDALIGN);
1646 if (pad)
1647 bus->rxctl += (BRCMF_SDALIGN - pad);
1648 bus->rxctl -= BRCMF_FIRSTREAD;
1649
1650 /* Copy the already-read portion over */
1651 memcpy(bus->rxctl, hdr, BRCMF_FIRSTREAD);
1652 if (len <= BRCMF_FIRSTREAD)
1653 goto gotpkt;
1654
1655 /* Raise rdlen to next SDIO block to avoid tail command */
1656 rdlen = len - BRCMF_FIRSTREAD;
1657 if (bus->roundup && bus->blocksize && (rdlen > bus->blocksize)) {
1658 pad = bus->blocksize - (rdlen % bus->blocksize);
1659 if ((pad <= bus->roundup) && (pad < bus->blocksize) &&
1660 ((len + pad) < bus->drvr->maxctl))
1661 rdlen += pad;
1662 } else if (rdlen % BRCMF_SDALIGN) {
1663 rdlen += BRCMF_SDALIGN - (rdlen % BRCMF_SDALIGN);
1664 }
1665
1666 /* Satisfy length-alignment requirements */
1667 if (rdlen & (ALIGNMENT - 1))
1668 rdlen = roundup(rdlen, ALIGNMENT);
1669
1670 /* Drop if the read is too big or it exceeds our maximum */
1671 if ((rdlen + BRCMF_FIRSTREAD) > bus->drvr->maxctl) {
1672 brcmf_dbg(ERROR, "%d-byte control read exceeds %d-byte buffer\n",
1673 rdlen, bus->drvr->maxctl);
1674 bus->drvr->rx_errors++;
1675 brcmf_sdbrcm_rxfail(bus, false, false);
1676 goto done;
1677 }
1678
1679 if ((len - doff) > bus->drvr->maxctl) {
1680 brcmf_dbg(ERROR, "%d-byte ctl frame (%d-byte ctl data) exceeds %d-byte limit\n",
1681 len, len - doff, bus->drvr->maxctl);
1682 bus->drvr->rx_errors++;
1683 bus->rx_toolong++;
1684 brcmf_sdbrcm_rxfail(bus, false, false);
1685 goto done;
1686 }
1687
1688 /* Read remainder of frame body into the rxctl buffer */
1689 sdret = brcmf_sdcard_recv_buf(bus->sdiodev,
1690 bus->sdiodev->sbwad,
1691 SDIO_FUNC_2,
1692 F2SYNC, (bus->rxctl + BRCMF_FIRSTREAD), rdlen,
1693 NULL);
1694 bus->f2rxdata++;
1695
1696 /* Control frame failures need retransmission */
1697 if (sdret < 0) {
1698 brcmf_dbg(ERROR, "read %d control bytes failed: %d\n",
1699 rdlen, sdret);
1700 bus->rxc_errors++;
1701 brcmf_sdbrcm_rxfail(bus, true, true);
1702 goto done;
1703 }
1704
1705 gotpkt:
1706
1707 #ifdef BCMDBG
1708 if (BRCMF_BYTES_ON() && BRCMF_CTL_ON()) {
1709 printk(KERN_DEBUG "RxCtrl:\n");
1710 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, bus->rxctl, len);
1711 }
1712 #endif
1713
1714 /* Point to valid data and indicate its length */
1715 bus->rxctl += doff;
1716 bus->rxlen = len - doff;
1717
1718 done:
1719 /* Awake any waiters */
1720 brcmf_sdbrcm_dcmd_resp_wake(bus);
1721 }
1722
1723 /* Pad read to blocksize for efficiency */
1724 static void brcmf_pad(struct brcmf_bus *bus, u16 *pad, u16 *rdlen)
1725 {
1726 if (bus->roundup && bus->blocksize && *rdlen > bus->blocksize) {
1727 *pad = bus->blocksize - (*rdlen % bus->blocksize);
1728 if (*pad <= bus->roundup && *pad < bus->blocksize &&
1729 *rdlen + *pad + BRCMF_FIRSTREAD < MAX_RX_DATASZ)
1730 *rdlen += *pad;
1731 } else if (*rdlen % BRCMF_SDALIGN) {
1732 *rdlen += BRCMF_SDALIGN - (*rdlen % BRCMF_SDALIGN);
1733 }
1734 }
1735
1736 static void
1737 brcmf_alloc_pkt_and_read(struct brcmf_bus *bus, u16 rdlen,
1738 struct sk_buff **pkt, u8 **rxbuf)
1739 {
1740 int sdret; /* Return code from calls */
1741
1742 *pkt = brcmu_pkt_buf_get_skb(rdlen + BRCMF_SDALIGN);
1743 if (*pkt == NULL)
1744 return;
1745
1746 pkt_align(*pkt, rdlen, BRCMF_SDALIGN);
1747 *rxbuf = (u8 *) ((*pkt)->data);
1748 /* Read the entire frame */
1749 sdret = brcmf_sdcard_recv_buf(bus->sdiodev, bus->sdiodev->sbwad,
1750 SDIO_FUNC_2, F2SYNC,
1751 *rxbuf, rdlen, *pkt);
1752 bus->f2rxdata++;
1753
1754 if (sdret < 0) {
1755 brcmf_dbg(ERROR, "(nextlen): read %d bytes failed: %d\n",
1756 rdlen, sdret);
1757 brcmu_pkt_buf_free_skb(*pkt);
1758 bus->drvr->rx_errors++;
1759 /* Force retry w/normal header read.
1760 * Don't attempt NAK for
1761 * gSPI
1762 */
1763 brcmf_sdbrcm_rxfail(bus, true, true);
1764 *pkt = NULL;
1765 }
1766 }
1767
1768 /* Checks the header */
1769 static int
1770 brcmf_check_rxbuf(struct brcmf_bus *bus, struct sk_buff *pkt, u8 *rxbuf,
1771 u8 rxseq, u16 nextlen, u16 *len)
1772 {
1773 u16 check;
1774 bool len_consistent; /* Result of comparing readahead len and
1775 len from hw-hdr */
1776
1777 memcpy(bus->rxhdr, rxbuf, SDPCM_HDRLEN);
1778
1779 /* Extract hardware header fields */
1780 *len = get_unaligned_le16(bus->rxhdr);
1781 check = get_unaligned_le16(bus->rxhdr + sizeof(u16));
1782
1783 /* All zeros means readahead info was bad */
1784 if (!(*len | check)) {
1785 brcmf_dbg(INFO, "(nextlen): read zeros in HW header???\n");
1786 goto fail;
1787 }
1788
1789 /* Validate check bytes */
1790 if ((u16)~(*len ^ check)) {
1791 brcmf_dbg(ERROR, "(nextlen): HW hdr error: nextlen/len/check 0x%04x/0x%04x/0x%04x\n",
1792 nextlen, *len, check);
1793 bus->rx_badhdr++;
1794 brcmf_sdbrcm_rxfail(bus, false, false);
1795 goto fail;
1796 }
1797
1798 /* Validate frame length */
1799 if (*len < SDPCM_HDRLEN) {
1800 brcmf_dbg(ERROR, "(nextlen): HW hdr length invalid: %d\n",
1801 *len);
1802 goto fail;
1803 }
1804
1805 /* Check for consistency with readahead info */
1806 len_consistent = (nextlen != (roundup(*len, 16) >> 4));
1807 if (len_consistent) {
1808 /* Mismatch, force retry w/normal
1809 header (may be >4K) */
1810 brcmf_dbg(ERROR, "(nextlen): mismatch, nextlen %d len %d rnd %d; expected rxseq %d\n",
1811 nextlen, *len, roundup(*len, 16),
1812 rxseq);
1813 brcmf_sdbrcm_rxfail(bus, true, true);
1814 goto fail;
1815 }
1816
1817 return 0;
1818
1819 fail:
1820 brcmf_sdbrcm_pktfree2(bus, pkt);
1821 return -EINVAL;
1822 }
1823
1824 /* Return true if there may be more frames to read */
1825 static uint
1826 brcmf_sdbrcm_readframes(struct brcmf_bus *bus, uint maxframes, bool *finished)
1827 {
1828 u16 len, check; /* Extracted hardware header fields */
1829 u8 chan, seq, doff; /* Extracted software header fields */
1830 u8 fcbits; /* Extracted fcbits from software header */
1831
1832 struct sk_buff *pkt; /* Packet for event or data frames */
1833 u16 pad; /* Number of pad bytes to read */
1834 u16 rdlen; /* Total number of bytes to read */
1835 u8 rxseq; /* Next sequence number to expect */
1836 uint rxleft = 0; /* Remaining number of frames allowed */
1837 int sdret; /* Return code from calls */
1838 u8 txmax; /* Maximum tx sequence offered */
1839 u8 *rxbuf;
1840 int ifidx = 0;
1841 uint rxcount = 0; /* Total frames read */
1842
1843 brcmf_dbg(TRACE, "Enter\n");
1844
1845 /* Not finished unless we encounter no more frames indication */
1846 *finished = false;
1847
1848 for (rxseq = bus->rx_seq, rxleft = maxframes;
1849 !bus->rxskip && rxleft && bus->drvr->busstate != BRCMF_BUS_DOWN;
1850 rxseq++, rxleft--) {
1851
1852 /* Handle glomming separately */
1853 if (bus->glom || bus->glomd) {
1854 u8 cnt;
1855 brcmf_dbg(GLOM, "calling rxglom: glomd %p, glom %p\n",
1856 bus->glomd, bus->glom);
1857 cnt = brcmf_sdbrcm_rxglom(bus, rxseq);
1858 brcmf_dbg(GLOM, "rxglom returned %d\n", cnt);
1859 rxseq += cnt - 1;
1860 rxleft = (rxleft > cnt) ? (rxleft - cnt) : 1;
1861 continue;
1862 }
1863
1864 /* Try doing single read if we can */
1865 if (bus->nextlen) {
1866 u16 nextlen = bus->nextlen;
1867 bus->nextlen = 0;
1868
1869 rdlen = len = nextlen << 4;
1870 brcmf_pad(bus, &pad, &rdlen);
1871
1872 /*
1873 * After the frame is received we have to
1874 * distinguish whether it is data
1875 * or non-data frame.
1876 */
1877 brcmf_alloc_pkt_and_read(bus, rdlen, &pkt, &rxbuf);
1878 if (pkt == NULL) {
1879 /* Give up on data, request rtx of events */
1880 brcmf_dbg(ERROR, "(nextlen): brcmf_alloc_pkt_and_read failed: len %d rdlen %d expected rxseq %d\n",
1881 len, rdlen, rxseq);
1882 continue;
1883 }
1884
1885 if (brcmf_check_rxbuf(bus, pkt, rxbuf, rxseq, nextlen,
1886 &len) < 0)
1887 continue;
1888
1889 /* Extract software header fields */
1890 chan = SDPCM_PACKET_CHANNEL(
1891 &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
1892 seq = SDPCM_PACKET_SEQUENCE(
1893 &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
1894 doff = SDPCM_DOFFSET_VALUE(
1895 &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
1896 txmax = SDPCM_WINDOW_VALUE(
1897 &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
1898
1899 bus->nextlen =
1900 bus->rxhdr[SDPCM_FRAMETAG_LEN +
1901 SDPCM_NEXTLEN_OFFSET];
1902 if ((bus->nextlen << 4) > MAX_RX_DATASZ) {
1903 brcmf_dbg(INFO, "(nextlen): got frame w/nextlen too large (%d), seq %d\n",
1904 bus->nextlen, seq);
1905 bus->nextlen = 0;
1906 }
1907
1908 bus->drvr->rx_readahead_cnt++;
1909
1910 /* Handle Flow Control */
1911 fcbits = SDPCM_FCMASK_VALUE(
1912 &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
1913
1914 if (bus->flowcontrol != fcbits) {
1915 if (~bus->flowcontrol & fcbits)
1916 bus->fc_xoff++;
1917
1918 if (bus->flowcontrol & ~fcbits)
1919 bus->fc_xon++;
1920
1921 bus->fc_rcvd++;
1922 bus->flowcontrol = fcbits;
1923 }
1924
1925 /* Check and update sequence number */
1926 if (rxseq != seq) {
1927 brcmf_dbg(INFO, "(nextlen): rx_seq %d, expected %d\n",
1928 seq, rxseq);
1929 bus->rx_badseq++;
1930 rxseq = seq;
1931 }
1932
1933 /* Check window for sanity */
1934 if ((u8) (txmax - bus->tx_seq) > 0x40) {
1935 brcmf_dbg(ERROR, "got unlikely tx max %d with tx_seq %d\n",
1936 txmax, bus->tx_seq);
1937 txmax = bus->tx_seq + 2;
1938 }
1939 bus->tx_max = txmax;
1940
1941 #ifdef BCMDBG
1942 if (BRCMF_BYTES_ON() && BRCMF_DATA_ON()) {
1943 printk(KERN_DEBUG "Rx Data:\n");
1944 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
1945 rxbuf, len);
1946 } else if (BRCMF_HDRS_ON()) {
1947 printk(KERN_DEBUG "RxHdr:\n");
1948 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
1949 bus->rxhdr, SDPCM_HDRLEN);
1950 }
1951 #endif
1952
1953 if (chan == SDPCM_CONTROL_CHANNEL) {
1954 brcmf_dbg(ERROR, "(nextlen): readahead on control packet %d?\n",
1955 seq);
1956 /* Force retry w/normal header read */
1957 bus->nextlen = 0;
1958 brcmf_sdbrcm_rxfail(bus, false, true);
1959 brcmf_sdbrcm_pktfree2(bus, pkt);
1960 continue;
1961 }
1962
1963 /* Validate data offset */
1964 if ((doff < SDPCM_HDRLEN) || (doff > len)) {
1965 brcmf_dbg(ERROR, "(nextlen): bad data offset %d: HW len %d min %d\n",
1966 doff, len, SDPCM_HDRLEN);
1967 brcmf_sdbrcm_rxfail(bus, false, false);
1968 brcmf_sdbrcm_pktfree2(bus, pkt);
1969 continue;
1970 }
1971
1972 /* All done with this one -- now deliver the packet */
1973 goto deliver;
1974 }
1975
1976 /* Read frame header (hardware and software) */
1977 sdret = brcmf_sdcard_recv_buf(bus->sdiodev, bus->sdiodev->sbwad,
1978 SDIO_FUNC_2, F2SYNC, bus->rxhdr,
1979 BRCMF_FIRSTREAD, NULL);
1980 bus->f2rxhdrs++;
1981
1982 if (sdret < 0) {
1983 brcmf_dbg(ERROR, "RXHEADER FAILED: %d\n", sdret);
1984 bus->rx_hdrfail++;
1985 brcmf_sdbrcm_rxfail(bus, true, true);
1986 continue;
1987 }
1988 #ifdef BCMDBG
1989 if (BRCMF_BYTES_ON() || BRCMF_HDRS_ON()) {
1990 printk(KERN_DEBUG "RxHdr:\n");
1991 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
1992 bus->rxhdr, SDPCM_HDRLEN);
1993 }
1994 #endif
1995
1996 /* Extract hardware header fields */
1997 len = get_unaligned_le16(bus->rxhdr);
1998 check = get_unaligned_le16(bus->rxhdr + sizeof(u16));
1999
2000 /* All zeros means no more frames */
2001 if (!(len | check)) {
2002 *finished = true;
2003 break;
2004 }
2005
2006 /* Validate check bytes */
2007 if ((u16) ~(len ^ check)) {
2008 brcmf_dbg(ERROR, "HW hdr err: len/check 0x%04x/0x%04x\n",
2009 len, check);
2010 bus->rx_badhdr++;
2011 brcmf_sdbrcm_rxfail(bus, false, false);
2012 continue;
2013 }
2014
2015 /* Validate frame length */
2016 if (len < SDPCM_HDRLEN) {
2017 brcmf_dbg(ERROR, "HW hdr length invalid: %d\n", len);
2018 continue;
2019 }
2020
2021 /* Extract software header fields */
2022 chan = SDPCM_PACKET_CHANNEL(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
2023 seq = SDPCM_PACKET_SEQUENCE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
2024 doff = SDPCM_DOFFSET_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
2025 txmax = SDPCM_WINDOW_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
2026
2027 /* Validate data offset */
2028 if ((doff < SDPCM_HDRLEN) || (doff > len)) {
2029 brcmf_dbg(ERROR, "Bad data offset %d: HW len %d, min %d seq %d\n",
2030 doff, len, SDPCM_HDRLEN, seq);
2031 bus->rx_badhdr++;
2032 brcmf_sdbrcm_rxfail(bus, false, false);
2033 continue;
2034 }
2035
2036 /* Save the readahead length if there is one */
2037 bus->nextlen =
2038 bus->rxhdr[SDPCM_FRAMETAG_LEN + SDPCM_NEXTLEN_OFFSET];
2039 if ((bus->nextlen << 4) > MAX_RX_DATASZ) {
2040 brcmf_dbg(INFO, "(nextlen): got frame w/nextlen too large (%d), seq %d\n",
2041 bus->nextlen, seq);
2042 bus->nextlen = 0;
2043 }
2044
2045 /* Handle Flow Control */
2046 fcbits = SDPCM_FCMASK_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
2047
2048 if (bus->flowcontrol != fcbits) {
2049 if (~bus->flowcontrol & fcbits)
2050 bus->fc_xoff++;
2051
2052 if (bus->flowcontrol & ~fcbits)
2053 bus->fc_xon++;
2054
2055 bus->fc_rcvd++;
2056 bus->flowcontrol = fcbits;
2057 }
2058
2059 /* Check and update sequence number */
2060 if (rxseq != seq) {
2061 brcmf_dbg(INFO, "rx_seq %d, expected %d\n", seq, rxseq);
2062 bus->rx_badseq++;
2063 rxseq = seq;
2064 }
2065
2066 /* Check window for sanity */
2067 if ((u8) (txmax - bus->tx_seq) > 0x40) {
2068 brcmf_dbg(ERROR, "unlikely tx max %d with tx_seq %d\n",
2069 txmax, bus->tx_seq);
2070 txmax = bus->tx_seq + 2;
2071 }
2072 bus->tx_max = txmax;
2073
2074 /* Call a separate function for control frames */
2075 if (chan == SDPCM_CONTROL_CHANNEL) {
2076 brcmf_sdbrcm_read_control(bus, bus->rxhdr, len, doff);
2077 continue;
2078 }
2079
2080 /* precondition: chan is either SDPCM_DATA_CHANNEL,
2081 SDPCM_EVENT_CHANNEL, SDPCM_TEST_CHANNEL or
2082 SDPCM_GLOM_CHANNEL */
2083
2084 /* Length to read */
2085 rdlen = (len > BRCMF_FIRSTREAD) ? (len - BRCMF_FIRSTREAD) : 0;
2086
2087 /* May pad read to blocksize for efficiency */
2088 if (bus->roundup && bus->blocksize &&
2089 (rdlen > bus->blocksize)) {
2090 pad = bus->blocksize - (rdlen % bus->blocksize);
2091 if ((pad <= bus->roundup) && (pad < bus->blocksize) &&
2092 ((rdlen + pad + BRCMF_FIRSTREAD) < MAX_RX_DATASZ))
2093 rdlen += pad;
2094 } else if (rdlen % BRCMF_SDALIGN) {
2095 rdlen += BRCMF_SDALIGN - (rdlen % BRCMF_SDALIGN);
2096 }
2097
2098 /* Satisfy length-alignment requirements */
2099 if (rdlen & (ALIGNMENT - 1))
2100 rdlen = roundup(rdlen, ALIGNMENT);
2101
2102 if ((rdlen + BRCMF_FIRSTREAD) > MAX_RX_DATASZ) {
2103 /* Too long -- skip this frame */
2104 brcmf_dbg(ERROR, "too long: len %d rdlen %d\n",
2105 len, rdlen);
2106 bus->drvr->rx_errors++;
2107 bus->rx_toolong++;
2108 brcmf_sdbrcm_rxfail(bus, false, false);
2109 continue;
2110 }
2111
2112 pkt = brcmu_pkt_buf_get_skb(rdlen +
2113 BRCMF_FIRSTREAD + BRCMF_SDALIGN);
2114 if (!pkt) {
2115 /* Give up on data, request rtx of events */
2116 brcmf_dbg(ERROR, "brcmu_pkt_buf_get_skb failed: rdlen %d chan %d\n",
2117 rdlen, chan);
2118 bus->drvr->rx_dropped++;
2119 brcmf_sdbrcm_rxfail(bus, false, RETRYCHAN(chan));
2120 continue;
2121 }
2122
2123 /* Leave room for what we already read, and align remainder */
2124 skb_pull(pkt, BRCMF_FIRSTREAD);
2125 pkt_align(pkt, rdlen, BRCMF_SDALIGN);
2126
2127 /* Read the remaining frame data */
2128 sdret = brcmf_sdcard_recv_buf(bus->sdiodev, bus->sdiodev->sbwad,
2129 SDIO_FUNC_2, F2SYNC, ((u8 *) (pkt->data)),
2130 rdlen, pkt);
2131 bus->f2rxdata++;
2132
2133 if (sdret < 0) {
2134 brcmf_dbg(ERROR, "read %d %s bytes failed: %d\n", rdlen,
2135 ((chan == SDPCM_EVENT_CHANNEL) ? "event"
2136 : ((chan == SDPCM_DATA_CHANNEL) ? "data"
2137 : "test")), sdret);
2138 brcmu_pkt_buf_free_skb(pkt);
2139 bus->drvr->rx_errors++;
2140 brcmf_sdbrcm_rxfail(bus, true, RETRYCHAN(chan));
2141 continue;
2142 }
2143
2144 /* Copy the already-read portion */
2145 skb_push(pkt, BRCMF_FIRSTREAD);
2146 memcpy(pkt->data, bus->rxhdr, BRCMF_FIRSTREAD);
2147
2148 #ifdef BCMDBG
2149 if (BRCMF_BYTES_ON() && BRCMF_DATA_ON()) {
2150 printk(KERN_DEBUG "Rx Data:\n");
2151 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
2152 pkt->data, len);
2153 }
2154 #endif
2155
2156 deliver:
2157 /* Save superframe descriptor and allocate packet frame */
2158 if (chan == SDPCM_GLOM_CHANNEL) {
2159 if (SDPCM_GLOMDESC(&bus->rxhdr[SDPCM_FRAMETAG_LEN])) {
2160 brcmf_dbg(GLOM, "glom descriptor, %d bytes:\n",
2161 len);
2162 #ifdef BCMDBG
2163 if (BRCMF_GLOM_ON()) {
2164 printk(KERN_DEBUG "Glom Data:\n");
2165 print_hex_dump_bytes("",
2166 DUMP_PREFIX_OFFSET,
2167 pkt->data, len);
2168 }
2169 #endif
2170 __skb_trim(pkt, len);
2171 skb_pull(pkt, SDPCM_HDRLEN);
2172 bus->glomd = pkt;
2173 } else {
2174 brcmf_dbg(ERROR, "%s: glom superframe w/o "
2175 "descriptor!\n", __func__);
2176 brcmf_sdbrcm_rxfail(bus, false, false);
2177 }
2178 continue;
2179 }
2180
2181 /* Fill in packet len and prio, deliver upward */
2182 __skb_trim(pkt, len);
2183 skb_pull(pkt, doff);
2184
2185 if (pkt->len == 0) {
2186 brcmu_pkt_buf_free_skb(pkt);
2187 continue;
2188 } else if (brcmf_proto_hdrpull(bus->drvr, &ifidx, pkt) != 0) {
2189 brcmf_dbg(ERROR, "rx protocol error\n");
2190 brcmu_pkt_buf_free_skb(pkt);
2191 bus->drvr->rx_errors++;
2192 continue;
2193 }
2194
2195 /* Unlock during rx call */
2196 up(&bus->sdsem);
2197 brcmf_rx_frame(bus->drvr, ifidx, pkt, 1);
2198 down(&bus->sdsem);
2199 }
2200 rxcount = maxframes - rxleft;
2201 #ifdef BCMDBG
2202 /* Message if we hit the limit */
2203 if (!rxleft)
2204 brcmf_dbg(DATA, "hit rx limit of %d frames\n",
2205 maxframes);
2206 else
2207 #endif /* BCMDBG */
2208 brcmf_dbg(DATA, "processed %d frames\n", rxcount);
2209 /* Back off rxseq if awaiting rtx, update rx_seq */
2210 if (bus->rxskip)
2211 rxseq--;
2212 bus->rx_seq = rxseq;
2213
2214 return rxcount;
2215 }
2216
2217 static int
2218 brcmf_sdbrcm_send_buf(struct brcmf_bus *bus, u32 addr, uint fn, uint flags,
2219 u8 *buf, uint nbytes, struct sk_buff *pkt)
2220 {
2221 return brcmf_sdcard_send_buf
2222 (bus->sdiodev, addr, fn, flags, buf, nbytes, pkt);
2223 }
2224
2225 static void
2226 brcmf_sdbrcm_wait_for_event(struct brcmf_bus *bus, bool *lockvar)
2227 {
2228 up(&bus->sdsem);
2229 wait_event_interruptible_timeout(bus->ctrl_wait,
2230 (*lockvar == false), HZ * 2);
2231 down(&bus->sdsem);
2232 return;
2233 }
2234
2235 static void
2236 brcmf_sdbrcm_wait_event_wakeup(struct brcmf_bus *bus)
2237 {
2238 if (waitqueue_active(&bus->ctrl_wait))
2239 wake_up_interruptible(&bus->ctrl_wait);
2240 return;
2241 }
2242
2243 /* Writes a HW/SW header into the packet and sends it. */
2244 /* Assumes: (a) header space already there, (b) caller holds lock */
2245 static int brcmf_sdbrcm_txpkt(struct brcmf_bus *bus, struct sk_buff *pkt,
2246 uint chan, bool free_pkt)
2247 {
2248 int ret;
2249 u8 *frame;
2250 u16 len, pad = 0;
2251 u32 swheader;
2252 struct sk_buff *new;
2253 int i;
2254
2255 brcmf_dbg(TRACE, "Enter\n");
2256
2257 frame = (u8 *) (pkt->data);
2258
2259 /* Add alignment padding, allocate new packet if needed */
2260 pad = ((unsigned long)frame % BRCMF_SDALIGN);
2261 if (pad) {
2262 if (skb_headroom(pkt) < pad) {
2263 brcmf_dbg(INFO, "insufficient headroom %d for %d pad\n",
2264 skb_headroom(pkt), pad);
2265 bus->drvr->tx_realloc++;
2266 new = brcmu_pkt_buf_get_skb(pkt->len + BRCMF_SDALIGN);
2267 if (!new) {
2268 brcmf_dbg(ERROR, "couldn't allocate new %d-byte packet\n",
2269 pkt->len + BRCMF_SDALIGN);
2270 ret = -ENOMEM;
2271 goto done;
2272 }
2273
2274 pkt_align(new, pkt->len, BRCMF_SDALIGN);
2275 memcpy(new->data, pkt->data, pkt->len);
2276 if (free_pkt)
2277 brcmu_pkt_buf_free_skb(pkt);
2278 /* free the pkt if canned one is not used */
2279 free_pkt = true;
2280 pkt = new;
2281 frame = (u8 *) (pkt->data);
2282 /* precondition: (frame % BRCMF_SDALIGN) == 0) */
2283 pad = 0;
2284 } else {
2285 skb_push(pkt, pad);
2286 frame = (u8 *) (pkt->data);
2287 /* precondition: pad + SDPCM_HDRLEN <= pkt->len */
2288 memset(frame, 0, pad + SDPCM_HDRLEN);
2289 }
2290 }
2291 /* precondition: pad < BRCMF_SDALIGN */
2292
2293 /* Hardware tag: 2 byte len followed by 2 byte ~len check (all LE) */
2294 len = (u16) (pkt->len);
2295 *(__le16 *) frame = cpu_to_le16(len);
2296 *(((__le16 *) frame) + 1) = cpu_to_le16(~len);
2297
2298 /* Software tag: channel, sequence number, data offset */
2299 swheader =
2300 ((chan << SDPCM_CHANNEL_SHIFT) & SDPCM_CHANNEL_MASK) | bus->tx_seq |
2301 (((pad +
2302 SDPCM_HDRLEN) << SDPCM_DOFFSET_SHIFT) & SDPCM_DOFFSET_MASK);
2303
2304 put_unaligned_le32(swheader, frame + SDPCM_FRAMETAG_LEN);
2305 put_unaligned_le32(0, frame + SDPCM_FRAMETAG_LEN + sizeof(swheader));
2306
2307 #ifdef BCMDBG
2308 tx_packets[pkt->priority]++;
2309 if (BRCMF_BYTES_ON() &&
2310 (((BRCMF_CTL_ON() && (chan == SDPCM_CONTROL_CHANNEL)) ||
2311 (BRCMF_DATA_ON() && (chan != SDPCM_CONTROL_CHANNEL))))) {
2312 printk(KERN_DEBUG "Tx Frame:\n");
2313 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, frame, len);
2314 } else if (BRCMF_HDRS_ON()) {
2315 printk(KERN_DEBUG "TxHdr:\n");
2316 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
2317 frame, min_t(u16, len, 16));
2318 }
2319 #endif
2320
2321 /* Raise len to next SDIO block to eliminate tail command */
2322 if (bus->roundup && bus->blocksize && (len > bus->blocksize)) {
2323 u16 pad = bus->blocksize - (len % bus->blocksize);
2324 if ((pad <= bus->roundup) && (pad < bus->blocksize))
2325 len += pad;
2326 } else if (len % BRCMF_SDALIGN) {
2327 len += BRCMF_SDALIGN - (len % BRCMF_SDALIGN);
2328 }
2329
2330 /* Some controllers have trouble with odd bytes -- round to even */
2331 if (len & (ALIGNMENT - 1))
2332 len = roundup(len, ALIGNMENT);
2333
2334 ret = brcmf_sdbrcm_send_buf(bus, bus->sdiodev->sbwad,
2335 SDIO_FUNC_2, F2SYNC, frame,
2336 len, pkt);
2337 bus->f2txdata++;
2338
2339 if (ret < 0) {
2340 /* On failure, abort the command and terminate the frame */
2341 brcmf_dbg(INFO, "sdio error %d, abort command and terminate frame\n",
2342 ret);
2343 bus->tx_sderrs++;
2344
2345 brcmf_sdcard_abort(bus->sdiodev, SDIO_FUNC_2);
2346 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
2347 SBSDIO_FUNC1_FRAMECTRL, SFC_WF_TERM,
2348 NULL);
2349 bus->f1regdata++;
2350
2351 for (i = 0; i < 3; i++) {
2352 u8 hi, lo;
2353 hi = brcmf_sdcard_cfg_read(bus->sdiodev,
2354 SDIO_FUNC_1,
2355 SBSDIO_FUNC1_WFRAMEBCHI,
2356 NULL);
2357 lo = brcmf_sdcard_cfg_read(bus->sdiodev,
2358 SDIO_FUNC_1,
2359 SBSDIO_FUNC1_WFRAMEBCLO,
2360 NULL);
2361 bus->f1regdata += 2;
2362 if ((hi == 0) && (lo == 0))
2363 break;
2364 }
2365
2366 }
2367 if (ret == 0)
2368 bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
2369
2370 done:
2371 /* restore pkt buffer pointer before calling tx complete routine */
2372 skb_pull(pkt, SDPCM_HDRLEN + pad);
2373 up(&bus->sdsem);
2374 brcmf_txcomplete(bus->drvr, pkt, ret != 0);
2375 down(&bus->sdsem);
2376
2377 if (free_pkt)
2378 brcmu_pkt_buf_free_skb(pkt);
2379
2380 return ret;
2381 }
2382
2383 static uint brcmf_sdbrcm_sendfromq(struct brcmf_bus *bus, uint maxframes)
2384 {
2385 struct sk_buff *pkt;
2386 u32 intstatus = 0;
2387 uint retries = 0;
2388 int ret = 0, prec_out;
2389 uint cnt = 0;
2390 uint datalen;
2391 u8 tx_prec_map;
2392
2393 struct brcmf_pub *drvr = bus->drvr;
2394
2395 brcmf_dbg(TRACE, "Enter\n");
2396
2397 tx_prec_map = ~bus->flowcontrol;
2398
2399 /* Send frames until the limit or some other event */
2400 for (cnt = 0; (cnt < maxframes) && data_ok(bus); cnt++) {
2401 spin_lock_bh(&bus->txqlock);
2402 pkt = brcmu_pktq_mdeq(&bus->txq, tx_prec_map, &prec_out);
2403 if (pkt == NULL) {
2404 spin_unlock_bh(&bus->txqlock);
2405 break;
2406 }
2407 spin_unlock_bh(&bus->txqlock);
2408 datalen = pkt->len - SDPCM_HDRLEN;
2409
2410 ret = brcmf_sdbrcm_txpkt(bus, pkt, SDPCM_DATA_CHANNEL, true);
2411 if (ret)
2412 bus->drvr->tx_errors++;
2413 else
2414 bus->drvr->dstats.tx_bytes += datalen;
2415
2416 /* In poll mode, need to check for other events */
2417 if (!bus->intr && cnt) {
2418 /* Check device status, signal pending interrupt */
2419 r_sdreg32(bus, &intstatus,
2420 offsetof(struct sdpcmd_regs, intstatus),
2421 &retries);
2422 bus->f2txdata++;
2423 if (brcmf_sdcard_regfail(bus->sdiodev))
2424 break;
2425 if (intstatus & bus->hostintmask)
2426 bus->ipend = true;
2427 }
2428 }
2429
2430 /* Deflow-control stack if needed */
2431 if (drvr->up && (drvr->busstate == BRCMF_BUS_DATA) &&
2432 drvr->txoff && (pktq_len(&bus->txq) < TXLOW))
2433 brcmf_txflowcontrol(drvr, 0, OFF);
2434
2435 return cnt;
2436 }
2437
2438 static bool brcmf_sdbrcm_dpc(struct brcmf_bus *bus)
2439 {
2440 u32 intstatus, newstatus = 0;
2441 uint retries = 0;
2442 uint rxlimit = bus->rxbound; /* Rx frames to read before resched */
2443 uint txlimit = bus->txbound; /* Tx frames to send before resched */
2444 uint framecnt = 0; /* Temporary counter of tx/rx frames */
2445 bool rxdone = true; /* Flag for no more read data */
2446 bool resched = false; /* Flag indicating resched wanted */
2447
2448 brcmf_dbg(TRACE, "Enter\n");
2449
2450 /* Start with leftover status bits */
2451 intstatus = bus->intstatus;
2452
2453 down(&bus->sdsem);
2454
2455 /* If waiting for HTAVAIL, check status */
2456 if (bus->clkstate == CLK_PENDING) {
2457 int err;
2458 u8 clkctl, devctl = 0;
2459
2460 #ifdef BCMDBG
2461 /* Check for inconsistent device control */
2462 devctl = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
2463 SBSDIO_DEVICE_CTL, &err);
2464 if (err) {
2465 brcmf_dbg(ERROR, "error reading DEVCTL: %d\n", err);
2466 bus->drvr->busstate = BRCMF_BUS_DOWN;
2467 }
2468 #endif /* BCMDBG */
2469
2470 /* Read CSR, if clock on switch to AVAIL, else ignore */
2471 clkctl = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
2472 SBSDIO_FUNC1_CHIPCLKCSR, &err);
2473 if (err) {
2474 brcmf_dbg(ERROR, "error reading CSR: %d\n",
2475 err);
2476 bus->drvr->busstate = BRCMF_BUS_DOWN;
2477 }
2478
2479 brcmf_dbg(INFO, "DPC: PENDING, devctl 0x%02x clkctl 0x%02x\n",
2480 devctl, clkctl);
2481
2482 if (SBSDIO_HTAV(clkctl)) {
2483 devctl = brcmf_sdcard_cfg_read(bus->sdiodev,
2484 SDIO_FUNC_1,
2485 SBSDIO_DEVICE_CTL, &err);
2486 if (err) {
2487 brcmf_dbg(ERROR, "error reading DEVCTL: %d\n",
2488 err);
2489 bus->drvr->busstate = BRCMF_BUS_DOWN;
2490 }
2491 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
2492 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
2493 SBSDIO_DEVICE_CTL, devctl, &err);
2494 if (err) {
2495 brcmf_dbg(ERROR, "error writing DEVCTL: %d\n",
2496 err);
2497 bus->drvr->busstate = BRCMF_BUS_DOWN;
2498 }
2499 bus->clkstate = CLK_AVAIL;
2500 } else {
2501 goto clkwait;
2502 }
2503 }
2504
2505 bus_wake(bus);
2506
2507 /* Make sure backplane clock is on */
2508 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, true);
2509 if (bus->clkstate == CLK_PENDING)
2510 goto clkwait;
2511
2512 /* Pending interrupt indicates new device status */
2513 if (bus->ipend) {
2514 bus->ipend = false;
2515 r_sdreg32(bus, &newstatus,
2516 offsetof(struct sdpcmd_regs, intstatus), &retries);
2517 bus->f1regdata++;
2518 if (brcmf_sdcard_regfail(bus->sdiodev))
2519 newstatus = 0;
2520 newstatus &= bus->hostintmask;
2521 bus->fcstate = !!(newstatus & I_HMB_FC_STATE);
2522 if (newstatus) {
2523 w_sdreg32(bus, newstatus,
2524 offsetof(struct sdpcmd_regs, intstatus),
2525 &retries);
2526 bus->f1regdata++;
2527 }
2528 }
2529
2530 /* Merge new bits with previous */
2531 intstatus |= newstatus;
2532 bus->intstatus = 0;
2533
2534 /* Handle flow-control change: read new state in case our ack
2535 * crossed another change interrupt. If change still set, assume
2536 * FC ON for safety, let next loop through do the debounce.
2537 */
2538 if (intstatus & I_HMB_FC_CHANGE) {
2539 intstatus &= ~I_HMB_FC_CHANGE;
2540 w_sdreg32(bus, I_HMB_FC_CHANGE,
2541 offsetof(struct sdpcmd_regs, intstatus), &retries);
2542
2543 r_sdreg32(bus, &newstatus,
2544 offsetof(struct sdpcmd_regs, intstatus), &retries);
2545 bus->f1regdata += 2;
2546 bus->fcstate =
2547 !!(newstatus & (I_HMB_FC_STATE | I_HMB_FC_CHANGE));
2548 intstatus |= (newstatus & bus->hostintmask);
2549 }
2550
2551 /* Handle host mailbox indication */
2552 if (intstatus & I_HMB_HOST_INT) {
2553 intstatus &= ~I_HMB_HOST_INT;
2554 intstatus |= brcmf_sdbrcm_hostmail(bus);
2555 }
2556
2557 /* Generally don't ask for these, can get CRC errors... */
2558 if (intstatus & I_WR_OOSYNC) {
2559 brcmf_dbg(ERROR, "Dongle reports WR_OOSYNC\n");
2560 intstatus &= ~I_WR_OOSYNC;
2561 }
2562
2563 if (intstatus & I_RD_OOSYNC) {
2564 brcmf_dbg(ERROR, "Dongle reports RD_OOSYNC\n");
2565 intstatus &= ~I_RD_OOSYNC;
2566 }
2567
2568 if (intstatus & I_SBINT) {
2569 brcmf_dbg(ERROR, "Dongle reports SBINT\n");
2570 intstatus &= ~I_SBINT;
2571 }
2572
2573 /* Would be active due to wake-wlan in gSPI */
2574 if (intstatus & I_CHIPACTIVE) {
2575 brcmf_dbg(INFO, "Dongle reports CHIPACTIVE\n");
2576 intstatus &= ~I_CHIPACTIVE;
2577 }
2578
2579 /* Ignore frame indications if rxskip is set */
2580 if (bus->rxskip)
2581 intstatus &= ~I_HMB_FRAME_IND;
2582
2583 /* On frame indication, read available frames */
2584 if (PKT_AVAILABLE()) {
2585 framecnt = brcmf_sdbrcm_readframes(bus, rxlimit, &rxdone);
2586 if (rxdone || bus->rxskip)
2587 intstatus &= ~I_HMB_FRAME_IND;
2588 rxlimit -= min(framecnt, rxlimit);
2589 }
2590
2591 /* Keep still-pending events for next scheduling */
2592 bus->intstatus = intstatus;
2593
2594 clkwait:
2595 if (data_ok(bus) && bus->ctrl_frame_stat &&
2596 (bus->clkstate == CLK_AVAIL)) {
2597 int ret, i;
2598
2599 ret = brcmf_sdbrcm_send_buf(bus, bus->sdiodev->sbwad,
2600 SDIO_FUNC_2, F2SYNC, (u8 *) bus->ctrl_frame_buf,
2601 (u32) bus->ctrl_frame_len, NULL);
2602
2603 if (ret < 0) {
2604 /* On failure, abort the command and
2605 terminate the frame */
2606 brcmf_dbg(INFO, "sdio error %d, abort command and terminate frame\n",
2607 ret);
2608 bus->tx_sderrs++;
2609
2610 brcmf_sdcard_abort(bus->sdiodev, SDIO_FUNC_2);
2611
2612 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
2613 SBSDIO_FUNC1_FRAMECTRL, SFC_WF_TERM,
2614 NULL);
2615 bus->f1regdata++;
2616
2617 for (i = 0; i < 3; i++) {
2618 u8 hi, lo;
2619 hi = brcmf_sdcard_cfg_read(bus->sdiodev,
2620 SDIO_FUNC_1,
2621 SBSDIO_FUNC1_WFRAMEBCHI,
2622 NULL);
2623 lo = brcmf_sdcard_cfg_read(bus->sdiodev,
2624 SDIO_FUNC_1,
2625 SBSDIO_FUNC1_WFRAMEBCLO,
2626 NULL);
2627 bus->f1regdata += 2;
2628 if ((hi == 0) && (lo == 0))
2629 break;
2630 }
2631
2632 }
2633 if (ret == 0)
2634 bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
2635
2636 brcmf_dbg(INFO, "Return_dpc value is : %d\n", ret);
2637 bus->ctrl_frame_stat = false;
2638 brcmf_sdbrcm_wait_event_wakeup(bus);
2639 }
2640 /* Send queued frames (limit 1 if rx may still be pending) */
2641 else if ((bus->clkstate == CLK_AVAIL) && !bus->fcstate &&
2642 brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol) && txlimit
2643 && data_ok(bus)) {
2644 framecnt = rxdone ? txlimit : min(txlimit, bus->txminmax);
2645 framecnt = brcmf_sdbrcm_sendfromq(bus, framecnt);
2646 txlimit -= framecnt;
2647 }
2648
2649 /* Resched if events or tx frames are pending,
2650 else await next interrupt */
2651 /* On failed register access, all bets are off:
2652 no resched or interrupts */
2653 if ((bus->drvr->busstate == BRCMF_BUS_DOWN) ||
2654 brcmf_sdcard_regfail(bus->sdiodev)) {
2655 brcmf_dbg(ERROR, "failed backplane access over SDIO, halting operation %d\n",
2656 brcmf_sdcard_regfail(bus->sdiodev));
2657 bus->drvr->busstate = BRCMF_BUS_DOWN;
2658 bus->intstatus = 0;
2659 } else if (bus->clkstate == CLK_PENDING) {
2660 brcmf_dbg(INFO, "rescheduled due to CLK_PENDING awaiting I_CHIPACTIVE interrupt\n");
2661 resched = true;
2662 } else if (bus->intstatus || bus->ipend ||
2663 (!bus->fcstate && brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol)
2664 && data_ok(bus)) || PKT_AVAILABLE()) {
2665 resched = true;
2666 }
2667
2668 bus->dpc_sched = resched;
2669
2670 /* If we're done for now, turn off clock request. */
2671 if ((bus->clkstate != CLK_PENDING)
2672 && bus->idletime == BRCMF_IDLE_IMMEDIATE) {
2673 bus->activity = false;
2674 brcmf_sdbrcm_clkctl(bus, CLK_NONE, false);
2675 }
2676
2677 up(&bus->sdsem);
2678
2679 return resched;
2680 }
2681
2682 static int brcmf_sdbrcm_dpc_thread(void *data)
2683 {
2684 struct brcmf_bus *bus = (struct brcmf_bus *) data;
2685
2686 allow_signal(SIGTERM);
2687 /* Run until signal received */
2688 while (1) {
2689 if (kthread_should_stop())
2690 break;
2691 if (!wait_for_completion_interruptible(&bus->dpc_wait)) {
2692 /* Call bus dpc unless it indicated down
2693 (then clean stop) */
2694 if (bus->drvr->busstate != BRCMF_BUS_DOWN) {
2695 if (brcmf_sdbrcm_dpc(bus))
2696 complete(&bus->dpc_wait);
2697 } else {
2698 /* after stopping the bus, exit thread */
2699 brcmf_sdbrcm_bus_stop(bus);
2700 bus->dpc_tsk = NULL;
2701 break;
2702 }
2703 } else
2704 break;
2705 }
2706 return 0;
2707 }
2708
2709 int brcmf_sdbrcm_bus_txdata(struct brcmf_bus *bus, struct sk_buff *pkt)
2710 {
2711 int ret = -EBADE;
2712 uint datalen, prec;
2713
2714 brcmf_dbg(TRACE, "Enter\n");
2715
2716 datalen = pkt->len;
2717
2718 /* Add space for the header */
2719 skb_push(pkt, SDPCM_HDRLEN);
2720 /* precondition: IS_ALIGNED((unsigned long)(pkt->data), 2) */
2721
2722 prec = prio2prec((pkt->priority & PRIOMASK));
2723
2724 /* Check for existing queue, current flow-control,
2725 pending event, or pending clock */
2726 brcmf_dbg(TRACE, "deferring pktq len %d\n", pktq_len(&bus->txq));
2727 bus->fcqueued++;
2728
2729 /* Priority based enq */
2730 spin_lock_bh(&bus->txqlock);
2731 if (brcmf_c_prec_enq(bus->drvr, &bus->txq, pkt, prec) == false) {
2732 skb_pull(pkt, SDPCM_HDRLEN);
2733 brcmf_txcomplete(bus->drvr, pkt, false);
2734 brcmu_pkt_buf_free_skb(pkt);
2735 brcmf_dbg(ERROR, "out of bus->txq !!!\n");
2736 ret = -ENOSR;
2737 } else {
2738 ret = 0;
2739 }
2740 spin_unlock_bh(&bus->txqlock);
2741
2742 if (pktq_len(&bus->txq) >= TXHI)
2743 brcmf_txflowcontrol(bus->drvr, 0, ON);
2744
2745 #ifdef BCMDBG
2746 if (pktq_plen(&bus->txq, prec) > qcount[prec])
2747 qcount[prec] = pktq_plen(&bus->txq, prec);
2748 #endif
2749 /* Schedule DPC if needed to send queued packet(s) */
2750 if (!bus->dpc_sched) {
2751 bus->dpc_sched = true;
2752 if (bus->dpc_tsk)
2753 complete(&bus->dpc_wait);
2754 }
2755
2756 return ret;
2757 }
2758
2759 static int
2760 brcmf_sdbrcm_membytes(struct brcmf_bus *bus, bool write, u32 address, u8 *data,
2761 uint size)
2762 {
2763 int bcmerror = 0;
2764 u32 sdaddr;
2765 uint dsize;
2766
2767 /* Determine initial transfer parameters */
2768 sdaddr = address & SBSDIO_SB_OFT_ADDR_MASK;
2769 if ((sdaddr + size) & SBSDIO_SBWINDOW_MASK)
2770 dsize = (SBSDIO_SB_OFT_ADDR_LIMIT - sdaddr);
2771 else
2772 dsize = size;
2773
2774 /* Set the backplane window to include the start address */
2775 bcmerror = brcmf_sdcard_set_sbaddr_window(bus->sdiodev, address);
2776 if (bcmerror) {
2777 brcmf_dbg(ERROR, "window change failed\n");
2778 goto xfer_done;
2779 }
2780
2781 /* Do the transfer(s) */
2782 while (size) {
2783 brcmf_dbg(INFO, "%s %d bytes at offset 0x%08x in window 0x%08x\n",
2784 write ? "write" : "read", dsize,
2785 sdaddr, address & SBSDIO_SBWINDOW_MASK);
2786 bcmerror = brcmf_sdcard_rwdata(bus->sdiodev, write,
2787 sdaddr, data, dsize);
2788 if (bcmerror) {
2789 brcmf_dbg(ERROR, "membytes transfer failed\n");
2790 break;
2791 }
2792
2793 /* Adjust for next transfer (if any) */
2794 size -= dsize;
2795 if (size) {
2796 data += dsize;
2797 address += dsize;
2798 bcmerror = brcmf_sdcard_set_sbaddr_window(bus->sdiodev,
2799 address);
2800 if (bcmerror) {
2801 brcmf_dbg(ERROR, "window change failed\n");
2802 break;
2803 }
2804 sdaddr = 0;
2805 dsize = min_t(uint, SBSDIO_SB_OFT_ADDR_LIMIT, size);
2806 }
2807 }
2808
2809 xfer_done:
2810 /* Return the window to backplane enumeration space for core access */
2811 if (brcmf_sdcard_set_sbaddr_window(bus->sdiodev, bus->sdiodev->sbwad))
2812 brcmf_dbg(ERROR, "FAILED to set window back to 0x%x\n",
2813 bus->sdiodev->sbwad);
2814
2815 return bcmerror;
2816 }
2817
2818 #ifdef BCMDBG
2819 #define CONSOLE_LINE_MAX 192
2820
2821 static int brcmf_sdbrcm_readconsole(struct brcmf_bus *bus)
2822 {
2823 struct brcmf_console *c = &bus->console;
2824 u8 line[CONSOLE_LINE_MAX], ch;
2825 u32 n, idx, addr;
2826 int rv;
2827
2828 /* Don't do anything until FWREADY updates console address */
2829 if (bus->console_addr == 0)
2830 return 0;
2831
2832 /* Read console log struct */
2833 addr = bus->console_addr + offsetof(struct rte_console, log_le);
2834 rv = brcmf_sdbrcm_membytes(bus, false, addr, (u8 *)&c->log_le,
2835 sizeof(c->log_le));
2836 if (rv < 0)
2837 return rv;
2838
2839 /* Allocate console buffer (one time only) */
2840 if (c->buf == NULL) {
2841 c->bufsize = le32_to_cpu(c->log_le.buf_size);
2842 c->buf = kmalloc(c->bufsize, GFP_ATOMIC);
2843 if (c->buf == NULL)
2844 return -ENOMEM;
2845 }
2846
2847 idx = le32_to_cpu(c->log_le.idx);
2848
2849 /* Protect against corrupt value */
2850 if (idx > c->bufsize)
2851 return -EBADE;
2852
2853 /* Skip reading the console buffer if the index pointer
2854 has not moved */
2855 if (idx == c->last)
2856 return 0;
2857
2858 /* Read the console buffer */
2859 addr = le32_to_cpu(c->log_le.buf);
2860 rv = brcmf_sdbrcm_membytes(bus, false, addr, c->buf, c->bufsize);
2861 if (rv < 0)
2862 return rv;
2863
2864 while (c->last != idx) {
2865 for (n = 0; n < CONSOLE_LINE_MAX - 2; n++) {
2866 if (c->last == idx) {
2867 /* This would output a partial line.
2868 * Instead, back up
2869 * the buffer pointer and output this
2870 * line next time around.
2871 */
2872 if (c->last >= n)
2873 c->last -= n;
2874 else
2875 c->last = c->bufsize - n;
2876 goto break2;
2877 }
2878 ch = c->buf[c->last];
2879 c->last = (c->last + 1) % c->bufsize;
2880 if (ch == '\n')
2881 break;
2882 line[n] = ch;
2883 }
2884
2885 if (n > 0) {
2886 if (line[n - 1] == '\r')
2887 n--;
2888 line[n] = 0;
2889 printk(KERN_DEBUG "CONSOLE: %s\n", line);
2890 }
2891 }
2892 break2:
2893
2894 return 0;
2895 }
2896 #endif /* BCMDBG */
2897
2898 static int brcmf_tx_frame(struct brcmf_bus *bus, u8 *frame, u16 len)
2899 {
2900 int i;
2901 int ret;
2902
2903 bus->ctrl_frame_stat = false;
2904 ret = brcmf_sdbrcm_send_buf(bus, bus->sdiodev->sbwad,
2905 SDIO_FUNC_2, F2SYNC, frame, len, NULL);
2906
2907 if (ret < 0) {
2908 /* On failure, abort the command and terminate the frame */
2909 brcmf_dbg(INFO, "sdio error %d, abort command and terminate frame\n",
2910 ret);
2911 bus->tx_sderrs++;
2912
2913 brcmf_sdcard_abort(bus->sdiodev, SDIO_FUNC_2);
2914
2915 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
2916 SBSDIO_FUNC1_FRAMECTRL,
2917 SFC_WF_TERM, NULL);
2918 bus->f1regdata++;
2919
2920 for (i = 0; i < 3; i++) {
2921 u8 hi, lo;
2922 hi = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
2923 SBSDIO_FUNC1_WFRAMEBCHI,
2924 NULL);
2925 lo = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
2926 SBSDIO_FUNC1_WFRAMEBCLO,
2927 NULL);
2928 bus->f1regdata += 2;
2929 if (hi == 0 && lo == 0)
2930 break;
2931 }
2932 return ret;
2933 }
2934
2935 bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
2936
2937 return ret;
2938 }
2939
2940 int
2941 brcmf_sdbrcm_bus_txctl(struct brcmf_bus *bus, unsigned char *msg, uint msglen)
2942 {
2943 u8 *frame;
2944 u16 len;
2945 u32 swheader;
2946 uint retries = 0;
2947 u8 doff = 0;
2948 int ret = -1;
2949
2950 brcmf_dbg(TRACE, "Enter\n");
2951
2952 /* Back the pointer to make a room for bus header */
2953 frame = msg - SDPCM_HDRLEN;
2954 len = (msglen += SDPCM_HDRLEN);
2955
2956 /* Add alignment padding (optional for ctl frames) */
2957 doff = ((unsigned long)frame % BRCMF_SDALIGN);
2958 if (doff) {
2959 frame -= doff;
2960 len += doff;
2961 msglen += doff;
2962 memset(frame, 0, doff + SDPCM_HDRLEN);
2963 }
2964 /* precondition: doff < BRCMF_SDALIGN */
2965 doff += SDPCM_HDRLEN;
2966
2967 /* Round send length to next SDIO block */
2968 if (bus->roundup && bus->blocksize && (len > bus->blocksize)) {
2969 u16 pad = bus->blocksize - (len % bus->blocksize);
2970 if ((pad <= bus->roundup) && (pad < bus->blocksize))
2971 len += pad;
2972 } else if (len % BRCMF_SDALIGN) {
2973 len += BRCMF_SDALIGN - (len % BRCMF_SDALIGN);
2974 }
2975
2976 /* Satisfy length-alignment requirements */
2977 if (len & (ALIGNMENT - 1))
2978 len = roundup(len, ALIGNMENT);
2979
2980 /* precondition: IS_ALIGNED((unsigned long)frame, 2) */
2981
2982 /* Need to lock here to protect txseq and SDIO tx calls */
2983 down(&bus->sdsem);
2984
2985 bus_wake(bus);
2986
2987 /* Make sure backplane clock is on */
2988 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
2989
2990 /* Hardware tag: 2 byte len followed by 2 byte ~len check (all LE) */
2991 *(__le16 *) frame = cpu_to_le16((u16) msglen);
2992 *(((__le16 *) frame) + 1) = cpu_to_le16(~msglen);
2993
2994 /* Software tag: channel, sequence number, data offset */
2995 swheader =
2996 ((SDPCM_CONTROL_CHANNEL << SDPCM_CHANNEL_SHIFT) &
2997 SDPCM_CHANNEL_MASK)
2998 | bus->tx_seq | ((doff << SDPCM_DOFFSET_SHIFT) &
2999 SDPCM_DOFFSET_MASK);
3000 put_unaligned_le32(swheader, frame + SDPCM_FRAMETAG_LEN);
3001 put_unaligned_le32(0, frame + SDPCM_FRAMETAG_LEN + sizeof(swheader));
3002
3003 if (!data_ok(bus)) {
3004 brcmf_dbg(INFO, "No bus credit bus->tx_max %d, bus->tx_seq %d\n",
3005 bus->tx_max, bus->tx_seq);
3006 bus->ctrl_frame_stat = true;
3007 /* Send from dpc */
3008 bus->ctrl_frame_buf = frame;
3009 bus->ctrl_frame_len = len;
3010
3011 brcmf_sdbrcm_wait_for_event(bus, &bus->ctrl_frame_stat);
3012
3013 if (bus->ctrl_frame_stat == false) {
3014 brcmf_dbg(INFO, "ctrl_frame_stat == false\n");
3015 ret = 0;
3016 } else {
3017 brcmf_dbg(INFO, "ctrl_frame_stat == true\n");
3018 ret = -1;
3019 }
3020 }
3021
3022 if (ret == -1) {
3023 #ifdef BCMDBG
3024 if (BRCMF_BYTES_ON() && BRCMF_CTL_ON()) {
3025 printk(KERN_DEBUG "Tx Frame:\n");
3026 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
3027 frame, len);
3028 } else if (BRCMF_HDRS_ON()) {
3029 printk(KERN_DEBUG "TxHdr:\n");
3030 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
3031 frame, min_t(u16, len, 16));
3032 }
3033 #endif
3034
3035 do {
3036 ret = brcmf_tx_frame(bus, frame, len);
3037 } while (ret < 0 && retries++ < TXRETRIES);
3038 }
3039
3040 if ((bus->idletime == BRCMF_IDLE_IMMEDIATE) && !bus->dpc_sched) {
3041 bus->activity = false;
3042 brcmf_sdbrcm_clkctl(bus, CLK_NONE, true);
3043 }
3044
3045 up(&bus->sdsem);
3046
3047 if (ret)
3048 bus->drvr->tx_ctlerrs++;
3049 else
3050 bus->drvr->tx_ctlpkts++;
3051
3052 return ret ? -EIO : 0;
3053 }
3054
3055 int
3056 brcmf_sdbrcm_bus_rxctl(struct brcmf_bus *bus, unsigned char *msg, uint msglen)
3057 {
3058 int timeleft;
3059 uint rxlen = 0;
3060 bool pending;
3061
3062 brcmf_dbg(TRACE, "Enter\n");
3063
3064 /* Wait until control frame is available */
3065 timeleft = brcmf_sdbrcm_dcmd_resp_wait(bus, &bus->rxlen, &pending);
3066
3067 down(&bus->sdsem);
3068 rxlen = bus->rxlen;
3069 memcpy(msg, bus->rxctl, min(msglen, rxlen));
3070 bus->rxlen = 0;
3071 up(&bus->sdsem);
3072
3073 if (rxlen) {
3074 brcmf_dbg(CTL, "resumed on rxctl frame, got %d expected %d\n",
3075 rxlen, msglen);
3076 } else if (timeleft == 0) {
3077 brcmf_dbg(ERROR, "resumed on timeout\n");
3078 } else if (pending == true) {
3079 brcmf_dbg(CTL, "cancelled\n");
3080 return -ERESTARTSYS;
3081 } else {
3082 brcmf_dbg(CTL, "resumed for unknown reason?\n");
3083 }
3084
3085 if (rxlen)
3086 bus->drvr->rx_ctlpkts++;
3087 else
3088 bus->drvr->rx_ctlerrs++;
3089
3090 return rxlen ? (int)rxlen : -ETIMEDOUT;
3091 }
3092
3093 static int brcmf_sdbrcm_downloadvars(struct brcmf_bus *bus, void *arg, int len)
3094 {
3095 int bcmerror = 0;
3096
3097 brcmf_dbg(TRACE, "Enter\n");
3098
3099 /* Basic sanity checks */
3100 if (bus->drvr->up) {
3101 bcmerror = -EISCONN;
3102 goto err;
3103 }
3104 if (!len) {
3105 bcmerror = -EOVERFLOW;
3106 goto err;
3107 }
3108
3109 /* Free the old ones and replace with passed variables */
3110 kfree(bus->vars);
3111
3112 bus->vars = kmalloc(len, GFP_ATOMIC);
3113 bus->varsz = bus->vars ? len : 0;
3114 if (bus->vars == NULL) {
3115 bcmerror = -ENOMEM;
3116 goto err;
3117 }
3118
3119 /* Copy the passed variables, which should include the
3120 terminating double-null */
3121 memcpy(bus->vars, arg, bus->varsz);
3122 err:
3123 return bcmerror;
3124 }
3125
3126 static int brcmf_sdbrcm_write_vars(struct brcmf_bus *bus)
3127 {
3128 int bcmerror = 0;
3129 u32 varsize;
3130 u32 varaddr;
3131 u8 *vbuffer;
3132 u32 varsizew;
3133 __le32 varsizew_le;
3134 #ifdef BCMDBG
3135 char *nvram_ularray;
3136 #endif /* BCMDBG */
3137
3138 /* Even if there are no vars are to be written, we still
3139 need to set the ramsize. */
3140 varsize = bus->varsz ? roundup(bus->varsz, 4) : 0;
3141 varaddr = (bus->ramsize - 4) - varsize;
3142
3143 if (bus->vars) {
3144 vbuffer = kzalloc(varsize, GFP_ATOMIC);
3145 if (!vbuffer)
3146 return -ENOMEM;
3147
3148 memcpy(vbuffer, bus->vars, bus->varsz);
3149
3150 /* Write the vars list */
3151 bcmerror =
3152 brcmf_sdbrcm_membytes(bus, true, varaddr, vbuffer, varsize);
3153 #ifdef BCMDBG
3154 /* Verify NVRAM bytes */
3155 brcmf_dbg(INFO, "Compare NVRAM dl & ul; varsize=%d\n", varsize);
3156 nvram_ularray = kmalloc(varsize, GFP_ATOMIC);
3157 if (!nvram_ularray)
3158 return -ENOMEM;
3159
3160 /* Upload image to verify downloaded contents. */
3161 memset(nvram_ularray, 0xaa, varsize);
3162
3163 /* Read the vars list to temp buffer for comparison */
3164 bcmerror =
3165 brcmf_sdbrcm_membytes(bus, false, varaddr, nvram_ularray,
3166 varsize);
3167 if (bcmerror) {
3168 brcmf_dbg(ERROR, "error %d on reading %d nvram bytes at 0x%08x\n",
3169 bcmerror, varsize, varaddr);
3170 }
3171 /* Compare the org NVRAM with the one read from RAM */
3172 if (memcmp(vbuffer, nvram_ularray, varsize))
3173 brcmf_dbg(ERROR, "Downloaded NVRAM image is corrupted\n");
3174 else
3175 brcmf_dbg(ERROR, "Download/Upload/Compare of NVRAM ok\n");
3176
3177 kfree(nvram_ularray);
3178 #endif /* BCMDBG */
3179
3180 kfree(vbuffer);
3181 }
3182
3183 /* adjust to the user specified RAM */
3184 brcmf_dbg(INFO, "Physical memory size: %d\n", bus->ramsize);
3185 brcmf_dbg(INFO, "Vars are at %d, orig varsize is %d\n",
3186 varaddr, varsize);
3187 varsize = ((bus->ramsize - 4) - varaddr);
3188
3189 /*
3190 * Determine the length token:
3191 * Varsize, converted to words, in lower 16-bits, checksum
3192 * in upper 16-bits.
3193 */
3194 if (bcmerror) {
3195 varsizew = 0;
3196 varsizew_le = cpu_to_le32(0);
3197 } else {
3198 varsizew = varsize / 4;
3199 varsizew = (~varsizew << 16) | (varsizew & 0x0000FFFF);
3200 varsizew_le = cpu_to_le32(varsizew);
3201 }
3202
3203 brcmf_dbg(INFO, "New varsize is %d, length token=0x%08x\n",
3204 varsize, varsizew);
3205
3206 /* Write the length token to the last word */
3207 bcmerror = brcmf_sdbrcm_membytes(bus, true, (bus->ramsize - 4),
3208 (u8 *)&varsizew_le, 4);
3209
3210 return bcmerror;
3211 }
3212
3213 static void
3214 brcmf_sdbrcm_chip_disablecore(struct brcmf_sdio_dev *sdiodev, u32 corebase)
3215 {
3216 u32 regdata;
3217
3218 regdata = brcmf_sdcard_reg_read(sdiodev,
3219 CORE_SB(corebase, sbtmstatelow), 4);
3220 if (regdata & SBTML_RESET)
3221 return;
3222
3223 regdata = brcmf_sdcard_reg_read(sdiodev,
3224 CORE_SB(corebase, sbtmstatelow), 4);
3225 if ((regdata & (SICF_CLOCK_EN << SBTML_SICF_SHIFT)) != 0) {
3226 /*
3227 * set target reject and spin until busy is clear
3228 * (preserve core-specific bits)
3229 */
3230 regdata = brcmf_sdcard_reg_read(sdiodev,
3231 CORE_SB(corebase, sbtmstatelow), 4);
3232 brcmf_sdcard_reg_write(sdiodev, CORE_SB(corebase, sbtmstatelow),
3233 4, regdata | SBTML_REJ);
3234
3235 regdata = brcmf_sdcard_reg_read(sdiodev,
3236 CORE_SB(corebase, sbtmstatelow), 4);
3237 udelay(1);
3238 SPINWAIT((brcmf_sdcard_reg_read(sdiodev,
3239 CORE_SB(corebase, sbtmstatehigh), 4) &
3240 SBTMH_BUSY), 100000);
3241
3242 regdata = brcmf_sdcard_reg_read(sdiodev,
3243 CORE_SB(corebase, sbtmstatehigh), 4);
3244 if (regdata & SBTMH_BUSY)
3245 brcmf_dbg(ERROR, "ARM core still busy\n");
3246
3247 regdata = brcmf_sdcard_reg_read(sdiodev,
3248 CORE_SB(corebase, sbidlow), 4);
3249 if (regdata & SBIDL_INIT) {
3250 regdata = brcmf_sdcard_reg_read(sdiodev,
3251 CORE_SB(corebase, sbimstate), 4) |
3252 SBIM_RJ;
3253 brcmf_sdcard_reg_write(sdiodev,
3254 CORE_SB(corebase, sbimstate), 4,
3255 regdata);
3256 regdata = brcmf_sdcard_reg_read(sdiodev,
3257 CORE_SB(corebase, sbimstate), 4);
3258 udelay(1);
3259 SPINWAIT((brcmf_sdcard_reg_read(sdiodev,
3260 CORE_SB(corebase, sbimstate), 4) &
3261 SBIM_BY), 100000);
3262 }
3263
3264 /* set reset and reject while enabling the clocks */
3265 brcmf_sdcard_reg_write(sdiodev,
3266 CORE_SB(corebase, sbtmstatelow), 4,
3267 (((SICF_FGC | SICF_CLOCK_EN) << SBTML_SICF_SHIFT) |
3268 SBTML_REJ | SBTML_RESET));
3269 regdata = brcmf_sdcard_reg_read(sdiodev,
3270 CORE_SB(corebase, sbtmstatelow), 4);
3271 udelay(10);
3272
3273 /* clear the initiator reject bit */
3274 regdata = brcmf_sdcard_reg_read(sdiodev,
3275 CORE_SB(corebase, sbidlow), 4);
3276 if (regdata & SBIDL_INIT) {
3277 regdata = brcmf_sdcard_reg_read(sdiodev,
3278 CORE_SB(corebase, sbimstate), 4) &
3279 ~SBIM_RJ;
3280 brcmf_sdcard_reg_write(sdiodev,
3281 CORE_SB(corebase, sbimstate), 4,
3282 regdata);
3283 }
3284 }
3285
3286 /* leave reset and reject asserted */
3287 brcmf_sdcard_reg_write(sdiodev, CORE_SB(corebase, sbtmstatelow), 4,
3288 (SBTML_REJ | SBTML_RESET));
3289 udelay(1);
3290 }
3291
3292 static void
3293 brcmf_sdbrcm_chip_resetcore(struct brcmf_sdio_dev *sdiodev, u32 corebase)
3294 {
3295 u32 regdata;
3296
3297 /*
3298 * Must do the disable sequence first to work for
3299 * arbitrary current core state.
3300 */
3301 brcmf_sdbrcm_chip_disablecore(sdiodev, corebase);
3302
3303 /*
3304 * Now do the initialization sequence.
3305 * set reset while enabling the clock and
3306 * forcing them on throughout the core
3307 */
3308 brcmf_sdcard_reg_write(sdiodev, CORE_SB(corebase, sbtmstatelow), 4,
3309 ((SICF_FGC | SICF_CLOCK_EN) << SBTML_SICF_SHIFT) |
3310 SBTML_RESET);
3311 udelay(1);
3312
3313 regdata = brcmf_sdcard_reg_read(sdiodev,
3314 CORE_SB(corebase, sbtmstatehigh), 4);
3315 if (regdata & SBTMH_SERR)
3316 brcmf_sdcard_reg_write(sdiodev,
3317 CORE_SB(corebase, sbtmstatehigh), 4, 0);
3318
3319 regdata = brcmf_sdcard_reg_read(sdiodev,
3320 CORE_SB(corebase, sbimstate), 4);
3321 if (regdata & (SBIM_IBE | SBIM_TO))
3322 brcmf_sdcard_reg_write(sdiodev, CORE_SB(corebase, sbimstate), 4,
3323 regdata & ~(SBIM_IBE | SBIM_TO));
3324
3325 /* clear reset and allow it to propagate throughout the core */
3326 brcmf_sdcard_reg_write(sdiodev, CORE_SB(corebase, sbtmstatelow), 4,
3327 (SICF_FGC << SBTML_SICF_SHIFT) |
3328 (SICF_CLOCK_EN << SBTML_SICF_SHIFT));
3329 udelay(1);
3330
3331 /* leave clock enabled */
3332 brcmf_sdcard_reg_write(sdiodev, CORE_SB(corebase, sbtmstatelow), 4,
3333 (SICF_CLOCK_EN << SBTML_SICF_SHIFT));
3334 udelay(1);
3335 }
3336
3337 static int brcmf_sdbrcm_download_state(struct brcmf_bus *bus, bool enter)
3338 {
3339 uint retries;
3340 u32 regdata;
3341 int bcmerror = 0;
3342
3343 /* To enter download state, disable ARM and reset SOCRAM.
3344 * To exit download state, simply reset ARM (default is RAM boot).
3345 */
3346 if (enter) {
3347 bus->alp_only = true;
3348
3349 brcmf_sdbrcm_chip_disablecore(bus->sdiodev,
3350 bus->ci->armcorebase);
3351
3352 brcmf_sdbrcm_chip_resetcore(bus->sdiodev, bus->ci->ramcorebase);
3353
3354 /* Clear the top bit of memory */
3355 if (bus->ramsize) {
3356 u32 zeros = 0;
3357 brcmf_sdbrcm_membytes(bus, true, bus->ramsize - 4,
3358 (u8 *)&zeros, 4);
3359 }
3360 } else {
3361 regdata = brcmf_sdcard_reg_read(bus->sdiodev,
3362 CORE_SB(bus->ci->ramcorebase, sbtmstatelow), 4);
3363 regdata &= (SBTML_RESET | SBTML_REJ_MASK |
3364 (SICF_CLOCK_EN << SBTML_SICF_SHIFT));
3365 if ((SICF_CLOCK_EN << SBTML_SICF_SHIFT) != regdata) {
3366 brcmf_dbg(ERROR, "SOCRAM core is down after reset?\n");
3367 bcmerror = -EBADE;
3368 goto fail;
3369 }
3370
3371 bcmerror = brcmf_sdbrcm_write_vars(bus);
3372 if (bcmerror) {
3373 brcmf_dbg(ERROR, "no vars written to RAM\n");
3374 bcmerror = 0;
3375 }
3376
3377 w_sdreg32(bus, 0xFFFFFFFF,
3378 offsetof(struct sdpcmd_regs, intstatus), &retries);
3379
3380 brcmf_sdbrcm_chip_resetcore(bus->sdiodev, bus->ci->armcorebase);
3381
3382 /* Allow HT Clock now that the ARM is running. */
3383 bus->alp_only = false;
3384
3385 bus->drvr->busstate = BRCMF_BUS_LOAD;
3386 }
3387 fail:
3388 return bcmerror;
3389 }
3390
3391 static int brcmf_sdbrcm_get_image(char *buf, int len, struct brcmf_bus *bus)
3392 {
3393 if (bus->firmware->size < bus->fw_ptr + len)
3394 len = bus->firmware->size - bus->fw_ptr;
3395
3396 memcpy(buf, &bus->firmware->data[bus->fw_ptr], len);
3397 bus->fw_ptr += len;
3398 return len;
3399 }
3400
3401 MODULE_FIRMWARE(BCM4329_FW_NAME);
3402 MODULE_FIRMWARE(BCM4329_NV_NAME);
3403
3404 static int brcmf_sdbrcm_download_code_file(struct brcmf_bus *bus)
3405 {
3406 int offset = 0;
3407 uint len;
3408 u8 *memblock = NULL, *memptr;
3409 int ret;
3410
3411 brcmf_dbg(INFO, "Enter\n");
3412
3413 bus->fw_name = BCM4329_FW_NAME;
3414 ret = request_firmware(&bus->firmware, bus->fw_name,
3415 &bus->sdiodev->func[2]->dev);
3416 if (ret) {
3417 brcmf_dbg(ERROR, "Fail to request firmware %d\n", ret);
3418 return ret;
3419 }
3420 bus->fw_ptr = 0;
3421
3422 memptr = memblock = kmalloc(MEMBLOCK + BRCMF_SDALIGN, GFP_ATOMIC);
3423 if (memblock == NULL) {
3424 ret = -ENOMEM;
3425 goto err;
3426 }
3427 if ((u32)(unsigned long)memblock % BRCMF_SDALIGN)
3428 memptr += (BRCMF_SDALIGN -
3429 ((u32)(unsigned long)memblock % BRCMF_SDALIGN));
3430
3431 /* Download image */
3432 while ((len =
3433 brcmf_sdbrcm_get_image((char *)memptr, MEMBLOCK, bus))) {
3434 ret = brcmf_sdbrcm_membytes(bus, true, offset, memptr, len);
3435 if (ret) {
3436 brcmf_dbg(ERROR, "error %d on writing %d membytes at 0x%08x\n",
3437 ret, MEMBLOCK, offset);
3438 goto err;
3439 }
3440
3441 offset += MEMBLOCK;
3442 }
3443
3444 err:
3445 kfree(memblock);
3446
3447 release_firmware(bus->firmware);
3448 bus->fw_ptr = 0;
3449
3450 return ret;
3451 }
3452
3453 /*
3454 * ProcessVars:Takes a buffer of "<var>=<value>\n" lines read from a file
3455 * and ending in a NUL.
3456 * Removes carriage returns, empty lines, comment lines, and converts
3457 * newlines to NULs.
3458 * Shortens buffer as needed and pads with NULs. End of buffer is marked
3459 * by two NULs.
3460 */
3461
3462 static uint brcmf_process_nvram_vars(char *varbuf, uint len)
3463 {
3464 char *dp;
3465 bool findNewline;
3466 int column;
3467 uint buf_len, n;
3468
3469 dp = varbuf;
3470
3471 findNewline = false;
3472 column = 0;
3473
3474 for (n = 0; n < len; n++) {
3475 if (varbuf[n] == 0)
3476 break;
3477 if (varbuf[n] == '\r')
3478 continue;
3479 if (findNewline && varbuf[n] != '\n')
3480 continue;
3481 findNewline = false;
3482 if (varbuf[n] == '#') {
3483 findNewline = true;
3484 continue;
3485 }
3486 if (varbuf[n] == '\n') {
3487 if (column == 0)
3488 continue;
3489 *dp++ = 0;
3490 column = 0;
3491 continue;
3492 }
3493 *dp++ = varbuf[n];
3494 column++;
3495 }
3496 buf_len = dp - varbuf;
3497
3498 while (dp < varbuf + n)
3499 *dp++ = 0;
3500
3501 return buf_len;
3502 }
3503
3504 static int brcmf_sdbrcm_download_nvram(struct brcmf_bus *bus)
3505 {
3506 uint len;
3507 char *memblock = NULL;
3508 char *bufp;
3509 int ret;
3510
3511 bus->nv_name = BCM4329_NV_NAME;
3512 ret = request_firmware(&bus->firmware, bus->nv_name,
3513 &bus->sdiodev->func[2]->dev);
3514 if (ret) {
3515 brcmf_dbg(ERROR, "Fail to request nvram %d\n", ret);
3516 return ret;
3517 }
3518 bus->fw_ptr = 0;
3519
3520 memblock = kmalloc(MEMBLOCK, GFP_ATOMIC);
3521 if (memblock == NULL) {
3522 ret = -ENOMEM;
3523 goto err;
3524 }
3525
3526 len = brcmf_sdbrcm_get_image(memblock, MEMBLOCK, bus);
3527
3528 if (len > 0 && len < MEMBLOCK) {
3529 bufp = (char *)memblock;
3530 bufp[len] = 0;
3531 len = brcmf_process_nvram_vars(bufp, len);
3532 bufp += len;
3533 *bufp++ = 0;
3534 if (len)
3535 ret = brcmf_sdbrcm_downloadvars(bus, memblock, len + 1);
3536 if (ret)
3537 brcmf_dbg(ERROR, "error downloading vars: %d\n", ret);
3538 } else {
3539 brcmf_dbg(ERROR, "error reading nvram file: %d\n", len);
3540 ret = -EIO;
3541 }
3542
3543 err:
3544 kfree(memblock);
3545
3546 release_firmware(bus->firmware);
3547 bus->fw_ptr = 0;
3548
3549 return ret;
3550 }
3551
3552 static int _brcmf_sdbrcm_download_firmware(struct brcmf_bus *bus)
3553 {
3554 int bcmerror = -1;
3555
3556 /* Keep arm in reset */
3557 if (brcmf_sdbrcm_download_state(bus, true)) {
3558 brcmf_dbg(ERROR, "error placing ARM core in reset\n");
3559 goto err;
3560 }
3561
3562 /* External image takes precedence if specified */
3563 if (brcmf_sdbrcm_download_code_file(bus)) {
3564 brcmf_dbg(ERROR, "dongle image file download failed\n");
3565 goto err;
3566 }
3567
3568 /* External nvram takes precedence if specified */
3569 if (brcmf_sdbrcm_download_nvram(bus))
3570 brcmf_dbg(ERROR, "dongle nvram file download failed\n");
3571
3572 /* Take arm out of reset */
3573 if (brcmf_sdbrcm_download_state(bus, false)) {
3574 brcmf_dbg(ERROR, "error getting out of ARM core reset\n");
3575 goto err;
3576 }
3577
3578 bcmerror = 0;
3579
3580 err:
3581 return bcmerror;
3582 }
3583
3584 static bool
3585 brcmf_sdbrcm_download_firmware(struct brcmf_bus *bus)
3586 {
3587 bool ret;
3588
3589 /* Download the firmware */
3590 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
3591
3592 ret = _brcmf_sdbrcm_download_firmware(bus) == 0;
3593
3594 brcmf_sdbrcm_clkctl(bus, CLK_SDONLY, false);
3595
3596 return ret;
3597 }
3598
3599 void brcmf_sdbrcm_bus_stop(struct brcmf_bus *bus)
3600 {
3601 u32 local_hostintmask;
3602 u8 saveclk;
3603 uint retries;
3604 int err;
3605
3606 brcmf_dbg(TRACE, "Enter\n");
3607
3608 if (bus->watchdog_tsk) {
3609 send_sig(SIGTERM, bus->watchdog_tsk, 1);
3610 kthread_stop(bus->watchdog_tsk);
3611 bus->watchdog_tsk = NULL;
3612 }
3613
3614 if (bus->dpc_tsk && bus->dpc_tsk != current) {
3615 send_sig(SIGTERM, bus->dpc_tsk, 1);
3616 kthread_stop(bus->dpc_tsk);
3617 bus->dpc_tsk = NULL;
3618 }
3619
3620 down(&bus->sdsem);
3621
3622 bus_wake(bus);
3623
3624 /* Enable clock for device interrupts */
3625 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
3626
3627 /* Disable and clear interrupts at the chip level also */
3628 w_sdreg32(bus, 0, offsetof(struct sdpcmd_regs, hostintmask), &retries);
3629 local_hostintmask = bus->hostintmask;
3630 bus->hostintmask = 0;
3631
3632 /* Change our idea of bus state */
3633 bus->drvr->busstate = BRCMF_BUS_DOWN;
3634
3635 /* Force clocks on backplane to be sure F2 interrupt propagates */
3636 saveclk = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
3637 SBSDIO_FUNC1_CHIPCLKCSR, &err);
3638 if (!err) {
3639 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
3640 SBSDIO_FUNC1_CHIPCLKCSR,
3641 (saveclk | SBSDIO_FORCE_HT), &err);
3642 }
3643 if (err)
3644 brcmf_dbg(ERROR, "Failed to force clock for F2: err %d\n", err);
3645
3646 /* Turn off the bus (F2), free any pending packets */
3647 brcmf_dbg(INTR, "disable SDIO interrupts\n");
3648 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_0, SDIO_CCCR_IOEx,
3649 SDIO_FUNC_ENABLE_1, NULL);
3650
3651 /* Clear any pending interrupts now that F2 is disabled */
3652 w_sdreg32(bus, local_hostintmask,
3653 offsetof(struct sdpcmd_regs, intstatus), &retries);
3654
3655 /* Turn off the backplane clock (only) */
3656 brcmf_sdbrcm_clkctl(bus, CLK_SDONLY, false);
3657
3658 /* Clear the data packet queues */
3659 brcmu_pktq_flush(&bus->txq, true, NULL, NULL);
3660
3661 /* Clear any held glomming stuff */
3662 if (bus->glomd)
3663 brcmu_pkt_buf_free_skb(bus->glomd);
3664
3665 if (bus->glom)
3666 brcmu_pkt_buf_free_skb(bus->glom);
3667
3668 bus->glom = bus->glomd = NULL;
3669
3670 /* Clear rx control and wake any waiters */
3671 bus->rxlen = 0;
3672 brcmf_sdbrcm_dcmd_resp_wake(bus);
3673
3674 /* Reset some F2 state stuff */
3675 bus->rxskip = false;
3676 bus->tx_seq = bus->rx_seq = 0;
3677
3678 up(&bus->sdsem);
3679 }
3680
3681 int brcmf_sdbrcm_bus_init(struct brcmf_pub *drvr)
3682 {
3683 struct brcmf_bus *bus = drvr->bus;
3684 unsigned long timeout;
3685 uint retries = 0;
3686 u8 ready, enable;
3687 int err, ret = 0;
3688 u8 saveclk;
3689
3690 brcmf_dbg(TRACE, "Enter\n");
3691
3692 /* try to download image and nvram to the dongle */
3693 if (drvr->busstate == BRCMF_BUS_DOWN) {
3694 if (!(brcmf_sdbrcm_download_firmware(bus)))
3695 return -1;
3696 }
3697
3698 if (!bus->drvr)
3699 return 0;
3700
3701 /* Start the watchdog timer */
3702 bus->drvr->tickcnt = 0;
3703 brcmf_sdbrcm_wd_timer(bus, BRCMF_WD_POLL_MS);
3704
3705 down(&bus->sdsem);
3706
3707 /* Make sure backplane clock is on, needed to generate F2 interrupt */
3708 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
3709 if (bus->clkstate != CLK_AVAIL)
3710 goto exit;
3711
3712 /* Force clocks on backplane to be sure F2 interrupt propagates */
3713 saveclk =
3714 brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
3715 SBSDIO_FUNC1_CHIPCLKCSR, &err);
3716 if (!err) {
3717 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
3718 SBSDIO_FUNC1_CHIPCLKCSR,
3719 (saveclk | SBSDIO_FORCE_HT), &err);
3720 }
3721 if (err) {
3722 brcmf_dbg(ERROR, "Failed to force clock for F2: err %d\n", err);
3723 goto exit;
3724 }
3725
3726 /* Enable function 2 (frame transfers) */
3727 w_sdreg32(bus, SDPCM_PROT_VERSION << SMB_DATA_VERSION_SHIFT,
3728 offsetof(struct sdpcmd_regs, tosbmailboxdata), &retries);
3729 enable = (SDIO_FUNC_ENABLE_1 | SDIO_FUNC_ENABLE_2);
3730
3731 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_0, SDIO_CCCR_IOEx,
3732 enable, NULL);
3733
3734 timeout = jiffies + msecs_to_jiffies(BRCMF_WAIT_F2RDY);
3735 ready = 0;
3736 while (enable != ready) {
3737 ready = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_0,
3738 SDIO_CCCR_IORx, NULL);
3739 if (time_after(jiffies, timeout))
3740 break;
3741 else if (time_after(jiffies, timeout - BRCMF_WAIT_F2RDY + 50))
3742 /* prevent busy waiting if it takes too long */
3743 msleep_interruptible(20);
3744 }
3745
3746 brcmf_dbg(INFO, "enable 0x%02x, ready 0x%02x\n", enable, ready);
3747
3748 /* If F2 successfully enabled, set core and enable interrupts */
3749 if (ready == enable) {
3750 /* Set up the interrupt mask and enable interrupts */
3751 bus->hostintmask = HOSTINTMASK;
3752 w_sdreg32(bus, bus->hostintmask,
3753 offsetof(struct sdpcmd_regs, hostintmask), &retries);
3754
3755 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
3756 SBSDIO_WATERMARK, 8, &err);
3757
3758 /* Set bus state according to enable result */
3759 drvr->busstate = BRCMF_BUS_DATA;
3760 }
3761
3762 else {
3763 /* Disable F2 again */
3764 enable = SDIO_FUNC_ENABLE_1;
3765 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_0,
3766 SDIO_CCCR_IOEx, enable, NULL);
3767 }
3768
3769 /* Restore previous clock setting */
3770 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
3771 SBSDIO_FUNC1_CHIPCLKCSR, saveclk, &err);
3772
3773 /* If we didn't come up, turn off backplane clock */
3774 if (drvr->busstate != BRCMF_BUS_DATA)
3775 brcmf_sdbrcm_clkctl(bus, CLK_NONE, false);
3776
3777 exit:
3778 up(&bus->sdsem);
3779
3780 return ret;
3781 }
3782
3783 void brcmf_sdbrcm_isr(void *arg)
3784 {
3785 struct brcmf_bus *bus = (struct brcmf_bus *) arg;
3786
3787 brcmf_dbg(TRACE, "Enter\n");
3788
3789 if (!bus) {
3790 brcmf_dbg(ERROR, "bus is null pointer, exiting\n");
3791 return;
3792 }
3793
3794 if (bus->drvr->busstate == BRCMF_BUS_DOWN) {
3795 brcmf_dbg(ERROR, "bus is down. we have nothing to do\n");
3796 return;
3797 }
3798 /* Count the interrupt call */
3799 bus->intrcount++;
3800 bus->ipend = true;
3801
3802 /* Shouldn't get this interrupt if we're sleeping? */
3803 if (bus->sleeping) {
3804 brcmf_dbg(ERROR, "INTERRUPT WHILE SLEEPING??\n");
3805 return;
3806 }
3807
3808 /* Disable additional interrupts (is this needed now)? */
3809 if (!bus->intr)
3810 brcmf_dbg(ERROR, "isr w/o interrupt configured!\n");
3811
3812 bus->dpc_sched = true;
3813 if (bus->dpc_tsk)
3814 complete(&bus->dpc_wait);
3815 }
3816
3817 static bool brcmf_sdbrcm_bus_watchdog(struct brcmf_pub *drvr)
3818 {
3819 struct brcmf_bus *bus;
3820
3821 brcmf_dbg(TIMER, "Enter\n");
3822
3823 bus = drvr->bus;
3824
3825 /* Ignore the timer if simulating bus down */
3826 if (bus->sleeping)
3827 return false;
3828
3829 down(&bus->sdsem);
3830
3831 /* Poll period: check device if appropriate. */
3832 if (bus->poll && (++bus->polltick >= bus->pollrate)) {
3833 u32 intstatus = 0;
3834
3835 /* Reset poll tick */
3836 bus->polltick = 0;
3837
3838 /* Check device if no interrupts */
3839 if (!bus->intr || (bus->intrcount == bus->lastintrs)) {
3840
3841 if (!bus->dpc_sched) {
3842 u8 devpend;
3843 devpend = brcmf_sdcard_cfg_read(bus->sdiodev,
3844 SDIO_FUNC_0, SDIO_CCCR_INTx,
3845 NULL);
3846 intstatus =
3847 devpend & (INTR_STATUS_FUNC1 |
3848 INTR_STATUS_FUNC2);
3849 }
3850
3851 /* If there is something, make like the ISR and
3852 schedule the DPC */
3853 if (intstatus) {
3854 bus->pollcnt++;
3855 bus->ipend = true;
3856
3857 bus->dpc_sched = true;
3858 if (bus->dpc_tsk)
3859 complete(&bus->dpc_wait);
3860 }
3861 }
3862
3863 /* Update interrupt tracking */
3864 bus->lastintrs = bus->intrcount;
3865 }
3866 #ifdef BCMDBG
3867 /* Poll for console output periodically */
3868 if (drvr->busstate == BRCMF_BUS_DATA && bus->console_interval != 0) {
3869 bus->console.count += BRCMF_WD_POLL_MS;
3870 if (bus->console.count >= bus->console_interval) {
3871 bus->console.count -= bus->console_interval;
3872 /* Make sure backplane clock is on */
3873 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
3874 if (brcmf_sdbrcm_readconsole(bus) < 0)
3875 /* stop on error */
3876 bus->console_interval = 0;
3877 }
3878 }
3879 #endif /* BCMDBG */
3880
3881 /* On idle timeout clear activity flag and/or turn off clock */
3882 if ((bus->idletime > 0) && (bus->clkstate == CLK_AVAIL)) {
3883 if (++bus->idlecount >= bus->idletime) {
3884 bus->idlecount = 0;
3885 if (bus->activity) {
3886 bus->activity = false;
3887 brcmf_sdbrcm_wd_timer(bus, BRCMF_WD_POLL_MS);
3888 } else {
3889 brcmf_sdbrcm_clkctl(bus, CLK_NONE, false);
3890 }
3891 }
3892 }
3893
3894 up(&bus->sdsem);
3895
3896 return bus->ipend;
3897 }
3898
3899 static bool brcmf_sdbrcm_chipmatch(u16 chipid)
3900 {
3901 if (chipid == BCM4329_CHIP_ID)
3902 return true;
3903 return false;
3904 }
3905
3906 static void brcmf_sdbrcm_release_malloc(struct brcmf_bus *bus)
3907 {
3908 brcmf_dbg(TRACE, "Enter\n");
3909
3910 kfree(bus->rxbuf);
3911 bus->rxctl = bus->rxbuf = NULL;
3912 bus->rxlen = 0;
3913
3914 kfree(bus->databuf);
3915 bus->databuf = NULL;
3916 }
3917
3918 static bool brcmf_sdbrcm_probe_malloc(struct brcmf_bus *bus)
3919 {
3920 brcmf_dbg(TRACE, "Enter\n");
3921
3922 if (bus->drvr->maxctl) {
3923 bus->rxblen =
3924 roundup((bus->drvr->maxctl + SDPCM_HDRLEN),
3925 ALIGNMENT) + BRCMF_SDALIGN;
3926 bus->rxbuf = kmalloc(bus->rxblen, GFP_ATOMIC);
3927 if (!(bus->rxbuf))
3928 goto fail;
3929 }
3930
3931 /* Allocate buffer to receive glomed packet */
3932 bus->databuf = kmalloc(MAX_DATA_BUF, GFP_ATOMIC);
3933 if (!(bus->databuf)) {
3934 /* release rxbuf which was already located as above */
3935 if (!bus->rxblen)
3936 kfree(bus->rxbuf);
3937 goto fail;
3938 }
3939
3940 /* Align the buffer */
3941 if ((unsigned long)bus->databuf % BRCMF_SDALIGN)
3942 bus->dataptr = bus->databuf + (BRCMF_SDALIGN -
3943 ((unsigned long)bus->databuf % BRCMF_SDALIGN));
3944 else
3945 bus->dataptr = bus->databuf;
3946
3947 return true;
3948
3949 fail:
3950 return false;
3951 }
3952
3953 /* SDIO Pad drive strength to select value mappings */
3954 struct sdiod_drive_str {
3955 u8 strength; /* Pad Drive Strength in mA */
3956 u8 sel; /* Chip-specific select value */
3957 };
3958
3959 /* SDIO Drive Strength to sel value table for PMU Rev 1 */
3960 static const struct sdiod_drive_str sdiod_drive_strength_tab1[] = {
3961 {
3962 4, 0x2}, {
3963 2, 0x3}, {
3964 1, 0x0}, {
3965 0, 0x0}
3966 };
3967
3968 /* SDIO Drive Strength to sel value table for PMU Rev 2, 3 */
3969 static const struct sdiod_drive_str sdiod_drive_strength_tab2[] = {
3970 {
3971 12, 0x7}, {
3972 10, 0x6}, {
3973 8, 0x5}, {
3974 6, 0x4}, {
3975 4, 0x2}, {
3976 2, 0x1}, {
3977 0, 0x0}
3978 };
3979
3980 /* SDIO Drive Strength to sel value table for PMU Rev 8 (1.8V) */
3981 static const struct sdiod_drive_str sdiod_drive_strength_tab3[] = {
3982 {
3983 32, 0x7}, {
3984 26, 0x6}, {
3985 22, 0x5}, {
3986 16, 0x4}, {
3987 12, 0x3}, {
3988 8, 0x2}, {
3989 4, 0x1}, {
3990 0, 0x0}
3991 };
3992
3993 #define SDIOD_DRVSTR_KEY(chip, pmu) (((chip) << 16) | (pmu))
3994
3995 static char *brcmf_chipname(uint chipid, char *buf, uint len)
3996 {
3997 const char *fmt;
3998
3999 fmt = ((chipid > 0xa000) || (chipid < 0x4000)) ? "%d" : "%x";
4000 snprintf(buf, len, fmt, chipid);
4001 return buf;
4002 }
4003
4004 static void brcmf_sdbrcm_sdiod_drive_strength_init(struct brcmf_bus *bus,
4005 u32 drivestrength) {
4006 struct sdiod_drive_str *str_tab = NULL;
4007 u32 str_mask = 0;
4008 u32 str_shift = 0;
4009 char chn[8];
4010
4011 if (!(bus->ci->cccaps & CC_CAP_PMU))
4012 return;
4013
4014 switch (SDIOD_DRVSTR_KEY(bus->ci->chip, bus->ci->pmurev)) {
4015 case SDIOD_DRVSTR_KEY(BCM4325_CHIP_ID, 1):
4016 str_tab = (struct sdiod_drive_str *)&sdiod_drive_strength_tab1;
4017 str_mask = 0x30000000;
4018 str_shift = 28;
4019 break;
4020 case SDIOD_DRVSTR_KEY(BCM4325_CHIP_ID, 2):
4021 case SDIOD_DRVSTR_KEY(BCM4325_CHIP_ID, 3):
4022 str_tab = (struct sdiod_drive_str *)&sdiod_drive_strength_tab2;
4023 str_mask = 0x00003800;
4024 str_shift = 11;
4025 break;
4026 case SDIOD_DRVSTR_KEY(BCM4336_CHIP_ID, 8):
4027 str_tab = (struct sdiod_drive_str *)&sdiod_drive_strength_tab3;
4028 str_mask = 0x00003800;
4029 str_shift = 11;
4030 break;
4031 default:
4032 brcmf_dbg(ERROR, "No SDIO Drive strength init done for chip %s rev %d pmurev %d\n",
4033 brcmf_chipname(bus->ci->chip, chn, 8),
4034 bus->ci->chiprev, bus->ci->pmurev);
4035 break;
4036 }
4037
4038 if (str_tab != NULL) {
4039 u32 drivestrength_sel = 0;
4040 u32 cc_data_temp;
4041 int i;
4042
4043 for (i = 0; str_tab[i].strength != 0; i++) {
4044 if (drivestrength >= str_tab[i].strength) {
4045 drivestrength_sel = str_tab[i].sel;
4046 break;
4047 }
4048 }
4049
4050 brcmf_sdcard_reg_write(bus->sdiodev,
4051 CORE_CC_REG(bus->ci->cccorebase, chipcontrol_addr),
4052 4, 1);
4053 cc_data_temp = brcmf_sdcard_reg_read(bus->sdiodev,
4054 CORE_CC_REG(bus->ci->cccorebase, chipcontrol_addr), 4);
4055 cc_data_temp &= ~str_mask;
4056 drivestrength_sel <<= str_shift;
4057 cc_data_temp |= drivestrength_sel;
4058 brcmf_sdcard_reg_write(bus->sdiodev,
4059 CORE_CC_REG(bus->ci->cccorebase, chipcontrol_addr),
4060 4, cc_data_temp);
4061
4062 brcmf_dbg(INFO, "SDIO: %dmA drive strength selected, set to 0x%08x\n",
4063 drivestrength, cc_data_temp);
4064 }
4065 }
4066
4067 static int
4068 brcmf_sdbrcm_chip_recognition(struct brcmf_sdio_dev *sdiodev,
4069 struct chip_info *ci, u32 regs)
4070 {
4071 u32 regdata;
4072
4073 /*
4074 * Get CC core rev
4075 * Chipid is assume to be at offset 0 from regs arg
4076 * For different chiptypes or old sdio hosts w/o chipcommon,
4077 * other ways of recognition should be added here.
4078 */
4079 ci->cccorebase = regs;
4080 regdata = brcmf_sdcard_reg_read(sdiodev,
4081 CORE_CC_REG(ci->cccorebase, chipid), 4);
4082 ci->chip = regdata & CID_ID_MASK;
4083 ci->chiprev = (regdata & CID_REV_MASK) >> CID_REV_SHIFT;
4084
4085 brcmf_dbg(INFO, "chipid=0x%x chiprev=%d\n", ci->chip, ci->chiprev);
4086
4087 /* Address of cores for new chips should be added here */
4088 switch (ci->chip) {
4089 case BCM4329_CHIP_ID:
4090 ci->buscorebase = BCM4329_CORE_BUS_BASE;
4091 ci->ramcorebase = BCM4329_CORE_SOCRAM_BASE;
4092 ci->armcorebase = BCM4329_CORE_ARM_BASE;
4093 ci->ramsize = BCM4329_RAMSIZE;
4094 break;
4095 default:
4096 brcmf_dbg(ERROR, "chipid 0x%x is not supported\n", ci->chip);
4097 return -ENODEV;
4098 }
4099
4100 regdata = brcmf_sdcard_reg_read(sdiodev,
4101 CORE_SB(ci->cccorebase, sbidhigh), 4);
4102 ci->ccrev = SBCOREREV(regdata);
4103
4104 regdata = brcmf_sdcard_reg_read(sdiodev,
4105 CORE_CC_REG(ci->cccorebase, pmucapabilities), 4);
4106 ci->pmurev = regdata & PCAP_REV_MASK;
4107
4108 regdata = brcmf_sdcard_reg_read(sdiodev,
4109 CORE_SB(ci->buscorebase, sbidhigh), 4);
4110 ci->buscorerev = SBCOREREV(regdata);
4111 ci->buscoretype = (regdata & SBIDH_CC_MASK) >> SBIDH_CC_SHIFT;
4112
4113 brcmf_dbg(INFO, "ccrev=%d, pmurev=%d, buscore rev/type=%d/0x%x\n",
4114 ci->ccrev, ci->pmurev, ci->buscorerev, ci->buscoretype);
4115
4116 /* get chipcommon capabilites */
4117 ci->cccaps = brcmf_sdcard_reg_read(sdiodev,
4118 CORE_CC_REG(ci->cccorebase, capabilities), 4);
4119
4120 return 0;
4121 }
4122
4123 static int
4124 brcmf_sdbrcm_chip_attach(struct brcmf_bus *bus, u32 regs)
4125 {
4126 struct chip_info *ci;
4127 int err;
4128 u8 clkval, clkset;
4129
4130 brcmf_dbg(TRACE, "Enter\n");
4131
4132 /* alloc chip_info_t */
4133 ci = kzalloc(sizeof(struct chip_info), GFP_ATOMIC);
4134 if (NULL == ci)
4135 return -ENOMEM;
4136
4137 /* bus/core/clk setup for register access */
4138 /* Try forcing SDIO core to do ALPAvail request only */
4139 clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_ALP_AVAIL_REQ;
4140 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
4141 SBSDIO_FUNC1_CHIPCLKCSR, clkset, &err);
4142 if (err) {
4143 brcmf_dbg(ERROR, "error writing for HT off\n");
4144 goto fail;
4145 }
4146
4147 /* If register supported, wait for ALPAvail and then force ALP */
4148 /* This may take up to 15 milliseconds */
4149 clkval = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
4150 SBSDIO_FUNC1_CHIPCLKCSR, NULL);
4151 if ((clkval & ~SBSDIO_AVBITS) == clkset) {
4152 SPINWAIT(((clkval =
4153 brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
4154 SBSDIO_FUNC1_CHIPCLKCSR,
4155 NULL)),
4156 !SBSDIO_ALPAV(clkval)),
4157 PMU_MAX_TRANSITION_DLY);
4158 if (!SBSDIO_ALPAV(clkval)) {
4159 brcmf_dbg(ERROR, "timeout on ALPAV wait, clkval 0x%02x\n",
4160 clkval);
4161 err = -EBUSY;
4162 goto fail;
4163 }
4164 clkset = SBSDIO_FORCE_HW_CLKREQ_OFF |
4165 SBSDIO_FORCE_ALP;
4166 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
4167 SBSDIO_FUNC1_CHIPCLKCSR,
4168 clkset, &err);
4169 udelay(65);
4170 } else {
4171 brcmf_dbg(ERROR, "ChipClkCSR access: wrote 0x%02x read 0x%02x\n",
4172 clkset, clkval);
4173 err = -EACCES;
4174 goto fail;
4175 }
4176
4177 /* Also, disable the extra SDIO pull-ups */
4178 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
4179 SBSDIO_FUNC1_SDIOPULLUP, 0, NULL);
4180
4181 err = brcmf_sdbrcm_chip_recognition(bus->sdiodev, ci, regs);
4182 if (err)
4183 goto fail;
4184
4185 /*
4186 * Make sure any on-chip ARM is off (in case strapping is wrong),
4187 * or downloaded code was already running.
4188 */
4189 brcmf_sdbrcm_chip_disablecore(bus->sdiodev, ci->armcorebase);
4190
4191 brcmf_sdcard_reg_write(bus->sdiodev,
4192 CORE_CC_REG(ci->cccorebase, gpiopullup), 4, 0);
4193 brcmf_sdcard_reg_write(bus->sdiodev,
4194 CORE_CC_REG(ci->cccorebase, gpiopulldown), 4, 0);
4195
4196 /* Disable F2 to clear any intermediate frame state on the dongle */
4197 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_0, SDIO_CCCR_IOEx,
4198 SDIO_FUNC_ENABLE_1, NULL);
4199
4200 /* WAR: cmd52 backplane read so core HW will drop ALPReq */
4201 clkval = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
4202 0, NULL);
4203
4204 /* Done with backplane-dependent accesses, can drop clock... */
4205 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
4206 SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL);
4207
4208 bus->ci = ci;
4209 return 0;
4210 fail:
4211 bus->ci = NULL;
4212 kfree(ci);
4213 return err;
4214 }
4215
4216 static bool
4217 brcmf_sdbrcm_probe_attach(struct brcmf_bus *bus, u32 regsva)
4218 {
4219 u8 clkctl = 0;
4220 int err = 0;
4221 int reg_addr;
4222 u32 reg_val;
4223
4224 bus->alp_only = true;
4225
4226 /* Return the window to backplane enumeration space for core access */
4227 if (brcmf_sdcard_set_sbaddr_window(bus->sdiodev, SI_ENUM_BASE))
4228 brcmf_dbg(ERROR, "FAILED to return to SI_ENUM_BASE\n");
4229
4230 #ifdef BCMDBG
4231 printk(KERN_DEBUG "F1 signature read @0x18000000=0x%4x\n",
4232 brcmf_sdcard_reg_read(bus->sdiodev, SI_ENUM_BASE, 4));
4233
4234 #endif /* BCMDBG */
4235
4236 /*
4237 * Force PLL off until brcmf_sdbrcm_chip_attach()
4238 * programs PLL control regs
4239 */
4240
4241 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
4242 SBSDIO_FUNC1_CHIPCLKCSR,
4243 BRCMF_INIT_CLKCTL1, &err);
4244 if (!err)
4245 clkctl =
4246 brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
4247 SBSDIO_FUNC1_CHIPCLKCSR, &err);
4248
4249 if (err || ((clkctl & ~SBSDIO_AVBITS) != BRCMF_INIT_CLKCTL1)) {
4250 brcmf_dbg(ERROR, "ChipClkCSR access: err %d wrote 0x%02x read 0x%02x\n",
4251 err, BRCMF_INIT_CLKCTL1, clkctl);
4252 goto fail;
4253 }
4254
4255 if (brcmf_sdbrcm_chip_attach(bus, regsva)) {
4256 brcmf_dbg(ERROR, "brcmf_sdbrcm_chip_attach failed!\n");
4257 goto fail;
4258 }
4259
4260 if (!brcmf_sdbrcm_chipmatch((u16) bus->ci->chip)) {
4261 brcmf_dbg(ERROR, "unsupported chip: 0x%04x\n", bus->ci->chip);
4262 goto fail;
4263 }
4264
4265 brcmf_sdbrcm_sdiod_drive_strength_init(bus, SDIO_DRIVE_STRENGTH);
4266
4267 /* Get info on the ARM and SOCRAM cores... */
4268 brcmf_sdcard_reg_read(bus->sdiodev,
4269 CORE_SB(bus->ci->armcorebase, sbidhigh), 4);
4270 bus->ramsize = bus->ci->ramsize;
4271 if (!(bus->ramsize)) {
4272 brcmf_dbg(ERROR, "failed to find SOCRAM memory!\n");
4273 goto fail;
4274 }
4275
4276 /* Set core control so an SDIO reset does a backplane reset */
4277 reg_addr = bus->ci->buscorebase +
4278 offsetof(struct sdpcmd_regs, corecontrol);
4279 reg_val = brcmf_sdcard_reg_read(bus->sdiodev, reg_addr, sizeof(u32));
4280 brcmf_sdcard_reg_write(bus->sdiodev, reg_addr, sizeof(u32),
4281 reg_val | CC_BPRESEN);
4282
4283 brcmu_pktq_init(&bus->txq, (PRIOMASK + 1), TXQLEN);
4284
4285 /* Locate an appropriately-aligned portion of hdrbuf */
4286 bus->rxhdr = (u8 *) roundup((unsigned long)&bus->hdrbuf[0],
4287 BRCMF_SDALIGN);
4288
4289 /* Set the poll and/or interrupt flags */
4290 bus->intr = true;
4291 bus->poll = false;
4292 if (bus->poll)
4293 bus->pollrate = 1;
4294
4295 return true;
4296
4297 fail:
4298 return false;
4299 }
4300
4301 static bool brcmf_sdbrcm_probe_init(struct brcmf_bus *bus)
4302 {
4303 brcmf_dbg(TRACE, "Enter\n");
4304
4305 /* Disable F2 to clear any intermediate frame state on the dongle */
4306 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_0, SDIO_CCCR_IOEx,
4307 SDIO_FUNC_ENABLE_1, NULL);
4308
4309 bus->drvr->busstate = BRCMF_BUS_DOWN;
4310 bus->sleeping = false;
4311 bus->rxflow = false;
4312
4313 /* Done with backplane-dependent accesses, can drop clock... */
4314 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
4315 SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL);
4316
4317 /* ...and initialize clock/power states */
4318 bus->clkstate = CLK_SDONLY;
4319 bus->idletime = BRCMF_IDLE_INTERVAL;
4320 bus->idleclock = BRCMF_IDLE_ACTIVE;
4321
4322 /* Query the F2 block size, set roundup accordingly */
4323 bus->blocksize = bus->sdiodev->func[2]->cur_blksize;
4324 bus->roundup = min(max_roundup, bus->blocksize);
4325
4326 /* bus module does not support packet chaining */
4327 bus->use_rxchain = false;
4328 bus->sd_rxchain = false;
4329
4330 return true;
4331 }
4332
4333 static int
4334 brcmf_sdbrcm_watchdog_thread(void *data)
4335 {
4336 struct brcmf_bus *bus = (struct brcmf_bus *)data;
4337
4338 allow_signal(SIGTERM);
4339 /* Run until signal received */
4340 while (1) {
4341 if (kthread_should_stop())
4342 break;
4343 if (!wait_for_completion_interruptible(&bus->watchdog_wait)) {
4344 brcmf_sdbrcm_bus_watchdog(bus->drvr);
4345 /* Count the tick for reference */
4346 bus->drvr->tickcnt++;
4347 } else
4348 break;
4349 }
4350 return 0;
4351 }
4352
4353 static void
4354 brcmf_sdbrcm_watchdog(unsigned long data)
4355 {
4356 struct brcmf_bus *bus = (struct brcmf_bus *)data;
4357
4358 if (bus->watchdog_tsk) {
4359 complete(&bus->watchdog_wait);
4360 /* Reschedule the watchdog */
4361 if (bus->wd_timer_valid)
4362 mod_timer(&bus->timer,
4363 jiffies + BRCMF_WD_POLL_MS * HZ / 1000);
4364 }
4365 }
4366
4367 static void
4368 brcmf_sdbrcm_chip_detach(struct brcmf_bus *bus)
4369 {
4370 brcmf_dbg(TRACE, "Enter\n");
4371
4372 kfree(bus->ci);
4373 bus->ci = NULL;
4374 }
4375
4376 static void brcmf_sdbrcm_release_dongle(struct brcmf_bus *bus)
4377 {
4378 brcmf_dbg(TRACE, "Enter\n");
4379
4380 if (bus->ci) {
4381 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
4382 brcmf_sdbrcm_clkctl(bus, CLK_NONE, false);
4383 brcmf_sdbrcm_chip_detach(bus);
4384 if (bus->vars && bus->varsz)
4385 kfree(bus->vars);
4386 bus->vars = NULL;
4387 }
4388
4389 brcmf_dbg(TRACE, "Disconnected\n");
4390 }
4391
4392 /* Detach and free everything */
4393 static void brcmf_sdbrcm_release(struct brcmf_bus *bus)
4394 {
4395 brcmf_dbg(TRACE, "Enter\n");
4396
4397 if (bus) {
4398 /* De-register interrupt handler */
4399 brcmf_sdcard_intr_dereg(bus->sdiodev);
4400
4401 if (bus->drvr) {
4402 brcmf_detach(bus->drvr);
4403 brcmf_sdbrcm_release_dongle(bus);
4404 bus->drvr = NULL;
4405 }
4406
4407 brcmf_sdbrcm_release_malloc(bus);
4408
4409 kfree(bus);
4410 }
4411
4412 brcmf_dbg(TRACE, "Disconnected\n");
4413 }
4414
4415 void *brcmf_sdbrcm_probe(u16 bus_no, u16 slot, u16 func, uint bustype,
4416 u32 regsva, struct brcmf_sdio_dev *sdiodev)
4417 {
4418 int ret;
4419 struct brcmf_bus *bus;
4420
4421 /* Init global variables at run-time, not as part of the declaration.
4422 * This is required to support init/de-init of the driver.
4423 * Initialization
4424 * of globals as part of the declaration results in non-deterministic
4425 * behavior since the value of the globals may be different on the
4426 * first time that the driver is initialized vs subsequent
4427 * initializations.
4428 */
4429 brcmf_c_init();
4430
4431 brcmf_dbg(TRACE, "Enter\n");
4432
4433 /* We make an assumption about address window mappings:
4434 * regsva == SI_ENUM_BASE*/
4435
4436 /* Allocate private bus interface state */
4437 bus = kzalloc(sizeof(struct brcmf_bus), GFP_ATOMIC);
4438 if (!bus)
4439 goto fail;
4440
4441 bus->sdiodev = sdiodev;
4442 sdiodev->bus = bus;
4443 bus->txbound = BRCMF_TXBOUND;
4444 bus->rxbound = BRCMF_RXBOUND;
4445 bus->txminmax = BRCMF_TXMINMAX;
4446 bus->tx_seq = SDPCM_SEQUENCE_WRAP - 1;
4447 bus->usebufpool = false; /* Use bufpool if allocated,
4448 else use locally malloced rxbuf */
4449
4450 /* attempt to attach to the dongle */
4451 if (!(brcmf_sdbrcm_probe_attach(bus, regsva))) {
4452 brcmf_dbg(ERROR, "brcmf_sdbrcm_probe_attach failed\n");
4453 goto fail;
4454 }
4455
4456 spin_lock_init(&bus->txqlock);
4457 init_waitqueue_head(&bus->ctrl_wait);
4458 init_waitqueue_head(&bus->dcmd_resp_wait);
4459
4460 /* Set up the watchdog timer */
4461 init_timer(&bus->timer);
4462 bus->timer.data = (unsigned long)bus;
4463 bus->timer.function = brcmf_sdbrcm_watchdog;
4464
4465 /* Initialize thread based operation and lock */
4466 sema_init(&bus->sdsem, 1);
4467
4468 /* Initialize watchdog thread */
4469 init_completion(&bus->watchdog_wait);
4470 bus->watchdog_tsk = kthread_run(brcmf_sdbrcm_watchdog_thread,
4471 bus, "brcmf_watchdog");
4472 if (IS_ERR(bus->watchdog_tsk)) {
4473 printk(KERN_WARNING
4474 "brcmf_watchdog thread failed to start\n");
4475 bus->watchdog_tsk = NULL;
4476 }
4477 /* Initialize DPC thread */
4478 init_completion(&bus->dpc_wait);
4479 bus->dpc_tsk = kthread_run(brcmf_sdbrcm_dpc_thread,
4480 bus, "brcmf_dpc");
4481 if (IS_ERR(bus->dpc_tsk)) {
4482 printk(KERN_WARNING
4483 "brcmf_dpc thread failed to start\n");
4484 bus->dpc_tsk = NULL;
4485 }
4486
4487 /* Attach to the brcmf/OS/network interface */
4488 bus->drvr = brcmf_attach(bus, SDPCM_RESERVE);
4489 if (!bus->drvr) {
4490 brcmf_dbg(ERROR, "brcmf_attach failed\n");
4491 goto fail;
4492 }
4493
4494 /* Allocate buffers */
4495 if (!(brcmf_sdbrcm_probe_malloc(bus))) {
4496 brcmf_dbg(ERROR, "brcmf_sdbrcm_probe_malloc failed\n");
4497 goto fail;
4498 }
4499
4500 if (!(brcmf_sdbrcm_probe_init(bus))) {
4501 brcmf_dbg(ERROR, "brcmf_sdbrcm_probe_init failed\n");
4502 goto fail;
4503 }
4504
4505 /* Register interrupt callback, but mask it (not operational yet). */
4506 brcmf_dbg(INTR, "disable SDIO interrupts (not interested yet)\n");
4507 ret = brcmf_sdcard_intr_reg(bus->sdiodev);
4508 if (ret != 0) {
4509 brcmf_dbg(ERROR, "FAILED: sdcard_intr_reg returned %d\n", ret);
4510 goto fail;
4511 }
4512 brcmf_dbg(INTR, "registered SDIO interrupt function ok\n");
4513
4514 brcmf_dbg(INFO, "completed!!\n");
4515
4516 /* if firmware path present try to download and bring up bus */
4517 ret = brcmf_bus_start(bus->drvr);
4518 if (ret != 0) {
4519 if (ret == -ENOLINK) {
4520 brcmf_dbg(ERROR, "dongle is not responding\n");
4521 goto fail;
4522 }
4523 }
4524 /* Ok, have the per-port tell the stack we're open for business */
4525 if (brcmf_net_attach(bus->drvr, 0) != 0) {
4526 brcmf_dbg(ERROR, "Net attach failed!!\n");
4527 goto fail;
4528 }
4529
4530 return bus;
4531
4532 fail:
4533 brcmf_sdbrcm_release(bus);
4534 return NULL;
4535 }
4536
4537 void brcmf_sdbrcm_disconnect(void *ptr)
4538 {
4539 struct brcmf_bus *bus = (struct brcmf_bus *)ptr;
4540
4541 brcmf_dbg(TRACE, "Enter\n");
4542
4543 if (bus)
4544 brcmf_sdbrcm_release(bus);
4545
4546 brcmf_dbg(TRACE, "Disconnected\n");
4547 }
4548
4549 struct device *brcmf_bus_get_device(struct brcmf_bus *bus)
4550 {
4551 return &bus->sdiodev->func[2]->dev;
4552 }
4553
4554 void
4555 brcmf_sdbrcm_wd_timer(struct brcmf_bus *bus, uint wdtick)
4556 {
4557 /* don't start the wd until fw is loaded */
4558 if (bus->drvr->busstate == BRCMF_BUS_DOWN)
4559 return;
4560
4561 /* Totally stop the timer */
4562 if (!wdtick && bus->wd_timer_valid == true) {
4563 del_timer_sync(&bus->timer);
4564 bus->wd_timer_valid = false;
4565 bus->save_ms = wdtick;
4566 return;
4567 }
4568
4569 if (wdtick) {
4570 if (bus->save_ms != BRCMF_WD_POLL_MS) {
4571 if (bus->wd_timer_valid == true)
4572 /* Stop timer and restart at new value */
4573 del_timer_sync(&bus->timer);
4574
4575 /* Create timer again when watchdog period is
4576 dynamically changed or in the first instance
4577 */
4578 bus->timer.expires =
4579 jiffies + BRCMF_WD_POLL_MS * HZ / 1000;
4580 add_timer(&bus->timer);
4581
4582 } else {
4583 /* Re arm the timer, at last watchdog period */
4584 mod_timer(&bus->timer,
4585 jiffies + BRCMF_WD_POLL_MS * HZ / 1000);
4586 }
4587
4588 bus->wd_timer_valid = true;
4589 bus->save_ms = wdtick;
4590 }
4591 }
Linux kernel - Deliverables
This page took 0.128814 seconds and 6 git commands to generate.